[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / dw_dmac.h

/*
 * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
 * AVR32 systems.)
 *
 * Copyright (C) 2007 Atmel Corporation
 * Copyright (C) 2010-2011 ST Microelectronics
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef DW_DMAC_H
#define DW_DMAC_H

#include <linux/dmaengine.h>

/**
 * struct dw_dma_slave - Controller-specific information about a slave
 *
 * @dma_dev: required DMA master device. Depricated.
 * @bus_id: name of this device channel, not just a device name since
 *          devices may have more than one channel e.g. "foo_tx"
 * @cfg_hi: Platform-specific initializer for the CFG_HI register
 * @cfg_lo: Platform-specific initializer for the CFG_LO register
 * @src_master: src master for transfers on allocated channel.
 * @dst_master: dest master for transfers on allocated channel.
 */
struct dw_dma_slave {
	struct device		*dma_dev;
	u32			cfg_hi;
	u32			cfg_lo;
	u8			src_master;
	u8			dst_master;
};

/**
 * struct dw_dma_platform_data - Controller configuration parameters
 * @nr_channels: Number of channels supported by hardware (max 8)
 * @is_private: The device channels should be marked as private and not for
 *	by the general purpose DMA channel allocator.
 * @chan_allocation_order: Allocate channels starting from 0 or 7
 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
 * @block_size: Maximum block size supported by the controller
 * @nr_masters: Number of AHB masters supported by the controller
 * @data_width: Maximum data width supported by hardware per AHB master
 *		(0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
 * @sd: slave specific data. Used for configuring channels
 * @sd_count: count of slave data structures passed.
 */
struct dw_dma_platform_data {
	unsigned int	nr_channels;
	bool		is_private;
#define CHAN_ALLOCATION_ASCENDING	0	/* zero to seven */
#define CHAN_ALLOCATION_DESCENDING	1	/* seven to zero */
	unsigned char	chan_allocation_order;
#define CHAN_PRIORITY_ASCENDING		0	/* chan0 highest */
#define CHAN_PRIORITY_DESCENDING	1	/* chan7 highest */
	unsigned char	chan_priority;
	unsigned short	block_size;
	unsigned char	nr_masters;
	unsigned char	data_width[4];
};

/* bursts size */
enum dw_dma_msize {
	DW_DMA_MSIZE_1,
	DW_DMA_MSIZE_4,
	DW_DMA_MSIZE_8,
	DW_DMA_MSIZE_16,
	DW_DMA_MSIZE_32,
	DW_DMA_MSIZE_64,
	DW_DMA_MSIZE_128,
	DW_DMA_MSIZE_256,
};

/* Platform-configurable bits in CFG_HI */
#define DWC_CFGH_FCMODE		(1 << 0)
#define DWC_CFGH_FIFO_MODE	(1 << 1)
#define DWC_CFGH_PROTCTL(x)	((x) << 2)
#define DWC_CFGH_SRC_PER(x)	((x) << 7)
#define DWC_CFGH_DST_PER(x)	((x) << 11)

/* Platform-configurable bits in CFG_LO */
#define DWC_CFGL_LOCK_CH_XFER	(0 << 12)	/* scope of LOCK_CH */
#define DWC_CFGL_LOCK_CH_BLOCK	(1 << 12)
#define DWC_CFGL_LOCK_CH_XACT	(2 << 12)
#define DWC_CFGL_LOCK_BUS_XFER	(0 << 14)	/* scope of LOCK_BUS */
#define DWC_CFGL_LOCK_BUS_BLOCK	(1 << 14)
#define DWC_CFGL_LOCK_BUS_XACT	(2 << 14)
#define DWC_CFGL_LOCK_CH	(1 << 15)	/* channel lockout */
#define DWC_CFGL_LOCK_BUS	(1 << 16)	/* busmaster lockout */
#define DWC_CFGL_HS_DST_POL	(1 << 18)	/* dst handshake active low */
#define DWC_CFGL_HS_SRC_POL	(1 << 19)	/* src handshake active low */

/* DMA API extensions */
struct dw_cyclic_desc {
	struct dw_desc	**desc;
	unsigned long	periods;
	void		(*period_callback)(void *param);
	void		*period_callback_param;
};

struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
		dma_addr_t buf_addr, size_t buf_len, size_t period_len,
		enum dma_transfer_direction direction);
void dw_dma_cyclic_free(struct dma_chan *chan);
int dw_dma_cyclic_start(struct dma_chan *chan);
void dw_dma_cyclic_stop(struct dma_chan *chan);

dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);

dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);

#endif /* DW_DMAC_H */
Commit	Line	Data
3bfb1d20 HS	1	/*
	2	* Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
	3	* AVR32 systems.)
	4	*
	5	* Copyright (C) 2007 Atmel Corporation
aecb7b64	6	* Copyright (C) 2010-2011 ST Microelectronics
3bfb1d20 HS	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12	#ifndef DW_DMAC_H
	13	#define DW_DMAC_H
	14
	15	#include <linux/dmaengine.h>
	16
a9ddb575 VK	17	/**
	18	* struct dw_dma_slave - Controller-specific information about a slave
	19	*
	20	* @dma_dev: required DMA master device. Depricated.
	21	* @bus_id: name of this device channel, not just a device name since
	22	* devices may have more than one channel e.g. "foo_tx"
	23	* @cfg_hi: Platform-specific initializer for the CFG_HI register
	24	* @cfg_lo: Platform-specific initializer for the CFG_LO register
	25	* @src_master: src master for transfers on allocated channel.
	26	* @dst_master: dest master for transfers on allocated channel.
	27	*/
	28	struct dw_dma_slave {
	29	struct device *dma_dev;
a9ddb575 VK	30	u32 cfg_hi;
	31	u32 cfg_lo;
	32	u8 src_master;
	33	u8 dst_master;
	34	};
	35
3bfb1d20 HS	36	/**
	37	* struct dw_dma_platform_data - Controller configuration parameters
	38	* @nr_channels: Number of channels supported by hardware (max 8)
95ea759e JI	39	* @is_private: The device channels should be marked as private and not for
95ea759e JI	40	* by the general purpose DMA channel allocator.
177d2bf5 VK	41	* @chan_allocation_order: Allocate channels starting from 0 or 7
177d2bf5 VK	42	* @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
4a63a8b3	43	* @block_size: Maximum block size supported by the controller
a0982004 AS	44	* @nr_masters: Number of AHB masters supported by the controller
	45	* @data_width: Maximum data width supported by hardware per AHB master
	46	* (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
a9ddb575 VK	47	* @sd: slave specific data. Used for configuring channels
a9ddb575 VK	48	* @sd_count: count of slave data structures passed.
3bfb1d20 HS	49	*/
	50	struct dw_dma_platform_data {
	51	unsigned int nr_channels;
95ea759e	52	bool is_private;
b0c3130d VK	53	#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
	54	#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
	55	unsigned char chan_allocation_order;
93317e8e VK	56	#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
	57	#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
	58	unsigned char chan_priority;
4a63a8b3	59	unsigned short block_size;
a0982004 AS	60	unsigned char nr_masters;
a0982004 AS	61	unsigned char data_width[4];
3bfb1d20 HS	62	};
3bfb1d20 HS	63
ee66509d VK	64	/* bursts size */
	65	enum dw_dma_msize {
	66	DW_DMA_MSIZE_1,
	67	DW_DMA_MSIZE_4,
	68	DW_DMA_MSIZE_8,
	69	DW_DMA_MSIZE_16,
	70	DW_DMA_MSIZE_32,
	71	DW_DMA_MSIZE_64,
	72	DW_DMA_MSIZE_128,
	73	DW_DMA_MSIZE_256,
	74	};
	75
3bfb1d20 HS	76	/* Platform-configurable bits in CFG_HI */
	77	#define DWC_CFGH_FCMODE (1 << 0)
	78	#define DWC_CFGH_FIFO_MODE (1 << 1)
	79	#define DWC_CFGH_PROTCTL(x) ((x) << 2)
	80	#define DWC_CFGH_SRC_PER(x) ((x) << 7)
	81	#define DWC_CFGH_DST_PER(x) ((x) << 11)
	82
	83	/* Platform-configurable bits in CFG_LO */
3bfb1d20 HS	84	#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
	85	#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
	86	#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
	87	#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
	88	#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
	89	#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
	90	#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
	91	#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
	92	#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
	93	#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
	94
d9de4519 HCE	95	/* DMA API extensions */
	96	struct dw_cyclic_desc {
	97	struct dw_desc **desc;
	98	unsigned long periods;
	99	void (period_callback)(void param);
	100	void *period_callback_param;
	101	};
	102
	103	struct dw_cyclic_desc dw_dma_cyclic_prep(struct dma_chan chan,
	104	dma_addr_t buf_addr, size_t buf_len, size_t period_len,
db8196df	105	enum dma_transfer_direction direction);
d9de4519 HCE	106	void dw_dma_cyclic_free(struct dma_chan *chan);
	107	int dw_dma_cyclic_start(struct dma_chan *chan);
	108	void dw_dma_cyclic_stop(struct dma_chan *chan);
	109
	110	dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
	111
	112	dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
	113
3bfb1d20	114	#endif /* DW_DMAC_H */