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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi-atmel.c
1 /*
2 * Driver for Atmel AT32 and AT91 SPI Controllers
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/dmaengine.h>
19 #include <linux/err.h>
20 #include <linux/interrupt.h>
21 #include <linux/spi/spi.h>
22 #include <linux/slab.h>
23 #include <linux/platform_data/atmel.h>
24 #include <linux/platform_data/dma-atmel.h>
25 #include <linux/of.h>
26
27 #include <linux/io.h>
28 #include <linux/gpio.h>
29
30 /* SPI register offsets */
31 #define SPI_CR 0x0000
32 #define SPI_MR 0x0004
33 #define SPI_RDR 0x0008
34 #define SPI_TDR 0x000c
35 #define SPI_SR 0x0010
36 #define SPI_IER 0x0014
37 #define SPI_IDR 0x0018
38 #define SPI_IMR 0x001c
39 #define SPI_CSR0 0x0030
40 #define SPI_CSR1 0x0034
41 #define SPI_CSR2 0x0038
42 #define SPI_CSR3 0x003c
43 #define SPI_VERSION 0x00fc
44 #define SPI_RPR 0x0100
45 #define SPI_RCR 0x0104
46 #define SPI_TPR 0x0108
47 #define SPI_TCR 0x010c
48 #define SPI_RNPR 0x0110
49 #define SPI_RNCR 0x0114
50 #define SPI_TNPR 0x0118
51 #define SPI_TNCR 0x011c
52 #define SPI_PTCR 0x0120
53 #define SPI_PTSR 0x0124
54
55 /* Bitfields in CR */
56 #define SPI_SPIEN_OFFSET 0
57 #define SPI_SPIEN_SIZE 1
58 #define SPI_SPIDIS_OFFSET 1
59 #define SPI_SPIDIS_SIZE 1
60 #define SPI_SWRST_OFFSET 7
61 #define SPI_SWRST_SIZE 1
62 #define SPI_LASTXFER_OFFSET 24
63 #define SPI_LASTXFER_SIZE 1
64
65 /* Bitfields in MR */
66 #define SPI_MSTR_OFFSET 0
67 #define SPI_MSTR_SIZE 1
68 #define SPI_PS_OFFSET 1
69 #define SPI_PS_SIZE 1
70 #define SPI_PCSDEC_OFFSET 2
71 #define SPI_PCSDEC_SIZE 1
72 #define SPI_FDIV_OFFSET 3
73 #define SPI_FDIV_SIZE 1
74 #define SPI_MODFDIS_OFFSET 4
75 #define SPI_MODFDIS_SIZE 1
76 #define SPI_WDRBT_OFFSET 5
77 #define SPI_WDRBT_SIZE 1
78 #define SPI_LLB_OFFSET 7
79 #define SPI_LLB_SIZE 1
80 #define SPI_PCS_OFFSET 16
81 #define SPI_PCS_SIZE 4
82 #define SPI_DLYBCS_OFFSET 24
83 #define SPI_DLYBCS_SIZE 8
84
85 /* Bitfields in RDR */
86 #define SPI_RD_OFFSET 0
87 #define SPI_RD_SIZE 16
88
89 /* Bitfields in TDR */
90 #define SPI_TD_OFFSET 0
91 #define SPI_TD_SIZE 16
92
93 /* Bitfields in SR */
94 #define SPI_RDRF_OFFSET 0
95 #define SPI_RDRF_SIZE 1
96 #define SPI_TDRE_OFFSET 1
97 #define SPI_TDRE_SIZE 1
98 #define SPI_MODF_OFFSET 2
99 #define SPI_MODF_SIZE 1
100 #define SPI_OVRES_OFFSET 3
101 #define SPI_OVRES_SIZE 1
102 #define SPI_ENDRX_OFFSET 4
103 #define SPI_ENDRX_SIZE 1
104 #define SPI_ENDTX_OFFSET 5
105 #define SPI_ENDTX_SIZE 1
106 #define SPI_RXBUFF_OFFSET 6
107 #define SPI_RXBUFF_SIZE 1
108 #define SPI_TXBUFE_OFFSET 7
109 #define SPI_TXBUFE_SIZE 1
110 #define SPI_NSSR_OFFSET 8
111 #define SPI_NSSR_SIZE 1
112 #define SPI_TXEMPTY_OFFSET 9
113 #define SPI_TXEMPTY_SIZE 1
114 #define SPI_SPIENS_OFFSET 16
115 #define SPI_SPIENS_SIZE 1
116
117 /* Bitfields in CSR0 */
118 #define SPI_CPOL_OFFSET 0
119 #define SPI_CPOL_SIZE 1
120 #define SPI_NCPHA_OFFSET 1
121 #define SPI_NCPHA_SIZE 1
122 #define SPI_CSAAT_OFFSET 3
123 #define SPI_CSAAT_SIZE 1
124 #define SPI_BITS_OFFSET 4
125 #define SPI_BITS_SIZE 4
126 #define SPI_SCBR_OFFSET 8
127 #define SPI_SCBR_SIZE 8
128 #define SPI_DLYBS_OFFSET 16
129 #define SPI_DLYBS_SIZE 8
130 #define SPI_DLYBCT_OFFSET 24
131 #define SPI_DLYBCT_SIZE 8
132
133 /* Bitfields in RCR */
134 #define SPI_RXCTR_OFFSET 0
135 #define SPI_RXCTR_SIZE 16
136
137 /* Bitfields in TCR */
138 #define SPI_TXCTR_OFFSET 0
139 #define SPI_TXCTR_SIZE 16
140
141 /* Bitfields in RNCR */
142 #define SPI_RXNCR_OFFSET 0
143 #define SPI_RXNCR_SIZE 16
144
145 /* Bitfields in TNCR */
146 #define SPI_TXNCR_OFFSET 0
147 #define SPI_TXNCR_SIZE 16
148
149 /* Bitfields in PTCR */
150 #define SPI_RXTEN_OFFSET 0
151 #define SPI_RXTEN_SIZE 1
152 #define SPI_RXTDIS_OFFSET 1
153 #define SPI_RXTDIS_SIZE 1
154 #define SPI_TXTEN_OFFSET 8
155 #define SPI_TXTEN_SIZE 1
156 #define SPI_TXTDIS_OFFSET 9
157 #define SPI_TXTDIS_SIZE 1
158
159 /* Constants for BITS */
160 #define SPI_BITS_8_BPT 0
161 #define SPI_BITS_9_BPT 1
162 #define SPI_BITS_10_BPT 2
163 #define SPI_BITS_11_BPT 3
164 #define SPI_BITS_12_BPT 4
165 #define SPI_BITS_13_BPT 5
166 #define SPI_BITS_14_BPT 6
167 #define SPI_BITS_15_BPT 7
168 #define SPI_BITS_16_BPT 8
169
170 /* Bit manipulation macros */
171 #define SPI_BIT(name) \
172 (1 << SPI_##name##_OFFSET)
173 #define SPI_BF(name,value) \
174 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
175 #define SPI_BFEXT(name,value) \
176 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
177 #define SPI_BFINS(name,value,old) \
178 ( ((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
179 | SPI_BF(name,value))
180
181 /* Register access macros */
182 #define spi_readl(port,reg) \
183 __raw_readl((port)->regs + SPI_##reg)
184 #define spi_writel(port,reg,value) \
185 __raw_writel((value), (port)->regs + SPI_##reg)
186
187 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
188 * cache operations; better heuristics consider wordsize and bitrate.
189 */
190 #define DMA_MIN_BYTES 16
191
192 struct atmel_spi_dma {
193 struct dma_chan *chan_rx;
194 struct dma_chan *chan_tx;
195 struct scatterlist sgrx;
196 struct scatterlist sgtx;
197 struct dma_async_tx_descriptor *data_desc_rx;
198 struct dma_async_tx_descriptor *data_desc_tx;
199
200 struct at_dma_slave dma_slave;
201 };
202
203 struct atmel_spi_caps {
204 bool is_spi2;
205 bool has_wdrbt;
206 bool has_dma_support;
207 };
208
209 /*
210 * The core SPI transfer engine just talks to a register bank to set up
211 * DMA transfers; transfer queue progress is driven by IRQs. The clock
212 * framework provides the base clock, subdivided for each spi_device.
213 */
214 struct atmel_spi {
215 spinlock_t lock;
216 unsigned long flags;
217
218 phys_addr_t phybase;
219 void __iomem *regs;
220 int irq;
221 struct clk *clk;
222 struct platform_device *pdev;
223 struct spi_device *stay;
224
225 u8 stopping;
226 struct list_head queue;
227 struct tasklet_struct tasklet;
228 struct spi_transfer *current_transfer;
229 unsigned long current_remaining_bytes;
230 struct spi_transfer *next_transfer;
231 unsigned long next_remaining_bytes;
232 int done_status;
233
234 /* scratch buffer */
235 void *buffer;
236 dma_addr_t buffer_dma;
237
238 struct atmel_spi_caps caps;
239
240 bool use_dma;
241 bool use_pdc;
242 /* dmaengine data */
243 struct atmel_spi_dma dma;
244 };
245
246 /* Controller-specific per-slave state */
247 struct atmel_spi_device {
248 unsigned int npcs_pin;
249 u32 csr;
250 };
251
252 #define BUFFER_SIZE PAGE_SIZE
253 #define INVALID_DMA_ADDRESS 0xffffffff
254
255 /*
256 * Version 2 of the SPI controller has
257 * - CR.LASTXFER
258 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
259 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
260 * - SPI_CSRx.CSAAT
261 * - SPI_CSRx.SBCR allows faster clocking
262 */
263 static bool atmel_spi_is_v2(struct atmel_spi *as)
264 {
265 return as->caps.is_spi2;
266 }
267
268 /*
269 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
270 * they assume that spi slave device state will not change on deselect, so
271 * that automagic deselection is OK. ("NPCSx rises if no data is to be
272 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
273 * controllers have CSAAT and friends.
274 *
275 * Since the CSAAT functionality is a bit weird on newer controllers as
276 * well, we use GPIO to control nCSx pins on all controllers, updating
277 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
278 * support active-high chipselects despite the controller's belief that
279 * only active-low devices/systems exists.
280 *
281 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
282 * right when driven with GPIO. ("Mode Fault does not allow more than one
283 * Master on Chip Select 0.") No workaround exists for that ... so for
284 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
285 * and (c) will trigger that first erratum in some cases.
286 */
287
288 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
289 {
290 struct atmel_spi_device *asd = spi->controller_state;
291 unsigned active = spi->mode & SPI_CS_HIGH;
292 u32 mr;
293
294 if (atmel_spi_is_v2(as)) {
295 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
296 /* For the low SPI version, there is a issue that PDC transfer
297 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
298 */
299 spi_writel(as, CSR0, asd->csr);
300 if (as->caps.has_wdrbt) {
301 spi_writel(as, MR,
302 SPI_BF(PCS, ~(0x01 << spi->chip_select))
303 | SPI_BIT(WDRBT)
304 | SPI_BIT(MODFDIS)
305 | SPI_BIT(MSTR));
306 } else {
307 spi_writel(as, MR,
308 SPI_BF(PCS, ~(0x01 << spi->chip_select))
309 | SPI_BIT(MODFDIS)
310 | SPI_BIT(MSTR));
311 }
312
313 mr = spi_readl(as, MR);
314 gpio_set_value(asd->npcs_pin, active);
315 } else {
316 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
317 int i;
318 u32 csr;
319
320 /* Make sure clock polarity is correct */
321 for (i = 0; i < spi->master->num_chipselect; i++) {
322 csr = spi_readl(as, CSR0 + 4 * i);
323 if ((csr ^ cpol) & SPI_BIT(CPOL))
324 spi_writel(as, CSR0 + 4 * i,
325 csr ^ SPI_BIT(CPOL));
326 }
327
328 mr = spi_readl(as, MR);
329 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
330 if (spi->chip_select != 0)
331 gpio_set_value(asd->npcs_pin, active);
332 spi_writel(as, MR, mr);
333 }
334
335 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
336 asd->npcs_pin, active ? " (high)" : "",
337 mr);
338 }
339
340 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
341 {
342 struct atmel_spi_device *asd = spi->controller_state;
343 unsigned active = spi->mode & SPI_CS_HIGH;
344 u32 mr;
345
346 /* only deactivate *this* device; sometimes transfers to
347 * another device may be active when this routine is called.
348 */
349 mr = spi_readl(as, MR);
350 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
351 mr = SPI_BFINS(PCS, 0xf, mr);
352 spi_writel(as, MR, mr);
353 }
354
355 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
356 asd->npcs_pin, active ? " (low)" : "",
357 mr);
358
359 if (atmel_spi_is_v2(as) || spi->chip_select != 0)
360 gpio_set_value(asd->npcs_pin, !active);
361 }
362
363 static void atmel_spi_lock(struct atmel_spi *as)
364 {
365 spin_lock_irqsave(&as->lock, as->flags);
366 }
367
368 static void atmel_spi_unlock(struct atmel_spi *as)
369 {
370 spin_unlock_irqrestore(&as->lock, as->flags);
371 }
372
373 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
374 struct spi_transfer *xfer)
375 {
376 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
377 }
378
379 static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
380 struct spi_transfer *xfer)
381 {
382 return msg->transfers.prev == &xfer->transfer_list;
383 }
384
385 static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
386 {
387 return xfer->delay_usecs == 0 && !xfer->cs_change;
388 }
389
390 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
391 struct dma_slave_config *slave_config,
392 u8 bits_per_word)
393 {
394 int err = 0;
395
396 if (bits_per_word > 8) {
397 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
398 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
399 } else {
400 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
401 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
402 }
403
404 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
405 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
406 slave_config->src_maxburst = 1;
407 slave_config->dst_maxburst = 1;
408 slave_config->device_fc = false;
409
410 slave_config->direction = DMA_MEM_TO_DEV;
411 if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
412 dev_err(&as->pdev->dev,
413 "failed to configure tx dma channel\n");
414 err = -EINVAL;
415 }
416
417 slave_config->direction = DMA_DEV_TO_MEM;
418 if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
419 dev_err(&as->pdev->dev,
420 "failed to configure rx dma channel\n");
421 err = -EINVAL;
422 }
423
424 return err;
425 }
426
427 static bool filter(struct dma_chan *chan, void *slave)
428 {
429 struct at_dma_slave *sl = slave;
430
431 if (sl->dma_dev == chan->device->dev) {
432 chan->private = sl;
433 return true;
434 } else {
435 return false;
436 }
437 }
438
439 static int atmel_spi_configure_dma(struct atmel_spi *as)
440 {
441 struct at_dma_slave *sdata = &as->dma.dma_slave;
442 struct dma_slave_config slave_config;
443 int err;
444
445 if (sdata && sdata->dma_dev) {
446 dma_cap_mask_t mask;
447
448 /* Try to grab two DMA channels */
449 dma_cap_zero(mask);
450 dma_cap_set(DMA_SLAVE, mask);
451 as->dma.chan_tx = dma_request_channel(mask, filter, sdata);
452 if (as->dma.chan_tx)
453 as->dma.chan_rx =
454 dma_request_channel(mask, filter, sdata);
455 }
456 if (!as->dma.chan_rx || !as->dma.chan_tx) {
457 dev_err(&as->pdev->dev,
458 "DMA channel not available, SPI unable to use DMA\n");
459 err = -EBUSY;
460 goto error;
461 }
462
463 err = atmel_spi_dma_slave_config(as, &slave_config, 8);
464 if (err)
465 goto error;
466
467 dev_info(&as->pdev->dev,
468 "Using %s (tx) and %s (rx) for DMA transfers\n",
469 dma_chan_name(as->dma.chan_tx),
470 dma_chan_name(as->dma.chan_rx));
471 return 0;
472 error:
473 if (as->dma.chan_rx)
474 dma_release_channel(as->dma.chan_rx);
475 if (as->dma.chan_tx)
476 dma_release_channel(as->dma.chan_tx);
477 return err;
478 }
479
480 static void atmel_spi_stop_dma(struct atmel_spi *as)
481 {
482 if (as->dma.chan_rx)
483 as->dma.chan_rx->device->device_control(as->dma.chan_rx,
484 DMA_TERMINATE_ALL, 0);
485 if (as->dma.chan_tx)
486 as->dma.chan_tx->device->device_control(as->dma.chan_tx,
487 DMA_TERMINATE_ALL, 0);
488 }
489
490 static void atmel_spi_release_dma(struct atmel_spi *as)
491 {
492 if (as->dma.chan_rx)
493 dma_release_channel(as->dma.chan_rx);
494 if (as->dma.chan_tx)
495 dma_release_channel(as->dma.chan_tx);
496 }
497
498 /* This function is called by the DMA driver from tasklet context */
499 static void dma_callback(void *data)
500 {
501 struct spi_master *master = data;
502 struct atmel_spi *as = spi_master_get_devdata(master);
503
504 /* trigger SPI tasklet */
505 tasklet_schedule(&as->tasklet);
506 }
507
508 /*
509 * Next transfer using PIO.
510 * lock is held, spi tasklet is blocked
511 */
512 static void atmel_spi_next_xfer_pio(struct spi_master *master,
513 struct spi_transfer *xfer)
514 {
515 struct atmel_spi *as = spi_master_get_devdata(master);
516
517 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
518
519 as->current_remaining_bytes = xfer->len;
520
521 /* Make sure data is not remaining in RDR */
522 spi_readl(as, RDR);
523 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
524 spi_readl(as, RDR);
525 cpu_relax();
526 }
527
528 if (xfer->tx_buf)
529 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf));
530 else
531 spi_writel(as, TDR, 0);
532
533 dev_dbg(master->dev.parent,
534 " start pio xfer %p: len %u tx %p rx %p\n",
535 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf);
536
537 /* Enable relevant interrupts */
538 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
539 }
540
541 /*
542 * Submit next transfer for DMA.
543 * lock is held, spi tasklet is blocked
544 */
545 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
546 struct spi_transfer *xfer,
547 u32 *plen)
548 {
549 struct atmel_spi *as = spi_master_get_devdata(master);
550 struct dma_chan *rxchan = as->dma.chan_rx;
551 struct dma_chan *txchan = as->dma.chan_tx;
552 struct dma_async_tx_descriptor *rxdesc;
553 struct dma_async_tx_descriptor *txdesc;
554 struct dma_slave_config slave_config;
555 dma_cookie_t cookie;
556 u32 len = *plen;
557
558 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
559
560 /* Check that the channels are available */
561 if (!rxchan || !txchan)
562 return -ENODEV;
563
564 /* release lock for DMA operations */
565 atmel_spi_unlock(as);
566
567 /* prepare the RX dma transfer */
568 sg_init_table(&as->dma.sgrx, 1);
569 if (xfer->rx_buf) {
570 as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
571 } else {
572 as->dma.sgrx.dma_address = as->buffer_dma;
573 if (len > BUFFER_SIZE)
574 len = BUFFER_SIZE;
575 }
576
577 /* prepare the TX dma transfer */
578 sg_init_table(&as->dma.sgtx, 1);
579 if (xfer->tx_buf) {
580 as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
581 } else {
582 as->dma.sgtx.dma_address = as->buffer_dma;
583 if (len > BUFFER_SIZE)
584 len = BUFFER_SIZE;
585 memset(as->buffer, 0, len);
586 }
587
588 sg_dma_len(&as->dma.sgtx) = len;
589 sg_dma_len(&as->dma.sgrx) = len;
590
591 *plen = len;
592
593 if (atmel_spi_dma_slave_config(as, &slave_config, 8))
594 goto err_exit;
595
596 /* Send both scatterlists */
597 rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
598 &as->dma.sgrx,
599 1,
600 DMA_FROM_DEVICE,
601 DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
602 NULL);
603 if (!rxdesc)
604 goto err_dma;
605
606 txdesc = txchan->device->device_prep_slave_sg(txchan,
607 &as->dma.sgtx,
608 1,
609 DMA_TO_DEVICE,
610 DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
611 NULL);
612 if (!txdesc)
613 goto err_dma;
614
615 dev_dbg(master->dev.parent,
616 " start dma xfer %p: len %u tx %p/%08x rx %p/%08x\n",
617 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
618 xfer->rx_buf, xfer->rx_dma);
619
620 /* Enable relevant interrupts */
621 spi_writel(as, IER, SPI_BIT(OVRES));
622
623 /* Put the callback on the RX transfer only, that should finish last */
624 rxdesc->callback = dma_callback;
625 rxdesc->callback_param = master;
626
627 /* Submit and fire RX and TX with TX last so we're ready to read! */
628 cookie = rxdesc->tx_submit(rxdesc);
629 if (dma_submit_error(cookie))
630 goto err_dma;
631 cookie = txdesc->tx_submit(txdesc);
632 if (dma_submit_error(cookie))
633 goto err_dma;
634 rxchan->device->device_issue_pending(rxchan);
635 txchan->device->device_issue_pending(txchan);
636
637 /* take back lock */
638 atmel_spi_lock(as);
639 return 0;
640
641 err_dma:
642 spi_writel(as, IDR, SPI_BIT(OVRES));
643 atmel_spi_stop_dma(as);
644 err_exit:
645 atmel_spi_lock(as);
646 return -ENOMEM;
647 }
648
649 static void atmel_spi_next_xfer_data(struct spi_master *master,
650 struct spi_transfer *xfer,
651 dma_addr_t *tx_dma,
652 dma_addr_t *rx_dma,
653 u32 *plen)
654 {
655 struct atmel_spi *as = spi_master_get_devdata(master);
656 u32 len = *plen;
657
658 /* use scratch buffer only when rx or tx data is unspecified */
659 if (xfer->rx_buf)
660 *rx_dma = xfer->rx_dma + xfer->len - *plen;
661 else {
662 *rx_dma = as->buffer_dma;
663 if (len > BUFFER_SIZE)
664 len = BUFFER_SIZE;
665 }
666
667 if (xfer->tx_buf)
668 *tx_dma = xfer->tx_dma + xfer->len - *plen;
669 else {
670 *tx_dma = as->buffer_dma;
671 if (len > BUFFER_SIZE)
672 len = BUFFER_SIZE;
673 memset(as->buffer, 0, len);
674 dma_sync_single_for_device(&as->pdev->dev,
675 as->buffer_dma, len, DMA_TO_DEVICE);
676 }
677
678 *plen = len;
679 }
680
681 /*
682 * Submit next transfer for PDC.
683 * lock is held, spi irq is blocked
684 */
685 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
686 struct spi_message *msg)
687 {
688 struct atmel_spi *as = spi_master_get_devdata(master);
689 struct spi_transfer *xfer;
690 u32 len, remaining;
691 u32 ieval;
692 dma_addr_t tx_dma, rx_dma;
693
694 if (!as->current_transfer)
695 xfer = list_entry(msg->transfers.next,
696 struct spi_transfer, transfer_list);
697 else if (!as->next_transfer)
698 xfer = list_entry(as->current_transfer->transfer_list.next,
699 struct spi_transfer, transfer_list);
700 else
701 xfer = NULL;
702
703 if (xfer) {
704 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
705
706 len = xfer->len;
707 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
708 remaining = xfer->len - len;
709
710 spi_writel(as, RPR, rx_dma);
711 spi_writel(as, TPR, tx_dma);
712
713 if (msg->spi->bits_per_word > 8)
714 len >>= 1;
715 spi_writel(as, RCR, len);
716 spi_writel(as, TCR, len);
717
718 dev_dbg(&msg->spi->dev,
719 " start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
720 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
721 xfer->rx_buf, xfer->rx_dma);
722 } else {
723 xfer = as->next_transfer;
724 remaining = as->next_remaining_bytes;
725 }
726
727 as->current_transfer = xfer;
728 as->current_remaining_bytes = remaining;
729
730 if (remaining > 0)
731 len = remaining;
732 else if (!atmel_spi_xfer_is_last(msg, xfer)
733 && atmel_spi_xfer_can_be_chained(xfer)) {
734 xfer = list_entry(xfer->transfer_list.next,
735 struct spi_transfer, transfer_list);
736 len = xfer->len;
737 } else
738 xfer = NULL;
739
740 as->next_transfer = xfer;
741
742 if (xfer) {
743 u32 total;
744
745 total = len;
746 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
747 as->next_remaining_bytes = total - len;
748
749 spi_writel(as, RNPR, rx_dma);
750 spi_writel(as, TNPR, tx_dma);
751
752 if (msg->spi->bits_per_word > 8)
753 len >>= 1;
754 spi_writel(as, RNCR, len);
755 spi_writel(as, TNCR, len);
756
757 dev_dbg(&msg->spi->dev,
758 " next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
759 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
760 xfer->rx_buf, xfer->rx_dma);
761 ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
762 } else {
763 spi_writel(as, RNCR, 0);
764 spi_writel(as, TNCR, 0);
765 ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
766 }
767
768 /* REVISIT: We're waiting for ENDRX before we start the next
769 * transfer because we need to handle some difficult timing
770 * issues otherwise. If we wait for ENDTX in one transfer and
771 * then starts waiting for ENDRX in the next, it's difficult
772 * to tell the difference between the ENDRX interrupt we're
773 * actually waiting for and the ENDRX interrupt of the
774 * previous transfer.
775 *
776 * It should be doable, though. Just not now...
777 */
778 spi_writel(as, IER, ieval);
779 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
780 }
781
782 /*
783 * Choose way to submit next transfer and start it.
784 * lock is held, spi tasklet is blocked
785 */
786 static void atmel_spi_dma_next_xfer(struct spi_master *master,
787 struct spi_message *msg)
788 {
789 struct atmel_spi *as = spi_master_get_devdata(master);
790 struct spi_transfer *xfer;
791 u32 remaining, len;
792
793 remaining = as->current_remaining_bytes;
794 if (remaining) {
795 xfer = as->current_transfer;
796 len = remaining;
797 } else {
798 if (!as->current_transfer)
799 xfer = list_entry(msg->transfers.next,
800 struct spi_transfer, transfer_list);
801 else
802 xfer = list_entry(
803 as->current_transfer->transfer_list.next,
804 struct spi_transfer, transfer_list);
805
806 as->current_transfer = xfer;
807 len = xfer->len;
808 }
809
810 if (atmel_spi_use_dma(as, xfer)) {
811 u32 total = len;
812 if (!atmel_spi_next_xfer_dma_submit(master, xfer, &len)) {
813 as->current_remaining_bytes = total - len;
814 return;
815 } else {
816 dev_err(&msg->spi->dev, "unable to use DMA, fallback to PIO\n");
817 }
818 }
819
820 /* use PIO if error appened using DMA */
821 atmel_spi_next_xfer_pio(master, xfer);
822 }
823
824 static void atmel_spi_next_message(struct spi_master *master)
825 {
826 struct atmel_spi *as = spi_master_get_devdata(master);
827 struct spi_message *msg;
828 struct spi_device *spi;
829
830 BUG_ON(as->current_transfer);
831
832 msg = list_entry(as->queue.next, struct spi_message, queue);
833 spi = msg->spi;
834
835 dev_dbg(master->dev.parent, "start message %p for %s\n",
836 msg, dev_name(&spi->dev));
837
838 /* select chip if it's not still active */
839 if (as->stay) {
840 if (as->stay != spi) {
841 cs_deactivate(as, as->stay);
842 cs_activate(as, spi);
843 }
844 as->stay = NULL;
845 } else
846 cs_activate(as, spi);
847
848 if (as->use_pdc)
849 atmel_spi_pdc_next_xfer(master, msg);
850 else
851 atmel_spi_dma_next_xfer(master, msg);
852 }
853
854 /*
855 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
856 * - The buffer is either valid for CPU access, else NULL
857 * - If the buffer is valid, so is its DMA address
858 *
859 * This driver manages the dma address unless message->is_dma_mapped.
860 */
861 static int
862 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
863 {
864 struct device *dev = &as->pdev->dev;
865
866 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
867 if (xfer->tx_buf) {
868 /* tx_buf is a const void* where we need a void * for the dma
869 * mapping */
870 void *nonconst_tx = (void *)xfer->tx_buf;
871
872 xfer->tx_dma = dma_map_single(dev,
873 nonconst_tx, xfer->len,
874 DMA_TO_DEVICE);
875 if (dma_mapping_error(dev, xfer->tx_dma))
876 return -ENOMEM;
877 }
878 if (xfer->rx_buf) {
879 xfer->rx_dma = dma_map_single(dev,
880 xfer->rx_buf, xfer->len,
881 DMA_FROM_DEVICE);
882 if (dma_mapping_error(dev, xfer->rx_dma)) {
883 if (xfer->tx_buf)
884 dma_unmap_single(dev,
885 xfer->tx_dma, xfer->len,
886 DMA_TO_DEVICE);
887 return -ENOMEM;
888 }
889 }
890 return 0;
891 }
892
893 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
894 struct spi_transfer *xfer)
895 {
896 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
897 dma_unmap_single(master->dev.parent, xfer->tx_dma,
898 xfer->len, DMA_TO_DEVICE);
899 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
900 dma_unmap_single(master->dev.parent, xfer->rx_dma,
901 xfer->len, DMA_FROM_DEVICE);
902 }
903
904 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
905 {
906 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
907 }
908
909 static void
910 atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
911 struct spi_message *msg, int stay)
912 {
913 if (!stay || as->done_status < 0)
914 cs_deactivate(as, msg->spi);
915 else
916 as->stay = msg->spi;
917
918 list_del(&msg->queue);
919 msg->status = as->done_status;
920
921 dev_dbg(master->dev.parent,
922 "xfer complete: %u bytes transferred\n",
923 msg->actual_length);
924
925 atmel_spi_unlock(as);
926 msg->complete(msg->context);
927 atmel_spi_lock(as);
928
929 as->current_transfer = NULL;
930 as->next_transfer = NULL;
931 as->done_status = 0;
932
933 /* continue if needed */
934 if (list_empty(&as->queue) || as->stopping) {
935 if (as->use_pdc)
936 atmel_spi_disable_pdc_transfer(as);
937 } else {
938 atmel_spi_next_message(master);
939 }
940 }
941
942 /* Called from IRQ
943 * lock is held
944 *
945 * Must update "current_remaining_bytes" to keep track of data
946 * to transfer.
947 */
948 static void
949 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
950 {
951 u8 *txp;
952 u8 *rxp;
953 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
954
955 if (xfer->rx_buf) {
956 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
957 *rxp = spi_readl(as, RDR);
958 } else {
959 spi_readl(as, RDR);
960 }
961
962 as->current_remaining_bytes--;
963
964 if (as->current_remaining_bytes) {
965 if (xfer->tx_buf) {
966 txp = ((u8 *)xfer->tx_buf) + xfer_pos + 1;
967 spi_writel(as, TDR, *txp);
968 } else {
969 spi_writel(as, TDR, 0);
970 }
971 }
972 }
973
974 /* Tasklet
975 * Called from DMA callback + pio transfer and overrun IRQ.
976 */
977 static void atmel_spi_tasklet_func(unsigned long data)
978 {
979 struct spi_master *master = (struct spi_master *)data;
980 struct atmel_spi *as = spi_master_get_devdata(master);
981 struct spi_message *msg;
982 struct spi_transfer *xfer;
983
984 dev_vdbg(master->dev.parent, "atmel_spi_tasklet_func\n");
985
986 atmel_spi_lock(as);
987
988 xfer = as->current_transfer;
989
990 if (xfer == NULL)
991 /* already been there */
992 goto tasklet_out;
993
994 msg = list_entry(as->queue.next, struct spi_message, queue);
995
996 if (as->current_remaining_bytes == 0) {
997 if (as->done_status < 0) {
998 /* error happened (overrun) */
999 if (atmel_spi_use_dma(as, xfer))
1000 atmel_spi_stop_dma(as);
1001 } else {
1002 /* only update length if no error */
1003 msg->actual_length += xfer->len;
1004 }
1005
1006 if (atmel_spi_use_dma(as, xfer))
1007 if (!msg->is_dma_mapped)
1008 atmel_spi_dma_unmap_xfer(master, xfer);
1009
1010 if (xfer->delay_usecs)
1011 udelay(xfer->delay_usecs);
1012
1013 if (atmel_spi_xfer_is_last(msg, xfer) || as->done_status < 0) {
1014 /* report completed (or erroneous) message */
1015 atmel_spi_msg_done(master, as, msg, xfer->cs_change);
1016 } else {
1017 if (xfer->cs_change) {
1018 cs_deactivate(as, msg->spi);
1019 udelay(1);
1020 cs_activate(as, msg->spi);
1021 }
1022
1023 /*
1024 * Not done yet. Submit the next transfer.
1025 *
1026 * FIXME handle protocol options for xfer
1027 */
1028 atmel_spi_dma_next_xfer(master, msg);
1029 }
1030 } else {
1031 /*
1032 * Keep going, we still have data to send in
1033 * the current transfer.
1034 */
1035 atmel_spi_dma_next_xfer(master, msg);
1036 }
1037
1038 tasklet_out:
1039 atmel_spi_unlock(as);
1040 }
1041
1042 /* Interrupt
1043 *
1044 * No need for locking in this Interrupt handler: done_status is the
1045 * only information modified. What we need is the update of this field
1046 * before tasklet runs. This is ensured by using barrier.
1047 */
1048 static irqreturn_t
1049 atmel_spi_pio_interrupt(int irq, void *dev_id)
1050 {
1051 struct spi_master *master = dev_id;
1052 struct atmel_spi *as = spi_master_get_devdata(master);
1053 u32 status, pending, imr;
1054 struct spi_transfer *xfer;
1055 int ret = IRQ_NONE;
1056
1057 imr = spi_readl(as, IMR);
1058 status = spi_readl(as, SR);
1059 pending = status & imr;
1060
1061 if (pending & SPI_BIT(OVRES)) {
1062 ret = IRQ_HANDLED;
1063 spi_writel(as, IDR, SPI_BIT(OVRES));
1064 dev_warn(master->dev.parent, "overrun\n");
1065
1066 /*
1067 * When we get an overrun, we disregard the current
1068 * transfer. Data will not be copied back from any
1069 * bounce buffer and msg->actual_len will not be
1070 * updated with the last xfer.
1071 *
1072 * We will also not process any remaning transfers in
1073 * the message.
1074 *
1075 * All actions are done in tasklet with done_status indication
1076 */
1077 as->done_status = -EIO;
1078 smp_wmb();
1079
1080 /* Clear any overrun happening while cleaning up */
1081 spi_readl(as, SR);
1082
1083 tasklet_schedule(&as->tasklet);
1084
1085 } else if (pending & SPI_BIT(RDRF)) {
1086 atmel_spi_lock(as);
1087
1088 if (as->current_remaining_bytes) {
1089 ret = IRQ_HANDLED;
1090 xfer = as->current_transfer;
1091 atmel_spi_pump_pio_data(as, xfer);
1092 if (!as->current_remaining_bytes) {
1093 /* no more data to xfer, kick tasklet */
1094 spi_writel(as, IDR, pending);
1095 tasklet_schedule(&as->tasklet);
1096 }
1097 }
1098
1099 atmel_spi_unlock(as);
1100 } else {
1101 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1102 ret = IRQ_HANDLED;
1103 spi_writel(as, IDR, pending);
1104 }
1105
1106 return ret;
1107 }
1108
1109 static irqreturn_t
1110 atmel_spi_pdc_interrupt(int irq, void *dev_id)
1111 {
1112 struct spi_master *master = dev_id;
1113 struct atmel_spi *as = spi_master_get_devdata(master);
1114 struct spi_message *msg;
1115 struct spi_transfer *xfer;
1116 u32 status, pending, imr;
1117 int ret = IRQ_NONE;
1118
1119 atmel_spi_lock(as);
1120
1121 xfer = as->current_transfer;
1122 msg = list_entry(as->queue.next, struct spi_message, queue);
1123
1124 imr = spi_readl(as, IMR);
1125 status = spi_readl(as, SR);
1126 pending = status & imr;
1127
1128 if (pending & SPI_BIT(OVRES)) {
1129 int timeout;
1130
1131 ret = IRQ_HANDLED;
1132
1133 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1134 | SPI_BIT(OVRES)));
1135
1136 /*
1137 * When we get an overrun, we disregard the current
1138 * transfer. Data will not be copied back from any
1139 * bounce buffer and msg->actual_len will not be
1140 * updated with the last xfer.
1141 *
1142 * We will also not process any remaning transfers in
1143 * the message.
1144 *
1145 * First, stop the transfer and unmap the DMA buffers.
1146 */
1147 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1148 if (!msg->is_dma_mapped)
1149 atmel_spi_dma_unmap_xfer(master, xfer);
1150
1151 /* REVISIT: udelay in irq is unfriendly */
1152 if (xfer->delay_usecs)
1153 udelay(xfer->delay_usecs);
1154
1155 dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
1156 spi_readl(as, TCR), spi_readl(as, RCR));
1157
1158 /*
1159 * Clean up DMA registers and make sure the data
1160 * registers are empty.
1161 */
1162 spi_writel(as, RNCR, 0);
1163 spi_writel(as, TNCR, 0);
1164 spi_writel(as, RCR, 0);
1165 spi_writel(as, TCR, 0);
1166 for (timeout = 1000; timeout; timeout--)
1167 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1168 break;
1169 if (!timeout)
1170 dev_warn(master->dev.parent,
1171 "timeout waiting for TXEMPTY");
1172 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1173 spi_readl(as, RDR);
1174
1175 /* Clear any overrun happening while cleaning up */
1176 spi_readl(as, SR);
1177
1178 as->done_status = -EIO;
1179 atmel_spi_msg_done(master, as, msg, 0);
1180 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1181 ret = IRQ_HANDLED;
1182
1183 spi_writel(as, IDR, pending);
1184
1185 if (as->current_remaining_bytes == 0) {
1186 msg->actual_length += xfer->len;
1187
1188 if (!msg->is_dma_mapped)
1189 atmel_spi_dma_unmap_xfer(master, xfer);
1190
1191 /* REVISIT: udelay in irq is unfriendly */
1192 if (xfer->delay_usecs)
1193 udelay(xfer->delay_usecs);
1194
1195 if (atmel_spi_xfer_is_last(msg, xfer)) {
1196 /* report completed message */
1197 atmel_spi_msg_done(master, as, msg,
1198 xfer->cs_change);
1199 } else {
1200 if (xfer->cs_change) {
1201 cs_deactivate(as, msg->spi);
1202 udelay(1);
1203 cs_activate(as, msg->spi);
1204 }
1205
1206 /*
1207 * Not done yet. Submit the next transfer.
1208 *
1209 * FIXME handle protocol options for xfer
1210 */
1211 atmel_spi_pdc_next_xfer(master, msg);
1212 }
1213 } else {
1214 /*
1215 * Keep going, we still have data to send in
1216 * the current transfer.
1217 */
1218 atmel_spi_pdc_next_xfer(master, msg);
1219 }
1220 }
1221
1222 atmel_spi_unlock(as);
1223
1224 return ret;
1225 }
1226
1227 static int atmel_spi_setup(struct spi_device *spi)
1228 {
1229 struct atmel_spi *as;
1230 struct atmel_spi_device *asd;
1231 u32 scbr, csr;
1232 unsigned int bits = spi->bits_per_word;
1233 unsigned long bus_hz;
1234 unsigned int npcs_pin;
1235 int ret;
1236
1237 as = spi_master_get_devdata(spi->master);
1238
1239 if (as->stopping)
1240 return -ESHUTDOWN;
1241
1242 if (spi->chip_select > spi->master->num_chipselect) {
1243 dev_dbg(&spi->dev,
1244 "setup: invalid chipselect %u (%u defined)\n",
1245 spi->chip_select, spi->master->num_chipselect);
1246 return -EINVAL;
1247 }
1248
1249 if (bits < 8 || bits > 16) {
1250 dev_dbg(&spi->dev,
1251 "setup: invalid bits_per_word %u (8 to 16)\n",
1252 bits);
1253 return -EINVAL;
1254 }
1255
1256 /* see notes above re chipselect */
1257 if (!atmel_spi_is_v2(as)
1258 && spi->chip_select == 0
1259 && (spi->mode & SPI_CS_HIGH)) {
1260 dev_dbg(&spi->dev, "setup: can't be active-high\n");
1261 return -EINVAL;
1262 }
1263
1264 /* v1 chips start out at half the peripheral bus speed. */
1265 bus_hz = clk_get_rate(as->clk);
1266 if (!atmel_spi_is_v2(as))
1267 bus_hz /= 2;
1268
1269 if (spi->max_speed_hz) {
1270 /*
1271 * Calculate the lowest divider that satisfies the
1272 * constraint, assuming div32/fdiv/mbz == 0.
1273 */
1274 scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
1275
1276 /*
1277 * If the resulting divider doesn't fit into the
1278 * register bitfield, we can't satisfy the constraint.
1279 */
1280 if (scbr >= (1 << SPI_SCBR_SIZE)) {
1281 dev_dbg(&spi->dev,
1282 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
1283 spi->max_speed_hz, scbr, bus_hz/255);
1284 return -EINVAL;
1285 }
1286 } else
1287 /* speed zero means "as slow as possible" */
1288 scbr = 0xff;
1289
1290 csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
1291 if (spi->mode & SPI_CPOL)
1292 csr |= SPI_BIT(CPOL);
1293 if (!(spi->mode & SPI_CPHA))
1294 csr |= SPI_BIT(NCPHA);
1295
1296 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1297 *
1298 * DLYBCT would add delays between words, slowing down transfers.
1299 * It could potentially be useful to cope with DMA bottlenecks, but
1300 * in those cases it's probably best to just use a lower bitrate.
1301 */
1302 csr |= SPI_BF(DLYBS, 0);
1303 csr |= SPI_BF(DLYBCT, 0);
1304
1305 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1306 npcs_pin = (unsigned int)spi->controller_data;
1307
1308 if (gpio_is_valid(spi->cs_gpio))
1309 npcs_pin = spi->cs_gpio;
1310
1311 asd = spi->controller_state;
1312 if (!asd) {
1313 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1314 if (!asd)
1315 return -ENOMEM;
1316
1317 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
1318 if (ret) {
1319 kfree(asd);
1320 return ret;
1321 }
1322
1323 asd->npcs_pin = npcs_pin;
1324 spi->controller_state = asd;
1325 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
1326 } else {
1327 atmel_spi_lock(as);
1328 if (as->stay == spi)
1329 as->stay = NULL;
1330 cs_deactivate(as, spi);
1331 atmel_spi_unlock(as);
1332 }
1333
1334 asd->csr = csr;
1335
1336 dev_dbg(&spi->dev,
1337 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
1338 bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
1339
1340 if (!atmel_spi_is_v2(as))
1341 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1342
1343 return 0;
1344 }
1345
1346 static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
1347 {
1348 struct atmel_spi *as;
1349 struct spi_transfer *xfer;
1350 struct device *controller = spi->master->dev.parent;
1351 u8 bits;
1352 struct atmel_spi_device *asd;
1353
1354 as = spi_master_get_devdata(spi->master);
1355
1356 dev_dbg(controller, "new message %p submitted for %s\n",
1357 msg, dev_name(&spi->dev));
1358
1359 if (unlikely(list_empty(&msg->transfers)))
1360 return -EINVAL;
1361
1362 if (as->stopping)
1363 return -ESHUTDOWN;
1364
1365 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1366 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1367 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1368 return -EINVAL;
1369 }
1370
1371 if (xfer->bits_per_word) {
1372 asd = spi->controller_state;
1373 bits = (asd->csr >> 4) & 0xf;
1374 if (bits != xfer->bits_per_word - 8) {
1375 dev_dbg(&spi->dev, "you can't yet change "
1376 "bits_per_word in transfers\n");
1377 return -ENOPROTOOPT;
1378 }
1379 }
1380
1381 /* FIXME implement these protocol options!! */
1382 if (xfer->speed_hz) {
1383 dev_dbg(&spi->dev, "no protocol options yet\n");
1384 return -ENOPROTOOPT;
1385 }
1386
1387 /*
1388 * DMA map early, for performance (empties dcache ASAP) and
1389 * better fault reporting.
1390 */
1391 if ((!msg->is_dma_mapped) && (atmel_spi_use_dma(as, xfer)
1392 || as->use_pdc)) {
1393 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1394 return -ENOMEM;
1395 }
1396 }
1397
1398 #ifdef VERBOSE
1399 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1400 dev_dbg(controller,
1401 " xfer %p: len %u tx %p/%08x rx %p/%08x\n",
1402 xfer, xfer->len,
1403 xfer->tx_buf, xfer->tx_dma,
1404 xfer->rx_buf, xfer->rx_dma);
1405 }
1406 #endif
1407
1408 msg->status = -EINPROGRESS;
1409 msg->actual_length = 0;
1410
1411 atmel_spi_lock(as);
1412 list_add_tail(&msg->queue, &as->queue);
1413 if (!as->current_transfer)
1414 atmel_spi_next_message(spi->master);
1415 atmel_spi_unlock(as);
1416
1417 return 0;
1418 }
1419
1420 static void atmel_spi_cleanup(struct spi_device *spi)
1421 {
1422 struct atmel_spi *as = spi_master_get_devdata(spi->master);
1423 struct atmel_spi_device *asd = spi->controller_state;
1424 unsigned gpio = (unsigned) spi->controller_data;
1425
1426 if (!asd)
1427 return;
1428
1429 atmel_spi_lock(as);
1430 if (as->stay == spi) {
1431 as->stay = NULL;
1432 cs_deactivate(as, spi);
1433 }
1434 atmel_spi_unlock(as);
1435
1436 spi->controller_state = NULL;
1437 gpio_free(gpio);
1438 kfree(asd);
1439 }
1440
1441 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1442 {
1443 return spi_readl(as, VERSION) & 0x00000fff;
1444 }
1445
1446 static void atmel_get_caps(struct atmel_spi *as)
1447 {
1448 unsigned int version;
1449
1450 version = atmel_get_version(as);
1451 dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1452
1453 as->caps.is_spi2 = version > 0x121;
1454 as->caps.has_wdrbt = version >= 0x210;
1455 as->caps.has_dma_support = version >= 0x212;
1456 }
1457
1458 /*-------------------------------------------------------------------------*/
1459
1460 static int atmel_spi_probe(struct platform_device *pdev)
1461 {
1462 struct resource *regs;
1463 int irq;
1464 struct clk *clk;
1465 int ret;
1466 struct spi_master *master;
1467 struct atmel_spi *as;
1468
1469 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1470 if (!regs)
1471 return -ENXIO;
1472
1473 irq = platform_get_irq(pdev, 0);
1474 if (irq < 0)
1475 return irq;
1476
1477 clk = clk_get(&pdev->dev, "spi_clk");
1478 if (IS_ERR(clk))
1479 return PTR_ERR(clk);
1480
1481 /* setup spi core then atmel-specific driver state */
1482 ret = -ENOMEM;
1483 master = spi_alloc_master(&pdev->dev, sizeof *as);
1484 if (!master)
1485 goto out_free;
1486
1487 /* the spi->mode bits understood by this driver: */
1488 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1489
1490 master->dev.of_node = pdev->dev.of_node;
1491 master->bus_num = pdev->id;
1492 master->num_chipselect = master->dev.of_node ? 0 : 4;
1493 master->setup = atmel_spi_setup;
1494 master->transfer = atmel_spi_transfer;
1495 master->cleanup = atmel_spi_cleanup;
1496 platform_set_drvdata(pdev, master);
1497
1498 as = spi_master_get_devdata(master);
1499
1500 /*
1501 * Scratch buffer is used for throwaway rx and tx data.
1502 * It's coherent to minimize dcache pollution.
1503 */
1504 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
1505 &as->buffer_dma, GFP_KERNEL);
1506 if (!as->buffer)
1507 goto out_free;
1508
1509 spin_lock_init(&as->lock);
1510 INIT_LIST_HEAD(&as->queue);
1511
1512 as->pdev = pdev;
1513 as->regs = ioremap(regs->start, resource_size(regs));
1514 if (!as->regs)
1515 goto out_free_buffer;
1516 as->phybase = regs->start;
1517 as->irq = irq;
1518 as->clk = clk;
1519
1520 atmel_get_caps(as);
1521
1522 as->use_dma = false;
1523 as->use_pdc = false;
1524 if (as->caps.has_dma_support) {
1525 if (atmel_spi_configure_dma(as) == 0)
1526 as->use_dma = true;
1527 } else {
1528 as->use_pdc = true;
1529 }
1530
1531 if (as->caps.has_dma_support && !as->use_dma)
1532 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1533
1534 if (as->use_pdc) {
1535 ret = request_irq(irq, atmel_spi_pdc_interrupt, 0,
1536 dev_name(&pdev->dev), master);
1537 } else {
1538 tasklet_init(&as->tasklet, atmel_spi_tasklet_func,
1539 (unsigned long)master);
1540
1541 ret = request_irq(irq, atmel_spi_pio_interrupt, 0,
1542 dev_name(&pdev->dev), master);
1543 }
1544 if (ret)
1545 goto out_unmap_regs;
1546
1547 /* Initialize the hardware */
1548 clk_enable(clk);
1549 spi_writel(as, CR, SPI_BIT(SWRST));
1550 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1551 if (as->caps.has_wdrbt) {
1552 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1553 | SPI_BIT(MSTR));
1554 } else {
1555 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1556 }
1557
1558 if (as->use_pdc)
1559 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1560 spi_writel(as, CR, SPI_BIT(SPIEN));
1561
1562 /* go! */
1563 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1564 (unsigned long)regs->start, irq);
1565
1566 ret = spi_register_master(master);
1567 if (ret)
1568 goto out_free_dma;
1569
1570 return 0;
1571
1572 out_free_dma:
1573 if (as->use_dma)
1574 atmel_spi_release_dma(as);
1575
1576 spi_writel(as, CR, SPI_BIT(SWRST));
1577 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1578 clk_disable(clk);
1579 free_irq(irq, master);
1580 out_unmap_regs:
1581 iounmap(as->regs);
1582 out_free_buffer:
1583 if (!as->use_pdc)
1584 tasklet_kill(&as->tasklet);
1585 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1586 as->buffer_dma);
1587 out_free:
1588 clk_put(clk);
1589 spi_master_put(master);
1590 return ret;
1591 }
1592
1593 static int atmel_spi_remove(struct platform_device *pdev)
1594 {
1595 struct spi_master *master = platform_get_drvdata(pdev);
1596 struct atmel_spi *as = spi_master_get_devdata(master);
1597 struct spi_message *msg;
1598 struct spi_transfer *xfer;
1599
1600 /* reset the hardware and block queue progress */
1601 spin_lock_irq(&as->lock);
1602 as->stopping = 1;
1603 if (as->use_dma) {
1604 atmel_spi_stop_dma(as);
1605 atmel_spi_release_dma(as);
1606 }
1607
1608 spi_writel(as, CR, SPI_BIT(SWRST));
1609 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1610 spi_readl(as, SR);
1611 spin_unlock_irq(&as->lock);
1612
1613 /* Terminate remaining queued transfers */
1614 list_for_each_entry(msg, &as->queue, queue) {
1615 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1616 if (!msg->is_dma_mapped
1617 && (atmel_spi_use_dma(as, xfer)
1618 || as->use_pdc))
1619 atmel_spi_dma_unmap_xfer(master, xfer);
1620 }
1621 msg->status = -ESHUTDOWN;
1622 msg->complete(msg->context);
1623 }
1624
1625 if (!as->use_pdc)
1626 tasklet_kill(&as->tasklet);
1627 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1628 as->buffer_dma);
1629
1630 clk_disable(as->clk);
1631 clk_put(as->clk);
1632 free_irq(as->irq, master);
1633 iounmap(as->regs);
1634
1635 spi_unregister_master(master);
1636
1637 return 0;
1638 }
1639
1640 #ifdef CONFIG_PM
1641
1642 static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
1643 {
1644 struct spi_master *master = platform_get_drvdata(pdev);
1645 struct atmel_spi *as = spi_master_get_devdata(master);
1646
1647 clk_disable(as->clk);
1648 return 0;
1649 }
1650
1651 static int atmel_spi_resume(struct platform_device *pdev)
1652 {
1653 struct spi_master *master = platform_get_drvdata(pdev);
1654 struct atmel_spi *as = spi_master_get_devdata(master);
1655
1656 clk_enable(as->clk);
1657 return 0;
1658 }
1659
1660 #else
1661 #define atmel_spi_suspend NULL
1662 #define atmel_spi_resume NULL
1663 #endif
1664
1665 #if defined(CONFIG_OF)
1666 static const struct of_device_id atmel_spi_dt_ids[] = {
1667 { .compatible = "atmel,at91rm9200-spi" },
1668 { /* sentinel */ }
1669 };
1670
1671 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1672 #endif
1673
1674 static struct platform_driver atmel_spi_driver = {
1675 .driver = {
1676 .name = "atmel_spi",
1677 .owner = THIS_MODULE,
1678 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1679 },
1680 .suspend = atmel_spi_suspend,
1681 .resume = atmel_spi_resume,
1682 .probe = atmel_spi_probe,
1683 .remove = atmel_spi_remove,
1684 };
1685 module_platform_driver(atmel_spi_driver);
1686
1687 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1688 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1689 MODULE_LICENSE("GPL");
1690 MODULE_ALIAS("platform:atmel_spi");
kernel source for telekom puls (alcatel/mediatek)