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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi-atmel.c
1 /*
2 * Driver for Atmel AT32 and AT91 SPI Controllers
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/dmaengine.h>
19 #include <linux/err.h>
20 #include <linux/interrupt.h>
21 #include <linux/spi/spi.h>
22 #include <linux/slab.h>
23 #include <linux/platform_data/atmel.h>
24 #include <linux/platform_data/dma-atmel.h>
25 #include <linux/of.h>
26
27 #include <linux/io.h>
28 #include <linux/gpio.h>
29
30 /* SPI register offsets */
31 #define SPI_CR 0x0000
32 #define SPI_MR 0x0004
33 #define SPI_RDR 0x0008
34 #define SPI_TDR 0x000c
35 #define SPI_SR 0x0010
36 #define SPI_IER 0x0014
37 #define SPI_IDR 0x0018
38 #define SPI_IMR 0x001c
39 #define SPI_CSR0 0x0030
40 #define SPI_CSR1 0x0034
41 #define SPI_CSR2 0x0038
42 #define SPI_CSR3 0x003c
43 #define SPI_VERSION 0x00fc
44 #define SPI_RPR 0x0100
45 #define SPI_RCR 0x0104
46 #define SPI_TPR 0x0108
47 #define SPI_TCR 0x010c
48 #define SPI_RNPR 0x0110
49 #define SPI_RNCR 0x0114
50 #define SPI_TNPR 0x0118
51 #define SPI_TNCR 0x011c
52 #define SPI_PTCR 0x0120
53 #define SPI_PTSR 0x0124
54
55 /* Bitfields in CR */
56 #define SPI_SPIEN_OFFSET 0
57 #define SPI_SPIEN_SIZE 1
58 #define SPI_SPIDIS_OFFSET 1
59 #define SPI_SPIDIS_SIZE 1
60 #define SPI_SWRST_OFFSET 7
61 #define SPI_SWRST_SIZE 1
62 #define SPI_LASTXFER_OFFSET 24
63 #define SPI_LASTXFER_SIZE 1
64
65 /* Bitfields in MR */
66 #define SPI_MSTR_OFFSET 0
67 #define SPI_MSTR_SIZE 1
68 #define SPI_PS_OFFSET 1
69 #define SPI_PS_SIZE 1
70 #define SPI_PCSDEC_OFFSET 2
71 #define SPI_PCSDEC_SIZE 1
72 #define SPI_FDIV_OFFSET 3
73 #define SPI_FDIV_SIZE 1
74 #define SPI_MODFDIS_OFFSET 4
75 #define SPI_MODFDIS_SIZE 1
76 #define SPI_WDRBT_OFFSET 5
77 #define SPI_WDRBT_SIZE 1
78 #define SPI_LLB_OFFSET 7
79 #define SPI_LLB_SIZE 1
80 #define SPI_PCS_OFFSET 16
81 #define SPI_PCS_SIZE 4
82 #define SPI_DLYBCS_OFFSET 24
83 #define SPI_DLYBCS_SIZE 8
84
85 /* Bitfields in RDR */
86 #define SPI_RD_OFFSET 0
87 #define SPI_RD_SIZE 16
88
89 /* Bitfields in TDR */
90 #define SPI_TD_OFFSET 0
91 #define SPI_TD_SIZE 16
92
93 /* Bitfields in SR */
94 #define SPI_RDRF_OFFSET 0
95 #define SPI_RDRF_SIZE 1
96 #define SPI_TDRE_OFFSET 1
97 #define SPI_TDRE_SIZE 1
98 #define SPI_MODF_OFFSET 2
99 #define SPI_MODF_SIZE 1
100 #define SPI_OVRES_OFFSET 3
101 #define SPI_OVRES_SIZE 1
102 #define SPI_ENDRX_OFFSET 4
103 #define SPI_ENDRX_SIZE 1
104 #define SPI_ENDTX_OFFSET 5
105 #define SPI_ENDTX_SIZE 1
106 #define SPI_RXBUFF_OFFSET 6
107 #define SPI_RXBUFF_SIZE 1
108 #define SPI_TXBUFE_OFFSET 7
109 #define SPI_TXBUFE_SIZE 1
110 #define SPI_NSSR_OFFSET 8
111 #define SPI_NSSR_SIZE 1
112 #define SPI_TXEMPTY_OFFSET 9
113 #define SPI_TXEMPTY_SIZE 1
114 #define SPI_SPIENS_OFFSET 16
115 #define SPI_SPIENS_SIZE 1
116
117 /* Bitfields in CSR0 */
118 #define SPI_CPOL_OFFSET 0
119 #define SPI_CPOL_SIZE 1
120 #define SPI_NCPHA_OFFSET 1
121 #define SPI_NCPHA_SIZE 1
122 #define SPI_CSAAT_OFFSET 3
123 #define SPI_CSAAT_SIZE 1
124 #define SPI_BITS_OFFSET 4
125 #define SPI_BITS_SIZE 4
126 #define SPI_SCBR_OFFSET 8
127 #define SPI_SCBR_SIZE 8
128 #define SPI_DLYBS_OFFSET 16
129 #define SPI_DLYBS_SIZE 8
130 #define SPI_DLYBCT_OFFSET 24
131 #define SPI_DLYBCT_SIZE 8
132
133 /* Bitfields in RCR */
134 #define SPI_RXCTR_OFFSET 0
135 #define SPI_RXCTR_SIZE 16
136
137 /* Bitfields in TCR */
138 #define SPI_TXCTR_OFFSET 0
139 #define SPI_TXCTR_SIZE 16
140
141 /* Bitfields in RNCR */
142 #define SPI_RXNCR_OFFSET 0
143 #define SPI_RXNCR_SIZE 16
144
145 /* Bitfields in TNCR */
146 #define SPI_TXNCR_OFFSET 0
147 #define SPI_TXNCR_SIZE 16
148
149 /* Bitfields in PTCR */
150 #define SPI_RXTEN_OFFSET 0
151 #define SPI_RXTEN_SIZE 1
152 #define SPI_RXTDIS_OFFSET 1
153 #define SPI_RXTDIS_SIZE 1
154 #define SPI_TXTEN_OFFSET 8
155 #define SPI_TXTEN_SIZE 1
156 #define SPI_TXTDIS_OFFSET 9
157 #define SPI_TXTDIS_SIZE 1
158
159 /* Constants for BITS */
160 #define SPI_BITS_8_BPT 0
161 #define SPI_BITS_9_BPT 1
162 #define SPI_BITS_10_BPT 2
163 #define SPI_BITS_11_BPT 3
164 #define SPI_BITS_12_BPT 4
165 #define SPI_BITS_13_BPT 5
166 #define SPI_BITS_14_BPT 6
167 #define SPI_BITS_15_BPT 7
168 #define SPI_BITS_16_BPT 8
169
170 /* Bit manipulation macros */
171 #define SPI_BIT(name) \
172 (1 << SPI_##name##_OFFSET)
173 #define SPI_BF(name,value) \
174 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
175 #define SPI_BFEXT(name,value) \
176 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
177 #define SPI_BFINS(name,value,old) \
178 ( ((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
179 | SPI_BF(name,value))
180
181 /* Register access macros */
182 #define spi_readl(port,reg) \
183 __raw_readl((port)->regs + SPI_##reg)
184 #define spi_writel(port,reg,value) \
185 __raw_writel((value), (port)->regs + SPI_##reg)
186
187 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
188 * cache operations; better heuristics consider wordsize and bitrate.
189 */
190 #define DMA_MIN_BYTES 16
191
192 struct atmel_spi_dma {
193 struct dma_chan *chan_rx;
194 struct dma_chan *chan_tx;
195 struct scatterlist sgrx;
196 struct scatterlist sgtx;
197 struct dma_async_tx_descriptor *data_desc_rx;
198 struct dma_async_tx_descriptor *data_desc_tx;
199
200 struct at_dma_slave dma_slave;
201 };
202
203 struct atmel_spi_caps {
204 bool is_spi2;
205 bool has_wdrbt;
206 bool has_dma_support;
207 };
208
209 /*
210 * The core SPI transfer engine just talks to a register bank to set up
211 * DMA transfers; transfer queue progress is driven by IRQs. The clock
212 * framework provides the base clock, subdivided for each spi_device.
213 */
214 struct atmel_spi {
215 spinlock_t lock;
216 unsigned long flags;
217
218 phys_addr_t phybase;
219 void __iomem *regs;
220 int irq;
221 struct clk *clk;
222 struct platform_device *pdev;
223 struct spi_device *stay;
224
225 u8 stopping;
226 struct list_head queue;
227 struct tasklet_struct tasklet;
228 struct spi_transfer *current_transfer;
229 unsigned long current_remaining_bytes;
230 struct spi_transfer *next_transfer;
231 unsigned long next_remaining_bytes;
232 int done_status;
233
234 /* scratch buffer */
235 void *buffer;
236 dma_addr_t buffer_dma;
237
238 struct atmel_spi_caps caps;
239
240 bool use_dma;
241 bool use_pdc;
242 /* dmaengine data */
243 struct atmel_spi_dma dma;
244 };
245
246 /* Controller-specific per-slave state */
247 struct atmel_spi_device {
248 unsigned int npcs_pin;
249 u32 csr;
250 };
251
252 #define BUFFER_SIZE PAGE_SIZE
253 #define INVALID_DMA_ADDRESS 0xffffffff
254
255 /*
256 * Version 2 of the SPI controller has
257 * - CR.LASTXFER
258 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
259 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
260 * - SPI_CSRx.CSAAT
261 * - SPI_CSRx.SBCR allows faster clocking
262 */
263 static bool atmel_spi_is_v2(struct atmel_spi *as)
264 {
265 return as->caps.is_spi2;
266 }
267
268 /*
269 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
270 * they assume that spi slave device state will not change on deselect, so
271 * that automagic deselection is OK. ("NPCSx rises if no data is to be
272 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
273 * controllers have CSAAT and friends.
274 *
275 * Since the CSAAT functionality is a bit weird on newer controllers as
276 * well, we use GPIO to control nCSx pins on all controllers, updating
277 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
278 * support active-high chipselects despite the controller's belief that
279 * only active-low devices/systems exists.
280 *
281 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
282 * right when driven with GPIO. ("Mode Fault does not allow more than one
283 * Master on Chip Select 0.") No workaround exists for that ... so for
284 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
285 * and (c) will trigger that first erratum in some cases.
286 */
287
288 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
289 {
290 struct atmel_spi_device *asd = spi->controller_state;
291 unsigned active = spi->mode & SPI_CS_HIGH;
292 u32 mr;
293
294 if (atmel_spi_is_v2(as)) {
295 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
296 /* For the low SPI version, there is a issue that PDC transfer
297 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
298 */
299 spi_writel(as, CSR0, asd->csr);
300 if (as->caps.has_wdrbt) {
301 spi_writel(as, MR,
302 SPI_BF(PCS, ~(0x01 << spi->chip_select))
303 | SPI_BIT(WDRBT)
304 | SPI_BIT(MODFDIS)
305 | SPI_BIT(MSTR));
306 } else {
307 spi_writel(as, MR,
308 SPI_BF(PCS, ~(0x01 << spi->chip_select))
309 | SPI_BIT(MODFDIS)
310 | SPI_BIT(MSTR));
311 }
312
313 mr = spi_readl(as, MR);
314 gpio_set_value(asd->npcs_pin, active);
315 } else {
316 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
317 int i;
318 u32 csr;
319
320 /* Make sure clock polarity is correct */
321 for (i = 0; i < spi->master->num_chipselect; i++) {
322 csr = spi_readl(as, CSR0 + 4 * i);
323 if ((csr ^ cpol) & SPI_BIT(CPOL))
324 spi_writel(as, CSR0 + 4 * i,
325 csr ^ SPI_BIT(CPOL));
326 }
327
328 mr = spi_readl(as, MR);
329 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
330 if (spi->chip_select != 0)
331 gpio_set_value(asd->npcs_pin, active);
332 spi_writel(as, MR, mr);
333 }
334
335 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
336 asd->npcs_pin, active ? " (high)" : "",
337 mr);
338 }
339
340 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
341 {
342 struct atmel_spi_device *asd = spi->controller_state;
343 unsigned active = spi->mode & SPI_CS_HIGH;
344 u32 mr;
345
346 /* only deactivate *this* device; sometimes transfers to
347 * another device may be active when this routine is called.
348 */
349 mr = spi_readl(as, MR);
350 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
351 mr = SPI_BFINS(PCS, 0xf, mr);
352 spi_writel(as, MR, mr);
353 }
354
355 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
356 asd->npcs_pin, active ? " (low)" : "",
357 mr);
358
359 if (atmel_spi_is_v2(as) || spi->chip_select != 0)
360 gpio_set_value(asd->npcs_pin, !active);
361 }
362
363 static void atmel_spi_lock(struct atmel_spi *as)
364 {
365 spin_lock_irqsave(&as->lock, as->flags);
366 }
367
368 static void atmel_spi_unlock(struct atmel_spi *as)
369 {
370 spin_unlock_irqrestore(&as->lock, as->flags);
371 }
372
373 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
374 struct spi_transfer *xfer)
375 {
376 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
377 }
378
379 static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
380 struct spi_transfer *xfer)
381 {
382 return msg->transfers.prev == &xfer->transfer_list;
383 }
384
385 static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
386 {
387 return xfer->delay_usecs == 0 && !xfer->cs_change;
388 }
389
390 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
391 struct dma_slave_config *slave_config,
392 u8 bits_per_word)
393 {
394 int err = 0;
395
396 if (bits_per_word > 8) {
397 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
398 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
399 } else {
400 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
401 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
402 }
403
404 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
405 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
406 slave_config->src_maxburst = 1;
407 slave_config->dst_maxburst = 1;
408 slave_config->device_fc = false;
409
410 slave_config->direction = DMA_MEM_TO_DEV;
411 if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
412 dev_err(&as->pdev->dev,
413 "failed to configure tx dma channel\n");
414 err = -EINVAL;
415 }
416
417 slave_config->direction = DMA_DEV_TO_MEM;
418 if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
419 dev_err(&as->pdev->dev,
420 "failed to configure rx dma channel\n");
421 err = -EINVAL;
422 }
423
424 return err;
425 }
426
427 static bool filter(struct dma_chan *chan, void *slave)
428 {
429 struct at_dma_slave *sl = slave;
430
431 if (sl->dma_dev == chan->device->dev) {
432 chan->private = sl;
433 return true;
434 } else {
435 return false;
436 }
437 }
438
439 static int atmel_spi_configure_dma(struct atmel_spi *as)
440 {
441 struct at_dma_slave *sdata = &as->dma.dma_slave;
442 struct dma_slave_config slave_config;
443 int err;
444
445 if (sdata && sdata->dma_dev) {
446 dma_cap_mask_t mask;
447
448 /* Try to grab two DMA channels */
449 dma_cap_zero(mask);
450 dma_cap_set(DMA_SLAVE, mask);
451 as->dma.chan_tx = dma_request_channel(mask, filter, sdata);
452 if (as->dma.chan_tx)
453 as->dma.chan_rx =
454 dma_request_channel(mask, filter, sdata);
455 }
456 if (!as->dma.chan_rx || !as->dma.chan_tx) {
457 dev_err(&as->pdev->dev,
458 "DMA channel not available, SPI unable to use DMA\n");
459 err = -EBUSY;
460 goto error;
461 }
462
463 err = atmel_spi_dma_slave_config(as, &slave_config, 8);
464 if (err)
465 goto error;
466
467 dev_info(&as->pdev->dev,
468 "Using %s (tx) and %s (rx) for DMA transfers\n",
469 dma_chan_name(as->dma.chan_tx),
470 dma_chan_name(as->dma.chan_rx));
471 return 0;
472 error:
473 if (as->dma.chan_rx)
474 dma_release_channel(as->dma.chan_rx);
475 if (as->dma.chan_tx)
476 dma_release_channel(as->dma.chan_tx);
477 return err;
478 }
479
480 static void atmel_spi_stop_dma(struct atmel_spi *as)
481 {
482 if (as->dma.chan_rx)
483 as->dma.chan_rx->device->device_control(as->dma.chan_rx,
484 DMA_TERMINATE_ALL, 0);
485 if (as->dma.chan_tx)
486 as->dma.chan_tx->device->device_control(as->dma.chan_tx,
487 DMA_TERMINATE_ALL, 0);
488 }
489
490 static void atmel_spi_release_dma(struct atmel_spi *as)
491 {
492 if (as->dma.chan_rx)
493 dma_release_channel(as->dma.chan_rx);
494 if (as->dma.chan_tx)
495 dma_release_channel(as->dma.chan_tx);
496 }
497
498 /* This function is called by the DMA driver from tasklet context */
499 static void dma_callback(void *data)
500 {
501 struct spi_master *master = data;
502 struct atmel_spi *as = spi_master_get_devdata(master);
503
504 /* trigger SPI tasklet */
505 tasklet_schedule(&as->tasklet);
506 }
507
508 /*
509 * Next transfer using PIO.
510 * lock is held, spi tasklet is blocked
511 */
512 static void atmel_spi_next_xfer_pio(struct spi_master *master,
513 struct spi_transfer *xfer)
514 {
515 struct atmel_spi *as = spi_master_get_devdata(master);
516
517 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
518
519 as->current_remaining_bytes = xfer->len;
520
521 /* Make sure data is not remaining in RDR */
522 spi_readl(as, RDR);
523 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
524 spi_readl(as, RDR);
525 cpu_relax();
526 }
527
528 if (xfer->tx_buf)
529 if (xfer->bits_per_word > 8)
530 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf));
531 else
532 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf));
533 else
534 spi_writel(as, TDR, 0);
535
536 dev_dbg(master->dev.parent,
537 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
538 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
539 xfer->bits_per_word);
540
541 /* Enable relevant interrupts */
542 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
543 }
544
545 /*
546 * Submit next transfer for DMA.
547 * lock is held, spi tasklet is blocked
548 */
549 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
550 struct spi_transfer *xfer,
551 u32 *plen)
552 {
553 struct atmel_spi *as = spi_master_get_devdata(master);
554 struct dma_chan *rxchan = as->dma.chan_rx;
555 struct dma_chan *txchan = as->dma.chan_tx;
556 struct dma_async_tx_descriptor *rxdesc;
557 struct dma_async_tx_descriptor *txdesc;
558 struct dma_slave_config slave_config;
559 dma_cookie_t cookie;
560 u32 len = *plen;
561
562 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
563
564 /* Check that the channels are available */
565 if (!rxchan || !txchan)
566 return -ENODEV;
567
568 /* release lock for DMA operations */
569 atmel_spi_unlock(as);
570
571 /* prepare the RX dma transfer */
572 sg_init_table(&as->dma.sgrx, 1);
573 if (xfer->rx_buf) {
574 as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
575 } else {
576 as->dma.sgrx.dma_address = as->buffer_dma;
577 if (len > BUFFER_SIZE)
578 len = BUFFER_SIZE;
579 }
580
581 /* prepare the TX dma transfer */
582 sg_init_table(&as->dma.sgtx, 1);
583 if (xfer->tx_buf) {
584 as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
585 } else {
586 as->dma.sgtx.dma_address = as->buffer_dma;
587 if (len > BUFFER_SIZE)
588 len = BUFFER_SIZE;
589 memset(as->buffer, 0, len);
590 }
591
592 sg_dma_len(&as->dma.sgtx) = len;
593 sg_dma_len(&as->dma.sgrx) = len;
594
595 *plen = len;
596
597 if (atmel_spi_dma_slave_config(as, &slave_config,
598 xfer->bits_per_word))
599 goto err_exit;
600
601 /* Send both scatterlists */
602 rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
603 &as->dma.sgrx,
604 1,
605 DMA_FROM_DEVICE,
606 DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
607 NULL);
608 if (!rxdesc)
609 goto err_dma;
610
611 txdesc = txchan->device->device_prep_slave_sg(txchan,
612 &as->dma.sgtx,
613 1,
614 DMA_TO_DEVICE,
615 DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
616 NULL);
617 if (!txdesc)
618 goto err_dma;
619
620 dev_dbg(master->dev.parent,
621 " start dma xfer %p: len %u tx %p/%08x rx %p/%08x\n",
622 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
623 xfer->rx_buf, xfer->rx_dma);
624
625 /* Enable relevant interrupts */
626 spi_writel(as, IER, SPI_BIT(OVRES));
627
628 /* Put the callback on the RX transfer only, that should finish last */
629 rxdesc->callback = dma_callback;
630 rxdesc->callback_param = master;
631
632 /* Submit and fire RX and TX with TX last so we're ready to read! */
633 cookie = rxdesc->tx_submit(rxdesc);
634 if (dma_submit_error(cookie))
635 goto err_dma;
636 cookie = txdesc->tx_submit(txdesc);
637 if (dma_submit_error(cookie))
638 goto err_dma;
639 rxchan->device->device_issue_pending(rxchan);
640 txchan->device->device_issue_pending(txchan);
641
642 /* take back lock */
643 atmel_spi_lock(as);
644 return 0;
645
646 err_dma:
647 spi_writel(as, IDR, SPI_BIT(OVRES));
648 atmel_spi_stop_dma(as);
649 err_exit:
650 atmel_spi_lock(as);
651 return -ENOMEM;
652 }
653
654 static void atmel_spi_next_xfer_data(struct spi_master *master,
655 struct spi_transfer *xfer,
656 dma_addr_t *tx_dma,
657 dma_addr_t *rx_dma,
658 u32 *plen)
659 {
660 struct atmel_spi *as = spi_master_get_devdata(master);
661 u32 len = *plen;
662
663 /* use scratch buffer only when rx or tx data is unspecified */
664 if (xfer->rx_buf)
665 *rx_dma = xfer->rx_dma + xfer->len - *plen;
666 else {
667 *rx_dma = as->buffer_dma;
668 if (len > BUFFER_SIZE)
669 len = BUFFER_SIZE;
670 }
671
672 if (xfer->tx_buf)
673 *tx_dma = xfer->tx_dma + xfer->len - *plen;
674 else {
675 *tx_dma = as->buffer_dma;
676 if (len > BUFFER_SIZE)
677 len = BUFFER_SIZE;
678 memset(as->buffer, 0, len);
679 dma_sync_single_for_device(&as->pdev->dev,
680 as->buffer_dma, len, DMA_TO_DEVICE);
681 }
682
683 *plen = len;
684 }
685
686 /*
687 * Submit next transfer for PDC.
688 * lock is held, spi irq is blocked
689 */
690 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
691 struct spi_message *msg)
692 {
693 struct atmel_spi *as = spi_master_get_devdata(master);
694 struct spi_transfer *xfer;
695 u32 len, remaining;
696 u32 ieval;
697 dma_addr_t tx_dma, rx_dma;
698
699 if (!as->current_transfer)
700 xfer = list_entry(msg->transfers.next,
701 struct spi_transfer, transfer_list);
702 else if (!as->next_transfer)
703 xfer = list_entry(as->current_transfer->transfer_list.next,
704 struct spi_transfer, transfer_list);
705 else
706 xfer = NULL;
707
708 if (xfer) {
709 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
710
711 len = xfer->len;
712 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
713 remaining = xfer->len - len;
714
715 spi_writel(as, RPR, rx_dma);
716 spi_writel(as, TPR, tx_dma);
717
718 if (msg->spi->bits_per_word > 8)
719 len >>= 1;
720 spi_writel(as, RCR, len);
721 spi_writel(as, TCR, len);
722
723 dev_dbg(&msg->spi->dev,
724 " start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
725 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
726 xfer->rx_buf, xfer->rx_dma);
727 } else {
728 xfer = as->next_transfer;
729 remaining = as->next_remaining_bytes;
730 }
731
732 as->current_transfer = xfer;
733 as->current_remaining_bytes = remaining;
734
735 if (remaining > 0)
736 len = remaining;
737 else if (!atmel_spi_xfer_is_last(msg, xfer)
738 && atmel_spi_xfer_can_be_chained(xfer)) {
739 xfer = list_entry(xfer->transfer_list.next,
740 struct spi_transfer, transfer_list);
741 len = xfer->len;
742 } else
743 xfer = NULL;
744
745 as->next_transfer = xfer;
746
747 if (xfer) {
748 u32 total;
749
750 total = len;
751 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
752 as->next_remaining_bytes = total - len;
753
754 spi_writel(as, RNPR, rx_dma);
755 spi_writel(as, TNPR, tx_dma);
756
757 if (msg->spi->bits_per_word > 8)
758 len >>= 1;
759 spi_writel(as, RNCR, len);
760 spi_writel(as, TNCR, len);
761
762 dev_dbg(&msg->spi->dev,
763 " next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
764 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
765 xfer->rx_buf, xfer->rx_dma);
766 ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
767 } else {
768 spi_writel(as, RNCR, 0);
769 spi_writel(as, TNCR, 0);
770 ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
771 }
772
773 /* REVISIT: We're waiting for ENDRX before we start the next
774 * transfer because we need to handle some difficult timing
775 * issues otherwise. If we wait for ENDTX in one transfer and
776 * then starts waiting for ENDRX in the next, it's difficult
777 * to tell the difference between the ENDRX interrupt we're
778 * actually waiting for and the ENDRX interrupt of the
779 * previous transfer.
780 *
781 * It should be doable, though. Just not now...
782 */
783 spi_writel(as, IER, ieval);
784 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
785 }
786
787 /*
788 * Choose way to submit next transfer and start it.
789 * lock is held, spi tasklet is blocked
790 */
791 static void atmel_spi_dma_next_xfer(struct spi_master *master,
792 struct spi_message *msg)
793 {
794 struct atmel_spi *as = spi_master_get_devdata(master);
795 struct spi_transfer *xfer;
796 u32 remaining, len;
797
798 remaining = as->current_remaining_bytes;
799 if (remaining) {
800 xfer = as->current_transfer;
801 len = remaining;
802 } else {
803 if (!as->current_transfer)
804 xfer = list_entry(msg->transfers.next,
805 struct spi_transfer, transfer_list);
806 else
807 xfer = list_entry(
808 as->current_transfer->transfer_list.next,
809 struct spi_transfer, transfer_list);
810
811 as->current_transfer = xfer;
812 len = xfer->len;
813 }
814
815 if (atmel_spi_use_dma(as, xfer)) {
816 u32 total = len;
817 if (!atmel_spi_next_xfer_dma_submit(master, xfer, &len)) {
818 as->current_remaining_bytes = total - len;
819 return;
820 } else {
821 dev_err(&msg->spi->dev, "unable to use DMA, fallback to PIO\n");
822 }
823 }
824
825 /* use PIO if error appened using DMA */
826 atmel_spi_next_xfer_pio(master, xfer);
827 }
828
829 static void atmel_spi_next_message(struct spi_master *master)
830 {
831 struct atmel_spi *as = spi_master_get_devdata(master);
832 struct spi_message *msg;
833 struct spi_device *spi;
834
835 BUG_ON(as->current_transfer);
836
837 msg = list_entry(as->queue.next, struct spi_message, queue);
838 spi = msg->spi;
839
840 dev_dbg(master->dev.parent, "start message %p for %s\n",
841 msg, dev_name(&spi->dev));
842
843 /* select chip if it's not still active */
844 if (as->stay) {
845 if (as->stay != spi) {
846 cs_deactivate(as, as->stay);
847 cs_activate(as, spi);
848 }
849 as->stay = NULL;
850 } else
851 cs_activate(as, spi);
852
853 if (as->use_pdc)
854 atmel_spi_pdc_next_xfer(master, msg);
855 else
856 atmel_spi_dma_next_xfer(master, msg);
857 }
858
859 /*
860 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
861 * - The buffer is either valid for CPU access, else NULL
862 * - If the buffer is valid, so is its DMA address
863 *
864 * This driver manages the dma address unless message->is_dma_mapped.
865 */
866 static int
867 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
868 {
869 struct device *dev = &as->pdev->dev;
870
871 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
872 if (xfer->tx_buf) {
873 /* tx_buf is a const void* where we need a void * for the dma
874 * mapping */
875 void *nonconst_tx = (void *)xfer->tx_buf;
876
877 xfer->tx_dma = dma_map_single(dev,
878 nonconst_tx, xfer->len,
879 DMA_TO_DEVICE);
880 if (dma_mapping_error(dev, xfer->tx_dma))
881 return -ENOMEM;
882 }
883 if (xfer->rx_buf) {
884 xfer->rx_dma = dma_map_single(dev,
885 xfer->rx_buf, xfer->len,
886 DMA_FROM_DEVICE);
887 if (dma_mapping_error(dev, xfer->rx_dma)) {
888 if (xfer->tx_buf)
889 dma_unmap_single(dev,
890 xfer->tx_dma, xfer->len,
891 DMA_TO_DEVICE);
892 return -ENOMEM;
893 }
894 }
895 return 0;
896 }
897
898 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
899 struct spi_transfer *xfer)
900 {
901 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
902 dma_unmap_single(master->dev.parent, xfer->tx_dma,
903 xfer->len, DMA_TO_DEVICE);
904 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
905 dma_unmap_single(master->dev.parent, xfer->rx_dma,
906 xfer->len, DMA_FROM_DEVICE);
907 }
908
909 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
910 {
911 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
912 }
913
914 static void
915 atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
916 struct spi_message *msg, int stay)
917 {
918 if (!stay || as->done_status < 0)
919 cs_deactivate(as, msg->spi);
920 else
921 as->stay = msg->spi;
922
923 list_del(&msg->queue);
924 msg->status = as->done_status;
925
926 dev_dbg(master->dev.parent,
927 "xfer complete: %u bytes transferred\n",
928 msg->actual_length);
929
930 atmel_spi_unlock(as);
931 msg->complete(msg->context);
932 atmel_spi_lock(as);
933
934 as->current_transfer = NULL;
935 as->next_transfer = NULL;
936 as->done_status = 0;
937
938 /* continue if needed */
939 if (list_empty(&as->queue) || as->stopping) {
940 if (as->use_pdc)
941 atmel_spi_disable_pdc_transfer(as);
942 } else {
943 atmel_spi_next_message(master);
944 }
945 }
946
947 /* Called from IRQ
948 * lock is held
949 *
950 * Must update "current_remaining_bytes" to keep track of data
951 * to transfer.
952 */
953 static void
954 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
955 {
956 u8 *txp;
957 u8 *rxp;
958 u16 *txp16;
959 u16 *rxp16;
960 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
961
962 if (xfer->rx_buf) {
963 if (xfer->bits_per_word > 8) {
964 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
965 *rxp16 = spi_readl(as, RDR);
966 } else {
967 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
968 *rxp = spi_readl(as, RDR);
969 }
970 } else {
971 spi_readl(as, RDR);
972 }
973 if (xfer->bits_per_word > 8) {
974 as->current_remaining_bytes -= 2;
975 if (as->current_remaining_bytes < 0)
976 as->current_remaining_bytes = 0;
977 } else {
978 as->current_remaining_bytes--;
979 }
980
981 if (as->current_remaining_bytes) {
982 if (xfer->tx_buf) {
983 if (xfer->bits_per_word > 8) {
984 txp16 = (u16 *)(((u8 *)xfer->tx_buf)
985 + xfer_pos + 2);
986 spi_writel(as, TDR, *txp16);
987 } else {
988 txp = ((u8 *)xfer->tx_buf) + xfer_pos + 1;
989 spi_writel(as, TDR, *txp);
990 }
991 } else {
992 spi_writel(as, TDR, 0);
993 }
994 }
995 }
996
997 /* Tasklet
998 * Called from DMA callback + pio transfer and overrun IRQ.
999 */
1000 static void atmel_spi_tasklet_func(unsigned long data)
1001 {
1002 struct spi_master *master = (struct spi_master *)data;
1003 struct atmel_spi *as = spi_master_get_devdata(master);
1004 struct spi_message *msg;
1005 struct spi_transfer *xfer;
1006
1007 dev_vdbg(master->dev.parent, "atmel_spi_tasklet_func\n");
1008
1009 atmel_spi_lock(as);
1010
1011 xfer = as->current_transfer;
1012
1013 if (xfer == NULL)
1014 /* already been there */
1015 goto tasklet_out;
1016
1017 msg = list_entry(as->queue.next, struct spi_message, queue);
1018
1019 if (as->current_remaining_bytes == 0) {
1020 if (as->done_status < 0) {
1021 /* error happened (overrun) */
1022 if (atmel_spi_use_dma(as, xfer))
1023 atmel_spi_stop_dma(as);
1024 } else {
1025 /* only update length if no error */
1026 msg->actual_length += xfer->len;
1027 }
1028
1029 if (atmel_spi_use_dma(as, xfer))
1030 if (!msg->is_dma_mapped)
1031 atmel_spi_dma_unmap_xfer(master, xfer);
1032
1033 if (xfer->delay_usecs)
1034 udelay(xfer->delay_usecs);
1035
1036 if (atmel_spi_xfer_is_last(msg, xfer) || as->done_status < 0) {
1037 /* report completed (or erroneous) message */
1038 atmel_spi_msg_done(master, as, msg, xfer->cs_change);
1039 } else {
1040 if (xfer->cs_change) {
1041 cs_deactivate(as, msg->spi);
1042 udelay(1);
1043 cs_activate(as, msg->spi);
1044 }
1045
1046 /*
1047 * Not done yet. Submit the next transfer.
1048 *
1049 * FIXME handle protocol options for xfer
1050 */
1051 atmel_spi_dma_next_xfer(master, msg);
1052 }
1053 } else {
1054 /*
1055 * Keep going, we still have data to send in
1056 * the current transfer.
1057 */
1058 atmel_spi_dma_next_xfer(master, msg);
1059 }
1060
1061 tasklet_out:
1062 atmel_spi_unlock(as);
1063 }
1064
1065 /* Interrupt
1066 *
1067 * No need for locking in this Interrupt handler: done_status is the
1068 * only information modified. What we need is the update of this field
1069 * before tasklet runs. This is ensured by using barrier.
1070 */
1071 static irqreturn_t
1072 atmel_spi_pio_interrupt(int irq, void *dev_id)
1073 {
1074 struct spi_master *master = dev_id;
1075 struct atmel_spi *as = spi_master_get_devdata(master);
1076 u32 status, pending, imr;
1077 struct spi_transfer *xfer;
1078 int ret = IRQ_NONE;
1079
1080 imr = spi_readl(as, IMR);
1081 status = spi_readl(as, SR);
1082 pending = status & imr;
1083
1084 if (pending & SPI_BIT(OVRES)) {
1085 ret = IRQ_HANDLED;
1086 spi_writel(as, IDR, SPI_BIT(OVRES));
1087 dev_warn(master->dev.parent, "overrun\n");
1088
1089 /*
1090 * When we get an overrun, we disregard the current
1091 * transfer. Data will not be copied back from any
1092 * bounce buffer and msg->actual_len will not be
1093 * updated with the last xfer.
1094 *
1095 * We will also not process any remaning transfers in
1096 * the message.
1097 *
1098 * All actions are done in tasklet with done_status indication
1099 */
1100 as->done_status = -EIO;
1101 smp_wmb();
1102
1103 /* Clear any overrun happening while cleaning up */
1104 spi_readl(as, SR);
1105
1106 tasklet_schedule(&as->tasklet);
1107
1108 } else if (pending & SPI_BIT(RDRF)) {
1109 atmel_spi_lock(as);
1110
1111 if (as->current_remaining_bytes) {
1112 ret = IRQ_HANDLED;
1113 xfer = as->current_transfer;
1114 atmel_spi_pump_pio_data(as, xfer);
1115 if (!as->current_remaining_bytes) {
1116 /* no more data to xfer, kick tasklet */
1117 spi_writel(as, IDR, pending);
1118 tasklet_schedule(&as->tasklet);
1119 }
1120 }
1121
1122 atmel_spi_unlock(as);
1123 } else {
1124 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1125 ret = IRQ_HANDLED;
1126 spi_writel(as, IDR, pending);
1127 }
1128
1129 return ret;
1130 }
1131
1132 static irqreturn_t
1133 atmel_spi_pdc_interrupt(int irq, void *dev_id)
1134 {
1135 struct spi_master *master = dev_id;
1136 struct atmel_spi *as = spi_master_get_devdata(master);
1137 struct spi_message *msg;
1138 struct spi_transfer *xfer;
1139 u32 status, pending, imr;
1140 int ret = IRQ_NONE;
1141
1142 atmel_spi_lock(as);
1143
1144 xfer = as->current_transfer;
1145 msg = list_entry(as->queue.next, struct spi_message, queue);
1146
1147 imr = spi_readl(as, IMR);
1148 status = spi_readl(as, SR);
1149 pending = status & imr;
1150
1151 if (pending & SPI_BIT(OVRES)) {
1152 int timeout;
1153
1154 ret = IRQ_HANDLED;
1155
1156 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1157 | SPI_BIT(OVRES)));
1158
1159 /*
1160 * When we get an overrun, we disregard the current
1161 * transfer. Data will not be copied back from any
1162 * bounce buffer and msg->actual_len will not be
1163 * updated with the last xfer.
1164 *
1165 * We will also not process any remaning transfers in
1166 * the message.
1167 *
1168 * First, stop the transfer and unmap the DMA buffers.
1169 */
1170 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1171 if (!msg->is_dma_mapped)
1172 atmel_spi_dma_unmap_xfer(master, xfer);
1173
1174 /* REVISIT: udelay in irq is unfriendly */
1175 if (xfer->delay_usecs)
1176 udelay(xfer->delay_usecs);
1177
1178 dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
1179 spi_readl(as, TCR), spi_readl(as, RCR));
1180
1181 /*
1182 * Clean up DMA registers and make sure the data
1183 * registers are empty.
1184 */
1185 spi_writel(as, RNCR, 0);
1186 spi_writel(as, TNCR, 0);
1187 spi_writel(as, RCR, 0);
1188 spi_writel(as, TCR, 0);
1189 for (timeout = 1000; timeout; timeout--)
1190 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1191 break;
1192 if (!timeout)
1193 dev_warn(master->dev.parent,
1194 "timeout waiting for TXEMPTY");
1195 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1196 spi_readl(as, RDR);
1197
1198 /* Clear any overrun happening while cleaning up */
1199 spi_readl(as, SR);
1200
1201 as->done_status = -EIO;
1202 atmel_spi_msg_done(master, as, msg, 0);
1203 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1204 ret = IRQ_HANDLED;
1205
1206 spi_writel(as, IDR, pending);
1207
1208 if (as->current_remaining_bytes == 0) {
1209 msg->actual_length += xfer->len;
1210
1211 if (!msg->is_dma_mapped)
1212 atmel_spi_dma_unmap_xfer(master, xfer);
1213
1214 /* REVISIT: udelay in irq is unfriendly */
1215 if (xfer->delay_usecs)
1216 udelay(xfer->delay_usecs);
1217
1218 if (atmel_spi_xfer_is_last(msg, xfer)) {
1219 /* report completed message */
1220 atmel_spi_msg_done(master, as, msg,
1221 xfer->cs_change);
1222 } else {
1223 if (xfer->cs_change) {
1224 cs_deactivate(as, msg->spi);
1225 udelay(1);
1226 cs_activate(as, msg->spi);
1227 }
1228
1229 /*
1230 * Not done yet. Submit the next transfer.
1231 *
1232 * FIXME handle protocol options for xfer
1233 */
1234 atmel_spi_pdc_next_xfer(master, msg);
1235 }
1236 } else {
1237 /*
1238 * Keep going, we still have data to send in
1239 * the current transfer.
1240 */
1241 atmel_spi_pdc_next_xfer(master, msg);
1242 }
1243 }
1244
1245 atmel_spi_unlock(as);
1246
1247 return ret;
1248 }
1249
1250 static int atmel_spi_setup(struct spi_device *spi)
1251 {
1252 struct atmel_spi *as;
1253 struct atmel_spi_device *asd;
1254 u32 scbr, csr;
1255 unsigned int bits = spi->bits_per_word;
1256 unsigned long bus_hz;
1257 unsigned int npcs_pin;
1258 int ret;
1259
1260 as = spi_master_get_devdata(spi->master);
1261
1262 if (as->stopping)
1263 return -ESHUTDOWN;
1264
1265 if (spi->chip_select > spi->master->num_chipselect) {
1266 dev_dbg(&spi->dev,
1267 "setup: invalid chipselect %u (%u defined)\n",
1268 spi->chip_select, spi->master->num_chipselect);
1269 return -EINVAL;
1270 }
1271
1272 if (bits < 8 || bits > 16) {
1273 dev_dbg(&spi->dev,
1274 "setup: invalid bits_per_word %u (8 to 16)\n",
1275 bits);
1276 return -EINVAL;
1277 }
1278
1279 /* see notes above re chipselect */
1280 if (!atmel_spi_is_v2(as)
1281 && spi->chip_select == 0
1282 && (spi->mode & SPI_CS_HIGH)) {
1283 dev_dbg(&spi->dev, "setup: can't be active-high\n");
1284 return -EINVAL;
1285 }
1286
1287 /* v1 chips start out at half the peripheral bus speed. */
1288 bus_hz = clk_get_rate(as->clk);
1289 if (!atmel_spi_is_v2(as))
1290 bus_hz /= 2;
1291
1292 if (spi->max_speed_hz) {
1293 /*
1294 * Calculate the lowest divider that satisfies the
1295 * constraint, assuming div32/fdiv/mbz == 0.
1296 */
1297 scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
1298
1299 /*
1300 * If the resulting divider doesn't fit into the
1301 * register bitfield, we can't satisfy the constraint.
1302 */
1303 if (scbr >= (1 << SPI_SCBR_SIZE)) {
1304 dev_dbg(&spi->dev,
1305 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
1306 spi->max_speed_hz, scbr, bus_hz/255);
1307 return -EINVAL;
1308 }
1309 } else
1310 /* speed zero means "as slow as possible" */
1311 scbr = 0xff;
1312
1313 csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
1314 if (spi->mode & SPI_CPOL)
1315 csr |= SPI_BIT(CPOL);
1316 if (!(spi->mode & SPI_CPHA))
1317 csr |= SPI_BIT(NCPHA);
1318
1319 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1320 *
1321 * DLYBCT would add delays between words, slowing down transfers.
1322 * It could potentially be useful to cope with DMA bottlenecks, but
1323 * in those cases it's probably best to just use a lower bitrate.
1324 */
1325 csr |= SPI_BF(DLYBS, 0);
1326 csr |= SPI_BF(DLYBCT, 0);
1327
1328 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1329 npcs_pin = (unsigned int)spi->controller_data;
1330
1331 if (gpio_is_valid(spi->cs_gpio))
1332 npcs_pin = spi->cs_gpio;
1333
1334 asd = spi->controller_state;
1335 if (!asd) {
1336 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1337 if (!asd)
1338 return -ENOMEM;
1339
1340 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
1341 if (ret) {
1342 kfree(asd);
1343 return ret;
1344 }
1345
1346 asd->npcs_pin = npcs_pin;
1347 spi->controller_state = asd;
1348 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
1349 } else {
1350 atmel_spi_lock(as);
1351 if (as->stay == spi)
1352 as->stay = NULL;
1353 cs_deactivate(as, spi);
1354 atmel_spi_unlock(as);
1355 }
1356
1357 asd->csr = csr;
1358
1359 dev_dbg(&spi->dev,
1360 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
1361 bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
1362
1363 if (!atmel_spi_is_v2(as))
1364 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1365
1366 return 0;
1367 }
1368
1369 static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
1370 {
1371 struct atmel_spi *as;
1372 struct spi_transfer *xfer;
1373 struct device *controller = spi->master->dev.parent;
1374 u8 bits;
1375 struct atmel_spi_device *asd;
1376
1377 as = spi_master_get_devdata(spi->master);
1378
1379 dev_dbg(controller, "new message %p submitted for %s\n",
1380 msg, dev_name(&spi->dev));
1381
1382 if (unlikely(list_empty(&msg->transfers)))
1383 return -EINVAL;
1384
1385 if (as->stopping)
1386 return -ESHUTDOWN;
1387
1388 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1389 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1390 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1391 return -EINVAL;
1392 }
1393
1394 if (xfer->bits_per_word) {
1395 asd = spi->controller_state;
1396 bits = (asd->csr >> 4) & 0xf;
1397 if (bits != xfer->bits_per_word - 8) {
1398 dev_dbg(&spi->dev, "you can't yet change "
1399 "bits_per_word in transfers\n");
1400 return -ENOPROTOOPT;
1401 }
1402 }
1403
1404 if (xfer->bits_per_word > 8) {
1405 if (xfer->len % 2) {
1406 dev_dbg(&spi->dev, "buffer len should be 16 bits aligned\n");
1407 return -EINVAL;
1408 }
1409 }
1410
1411 /* FIXME implement these protocol options!! */
1412 if (xfer->speed_hz < spi->max_speed_hz) {
1413 dev_dbg(&spi->dev, "can't change speed in transfer\n");
1414 return -ENOPROTOOPT;
1415 }
1416
1417 /*
1418 * DMA map early, for performance (empties dcache ASAP) and
1419 * better fault reporting.
1420 */
1421 if ((!msg->is_dma_mapped) && (atmel_spi_use_dma(as, xfer)
1422 || as->use_pdc)) {
1423 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1424 return -ENOMEM;
1425 }
1426 }
1427
1428 #ifdef VERBOSE
1429 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1430 dev_dbg(controller,
1431 " xfer %p: len %u tx %p/%08x rx %p/%08x\n",
1432 xfer, xfer->len,
1433 xfer->tx_buf, xfer->tx_dma,
1434 xfer->rx_buf, xfer->rx_dma);
1435 }
1436 #endif
1437
1438 msg->status = -EINPROGRESS;
1439 msg->actual_length = 0;
1440
1441 atmel_spi_lock(as);
1442 list_add_tail(&msg->queue, &as->queue);
1443 if (!as->current_transfer)
1444 atmel_spi_next_message(spi->master);
1445 atmel_spi_unlock(as);
1446
1447 return 0;
1448 }
1449
1450 static void atmel_spi_cleanup(struct spi_device *spi)
1451 {
1452 struct atmel_spi *as = spi_master_get_devdata(spi->master);
1453 struct atmel_spi_device *asd = spi->controller_state;
1454 unsigned gpio = (unsigned) spi->controller_data;
1455
1456 if (!asd)
1457 return;
1458
1459 atmel_spi_lock(as);
1460 if (as->stay == spi) {
1461 as->stay = NULL;
1462 cs_deactivate(as, spi);
1463 }
1464 atmel_spi_unlock(as);
1465
1466 spi->controller_state = NULL;
1467 gpio_free(gpio);
1468 kfree(asd);
1469 }
1470
1471 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1472 {
1473 return spi_readl(as, VERSION) & 0x00000fff;
1474 }
1475
1476 static void atmel_get_caps(struct atmel_spi *as)
1477 {
1478 unsigned int version;
1479
1480 version = atmel_get_version(as);
1481 dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1482
1483 as->caps.is_spi2 = version > 0x121;
1484 as->caps.has_wdrbt = version >= 0x210;
1485 as->caps.has_dma_support = version >= 0x212;
1486 }
1487
1488 /*-------------------------------------------------------------------------*/
1489
1490 static int atmel_spi_probe(struct platform_device *pdev)
1491 {
1492 struct resource *regs;
1493 int irq;
1494 struct clk *clk;
1495 int ret;
1496 struct spi_master *master;
1497 struct atmel_spi *as;
1498
1499 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1500 if (!regs)
1501 return -ENXIO;
1502
1503 irq = platform_get_irq(pdev, 0);
1504 if (irq < 0)
1505 return irq;
1506
1507 clk = clk_get(&pdev->dev, "spi_clk");
1508 if (IS_ERR(clk))
1509 return PTR_ERR(clk);
1510
1511 /* setup spi core then atmel-specific driver state */
1512 ret = -ENOMEM;
1513 master = spi_alloc_master(&pdev->dev, sizeof *as);
1514 if (!master)
1515 goto out_free;
1516
1517 /* the spi->mode bits understood by this driver: */
1518 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1519
1520 master->dev.of_node = pdev->dev.of_node;
1521 master->bus_num = pdev->id;
1522 master->num_chipselect = master->dev.of_node ? 0 : 4;
1523 master->setup = atmel_spi_setup;
1524 master->transfer = atmel_spi_transfer;
1525 master->cleanup = atmel_spi_cleanup;
1526 platform_set_drvdata(pdev, master);
1527
1528 as = spi_master_get_devdata(master);
1529
1530 /*
1531 * Scratch buffer is used for throwaway rx and tx data.
1532 * It's coherent to minimize dcache pollution.
1533 */
1534 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
1535 &as->buffer_dma, GFP_KERNEL);
1536 if (!as->buffer)
1537 goto out_free;
1538
1539 spin_lock_init(&as->lock);
1540 INIT_LIST_HEAD(&as->queue);
1541
1542 as->pdev = pdev;
1543 as->regs = ioremap(regs->start, resource_size(regs));
1544 if (!as->regs)
1545 goto out_free_buffer;
1546 as->phybase = regs->start;
1547 as->irq = irq;
1548 as->clk = clk;
1549
1550 atmel_get_caps(as);
1551
1552 as->use_dma = false;
1553 as->use_pdc = false;
1554 if (as->caps.has_dma_support) {
1555 if (atmel_spi_configure_dma(as) == 0)
1556 as->use_dma = true;
1557 } else {
1558 as->use_pdc = true;
1559 }
1560
1561 if (as->caps.has_dma_support && !as->use_dma)
1562 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1563
1564 if (as->use_pdc) {
1565 ret = request_irq(irq, atmel_spi_pdc_interrupt, 0,
1566 dev_name(&pdev->dev), master);
1567 } else {
1568 tasklet_init(&as->tasklet, atmel_spi_tasklet_func,
1569 (unsigned long)master);
1570
1571 ret = request_irq(irq, atmel_spi_pio_interrupt, 0,
1572 dev_name(&pdev->dev), master);
1573 }
1574 if (ret)
1575 goto out_unmap_regs;
1576
1577 /* Initialize the hardware */
1578 clk_enable(clk);
1579 spi_writel(as, CR, SPI_BIT(SWRST));
1580 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1581 if (as->caps.has_wdrbt) {
1582 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1583 | SPI_BIT(MSTR));
1584 } else {
1585 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1586 }
1587
1588 if (as->use_pdc)
1589 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1590 spi_writel(as, CR, SPI_BIT(SPIEN));
1591
1592 /* go! */
1593 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1594 (unsigned long)regs->start, irq);
1595
1596 ret = spi_register_master(master);
1597 if (ret)
1598 goto out_free_dma;
1599
1600 return 0;
1601
1602 out_free_dma:
1603 if (as->use_dma)
1604 atmel_spi_release_dma(as);
1605
1606 spi_writel(as, CR, SPI_BIT(SWRST));
1607 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1608 clk_disable(clk);
1609 free_irq(irq, master);
1610 out_unmap_regs:
1611 iounmap(as->regs);
1612 out_free_buffer:
1613 if (!as->use_pdc)
1614 tasklet_kill(&as->tasklet);
1615 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1616 as->buffer_dma);
1617 out_free:
1618 clk_put(clk);
1619 spi_master_put(master);
1620 return ret;
1621 }
1622
1623 static int atmel_spi_remove(struct platform_device *pdev)
1624 {
1625 struct spi_master *master = platform_get_drvdata(pdev);
1626 struct atmel_spi *as = spi_master_get_devdata(master);
1627 struct spi_message *msg;
1628 struct spi_transfer *xfer;
1629
1630 /* reset the hardware and block queue progress */
1631 spin_lock_irq(&as->lock);
1632 as->stopping = 1;
1633 if (as->use_dma) {
1634 atmel_spi_stop_dma(as);
1635 atmel_spi_release_dma(as);
1636 }
1637
1638 spi_writel(as, CR, SPI_BIT(SWRST));
1639 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1640 spi_readl(as, SR);
1641 spin_unlock_irq(&as->lock);
1642
1643 /* Terminate remaining queued transfers */
1644 list_for_each_entry(msg, &as->queue, queue) {
1645 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1646 if (!msg->is_dma_mapped
1647 && (atmel_spi_use_dma(as, xfer)
1648 || as->use_pdc))
1649 atmel_spi_dma_unmap_xfer(master, xfer);
1650 }
1651 msg->status = -ESHUTDOWN;
1652 msg->complete(msg->context);
1653 }
1654
1655 if (!as->use_pdc)
1656 tasklet_kill(&as->tasklet);
1657 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1658 as->buffer_dma);
1659
1660 clk_disable(as->clk);
1661 clk_put(as->clk);
1662 free_irq(as->irq, master);
1663 iounmap(as->regs);
1664
1665 spi_unregister_master(master);
1666
1667 return 0;
1668 }
1669
1670 #ifdef CONFIG_PM
1671
1672 static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
1673 {
1674 struct spi_master *master = platform_get_drvdata(pdev);
1675 struct atmel_spi *as = spi_master_get_devdata(master);
1676
1677 clk_disable(as->clk);
1678 return 0;
1679 }
1680
1681 static int atmel_spi_resume(struct platform_device *pdev)
1682 {
1683 struct spi_master *master = platform_get_drvdata(pdev);
1684 struct atmel_spi *as = spi_master_get_devdata(master);
1685
1686 clk_enable(as->clk);
1687 return 0;
1688 }
1689
1690 #else
1691 #define atmel_spi_suspend NULL
1692 #define atmel_spi_resume NULL
1693 #endif
1694
1695 #if defined(CONFIG_OF)
1696 static const struct of_device_id atmel_spi_dt_ids[] = {
1697 { .compatible = "atmel,at91rm9200-spi" },
1698 { /* sentinel */ }
1699 };
1700
1701 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1702 #endif
1703
1704 static struct platform_driver atmel_spi_driver = {
1705 .driver = {
1706 .name = "atmel_spi",
1707 .owner = THIS_MODULE,
1708 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1709 },
1710 .suspend = atmel_spi_suspend,
1711 .resume = atmel_spi_resume,
1712 .probe = atmel_spi_probe,
1713 .remove = atmel_spi_remove,
1714 };
1715 module_platform_driver(atmel_spi_driver);
1716
1717 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1718 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1719 MODULE_LICENSE("GPL");
1720 MODULE_ALIAS("platform:atmel_spi");
kernel source for telekom puls (alcatel/mediatek)