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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / pci / atiixp.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for ATI IXP 150/200/250/300 AC97 controllers
3 *
4 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
1da177e4
LT		 22#include <asm/io.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/pci.h>
27#include <linux/slab.h>
65a77217 28#include <linux/module.h>
62932df8 29#include <linux/mutex.h>
1da177e4
LT		 30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/info.h>
34#include <sound/ac97_codec.h>
35#include <sound/initval.h>
36
37MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
38MODULE_DESCRIPTION("ATI IXP AC97 controller");
39MODULE_LICENSE("GPL");
f4446ea0 40MODULE_SUPPORTED_DEVICE("{{ATI,IXP150/200/250/300/400/600}}");
1da177e4 41
b7fe4622
CL		 42static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
43static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
44static int ac97_clock = 48000;
45static char *ac97_quirk;
a67ff6a5 46static bool spdif_aclink = 1;
14e1d357 47static int ac97_codec = -1;
b7fe4622
CL		 48
49module_param(index, int, 0444);
1da177e4 50MODULE_PARM_DESC(index, "Index value for ATI IXP controller.");
b7fe4622 51module_param(id, charp, 0444);
1da177e4 52MODULE_PARM_DESC(id, "ID string for ATI IXP controller.");
b7fe4622 53module_param(ac97_clock, int, 0444);
1da177e4 54MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
b7fe4622 55module_param(ac97_quirk, charp, 0444);
1da177e4 56MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
14e1d357
DC		 57module_param(ac97_codec, int, 0444);
58MODULE_PARM_DESC(ac97_codec, "Specify codec instead of probing.");
b7fe4622 59module_param(spdif_aclink, bool, 0444);
1da177e4
LT		 60MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
61
2b3e584b 62/* just for backward compatibility */
a67ff6a5 63static bool enable;
698444f3 64module_param(enable, bool, 0444);
2b3e584b 65
1da177e4
LT		 66
67/*
68 */
69
70#define ATI_REG_ISR 0x00 /* interrupt source */
71#define ATI_REG_ISR_IN_XRUN (1U<<0)
72#define ATI_REG_ISR_IN_STATUS (1U<<1)
73#define ATI_REG_ISR_OUT_XRUN (1U<<2)
74#define ATI_REG_ISR_OUT_STATUS (1U<<3)
75#define ATI_REG_ISR_SPDF_XRUN (1U<<4)
76#define ATI_REG_ISR_SPDF_STATUS (1U<<5)
77#define ATI_REG_ISR_PHYS_INTR (1U<<8)
78#define ATI_REG_ISR_PHYS_MISMATCH (1U<<9)
79#define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10)
80#define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11)
81#define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12)
82#define ATI_REG_ISR_NEW_FRAME (1U<<13)
83
84#define ATI_REG_IER 0x04 /* interrupt enable */
85#define ATI_REG_IER_IN_XRUN_EN (1U<<0)
86#define ATI_REG_IER_IO_STATUS_EN (1U<<1)
87#define ATI_REG_IER_OUT_XRUN_EN (1U<<2)
88#define ATI_REG_IER_OUT_XRUN_COND (1U<<3)
89#define ATI_REG_IER_SPDF_XRUN_EN (1U<<4)
90#define ATI_REG_IER_SPDF_STATUS_EN (1U<<5)
91#define ATI_REG_IER_PHYS_INTR_EN (1U<<8)
92#define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9)
93#define ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
94#define ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
95#define ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
96#define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */
97#define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */
98
99#define ATI_REG_CMD 0x08 /* command */
100#define ATI_REG_CMD_POWERDOWN (1U<<0)
101#define ATI_REG_CMD_RECEIVE_EN (1U<<1)
102#define ATI_REG_CMD_SEND_EN (1U<<2)
103#define ATI_REG_CMD_STATUS_MEM (1U<<3)
104#define ATI_REG_CMD_SPDF_OUT_EN (1U<<4)
105#define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5)
106#define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6)
107#define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6
108#define ATI_REG_CMD_IN_DMA_EN (1U<<8)
109#define ATI_REG_CMD_OUT_DMA_EN (1U<<9)
110#define ATI_REG_CMD_SPDF_DMA_EN (1U<<10)
111#define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11)
112#define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12)
113#define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12)
114#define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12)
115#define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12)
116#define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12)
117#define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16)
118#define ATI_REG_CMD_AUDIO_PRESENT (1U<<20)
119#define ATI_REG_CMD_INTERLEAVE_IN (1U<<21)
120#define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22)
121#define ATI_REG_CMD_LOOPBACK_EN (1U<<23)
122#define ATI_REG_CMD_PACKED_DIS (1U<<24)
123#define ATI_REG_CMD_BURST_EN (1U<<25)
124#define ATI_REG_CMD_PANIC_EN (1U<<26)
125#define ATI_REG_CMD_MODEM_PRESENT (1U<<27)
126#define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28)
127#define ATI_REG_CMD_AC_SOFT_RESET (1U<<29)
128#define ATI_REG_CMD_AC_SYNC (1U<<30)
129#define ATI_REG_CMD_AC_RESET (1U<<31)
130
131#define ATI_REG_PHYS_OUT_ADDR 0x0c
132#define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
133#define ATI_REG_PHYS_OUT_RW (1U<<2)
134#define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8)
135#define ATI_REG_PHYS_OUT_ADDR_SHIFT 9
136#define ATI_REG_PHYS_OUT_DATA_SHIFT 16
137
138#define ATI_REG_PHYS_IN_ADDR 0x10
139#define ATI_REG_PHYS_IN_READ_FLAG (1U<<8)
140#define ATI_REG_PHYS_IN_ADDR_SHIFT 9
141#define ATI_REG_PHYS_IN_DATA_SHIFT 16
142
143#define ATI_REG_SLOTREQ 0x14
144
145#define ATI_REG_COUNTER 0x18
146#define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
147#define ATI_REG_COUNTER_BITCLOCK (31U<<8)
148
149#define ATI_REG_IN_FIFO_THRESHOLD 0x1c
150
151#define ATI_REG_IN_DMA_LINKPTR 0x20
152#define ATI_REG_IN_DMA_DT_START 0x24 /* RO */
153#define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */
154#define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */
155#define ATI_REG_IN_DMA_DT_SIZE 0x30
156
157#define ATI_REG_OUT_DMA_SLOT 0x34
158#define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3))
159#define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff
160#define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800
161#define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11
162
163#define ATI_REG_OUT_DMA_LINKPTR 0x38
164#define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */
165#define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */
166#define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */
167#define ATI_REG_OUT_DMA_DT_SIZE 0x48
168
169#define ATI_REG_SPDF_CMD 0x4c
170#define ATI_REG_SPDF_CMD_LFSR (1U<<4)
171#define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5)
172#define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */
173
174#define ATI_REG_SPDF_DMA_LINKPTR 0x50
175#define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */
176#define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */
177#define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */
178#define ATI_REG_SPDF_DMA_DT_SIZE 0x60
179
180#define ATI_REG_MODEM_MIRROR 0x7c
181#define ATI_REG_AUDIO_MIRROR 0x80
182
183#define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */
184#define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
185
186#define ATI_REG_FIFO_FLUSH 0x88
187#define ATI_REG_FIFO_OUT_FLUSH (1U<<0)
188#define ATI_REG_FIFO_IN_FLUSH (1U<<1)
189
190/* LINKPTR */
191#define ATI_REG_LINKPTR_EN (1U<<0)
192
193/* [INT|OUT|SPDIF]_DMA_DT_SIZE */
194#define ATI_REG_DMA_DT_SIZE (0xffffU<<0)
195#define ATI_REG_DMA_FIFO_USED (0x1fU<<16)
196#define ATI_REG_DMA_FIFO_FREE (0x1fU<<21)
197#define ATI_REG_DMA_STATE (7U<<26)
198
199
200#define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */
201
202
74ee4ff1 203struct atiixp;
1da177e4
LT		 204
205/*
206 * DMA packate descriptor
207 */
208
74ee4ff1 209struct atiixp_dma_desc {
1da177e4
LT		 210 u32 addr; /* DMA buffer address */
211 u16 status; /* status bits */
212 u16 size; /* size of the packet in dwords */
213 u32 next; /* address of the next packet descriptor */
74ee4ff1 214};
1da177e4
LT		 215
216/*
217 * stream enum
218 */
219enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */
220enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */
221enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */
222
223#define NUM_ATI_CODECS 3
224
225
226/*
227 * constants and callbacks for each DMA type
228 */
74ee4ff1 229struct atiixp_dma_ops {
1da177e4
LT		 230 int type; /* ATI_DMA_XXX */
231 unsigned int llp_offset; /* LINKPTR offset */
232 unsigned int dt_cur; /* DT_CUR offset */
74ee4ff1
TI		 233 /* called from open callback */
234 void (*enable_dma)(struct atiixp *chip, int on);
235 /* called from trigger (START/STOP) */
236 void (*enable_transfer)(struct atiixp *chip, int on);
237 /* called from trigger (STOP only) */
238 void (*flush_dma)(struct atiixp *chip);
1da177e4
LT		 239};
240
241/*
242 * DMA stream
243 */
74ee4ff1
TI		 244struct atiixp_dma {
245 const struct atiixp_dma_ops *ops;
1da177e4 246 struct snd_dma_buffer desc_buf;
74ee4ff1 247 struct snd_pcm_substream *substream; /* assigned PCM substream */
1da177e4
LT		 248 unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */
249 unsigned int period_bytes, periods;
250 int opened;
251 int running;
41e4845c 252 int suspended;
1da177e4
LT		 253 int pcm_open_flag;
254 int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */
255 unsigned int saved_curptr;
256};
257
258/*
259 * ATI IXP chip
260 */
74ee4ff1
TI		 261struct atiixp {
262 struct snd_card *card;
1da177e4
LT		 263 struct pci_dev *pci;
264
265 unsigned long addr;
266 void __iomem *remap_addr;
267 int irq;
268
74ee4ff1
TI		 269 struct snd_ac97_bus *ac97_bus;
270 struct snd_ac97 *ac97[NUM_ATI_CODECS];
1da177e4
LT		 271
272 spinlock_t reg_lock;
273
74ee4ff1 274 struct atiixp_dma dmas[NUM_ATI_DMAS];
1da177e4 275 struct ac97_pcm *pcms[NUM_ATI_PCMS];
74ee4ff1 276 struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS];
1da177e4
LT		 277
278 int max_channels; /* max. channels for PCM out */
279
280 unsigned int codec_not_ready_bits; /* for codec detection */
281
282 int spdif_over_aclink; /* passed from the module option */
62932df8 283 struct mutex open_mutex; /* playback open mutex */
1da177e4
LT		 284};
285
286
287/*
288 */
cebe41d4 289static DEFINE_PCI_DEVICE_TABLE(snd_atiixp_ids) = {
28d27aae
JP		 290 { PCI_VDEVICE(ATI, 0x4341), 0 }, /* SB200 */
291 { PCI_VDEVICE(ATI, 0x4361), 0 }, /* SB300 */
292 { PCI_VDEVICE(ATI, 0x4370), 0 }, /* SB400 */
293 { PCI_VDEVICE(ATI, 0x4382), 0 }, /* SB600 */
1da177e4
LT		 294 { 0, }
295};
296
297MODULE_DEVICE_TABLE(pci, snd_atiixp_ids);
298
e23e7a14 299static struct snd_pci_quirk atiixp_quirks[] = {
dfb12eeb 300 SND_PCI_QUIRK(0x105b, 0x0c81, "Foxconn RC4107MA-RS2", 0),
f41bea84
TI		 301 SND_PCI_QUIRK(0x15bd, 0x3100, "DFI RS482", 0),
302 { } /* terminator */
14e1d357 303};
1da177e4
LT		 304
305/*
306 * lowlevel functions
307 */
308
309/*
310 * update the bits of the given register.
311 * return 1 if the bits changed.
312 */
74ee4ff1 313static int snd_atiixp_update_bits(struct atiixp *chip, unsigned int reg,
1da177e4
LT		 314 unsigned int mask, unsigned int value)
315{
316 void __iomem *addr = chip->remap_addr + reg;
317 unsigned int data, old_data;
318 old_data = data = readl(addr);
319 data &= ~mask;
320 data |= value;
321 if (old_data == data)
322 return 0;
323 writel(data, addr);
324 return 1;
325}
326
327/*
328 * macros for easy use
329 */
330#define atiixp_write(chip,reg,value) \
331 writel(value, chip->remap_addr + ATI_REG_##reg)
332#define atiixp_read(chip,reg) \
333 readl(chip->remap_addr + ATI_REG_##reg)
334#define atiixp_update(chip,reg,mask,val) \
335 snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
336
1da177e4
LT		 337/*
338 * handling DMA packets
339 *
340 * we allocate a linear buffer for the DMA, and split it to each packet.
341 * in a future version, a scatter-gather buffer should be implemented.
342 */
343
344#define ATI_DESC_LIST_SIZE \
74ee4ff1 345 PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc))
1da177e4
LT		 346
347/*
348 * build packets ring for the given buffer size.
349 *
350 * IXP handles the buffer descriptors, which are connected as a linked
351 * list. although we can change the list dynamically, in this version,
352 * a static RING of buffer descriptors is used.
353 *
354 * the ring is built in this function, and is set up to the hardware.
355 */
74ee4ff1
TI		 356static int atiixp_build_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
357 struct snd_pcm_substream *substream,
358 unsigned int periods,
359 unsigned int period_bytes)
1da177e4
LT		 360{
361 unsigned int i;
362 u32 addr, desc_addr;
363 unsigned long flags;
364
365 if (periods > ATI_MAX_DESCRIPTORS)
366 return -ENOMEM;
367
368 if (dma->desc_buf.area == NULL) {
74ee4ff1
TI		 369 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
370 snd_dma_pci_data(chip->pci),
371 ATI_DESC_LIST_SIZE,
372 &dma->desc_buf) < 0)
1da177e4
LT		 373 return -ENOMEM;
374 dma->period_bytes = dma->periods = 0; /* clear */
375 }
376
377 if (dma->periods == periods && dma->period_bytes == period_bytes)
378 return 0;
379
380 /* reset DMA before changing the descriptor table */
381 spin_lock_irqsave(&chip->reg_lock, flags);
382 writel(0, chip->remap_addr + dma->ops->llp_offset);
383 dma->ops->enable_dma(chip, 0);
384 dma->ops->enable_dma(chip, 1);
385 spin_unlock_irqrestore(&chip->reg_lock, flags);
386
387 /* fill the entries */
388 addr = (u32)substream->runtime->dma_addr;
389 desc_addr = (u32)dma->desc_buf.addr;
390 for (i = 0; i < periods; i++) {
74ee4ff1
TI		 391 struct atiixp_dma_desc *desc;
392 desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i];
1da177e4
LT		 393 desc->addr = cpu_to_le32(addr);
394 desc->status = 0;
395 desc->size = period_bytes >> 2; /* in dwords */
74ee4ff1 396 desc_addr += sizeof(struct atiixp_dma_desc);
1da177e4
LT		 397 if (i == periods - 1)
398 desc->next = cpu_to_le32((u32)dma->desc_buf.addr);
399 else
400 desc->next = cpu_to_le32(desc_addr);
401 addr += period_bytes;
402 }
403
404 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
405 chip->remap_addr + dma->ops->llp_offset);
406
407 dma->period_bytes = period_bytes;
408 dma->periods = periods;
409
410 return 0;
411}
412
413/*
414 * remove the ring buffer and release it if assigned
415 */
74ee4ff1
TI		 416static void atiixp_clear_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
417 struct snd_pcm_substream *substream)
1da177e4
LT		 418{
419 if (dma->desc_buf.area) {
420 writel(0, chip->remap_addr + dma->ops->llp_offset);
421 snd_dma_free_pages(&dma->desc_buf);
422 dma->desc_buf.area = NULL;
423 }
424}
425
426/*
427 * AC97 interface
428 */
74ee4ff1 429static int snd_atiixp_acquire_codec(struct atiixp *chip)
1da177e4
LT		 430{
431 int timeout = 1000;
432
433 while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) {
434 if (! timeout--) {
435 snd_printk(KERN_WARNING "atiixp: codec acquire timeout\n");
436 return -EBUSY;
437 }
438 udelay(1);
439 }
440 return 0;
441}
442
74ee4ff1 443static unsigned short snd_atiixp_codec_read(struct atiixp *chip, unsigned short codec, unsigned short reg)
1da177e4
LT		 444{
445 unsigned int data;
446 int timeout;
447
448 if (snd_atiixp_acquire_codec(chip) < 0)
449 return 0xffff;
450 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
451 ATI_REG_PHYS_OUT_ADDR_EN |
452 ATI_REG_PHYS_OUT_RW |
453 codec;
454 atiixp_write(chip, PHYS_OUT_ADDR, data);
455 if (snd_atiixp_acquire_codec(chip) < 0)
456 return 0xffff;
457 timeout = 1000;
458 do {
459 data = atiixp_read(chip, PHYS_IN_ADDR);
460 if (data & ATI_REG_PHYS_IN_READ_FLAG)
461 return data >> ATI_REG_PHYS_IN_DATA_SHIFT;
462 udelay(1);
463 } while (--timeout);
464 /* time out may happen during reset */
465 if (reg < 0x7c)
466 snd_printk(KERN_WARNING "atiixp: codec read timeout (reg %x)\n", reg);
467 return 0xffff;
468}
469
470
74ee4ff1
TI		 471static void snd_atiixp_codec_write(struct atiixp *chip, unsigned short codec,
472 unsigned short reg, unsigned short val)
1da177e4
LT		 473{
474 unsigned int data;
475
476 if (snd_atiixp_acquire_codec(chip) < 0)
477 return;
478 data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) |
479 ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
480 ATI_REG_PHYS_OUT_ADDR_EN | codec;
481 atiixp_write(chip, PHYS_OUT_ADDR, data);
482}
483
484
74ee4ff1
TI		 485static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97,
486 unsigned short reg)
1da177e4 487{
74ee4ff1 488 struct atiixp *chip = ac97->private_data;
1da177e4
LT		 489 return snd_atiixp_codec_read(chip, ac97->num, reg);
490
491}
492
74ee4ff1
TI		 493static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
494 unsigned short val)
1da177e4 495{
74ee4ff1 496 struct atiixp *chip = ac97->private_data;
1da177e4
LT		 497 snd_atiixp_codec_write(chip, ac97->num, reg, val);
498}
499
500/*
501 * reset AC link
502 */
74ee4ff1 503static int snd_atiixp_aclink_reset(struct atiixp *chip)
1da177e4
LT		 504{
505 int timeout;
506
507 /* reset powerdoewn */
508 if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0))
509 udelay(10);
510
511 /* perform a software reset */
512 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET);
513 atiixp_read(chip, CMD);
514 udelay(10);
515 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0);
516
517 timeout = 10;
518 while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) {
519 /* do a hard reset */
520 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
521 ATI_REG_CMD_AC_SYNC);
522 atiixp_read(chip, CMD);
74ee4ff1 523 mdelay(1);
1da177e4 524 atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
7e79443c 525 if (!--timeout) {
1da177e4
LT		 526 snd_printk(KERN_ERR "atiixp: codec reset timeout\n");
527 break;
528 }
529 }
530
531 /* deassert RESET and assert SYNC to make sure */
532 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
533 ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET);
534
535 return 0;
536}
537
c7561cd8 538#ifdef CONFIG_PM_SLEEP
74ee4ff1 539static int snd_atiixp_aclink_down(struct atiixp *chip)
1da177e4
LT		 540{
541 // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */
542 // return -EBUSY;
543 atiixp_update(chip, CMD,
544 ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET,
545 ATI_REG_CMD_POWERDOWN);
546 return 0;
547}
548#endif
549
550/*
551 * auto-detection of codecs
552 *
553 * the IXP chip can generate interrupts for the non-existing codecs.
554 * NEW_FRAME interrupt is used to make sure that the interrupt is generated
555 * even if all three codecs are connected.
556 */
557
558#define ALL_CODEC_NOT_READY \
559 (ATI_REG_ISR_CODEC0_NOT_READY |\
560 ATI_REG_ISR_CODEC1_NOT_READY |\
561 ATI_REG_ISR_CODEC2_NOT_READY)
562#define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME)
563
e23e7a14 564static int ac97_probing_bugs(struct pci_dev *pci)
14e1d357 565{
f41bea84
TI		 566 const struct snd_pci_quirk *q;
567
568 q = snd_pci_quirk_lookup(pci, atiixp_quirks);
569 if (q) {
86b27237
TI		 570 snd_printdd(KERN_INFO
571 "Atiixp quirk for %s. Forcing codec %d\n",
572 snd_pci_quirk_name(q), q->value);
f41bea84 573 return q->value;
14e1d357
DC		 574 }
575 /* this hardware doesn't need workarounds. Probe for codec */
576 return -1;
577}
578
e23e7a14 579static int snd_atiixp_codec_detect(struct atiixp *chip)
1da177e4
LT		 580{
581 int timeout;
582
583 chip->codec_not_ready_bits = 0;
14e1d357
DC		 584 if (ac97_codec == -1)
585 ac97_codec = ac97_probing_bugs(chip->pci);
586 if (ac97_codec >= 0) {
587 chip->codec_not_ready_bits |=
588 CODEC_CHECK_BITS ^ (1 << (ac97_codec + 10));
589 return 0;
590 }
591
1da177e4
LT		 592 atiixp_write(chip, IER, CODEC_CHECK_BITS);
593 /* wait for the interrupts */
bfdcbace 594 timeout = 50;
1da177e4 595 while (timeout-- > 0) {
74ee4ff1 596 mdelay(1);
1da177e4
LT		 597 if (chip->codec_not_ready_bits)
598 break;
599 }
600 atiixp_write(chip, IER, 0); /* disable irqs */
601
602 if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) {
603 snd_printk(KERN_ERR "atiixp: no codec detected!\n");
604 return -ENXIO;
605 }
606 return 0;
607}
608
609
610/*
611 * enable DMA and irqs
612 */
74ee4ff1 613static int snd_atiixp_chip_start(struct atiixp *chip)
1da177e4
LT		 614{
615 unsigned int reg;
616
617 /* set up spdif, enable burst mode */
618 reg = atiixp_read(chip, CMD);
619 reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT;
620 reg |= ATI_REG_CMD_BURST_EN;
621 atiixp_write(chip, CMD, reg);
622
623 reg = atiixp_read(chip, SPDF_CMD);
624 reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH);
625 atiixp_write(chip, SPDF_CMD, reg);
626
627 /* clear all interrupt source */
628 atiixp_write(chip, ISR, 0xffffffff);
629 /* enable irqs */
630 atiixp_write(chip, IER,
631 ATI_REG_IER_IO_STATUS_EN |
632 ATI_REG_IER_IN_XRUN_EN |
633 ATI_REG_IER_OUT_XRUN_EN |
634 ATI_REG_IER_SPDF_XRUN_EN |
635 ATI_REG_IER_SPDF_STATUS_EN);
636 return 0;
637}
638
639
640/*
641 * disable DMA and IRQs
642 */
74ee4ff1 643static int snd_atiixp_chip_stop(struct atiixp *chip)
1da177e4
LT		 644{
645 /* clear interrupt source */
646 atiixp_write(chip, ISR, atiixp_read(chip, ISR));
647 /* disable irqs */
648 atiixp_write(chip, IER, 0);
649 return 0;
650}
651
652
653/*
654 * PCM section
655 */
656
657/*
658 * pointer callback simplly reads XXX_DMA_DT_CUR register as the current
659 * position. when SG-buffer is implemented, the offset must be calculated
660 * correctly...
661 */
74ee4ff1 662static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream)
1da177e4 663{
74ee4ff1
TI		 664 struct atiixp *chip = snd_pcm_substream_chip(substream);
665 struct snd_pcm_runtime *runtime = substream->runtime;
666 struct atiixp_dma *dma = runtime->private_data;
1da177e4
LT		 667 unsigned int curptr;
668 int timeout = 1000;
669
670 while (timeout--) {
671 curptr = readl(chip->remap_addr + dma->ops->dt_cur);
672 if (curptr < dma->buf_addr)
673 continue;
674 curptr -= dma->buf_addr;
675 if (curptr >= dma->buf_bytes)
676 continue;
677 return bytes_to_frames(runtime, curptr);
678 }
679 snd_printd("atiixp: invalid DMA pointer read 0x%x (buf=%x)\n",
680 readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr);
681 return 0;
682}
683
684/*
685 * XRUN detected, and stop the PCM substream
686 */
74ee4ff1 687static void snd_atiixp_xrun_dma(struct atiixp *chip, struct atiixp_dma *dma)
1da177e4
LT		 688{
689 if (! dma->substream || ! dma->running)
690 return;
691 snd_printdd("atiixp: XRUN detected (DMA %d)\n", dma->ops->type);
8268d1c7 692 snd_pcm_stream_lock(dma->substream);
1da177e4 693 snd_pcm_stop(dma->substream, SNDRV_PCM_STATE_XRUN);
8268d1c7 694 snd_pcm_stream_unlock(dma->substream);
1da177e4
LT		 695}
696
697/*
698 * the period ack. update the substream.
699 */
74ee4ff1 700static void snd_atiixp_update_dma(struct atiixp *chip, struct atiixp_dma *dma)
1da177e4
LT		 701{
702 if (! dma->substream || ! dma->running)
703 return;
704 snd_pcm_period_elapsed(dma->substream);
705}
706
707/* set BUS_BUSY interrupt bit if any DMA is running */
708/* call with spinlock held */
74ee4ff1 709static void snd_atiixp_check_bus_busy(struct atiixp *chip)
1da177e4
LT		 710{
711 unsigned int bus_busy;
712 if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN |
713 ATI_REG_CMD_RECEIVE_EN |
714 ATI_REG_CMD_SPDF_OUT_EN))
715 bus_busy = ATI_REG_IER_SET_BUS_BUSY;
716 else
717 bus_busy = 0;
718 atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy);
719}
720
721/* common trigger callback
722 * calling the lowlevel callbacks in it
723 */
74ee4ff1 724static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 725{
74ee4ff1
TI		 726 struct atiixp *chip = snd_pcm_substream_chip(substream);
727 struct atiixp_dma *dma = substream->runtime->private_data;
1da177e4
LT		 728 int err = 0;
729
da3cec35
TI		 730 if (snd_BUG_ON(!dma->ops->enable_transfer ||
731 !dma->ops->flush_dma))
732 return -EINVAL;
1da177e4
LT		 733
734 spin_lock(&chip->reg_lock);
735 switch (cmd) {
736 case SNDRV_PCM_TRIGGER_START:
41e4845c
JK		 737 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
738 case SNDRV_PCM_TRIGGER_RESUME:
1da177e4
LT		 739 dma->ops->enable_transfer(chip, 1);
740 dma->running = 1;
41e4845c 741 dma->suspended = 0;
1da177e4
LT		 742 break;
743 case SNDRV_PCM_TRIGGER_STOP:
41e4845c
JK		 744 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
745 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 746 dma->ops->enable_transfer(chip, 0);
747 dma->running = 0;
41e4845c 748 dma->suspended = cmd == SNDRV_PCM_TRIGGER_SUSPEND;
1da177e4
LT		 749 break;
750 default:
751 err = -EINVAL;
752 break;
753 }
754 if (! err) {
755 snd_atiixp_check_bus_busy(chip);
756 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
757 dma->ops->flush_dma(chip);
758 snd_atiixp_check_bus_busy(chip);
759 }
760 }
761 spin_unlock(&chip->reg_lock);
762 return err;
763}
764
765
766/*
767 * lowlevel callbacks for each DMA type
768 *
769 * every callback is supposed to be called in chip->reg_lock spinlock
770 */
771
772/* flush FIFO of analog OUT DMA */
74ee4ff1 773static void atiixp_out_flush_dma(struct atiixp *chip)
1da177e4
LT		 774{
775 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH);
776}
777
778/* enable/disable analog OUT DMA */
74ee4ff1 779static void atiixp_out_enable_dma(struct atiixp *chip, int on)
1da177e4
LT		 780{
781 unsigned int data;
782 data = atiixp_read(chip, CMD);
783 if (on) {
784 if (data & ATI_REG_CMD_OUT_DMA_EN)
785 return;
786 atiixp_out_flush_dma(chip);
787 data |= ATI_REG_CMD_OUT_DMA_EN;
788 } else
789 data &= ~ATI_REG_CMD_OUT_DMA_EN;
790 atiixp_write(chip, CMD, data);
791}
792
793/* start/stop transfer over OUT DMA */
74ee4ff1 794static void atiixp_out_enable_transfer(struct atiixp *chip, int on)
1da177e4
LT		 795{
796 atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN,
797 on ? ATI_REG_CMD_SEND_EN : 0);
798}
799
800/* enable/disable analog IN DMA */
74ee4ff1 801static void atiixp_in_enable_dma(struct atiixp *chip, int on)
1da177e4
LT		 802{
803 atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN,
804 on ? ATI_REG_CMD_IN_DMA_EN : 0);
805}
806
807/* start/stop analog IN DMA */
74ee4ff1 808static void atiixp_in_enable_transfer(struct atiixp *chip, int on)
1da177e4
LT		 809{
810 if (on) {
811 unsigned int data = atiixp_read(chip, CMD);
812 if (! (data & ATI_REG_CMD_RECEIVE_EN)) {
813 data |= ATI_REG_CMD_RECEIVE_EN;
814#if 0 /* FIXME: this causes the endless loop */
815 /* wait until slot 3/4 are finished */
816 while ((atiixp_read(chip, COUNTER) &
817 ATI_REG_COUNTER_SLOT) != 5)
818 ;
819#endif
820 atiixp_write(chip, CMD, data);
821 }
822 } else
823 atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0);
824}
825
826/* flush FIFO of analog IN DMA */
74ee4ff1 827static void atiixp_in_flush_dma(struct atiixp *chip)
1da177e4
LT		 828{
829 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH);
830}
831
832/* enable/disable SPDIF OUT DMA */
74ee4ff1 833static void atiixp_spdif_enable_dma(struct atiixp *chip, int on)
1da177e4
LT		 834{
835 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN,
836 on ? ATI_REG_CMD_SPDF_DMA_EN : 0);
837}
838
839/* start/stop SPDIF OUT DMA */
74ee4ff1 840static void atiixp_spdif_enable_transfer(struct atiixp *chip, int on)
1da177e4
LT		 841{
842 unsigned int data;
843 data = atiixp_read(chip, CMD);
844 if (on)
845 data |= ATI_REG_CMD_SPDF_OUT_EN;
846 else
847 data &= ~ATI_REG_CMD_SPDF_OUT_EN;
848 atiixp_write(chip, CMD, data);
849}
850
851/* flush FIFO of SPDIF OUT DMA */
74ee4ff1 852static void atiixp_spdif_flush_dma(struct atiixp *chip)
1da177e4
LT		 853{
854 int timeout;
855
856 /* DMA off, transfer on */
857 atiixp_spdif_enable_dma(chip, 0);
858 atiixp_spdif_enable_transfer(chip, 1);
859
860 timeout = 100;
861 do {
862 if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED))
863 break;
864 udelay(1);
865 } while (timeout-- > 0);
866
867 atiixp_spdif_enable_transfer(chip, 0);
868}
869
870/* set up slots and formats for SPDIF OUT */
74ee4ff1 871static int snd_atiixp_spdif_prepare(struct snd_pcm_substream *substream)
1da177e4 872{
74ee4ff1 873 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 874
875 spin_lock_irq(&chip->reg_lock);
876 if (chip->spdif_over_aclink) {
877 unsigned int data;
878 /* enable slots 10/11 */
879 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK,
880 ATI_REG_CMD_SPDF_CONFIG_01);
881 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
882 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
883 ATI_REG_OUT_DMA_SLOT_BIT(11);
884 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
885 atiixp_write(chip, OUT_DMA_SLOT, data);
886 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
887 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
888 ATI_REG_CMD_INTERLEAVE_OUT : 0);
889 } else {
890 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0);
891 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0);
892 }
893 spin_unlock_irq(&chip->reg_lock);
894 return 0;
895}
896
897/* set up slots and formats for analog OUT */
74ee4ff1 898static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 899{
74ee4ff1 900 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 901 unsigned int data;
902
903 spin_lock_irq(&chip->reg_lock);
904 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
905 switch (substream->runtime->channels) {
906 case 8:
907 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
908 ATI_REG_OUT_DMA_SLOT_BIT(11);
909 /* fallthru */
910 case 6:
911 data |= ATI_REG_OUT_DMA_SLOT_BIT(7) |
912 ATI_REG_OUT_DMA_SLOT_BIT(8);
913 /* fallthru */
914 case 4:
915 data |= ATI_REG_OUT_DMA_SLOT_BIT(6) |
916 ATI_REG_OUT_DMA_SLOT_BIT(9);
917 /* fallthru */
918 default:
919 data |= ATI_REG_OUT_DMA_SLOT_BIT(3) |
920 ATI_REG_OUT_DMA_SLOT_BIT(4);
921 break;
922 }
923
924 /* set output threshold */
925 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
926 atiixp_write(chip, OUT_DMA_SLOT, data);
927
928 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
929 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
930 ATI_REG_CMD_INTERLEAVE_OUT : 0);
931
932 /*
933 * enable 6 channel re-ordering bit if needed
934 */
935 atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN,
936 substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0);
937
938 spin_unlock_irq(&chip->reg_lock);
939 return 0;
940}
941
942/* set up slots and formats for analog IN */
74ee4ff1 943static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 944{
74ee4ff1 945 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 946
947 spin_lock_irq(&chip->reg_lock);
948 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN,
949 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
950 ATI_REG_CMD_INTERLEAVE_IN : 0);
951 spin_unlock_irq(&chip->reg_lock);
952 return 0;
953}
954
955/*
956 * hw_params - allocate the buffer and set up buffer descriptors
957 */
74ee4ff1
TI		 958static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream,
959 struct snd_pcm_hw_params *hw_params)
1da177e4 960{
74ee4ff1
TI		 961 struct atiixp *chip = snd_pcm_substream_chip(substream);
962 struct atiixp_dma *dma = substream->runtime->private_data;
1da177e4
LT		 963 int err;
964
965 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
966 if (err < 0)
967 return err;
968 dma->buf_addr = substream->runtime->dma_addr;
969 dma->buf_bytes = params_buffer_bytes(hw_params);
970
971 err = atiixp_build_dma_packets(chip, dma, substream,
972 params_periods(hw_params),
973 params_period_bytes(hw_params));
974 if (err < 0)
975 return err;
976
977 if (dma->ac97_pcm_type >= 0) {
978 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
979 /* PCM is bound to AC97 codec(s)
980 * set up the AC97 codecs
981 */
982 if (dma->pcm_open_flag) {
983 snd_ac97_pcm_close(pcm);
984 dma->pcm_open_flag = 0;
985 }
986 err = snd_ac97_pcm_open(pcm, params_rate(hw_params),
987 params_channels(hw_params),
988 pcm->r[0].slots);
989 if (err >= 0)
990 dma->pcm_open_flag = 1;
991 }
992
993 return err;
994}
995
74ee4ff1 996static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4 997{
74ee4ff1
TI		 998 struct atiixp *chip = snd_pcm_substream_chip(substream);
999 struct atiixp_dma *dma = substream->runtime->private_data;
1da177e4
LT		 1000
1001 if (dma->pcm_open_flag) {
1002 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
1003 snd_ac97_pcm_close(pcm);
1004 dma->pcm_open_flag = 0;
1005 }
1006 atiixp_clear_dma_packets(chip, dma, substream);
1007 snd_pcm_lib_free_pages(substream);
1008 return 0;
1009}
1010
1011
1012/*
1013 * pcm hardware definition, identical for all DMA types
1014 */
74ee4ff1 1015static struct snd_pcm_hardware snd_atiixp_pcm_hw =
1da177e4
LT		 1016{
1017 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1018 SNDRV_PCM_INFO_BLOCK_TRANSFER |
41e4845c 1019 SNDRV_PCM_INFO_PAUSE |
1da177e4
LT		 1020 SNDRV_PCM_INFO_RESUME |
1021 SNDRV_PCM_INFO_MMAP_VALID),
1022 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1023 .rates = SNDRV_PCM_RATE_48000,
1024 .rate_min = 48000,
1025 .rate_max = 48000,
1026 .channels_min = 2,
1027 .channels_max = 2,
1028 .buffer_bytes_max = 256 * 1024,
1029 .period_bytes_min = 32,
1030 .period_bytes_max = 128 * 1024,
1031 .periods_min = 2,
1032 .periods_max = ATI_MAX_DESCRIPTORS,
1033};
1034
74ee4ff1
TI		 1035static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream,
1036 struct atiixp_dma *dma, int pcm_type)
1da177e4 1037{
74ee4ff1
TI		 1038 struct atiixp *chip = snd_pcm_substream_chip(substream);
1039 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1040 int err;
1041
da3cec35
TI		 1042 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
1043 return -EINVAL;
1da177e4
LT		 1044
1045 if (dma->opened)
1046 return -EBUSY;
1047 dma->substream = substream;
1048 runtime->hw = snd_atiixp_pcm_hw;
1049 dma->ac97_pcm_type = pcm_type;
1050 if (pcm_type >= 0) {
1051 runtime->hw.rates = chip->pcms[pcm_type]->rates;
1052 snd_pcm_limit_hw_rates(runtime);
1053 } else {
1054 /* direct SPDIF */
1055 runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
1056 }
1057 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1058 return err;
1059 runtime->private_data = dma;
1060
1061 /* enable DMA bits */
1062 spin_lock_irq(&chip->reg_lock);
1063 dma->ops->enable_dma(chip, 1);
1064 spin_unlock_irq(&chip->reg_lock);
1065 dma->opened = 1;
1066
1067 return 0;
1068}
1069
74ee4ff1
TI		 1070static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream,
1071 struct atiixp_dma *dma)
1da177e4 1072{
74ee4ff1 1073 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4 1074 /* disable DMA bits */
da3cec35
TI		 1075 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
1076 return -EINVAL;
1da177e4
LT		 1077 spin_lock_irq(&chip->reg_lock);
1078 dma->ops->enable_dma(chip, 0);
1079 spin_unlock_irq(&chip->reg_lock);
1080 dma->substream = NULL;
1081 dma->opened = 0;
1082 return 0;
1083}
1084
1085/*
1086 */
74ee4ff1 1087static int snd_atiixp_playback_open(struct snd_pcm_substream *substream)
1da177e4 1088{
74ee4ff1 1089 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1090 int err;
1091
62932df8 1092 mutex_lock(&chip->open_mutex);
1da177e4 1093 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0);
62932df8 1094 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1095 if (err < 0)
1096 return err;
1097 substream->runtime->hw.channels_max = chip->max_channels;
1098 if (chip->max_channels > 2)
1099 /* channels must be even */
1100 snd_pcm_hw_constraint_step(substream->runtime, 0,
1101 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1102 return 0;
1103}
1104
74ee4ff1 1105static int snd_atiixp_playback_close(struct snd_pcm_substream *substream)
1da177e4 1106{
74ee4ff1 1107 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4 1108 int err;
62932df8 1109 mutex_lock(&chip->open_mutex);
1da177e4 1110 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
62932df8 1111 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1112 return err;
1113}
1114
74ee4ff1 1115static int snd_atiixp_capture_open(struct snd_pcm_substream *substream)
1da177e4 1116{
74ee4ff1 1117 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1118 return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1);
1119}
1120
74ee4ff1 1121static int snd_atiixp_capture_close(struct snd_pcm_substream *substream)
1da177e4 1122{
74ee4ff1 1123 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1124 return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]);
1125}
1126
74ee4ff1 1127static int snd_atiixp_spdif_open(struct snd_pcm_substream *substream)
1da177e4 1128{
74ee4ff1 1129 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4 1130 int err;
62932df8 1131 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1132 if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */
1133 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2);
1134 else
1135 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1);
62932df8 1136 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1137 return err;
1138}
1139
74ee4ff1 1140static int snd_atiixp_spdif_close(struct snd_pcm_substream *substream)
1da177e4 1141{
74ee4ff1 1142 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4 1143 int err;
62932df8 1144 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1145 if (chip->spdif_over_aclink)
1146 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
1147 else
1148 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]);
62932df8 1149 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1150 return err;
1151}
1152
1153/* AC97 playback */
74ee4ff1 1154static struct snd_pcm_ops snd_atiixp_playback_ops = {
1da177e4
LT		 1155 .open = snd_atiixp_playback_open,
1156 .close = snd_atiixp_playback_close,
1157 .ioctl = snd_pcm_lib_ioctl,
1158 .hw_params = snd_atiixp_pcm_hw_params,
1159 .hw_free = snd_atiixp_pcm_hw_free,
1160 .prepare = snd_atiixp_playback_prepare,
1161 .trigger = snd_atiixp_pcm_trigger,
1162 .pointer = snd_atiixp_pcm_pointer,
1163};
1164
1165/* AC97 capture */
74ee4ff1 1166static struct snd_pcm_ops snd_atiixp_capture_ops = {
1da177e4
LT		 1167 .open = snd_atiixp_capture_open,
1168 .close = snd_atiixp_capture_close,
1169 .ioctl = snd_pcm_lib_ioctl,
1170 .hw_params = snd_atiixp_pcm_hw_params,
1171 .hw_free = snd_atiixp_pcm_hw_free,
1172 .prepare = snd_atiixp_capture_prepare,
1173 .trigger = snd_atiixp_pcm_trigger,
1174 .pointer = snd_atiixp_pcm_pointer,
1175};
1176
1177/* SPDIF playback */
74ee4ff1 1178static struct snd_pcm_ops snd_atiixp_spdif_ops = {
1da177e4
LT		 1179 .open = snd_atiixp_spdif_open,
1180 .close = snd_atiixp_spdif_close,
1181 .ioctl = snd_pcm_lib_ioctl,
1182 .hw_params = snd_atiixp_pcm_hw_params,
1183 .hw_free = snd_atiixp_pcm_hw_free,
1184 .prepare = snd_atiixp_spdif_prepare,
1185 .trigger = snd_atiixp_pcm_trigger,
1186 .pointer = snd_atiixp_pcm_pointer,
1187};
1188
e23e7a14 1189static struct ac97_pcm atiixp_pcm_defs[] = {
1da177e4
LT		 1190 /* front PCM */
1191 {
1192 .exclusive = 1,
1193 .r = { {
1194 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1195 (1 << AC97_SLOT_PCM_RIGHT) |
1196 (1 << AC97_SLOT_PCM_CENTER) |
1197 (1 << AC97_SLOT_PCM_SLEFT) |
1198 (1 << AC97_SLOT_PCM_SRIGHT) |
1199 (1 << AC97_SLOT_LFE)
1200 }
1201 }
1202 },
1203 /* PCM IN #1 */
1204 {
1205 .stream = 1,
1206 .exclusive = 1,
1207 .r = { {
1208 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1209 (1 << AC97_SLOT_PCM_RIGHT)
1210 }
1211 }
1212 },
1213 /* S/PDIF OUT (optional) */
1214 {
1215 .exclusive = 1,
1216 .spdif = 1,
1217 .r = { {
1218 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1219 (1 << AC97_SLOT_SPDIF_RIGHT2)
1220 }
1221 }
1222 },
1223};
1224
74ee4ff1 1225static struct atiixp_dma_ops snd_atiixp_playback_dma_ops = {
1da177e4
LT		 1226 .type = ATI_DMA_PLAYBACK,
1227 .llp_offset = ATI_REG_OUT_DMA_LINKPTR,
1228 .dt_cur = ATI_REG_OUT_DMA_DT_CUR,
1229 .enable_dma = atiixp_out_enable_dma,
1230 .enable_transfer = atiixp_out_enable_transfer,
1231 .flush_dma = atiixp_out_flush_dma,
1232};
1233
74ee4ff1 1234static struct atiixp_dma_ops snd_atiixp_capture_dma_ops = {
1da177e4
LT		 1235 .type = ATI_DMA_CAPTURE,
1236 .llp_offset = ATI_REG_IN_DMA_LINKPTR,
1237 .dt_cur = ATI_REG_IN_DMA_DT_CUR,
1238 .enable_dma = atiixp_in_enable_dma,
1239 .enable_transfer = atiixp_in_enable_transfer,
1240 .flush_dma = atiixp_in_flush_dma,
1241};
1242
74ee4ff1 1243static struct atiixp_dma_ops snd_atiixp_spdif_dma_ops = {
1da177e4
LT		 1244 .type = ATI_DMA_SPDIF,
1245 .llp_offset = ATI_REG_SPDF_DMA_LINKPTR,
1246 .dt_cur = ATI_REG_SPDF_DMA_DT_CUR,
1247 .enable_dma = atiixp_spdif_enable_dma,
1248 .enable_transfer = atiixp_spdif_enable_transfer,
1249 .flush_dma = atiixp_spdif_flush_dma,
1250};
1251
1252
e23e7a14 1253static int snd_atiixp_pcm_new(struct atiixp *chip)
1da177e4 1254{
74ee4ff1 1255 struct snd_pcm *pcm;
e36e3b86 1256 struct snd_pcm_chmap *chmap;
74ee4ff1 1257 struct snd_ac97_bus *pbus = chip->ac97_bus;
1da177e4
LT		 1258 int err, i, num_pcms;
1259
1260 /* initialize constants */
1261 chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops;
1262 chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops;
1263 if (! chip->spdif_over_aclink)
1264 chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops;
1265
1266 /* assign AC97 pcm */
1267 if (chip->spdif_over_aclink)
1268 num_pcms = 3;
1269 else
1270 num_pcms = 2;
1271 err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs);
1272 if (err < 0)
1273 return err;
1274 for (i = 0; i < num_pcms; i++)
1275 chip->pcms[i] = &pbus->pcms[i];
1276
1277 chip->max_channels = 2;
1278 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
1279 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE))
1280 chip->max_channels = 6;
1281 else
1282 chip->max_channels = 4;
1283 }
1284
1285 /* PCM #0: analog I/O */
74ee4ff1
TI		 1286 err = snd_pcm_new(chip->card, "ATI IXP AC97",
1287 ATI_PCMDEV_ANALOG, 1, 1, &pcm);
1da177e4
LT		 1288 if (err < 0)
1289 return err;
1290 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops);
1291 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops);
1292 pcm->private_data = chip;
1293 strcpy(pcm->name, "ATI IXP AC97");
1294 chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm;
1295
1296 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
74ee4ff1
TI		 1297 snd_dma_pci_data(chip->pci),
1298 64*1024, 128*1024);
1da177e4 1299
e36e3b86
TI		 1300 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1301 snd_pcm_alt_chmaps, chip->max_channels, 0,
1302 &chmap);
1303 if (err < 0)
1304 return err;
1305 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1306 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1307
1da177e4
LT		 1308 /* no SPDIF support on codec? */
1309 if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates)
1310 return 0;
1311
1312 /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */
1313 if (chip->pcms[ATI_PCM_SPDIF])
1314 chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000;
1315
1316 /* PCM #1: spdif playback */
74ee4ff1
TI		 1317 err = snd_pcm_new(chip->card, "ATI IXP IEC958",
1318 ATI_PCMDEV_DIGITAL, 1, 0, &pcm);
1da177e4
LT		 1319 if (err < 0)
1320 return err;
1321 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops);
1322 pcm->private_data = chip;
1323 if (chip->spdif_over_aclink)
1324 strcpy(pcm->name, "ATI IXP IEC958 (AC97)");
1325 else
1326 strcpy(pcm->name, "ATI IXP IEC958 (Direct)");
1327 chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm;
1328
1329 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
74ee4ff1
TI		 1330 snd_dma_pci_data(chip->pci),
1331 64*1024, 128*1024);
1da177e4
LT		 1332
1333 /* pre-select AC97 SPDIF slots 10/11 */
1334 for (i = 0; i < NUM_ATI_CODECS; i++) {
1335 if (chip->ac97[i])
74ee4ff1
TI		 1336 snd_ac97_update_bits(chip->ac97[i],
1337 AC97_EXTENDED_STATUS,
1338 0x03 << 4, 0x03 << 4);
1da177e4
LT		 1339 }
1340
1341 return 0;
1342}
1343
1344
1345
1346/*
1347 * interrupt handler
1348 */
7d12e780 1349static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id)
1da177e4 1350{
74ee4ff1 1351 struct atiixp *chip = dev_id;
1da177e4
LT		 1352 unsigned int status;
1353
1354 status = atiixp_read(chip, ISR);
1355
1356 if (! status)
1357 return IRQ_NONE;
1358
1359 /* process audio DMA */
1360 if (status & ATI_REG_ISR_OUT_XRUN)
1361 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1362 else if (status & ATI_REG_ISR_OUT_STATUS)
1363 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1364 if (status & ATI_REG_ISR_IN_XRUN)
1365 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1366 else if (status & ATI_REG_ISR_IN_STATUS)
1367 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1368 if (! chip->spdif_over_aclink) {
1369 if (status & ATI_REG_ISR_SPDF_XRUN)
1370 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1371 else if (status & ATI_REG_ISR_SPDF_STATUS)
1372 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1373 }
1374
1375 /* for codec detection */
1376 if (status & CODEC_CHECK_BITS) {
1377 unsigned int detected;
1378 detected = status & CODEC_CHECK_BITS;
1379 spin_lock(&chip->reg_lock);
1380 chip->codec_not_ready_bits |= detected;
1381 atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
1382 spin_unlock(&chip->reg_lock);
1383 }
1384
1385 /* ack */
1386 atiixp_write(chip, ISR, status);
1387
1388 return IRQ_HANDLED;
1389}
1390
1391
1392/*
1393 * ac97 mixer section
1394 */
1395
e23e7a14 1396static struct ac97_quirk ac97_quirks[] = {
1da177e4 1397 {
69ad07cf
JK		 1398 .subvendor = 0x103c,
1399 .subdevice = 0x006b,
1da177e4
LT		 1400 .name = "HP Pavilion ZV5030US",
1401 .type = AC97_TUNE_MUTE_LED
1402 },
a0faefed
MG		 1403 {
1404 .subvendor = 0x103c,
1405 .subdevice = 0x308b,
1406 .name = "HP nx6125",
1407 .type = AC97_TUNE_MUTE_LED
1408 },
e3ba906a
DC		 1409 {
1410 .subvendor = 0x103c,
1411 .subdevice = 0x3091,
1412 .name = "unknown HP",
1413 .type = AC97_TUNE_MUTE_LED
1414 },
1da177e4
LT		 1415 { } /* terminator */
1416};
1417
e23e7a14
BP		 1418static int snd_atiixp_mixer_new(struct atiixp *chip, int clock,
1419 const char *quirk_override)
1da177e4 1420{
74ee4ff1
TI		 1421 struct snd_ac97_bus *pbus;
1422 struct snd_ac97_template ac97;
1da177e4
LT		 1423 int i, err;
1424 int codec_count;
74ee4ff1 1425 static struct snd_ac97_bus_ops ops = {
1da177e4
LT		 1426 .write = snd_atiixp_ac97_write,
1427 .read = snd_atiixp_ac97_read,
1428 };
1429 static unsigned int codec_skip[NUM_ATI_CODECS] = {
1430 ATI_REG_ISR_CODEC0_NOT_READY,
1431 ATI_REG_ISR_CODEC1_NOT_READY,
1432 ATI_REG_ISR_CODEC2_NOT_READY,
1433 };
1434
1435 if (snd_atiixp_codec_detect(chip) < 0)
1436 return -ENXIO;
1437
1438 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
1439 return err;
1440 pbus->clock = clock;
1da177e4
LT		 1441 chip->ac97_bus = pbus;
1442
1443 codec_count = 0;
1444 for (i = 0; i < NUM_ATI_CODECS; i++) {
1445 if (chip->codec_not_ready_bits & codec_skip[i])
1446 continue;
1447 memset(&ac97, 0, sizeof(ac97));
1448 ac97.private_data = chip;
1449 ac97.pci = chip->pci;
1450 ac97.num = i;
f1a63a38 1451 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
1da177e4
LT		 1452 if (! chip->spdif_over_aclink)
1453 ac97.scaps |= AC97_SCAP_NO_SPDIF;
1454 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
1455 chip->ac97[i] = NULL; /* to be sure */
1456 snd_printdd("atiixp: codec %d not available for audio\n", i);
1457 continue;
1458 }
1459 codec_count++;
1460 }
1461
1462 if (! codec_count) {
1463 snd_printk(KERN_ERR "atiixp: no codec available\n");
1464 return -ENODEV;
1465 }
1466
1467 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
1468
1469 return 0;
1470}
1471
1472
c7561cd8 1473#ifdef CONFIG_PM_SLEEP
1da177e4
LT		 1474/*
1475 * power management
1476 */
68cb2b55 1477static int snd_atiixp_suspend(struct device *dev)
1da177e4 1478{
68cb2b55
TI		 1479 struct pci_dev *pci = to_pci_dev(dev);
1480 struct snd_card *card = dev_get_drvdata(dev);
92304cc7 1481 struct atiixp *chip = card->private_data;
1da177e4
LT		 1482 int i;
1483
92304cc7 1484 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1da177e4
LT		 1485 for (i = 0; i < NUM_ATI_PCMDEVS; i++)
1486 if (chip->pcmdevs[i]) {
74ee4ff1 1487 struct atiixp_dma *dma = &chip->dmas[i];
1da177e4 1488 if (dma->substream && dma->running)
74ee4ff1
TI		 1489 dma->saved_curptr = readl(chip->remap_addr +
1490 dma->ops->dt_cur);
1da177e4
LT		 1491 snd_pcm_suspend_all(chip->pcmdevs[i]);
1492 }
1493 for (i = 0; i < NUM_ATI_CODECS; i++)
92304cc7 1494 snd_ac97_suspend(chip->ac97[i]);
1da177e4
LT		 1495 snd_atiixp_aclink_down(chip);
1496 snd_atiixp_chip_stop(chip);
1497
92304cc7
TI		 1498 pci_disable_device(pci);
1499 pci_save_state(pci);
68cb2b55 1500 pci_set_power_state(pci, PCI_D3hot);
1da177e4
LT		 1501 return 0;
1502}
1503
68cb2b55 1504static int snd_atiixp_resume(struct device *dev)
1da177e4 1505{
68cb2b55
TI		 1506 struct pci_dev *pci = to_pci_dev(dev);
1507 struct snd_card *card = dev_get_drvdata(dev);
92304cc7 1508 struct atiixp *chip = card->private_data;
1da177e4
LT		 1509 int i;
1510
92304cc7 1511 pci_set_power_state(pci, PCI_D0);
30b35399
TI		 1512 pci_restore_state(pci);
1513 if (pci_enable_device(pci) < 0) {
1514 printk(KERN_ERR "atiixp: pci_enable_device failed, "
1515 "disabling device\n");
1516 snd_card_disconnect(card);
1517 return -EIO;
1518 }
92304cc7 1519 pci_set_master(pci);
1da177e4
LT		 1520
1521 snd_atiixp_aclink_reset(chip);
1522 snd_atiixp_chip_start(chip);
1523
1524 for (i = 0; i < NUM_ATI_CODECS; i++)
92304cc7 1525 snd_ac97_resume(chip->ac97[i]);
1da177e4
LT		 1526
1527 for (i = 0; i < NUM_ATI_PCMDEVS; i++)
1528 if (chip->pcmdevs[i]) {
74ee4ff1 1529 struct atiixp_dma *dma = &chip->dmas[i];
41e4845c 1530 if (dma->substream && dma->suspended) {
1da177e4 1531 dma->ops->enable_dma(chip, 1);
8e3d759d 1532 dma->substream->ops->prepare(dma->substream);
1da177e4
LT		 1533 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
1534 chip->remap_addr + dma->ops->llp_offset);
74ee4ff1
TI		 1535 writel(dma->saved_curptr, chip->remap_addr +
1536 dma->ops->dt_cur);
1da177e4
LT		 1537 }
1538 }
1539
92304cc7 1540 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 1541 return 0;
1542}
68cb2b55
TI		 1543
1544static SIMPLE_DEV_PM_OPS(snd_atiixp_pm, snd_atiixp_suspend, snd_atiixp_resume);
1545#define SND_ATIIXP_PM_OPS &snd_atiixp_pm
1546#else
1547#define SND_ATIIXP_PM_OPS NULL
c7561cd8 1548#endif /* CONFIG_PM_SLEEP */
1da177e4
LT		 1549
1550
adf1b3d2 1551#ifdef CONFIG_PROC_FS
1da177e4
LT		 1552/*
1553 * proc interface for register dump
1554 */
1555
74ee4ff1
TI		 1556static void snd_atiixp_proc_read(struct snd_info_entry *entry,
1557 struct snd_info_buffer *buffer)
1da177e4 1558{
74ee4ff1 1559 struct atiixp *chip = entry->private_data;
1da177e4
LT		 1560 int i;
1561
1562 for (i = 0; i < 256; i += 4)
1563 snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i));
1564}
1565
e23e7a14 1566static void snd_atiixp_proc_init(struct atiixp *chip)
1da177e4 1567{
74ee4ff1 1568 struct snd_info_entry *entry;
1da177e4
LT		 1569
1570 if (! snd_card_proc_new(chip->card, "atiixp", &entry))
bf850204 1571 snd_info_set_text_ops(entry, chip, snd_atiixp_proc_read);
1da177e4 1572}
adf1b3d2
TI		 1573#else /* !CONFIG_PROC_FS */
1574#define snd_atiixp_proc_init(chip)
1575#endif
1da177e4
LT		 1576
1577
1578/*
1579 * destructor
1580 */
1581
74ee4ff1 1582static int snd_atiixp_free(struct atiixp *chip)
1da177e4
LT		 1583{
1584 if (chip->irq < 0)
1585 goto __hw_end;
1586 snd_atiixp_chip_stop(chip);
f000fd80 1587
1da177e4
LT		 1588 __hw_end:
1589 if (chip->irq >= 0)
74ee4ff1 1590 free_irq(chip->irq, chip);
1da177e4
LT		 1591 if (chip->remap_addr)
1592 iounmap(chip->remap_addr);
1593 pci_release_regions(chip->pci);
1594 pci_disable_device(chip->pci);
1595 kfree(chip);
1596 return 0;
1597}
1598
74ee4ff1 1599static int snd_atiixp_dev_free(struct snd_device *device)
1da177e4 1600{
74ee4ff1 1601 struct atiixp *chip = device->device_data;
1da177e4
LT		 1602 return snd_atiixp_free(chip);
1603}
1604
1605/*
1606 * constructor for chip instance
1607 */
e23e7a14
BP		 1608static int snd_atiixp_create(struct snd_card *card,
1609 struct pci_dev *pci,
1610 struct atiixp **r_chip)
1da177e4 1611{
74ee4ff1 1612 static struct snd_device_ops ops = {
1da177e4
LT		 1613 .dev_free = snd_atiixp_dev_free,
1614 };
74ee4ff1 1615 struct atiixp *chip;
1da177e4
LT		 1616 int err;
1617
1618 if ((err = pci_enable_device(pci)) < 0)
1619 return err;
1620
e560d8d8 1621 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 1622 if (chip == NULL) {
1623 pci_disable_device(pci);
1624 return -ENOMEM;
1625 }
1626
1627 spin_lock_init(&chip->reg_lock);
62932df8 1628 mutex_init(&chip->open_mutex);
1da177e4
LT		 1629 chip->card = card;
1630 chip->pci = pci;
1631 chip->irq = -1;
1632 if ((err = pci_request_regions(pci, "ATI IXP AC97")) < 0) {
1633 pci_disable_device(pci);
1634 kfree(chip);
1635 return err;
1636 }
1637 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 1638 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 1639 if (chip->remap_addr == NULL) {
1640 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
1641 snd_atiixp_free(chip);
1642 return -EIO;
1643 }
1644
437a5a46 1645 if (request_irq(pci->irq, snd_atiixp_interrupt, IRQF_SHARED,
934c2b6d 1646 KBUILD_MODNAME, chip)) {
1da177e4
LT		 1647 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1648 snd_atiixp_free(chip);
1649 return -EBUSY;
1650 }
1651 chip->irq = pci->irq;
1652 pci_set_master(pci);
1653 synchronize_irq(chip->irq);
1654
1655 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1656 snd_atiixp_free(chip);
1657 return err;
1658 }
1659
1660 snd_card_set_dev(card, &pci->dev);
1661
1662 *r_chip = chip;
1663 return 0;
1664}
1665
1666
e23e7a14
BP		 1667static int snd_atiixp_probe(struct pci_dev *pci,
1668 const struct pci_device_id *pci_id)
1da177e4 1669{
74ee4ff1
TI		 1670 struct snd_card *card;
1671 struct atiixp *chip;
1da177e4
LT		 1672 int err;
1673
e58de7ba
TI		 1674 err = snd_card_create(index, id, THIS_MODULE, 0, &card);
1675 if (err < 0)
1676 return err;
1da177e4 1677
b7fe4622 1678 strcpy(card->driver, spdif_aclink ? "ATIIXP" : "ATIIXP-SPDMA");
1da177e4
LT		 1679 strcpy(card->shortname, "ATI IXP");
1680 if ((err = snd_atiixp_create(card, pci, &chip)) < 0)
1681 goto __error;
92304cc7 1682 card->private_data = chip;
1da177e4
LT		 1683
1684 if ((err = snd_atiixp_aclink_reset(chip)) < 0)
1685 goto __error;
1686
b7fe4622 1687 chip->spdif_over_aclink = spdif_aclink;
1da177e4 1688
b7fe4622 1689 if ((err = snd_atiixp_mixer_new(chip, ac97_clock, ac97_quirk)) < 0)
1da177e4
LT		 1690 goto __error;
1691
1692 if ((err = snd_atiixp_pcm_new(chip)) < 0)
1693 goto __error;
1694
1695 snd_atiixp_proc_init(chip);
1696
1697 snd_atiixp_chip_start(chip);
1698
1699 snprintf(card->longname, sizeof(card->longname),
44c10138
AK		 1700 "%s rev %x with %s at %#lx, irq %i", card->shortname,
1701 pci->revision,
1da177e4
LT		 1702 chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?",
1703 chip->addr, chip->irq);
1704
1da177e4
LT		 1705 if ((err = snd_card_register(card)) < 0)
1706 goto __error;
1707
1708 pci_set_drvdata(pci, card);
1da177e4
LT		 1709 return 0;
1710
1711 __error:
1712 snd_card_free(card);
1713 return err;
1714}
1715
e23e7a14 1716static void snd_atiixp_remove(struct pci_dev *pci)
1da177e4
LT		 1717{
1718 snd_card_free(pci_get_drvdata(pci));
1719 pci_set_drvdata(pci, NULL);
1720}
1721
e9f66d9b 1722static struct pci_driver atiixp_driver = {
3733e424 1723 .name = KBUILD_MODNAME,
1da177e4
LT		 1724 .id_table = snd_atiixp_ids,
1725 .probe = snd_atiixp_probe,
e23e7a14 1726 .remove = snd_atiixp_remove,
68cb2b55
TI		 1727 .driver = {
1728 .pm = SND_ATIIXP_PM_OPS,
1729 },
1da177e4
LT		 1730};
1731
e9f66d9b 1732module_pci_driver(atiixp_driver);
kernel source for telekom puls (alcatel/mediatek)