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[ALSA] Add PCXHR driver
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / pci / atiixp.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for ATI IXP 150/200/250/300 AC97 controllers
3 *
4 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#include <sound/driver.h>
23#include <asm/io.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/slab.h>
29#include <linux/moduleparam.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/info.h>
34#include <sound/ac97_codec.h>
35#include <sound/initval.h>
36
37MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
38MODULE_DESCRIPTION("ATI IXP AC97 controller");
39MODULE_LICENSE("GPL");
40MODULE_SUPPORTED_DEVICE("{{ATI,IXP150/200/250/300/400}}");
41
b7fe4622
CL		 42static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
43static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
44static int ac97_clock = 48000;
45static char *ac97_quirk;
46static int spdif_aclink = 1;
47
48module_param(index, int, 0444);
1da177e4 49MODULE_PARM_DESC(index, "Index value for ATI IXP controller.");
b7fe4622 50module_param(id, charp, 0444);
1da177e4 51MODULE_PARM_DESC(id, "ID string for ATI IXP controller.");
b7fe4622 52module_param(ac97_clock, int, 0444);
1da177e4 53MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
b7fe4622 54module_param(ac97_quirk, charp, 0444);
1da177e4 55MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
b7fe4622 56module_param(spdif_aclink, bool, 0444);
1da177e4
LT		 57MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
58
2b3e584b
TI		 59/* just for backward compatibility */
60static int enable;
698444f3 61module_param(enable, bool, 0444);
2b3e584b 62
1da177e4
LT		 63
64/*
65 */
66
67#define ATI_REG_ISR 0x00 /* interrupt source */
68#define ATI_REG_ISR_IN_XRUN (1U<<0)
69#define ATI_REG_ISR_IN_STATUS (1U<<1)
70#define ATI_REG_ISR_OUT_XRUN (1U<<2)
71#define ATI_REG_ISR_OUT_STATUS (1U<<3)
72#define ATI_REG_ISR_SPDF_XRUN (1U<<4)
73#define ATI_REG_ISR_SPDF_STATUS (1U<<5)
74#define ATI_REG_ISR_PHYS_INTR (1U<<8)
75#define ATI_REG_ISR_PHYS_MISMATCH (1U<<9)
76#define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10)
77#define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11)
78#define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12)
79#define ATI_REG_ISR_NEW_FRAME (1U<<13)
80
81#define ATI_REG_IER 0x04 /* interrupt enable */
82#define ATI_REG_IER_IN_XRUN_EN (1U<<0)
83#define ATI_REG_IER_IO_STATUS_EN (1U<<1)
84#define ATI_REG_IER_OUT_XRUN_EN (1U<<2)
85#define ATI_REG_IER_OUT_XRUN_COND (1U<<3)
86#define ATI_REG_IER_SPDF_XRUN_EN (1U<<4)
87#define ATI_REG_IER_SPDF_STATUS_EN (1U<<5)
88#define ATI_REG_IER_PHYS_INTR_EN (1U<<8)
89#define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9)
90#define ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
91#define ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
92#define ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
93#define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */
94#define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */
95
96#define ATI_REG_CMD 0x08 /* command */
97#define ATI_REG_CMD_POWERDOWN (1U<<0)
98#define ATI_REG_CMD_RECEIVE_EN (1U<<1)
99#define ATI_REG_CMD_SEND_EN (1U<<2)
100#define ATI_REG_CMD_STATUS_MEM (1U<<3)
101#define ATI_REG_CMD_SPDF_OUT_EN (1U<<4)
102#define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5)
103#define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6)
104#define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6
105#define ATI_REG_CMD_IN_DMA_EN (1U<<8)
106#define ATI_REG_CMD_OUT_DMA_EN (1U<<9)
107#define ATI_REG_CMD_SPDF_DMA_EN (1U<<10)
108#define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11)
109#define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12)
110#define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12)
111#define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12)
112#define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12)
113#define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12)
114#define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16)
115#define ATI_REG_CMD_AUDIO_PRESENT (1U<<20)
116#define ATI_REG_CMD_INTERLEAVE_IN (1U<<21)
117#define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22)
118#define ATI_REG_CMD_LOOPBACK_EN (1U<<23)
119#define ATI_REG_CMD_PACKED_DIS (1U<<24)
120#define ATI_REG_CMD_BURST_EN (1U<<25)
121#define ATI_REG_CMD_PANIC_EN (1U<<26)
122#define ATI_REG_CMD_MODEM_PRESENT (1U<<27)
123#define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28)
124#define ATI_REG_CMD_AC_SOFT_RESET (1U<<29)
125#define ATI_REG_CMD_AC_SYNC (1U<<30)
126#define ATI_REG_CMD_AC_RESET (1U<<31)
127
128#define ATI_REG_PHYS_OUT_ADDR 0x0c
129#define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
130#define ATI_REG_PHYS_OUT_RW (1U<<2)
131#define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8)
132#define ATI_REG_PHYS_OUT_ADDR_SHIFT 9
133#define ATI_REG_PHYS_OUT_DATA_SHIFT 16
134
135#define ATI_REG_PHYS_IN_ADDR 0x10
136#define ATI_REG_PHYS_IN_READ_FLAG (1U<<8)
137#define ATI_REG_PHYS_IN_ADDR_SHIFT 9
138#define ATI_REG_PHYS_IN_DATA_SHIFT 16
139
140#define ATI_REG_SLOTREQ 0x14
141
142#define ATI_REG_COUNTER 0x18
143#define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
144#define ATI_REG_COUNTER_BITCLOCK (31U<<8)
145
146#define ATI_REG_IN_FIFO_THRESHOLD 0x1c
147
148#define ATI_REG_IN_DMA_LINKPTR 0x20
149#define ATI_REG_IN_DMA_DT_START 0x24 /* RO */
150#define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */
151#define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */
152#define ATI_REG_IN_DMA_DT_SIZE 0x30
153
154#define ATI_REG_OUT_DMA_SLOT 0x34
155#define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3))
156#define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff
157#define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800
158#define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11
159
160#define ATI_REG_OUT_DMA_LINKPTR 0x38
161#define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */
162#define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */
163#define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */
164#define ATI_REG_OUT_DMA_DT_SIZE 0x48
165
166#define ATI_REG_SPDF_CMD 0x4c
167#define ATI_REG_SPDF_CMD_LFSR (1U<<4)
168#define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5)
169#define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */
170
171#define ATI_REG_SPDF_DMA_LINKPTR 0x50
172#define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */
173#define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */
174#define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */
175#define ATI_REG_SPDF_DMA_DT_SIZE 0x60
176
177#define ATI_REG_MODEM_MIRROR 0x7c
178#define ATI_REG_AUDIO_MIRROR 0x80
179
180#define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */
181#define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
182
183#define ATI_REG_FIFO_FLUSH 0x88
184#define ATI_REG_FIFO_OUT_FLUSH (1U<<0)
185#define ATI_REG_FIFO_IN_FLUSH (1U<<1)
186
187/* LINKPTR */
188#define ATI_REG_LINKPTR_EN (1U<<0)
189
190/* [INT|OUT|SPDIF]_DMA_DT_SIZE */
191#define ATI_REG_DMA_DT_SIZE (0xffffU<<0)
192#define ATI_REG_DMA_FIFO_USED (0x1fU<<16)
193#define ATI_REG_DMA_FIFO_FREE (0x1fU<<21)
194#define ATI_REG_DMA_STATE (7U<<26)
195
196
197#define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */
198
199
74ee4ff1 200struct atiixp;
1da177e4
LT		 201
202/*
203 * DMA packate descriptor
204 */
205
74ee4ff1 206struct atiixp_dma_desc {
1da177e4
LT		 207 u32 addr; /* DMA buffer address */
208 u16 status; /* status bits */
209 u16 size; /* size of the packet in dwords */
210 u32 next; /* address of the next packet descriptor */
74ee4ff1 211};
1da177e4
LT		 212
213/*
214 * stream enum
215 */
216enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */
217enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */
218enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */
219
220#define NUM_ATI_CODECS 3
221
222
223/*
224 * constants and callbacks for each DMA type
225 */
74ee4ff1 226struct atiixp_dma_ops {
1da177e4
LT		 227 int type; /* ATI_DMA_XXX */
228 unsigned int llp_offset; /* LINKPTR offset */
229 unsigned int dt_cur; /* DT_CUR offset */
74ee4ff1
TI		 230 /* called from open callback */
231 void (*enable_dma)(struct atiixp *chip, int on);
232 /* called from trigger (START/STOP) */
233 void (*enable_transfer)(struct atiixp *chip, int on);
234 /* called from trigger (STOP only) */
235 void (*flush_dma)(struct atiixp *chip);
1da177e4
LT		 236};
237
238/*
239 * DMA stream
240 */
74ee4ff1
TI		 241struct atiixp_dma {
242 const struct atiixp_dma_ops *ops;
1da177e4 243 struct snd_dma_buffer desc_buf;
74ee4ff1 244 struct snd_pcm_substream *substream; /* assigned PCM substream */
1da177e4
LT		 245 unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */
246 unsigned int period_bytes, periods;
247 int opened;
248 int running;
41e4845c 249 int suspended;
1da177e4
LT		 250 int pcm_open_flag;
251 int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */
252 unsigned int saved_curptr;
253};
254
255/*
256 * ATI IXP chip
257 */
74ee4ff1
TI		 258struct atiixp {
259 struct snd_card *card;
1da177e4
LT		 260 struct pci_dev *pci;
261
262 unsigned long addr;
263 void __iomem *remap_addr;
264 int irq;
265
74ee4ff1
TI		 266 struct snd_ac97_bus *ac97_bus;
267 struct snd_ac97 *ac97[NUM_ATI_CODECS];
1da177e4
LT		 268
269 spinlock_t reg_lock;
270
74ee4ff1 271 struct atiixp_dma dmas[NUM_ATI_DMAS];
1da177e4 272 struct ac97_pcm *pcms[NUM_ATI_PCMS];
74ee4ff1 273 struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS];
1da177e4
LT		 274
275 int max_channels; /* max. channels for PCM out */
276
277 unsigned int codec_not_ready_bits; /* for codec detection */
278
279 int spdif_over_aclink; /* passed from the module option */
280 struct semaphore open_mutex; /* playback open mutex */
281};
282
283
284/*
285 */
286static struct pci_device_id snd_atiixp_ids[] = {
287 { 0x1002, 0x4341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB200 */
288 { 0x1002, 0x4361, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB300 */
289 { 0x1002, 0x4370, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB400 */
290 { 0, }
291};
292
293MODULE_DEVICE_TABLE(pci, snd_atiixp_ids);
294
295
296/*
297 * lowlevel functions
298 */
299
300/*
301 * update the bits of the given register.
302 * return 1 if the bits changed.
303 */
74ee4ff1 304static int snd_atiixp_update_bits(struct atiixp *chip, unsigned int reg,
1da177e4
LT		 305 unsigned int mask, unsigned int value)
306{
307 void __iomem *addr = chip->remap_addr + reg;
308 unsigned int data, old_data;
309 old_data = data = readl(addr);
310 data &= ~mask;
311 data |= value;
312 if (old_data == data)
313 return 0;
314 writel(data, addr);
315 return 1;
316}
317
318/*
319 * macros for easy use
320 */
321#define atiixp_write(chip,reg,value) \
322 writel(value, chip->remap_addr + ATI_REG_##reg)
323#define atiixp_read(chip,reg) \
324 readl(chip->remap_addr + ATI_REG_##reg)
325#define atiixp_update(chip,reg,mask,val) \
326 snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
327
1da177e4
LT		 328/*
329 * handling DMA packets
330 *
331 * we allocate a linear buffer for the DMA, and split it to each packet.
332 * in a future version, a scatter-gather buffer should be implemented.
333 */
334
335#define ATI_DESC_LIST_SIZE \
74ee4ff1 336 PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc))
1da177e4
LT		 337
338/*
339 * build packets ring for the given buffer size.
340 *
341 * IXP handles the buffer descriptors, which are connected as a linked
342 * list. although we can change the list dynamically, in this version,
343 * a static RING of buffer descriptors is used.
344 *
345 * the ring is built in this function, and is set up to the hardware.
346 */
74ee4ff1
TI		 347static int atiixp_build_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
348 struct snd_pcm_substream *substream,
349 unsigned int periods,
350 unsigned int period_bytes)
1da177e4
LT		 351{
352 unsigned int i;
353 u32 addr, desc_addr;
354 unsigned long flags;
355
356 if (periods > ATI_MAX_DESCRIPTORS)
357 return -ENOMEM;
358
359 if (dma->desc_buf.area == NULL) {
74ee4ff1
TI		 360 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
361 snd_dma_pci_data(chip->pci),
362 ATI_DESC_LIST_SIZE,
363 &dma->desc_buf) < 0)
1da177e4
LT		 364 return -ENOMEM;
365 dma->period_bytes = dma->periods = 0; /* clear */
366 }
367
368 if (dma->periods == periods && dma->period_bytes == period_bytes)
369 return 0;
370
371 /* reset DMA before changing the descriptor table */
372 spin_lock_irqsave(&chip->reg_lock, flags);
373 writel(0, chip->remap_addr + dma->ops->llp_offset);
374 dma->ops->enable_dma(chip, 0);
375 dma->ops->enable_dma(chip, 1);
376 spin_unlock_irqrestore(&chip->reg_lock, flags);
377
378 /* fill the entries */
379 addr = (u32)substream->runtime->dma_addr;
380 desc_addr = (u32)dma->desc_buf.addr;
381 for (i = 0; i < periods; i++) {
74ee4ff1
TI		 382 struct atiixp_dma_desc *desc;
383 desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i];
1da177e4
LT		 384 desc->addr = cpu_to_le32(addr);
385 desc->status = 0;
386 desc->size = period_bytes >> 2; /* in dwords */
74ee4ff1 387 desc_addr += sizeof(struct atiixp_dma_desc);
1da177e4
LT		 388 if (i == periods - 1)
389 desc->next = cpu_to_le32((u32)dma->desc_buf.addr);
390 else
391 desc->next = cpu_to_le32(desc_addr);
392 addr += period_bytes;
393 }
394
395 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
396 chip->remap_addr + dma->ops->llp_offset);
397
398 dma->period_bytes = period_bytes;
399 dma->periods = periods;
400
401 return 0;
402}
403
404/*
405 * remove the ring buffer and release it if assigned
406 */
74ee4ff1
TI		 407static void atiixp_clear_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
408 struct snd_pcm_substream *substream)
1da177e4
LT		 409{
410 if (dma->desc_buf.area) {
411 writel(0, chip->remap_addr + dma->ops->llp_offset);
412 snd_dma_free_pages(&dma->desc_buf);
413 dma->desc_buf.area = NULL;
414 }
415}
416
417/*
418 * AC97 interface
419 */
74ee4ff1 420static int snd_atiixp_acquire_codec(struct atiixp *chip)
1da177e4
LT		 421{
422 int timeout = 1000;
423
424 while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) {
425 if (! timeout--) {
426 snd_printk(KERN_WARNING "atiixp: codec acquire timeout\n");
427 return -EBUSY;
428 }
429 udelay(1);
430 }
431 return 0;
432}
433
74ee4ff1 434static unsigned short snd_atiixp_codec_read(struct atiixp *chip, unsigned short codec, unsigned short reg)
1da177e4
LT		 435{
436 unsigned int data;
437 int timeout;
438
439 if (snd_atiixp_acquire_codec(chip) < 0)
440 return 0xffff;
441 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
442 ATI_REG_PHYS_OUT_ADDR_EN |
443 ATI_REG_PHYS_OUT_RW |
444 codec;
445 atiixp_write(chip, PHYS_OUT_ADDR, data);
446 if (snd_atiixp_acquire_codec(chip) < 0)
447 return 0xffff;
448 timeout = 1000;
449 do {
450 data = atiixp_read(chip, PHYS_IN_ADDR);
451 if (data & ATI_REG_PHYS_IN_READ_FLAG)
452 return data >> ATI_REG_PHYS_IN_DATA_SHIFT;
453 udelay(1);
454 } while (--timeout);
455 /* time out may happen during reset */
456 if (reg < 0x7c)
457 snd_printk(KERN_WARNING "atiixp: codec read timeout (reg %x)\n", reg);
458 return 0xffff;
459}
460
461
74ee4ff1
TI		 462static void snd_atiixp_codec_write(struct atiixp *chip, unsigned short codec,
463 unsigned short reg, unsigned short val)
1da177e4
LT		 464{
465 unsigned int data;
466
467 if (snd_atiixp_acquire_codec(chip) < 0)
468 return;
469 data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) |
470 ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
471 ATI_REG_PHYS_OUT_ADDR_EN | codec;
472 atiixp_write(chip, PHYS_OUT_ADDR, data);
473}
474
475
74ee4ff1
TI		 476static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97,
477 unsigned short reg)
1da177e4 478{
74ee4ff1 479 struct atiixp *chip = ac97->private_data;
1da177e4
LT		 480 return snd_atiixp_codec_read(chip, ac97->num, reg);
481
482}
483
74ee4ff1
TI		 484static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
485 unsigned short val)
1da177e4 486{
74ee4ff1 487 struct atiixp *chip = ac97->private_data;
1da177e4
LT		 488 snd_atiixp_codec_write(chip, ac97->num, reg, val);
489}
490
491/*
492 * reset AC link
493 */
74ee4ff1 494static int snd_atiixp_aclink_reset(struct atiixp *chip)
1da177e4
LT		 495{
496 int timeout;
497
498 /* reset powerdoewn */
499 if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0))
500 udelay(10);
501
502 /* perform a software reset */
503 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET);
504 atiixp_read(chip, CMD);
505 udelay(10);
506 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0);
507
508 timeout = 10;
509 while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) {
510 /* do a hard reset */
511 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
512 ATI_REG_CMD_AC_SYNC);
513 atiixp_read(chip, CMD);
74ee4ff1 514 mdelay(1);
1da177e4
LT		 515 atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
516 if (--timeout) {
517 snd_printk(KERN_ERR "atiixp: codec reset timeout\n");
518 break;
519 }
520 }
521
522 /* deassert RESET and assert SYNC to make sure */
523 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
524 ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET);
525
526 return 0;
527}
528
529#ifdef CONFIG_PM
74ee4ff1 530static int snd_atiixp_aclink_down(struct atiixp *chip)
1da177e4
LT		 531{
532 // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */
533 // return -EBUSY;
534 atiixp_update(chip, CMD,
535 ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET,
536 ATI_REG_CMD_POWERDOWN);
537 return 0;
538}
539#endif
540
541/*
542 * auto-detection of codecs
543 *
544 * the IXP chip can generate interrupts for the non-existing codecs.
545 * NEW_FRAME interrupt is used to make sure that the interrupt is generated
546 * even if all three codecs are connected.
547 */
548
549#define ALL_CODEC_NOT_READY \
550 (ATI_REG_ISR_CODEC0_NOT_READY |\
551 ATI_REG_ISR_CODEC1_NOT_READY |\
552 ATI_REG_ISR_CODEC2_NOT_READY)
553#define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME)
554
74ee4ff1 555static int snd_atiixp_codec_detect(struct atiixp *chip)
1da177e4
LT		 556{
557 int timeout;
558
559 chip->codec_not_ready_bits = 0;
560 atiixp_write(chip, IER, CODEC_CHECK_BITS);
561 /* wait for the interrupts */
bfdcbace 562 timeout = 50;
1da177e4 563 while (timeout-- > 0) {
74ee4ff1 564 mdelay(1);
1da177e4
LT		 565 if (chip->codec_not_ready_bits)
566 break;
567 }
568 atiixp_write(chip, IER, 0); /* disable irqs */
569
570 if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) {
571 snd_printk(KERN_ERR "atiixp: no codec detected!\n");
572 return -ENXIO;
573 }
574 return 0;
575}
576
577
578/*
579 * enable DMA and irqs
580 */
74ee4ff1 581static int snd_atiixp_chip_start(struct atiixp *chip)
1da177e4
LT		 582{
583 unsigned int reg;
584
585 /* set up spdif, enable burst mode */
586 reg = atiixp_read(chip, CMD);
587 reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT;
588 reg |= ATI_REG_CMD_BURST_EN;
589 atiixp_write(chip, CMD, reg);
590
591 reg = atiixp_read(chip, SPDF_CMD);
592 reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH);
593 atiixp_write(chip, SPDF_CMD, reg);
594
595 /* clear all interrupt source */
596 atiixp_write(chip, ISR, 0xffffffff);
597 /* enable irqs */
598 atiixp_write(chip, IER,
599 ATI_REG_IER_IO_STATUS_EN |
600 ATI_REG_IER_IN_XRUN_EN |
601 ATI_REG_IER_OUT_XRUN_EN |
602 ATI_REG_IER_SPDF_XRUN_EN |
603 ATI_REG_IER_SPDF_STATUS_EN);
604 return 0;
605}
606
607
608/*
609 * disable DMA and IRQs
610 */
74ee4ff1 611static int snd_atiixp_chip_stop(struct atiixp *chip)
1da177e4
LT		 612{
613 /* clear interrupt source */
614 atiixp_write(chip, ISR, atiixp_read(chip, ISR));
615 /* disable irqs */
616 atiixp_write(chip, IER, 0);
617 return 0;
618}
619
620
621/*
622 * PCM section
623 */
624
625/*
626 * pointer callback simplly reads XXX_DMA_DT_CUR register as the current
627 * position. when SG-buffer is implemented, the offset must be calculated
628 * correctly...
629 */
74ee4ff1 630static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream)
1da177e4 631{
74ee4ff1
TI		 632 struct atiixp *chip = snd_pcm_substream_chip(substream);
633 struct snd_pcm_runtime *runtime = substream->runtime;
634 struct atiixp_dma *dma = runtime->private_data;
1da177e4
LT		 635 unsigned int curptr;
636 int timeout = 1000;
637
638 while (timeout--) {
639 curptr = readl(chip->remap_addr + dma->ops->dt_cur);
640 if (curptr < dma->buf_addr)
641 continue;
642 curptr -= dma->buf_addr;
643 if (curptr >= dma->buf_bytes)
644 continue;
645 return bytes_to_frames(runtime, curptr);
646 }
647 snd_printd("atiixp: invalid DMA pointer read 0x%x (buf=%x)\n",
648 readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr);
649 return 0;
650}
651
652/*
653 * XRUN detected, and stop the PCM substream
654 */
74ee4ff1 655static void snd_atiixp_xrun_dma(struct atiixp *chip, struct atiixp_dma *dma)
1da177e4
LT		 656{
657 if (! dma->substream || ! dma->running)
658 return;
659 snd_printdd("atiixp: XRUN detected (DMA %d)\n", dma->ops->type);
660 snd_pcm_stop(dma->substream, SNDRV_PCM_STATE_XRUN);
661}
662
663/*
664 * the period ack. update the substream.
665 */
74ee4ff1 666static void snd_atiixp_update_dma(struct atiixp *chip, struct atiixp_dma *dma)
1da177e4
LT		 667{
668 if (! dma->substream || ! dma->running)
669 return;
670 snd_pcm_period_elapsed(dma->substream);
671}
672
673/* set BUS_BUSY interrupt bit if any DMA is running */
674/* call with spinlock held */
74ee4ff1 675static void snd_atiixp_check_bus_busy(struct atiixp *chip)
1da177e4
LT		 676{
677 unsigned int bus_busy;
678 if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN |
679 ATI_REG_CMD_RECEIVE_EN |
680 ATI_REG_CMD_SPDF_OUT_EN))
681 bus_busy = ATI_REG_IER_SET_BUS_BUSY;
682 else
683 bus_busy = 0;
684 atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy);
685}
686
687/* common trigger callback
688 * calling the lowlevel callbacks in it
689 */
74ee4ff1 690static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 691{
74ee4ff1
TI		 692 struct atiixp *chip = snd_pcm_substream_chip(substream);
693 struct atiixp_dma *dma = substream->runtime->private_data;
1da177e4
LT		 694 int err = 0;
695
696 snd_assert(dma->ops->enable_transfer && dma->ops->flush_dma, return -EINVAL);
697
698 spin_lock(&chip->reg_lock);
699 switch (cmd) {
700 case SNDRV_PCM_TRIGGER_START:
41e4845c
JK		 701 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
702 case SNDRV_PCM_TRIGGER_RESUME:
1da177e4
LT		 703 dma->ops->enable_transfer(chip, 1);
704 dma->running = 1;
41e4845c 705 dma->suspended = 0;
1da177e4
LT		 706 break;
707 case SNDRV_PCM_TRIGGER_STOP:
41e4845c
JK		 708 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
709 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 710 dma->ops->enable_transfer(chip, 0);
711 dma->running = 0;
41e4845c 712 dma->suspended = cmd == SNDRV_PCM_TRIGGER_SUSPEND;
1da177e4
LT		 713 break;
714 default:
715 err = -EINVAL;
716 break;
717 }
718 if (! err) {
719 snd_atiixp_check_bus_busy(chip);
720 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
721 dma->ops->flush_dma(chip);
722 snd_atiixp_check_bus_busy(chip);
723 }
724 }
725 spin_unlock(&chip->reg_lock);
726 return err;
727}
728
729
730/*
731 * lowlevel callbacks for each DMA type
732 *
733 * every callback is supposed to be called in chip->reg_lock spinlock
734 */
735
736/* flush FIFO of analog OUT DMA */
74ee4ff1 737static void atiixp_out_flush_dma(struct atiixp *chip)
1da177e4
LT		 738{
739 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH);
740}
741
742/* enable/disable analog OUT DMA */
74ee4ff1 743static void atiixp_out_enable_dma(struct atiixp *chip, int on)
1da177e4
LT		 744{
745 unsigned int data;
746 data = atiixp_read(chip, CMD);
747 if (on) {
748 if (data & ATI_REG_CMD_OUT_DMA_EN)
749 return;
750 atiixp_out_flush_dma(chip);
751 data |= ATI_REG_CMD_OUT_DMA_EN;
752 } else
753 data &= ~ATI_REG_CMD_OUT_DMA_EN;
754 atiixp_write(chip, CMD, data);
755}
756
757/* start/stop transfer over OUT DMA */
74ee4ff1 758static void atiixp_out_enable_transfer(struct atiixp *chip, int on)
1da177e4
LT		 759{
760 atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN,
761 on ? ATI_REG_CMD_SEND_EN : 0);
762}
763
764/* enable/disable analog IN DMA */
74ee4ff1 765static void atiixp_in_enable_dma(struct atiixp *chip, int on)
1da177e4
LT		 766{
767 atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN,
768 on ? ATI_REG_CMD_IN_DMA_EN : 0);
769}
770
771/* start/stop analog IN DMA */
74ee4ff1 772static void atiixp_in_enable_transfer(struct atiixp *chip, int on)
1da177e4
LT		 773{
774 if (on) {
775 unsigned int data = atiixp_read(chip, CMD);
776 if (! (data & ATI_REG_CMD_RECEIVE_EN)) {
777 data |= ATI_REG_CMD_RECEIVE_EN;
778#if 0 /* FIXME: this causes the endless loop */
779 /* wait until slot 3/4 are finished */
780 while ((atiixp_read(chip, COUNTER) &
781 ATI_REG_COUNTER_SLOT) != 5)
782 ;
783#endif
784 atiixp_write(chip, CMD, data);
785 }
786 } else
787 atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0);
788}
789
790/* flush FIFO of analog IN DMA */
74ee4ff1 791static void atiixp_in_flush_dma(struct atiixp *chip)
1da177e4
LT		 792{
793 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH);
794}
795
796/* enable/disable SPDIF OUT DMA */
74ee4ff1 797static void atiixp_spdif_enable_dma(struct atiixp *chip, int on)
1da177e4
LT		 798{
799 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN,
800 on ? ATI_REG_CMD_SPDF_DMA_EN : 0);
801}
802
803/* start/stop SPDIF OUT DMA */
74ee4ff1 804static void atiixp_spdif_enable_transfer(struct atiixp *chip, int on)
1da177e4
LT		 805{
806 unsigned int data;
807 data = atiixp_read(chip, CMD);
808 if (on)
809 data |= ATI_REG_CMD_SPDF_OUT_EN;
810 else
811 data &= ~ATI_REG_CMD_SPDF_OUT_EN;
812 atiixp_write(chip, CMD, data);
813}
814
815/* flush FIFO of SPDIF OUT DMA */
74ee4ff1 816static void atiixp_spdif_flush_dma(struct atiixp *chip)
1da177e4
LT		 817{
818 int timeout;
819
820 /* DMA off, transfer on */
821 atiixp_spdif_enable_dma(chip, 0);
822 atiixp_spdif_enable_transfer(chip, 1);
823
824 timeout = 100;
825 do {
826 if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED))
827 break;
828 udelay(1);
829 } while (timeout-- > 0);
830
831 atiixp_spdif_enable_transfer(chip, 0);
832}
833
834/* set up slots and formats for SPDIF OUT */
74ee4ff1 835static int snd_atiixp_spdif_prepare(struct snd_pcm_substream *substream)
1da177e4 836{
74ee4ff1 837 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 838
839 spin_lock_irq(&chip->reg_lock);
840 if (chip->spdif_over_aclink) {
841 unsigned int data;
842 /* enable slots 10/11 */
843 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK,
844 ATI_REG_CMD_SPDF_CONFIG_01);
845 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
846 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
847 ATI_REG_OUT_DMA_SLOT_BIT(11);
848 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
849 atiixp_write(chip, OUT_DMA_SLOT, data);
850 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
851 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
852 ATI_REG_CMD_INTERLEAVE_OUT : 0);
853 } else {
854 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0);
855 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0);
856 }
857 spin_unlock_irq(&chip->reg_lock);
858 return 0;
859}
860
861/* set up slots and formats for analog OUT */
74ee4ff1 862static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 863{
74ee4ff1 864 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 865 unsigned int data;
866
867 spin_lock_irq(&chip->reg_lock);
868 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
869 switch (substream->runtime->channels) {
870 case 8:
871 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
872 ATI_REG_OUT_DMA_SLOT_BIT(11);
873 /* fallthru */
874 case 6:
875 data |= ATI_REG_OUT_DMA_SLOT_BIT(7) |
876 ATI_REG_OUT_DMA_SLOT_BIT(8);
877 /* fallthru */
878 case 4:
879 data |= ATI_REG_OUT_DMA_SLOT_BIT(6) |
880 ATI_REG_OUT_DMA_SLOT_BIT(9);
881 /* fallthru */
882 default:
883 data |= ATI_REG_OUT_DMA_SLOT_BIT(3) |
884 ATI_REG_OUT_DMA_SLOT_BIT(4);
885 break;
886 }
887
888 /* set output threshold */
889 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
890 atiixp_write(chip, OUT_DMA_SLOT, data);
891
892 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
893 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
894 ATI_REG_CMD_INTERLEAVE_OUT : 0);
895
896 /*
897 * enable 6 channel re-ordering bit if needed
898 */
899 atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN,
900 substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0);
901
902 spin_unlock_irq(&chip->reg_lock);
903 return 0;
904}
905
906/* set up slots and formats for analog IN */
74ee4ff1 907static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 908{
74ee4ff1 909 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 910
911 spin_lock_irq(&chip->reg_lock);
912 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN,
913 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
914 ATI_REG_CMD_INTERLEAVE_IN : 0);
915 spin_unlock_irq(&chip->reg_lock);
916 return 0;
917}
918
919/*
920 * hw_params - allocate the buffer and set up buffer descriptors
921 */
74ee4ff1
TI		 922static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream,
923 struct snd_pcm_hw_params *hw_params)
1da177e4 924{
74ee4ff1
TI		 925 struct atiixp *chip = snd_pcm_substream_chip(substream);
926 struct atiixp_dma *dma = substream->runtime->private_data;
1da177e4
LT		 927 int err;
928
929 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
930 if (err < 0)
931 return err;
932 dma->buf_addr = substream->runtime->dma_addr;
933 dma->buf_bytes = params_buffer_bytes(hw_params);
934
935 err = atiixp_build_dma_packets(chip, dma, substream,
936 params_periods(hw_params),
937 params_period_bytes(hw_params));
938 if (err < 0)
939 return err;
940
941 if (dma->ac97_pcm_type >= 0) {
942 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
943 /* PCM is bound to AC97 codec(s)
944 * set up the AC97 codecs
945 */
946 if (dma->pcm_open_flag) {
947 snd_ac97_pcm_close(pcm);
948 dma->pcm_open_flag = 0;
949 }
950 err = snd_ac97_pcm_open(pcm, params_rate(hw_params),
951 params_channels(hw_params),
952 pcm->r[0].slots);
953 if (err >= 0)
954 dma->pcm_open_flag = 1;
955 }
956
957 return err;
958}
959
74ee4ff1 960static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4 961{
74ee4ff1
TI		 962 struct atiixp *chip = snd_pcm_substream_chip(substream);
963 struct atiixp_dma *dma = substream->runtime->private_data;
1da177e4
LT		 964
965 if (dma->pcm_open_flag) {
966 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
967 snd_ac97_pcm_close(pcm);
968 dma->pcm_open_flag = 0;
969 }
970 atiixp_clear_dma_packets(chip, dma, substream);
971 snd_pcm_lib_free_pages(substream);
972 return 0;
973}
974
975
976/*
977 * pcm hardware definition, identical for all DMA types
978 */
74ee4ff1 979static struct snd_pcm_hardware snd_atiixp_pcm_hw =
1da177e4
LT		 980{
981 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
982 SNDRV_PCM_INFO_BLOCK_TRANSFER |
41e4845c 983 SNDRV_PCM_INFO_PAUSE |
1da177e4
LT		 984 SNDRV_PCM_INFO_RESUME |
985 SNDRV_PCM_INFO_MMAP_VALID),
986 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
987 .rates = SNDRV_PCM_RATE_48000,
988 .rate_min = 48000,
989 .rate_max = 48000,
990 .channels_min = 2,
991 .channels_max = 2,
992 .buffer_bytes_max = 256 * 1024,
993 .period_bytes_min = 32,
994 .period_bytes_max = 128 * 1024,
995 .periods_min = 2,
996 .periods_max = ATI_MAX_DESCRIPTORS,
997};
998
74ee4ff1
TI		 999static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream,
1000 struct atiixp_dma *dma, int pcm_type)
1da177e4 1001{
74ee4ff1
TI		 1002 struct atiixp *chip = snd_pcm_substream_chip(substream);
1003 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1004 int err;
1005
1006 snd_assert(dma->ops && dma->ops->enable_dma, return -EINVAL);
1007
1008 if (dma->opened)
1009 return -EBUSY;
1010 dma->substream = substream;
1011 runtime->hw = snd_atiixp_pcm_hw;
1012 dma->ac97_pcm_type = pcm_type;
1013 if (pcm_type >= 0) {
1014 runtime->hw.rates = chip->pcms[pcm_type]->rates;
1015 snd_pcm_limit_hw_rates(runtime);
1016 } else {
1017 /* direct SPDIF */
1018 runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
1019 }
1020 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1021 return err;
1022 runtime->private_data = dma;
1023
1024 /* enable DMA bits */
1025 spin_lock_irq(&chip->reg_lock);
1026 dma->ops->enable_dma(chip, 1);
1027 spin_unlock_irq(&chip->reg_lock);
1028 dma->opened = 1;
1029
1030 return 0;
1031}
1032
74ee4ff1
TI		 1033static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream,
1034 struct atiixp_dma *dma)
1da177e4 1035{
74ee4ff1 1036 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1037 /* disable DMA bits */
1038 snd_assert(dma->ops && dma->ops->enable_dma, return -EINVAL);
1039 spin_lock_irq(&chip->reg_lock);
1040 dma->ops->enable_dma(chip, 0);
1041 spin_unlock_irq(&chip->reg_lock);
1042 dma->substream = NULL;
1043 dma->opened = 0;
1044 return 0;
1045}
1046
1047/*
1048 */
74ee4ff1 1049static int snd_atiixp_playback_open(struct snd_pcm_substream *substream)
1da177e4 1050{
74ee4ff1 1051 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1052 int err;
1053
1054 down(&chip->open_mutex);
1055 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0);
1056 up(&chip->open_mutex);
1057 if (err < 0)
1058 return err;
1059 substream->runtime->hw.channels_max = chip->max_channels;
1060 if (chip->max_channels > 2)
1061 /* channels must be even */
1062 snd_pcm_hw_constraint_step(substream->runtime, 0,
1063 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1064 return 0;
1065}
1066
74ee4ff1 1067static int snd_atiixp_playback_close(struct snd_pcm_substream *substream)
1da177e4 1068{
74ee4ff1 1069 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1070 int err;
1071 down(&chip->open_mutex);
1072 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
1073 up(&chip->open_mutex);
1074 return err;
1075}
1076
74ee4ff1 1077static int snd_atiixp_capture_open(struct snd_pcm_substream *substream)
1da177e4 1078{
74ee4ff1 1079 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1080 return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1);
1081}
1082
74ee4ff1 1083static int snd_atiixp_capture_close(struct snd_pcm_substream *substream)
1da177e4 1084{
74ee4ff1 1085 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1086 return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]);
1087}
1088
74ee4ff1 1089static int snd_atiixp_spdif_open(struct snd_pcm_substream *substream)
1da177e4 1090{
74ee4ff1 1091 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1092 int err;
1093 down(&chip->open_mutex);
1094 if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */
1095 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2);
1096 else
1097 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1);
1098 up(&chip->open_mutex);
1099 return err;
1100}
1101
74ee4ff1 1102static int snd_atiixp_spdif_close(struct snd_pcm_substream *substream)
1da177e4 1103{
74ee4ff1 1104 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1105 int err;
1106 down(&chip->open_mutex);
1107 if (chip->spdif_over_aclink)
1108 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
1109 else
1110 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]);
1111 up(&chip->open_mutex);
1112 return err;
1113}
1114
1115/* AC97 playback */
74ee4ff1 1116static struct snd_pcm_ops snd_atiixp_playback_ops = {
1da177e4
LT		 1117 .open = snd_atiixp_playback_open,
1118 .close = snd_atiixp_playback_close,
1119 .ioctl = snd_pcm_lib_ioctl,
1120 .hw_params = snd_atiixp_pcm_hw_params,
1121 .hw_free = snd_atiixp_pcm_hw_free,
1122 .prepare = snd_atiixp_playback_prepare,
1123 .trigger = snd_atiixp_pcm_trigger,
1124 .pointer = snd_atiixp_pcm_pointer,
1125};
1126
1127/* AC97 capture */
74ee4ff1 1128static struct snd_pcm_ops snd_atiixp_capture_ops = {
1da177e4
LT		 1129 .open = snd_atiixp_capture_open,
1130 .close = snd_atiixp_capture_close,
1131 .ioctl = snd_pcm_lib_ioctl,
1132 .hw_params = snd_atiixp_pcm_hw_params,
1133 .hw_free = snd_atiixp_pcm_hw_free,
1134 .prepare = snd_atiixp_capture_prepare,
1135 .trigger = snd_atiixp_pcm_trigger,
1136 .pointer = snd_atiixp_pcm_pointer,
1137};
1138
1139/* SPDIF playback */
74ee4ff1 1140static struct snd_pcm_ops snd_atiixp_spdif_ops = {
1da177e4
LT		 1141 .open = snd_atiixp_spdif_open,
1142 .close = snd_atiixp_spdif_close,
1143 .ioctl = snd_pcm_lib_ioctl,
1144 .hw_params = snd_atiixp_pcm_hw_params,
1145 .hw_free = snd_atiixp_pcm_hw_free,
1146 .prepare = snd_atiixp_spdif_prepare,
1147 .trigger = snd_atiixp_pcm_trigger,
1148 .pointer = snd_atiixp_pcm_pointer,
1149};
1150
1151static struct ac97_pcm atiixp_pcm_defs[] __devinitdata = {
1152 /* front PCM */
1153 {
1154 .exclusive = 1,
1155 .r = { {
1156 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1157 (1 << AC97_SLOT_PCM_RIGHT) |
1158 (1 << AC97_SLOT_PCM_CENTER) |
1159 (1 << AC97_SLOT_PCM_SLEFT) |
1160 (1 << AC97_SLOT_PCM_SRIGHT) |
1161 (1 << AC97_SLOT_LFE)
1162 }
1163 }
1164 },
1165 /* PCM IN #1 */
1166 {
1167 .stream = 1,
1168 .exclusive = 1,
1169 .r = { {
1170 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1171 (1 << AC97_SLOT_PCM_RIGHT)
1172 }
1173 }
1174 },
1175 /* S/PDIF OUT (optional) */
1176 {
1177 .exclusive = 1,
1178 .spdif = 1,
1179 .r = { {
1180 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1181 (1 << AC97_SLOT_SPDIF_RIGHT2)
1182 }
1183 }
1184 },
1185};
1186
74ee4ff1 1187static struct atiixp_dma_ops snd_atiixp_playback_dma_ops = {
1da177e4
LT		 1188 .type = ATI_DMA_PLAYBACK,
1189 .llp_offset = ATI_REG_OUT_DMA_LINKPTR,
1190 .dt_cur = ATI_REG_OUT_DMA_DT_CUR,
1191 .enable_dma = atiixp_out_enable_dma,
1192 .enable_transfer = atiixp_out_enable_transfer,
1193 .flush_dma = atiixp_out_flush_dma,
1194};
1195
74ee4ff1 1196static struct atiixp_dma_ops snd_atiixp_capture_dma_ops = {
1da177e4
LT		 1197 .type = ATI_DMA_CAPTURE,
1198 .llp_offset = ATI_REG_IN_DMA_LINKPTR,
1199 .dt_cur = ATI_REG_IN_DMA_DT_CUR,
1200 .enable_dma = atiixp_in_enable_dma,
1201 .enable_transfer = atiixp_in_enable_transfer,
1202 .flush_dma = atiixp_in_flush_dma,
1203};
1204
74ee4ff1 1205static struct atiixp_dma_ops snd_atiixp_spdif_dma_ops = {
1da177e4
LT		 1206 .type = ATI_DMA_SPDIF,
1207 .llp_offset = ATI_REG_SPDF_DMA_LINKPTR,
1208 .dt_cur = ATI_REG_SPDF_DMA_DT_CUR,
1209 .enable_dma = atiixp_spdif_enable_dma,
1210 .enable_transfer = atiixp_spdif_enable_transfer,
1211 .flush_dma = atiixp_spdif_flush_dma,
1212};
1213
1214
74ee4ff1 1215static int __devinit snd_atiixp_pcm_new(struct atiixp *chip)
1da177e4 1216{
74ee4ff1
TI		 1217 struct snd_pcm *pcm;
1218 struct snd_ac97_bus *pbus = chip->ac97_bus;
1da177e4
LT		 1219 int err, i, num_pcms;
1220
1221 /* initialize constants */
1222 chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops;
1223 chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops;
1224 if (! chip->spdif_over_aclink)
1225 chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops;
1226
1227 /* assign AC97 pcm */
1228 if (chip->spdif_over_aclink)
1229 num_pcms = 3;
1230 else
1231 num_pcms = 2;
1232 err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs);
1233 if (err < 0)
1234 return err;
1235 for (i = 0; i < num_pcms; i++)
1236 chip->pcms[i] = &pbus->pcms[i];
1237
1238 chip->max_channels = 2;
1239 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
1240 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE))
1241 chip->max_channels = 6;
1242 else
1243 chip->max_channels = 4;
1244 }
1245
1246 /* PCM #0: analog I/O */
74ee4ff1
TI		 1247 err = snd_pcm_new(chip->card, "ATI IXP AC97",
1248 ATI_PCMDEV_ANALOG, 1, 1, &pcm);
1da177e4
LT		 1249 if (err < 0)
1250 return err;
1251 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops);
1252 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops);
1253 pcm->private_data = chip;
1254 strcpy(pcm->name, "ATI IXP AC97");
1255 chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm;
1256
1257 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
74ee4ff1
TI		 1258 snd_dma_pci_data(chip->pci),
1259 64*1024, 128*1024);
1da177e4
LT		 1260
1261 /* no SPDIF support on codec? */
1262 if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates)
1263 return 0;
1264
1265 /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */
1266 if (chip->pcms[ATI_PCM_SPDIF])
1267 chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000;
1268
1269 /* PCM #1: spdif playback */
74ee4ff1
TI		 1270 err = snd_pcm_new(chip->card, "ATI IXP IEC958",
1271 ATI_PCMDEV_DIGITAL, 1, 0, &pcm);
1da177e4
LT		 1272 if (err < 0)
1273 return err;
1274 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops);
1275 pcm->private_data = chip;
1276 if (chip->spdif_over_aclink)
1277 strcpy(pcm->name, "ATI IXP IEC958 (AC97)");
1278 else
1279 strcpy(pcm->name, "ATI IXP IEC958 (Direct)");
1280 chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm;
1281
1282 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
74ee4ff1
TI		 1283 snd_dma_pci_data(chip->pci),
1284 64*1024, 128*1024);
1da177e4
LT		 1285
1286 /* pre-select AC97 SPDIF slots 10/11 */
1287 for (i = 0; i < NUM_ATI_CODECS; i++) {
1288 if (chip->ac97[i])
74ee4ff1
TI		 1289 snd_ac97_update_bits(chip->ac97[i],
1290 AC97_EXTENDED_STATUS,
1291 0x03 << 4, 0x03 << 4);
1da177e4
LT		 1292 }
1293
1294 return 0;
1295}
1296
1297
1298
1299/*
1300 * interrupt handler
1301 */
1302static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1303{
74ee4ff1 1304 struct atiixp *chip = dev_id;
1da177e4
LT		 1305 unsigned int status;
1306
1307 status = atiixp_read(chip, ISR);
1308
1309 if (! status)
1310 return IRQ_NONE;
1311
1312 /* process audio DMA */
1313 if (status & ATI_REG_ISR_OUT_XRUN)
1314 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1315 else if (status & ATI_REG_ISR_OUT_STATUS)
1316 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1317 if (status & ATI_REG_ISR_IN_XRUN)
1318 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1319 else if (status & ATI_REG_ISR_IN_STATUS)
1320 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1321 if (! chip->spdif_over_aclink) {
1322 if (status & ATI_REG_ISR_SPDF_XRUN)
1323 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1324 else if (status & ATI_REG_ISR_SPDF_STATUS)
1325 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1326 }
1327
1328 /* for codec detection */
1329 if (status & CODEC_CHECK_BITS) {
1330 unsigned int detected;
1331 detected = status & CODEC_CHECK_BITS;
1332 spin_lock(&chip->reg_lock);
1333 chip->codec_not_ready_bits |= detected;
1334 atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
1335 spin_unlock(&chip->reg_lock);
1336 }
1337
1338 /* ack */
1339 atiixp_write(chip, ISR, status);
1340
1341 return IRQ_HANDLED;
1342}
1343
1344
1345/*
1346 * ac97 mixer section
1347 */
1348
1349static struct ac97_quirk ac97_quirks[] __devinitdata = {
1350 {
69ad07cf
JK		 1351 .subvendor = 0x103c,
1352 .subdevice = 0x006b,
1da177e4
LT		 1353 .name = "HP Pavilion ZV5030US",
1354 .type = AC97_TUNE_MUTE_LED
1355 },
1356 { } /* terminator */
1357};
1358
74ee4ff1
TI		 1359static int __devinit snd_atiixp_mixer_new(struct atiixp *chip, int clock,
1360 const char *quirk_override)
1da177e4 1361{
74ee4ff1
TI		 1362 struct snd_ac97_bus *pbus;
1363 struct snd_ac97_template ac97;
1da177e4
LT		 1364 int i, err;
1365 int codec_count;
74ee4ff1 1366 static struct snd_ac97_bus_ops ops = {
1da177e4
LT		 1367 .write = snd_atiixp_ac97_write,
1368 .read = snd_atiixp_ac97_read,
1369 };
1370 static unsigned int codec_skip[NUM_ATI_CODECS] = {
1371 ATI_REG_ISR_CODEC0_NOT_READY,
1372 ATI_REG_ISR_CODEC1_NOT_READY,
1373 ATI_REG_ISR_CODEC2_NOT_READY,
1374 };
1375
1376 if (snd_atiixp_codec_detect(chip) < 0)
1377 return -ENXIO;
1378
1379 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
1380 return err;
1381 pbus->clock = clock;
1da177e4
LT		 1382 chip->ac97_bus = pbus;
1383
1384 codec_count = 0;
1385 for (i = 0; i < NUM_ATI_CODECS; i++) {
1386 if (chip->codec_not_ready_bits & codec_skip[i])
1387 continue;
1388 memset(&ac97, 0, sizeof(ac97));
1389 ac97.private_data = chip;
1390 ac97.pci = chip->pci;
1391 ac97.num = i;
1392 ac97.scaps = AC97_SCAP_SKIP_MODEM;
1393 if (! chip->spdif_over_aclink)
1394 ac97.scaps |= AC97_SCAP_NO_SPDIF;
1395 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
1396 chip->ac97[i] = NULL; /* to be sure */
1397 snd_printdd("atiixp: codec %d not available for audio\n", i);
1398 continue;
1399 }
1400 codec_count++;
1401 }
1402
1403 if (! codec_count) {
1404 snd_printk(KERN_ERR "atiixp: no codec available\n");
1405 return -ENODEV;
1406 }
1407
1408 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
1409
1410 return 0;
1411}
1412
1413
1414#ifdef CONFIG_PM
1415/*
1416 * power management
1417 */
92304cc7 1418static int snd_atiixp_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 1419{
92304cc7
TI		 1420 struct snd_card *card = pci_get_drvdata(pci);
1421 struct atiixp *chip = card->private_data;
1da177e4
LT		 1422 int i;
1423
92304cc7 1424 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1da177e4
LT		 1425 for (i = 0; i < NUM_ATI_PCMDEVS; i++)
1426 if (chip->pcmdevs[i]) {
74ee4ff1 1427 struct atiixp_dma *dma = &chip->dmas[i];
1da177e4 1428 if (dma->substream && dma->running)
74ee4ff1
TI		 1429 dma->saved_curptr = readl(chip->remap_addr +
1430 dma->ops->dt_cur);
1da177e4
LT		 1431 snd_pcm_suspend_all(chip->pcmdevs[i]);
1432 }
1433 for (i = 0; i < NUM_ATI_CODECS; i++)
92304cc7 1434 snd_ac97_suspend(chip->ac97[i]);
1da177e4
LT		 1435 snd_atiixp_aclink_down(chip);
1436 snd_atiixp_chip_stop(chip);
1437
92304cc7
TI		 1438 pci_set_power_state(pci, PCI_D3hot);
1439 pci_disable_device(pci);
1440 pci_save_state(pci);
1da177e4
LT		 1441 return 0;
1442}
1443
92304cc7 1444static int snd_atiixp_resume(struct pci_dev *pci)
1da177e4 1445{
92304cc7
TI		 1446 struct snd_card *card = pci_get_drvdata(pci);
1447 struct atiixp *chip = card->private_data;
1da177e4
LT		 1448 int i;
1449
92304cc7
TI		 1450 pci_restore_state(pci);
1451 pci_enable_device(pci);
1452 pci_set_power_state(pci, PCI_D0);
1453 pci_set_master(pci);
1da177e4
LT		 1454
1455 snd_atiixp_aclink_reset(chip);
1456 snd_atiixp_chip_start(chip);
1457
1458 for (i = 0; i < NUM_ATI_CODECS; i++)
92304cc7 1459 snd_ac97_resume(chip->ac97[i]);
1da177e4
LT		 1460
1461 for (i = 0; i < NUM_ATI_PCMDEVS; i++)
1462 if (chip->pcmdevs[i]) {
74ee4ff1 1463 struct atiixp_dma *dma = &chip->dmas[i];
41e4845c 1464 if (dma->substream && dma->suspended) {
1da177e4 1465 dma->ops->enable_dma(chip, 1);
8e3d759d 1466 dma->substream->ops->prepare(dma->substream);
1da177e4
LT		 1467 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
1468 chip->remap_addr + dma->ops->llp_offset);
74ee4ff1
TI		 1469 writel(dma->saved_curptr, chip->remap_addr +
1470 dma->ops->dt_cur);
1da177e4
LT		 1471 }
1472 }
1473
92304cc7 1474 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 1475 return 0;
1476}
1477#endif /* CONFIG_PM */
1478
1479
adf1b3d2 1480#ifdef CONFIG_PROC_FS
1da177e4
LT		 1481/*
1482 * proc interface for register dump
1483 */
1484
74ee4ff1
TI		 1485static void snd_atiixp_proc_read(struct snd_info_entry *entry,
1486 struct snd_info_buffer *buffer)
1da177e4 1487{
74ee4ff1 1488 struct atiixp *chip = entry->private_data;
1da177e4
LT		 1489 int i;
1490
1491 for (i = 0; i < 256; i += 4)
1492 snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i));
1493}
1494
74ee4ff1 1495static void __devinit snd_atiixp_proc_init(struct atiixp *chip)
1da177e4 1496{
74ee4ff1 1497 struct snd_info_entry *entry;
1da177e4
LT		 1498
1499 if (! snd_card_proc_new(chip->card, "atiixp", &entry))
1500 snd_info_set_text_ops(entry, chip, 1024, snd_atiixp_proc_read);
1501}
adf1b3d2
TI		 1502#else /* !CONFIG_PROC_FS */
1503#define snd_atiixp_proc_init(chip)
1504#endif
1da177e4
LT		 1505
1506
1507/*
1508 * destructor
1509 */
1510
74ee4ff1 1511static int snd_atiixp_free(struct atiixp *chip)
1da177e4
LT		 1512{
1513 if (chip->irq < 0)
1514 goto __hw_end;
1515 snd_atiixp_chip_stop(chip);
1516 synchronize_irq(chip->irq);
1517 __hw_end:
1518 if (chip->irq >= 0)
74ee4ff1 1519 free_irq(chip->irq, chip);
1da177e4
LT		 1520 if (chip->remap_addr)
1521 iounmap(chip->remap_addr);
1522 pci_release_regions(chip->pci);
1523 pci_disable_device(chip->pci);
1524 kfree(chip);
1525 return 0;
1526}
1527
74ee4ff1 1528static int snd_atiixp_dev_free(struct snd_device *device)
1da177e4 1529{
74ee4ff1 1530 struct atiixp *chip = device->device_data;
1da177e4
LT		 1531 return snd_atiixp_free(chip);
1532}
1533
1534/*
1535 * constructor for chip instance
1536 */
74ee4ff1 1537static int __devinit snd_atiixp_create(struct snd_card *card,
1da177e4 1538 struct pci_dev *pci,
74ee4ff1 1539 struct atiixp **r_chip)
1da177e4 1540{
74ee4ff1 1541 static struct snd_device_ops ops = {
1da177e4
LT		 1542 .dev_free = snd_atiixp_dev_free,
1543 };
74ee4ff1 1544 struct atiixp *chip;
1da177e4
LT		 1545 int err;
1546
1547 if ((err = pci_enable_device(pci)) < 0)
1548 return err;
1549
e560d8d8 1550 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 1551 if (chip == NULL) {
1552 pci_disable_device(pci);
1553 return -ENOMEM;
1554 }
1555
1556 spin_lock_init(&chip->reg_lock);
1557 init_MUTEX(&chip->open_mutex);
1558 chip->card = card;
1559 chip->pci = pci;
1560 chip->irq = -1;
1561 if ((err = pci_request_regions(pci, "ATI IXP AC97")) < 0) {
1562 pci_disable_device(pci);
1563 kfree(chip);
1564 return err;
1565 }
1566 chip->addr = pci_resource_start(pci, 0);
1567 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci, 0));
1568 if (chip->remap_addr == NULL) {
1569 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
1570 snd_atiixp_free(chip);
1571 return -EIO;
1572 }
1573
74ee4ff1
TI		 1574 if (request_irq(pci->irq, snd_atiixp_interrupt, SA_INTERRUPT|SA_SHIRQ,
1575 card->shortname, chip)) {
1da177e4
LT		 1576 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1577 snd_atiixp_free(chip);
1578 return -EBUSY;
1579 }
1580 chip->irq = pci->irq;
1581 pci_set_master(pci);
1582 synchronize_irq(chip->irq);
1583
1584 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1585 snd_atiixp_free(chip);
1586 return err;
1587 }
1588
1589 snd_card_set_dev(card, &pci->dev);
1590
1591 *r_chip = chip;
1592 return 0;
1593}
1594
1595
1596static int __devinit snd_atiixp_probe(struct pci_dev *pci,
1597 const struct pci_device_id *pci_id)
1598{
74ee4ff1
TI		 1599 struct snd_card *card;
1600 struct atiixp *chip;
1da177e4
LT		 1601 unsigned char revision;
1602 int err;
1603
b7fe4622 1604 card = snd_card_new(index, id, THIS_MODULE, 0);
1da177e4
LT		 1605 if (card == NULL)
1606 return -ENOMEM;
1607
1608 pci_read_config_byte(pci, PCI_REVISION_ID, &revision);
1609
b7fe4622 1610 strcpy(card->driver, spdif_aclink ? "ATIIXP" : "ATIIXP-SPDMA");
1da177e4
LT		 1611 strcpy(card->shortname, "ATI IXP");
1612 if ((err = snd_atiixp_create(card, pci, &chip)) < 0)
1613 goto __error;
92304cc7 1614 card->private_data = chip;
1da177e4
LT		 1615
1616 if ((err = snd_atiixp_aclink_reset(chip)) < 0)
1617 goto __error;
1618
b7fe4622 1619 chip->spdif_over_aclink = spdif_aclink;
1da177e4 1620
b7fe4622 1621 if ((err = snd_atiixp_mixer_new(chip, ac97_clock, ac97_quirk)) < 0)
1da177e4
LT		 1622 goto __error;
1623
1624 if ((err = snd_atiixp_pcm_new(chip)) < 0)
1625 goto __error;
1626
1627 snd_atiixp_proc_init(chip);
1628
1629 snd_atiixp_chip_start(chip);
1630
1631 snprintf(card->longname, sizeof(card->longname),
1632 "%s rev %x with %s at %#lx, irq %i", card->shortname, revision,
1633 chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?",
1634 chip->addr, chip->irq);
1635
1da177e4
LT		 1636 if ((err = snd_card_register(card)) < 0)
1637 goto __error;
1638
1639 pci_set_drvdata(pci, card);
1da177e4
LT		 1640 return 0;
1641
1642 __error:
1643 snd_card_free(card);
1644 return err;
1645}
1646
1647static void __devexit snd_atiixp_remove(struct pci_dev *pci)
1648{
1649 snd_card_free(pci_get_drvdata(pci));
1650 pci_set_drvdata(pci, NULL);
1651}
1652
1653static struct pci_driver driver = {
1654 .name = "ATI IXP AC97 controller",
1655 .id_table = snd_atiixp_ids,
1656 .probe = snd_atiixp_probe,
1657 .remove = __devexit_p(snd_atiixp_remove),
92304cc7
TI		 1658#ifdef CONFIG_PM
1659 .suspend = snd_atiixp_suspend,
1660 .resume = snd_atiixp_resume,
1661#endif
1da177e4
LT		 1662};
1663
1664
1665static int __init alsa_card_atiixp_init(void)
1666{
01d25d46 1667 return pci_register_driver(&driver);
1da177e4
LT		 1668}
1669
1670static void __exit alsa_card_atiixp_exit(void)
1671{
1672 pci_unregister_driver(&driver);
1673}
1674
1675module_init(alsa_card_atiixp_init)
1676module_exit(alsa_card_atiixp_exit)
kernel source for telekom puls (alcatel/mediatek)