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md: Add in export.h for files using EXPORT_SYMBOL
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / pci / atiixp.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for ATI IXP 150/200/250/300 AC97 controllers
3 *
4 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
1da177e4
LT		 22#include <asm/io.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/pci.h>
27#include <linux/slab.h>
28#include <linux/moduleparam.h>
62932df8 29#include <linux/mutex.h>
1da177e4
LT		 30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/info.h>
34#include <sound/ac97_codec.h>
35#include <sound/initval.h>
36
37MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
38MODULE_DESCRIPTION("ATI IXP AC97 controller");
39MODULE_LICENSE("GPL");
f4446ea0 40MODULE_SUPPORTED_DEVICE("{{ATI,IXP150/200/250/300/400/600}}");
1da177e4 41
b7fe4622
CL		 42static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
43static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
44static int ac97_clock = 48000;
45static char *ac97_quirk;
46static int spdif_aclink = 1;
14e1d357 47static int ac97_codec = -1;
b7fe4622
CL		 48
49module_param(index, int, 0444);
1da177e4 50MODULE_PARM_DESC(index, "Index value for ATI IXP controller.");
b7fe4622 51module_param(id, charp, 0444);
1da177e4 52MODULE_PARM_DESC(id, "ID string for ATI IXP controller.");
b7fe4622 53module_param(ac97_clock, int, 0444);
1da177e4 54MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
b7fe4622 55module_param(ac97_quirk, charp, 0444);
1da177e4 56MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
14e1d357
DC		 57module_param(ac97_codec, int, 0444);
58MODULE_PARM_DESC(ac97_codec, "Specify codec instead of probing.");
b7fe4622 59module_param(spdif_aclink, bool, 0444);
1da177e4
LT		 60MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
61
2b3e584b
TI		 62/* just for backward compatibility */
63static int enable;
698444f3 64module_param(enable, bool, 0444);
2b3e584b 65
1da177e4
LT		 66
67/*
68 */
69
70#define ATI_REG_ISR 0x00 /* interrupt source */
71#define ATI_REG_ISR_IN_XRUN (1U<<0)
72#define ATI_REG_ISR_IN_STATUS (1U<<1)
73#define ATI_REG_ISR_OUT_XRUN (1U<<2)
74#define ATI_REG_ISR_OUT_STATUS (1U<<3)
75#define ATI_REG_ISR_SPDF_XRUN (1U<<4)
76#define ATI_REG_ISR_SPDF_STATUS (1U<<5)
77#define ATI_REG_ISR_PHYS_INTR (1U<<8)
78#define ATI_REG_ISR_PHYS_MISMATCH (1U<<9)
79#define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10)
80#define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11)
81#define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12)
82#define ATI_REG_ISR_NEW_FRAME (1U<<13)
83
84#define ATI_REG_IER 0x04 /* interrupt enable */
85#define ATI_REG_IER_IN_XRUN_EN (1U<<0)
86#define ATI_REG_IER_IO_STATUS_EN (1U<<1)
87#define ATI_REG_IER_OUT_XRUN_EN (1U<<2)
88#define ATI_REG_IER_OUT_XRUN_COND (1U<<3)
89#define ATI_REG_IER_SPDF_XRUN_EN (1U<<4)
90#define ATI_REG_IER_SPDF_STATUS_EN (1U<<5)
91#define ATI_REG_IER_PHYS_INTR_EN (1U<<8)
92#define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9)
93#define ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
94#define ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
95#define ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
96#define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */
97#define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */
98
99#define ATI_REG_CMD 0x08 /* command */
100#define ATI_REG_CMD_POWERDOWN (1U<<0)
101#define ATI_REG_CMD_RECEIVE_EN (1U<<1)
102#define ATI_REG_CMD_SEND_EN (1U<<2)
103#define ATI_REG_CMD_STATUS_MEM (1U<<3)
104#define ATI_REG_CMD_SPDF_OUT_EN (1U<<4)
105#define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5)
106#define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6)
107#define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6
108#define ATI_REG_CMD_IN_DMA_EN (1U<<8)
109#define ATI_REG_CMD_OUT_DMA_EN (1U<<9)
110#define ATI_REG_CMD_SPDF_DMA_EN (1U<<10)
111#define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11)
112#define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12)
113#define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12)
114#define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12)
115#define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12)
116#define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12)
117#define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16)
118#define ATI_REG_CMD_AUDIO_PRESENT (1U<<20)
119#define ATI_REG_CMD_INTERLEAVE_IN (1U<<21)
120#define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22)
121#define ATI_REG_CMD_LOOPBACK_EN (1U<<23)
122#define ATI_REG_CMD_PACKED_DIS (1U<<24)
123#define ATI_REG_CMD_BURST_EN (1U<<25)
124#define ATI_REG_CMD_PANIC_EN (1U<<26)
125#define ATI_REG_CMD_MODEM_PRESENT (1U<<27)
126#define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28)
127#define ATI_REG_CMD_AC_SOFT_RESET (1U<<29)
128#define ATI_REG_CMD_AC_SYNC (1U<<30)
129#define ATI_REG_CMD_AC_RESET (1U<<31)
130
131#define ATI_REG_PHYS_OUT_ADDR 0x0c
132#define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
133#define ATI_REG_PHYS_OUT_RW (1U<<2)
134#define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8)
135#define ATI_REG_PHYS_OUT_ADDR_SHIFT 9
136#define ATI_REG_PHYS_OUT_DATA_SHIFT 16
137
138#define ATI_REG_PHYS_IN_ADDR 0x10
139#define ATI_REG_PHYS_IN_READ_FLAG (1U<<8)
140#define ATI_REG_PHYS_IN_ADDR_SHIFT 9
141#define ATI_REG_PHYS_IN_DATA_SHIFT 16
142
143#define ATI_REG_SLOTREQ 0x14
144
145#define ATI_REG_COUNTER 0x18
146#define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
147#define ATI_REG_COUNTER_BITCLOCK (31U<<8)
148
149#define ATI_REG_IN_FIFO_THRESHOLD 0x1c
150
151#define ATI_REG_IN_DMA_LINKPTR 0x20
152#define ATI_REG_IN_DMA_DT_START 0x24 /* RO */
153#define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */
154#define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */
155#define ATI_REG_IN_DMA_DT_SIZE 0x30
156
157#define ATI_REG_OUT_DMA_SLOT 0x34
158#define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3))
159#define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff
160#define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800
161#define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11
162
163#define ATI_REG_OUT_DMA_LINKPTR 0x38
164#define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */
165#define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */
166#define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */
167#define ATI_REG_OUT_DMA_DT_SIZE 0x48
168
169#define ATI_REG_SPDF_CMD 0x4c
170#define ATI_REG_SPDF_CMD_LFSR (1U<<4)
171#define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5)
172#define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */
173
174#define ATI_REG_SPDF_DMA_LINKPTR 0x50
175#define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */
176#define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */
177#define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */
178#define ATI_REG_SPDF_DMA_DT_SIZE 0x60
179
180#define ATI_REG_MODEM_MIRROR 0x7c
181#define ATI_REG_AUDIO_MIRROR 0x80
182
183#define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */
184#define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
185
186#define ATI_REG_FIFO_FLUSH 0x88
187#define ATI_REG_FIFO_OUT_FLUSH (1U<<0)
188#define ATI_REG_FIFO_IN_FLUSH (1U<<1)
189
190/* LINKPTR */
191#define ATI_REG_LINKPTR_EN (1U<<0)
192
193/* [INT|OUT|SPDIF]_DMA_DT_SIZE */
194#define ATI_REG_DMA_DT_SIZE (0xffffU<<0)
195#define ATI_REG_DMA_FIFO_USED (0x1fU<<16)
196#define ATI_REG_DMA_FIFO_FREE (0x1fU<<21)
197#define ATI_REG_DMA_STATE (7U<<26)
198
199
200#define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */
201
202
74ee4ff1 203struct atiixp;
1da177e4
LT		 204
205/*
206 * DMA packate descriptor
207 */
208
74ee4ff1 209struct atiixp_dma_desc {
1da177e4
LT		 210 u32 addr; /* DMA buffer address */
211 u16 status; /* status bits */
212 u16 size; /* size of the packet in dwords */
213 u32 next; /* address of the next packet descriptor */
74ee4ff1 214};
1da177e4
LT		 215
216/*
217 * stream enum
218 */
219enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */
220enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */
221enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */
222
223#define NUM_ATI_CODECS 3
224
225
226/*
227 * constants and callbacks for each DMA type
228 */
74ee4ff1 229struct atiixp_dma_ops {
1da177e4
LT		 230 int type; /* ATI_DMA_XXX */
231 unsigned int llp_offset; /* LINKPTR offset */
232 unsigned int dt_cur; /* DT_CUR offset */
74ee4ff1
TI		 233 /* called from open callback */
234 void (*enable_dma)(struct atiixp *chip, int on);
235 /* called from trigger (START/STOP) */
236 void (*enable_transfer)(struct atiixp *chip, int on);
237 /* called from trigger (STOP only) */
238 void (*flush_dma)(struct atiixp *chip);
1da177e4
LT		 239};
240
241/*
242 * DMA stream
243 */
74ee4ff1
TI		 244struct atiixp_dma {
245 const struct atiixp_dma_ops *ops;
1da177e4 246 struct snd_dma_buffer desc_buf;
74ee4ff1 247 struct snd_pcm_substream *substream; /* assigned PCM substream */
1da177e4
LT		 248 unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */
249 unsigned int period_bytes, periods;
250 int opened;
251 int running;
41e4845c 252 int suspended;
1da177e4
LT		 253 int pcm_open_flag;
254 int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */
255 unsigned int saved_curptr;
256};
257
258/*
259 * ATI IXP chip
260 */
74ee4ff1
TI		 261struct atiixp {
262 struct snd_card *card;
1da177e4
LT		 263 struct pci_dev *pci;
264
265 unsigned long addr;
266 void __iomem *remap_addr;
267 int irq;
268
74ee4ff1
TI		 269 struct snd_ac97_bus *ac97_bus;
270 struct snd_ac97 *ac97[NUM_ATI_CODECS];
1da177e4
LT		 271
272 spinlock_t reg_lock;
273
74ee4ff1 274 struct atiixp_dma dmas[NUM_ATI_DMAS];
1da177e4 275 struct ac97_pcm *pcms[NUM_ATI_PCMS];
74ee4ff1 276 struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS];
1da177e4
LT		 277
278 int max_channels; /* max. channels for PCM out */
279
280 unsigned int codec_not_ready_bits; /* for codec detection */
281
282 int spdif_over_aclink; /* passed from the module option */
62932df8 283 struct mutex open_mutex; /* playback open mutex */
1da177e4
LT		 284};
285
286
287/*
288 */
cebe41d4 289static DEFINE_PCI_DEVICE_TABLE(snd_atiixp_ids) = {
28d27aae
JP		 290 { PCI_VDEVICE(ATI, 0x4341), 0 }, /* SB200 */
291 { PCI_VDEVICE(ATI, 0x4361), 0 }, /* SB300 */
292 { PCI_VDEVICE(ATI, 0x4370), 0 }, /* SB400 */
293 { PCI_VDEVICE(ATI, 0x4382), 0 }, /* SB600 */
1da177e4
LT		 294 { 0, }
295};
296
297MODULE_DEVICE_TABLE(pci, snd_atiixp_ids);
298
f41bea84 299static struct snd_pci_quirk atiixp_quirks[] __devinitdata = {
dfb12eeb 300 SND_PCI_QUIRK(0x105b, 0x0c81, "Foxconn RC4107MA-RS2", 0),
f41bea84
TI		 301 SND_PCI_QUIRK(0x15bd, 0x3100, "DFI RS482", 0),
302 { } /* terminator */
14e1d357 303};
1da177e4
LT		 304
305/*
306 * lowlevel functions
307 */
308
309/*
310 * update the bits of the given register.
311 * return 1 if the bits changed.
312 */
74ee4ff1 313static int snd_atiixp_update_bits(struct atiixp *chip, unsigned int reg,
1da177e4
LT		 314 unsigned int mask, unsigned int value)
315{
316 void __iomem *addr = chip->remap_addr + reg;
317 unsigned int data, old_data;
318 old_data = data = readl(addr);
319 data &= ~mask;
320 data |= value;
321 if (old_data == data)
322 return 0;
323 writel(data, addr);
324 return 1;
325}
326
327/*
328 * macros for easy use
329 */
330#define atiixp_write(chip,reg,value) \
331 writel(value, chip->remap_addr + ATI_REG_##reg)
332#define atiixp_read(chip,reg) \
333 readl(chip->remap_addr + ATI_REG_##reg)
334#define atiixp_update(chip,reg,mask,val) \
335 snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
336
1da177e4
LT		 337/*
338 * handling DMA packets
339 *
340 * we allocate a linear buffer for the DMA, and split it to each packet.
341 * in a future version, a scatter-gather buffer should be implemented.
342 */
343
344#define ATI_DESC_LIST_SIZE \
74ee4ff1 345 PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc))
1da177e4
LT		 346
347/*
348 * build packets ring for the given buffer size.
349 *
350 * IXP handles the buffer descriptors, which are connected as a linked
351 * list. although we can change the list dynamically, in this version,
352 * a static RING of buffer descriptors is used.
353 *
354 * the ring is built in this function, and is set up to the hardware.
355 */
74ee4ff1
TI		 356static int atiixp_build_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
357 struct snd_pcm_substream *substream,
358 unsigned int periods,
359 unsigned int period_bytes)
1da177e4
LT		 360{
361 unsigned int i;
362 u32 addr, desc_addr;
363 unsigned long flags;
364
365 if (periods > ATI_MAX_DESCRIPTORS)
366 return -ENOMEM;
367
368 if (dma->desc_buf.area == NULL) {
74ee4ff1
TI		 369 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
370 snd_dma_pci_data(chip->pci),
371 ATI_DESC_LIST_SIZE,
372 &dma->desc_buf) < 0)
1da177e4
LT		 373 return -ENOMEM;
374 dma->period_bytes = dma->periods = 0; /* clear */
375 }
376
377 if (dma->periods == periods && dma->period_bytes == period_bytes)
378 return 0;
379
380 /* reset DMA before changing the descriptor table */
381 spin_lock_irqsave(&chip->reg_lock, flags);
382 writel(0, chip->remap_addr + dma->ops->llp_offset);
383 dma->ops->enable_dma(chip, 0);
384 dma->ops->enable_dma(chip, 1);
385 spin_unlock_irqrestore(&chip->reg_lock, flags);
386
387 /* fill the entries */
388 addr = (u32)substream->runtime->dma_addr;
389 desc_addr = (u32)dma->desc_buf.addr;
390 for (i = 0; i < periods; i++) {
74ee4ff1
TI		 391 struct atiixp_dma_desc *desc;
392 desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i];
1da177e4
LT		 393 desc->addr = cpu_to_le32(addr);
394 desc->status = 0;
395 desc->size = period_bytes >> 2; /* in dwords */
74ee4ff1 396 desc_addr += sizeof(struct atiixp_dma_desc);
1da177e4
LT		 397 if (i == periods - 1)
398 desc->next = cpu_to_le32((u32)dma->desc_buf.addr);
399 else
400 desc->next = cpu_to_le32(desc_addr);
401 addr += period_bytes;
402 }
403
404 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
405 chip->remap_addr + dma->ops->llp_offset);
406
407 dma->period_bytes = period_bytes;
408 dma->periods = periods;
409
410 return 0;
411}
412
413/*
414 * remove the ring buffer and release it if assigned
415 */
74ee4ff1
TI		 416static void atiixp_clear_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
417 struct snd_pcm_substream *substream)
1da177e4
LT		 418{
419 if (dma->desc_buf.area) {
420 writel(0, chip->remap_addr + dma->ops->llp_offset);
421 snd_dma_free_pages(&dma->desc_buf);
422 dma->desc_buf.area = NULL;
423 }
424}
425
426/*
427 * AC97 interface
428 */
74ee4ff1 429static int snd_atiixp_acquire_codec(struct atiixp *chip)
1da177e4
LT		 430{
431 int timeout = 1000;
432
433 while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) {
434 if (! timeout--) {
435 snd_printk(KERN_WARNING "atiixp: codec acquire timeout\n");
436 return -EBUSY;
437 }
438 udelay(1);
439 }
440 return 0;
441}
442
74ee4ff1 443static unsigned short snd_atiixp_codec_read(struct atiixp *chip, unsigned short codec, unsigned short reg)
1da177e4
LT		 444{
445 unsigned int data;
446 int timeout;
447
448 if (snd_atiixp_acquire_codec(chip) < 0)
449 return 0xffff;
450 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
451 ATI_REG_PHYS_OUT_ADDR_EN |
452 ATI_REG_PHYS_OUT_RW |
453 codec;
454 atiixp_write(chip, PHYS_OUT_ADDR, data);
455 if (snd_atiixp_acquire_codec(chip) < 0)
456 return 0xffff;
457 timeout = 1000;
458 do {
459 data = atiixp_read(chip, PHYS_IN_ADDR);
460 if (data & ATI_REG_PHYS_IN_READ_FLAG)
461 return data >> ATI_REG_PHYS_IN_DATA_SHIFT;
462 udelay(1);
463 } while (--timeout);
464 /* time out may happen during reset */
465 if (reg < 0x7c)
466 snd_printk(KERN_WARNING "atiixp: codec read timeout (reg %x)\n", reg);
467 return 0xffff;
468}
469
470
74ee4ff1
TI		 471static void snd_atiixp_codec_write(struct atiixp *chip, unsigned short codec,
472 unsigned short reg, unsigned short val)
1da177e4
LT		 473{
474 unsigned int data;
475
476 if (snd_atiixp_acquire_codec(chip) < 0)
477 return;
478 data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) |
479 ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
480 ATI_REG_PHYS_OUT_ADDR_EN | codec;
481 atiixp_write(chip, PHYS_OUT_ADDR, data);
482}
483
484
74ee4ff1
TI		 485static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97,
486 unsigned short reg)
1da177e4 487{
74ee4ff1 488 struct atiixp *chip = ac97->private_data;
1da177e4
LT		 489 return snd_atiixp_codec_read(chip, ac97->num, reg);
490
491}
492
74ee4ff1
TI		 493static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
494 unsigned short val)
1da177e4 495{
74ee4ff1 496 struct atiixp *chip = ac97->private_data;
1da177e4
LT		 497 snd_atiixp_codec_write(chip, ac97->num, reg, val);
498}
499
500/*
501 * reset AC link
502 */
74ee4ff1 503static int snd_atiixp_aclink_reset(struct atiixp *chip)
1da177e4
LT		 504{
505 int timeout;
506
507 /* reset powerdoewn */
508 if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0))
509 udelay(10);
510
511 /* perform a software reset */
512 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET);
513 atiixp_read(chip, CMD);
514 udelay(10);
515 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0);
516
517 timeout = 10;
518 while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) {
519 /* do a hard reset */
520 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
521 ATI_REG_CMD_AC_SYNC);
522 atiixp_read(chip, CMD);
74ee4ff1 523 mdelay(1);
1da177e4 524 atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
7e79443c 525 if (!--timeout) {
1da177e4
LT		 526 snd_printk(KERN_ERR "atiixp: codec reset timeout\n");
527 break;
528 }
529 }
530
531 /* deassert RESET and assert SYNC to make sure */
532 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
533 ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET);
534
535 return 0;
536}
537
538#ifdef CONFIG_PM
74ee4ff1 539static int snd_atiixp_aclink_down(struct atiixp *chip)
1da177e4
LT		 540{
541 // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */
542 // return -EBUSY;
543 atiixp_update(chip, CMD,
544 ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET,
545 ATI_REG_CMD_POWERDOWN);
546 return 0;
547}
548#endif
549
550/*
551 * auto-detection of codecs
552 *
553 * the IXP chip can generate interrupts for the non-existing codecs.
554 * NEW_FRAME interrupt is used to make sure that the interrupt is generated
555 * even if all three codecs are connected.
556 */
557
558#define ALL_CODEC_NOT_READY \
559 (ATI_REG_ISR_CODEC0_NOT_READY |\
560 ATI_REG_ISR_CODEC1_NOT_READY |\
561 ATI_REG_ISR_CODEC2_NOT_READY)
562#define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME)
563
32a41b02 564static int __devinit ac97_probing_bugs(struct pci_dev *pci)
14e1d357 565{
f41bea84
TI		 566 const struct snd_pci_quirk *q;
567
568 q = snd_pci_quirk_lookup(pci, atiixp_quirks);
569 if (q) {
570 snd_printdd(KERN_INFO "Atiixp quirk for %s. "
571 "Forcing codec %d\n", q->name, q->value);
572 return q->value;
14e1d357
DC		 573 }
574 /* this hardware doesn't need workarounds. Probe for codec */
575 return -1;
576}
577
32a41b02 578static int __devinit snd_atiixp_codec_detect(struct atiixp *chip)
1da177e4
LT		 579{
580 int timeout;
581
582 chip->codec_not_ready_bits = 0;
14e1d357
DC		 583 if (ac97_codec == -1)
584 ac97_codec = ac97_probing_bugs(chip->pci);
585 if (ac97_codec >= 0) {
586 chip->codec_not_ready_bits |=
587 CODEC_CHECK_BITS ^ (1 << (ac97_codec + 10));
588 return 0;
589 }
590
1da177e4
LT		 591 atiixp_write(chip, IER, CODEC_CHECK_BITS);
592 /* wait for the interrupts */
bfdcbace 593 timeout = 50;
1da177e4 594 while (timeout-- > 0) {
74ee4ff1 595 mdelay(1);
1da177e4
LT		 596 if (chip->codec_not_ready_bits)
597 break;
598 }
599 atiixp_write(chip, IER, 0); /* disable irqs */
600
601 if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) {
602 snd_printk(KERN_ERR "atiixp: no codec detected!\n");
603 return -ENXIO;
604 }
605 return 0;
606}
607
608
609/*
610 * enable DMA and irqs
611 */
74ee4ff1 612static int snd_atiixp_chip_start(struct atiixp *chip)
1da177e4
LT		 613{
614 unsigned int reg;
615
616 /* set up spdif, enable burst mode */
617 reg = atiixp_read(chip, CMD);
618 reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT;
619 reg |= ATI_REG_CMD_BURST_EN;
620 atiixp_write(chip, CMD, reg);
621
622 reg = atiixp_read(chip, SPDF_CMD);
623 reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH);
624 atiixp_write(chip, SPDF_CMD, reg);
625
626 /* clear all interrupt source */
627 atiixp_write(chip, ISR, 0xffffffff);
628 /* enable irqs */
629 atiixp_write(chip, IER,
630 ATI_REG_IER_IO_STATUS_EN |
631 ATI_REG_IER_IN_XRUN_EN |
632 ATI_REG_IER_OUT_XRUN_EN |
633 ATI_REG_IER_SPDF_XRUN_EN |
634 ATI_REG_IER_SPDF_STATUS_EN);
635 return 0;
636}
637
638
639/*
640 * disable DMA and IRQs
641 */
74ee4ff1 642static int snd_atiixp_chip_stop(struct atiixp *chip)
1da177e4
LT		 643{
644 /* clear interrupt source */
645 atiixp_write(chip, ISR, atiixp_read(chip, ISR));
646 /* disable irqs */
647 atiixp_write(chip, IER, 0);
648 return 0;
649}
650
651
652/*
653 * PCM section
654 */
655
656/*
657 * pointer callback simplly reads XXX_DMA_DT_CUR register as the current
658 * position. when SG-buffer is implemented, the offset must be calculated
659 * correctly...
660 */
74ee4ff1 661static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream)
1da177e4 662{
74ee4ff1
TI		 663 struct atiixp *chip = snd_pcm_substream_chip(substream);
664 struct snd_pcm_runtime *runtime = substream->runtime;
665 struct atiixp_dma *dma = runtime->private_data;
1da177e4
LT		 666 unsigned int curptr;
667 int timeout = 1000;
668
669 while (timeout--) {
670 curptr = readl(chip->remap_addr + dma->ops->dt_cur);
671 if (curptr < dma->buf_addr)
672 continue;
673 curptr -= dma->buf_addr;
674 if (curptr >= dma->buf_bytes)
675 continue;
676 return bytes_to_frames(runtime, curptr);
677 }
678 snd_printd("atiixp: invalid DMA pointer read 0x%x (buf=%x)\n",
679 readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr);
680 return 0;
681}
682
683/*
684 * XRUN detected, and stop the PCM substream
685 */
74ee4ff1 686static void snd_atiixp_xrun_dma(struct atiixp *chip, struct atiixp_dma *dma)
1da177e4
LT		 687{
688 if (! dma->substream || ! dma->running)
689 return;
690 snd_printdd("atiixp: XRUN detected (DMA %d)\n", dma->ops->type);
691 snd_pcm_stop(dma->substream, SNDRV_PCM_STATE_XRUN);
692}
693
694/*
695 * the period ack. update the substream.
696 */
74ee4ff1 697static void snd_atiixp_update_dma(struct atiixp *chip, struct atiixp_dma *dma)
1da177e4
LT		 698{
699 if (! dma->substream || ! dma->running)
700 return;
701 snd_pcm_period_elapsed(dma->substream);
702}
703
704/* set BUS_BUSY interrupt bit if any DMA is running */
705/* call with spinlock held */
74ee4ff1 706static void snd_atiixp_check_bus_busy(struct atiixp *chip)
1da177e4
LT		 707{
708 unsigned int bus_busy;
709 if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN |
710 ATI_REG_CMD_RECEIVE_EN |
711 ATI_REG_CMD_SPDF_OUT_EN))
712 bus_busy = ATI_REG_IER_SET_BUS_BUSY;
713 else
714 bus_busy = 0;
715 atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy);
716}
717
718/* common trigger callback
719 * calling the lowlevel callbacks in it
720 */
74ee4ff1 721static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 722{
74ee4ff1
TI		 723 struct atiixp *chip = snd_pcm_substream_chip(substream);
724 struct atiixp_dma *dma = substream->runtime->private_data;
1da177e4
LT		 725 int err = 0;
726
da3cec35
TI		 727 if (snd_BUG_ON(!dma->ops->enable_transfer ||
728 !dma->ops->flush_dma))
729 return -EINVAL;
1da177e4
LT		 730
731 spin_lock(&chip->reg_lock);
732 switch (cmd) {
733 case SNDRV_PCM_TRIGGER_START:
41e4845c
JK		 734 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
735 case SNDRV_PCM_TRIGGER_RESUME:
1da177e4
LT		 736 dma->ops->enable_transfer(chip, 1);
737 dma->running = 1;
41e4845c 738 dma->suspended = 0;
1da177e4
LT		 739 break;
740 case SNDRV_PCM_TRIGGER_STOP:
41e4845c
JK		 741 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
742 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 743 dma->ops->enable_transfer(chip, 0);
744 dma->running = 0;
41e4845c 745 dma->suspended = cmd == SNDRV_PCM_TRIGGER_SUSPEND;
1da177e4
LT		 746 break;
747 default:
748 err = -EINVAL;
749 break;
750 }
751 if (! err) {
752 snd_atiixp_check_bus_busy(chip);
753 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
754 dma->ops->flush_dma(chip);
755 snd_atiixp_check_bus_busy(chip);
756 }
757 }
758 spin_unlock(&chip->reg_lock);
759 return err;
760}
761
762
763/*
764 * lowlevel callbacks for each DMA type
765 *
766 * every callback is supposed to be called in chip->reg_lock spinlock
767 */
768
769/* flush FIFO of analog OUT DMA */
74ee4ff1 770static void atiixp_out_flush_dma(struct atiixp *chip)
1da177e4
LT		 771{
772 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH);
773}
774
775/* enable/disable analog OUT DMA */
74ee4ff1 776static void atiixp_out_enable_dma(struct atiixp *chip, int on)
1da177e4
LT		 777{
778 unsigned int data;
779 data = atiixp_read(chip, CMD);
780 if (on) {
781 if (data & ATI_REG_CMD_OUT_DMA_EN)
782 return;
783 atiixp_out_flush_dma(chip);
784 data |= ATI_REG_CMD_OUT_DMA_EN;
785 } else
786 data &= ~ATI_REG_CMD_OUT_DMA_EN;
787 atiixp_write(chip, CMD, data);
788}
789
790/* start/stop transfer over OUT DMA */
74ee4ff1 791static void atiixp_out_enable_transfer(struct atiixp *chip, int on)
1da177e4
LT		 792{
793 atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN,
794 on ? ATI_REG_CMD_SEND_EN : 0);
795}
796
797/* enable/disable analog IN DMA */
74ee4ff1 798static void atiixp_in_enable_dma(struct atiixp *chip, int on)
1da177e4
LT		 799{
800 atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN,
801 on ? ATI_REG_CMD_IN_DMA_EN : 0);
802}
803
804/* start/stop analog IN DMA */
74ee4ff1 805static void atiixp_in_enable_transfer(struct atiixp *chip, int on)
1da177e4
LT		 806{
807 if (on) {
808 unsigned int data = atiixp_read(chip, CMD);
809 if (! (data & ATI_REG_CMD_RECEIVE_EN)) {
810 data |= ATI_REG_CMD_RECEIVE_EN;
811#if 0 /* FIXME: this causes the endless loop */
812 /* wait until slot 3/4 are finished */
813 while ((atiixp_read(chip, COUNTER) &
814 ATI_REG_COUNTER_SLOT) != 5)
815 ;
816#endif
817 atiixp_write(chip, CMD, data);
818 }
819 } else
820 atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0);
821}
822
823/* flush FIFO of analog IN DMA */
74ee4ff1 824static void atiixp_in_flush_dma(struct atiixp *chip)
1da177e4
LT		 825{
826 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH);
827}
828
829/* enable/disable SPDIF OUT DMA */
74ee4ff1 830static void atiixp_spdif_enable_dma(struct atiixp *chip, int on)
1da177e4
LT		 831{
832 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN,
833 on ? ATI_REG_CMD_SPDF_DMA_EN : 0);
834}
835
836/* start/stop SPDIF OUT DMA */
74ee4ff1 837static void atiixp_spdif_enable_transfer(struct atiixp *chip, int on)
1da177e4
LT		 838{
839 unsigned int data;
840 data = atiixp_read(chip, CMD);
841 if (on)
842 data |= ATI_REG_CMD_SPDF_OUT_EN;
843 else
844 data &= ~ATI_REG_CMD_SPDF_OUT_EN;
845 atiixp_write(chip, CMD, data);
846}
847
848/* flush FIFO of SPDIF OUT DMA */
74ee4ff1 849static void atiixp_spdif_flush_dma(struct atiixp *chip)
1da177e4
LT		 850{
851 int timeout;
852
853 /* DMA off, transfer on */
854 atiixp_spdif_enable_dma(chip, 0);
855 atiixp_spdif_enable_transfer(chip, 1);
856
857 timeout = 100;
858 do {
859 if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED))
860 break;
861 udelay(1);
862 } while (timeout-- > 0);
863
864 atiixp_spdif_enable_transfer(chip, 0);
865}
866
867/* set up slots and formats for SPDIF OUT */
74ee4ff1 868static int snd_atiixp_spdif_prepare(struct snd_pcm_substream *substream)
1da177e4 869{
74ee4ff1 870 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 871
872 spin_lock_irq(&chip->reg_lock);
873 if (chip->spdif_over_aclink) {
874 unsigned int data;
875 /* enable slots 10/11 */
876 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK,
877 ATI_REG_CMD_SPDF_CONFIG_01);
878 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
879 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
880 ATI_REG_OUT_DMA_SLOT_BIT(11);
881 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
882 atiixp_write(chip, OUT_DMA_SLOT, data);
883 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
884 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
885 ATI_REG_CMD_INTERLEAVE_OUT : 0);
886 } else {
887 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0);
888 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0);
889 }
890 spin_unlock_irq(&chip->reg_lock);
891 return 0;
892}
893
894/* set up slots and formats for analog OUT */
74ee4ff1 895static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 896{
74ee4ff1 897 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 898 unsigned int data;
899
900 spin_lock_irq(&chip->reg_lock);
901 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
902 switch (substream->runtime->channels) {
903 case 8:
904 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
905 ATI_REG_OUT_DMA_SLOT_BIT(11);
906 /* fallthru */
907 case 6:
908 data |= ATI_REG_OUT_DMA_SLOT_BIT(7) |
909 ATI_REG_OUT_DMA_SLOT_BIT(8);
910 /* fallthru */
911 case 4:
912 data |= ATI_REG_OUT_DMA_SLOT_BIT(6) |
913 ATI_REG_OUT_DMA_SLOT_BIT(9);
914 /* fallthru */
915 default:
916 data |= ATI_REG_OUT_DMA_SLOT_BIT(3) |
917 ATI_REG_OUT_DMA_SLOT_BIT(4);
918 break;
919 }
920
921 /* set output threshold */
922 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
923 atiixp_write(chip, OUT_DMA_SLOT, data);
924
925 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
926 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
927 ATI_REG_CMD_INTERLEAVE_OUT : 0);
928
929 /*
930 * enable 6 channel re-ordering bit if needed
931 */
932 atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN,
933 substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0);
934
935 spin_unlock_irq(&chip->reg_lock);
936 return 0;
937}
938
939/* set up slots and formats for analog IN */
74ee4ff1 940static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 941{
74ee4ff1 942 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 943
944 spin_lock_irq(&chip->reg_lock);
945 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN,
946 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
947 ATI_REG_CMD_INTERLEAVE_IN : 0);
948 spin_unlock_irq(&chip->reg_lock);
949 return 0;
950}
951
952/*
953 * hw_params - allocate the buffer and set up buffer descriptors
954 */
74ee4ff1
TI		 955static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream,
956 struct snd_pcm_hw_params *hw_params)
1da177e4 957{
74ee4ff1
TI		 958 struct atiixp *chip = snd_pcm_substream_chip(substream);
959 struct atiixp_dma *dma = substream->runtime->private_data;
1da177e4
LT		 960 int err;
961
962 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
963 if (err < 0)
964 return err;
965 dma->buf_addr = substream->runtime->dma_addr;
966 dma->buf_bytes = params_buffer_bytes(hw_params);
967
968 err = atiixp_build_dma_packets(chip, dma, substream,
969 params_periods(hw_params),
970 params_period_bytes(hw_params));
971 if (err < 0)
972 return err;
973
974 if (dma->ac97_pcm_type >= 0) {
975 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
976 /* PCM is bound to AC97 codec(s)
977 * set up the AC97 codecs
978 */
979 if (dma->pcm_open_flag) {
980 snd_ac97_pcm_close(pcm);
981 dma->pcm_open_flag = 0;
982 }
983 err = snd_ac97_pcm_open(pcm, params_rate(hw_params),
984 params_channels(hw_params),
985 pcm->r[0].slots);
986 if (err >= 0)
987 dma->pcm_open_flag = 1;
988 }
989
990 return err;
991}
992
74ee4ff1 993static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4 994{
74ee4ff1
TI		 995 struct atiixp *chip = snd_pcm_substream_chip(substream);
996 struct atiixp_dma *dma = substream->runtime->private_data;
1da177e4
LT		 997
998 if (dma->pcm_open_flag) {
999 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
1000 snd_ac97_pcm_close(pcm);
1001 dma->pcm_open_flag = 0;
1002 }
1003 atiixp_clear_dma_packets(chip, dma, substream);
1004 snd_pcm_lib_free_pages(substream);
1005 return 0;
1006}
1007
1008
1009/*
1010 * pcm hardware definition, identical for all DMA types
1011 */
74ee4ff1 1012static struct snd_pcm_hardware snd_atiixp_pcm_hw =
1da177e4
LT		 1013{
1014 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1015 SNDRV_PCM_INFO_BLOCK_TRANSFER |
41e4845c 1016 SNDRV_PCM_INFO_PAUSE |
1da177e4
LT		 1017 SNDRV_PCM_INFO_RESUME |
1018 SNDRV_PCM_INFO_MMAP_VALID),
1019 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1020 .rates = SNDRV_PCM_RATE_48000,
1021 .rate_min = 48000,
1022 .rate_max = 48000,
1023 .channels_min = 2,
1024 .channels_max = 2,
1025 .buffer_bytes_max = 256 * 1024,
1026 .period_bytes_min = 32,
1027 .period_bytes_max = 128 * 1024,
1028 .periods_min = 2,
1029 .periods_max = ATI_MAX_DESCRIPTORS,
1030};
1031
74ee4ff1
TI		 1032static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream,
1033 struct atiixp_dma *dma, int pcm_type)
1da177e4 1034{
74ee4ff1
TI		 1035 struct atiixp *chip = snd_pcm_substream_chip(substream);
1036 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1037 int err;
1038
da3cec35
TI		 1039 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
1040 return -EINVAL;
1da177e4
LT		 1041
1042 if (dma->opened)
1043 return -EBUSY;
1044 dma->substream = substream;
1045 runtime->hw = snd_atiixp_pcm_hw;
1046 dma->ac97_pcm_type = pcm_type;
1047 if (pcm_type >= 0) {
1048 runtime->hw.rates = chip->pcms[pcm_type]->rates;
1049 snd_pcm_limit_hw_rates(runtime);
1050 } else {
1051 /* direct SPDIF */
1052 runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
1053 }
1054 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1055 return err;
1056 runtime->private_data = dma;
1057
1058 /* enable DMA bits */
1059 spin_lock_irq(&chip->reg_lock);
1060 dma->ops->enable_dma(chip, 1);
1061 spin_unlock_irq(&chip->reg_lock);
1062 dma->opened = 1;
1063
1064 return 0;
1065}
1066
74ee4ff1
TI		 1067static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream,
1068 struct atiixp_dma *dma)
1da177e4 1069{
74ee4ff1 1070 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4 1071 /* disable DMA bits */
da3cec35
TI		 1072 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
1073 return -EINVAL;
1da177e4
LT		 1074 spin_lock_irq(&chip->reg_lock);
1075 dma->ops->enable_dma(chip, 0);
1076 spin_unlock_irq(&chip->reg_lock);
1077 dma->substream = NULL;
1078 dma->opened = 0;
1079 return 0;
1080}
1081
1082/*
1083 */
74ee4ff1 1084static int snd_atiixp_playback_open(struct snd_pcm_substream *substream)
1da177e4 1085{
74ee4ff1 1086 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1087 int err;
1088
62932df8 1089 mutex_lock(&chip->open_mutex);
1da177e4 1090 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0);
62932df8 1091 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1092 if (err < 0)
1093 return err;
1094 substream->runtime->hw.channels_max = chip->max_channels;
1095 if (chip->max_channels > 2)
1096 /* channels must be even */
1097 snd_pcm_hw_constraint_step(substream->runtime, 0,
1098 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1099 return 0;
1100}
1101
74ee4ff1 1102static int snd_atiixp_playback_close(struct snd_pcm_substream *substream)
1da177e4 1103{
74ee4ff1 1104 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4 1105 int err;
62932df8 1106 mutex_lock(&chip->open_mutex);
1da177e4 1107 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
62932df8 1108 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1109 return err;
1110}
1111
74ee4ff1 1112static int snd_atiixp_capture_open(struct snd_pcm_substream *substream)
1da177e4 1113{
74ee4ff1 1114 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1115 return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1);
1116}
1117
74ee4ff1 1118static int snd_atiixp_capture_close(struct snd_pcm_substream *substream)
1da177e4 1119{
74ee4ff1 1120 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1121 return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]);
1122}
1123
74ee4ff1 1124static int snd_atiixp_spdif_open(struct snd_pcm_substream *substream)
1da177e4 1125{
74ee4ff1 1126 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4 1127 int err;
62932df8 1128 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1129 if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */
1130 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2);
1131 else
1132 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1);
62932df8 1133 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1134 return err;
1135}
1136
74ee4ff1 1137static int snd_atiixp_spdif_close(struct snd_pcm_substream *substream)
1da177e4 1138{
74ee4ff1 1139 struct atiixp *chip = snd_pcm_substream_chip(substream);
1da177e4 1140 int err;
62932df8 1141 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1142 if (chip->spdif_over_aclink)
1143 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
1144 else
1145 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]);
62932df8 1146 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1147 return err;
1148}
1149
1150/* AC97 playback */
74ee4ff1 1151static struct snd_pcm_ops snd_atiixp_playback_ops = {
1da177e4
LT		 1152 .open = snd_atiixp_playback_open,
1153 .close = snd_atiixp_playback_close,
1154 .ioctl = snd_pcm_lib_ioctl,
1155 .hw_params = snd_atiixp_pcm_hw_params,
1156 .hw_free = snd_atiixp_pcm_hw_free,
1157 .prepare = snd_atiixp_playback_prepare,
1158 .trigger = snd_atiixp_pcm_trigger,
1159 .pointer = snd_atiixp_pcm_pointer,
1160};
1161
1162/* AC97 capture */
74ee4ff1 1163static struct snd_pcm_ops snd_atiixp_capture_ops = {
1da177e4
LT		 1164 .open = snd_atiixp_capture_open,
1165 .close = snd_atiixp_capture_close,
1166 .ioctl = snd_pcm_lib_ioctl,
1167 .hw_params = snd_atiixp_pcm_hw_params,
1168 .hw_free = snd_atiixp_pcm_hw_free,
1169 .prepare = snd_atiixp_capture_prepare,
1170 .trigger = snd_atiixp_pcm_trigger,
1171 .pointer = snd_atiixp_pcm_pointer,
1172};
1173
1174/* SPDIF playback */
74ee4ff1 1175static struct snd_pcm_ops snd_atiixp_spdif_ops = {
1da177e4
LT		 1176 .open = snd_atiixp_spdif_open,
1177 .close = snd_atiixp_spdif_close,
1178 .ioctl = snd_pcm_lib_ioctl,
1179 .hw_params = snd_atiixp_pcm_hw_params,
1180 .hw_free = snd_atiixp_pcm_hw_free,
1181 .prepare = snd_atiixp_spdif_prepare,
1182 .trigger = snd_atiixp_pcm_trigger,
1183 .pointer = snd_atiixp_pcm_pointer,
1184};
1185
1186static struct ac97_pcm atiixp_pcm_defs[] __devinitdata = {
1187 /* front PCM */
1188 {
1189 .exclusive = 1,
1190 .r = { {
1191 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1192 (1 << AC97_SLOT_PCM_RIGHT) |
1193 (1 << AC97_SLOT_PCM_CENTER) |
1194 (1 << AC97_SLOT_PCM_SLEFT) |
1195 (1 << AC97_SLOT_PCM_SRIGHT) |
1196 (1 << AC97_SLOT_LFE)
1197 }
1198 }
1199 },
1200 /* PCM IN #1 */
1201 {
1202 .stream = 1,
1203 .exclusive = 1,
1204 .r = { {
1205 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1206 (1 << AC97_SLOT_PCM_RIGHT)
1207 }
1208 }
1209 },
1210 /* S/PDIF OUT (optional) */
1211 {
1212 .exclusive = 1,
1213 .spdif = 1,
1214 .r = { {
1215 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1216 (1 << AC97_SLOT_SPDIF_RIGHT2)
1217 }
1218 }
1219 },
1220};
1221
74ee4ff1 1222static struct atiixp_dma_ops snd_atiixp_playback_dma_ops = {
1da177e4
LT		 1223 .type = ATI_DMA_PLAYBACK,
1224 .llp_offset = ATI_REG_OUT_DMA_LINKPTR,
1225 .dt_cur = ATI_REG_OUT_DMA_DT_CUR,
1226 .enable_dma = atiixp_out_enable_dma,
1227 .enable_transfer = atiixp_out_enable_transfer,
1228 .flush_dma = atiixp_out_flush_dma,
1229};
1230
74ee4ff1 1231static struct atiixp_dma_ops snd_atiixp_capture_dma_ops = {
1da177e4
LT		 1232 .type = ATI_DMA_CAPTURE,
1233 .llp_offset = ATI_REG_IN_DMA_LINKPTR,
1234 .dt_cur = ATI_REG_IN_DMA_DT_CUR,
1235 .enable_dma = atiixp_in_enable_dma,
1236 .enable_transfer = atiixp_in_enable_transfer,
1237 .flush_dma = atiixp_in_flush_dma,
1238};
1239
74ee4ff1 1240static struct atiixp_dma_ops snd_atiixp_spdif_dma_ops = {
1da177e4
LT		 1241 .type = ATI_DMA_SPDIF,
1242 .llp_offset = ATI_REG_SPDF_DMA_LINKPTR,
1243 .dt_cur = ATI_REG_SPDF_DMA_DT_CUR,
1244 .enable_dma = atiixp_spdif_enable_dma,
1245 .enable_transfer = atiixp_spdif_enable_transfer,
1246 .flush_dma = atiixp_spdif_flush_dma,
1247};
1248
1249
74ee4ff1 1250static int __devinit snd_atiixp_pcm_new(struct atiixp *chip)
1da177e4 1251{
74ee4ff1
TI		 1252 struct snd_pcm *pcm;
1253 struct snd_ac97_bus *pbus = chip->ac97_bus;
1da177e4
LT		 1254 int err, i, num_pcms;
1255
1256 /* initialize constants */
1257 chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops;
1258 chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops;
1259 if (! chip->spdif_over_aclink)
1260 chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops;
1261
1262 /* assign AC97 pcm */
1263 if (chip->spdif_over_aclink)
1264 num_pcms = 3;
1265 else
1266 num_pcms = 2;
1267 err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs);
1268 if (err < 0)
1269 return err;
1270 for (i = 0; i < num_pcms; i++)
1271 chip->pcms[i] = &pbus->pcms[i];
1272
1273 chip->max_channels = 2;
1274 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
1275 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE))
1276 chip->max_channels = 6;
1277 else
1278 chip->max_channels = 4;
1279 }
1280
1281 /* PCM #0: analog I/O */
74ee4ff1
TI		 1282 err = snd_pcm_new(chip->card, "ATI IXP AC97",
1283 ATI_PCMDEV_ANALOG, 1, 1, &pcm);
1da177e4
LT		 1284 if (err < 0)
1285 return err;
1286 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops);
1287 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops);
1288 pcm->private_data = chip;
1289 strcpy(pcm->name, "ATI IXP AC97");
1290 chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm;
1291
1292 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
74ee4ff1
TI		 1293 snd_dma_pci_data(chip->pci),
1294 64*1024, 128*1024);
1da177e4
LT		 1295
1296 /* no SPDIF support on codec? */
1297 if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates)
1298 return 0;
1299
1300 /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */
1301 if (chip->pcms[ATI_PCM_SPDIF])
1302 chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000;
1303
1304 /* PCM #1: spdif playback */
74ee4ff1
TI		 1305 err = snd_pcm_new(chip->card, "ATI IXP IEC958",
1306 ATI_PCMDEV_DIGITAL, 1, 0, &pcm);
1da177e4
LT		 1307 if (err < 0)
1308 return err;
1309 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops);
1310 pcm->private_data = chip;
1311 if (chip->spdif_over_aclink)
1312 strcpy(pcm->name, "ATI IXP IEC958 (AC97)");
1313 else
1314 strcpy(pcm->name, "ATI IXP IEC958 (Direct)");
1315 chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm;
1316
1317 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
74ee4ff1
TI		 1318 snd_dma_pci_data(chip->pci),
1319 64*1024, 128*1024);
1da177e4
LT		 1320
1321 /* pre-select AC97 SPDIF slots 10/11 */
1322 for (i = 0; i < NUM_ATI_CODECS; i++) {
1323 if (chip->ac97[i])
74ee4ff1
TI		 1324 snd_ac97_update_bits(chip->ac97[i],
1325 AC97_EXTENDED_STATUS,
1326 0x03 << 4, 0x03 << 4);
1da177e4
LT		 1327 }
1328
1329 return 0;
1330}
1331
1332
1333
1334/*
1335 * interrupt handler
1336 */
7d12e780 1337static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id)
1da177e4 1338{
74ee4ff1 1339 struct atiixp *chip = dev_id;
1da177e4
LT		 1340 unsigned int status;
1341
1342 status = atiixp_read(chip, ISR);
1343
1344 if (! status)
1345 return IRQ_NONE;
1346
1347 /* process audio DMA */
1348 if (status & ATI_REG_ISR_OUT_XRUN)
1349 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1350 else if (status & ATI_REG_ISR_OUT_STATUS)
1351 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1352 if (status & ATI_REG_ISR_IN_XRUN)
1353 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1354 else if (status & ATI_REG_ISR_IN_STATUS)
1355 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1356 if (! chip->spdif_over_aclink) {
1357 if (status & ATI_REG_ISR_SPDF_XRUN)
1358 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1359 else if (status & ATI_REG_ISR_SPDF_STATUS)
1360 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1361 }
1362
1363 /* for codec detection */
1364 if (status & CODEC_CHECK_BITS) {
1365 unsigned int detected;
1366 detected = status & CODEC_CHECK_BITS;
1367 spin_lock(&chip->reg_lock);
1368 chip->codec_not_ready_bits |= detected;
1369 atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
1370 spin_unlock(&chip->reg_lock);
1371 }
1372
1373 /* ack */
1374 atiixp_write(chip, ISR, status);
1375
1376 return IRQ_HANDLED;
1377}
1378
1379
1380/*
1381 * ac97 mixer section
1382 */
1383
1384static struct ac97_quirk ac97_quirks[] __devinitdata = {
1385 {
69ad07cf
JK		 1386 .subvendor = 0x103c,
1387 .subdevice = 0x006b,
1da177e4
LT		 1388 .name = "HP Pavilion ZV5030US",
1389 .type = AC97_TUNE_MUTE_LED
1390 },
a0faefed
MG		 1391 {
1392 .subvendor = 0x103c,
1393 .subdevice = 0x308b,
1394 .name = "HP nx6125",
1395 .type = AC97_TUNE_MUTE_LED
1396 },
e3ba906a
DC		 1397 {
1398 .subvendor = 0x103c,
1399 .subdevice = 0x3091,
1400 .name = "unknown HP",
1401 .type = AC97_TUNE_MUTE_LED
1402 },
1da177e4
LT		 1403 { } /* terminator */
1404};
1405
74ee4ff1
TI		 1406static int __devinit snd_atiixp_mixer_new(struct atiixp *chip, int clock,
1407 const char *quirk_override)
1da177e4 1408{
74ee4ff1
TI		 1409 struct snd_ac97_bus *pbus;
1410 struct snd_ac97_template ac97;
1da177e4
LT		 1411 int i, err;
1412 int codec_count;
74ee4ff1 1413 static struct snd_ac97_bus_ops ops = {
1da177e4
LT		 1414 .write = snd_atiixp_ac97_write,
1415 .read = snd_atiixp_ac97_read,
1416 };
1417 static unsigned int codec_skip[NUM_ATI_CODECS] = {
1418 ATI_REG_ISR_CODEC0_NOT_READY,
1419 ATI_REG_ISR_CODEC1_NOT_READY,
1420 ATI_REG_ISR_CODEC2_NOT_READY,
1421 };
1422
1423 if (snd_atiixp_codec_detect(chip) < 0)
1424 return -ENXIO;
1425
1426 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
1427 return err;
1428 pbus->clock = clock;
1da177e4
LT		 1429 chip->ac97_bus = pbus;
1430
1431 codec_count = 0;
1432 for (i = 0; i < NUM_ATI_CODECS; i++) {
1433 if (chip->codec_not_ready_bits & codec_skip[i])
1434 continue;
1435 memset(&ac97, 0, sizeof(ac97));
1436 ac97.private_data = chip;
1437 ac97.pci = chip->pci;
1438 ac97.num = i;
f1a63a38 1439 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
1da177e4
LT		 1440 if (! chip->spdif_over_aclink)
1441 ac97.scaps |= AC97_SCAP_NO_SPDIF;
1442 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
1443 chip->ac97[i] = NULL; /* to be sure */
1444 snd_printdd("atiixp: codec %d not available for audio\n", i);
1445 continue;
1446 }
1447 codec_count++;
1448 }
1449
1450 if (! codec_count) {
1451 snd_printk(KERN_ERR "atiixp: no codec available\n");
1452 return -ENODEV;
1453 }
1454
1455 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
1456
1457 return 0;
1458}
1459
1460
1461#ifdef CONFIG_PM
1462/*
1463 * power management
1464 */
92304cc7 1465static int snd_atiixp_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 1466{
92304cc7
TI		 1467 struct snd_card *card = pci_get_drvdata(pci);
1468 struct atiixp *chip = card->private_data;
1da177e4
LT		 1469 int i;
1470
92304cc7 1471 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1da177e4
LT		 1472 for (i = 0; i < NUM_ATI_PCMDEVS; i++)
1473 if (chip->pcmdevs[i]) {
74ee4ff1 1474 struct atiixp_dma *dma = &chip->dmas[i];
1da177e4 1475 if (dma->substream && dma->running)
74ee4ff1
TI		 1476 dma->saved_curptr = readl(chip->remap_addr +
1477 dma->ops->dt_cur);
1da177e4
LT		 1478 snd_pcm_suspend_all(chip->pcmdevs[i]);
1479 }
1480 for (i = 0; i < NUM_ATI_CODECS; i++)
92304cc7 1481 snd_ac97_suspend(chip->ac97[i]);
1da177e4
LT		 1482 snd_atiixp_aclink_down(chip);
1483 snd_atiixp_chip_stop(chip);
1484
92304cc7
TI		 1485 pci_disable_device(pci);
1486 pci_save_state(pci);
30b35399 1487 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 1488 return 0;
1489}
1490
92304cc7 1491static int snd_atiixp_resume(struct pci_dev *pci)
1da177e4 1492{
92304cc7
TI		 1493 struct snd_card *card = pci_get_drvdata(pci);
1494 struct atiixp *chip = card->private_data;
1da177e4
LT		 1495 int i;
1496
92304cc7 1497 pci_set_power_state(pci, PCI_D0);
30b35399
TI		 1498 pci_restore_state(pci);
1499 if (pci_enable_device(pci) < 0) {
1500 printk(KERN_ERR "atiixp: pci_enable_device failed, "
1501 "disabling device\n");
1502 snd_card_disconnect(card);
1503 return -EIO;
1504 }
92304cc7 1505 pci_set_master(pci);
1da177e4
LT		 1506
1507 snd_atiixp_aclink_reset(chip);
1508 snd_atiixp_chip_start(chip);
1509
1510 for (i = 0; i < NUM_ATI_CODECS; i++)
92304cc7 1511 snd_ac97_resume(chip->ac97[i]);
1da177e4
LT		 1512
1513 for (i = 0; i < NUM_ATI_PCMDEVS; i++)
1514 if (chip->pcmdevs[i]) {
74ee4ff1 1515 struct atiixp_dma *dma = &chip->dmas[i];
41e4845c 1516 if (dma->substream && dma->suspended) {
1da177e4 1517 dma->ops->enable_dma(chip, 1);
8e3d759d 1518 dma->substream->ops->prepare(dma->substream);
1da177e4
LT		 1519 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
1520 chip->remap_addr + dma->ops->llp_offset);
74ee4ff1
TI		 1521 writel(dma->saved_curptr, chip->remap_addr +
1522 dma->ops->dt_cur);
1da177e4
LT		 1523 }
1524 }
1525
92304cc7 1526 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 1527 return 0;
1528}
1529#endif /* CONFIG_PM */
1530
1531
adf1b3d2 1532#ifdef CONFIG_PROC_FS
1da177e4
LT		 1533/*
1534 * proc interface for register dump
1535 */
1536
74ee4ff1
TI		 1537static void snd_atiixp_proc_read(struct snd_info_entry *entry,
1538 struct snd_info_buffer *buffer)
1da177e4 1539{
74ee4ff1 1540 struct atiixp *chip = entry->private_data;
1da177e4
LT		 1541 int i;
1542
1543 for (i = 0; i < 256; i += 4)
1544 snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i));
1545}
1546
74ee4ff1 1547static void __devinit snd_atiixp_proc_init(struct atiixp *chip)
1da177e4 1548{
74ee4ff1 1549 struct snd_info_entry *entry;
1da177e4
LT		 1550
1551 if (! snd_card_proc_new(chip->card, "atiixp", &entry))
bf850204 1552 snd_info_set_text_ops(entry, chip, snd_atiixp_proc_read);
1da177e4 1553}
adf1b3d2
TI		 1554#else /* !CONFIG_PROC_FS */
1555#define snd_atiixp_proc_init(chip)
1556#endif
1da177e4
LT		 1557
1558
1559/*
1560 * destructor
1561 */
1562
74ee4ff1 1563static int snd_atiixp_free(struct atiixp *chip)
1da177e4
LT		 1564{
1565 if (chip->irq < 0)
1566 goto __hw_end;
1567 snd_atiixp_chip_stop(chip);
f000fd80 1568
1da177e4
LT		 1569 __hw_end:
1570 if (chip->irq >= 0)
74ee4ff1 1571 free_irq(chip->irq, chip);
1da177e4
LT		 1572 if (chip->remap_addr)
1573 iounmap(chip->remap_addr);
1574 pci_release_regions(chip->pci);
1575 pci_disable_device(chip->pci);
1576 kfree(chip);
1577 return 0;
1578}
1579
74ee4ff1 1580static int snd_atiixp_dev_free(struct snd_device *device)
1da177e4 1581{
74ee4ff1 1582 struct atiixp *chip = device->device_data;
1da177e4
LT		 1583 return snd_atiixp_free(chip);
1584}
1585
1586/*
1587 * constructor for chip instance
1588 */
74ee4ff1 1589static int __devinit snd_atiixp_create(struct snd_card *card,
1da177e4 1590 struct pci_dev *pci,
74ee4ff1 1591 struct atiixp **r_chip)
1da177e4 1592{
74ee4ff1 1593 static struct snd_device_ops ops = {
1da177e4
LT		 1594 .dev_free = snd_atiixp_dev_free,
1595 };
74ee4ff1 1596 struct atiixp *chip;
1da177e4
LT		 1597 int err;
1598
1599 if ((err = pci_enable_device(pci)) < 0)
1600 return err;
1601
e560d8d8 1602 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 1603 if (chip == NULL) {
1604 pci_disable_device(pci);
1605 return -ENOMEM;
1606 }
1607
1608 spin_lock_init(&chip->reg_lock);
62932df8 1609 mutex_init(&chip->open_mutex);
1da177e4
LT		 1610 chip->card = card;
1611 chip->pci = pci;
1612 chip->irq = -1;
1613 if ((err = pci_request_regions(pci, "ATI IXP AC97")) < 0) {
1614 pci_disable_device(pci);
1615 kfree(chip);
1616 return err;
1617 }
1618 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 1619 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 1620 if (chip->remap_addr == NULL) {
1621 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
1622 snd_atiixp_free(chip);
1623 return -EIO;
1624 }
1625
437a5a46 1626 if (request_irq(pci->irq, snd_atiixp_interrupt, IRQF_SHARED,
934c2b6d 1627 KBUILD_MODNAME, chip)) {
1da177e4
LT		 1628 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1629 snd_atiixp_free(chip);
1630 return -EBUSY;
1631 }
1632 chip->irq = pci->irq;
1633 pci_set_master(pci);
1634 synchronize_irq(chip->irq);
1635
1636 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1637 snd_atiixp_free(chip);
1638 return err;
1639 }
1640
1641 snd_card_set_dev(card, &pci->dev);
1642
1643 *r_chip = chip;
1644 return 0;
1645}
1646
1647
1648static int __devinit snd_atiixp_probe(struct pci_dev *pci,
1649 const struct pci_device_id *pci_id)
1650{
74ee4ff1
TI		 1651 struct snd_card *card;
1652 struct atiixp *chip;
1da177e4
LT		 1653 int err;
1654
e58de7ba
TI		 1655 err = snd_card_create(index, id, THIS_MODULE, 0, &card);
1656 if (err < 0)
1657 return err;
1da177e4 1658
b7fe4622 1659 strcpy(card->driver, spdif_aclink ? "ATIIXP" : "ATIIXP-SPDMA");
1da177e4
LT		 1660 strcpy(card->shortname, "ATI IXP");
1661 if ((err = snd_atiixp_create(card, pci, &chip)) < 0)
1662 goto __error;
92304cc7 1663 card->private_data = chip;
1da177e4
LT		 1664
1665 if ((err = snd_atiixp_aclink_reset(chip)) < 0)
1666 goto __error;
1667
b7fe4622 1668 chip->spdif_over_aclink = spdif_aclink;
1da177e4 1669
b7fe4622 1670 if ((err = snd_atiixp_mixer_new(chip, ac97_clock, ac97_quirk)) < 0)
1da177e4
LT		 1671 goto __error;
1672
1673 if ((err = snd_atiixp_pcm_new(chip)) < 0)
1674 goto __error;
1675
1676 snd_atiixp_proc_init(chip);
1677
1678 snd_atiixp_chip_start(chip);
1679
1680 snprintf(card->longname, sizeof(card->longname),
44c10138
AK		 1681 "%s rev %x with %s at %#lx, irq %i", card->shortname,
1682 pci->revision,
1da177e4
LT		 1683 chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?",
1684 chip->addr, chip->irq);
1685
1da177e4
LT		 1686 if ((err = snd_card_register(card)) < 0)
1687 goto __error;
1688
1689 pci_set_drvdata(pci, card);
1da177e4
LT		 1690 return 0;
1691
1692 __error:
1693 snd_card_free(card);
1694 return err;
1695}
1696
1697static void __devexit snd_atiixp_remove(struct pci_dev *pci)
1698{
1699 snd_card_free(pci_get_drvdata(pci));
1700 pci_set_drvdata(pci, NULL);
1701}
1702
1703static struct pci_driver driver = {
3733e424 1704 .name = KBUILD_MODNAME,
1da177e4
LT		 1705 .id_table = snd_atiixp_ids,
1706 .probe = snd_atiixp_probe,
1707 .remove = __devexit_p(snd_atiixp_remove),
92304cc7
TI		 1708#ifdef CONFIG_PM
1709 .suspend = snd_atiixp_suspend,
1710 .resume = snd_atiixp_resume,
1711#endif
1da177e4
LT		 1712};
1713
1714
1715static int __init alsa_card_atiixp_init(void)
1716{
01d25d46 1717 return pci_register_driver(&driver);
1da177e4
LT		 1718}
1719
1720static void __exit alsa_card_atiixp_exit(void)
1721{
1722 pci_unregister_driver(&driver);
1723}
1724
1725module_init(alsa_card_atiixp_init)
1726module_exit(alsa_card_atiixp_exit)
kernel source for telekom puls (alcatel/mediatek)