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Fix common misspellings
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath5k / eeprom.c
CommitLineData
c6e387a2
NK		 1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
8e218fb2
NK		 3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
c6e387a2
NK		 5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20/*************************************\
21* EEPROM access functions and helpers *
22\*************************************/
23
5a0e3ad6
TH		 24#include <linux/slab.h>
25
c6e387a2
NK		 26#include "ath5k.h"
27#include "reg.h"
28#include "debug.h"
29#include "base.h"
30
9320b5c4
NK		 31
32/******************\
33* Helper functions *
34\******************/
35
36/*
37 * Translate binary channel representation in EEPROM to frequency
38 */
39static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
40 unsigned int mode)
41{
42 u16 val;
43
44 if (bin == AR5K_EEPROM_CHANNEL_DIS)
45 return bin;
46
47 if (mode == AR5K_EEPROM_MODE_11A) {
48 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
49 val = (5 * bin) + 4800;
50 else
51 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
52 (bin * 10) + 5100;
53 } else {
54 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
55 val = bin + 2300;
56 else
57 val = bin + 2400;
58 }
59
60 return val;
61}
62
63
64/*********\
65* Parsers *
66\*********/
67
1048643e
FF		 68/*
69 * Initialize eeprom & capabilities structs
70 */
71static int
72ath5k_eeprom_init_header(struct ath5k_hw *ah)
73{
74 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1048643e 75 u16 val;
359207c6 76 u32 cksum, offset, eep_max = AR5K_EEPROM_INFO_MAX;
1048643e 77
1048643e
FF		 78 /*
79 * Read values from EEPROM and store them in the capability structure
80 */
81 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
82 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
83 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
84 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
85 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
86
87 /* Return if we have an old EEPROM */
88 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
89 return 0;
90
1048643e
FF		 91 /*
92 * Validate the checksum of the EEPROM date. There are some
93 * devices with invalid EEPROMs.
94 */
359207c6
LR		 95 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val);
96 if (val) {
97 eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) <<
98 AR5K_EEPROM_SIZE_ENDLOC_SHIFT;
99 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_LOWER, val);
100 eep_max = (eep_max | val) - AR5K_EEPROM_INFO_BASE;
101
102 /*
103 * Fail safe check to prevent stupid loops due
104 * to busted EEPROMs. XXX: This value is likely too
105 * big still, waiting on a better value.
106 */
107 if (eep_max > (3 * AR5K_EEPROM_INFO_MAX)) {
108 ATH5K_ERR(ah->ah_sc, "Invalid max custom EEPROM size: "
109 "%d (0x%04x) max expected: %d (0x%04x)\n",
110 eep_max, eep_max,
111 3 * AR5K_EEPROM_INFO_MAX,
112 3 * AR5K_EEPROM_INFO_MAX);
113 return -EIO;
114 }
115 }
116
117 for (cksum = 0, offset = 0; offset < eep_max; offset++) {
1048643e
FF		 118 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
119 cksum ^= val;
120 }
121 if (cksum != AR5K_EEPROM_INFO_CKSUM) {
359207c6
LR		 122 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM "
123 "checksum: 0x%04x eep_max: 0x%04x (%s)\n",
124 cksum, eep_max,
125 eep_max == AR5K_EEPROM_INFO_MAX ?
126 "default size" : "custom size");
1048643e
FF		 127 return -EIO;
128 }
1048643e
FF		 129
130 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
131 ee_ant_gain);
132
133 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
134 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
135 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
0ea9c00c
NK		 136
137 /* XXX: Don't know which versions include these two */
138 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC2, ee_misc2);
139
140 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3)
141 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC3, ee_misc3);
142
143 if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) {
144 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC4, ee_misc4);
145 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC5, ee_misc5);
146 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC6, ee_misc6);
147 }
1048643e
FF		 148 }
149
150 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
151 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
152 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
153 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
154
155 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
156 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
157 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
158 }
159
1889ba0a
NK		 160 AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val);
161
162 if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && val)
163 ee->ee_is_hb63 = true;
164 else
165 ee->ee_is_hb63 = false;
166
167 AR5K_EEPROM_READ(AR5K_EEPROM_RFKILL, val);
168 ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL);
169 ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false;
170
c38e7a93
NK		 171 /* Check if PCIE_OFFSET points to PCIE_SERDES_SECTION
172 * and enable serdes programming if needed.
173 *
174 * XXX: Serdes values seem to be fixed so
175 * no need to read them here, we write them
132b1c3e 176 * during ath5k_hw_init */
c38e7a93
NK		 177 AR5K_EEPROM_READ(AR5K_EEPROM_PCIE_OFFSET, val);
178 ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ?
179 true : false;
180
1048643e
FF		 181 return 0;
182}
183
184
c6e387a2
NK		 185/*
186 * Read antenna infos from eeprom
187 */
188static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
189 unsigned int mode)
190{
191 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
192 u32 o = *offset;
193 u16 val;
fda9b7af 194 int i = 0;
c6e387a2
NK		 195
196 AR5K_EEPROM_READ(o++, val);
197 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
1048643e 198 ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f;
c6e387a2
NK		 199 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
200
201 AR5K_EEPROM_READ(o++, val);
202 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
203 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
204 ee->ee_ant_control[mode][i++] = val & 0x3f;
205
206 AR5K_EEPROM_READ(o++, val);
207 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
208 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
209 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
210
211 AR5K_EEPROM_READ(o++, val);
212 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
213 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
214 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
215 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
216
217 AR5K_EEPROM_READ(o++, val);
218 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
219 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
220 ee->ee_ant_control[mode][i++] = val & 0x3f;
221
2bed03eb
NK		 222 /* Get antenna switch tables */
223 ah->ah_ant_ctl[mode][AR5K_ANT_CTL] =
e8f055f0 224 (ee->ee_ant_control[mode][0] << 4);
2bed03eb 225 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] =
c6e387a2
NK		 226 ee->ee_ant_control[mode][1] |
227 (ee->ee_ant_control[mode][2] << 6) |
228 (ee->ee_ant_control[mode][3] << 12) |
229 (ee->ee_ant_control[mode][4] << 18) |
230 (ee->ee_ant_control[mode][5] << 24);
2bed03eb 231 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] =
c6e387a2
NK		 232 ee->ee_ant_control[mode][6] |
233 (ee->ee_ant_control[mode][7] << 6) |
234 (ee->ee_ant_control[mode][8] << 12) |
235 (ee->ee_ant_control[mode][9] << 18) |
236 (ee->ee_ant_control[mode][10] << 24);
237
238 /* return new offset */
239 *offset = o;
240
241 return 0;
242}
243
244/*
0ea9c00c
NK		 245 * Read supported modes and some mode-specific calibration data
246 * from eeprom
c6e387a2
NK		 247 */
248static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
249 unsigned int mode)
250{
251 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
252 u32 o = *offset;
253 u16 val;
c6e387a2 254
1048643e
FF		 255 ee->ee_n_piers[mode] = 0;
256 AR5K_EEPROM_READ(o++, val);
257 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
258 switch(mode) {
259 case AR5K_EEPROM_MODE_11A:
8e218fb2
NK		 260 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
261 ee->ee_db[mode][3] = (val >> 2) & 0x7;
262 ee->ee_ob[mode][2] = (val << 1) & 0x7;
1048643e
FF		 263
264 AR5K_EEPROM_READ(o++, val);
8e218fb2
NK		 265 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
266 ee->ee_db[mode][2] = (val >> 12) & 0x7;
267 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
268 ee->ee_db[mode][1] = (val >> 6) & 0x7;
269 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
270 ee->ee_db[mode][0] = val & 0x7;
1048643e
FF		 271 break;
272 case AR5K_EEPROM_MODE_11G:
273 case AR5K_EEPROM_MODE_11B:
8e218fb2
NK		 274 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
275 ee->ee_db[mode][1] = val & 0x7;
1048643e
FF		 276 break;
277 }
278
c6e387a2
NK		 279 AR5K_EEPROM_READ(o++, val);
280 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
281 ee->ee_thr_62[mode] = val & 0xff;
282
283 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
284 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
285
286 AR5K_EEPROM_READ(o++, val);
287 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
288 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
289
290 AR5K_EEPROM_READ(o++, val);
291 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
292
293 if ((val & 0xff) & 0x80)
294 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
295 else
296 ee->ee_noise_floor_thr[mode] = val & 0xff;
297
298 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
299 ee->ee_noise_floor_thr[mode] =
300 mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
301
302 AR5K_EEPROM_READ(o++, val);
303 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
304 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
305 ee->ee_xpd[mode] = val & 0x1;
306
687c8ff1
BR		 307 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
308 mode != AR5K_EEPROM_MODE_11B)
c6e387a2
NK		 309 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
310
311 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
312 AR5K_EEPROM_READ(o++, val);
313 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
314
315 if (mode == AR5K_EEPROM_MODE_11A)
316 ee->ee_xr_power[mode] = val & 0x3f;
317 else {
687c8ff1 318 /* b_DB_11[bg] and b_OB_11[bg] */
c6e387a2
NK		 319 ee->ee_ob[mode][0] = val & 0x7;
320 ee->ee_db[mode][0] = (val >> 3) & 0x7;
321 }
322 }
323
324 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
325 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
326 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
327 } else {
328 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
329
330 AR5K_EEPROM_READ(o++, val);
331 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
332
1048643e 333 if (mode == AR5K_EEPROM_MODE_11G) {
c6e387a2 334 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
1048643e
FF		 335 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6)
336 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
337 }
c6e387a2
NK		 338 }
339
340 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
341 mode == AR5K_EEPROM_MODE_11A) {
342 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
343 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
344 }
345
1048643e
FF		 346 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_0)
347 goto done;
348
0ea9c00c
NK		 349 /* Note: >= v5 have bg freq piers on another location
350 * so these freq piers are ignored for >= v5 (should be 0xff
351 * anyway) */
1048643e
FF		 352 switch(mode) {
353 case AR5K_EEPROM_MODE_11A:
354 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1)
355 break;
356
357 AR5K_EEPROM_READ(o++, val);
358 ee->ee_margin_tx_rx[mode] = val & 0x3f;
359 break;
360 case AR5K_EEPROM_MODE_11B:
361 AR5K_EEPROM_READ(o++, val);
362
363 ee->ee_pwr_cal_b[0].freq =
364 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
365 if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS)
366 ee->ee_n_piers[mode]++;
367
368 ee->ee_pwr_cal_b[1].freq =
369 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
370 if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS)
371 ee->ee_n_piers[mode]++;
372
373 AR5K_EEPROM_READ(o++, val);
374 ee->ee_pwr_cal_b[2].freq =
375 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
376 if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS)
377 ee->ee_n_piers[mode]++;
378
379 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
380 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
381 break;
382 case AR5K_EEPROM_MODE_11G:
383 AR5K_EEPROM_READ(o++, val);
384
385 ee->ee_pwr_cal_g[0].freq =
386 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
387 if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS)
388 ee->ee_n_piers[mode]++;
389
390 ee->ee_pwr_cal_g[1].freq =
391 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
392 if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS)
393 ee->ee_n_piers[mode]++;
394
395 AR5K_EEPROM_READ(o++, val);
396 ee->ee_turbo_max_power[mode] = val & 0x7f;
397 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
398
399 AR5K_EEPROM_READ(o++, val);
400 ee->ee_pwr_cal_g[2].freq =
401 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
402 if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS)
403 ee->ee_n_piers[mode]++;
c6e387a2 404
1048643e
FF		 405 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
406 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
407
408 AR5K_EEPROM_READ(o++, val);
5f13bfac
BR		 409 ee->ee_i_cal[mode] = (val >> 5) & 0x3f;
410 ee->ee_q_cal[mode] = val & 0x1f;
1048643e
FF		 411
412 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
413 AR5K_EEPROM_READ(o++, val);
414 ee->ee_cck_ofdm_gain_delta = val & 0xff;
415 }
416 break;
417 }
418
3b3ee43d
PR		 419 /*
420 * Read turbo mode information on newer EEPROM versions
421 */
1048643e 422 if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
3b3ee43d 423 goto done;
c6e387a2 424
1048643e
FF		 425 switch (mode){
426 case AR5K_EEPROM_MODE_11A:
427 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
c6e387a2 428
1048643e
FF		 429 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
430 AR5K_EEPROM_READ(o++, val);
431 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
432 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;
433
434 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
435 AR5K_EEPROM_READ(o++, val);
436 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
437 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
438
439 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2)
440 ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
441 break;
442 case AR5K_EEPROM_MODE_11G:
443 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;
444
445 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
446 AR5K_EEPROM_READ(o++, val);
447 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
448 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;
449
450 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
451 AR5K_EEPROM_READ(o++, val);
452 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
453 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
454 break;
455 }
456
3b3ee43d 457done:
1048643e
FF		 458 /* return new offset */
459 *offset = o;
460
461 return 0;
462}
463
0ea9c00c 464/* Read mode-specific data (except power calibration data) */
1048643e
FF		 465static int
466ath5k_eeprom_init_modes(struct ath5k_hw *ah)
467{
468 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
469 u32 mode_offset[3];
470 unsigned int mode;
471 u32 offset;
472 int ret;
c6e387a2 473
c6e387a2 474 /*
1048643e 475 * Get values for all modes
c6e387a2 476 */
1048643e
FF		 477 mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
478 mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
479 mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
480
481 ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] =
482 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
483
484 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) {
485 offset = mode_offset[mode];
486
487 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
488 if (ret)
489 return ret;
490
491 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
492 if (ret)
493 return ret;
c6e387a2 494 }
1048643e
FF		 495
496 /* override for older eeprom versions for better performance */
497 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) {
498 ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15;
499 ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28;
500 ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28;
c6e387a2 501 }
c6e387a2 502
1048643e
FF		 503 return 0;
504}
c6e387a2 505
0ea9c00c
NK		 506/* Read the frequency piers for each mode (mostly used on newer eeproms with 0xff
507 * frequency mask) */
1048643e
FF		 508static inline int
509ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max,
0ea9c00c 510 struct ath5k_chan_pcal_info *pc, unsigned int mode)
1048643e 511{
0ea9c00c 512 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1048643e
FF		 513 int o = *offset;
514 int i = 0;
0ea9c00c 515 u8 freq1, freq2;
1048643e
FF		 516 u16 val;
517
8e218fb2 518 ee->ee_n_piers[mode] = 0;
1048643e
FF		 519 while(i < max) {
520 AR5K_EEPROM_READ(o++, val);
521
8e218fb2
NK		 522 freq1 = val & 0xff;
523 if (!freq1)
524 break;
1048643e 525
8e218fb2
NK		 526 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
527 freq1, mode);
528 ee->ee_n_piers[mode]++;
1048643e 529
8e218fb2
NK		 530 freq2 = (val >> 8) & 0xff;
531 if (!freq2)
1048643e 532 break;
8e218fb2
NK		 533
534 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
535 freq2, mode);
536 ee->ee_n_piers[mode]++;
c6e387a2 537 }
0ea9c00c
NK		 538
539 /* return new offset */
1048643e 540 *offset = o;
c6e387a2 541
1048643e
FF		 542 return 0;
543}
544
0ea9c00c 545/* Read frequency piers for 802.11a */
1048643e
FF		 546static int
547ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset)
548{
549 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
550 struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a;
fda9b7af 551 int i;
1048643e
FF		 552 u16 val;
553 u8 mask;
554
555 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
556 ath5k_eeprom_read_freq_list(ah, &offset,
557 AR5K_EEPROM_N_5GHZ_CHAN, pcal,
0ea9c00c 558 AR5K_EEPROM_MODE_11A);
1048643e
FF		 559 } else {
560 mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version);
c6e387a2 561
c6e387a2 562 AR5K_EEPROM_READ(offset++, val);
1048643e
FF		 563 pcal[0].freq = (val >> 9) & mask;
564 pcal[1].freq = (val >> 2) & mask;
565 pcal[2].freq = (val << 5) & mask;
566
567 AR5K_EEPROM_READ(offset++, val);
568 pcal[2].freq |= (val >> 11) & 0x1f;
569 pcal[3].freq = (val >> 4) & mask;
570 pcal[4].freq = (val << 3) & mask;
571
572 AR5K_EEPROM_READ(offset++, val);
573 pcal[4].freq |= (val >> 13) & 0x7;
574 pcal[5].freq = (val >> 6) & mask;
575 pcal[6].freq = (val << 1) & mask;
576
577 AR5K_EEPROM_READ(offset++, val);
578 pcal[6].freq |= (val >> 15) & 0x1;
579 pcal[7].freq = (val >> 8) & mask;
580 pcal[8].freq = (val >> 1) & mask;
581 pcal[9].freq = (val << 6) & mask;
582
583 AR5K_EEPROM_READ(offset++, val);
584 pcal[9].freq |= (val >> 10) & 0x3f;
0ea9c00c
NK		 585
586 /* Fixed number of piers */
1048643e 587 ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10;
c6e387a2 588
0ea9c00c
NK		 589 for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
590 pcal[i].freq = ath5k_eeprom_bin2freq(ee,
1048643e 591 pcal[i].freq, AR5K_EEPROM_MODE_11A);
0ea9c00c 592 }
1048643e 593 }
c6e387a2 594
1048643e
FF		 595 return 0;
596}
c6e387a2 597
0ea9c00c 598/* Read frequency piers for 802.11bg on eeprom versions >= 5 and eemap >= 2 */
1048643e
FF		 599static inline int
600ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
601{
602 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
603 struct ath5k_chan_pcal_info *pcal;
1048643e
FF		 604
605 switch(mode) {
606 case AR5K_EEPROM_MODE_11B:
607 pcal = ee->ee_pwr_cal_b;
608 break;
609 case AR5K_EEPROM_MODE_11G:
610 pcal = ee->ee_pwr_cal_g;
611 break;
612 default:
613 return -EINVAL;
614 }
c6e387a2 615
1048643e
FF		 616 ath5k_eeprom_read_freq_list(ah, &offset,
617 AR5K_EEPROM_N_2GHZ_CHAN_2413, pcal,
0ea9c00c 618 mode);
c6e387a2 619
1048643e
FF		 620 return 0;
621}
c6e387a2 622
9320b5c4 623
8e218fb2
NK		 624/*
625 * Read power calibration for RF5111 chips
626 *
0ea9c00c 627 * For RF5111 we have an XPD -eXternal Power Detector- curve
8e218fb2
NK		 628 * for each calibrated channel. Each curve has 0,5dB Power steps
629 * on x axis and PCDAC steps (offsets) on y axis and looks like an
630 * exponential function. To recreate the curve we read 11 points
631 * here and interpolate later.
0ea9c00c 632 */
8e218fb2
NK		 633
634/* Used to match PCDAC steps with power values on RF5111 chips
635 * (eeprom versions < 4). For RF5111 we have 11 pre-defined PCDAC
636 * steps that match with the power values we read from eeprom. On
637 * older eeprom versions (< 3.2) these steps are equaly spaced at
a180a130 638 * 10% of the pcdac curve -until the curve reaches its maximum-
8e218fb2
NK		 639 * (11 steps from 0 to 100%) but on newer eeprom versions (>= 3.2)
640 * these 11 steps are spaced in a different way. This function returns
641 * the pcdac steps based on eeprom version and curve min/max so that we
642 * can have pcdac/pwr points.
643 */
644static inline void
645ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
646{
bbb33881 647 static const u16 intercepts3[] =
8e218fb2 648 { 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
bbb33881 649 static const u16 intercepts3_2[] =
8e218fb2
NK		 650 { 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
651 const u16 *ip;
652 int i;
653
654 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_2)
655 ip = intercepts3_2;
656 else
657 ip = intercepts3;
658
659 for (i = 0; i < ARRAY_SIZE(intercepts3); i++)
660 vp[i] = (ip[i] * max + (100 - ip[i]) * min) / 100;
661}
662
663/* Convert RF5111 specific data to generic raw data
664 * used by interpolation code */
665static int
666ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode,
667 struct ath5k_chan_pcal_info *chinfo)
668{
669 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
670 struct ath5k_chan_pcal_info_rf5111 *pcinfo;
671 struct ath5k_pdgain_info *pd;
672 u8 pier, point, idx;
673 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
674
675 /* Fill raw data for each calibration pier */
676 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
677
678 pcinfo = &chinfo[pier].rf5111_info;
679
680 /* Allocate pd_curves for this cal pier */
681 chinfo[pier].pd_curves =
682 kcalloc(AR5K_EEPROM_N_PD_CURVES,
683 sizeof(struct ath5k_pdgain_info),
684 GFP_KERNEL);
685
686 if (!chinfo[pier].pd_curves)
687 return -ENOMEM;
688
689 /* Only one curve for RF5111
690 * find out which one and place
77c2061d 691 * in pd_curves.
8e218fb2
NK		 692 * Note: ee_x_gain is reversed here */
693 for (idx = 0; idx < AR5K_EEPROM_N_PD_CURVES; idx++) {
694
695 if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) {
696 pdgain_idx[0] = idx;
697 break;
698 }
699 }
700
701 ee->ee_pd_gains[mode] = 1;
702
703 pd = &chinfo[pier].pd_curves[idx];
704
705 pd->pd_points = AR5K_EEPROM_N_PWR_POINTS_5111;
706
707 /* Allocate pd points for this curve */
708 pd->pd_step = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
709 sizeof(u8), GFP_KERNEL);
710 if (!pd->pd_step)
711 return -ENOMEM;
712
713 pd->pd_pwr = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
714 sizeof(s16), GFP_KERNEL);
715 if (!pd->pd_pwr)
716 return -ENOMEM;
717
718 /* Fill raw dataset
719 * (convert power to 0.25dB units
720 * for RF5112 combatibility) */
721 for (point = 0; point < pd->pd_points; point++) {
722
723 /* Absolute values */
724 pd->pd_pwr[point] = 2 * pcinfo->pwr[point];
725
726 /* Already sorted */
727 pd->pd_step[point] = pcinfo->pcdac[point];
728 }
729
730 /* Set min/max pwr */
731 chinfo[pier].min_pwr = pd->pd_pwr[0];
732 chinfo[pier].max_pwr = pd->pd_pwr[10];
733
734 }
735
736 return 0;
737}
738
739/* Parse EEPROM data */
1048643e
FF		 740static int
741ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
742{
743 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
744 struct ath5k_chan_pcal_info *pcal;
745 int offset, ret;
eaee7cc2 746 int i;
1048643e
FF		 747 u16 val;
748
749 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
750 switch(mode) {
751 case AR5K_EEPROM_MODE_11A:
752 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
753 return 0;
754
755 ret = ath5k_eeprom_init_11a_pcal_freq(ah,
756 offset + AR5K_EEPROM_GROUP1_OFFSET);
757 if (ret < 0)
758 return ret;
759
760 offset += AR5K_EEPROM_GROUP2_OFFSET;
761 pcal = ee->ee_pwr_cal_a;
762 break;
763 case AR5K_EEPROM_MODE_11B:
764 if (!AR5K_EEPROM_HDR_11B(ee->ee_header) &&
765 !AR5K_EEPROM_HDR_11G(ee->ee_header))
766 return 0;
767
768 pcal = ee->ee_pwr_cal_b;
769 offset += AR5K_EEPROM_GROUP3_OFFSET;
770
771 /* fixed piers */
772 pcal[0].freq = 2412;
773 pcal[1].freq = 2447;
774 pcal[2].freq = 2484;
775 ee->ee_n_piers[mode] = 3;
776 break;
777 case AR5K_EEPROM_MODE_11G:
778 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
779 return 0;
780
781 pcal = ee->ee_pwr_cal_g;
782 offset += AR5K_EEPROM_GROUP4_OFFSET;
783
784 /* fixed piers */
785 pcal[0].freq = 2312;
786 pcal[1].freq = 2412;
787 pcal[2].freq = 2484;
788 ee->ee_n_piers[mode] = 3;
789 break;
790 default:
791 return -EINVAL;
c6e387a2
NK		 792 }
793
1048643e
FF		 794 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
795 struct ath5k_chan_pcal_info_rf5111 *cdata =
796 &pcal[i].rf5111_info;
c6e387a2 797
1048643e
FF		 798 AR5K_EEPROM_READ(offset++, val);
799 cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M);
800 cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M);
801 cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M);
c6e387a2 802
1048643e
FF		 803 AR5K_EEPROM_READ(offset++, val);
804 cdata->pwr[0] |= ((val >> 14) & 0x3);
805 cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M);
806 cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M);
807 cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M);
c6e387a2 808
1048643e
FF		 809 AR5K_EEPROM_READ(offset++, val);
810 cdata->pwr[3] |= ((val >> 12) & 0xf);
811 cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M);
812 cdata->pwr[5] = (val & AR5K_EEPROM_POWER_M);
c6e387a2 813
c6e387a2 814 AR5K_EEPROM_READ(offset++, val);
1048643e
FF		 815 cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M);
816 cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M);
817 cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M);
c6e387a2
NK		 818
819 AR5K_EEPROM_READ(offset++, val);
1048643e
FF		 820 cdata->pwr[8] |= ((val >> 14) & 0x3);
821 cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M);
822 cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M);
823
824 ath5k_get_pcdac_intercepts(ah, cdata->pcdac_min,
825 cdata->pcdac_max, cdata->pcdac);
c6e387a2
NK		 826 }
827
8e218fb2 828 return ath5k_eeprom_convert_pcal_info_5111(ah, mode, pcal);
1048643e 829}
c6e387a2 830
8e218fb2
NK		 831
832/*
833 * Read power calibration for RF5112 chips
834 *
0ea9c00c
NK		 835 * For RF5112 we have 4 XPD -eXternal Power Detector- curves
836 * for each calibrated channel on 0, -6, -12 and -18dbm but we only
8e218fb2
NK		 837 * use the higher (3) and the lower (0) curves. Each curve has 0.5dB
838 * power steps on x axis and PCDAC steps on y axis and looks like a
839 * linear function. To recreate the curve and pass the power values
840 * on hw, we read 4 points for xpd 0 (lower gain -> max power)
841 * and 3 points for xpd 3 (higher gain -> lower power) here and
842 * interpolate later.
0ea9c00c
NK		 843 *
844 * Note: Many vendors just use xpd 0 so xpd 3 is zeroed.
845 */
8e218fb2
NK		 846
847/* Convert RF5112 specific data to generic raw data
848 * used by interpolation code */
849static int
850ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode,
851 struct ath5k_chan_pcal_info *chinfo)
852{
853 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
854 struct ath5k_chan_pcal_info_rf5112 *pcinfo;
855 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
856 unsigned int pier, pdg, point;
857
858 /* Fill raw data for each calibration pier */
859 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
860
861 pcinfo = &chinfo[pier].rf5112_info;
862
863 /* Allocate pd_curves for this cal pier */
864 chinfo[pier].pd_curves =
865 kcalloc(AR5K_EEPROM_N_PD_CURVES,
866 sizeof(struct ath5k_pdgain_info),
867 GFP_KERNEL);
868
869 if (!chinfo[pier].pd_curves)
870 return -ENOMEM;
871
872 /* Fill pd_curves */
873 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
874
875 u8 idx = pdgain_idx[pdg];
876 struct ath5k_pdgain_info *pd =
877 &chinfo[pier].pd_curves[idx];
878
879 /* Lowest gain curve (max power) */
880 if (pdg == 0) {
881 /* One more point for better accuracy */
882 pd->pd_points = AR5K_EEPROM_N_XPD0_POINTS;
883
884 /* Allocate pd points for this curve */
885 pd->pd_step = kcalloc(pd->pd_points,
886 sizeof(u8), GFP_KERNEL);
887
888 if (!pd->pd_step)
889 return -ENOMEM;
890
891 pd->pd_pwr = kcalloc(pd->pd_points,
892 sizeof(s16), GFP_KERNEL);
893
894 if (!pd->pd_pwr)
895 return -ENOMEM;
896
897
898 /* Fill raw dataset
899 * (all power levels are in 0.25dB units) */
900 pd->pd_step[0] = pcinfo->pcdac_x0[0];
901 pd->pd_pwr[0] = pcinfo->pwr_x0[0];
902
903 for (point = 1; point < pd->pd_points;
904 point++) {
905 /* Absolute values */
906 pd->pd_pwr[point] =
907 pcinfo->pwr_x0[point];
908
909 /* Deltas */
910 pd->pd_step[point] =
911 pd->pd_step[point - 1] +
912 pcinfo->pcdac_x0[point];
913 }
914
915 /* Set min power for this frequency */
916 chinfo[pier].min_pwr = pd->pd_pwr[0];
917
918 /* Highest gain curve (min power) */
919 } else if (pdg == 1) {
920
921 pd->pd_points = AR5K_EEPROM_N_XPD3_POINTS;
922
923 /* Allocate pd points for this curve */
924 pd->pd_step = kcalloc(pd->pd_points,
925 sizeof(u8), GFP_KERNEL);
926
927 if (!pd->pd_step)
928 return -ENOMEM;
929
930 pd->pd_pwr = kcalloc(pd->pd_points,
931 sizeof(s16), GFP_KERNEL);
932
933 if (!pd->pd_pwr)
934 return -ENOMEM;
935
936 /* Fill raw dataset
937 * (all power levels are in 0.25dB units) */
938 for (point = 0; point < pd->pd_points;
939 point++) {
940 /* Absolute values */
941 pd->pd_pwr[point] =
942 pcinfo->pwr_x3[point];
943
944 /* Fixed points */
945 pd->pd_step[point] =
946 pcinfo->pcdac_x3[point];
947 }
948
949 /* Since we have a higher gain curve
950 * override min power */
951 chinfo[pier].min_pwr = pd->pd_pwr[0];
952 }
953 }
954 }
955
956 return 0;
957}
958
959/* Parse EEPROM data */
1048643e
FF		 960static int
961ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
962{
963 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
964 struct ath5k_chan_pcal_info_rf5112 *chan_pcal_info;
965 struct ath5k_chan_pcal_info *gen_chan_info;
8e218fb2 966 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1048643e 967 u32 offset;
8e218fb2 968 u8 i, c;
1048643e 969 u16 val;
8e218fb2
NK		 970 u8 pd_gains = 0;
971
972 /* Count how many curves we have and
973 * identify them (which one of the 4
974 * available curves we have on each count).
975 * Curves are stored from lower (x0) to
976 * higher (x3) gain */
977 for (i = 0; i < AR5K_EEPROM_N_PD_CURVES; i++) {
978 /* ee_x_gain[mode] is x gain mask */
979 if ((ee->ee_x_gain[mode] >> i) & 0x1)
980 pdgain_idx[pd_gains++] = i;
981 }
982 ee->ee_pd_gains[mode] = pd_gains;
983
984 if (pd_gains == 0 || pd_gains > 2)
985 return -EINVAL;
c6e387a2 986
1048643e
FF		 987 switch (mode) {
988 case AR5K_EEPROM_MODE_11A:
989 /*
990 * Read 5GHz EEPROM channels
991 */
992 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
993 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
994
995 offset += AR5K_EEPROM_GROUP2_OFFSET;
996 gen_chan_info = ee->ee_pwr_cal_a;
997 break;
998 case AR5K_EEPROM_MODE_11B:
999 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1000 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1001 offset += AR5K_EEPROM_GROUP3_OFFSET;
1002
1003 /* NB: frequency piers parsed during mode init */
1004 gen_chan_info = ee->ee_pwr_cal_b;
1005 break;
1006 case AR5K_EEPROM_MODE_11G:
1007 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1008 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1009 offset += AR5K_EEPROM_GROUP4_OFFSET;
1010 else if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1011 offset += AR5K_EEPROM_GROUP2_OFFSET;
1012
1013 /* NB: frequency piers parsed during mode init */
1014 gen_chan_info = ee->ee_pwr_cal_g;
1015 break;
1016 default:
1017 return -EINVAL;
1018 }
c6e387a2 1019
1048643e
FF		 1020 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1021 chan_pcal_info = &gen_chan_info[i].rf5112_info;
c6e387a2 1022
8e218fb2 1023 /* Power values in quarter dB
1048643e
FF		 1024 * for the lower xpd gain curve
1025 * (0 dBm -> higher output power) */
1026 for (c = 0; c < AR5K_EEPROM_N_XPD0_POINTS; c++) {
1027 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1028 chan_pcal_info->pwr_x0[c] = (s8) (val & 0xff);
1029 chan_pcal_info->pwr_x0[++c] = (s8) ((val >> 8) & 0xff);
1048643e 1030 }
c6e387a2 1031
1048643e
FF		 1032 /* PCDAC steps
1033 * corresponding to the above power
1034 * measurements */
c6e387a2 1035 AR5K_EEPROM_READ(offset++, val);
1048643e
FF		 1036 chan_pcal_info->pcdac_x0[1] = (val & 0x1f);
1037 chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f);
1038 chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f);
c6e387a2 1039
8e218fb2 1040 /* Power values in quarter dB
1048643e
FF		 1041 * for the higher xpd gain curve
1042 * (18 dBm -> lower output power) */
c6e387a2 1043 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1044 chan_pcal_info->pwr_x3[0] = (s8) (val & 0xff);
1045 chan_pcal_info->pwr_x3[1] = (s8) ((val >> 8) & 0xff);
c6e387a2
NK		 1046
1047 AR5K_EEPROM_READ(offset++, val);
1048643e
FF		 1048 chan_pcal_info->pwr_x3[2] = (val & 0xff);
1049
1050 /* PCDAC steps
1051 * corresponding to the above power
0ea9c00c 1052 * measurements (fixed) */
1048643e
FF		 1053 chan_pcal_info->pcdac_x3[0] = 20;
1054 chan_pcal_info->pcdac_x3[1] = 35;
1055 chan_pcal_info->pcdac_x3[2] = 63;
1056
1057 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) {
8e218fb2 1058 chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0x3f);
1048643e
FF		 1059
1060 /* Last xpd0 power level is also channel maximum */
1061 gen_chan_info[i].max_pwr = chan_pcal_info->pwr_x0[3];
1062 } else {
1063 chan_pcal_info->pcdac_x0[0] = 1;
8e218fb2 1064 gen_chan_info[i].max_pwr = (s8) ((val >> 8) & 0xff);
1048643e 1065 }
c6e387a2 1066
1048643e
FF		 1067 }
1068
8e218fb2 1069 return ath5k_eeprom_convert_pcal_info_5112(ah, mode, gen_chan_info);
1048643e
FF		 1070}
1071
8e218fb2
NK		 1072
1073/*
1074 * Read power calibration for RF2413 chips
1075 *
1076 * For RF2413 we have a Power to PDDAC table (Power Detector)
1077 * instead of a PCDAC and 4 pd gain curves for each calibrated channel.
1078 * Each curve has power on x axis in 0.5 db steps and PDDADC steps on y
1079 * axis and looks like an exponential function like the RF5111 curve.
1080 *
1081 * To recreate the curves we read here the points and interpolate
1082 * later. Note that in most cases only 2 (higher and lower) curves are
25985edc 1083 * used (like RF5112) but vendors have the opportunity to include all
8e218fb2
NK		 1084 * 4 curves on eeprom. The final curve (higher power) has an extra
1085 * point for better accuracy like RF5112.
1086 */
1087
0ea9c00c 1088/* For RF2413 power calibration data doesn't start on a fixed location and
a180a130 1089 * if a mode is not supported, its section is missing -not zeroed-.
0ea9c00c
NK		 1090 * So we need to calculate the starting offset for each section by using
1091 * these two functions */
1092
1093/* Return the size of each section based on the mode and the number of pd
1094 * gains available (maximum 4). */
1048643e
FF		 1095static inline unsigned int
1096ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode)
1097{
1098 static const unsigned int pdgains_size[] = { 4, 6, 9, 12 };
1099 unsigned int sz;
1100
1101 sz = pdgains_size[ee->ee_pd_gains[mode] - 1];
1102 sz *= ee->ee_n_piers[mode];
1103
1104 return sz;
1105}
1106
0ea9c00c
NK		 1107/* Return the starting offset for a section based on the modes supported
1108 * and each section's size. */
1048643e
FF		 1109static unsigned int
1110ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
1111{
1112 u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
1113
1114 switch(mode) {
1115 case AR5K_EEPROM_MODE_11G:
1116 if (AR5K_EEPROM_HDR_11B(ee->ee_header))
8e218fb2
NK		 1117 offset += ath5k_pdgains_size_2413(ee,
1118 AR5K_EEPROM_MODE_11B) +
1119 AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1048643e
FF		 1120 /* fall through */
1121 case AR5K_EEPROM_MODE_11B:
1122 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
8e218fb2
NK		 1123 offset += ath5k_pdgains_size_2413(ee,
1124 AR5K_EEPROM_MODE_11A) +
1125 AR5K_EEPROM_N_5GHZ_CHAN / 2;
1048643e
FF		 1126 /* fall through */
1127 case AR5K_EEPROM_MODE_11A:
1128 break;
1129 default:
1130 break;
1131 }
1132
1133 return offset;
1134}
1135
8e218fb2
NK		 1136/* Convert RF2413 specific data to generic raw data
1137 * used by interpolation code */
1138static int
1139ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode,
1140 struct ath5k_chan_pcal_info *chinfo)
1141{
1142 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1143 struct ath5k_chan_pcal_info_rf2413 *pcinfo;
1144 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1145 unsigned int pier, pdg, point;
1146
1147 /* Fill raw data for each calibration pier */
1148 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1149
1150 pcinfo = &chinfo[pier].rf2413_info;
1151
1152 /* Allocate pd_curves for this cal pier */
1153 chinfo[pier].pd_curves =
1154 kcalloc(AR5K_EEPROM_N_PD_CURVES,
1155 sizeof(struct ath5k_pdgain_info),
1156 GFP_KERNEL);
1157
1158 if (!chinfo[pier].pd_curves)
1159 return -ENOMEM;
1160
1161 /* Fill pd_curves */
1162 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1163
1164 u8 idx = pdgain_idx[pdg];
1165 struct ath5k_pdgain_info *pd =
1166 &chinfo[pier].pd_curves[idx];
1167
1168 /* One more point for the highest power
1169 * curve (lowest gain) */
1170 if (pdg == ee->ee_pd_gains[mode] - 1)
1171 pd->pd_points = AR5K_EEPROM_N_PD_POINTS;
1172 else
1173 pd->pd_points = AR5K_EEPROM_N_PD_POINTS - 1;
1174
1175 /* Allocate pd points for this curve */
1176 pd->pd_step = kcalloc(pd->pd_points,
1177 sizeof(u8), GFP_KERNEL);
1178
1179 if (!pd->pd_step)
1180 return -ENOMEM;
1181
1182 pd->pd_pwr = kcalloc(pd->pd_points,
1183 sizeof(s16), GFP_KERNEL);
1184
1185 if (!pd->pd_pwr)
1186 return -ENOMEM;
1187
1188 /* Fill raw dataset
1189 * convert all pwr levels to
1190 * quarter dB for RF5112 combatibility */
1191 pd->pd_step[0] = pcinfo->pddac_i[pdg];
1192 pd->pd_pwr[0] = 4 * pcinfo->pwr_i[pdg];
1193
1194 for (point = 1; point < pd->pd_points; point++) {
1195
1196 pd->pd_pwr[point] = pd->pd_pwr[point - 1] +
1197 2 * pcinfo->pwr[pdg][point - 1];
1198
1199 pd->pd_step[point] = pd->pd_step[point - 1] +
1200 pcinfo->pddac[pdg][point - 1];
1201
1202 }
1203
1204 /* Highest gain curve -> min power */
1205 if (pdg == 0)
1206 chinfo[pier].min_pwr = pd->pd_pwr[0];
1207
1208 /* Lowest gain curve -> max power */
1209 if (pdg == ee->ee_pd_gains[mode] - 1)
1210 chinfo[pier].max_pwr =
1211 pd->pd_pwr[pd->pd_points - 1];
1212 }
1213 }
1214
1215 return 0;
1216}
1217
1218/* Parse EEPROM data */
1048643e
FF		 1219static int
1220ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
1221{
1222 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
8e218fb2
NK		 1223 struct ath5k_chan_pcal_info_rf2413 *pcinfo;
1224 struct ath5k_chan_pcal_info *chinfo;
1225 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1048643e 1226 u32 offset;
fda9b7af 1227 int idx, i;
1048643e
FF		 1228 u16 val;
1229 u8 pd_gains = 0;
1230
8e218fb2
NK		 1231 /* Count how many curves we have and
1232 * identify them (which one of the 4
1233 * available curves we have on each count).
1234 * Curves are stored from higher to
1235 * lower gain so we go backwards */
1236 for (idx = AR5K_EEPROM_N_PD_CURVES - 1; idx >= 0; idx--) {
1237 /* ee_x_gain[mode] is x gain mask */
1238 if ((ee->ee_x_gain[mode] >> idx) & 0x1)
1239 pdgain_idx[pd_gains++] = idx;
1240
1241 }
1048643e
FF		 1242 ee->ee_pd_gains[mode] = pd_gains;
1243
8e218fb2
NK		 1244 if (pd_gains == 0)
1245 return -EINVAL;
1246
1048643e
FF		 1247 offset = ath5k_cal_data_offset_2413(ee, mode);
1248 switch (mode) {
1249 case AR5K_EEPROM_MODE_11A:
1250 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
1251 return 0;
1252
1253 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1254 offset += AR5K_EEPROM_N_5GHZ_CHAN / 2;
8e218fb2 1255 chinfo = ee->ee_pwr_cal_a;
1048643e
FF		 1256 break;
1257 case AR5K_EEPROM_MODE_11B:
1258 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
1259 return 0;
c6e387a2 1260
1048643e
FF		 1261 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1262 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
8e218fb2 1263 chinfo = ee->ee_pwr_cal_b;
1048643e
FF		 1264 break;
1265 case AR5K_EEPROM_MODE_11G:
1266 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
1267 return 0;
1268
1269 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1270 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
8e218fb2 1271 chinfo = ee->ee_pwr_cal_g;
1048643e
FF		 1272 break;
1273 default:
1274 return -EINVAL;
1275 }
1276
1048643e 1277 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
8e218fb2 1278 pcinfo = &chinfo[i].rf2413_info;
1048643e
FF		 1279
1280 /*
1281 * Read pwr_i, pddac_i and the first
1282 * 2 pd points (pwr, pddac)
1283 */
c6e387a2 1284 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1285 pcinfo->pwr_i[0] = val & 0x1f;
1286 pcinfo->pddac_i[0] = (val >> 5) & 0x7f;
1287 pcinfo->pwr[0][0] = (val >> 12) & 0xf;
c6e387a2 1288
1048643e 1289 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1290 pcinfo->pddac[0][0] = val & 0x3f;
1291 pcinfo->pwr[0][1] = (val >> 6) & 0xf;
1292 pcinfo->pddac[0][1] = (val >> 10) & 0x3f;
1048643e
FF		 1293
1294 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1295 pcinfo->pwr[0][2] = val & 0xf;
1296 pcinfo->pddac[0][2] = (val >> 4) & 0x3f;
1048643e 1297
8e218fb2
NK		 1298 pcinfo->pwr[0][3] = 0;
1299 pcinfo->pddac[0][3] = 0;
1048643e
FF		 1300
1301 if (pd_gains > 1) {
1302 /*
1303 * Pd gain 0 is not the last pd gain
1304 * so it only has 2 pd points.
25985edc 1305 * Continue with pd gain 1.
1048643e 1306 */
8e218fb2 1307 pcinfo->pwr_i[1] = (val >> 10) & 0x1f;
1048643e 1308
8e218fb2 1309 pcinfo->pddac_i[1] = (val >> 15) & 0x1;
c6e387a2 1310 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1311 pcinfo->pddac_i[1] |= (val & 0x3F) << 1;
1048643e 1312
8e218fb2
NK		 1313 pcinfo->pwr[1][0] = (val >> 6) & 0xf;
1314 pcinfo->pddac[1][0] = (val >> 10) & 0x3f;
1048643e
FF		 1315
1316 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1317 pcinfo->pwr[1][1] = val & 0xf;
1318 pcinfo->pddac[1][1] = (val >> 4) & 0x3f;
1319 pcinfo->pwr[1][2] = (val >> 10) & 0xf;
1320
1321 pcinfo->pddac[1][2] = (val >> 14) & 0x3;
1048643e 1322 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1323 pcinfo->pddac[1][2] |= (val & 0xF) << 2;
1048643e 1324
8e218fb2
NK		 1325 pcinfo->pwr[1][3] = 0;
1326 pcinfo->pddac[1][3] = 0;
1048643e
FF		 1327 } else if (pd_gains == 1) {
1328 /*
1329 * Pd gain 0 is the last one so
1330 * read the extra point.
1331 */
8e218fb2 1332 pcinfo->pwr[0][3] = (val >> 10) & 0xf;
1048643e 1333
8e218fb2 1334 pcinfo->pddac[0][3] = (val >> 14) & 0x3;
1048643e 1335 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1336 pcinfo->pddac[0][3] |= (val & 0xF) << 2;
1048643e
FF		 1337 }
1338
1339 /*
1340 * Proceed with the other pd_gains
1341 * as above.
1342 */
1343 if (pd_gains > 2) {
8e218fb2
NK		 1344 pcinfo->pwr_i[2] = (val >> 4) & 0x1f;
1345 pcinfo->pddac_i[2] = (val >> 9) & 0x7f;
1048643e
FF		 1346
1347 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1348 pcinfo->pwr[2][0] = (val >> 0) & 0xf;
1349 pcinfo->pddac[2][0] = (val >> 4) & 0x3f;
1350 pcinfo->pwr[2][1] = (val >> 10) & 0xf;
1351
1352 pcinfo->pddac[2][1] = (val >> 14) & 0x3;
1048643e 1353 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1354 pcinfo->pddac[2][1] |= (val & 0xF) << 2;
1048643e 1355
8e218fb2
NK		 1356 pcinfo->pwr[2][2] = (val >> 4) & 0xf;
1357 pcinfo->pddac[2][2] = (val >> 8) & 0x3f;
1048643e 1358
8e218fb2
NK		 1359 pcinfo->pwr[2][3] = 0;
1360 pcinfo->pddac[2][3] = 0;
1048643e 1361 } else if (pd_gains == 2) {
8e218fb2
NK		 1362 pcinfo->pwr[1][3] = (val >> 4) & 0xf;
1363 pcinfo->pddac[1][3] = (val >> 8) & 0x3f;
1048643e
FF		 1364 }
1365
1366 if (pd_gains > 3) {
8e218fb2 1367 pcinfo->pwr_i[3] = (val >> 14) & 0x3;
1048643e 1368 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1369 pcinfo->pwr_i[3] |= ((val >> 0) & 0x7) << 2;
1048643e 1370
8e218fb2
NK		 1371 pcinfo->pddac_i[3] = (val >> 3) & 0x7f;
1372 pcinfo->pwr[3][0] = (val >> 10) & 0xf;
1373 pcinfo->pddac[3][0] = (val >> 14) & 0x3;
1048643e
FF		 1374
1375 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1376 pcinfo->pddac[3][0] |= (val & 0xF) << 2;
1377 pcinfo->pwr[3][1] = (val >> 4) & 0xf;
1378 pcinfo->pddac[3][1] = (val >> 8) & 0x3f;
1379
1380 pcinfo->pwr[3][2] = (val >> 14) & 0x3;
1048643e 1381 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1382 pcinfo->pwr[3][2] |= ((val >> 0) & 0x3) << 2;
1048643e 1383
8e218fb2
NK		 1384 pcinfo->pddac[3][2] = (val >> 2) & 0x3f;
1385 pcinfo->pwr[3][3] = (val >> 8) & 0xf;
1048643e 1386
8e218fb2 1387 pcinfo->pddac[3][3] = (val >> 12) & 0xF;
1048643e 1388 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1389 pcinfo->pddac[3][3] |= ((val >> 0) & 0x3) << 4;
1048643e 1390 } else if (pd_gains == 3) {
8e218fb2 1391 pcinfo->pwr[2][3] = (val >> 14) & 0x3;
1048643e 1392 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1393 pcinfo->pwr[2][3] |= ((val >> 0) & 0x3) << 2;
1048643e 1394
8e218fb2 1395 pcinfo->pddac[2][3] = (val >> 2) & 0x3f;
c6e387a2
NK		 1396 }
1397 }
1398
8e218fb2 1399 return ath5k_eeprom_convert_pcal_info_2413(ah, mode, chinfo);
1048643e
FF		 1400}
1401
8e218fb2 1402
1048643e
FF		 1403/*
1404 * Read per rate target power (this is the maximum tx power
1405 * supported by the card). This info is used when setting
1406 * tx power, no matter the channel.
1407 *
1408 * This also works for v5 EEPROMs.
1409 */
8e218fb2
NK		 1410static int
1411ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
1048643e
FF		 1412{
1413 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1414 struct ath5k_rate_pcal_info *rate_pcal_info;
8e218fb2 1415 u8 *rate_target_pwr_num;
1048643e
FF		 1416 u32 offset;
1417 u16 val;
fda9b7af 1418 int i;
1048643e
FF		 1419
1420 offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1);
1421 rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
1422 switch (mode) {
1423 case AR5K_EEPROM_MODE_11A:
1424 offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version);
1425 rate_pcal_info = ee->ee_rate_tpwr_a;
1426 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_CHAN;
1427 break;
1428 case AR5K_EEPROM_MODE_11B:
1429 offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version);
1430 rate_pcal_info = ee->ee_rate_tpwr_b;
1431 ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */
1432 break;
1433 case AR5K_EEPROM_MODE_11G:
1434 offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version);
1435 rate_pcal_info = ee->ee_rate_tpwr_g;
1436 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN;
1437 break;
1438 default:
1439 return -EINVAL;
1440 }
1441
1442 /* Different freq mask for older eeproms (<= v3.2) */
1443 if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) {
1444 for (i = 0; i < (*rate_target_pwr_num); i++) {
1445 AR5K_EEPROM_READ(offset++, val);
1446 rate_pcal_info[i].freq =
1447 ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode);
1448
1449 rate_pcal_info[i].target_power_6to24 = ((val >> 3) & 0x3f);
1450 rate_pcal_info[i].target_power_36 = (val << 3) & 0x3f;
1451
1452 AR5K_EEPROM_READ(offset++, val);
1453
1454 if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1455 val == 0) {
1456 (*rate_target_pwr_num) = i;
1457 break;
1458 }
1459
1460 rate_pcal_info[i].target_power_36 |= ((val >> 13) & 0x7);
1461 rate_pcal_info[i].target_power_48 = ((val >> 7) & 0x3f);
1462 rate_pcal_info[i].target_power_54 = ((val >> 1) & 0x3f);
1463 }
1464 } else {
1465 for (i = 0; i < (*rate_target_pwr_num); i++) {
1466 AR5K_EEPROM_READ(offset++, val);
1467 rate_pcal_info[i].freq =
1468 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
1469
1470 rate_pcal_info[i].target_power_6to24 = ((val >> 2) & 0x3f);
1471 rate_pcal_info[i].target_power_36 = (val << 4) & 0x3f;
1472
1473 AR5K_EEPROM_READ(offset++, val);
1474
1475 if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1476 val == 0) {
1477 (*rate_target_pwr_num) = i;
1478 break;
1479 }
1480
1481 rate_pcal_info[i].target_power_36 |= (val >> 12) & 0xf;
1482 rate_pcal_info[i].target_power_48 = ((val >> 6) & 0x3f);
1483 rate_pcal_info[i].target_power_54 = (val & 0x3f);
1484 }
1485 }
1486
1487 return 0;
1488}
1489
9320b5c4 1490
0ea9c00c
NK		 1491/*
1492 * Read per channel calibration info from EEPROM
1493 *
1494 * This info is used to calibrate the baseband power table. Imagine
1495 * that for each channel there is a power curve that's hw specific
1496 * (depends on amplifier etc) and we try to "correct" this curve using
bf48aabb 1497 * offsets we pass on to phy chip (baseband -> before amplifier) so that
0ea9c00c
NK		 1498 * it can use accurate power values when setting tx power (takes amplifier's
1499 * performance on each channel into account).
1500 *
1501 * EEPROM provides us with the offsets for some pre-calibrated channels
1502 * and we have to interpolate to create the full table for these channels and
1503 * also the table for any channel.
1504 */
1048643e
FF		 1505static int
1506ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah)
1507{
1508 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1509 int (*read_pcal)(struct ath5k_hw *hw, int mode);
1510 int mode;
1511 int err;
1512
1513 if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) &&
1514 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1))
1515 read_pcal = ath5k_eeprom_read_pcal_info_5112;
1516 else if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0) &&
1517 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2))
1518 read_pcal = ath5k_eeprom_read_pcal_info_2413;
1519 else
1520 read_pcal = ath5k_eeprom_read_pcal_info_5111;
1521
8e218fb2
NK		 1522
1523 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G;
1524 mode++) {
1048643e
FF		 1525 err = read_pcal(ah, mode);
1526 if (err)
1527 return err;
1528
1529 err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode);
1530 if (err < 0)
1531 return err;
1532 }
1533
1534 return 0;
1535}
1536
8e218fb2
NK		 1537static int
1538ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
1539{
1540 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1541 struct ath5k_chan_pcal_info *chinfo;
1542 u8 pier, pdg;
1543
1544 switch (mode) {
1545 case AR5K_EEPROM_MODE_11A:
1546 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
1547 return 0;
1548 chinfo = ee->ee_pwr_cal_a;
1549 break;
1550 case AR5K_EEPROM_MODE_11B:
1551 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
1552 return 0;
1553 chinfo = ee->ee_pwr_cal_b;
1554 break;
1555 case AR5K_EEPROM_MODE_11G:
1556 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
1557 return 0;
1558 chinfo = ee->ee_pwr_cal_g;
1559 break;
1560 default:
1561 return -EINVAL;
1562 }
1563
1564 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1565 if (!chinfo[pier].pd_curves)
1566 continue;
1567
1568 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1569 struct ath5k_pdgain_info *pd =
1570 &chinfo[pier].pd_curves[pdg];
1571
1572 if (pd != NULL) {
1573 kfree(pd->pd_step);
1574 kfree(pd->pd_pwr);
1575 }
1576 }
1577
1578 kfree(chinfo[pier].pd_curves);
1579 }
1580
1581 return 0;
1582}
1583
0ea9c00c 1584/* Read conformance test limits used for regulatory control */
1048643e
FF		 1585static int
1586ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
1587{
1588 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1589 struct ath5k_edge_power *rep;
1590 unsigned int fmask, pmask;
1591 unsigned int ctl_mode;
fda9b7af 1592 int i, j;
1048643e
FF		 1593 u32 offset;
1594 u16 val;
1595
1596 pmask = AR5K_EEPROM_POWER_M;
1597 fmask = AR5K_EEPROM_FREQ_M(ee->ee_version);
1598 offset = AR5K_EEPROM_CTL(ee->ee_version);
1599 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version);
1600 for (i = 0; i < ee->ee_ctls; i += 2) {
1601 AR5K_EEPROM_READ(offset++, val);
1602 ee->ee_ctl[i] = (val >> 8) & 0xff;
1603 ee->ee_ctl[i + 1] = val & 0xff;
1604 }
1605
1606 offset = AR5K_EEPROM_GROUP8_OFFSET;
1607 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0)
1608 offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) -
1609 AR5K_EEPROM_GROUP5_OFFSET;
1610 else
1611 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version);
1612
1613 rep = ee->ee_ctl_pwr;
1614 for(i = 0; i < ee->ee_ctls; i++) {
1615 switch(ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
1616 case AR5K_CTL_11A:
1617 case AR5K_CTL_TURBO:
1618 ctl_mode = AR5K_EEPROM_MODE_11A;
1619 break;
1620 default:
1621 ctl_mode = AR5K_EEPROM_MODE_11G;
1622 break;
1623 }
1624 if (ee->ee_ctl[i] == 0) {
1625 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3)
1626 offset += 8;
1627 else
1628 offset += 7;
1629 rep += AR5K_EEPROM_N_EDGES;
1630 continue;
1631 }
1632 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
1633 for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1634 AR5K_EEPROM_READ(offset++, val);
1635 rep[j].freq = (val >> 8) & fmask;
1636 rep[j + 1].freq = val & fmask;
1637 }
1638 for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1639 AR5K_EEPROM_READ(offset++, val);
1640 rep[j].edge = (val >> 8) & pmask;
1641 rep[j].flag = (val >> 14) & 1;
1642 rep[j + 1].edge = val & pmask;
1643 rep[j + 1].flag = (val >> 6) & 1;
1644 }
1645 } else {
1646 AR5K_EEPROM_READ(offset++, val);
1647 rep[0].freq = (val >> 9) & fmask;
1648 rep[1].freq = (val >> 2) & fmask;
1649 rep[2].freq = (val << 5) & fmask;
1650
1651 AR5K_EEPROM_READ(offset++, val);
1652 rep[2].freq |= (val >> 11) & 0x1f;
1653 rep[3].freq = (val >> 4) & fmask;
1654 rep[4].freq = (val << 3) & fmask;
1655
1656 AR5K_EEPROM_READ(offset++, val);
1657 rep[4].freq |= (val >> 13) & 0x7;
1658 rep[5].freq = (val >> 6) & fmask;
1659 rep[6].freq = (val << 1) & fmask;
1660
1661 AR5K_EEPROM_READ(offset++, val);
1662 rep[6].freq |= (val >> 15) & 0x1;
1663 rep[7].freq = (val >> 8) & fmask;
1664
1665 rep[0].edge = (val >> 2) & pmask;
1666 rep[1].edge = (val << 4) & pmask;
1667
1668 AR5K_EEPROM_READ(offset++, val);
1669 rep[1].edge |= (val >> 12) & 0xf;
1670 rep[2].edge = (val >> 6) & pmask;
1671 rep[3].edge = val & pmask;
1672
1673 AR5K_EEPROM_READ(offset++, val);
1674 rep[4].edge = (val >> 10) & pmask;
1675 rep[5].edge = (val >> 4) & pmask;
1676 rep[6].edge = (val << 2) & pmask;
1677
1678 AR5K_EEPROM_READ(offset++, val);
1679 rep[6].edge |= (val >> 14) & 0x3;
1680 rep[7].edge = (val >> 8) & pmask;
1681 }
1682 for (j = 0; j < AR5K_EEPROM_N_EDGES; j++) {
1683 rep[j].freq = ath5k_eeprom_bin2freq(ee,
1684 rep[j].freq, ctl_mode);
1685 }
1686 rep += AR5K_EEPROM_N_EDGES;
1687 }
c6e387a2
NK		 1688
1689 return 0;
1690}
1691
cd417519
NK		 1692static int
1693ath5k_eeprom_read_spur_chans(struct ath5k_hw *ah)
1694{
1695 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1696 u32 offset;
1697 u16 val;
1698 int ret = 0, i;
1699
1700 offset = AR5K_EEPROM_CTL(ee->ee_version) +
1701 AR5K_EEPROM_N_CTLS(ee->ee_version);
1702
1703 if (ee->ee_version < AR5K_EEPROM_VERSION_5_3) {
1704 /* No spur info for 5GHz */
1705 ee->ee_spur_chans[0][0] = AR5K_EEPROM_NO_SPUR;
1706 /* 2 channels for 2GHz (2464/2420) */
1707 ee->ee_spur_chans[0][1] = AR5K_EEPROM_5413_SPUR_CHAN_1;
1708 ee->ee_spur_chans[1][1] = AR5K_EEPROM_5413_SPUR_CHAN_2;
1709 ee->ee_spur_chans[2][1] = AR5K_EEPROM_NO_SPUR;
1710 } else if (ee->ee_version >= AR5K_EEPROM_VERSION_5_3) {
1711 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1712 AR5K_EEPROM_READ(offset, val);
1713 ee->ee_spur_chans[i][0] = val;
1714 AR5K_EEPROM_READ(offset + AR5K_EEPROM_N_SPUR_CHANS,
1715 val);
1716 ee->ee_spur_chans[i][1] = val;
1717 offset++;
1718 }
1719 }
1720
1721 return ret;
1722}
1048643e 1723
9320b5c4
NK		 1724/*
1725 * Read the MAC address from eeprom
1726 */
1727int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
1728{
1729 u8 mac_d[ETH_ALEN] = {};
1730 u32 total, offset;
1731 u16 data;
fda9b7af 1732 int octet;
9320b5c4 1733
fda9b7af 1734 AR5K_EEPROM_READ(0x20, data);
9320b5c4
NK		 1735
1736 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
fda9b7af 1737 AR5K_EEPROM_READ(offset, data);
9320b5c4
NK		 1738
1739 total += data;
1740 mac_d[octet + 1] = data & 0xff;
1741 mac_d[octet] = data >> 8;
1742 octet += 2;
1743 }
1744
1745 if (!total || total == 3 * 0xffff)
1746 return -EINVAL;
1747
1748 memcpy(mac, mac_d, ETH_ALEN);
1749
1750 return 0;
1751}
1752
1753
1754/***********************\
1755* Init/Detach functions *
1756\***********************/
1757
1048643e 1758/*
cd417519 1759 * Initialize eeprom data structure
1048643e
FF		 1760 */
1761int
1762ath5k_eeprom_init(struct ath5k_hw *ah)
1763{
1764 int err;
1765
1766 err = ath5k_eeprom_init_header(ah);
1767 if (err < 0)
1768 return err;
1769
1770 err = ath5k_eeprom_init_modes(ah);
1771 if (err < 0)
1772 return err;
1773
1774 err = ath5k_eeprom_read_pcal_info(ah);
1775 if (err < 0)
1776 return err;
1777
1778 err = ath5k_eeprom_read_ctl_info(ah);
1779 if (err < 0)
1780 return err;
1781
cd417519
NK		 1782 err = ath5k_eeprom_read_spur_chans(ah);
1783 if (err < 0)
1784 return err;
1785
1048643e
FF		 1786 return 0;
1787}
e8f055f0 1788
9320b5c4
NK		 1789void
1790ath5k_eeprom_detach(struct ath5k_hw *ah)
c6e387a2 1791{
9320b5c4 1792 u8 mode;
8d6c39ef 1793
9320b5c4
NK		 1794 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
1795 ath5k_eeprom_free_pcal_info(ah, mode);
c6e387a2 1796}
0207c0c5
BR		 1797
1798int
1799ath5k_eeprom_mode_from_channel(struct ieee80211_channel *channel)
1800{
1801 switch (channel->hw_value & CHANNEL_MODES) {
1802 case CHANNEL_A:
1803 case CHANNEL_XR:
1804 return AR5K_EEPROM_MODE_11A;
1805 case CHANNEL_G:
1806 return AR5K_EEPROM_MODE_11G;
1807 case CHANNEL_B:
1808 return AR5K_EEPROM_MODE_11B;
1809 default:
1810 return -1;
1811 }
1812}
kernel source for telekom puls (alcatel/mediatek)