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vmxnet3: remove device counter
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / vmxnet3 / vmxnet3_drv.c
CommitLineData
d1a890fa
SB		 1/*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
4 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
23 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
24 *
25 */
26
9d9779e7 27#include <linux/module.h>
b038b040
SR		 28#include <net/ip6_checksum.h>
29
d1a890fa
SB		 30#include "vmxnet3_int.h"
31
32char vmxnet3_driver_name[] = "vmxnet3";
33#define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
34
d1a890fa
SB		 35/*
36 * PCI Device ID Table
37 * Last entry must be all 0s
38 */
a3aa1884 39static DEFINE_PCI_DEVICE_TABLE(vmxnet3_pciid_table) = {
d1a890fa
SB		 40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
41 {0}
42};
43
44MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
45
09c5088e
SB		 46static int enable_mq = 1;
47static int irq_share_mode;
d1a890fa 48
f9f25026
SB		 49static void
50vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
51
d1a890fa
SB		 52/*
53 * Enable/Disable the given intr
54 */
55static void
56vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
57{
58 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
59}
60
61
62static void
63vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
64{
65 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
66}
67
68
69/*
70 * Enable/Disable all intrs used by the device
71 */
72static void
73vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
74{
75 int i;
76
77 for (i = 0; i < adapter->intr.num_intrs; i++)
78 vmxnet3_enable_intr(adapter, i);
6929fe8a
RZ		 79 adapter->shared->devRead.intrConf.intrCtrl &=
80 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 81}
82
83
84static void
85vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
86{
87 int i;
88
6929fe8a
RZ		 89 adapter->shared->devRead.intrConf.intrCtrl |=
90 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 91 for (i = 0; i < adapter->intr.num_intrs; i++)
92 vmxnet3_disable_intr(adapter, i);
93}
94
95
96static void
97vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
98{
99 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
100}
101
102
103static bool
104vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
105{
09c5088e 106 return tq->stopped;
d1a890fa
SB		 107}
108
109
110static void
111vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
112{
113 tq->stopped = false;
09c5088e 114 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
d1a890fa
SB		 115}
116
117
118static void
119vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
120{
121 tq->stopped = false;
09c5088e 122 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
d1a890fa
SB		 123}
124
125
126static void
127vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
128{
129 tq->stopped = true;
130 tq->num_stop++;
09c5088e 131 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
d1a890fa
SB		 132}
133
134
135/*
136 * Check the link state. This may start or stop the tx queue.
137 */
138static void
4a1745fc 139vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
d1a890fa
SB		 140{
141 u32 ret;
09c5088e 142 int i;
83d0feff 143 unsigned long flags;
d1a890fa 144
83d0feff 145 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 146 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
147 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
83d0feff
SB		 148 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
149
d1a890fa
SB		 150 adapter->link_speed = ret >> 16;
151 if (ret & 1) { /* Link is up. */
204a6e65
SH		 152 netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n",
153 adapter->link_speed);
d1a890fa
SB		 154 if (!netif_carrier_ok(adapter->netdev))
155 netif_carrier_on(adapter->netdev);
156
09c5088e
SB		 157 if (affectTxQueue) {
158 for (i = 0; i < adapter->num_tx_queues; i++)
159 vmxnet3_tq_start(&adapter->tx_queue[i],
160 adapter);
161 }
d1a890fa 162 } else {
204a6e65 163 netdev_info(adapter->netdev, "NIC Link is Down\n");
d1a890fa
SB		 164 if (netif_carrier_ok(adapter->netdev))
165 netif_carrier_off(adapter->netdev);
166
09c5088e
SB		 167 if (affectTxQueue) {
168 for (i = 0; i < adapter->num_tx_queues; i++)
169 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
170 }
d1a890fa
SB		 171 }
172}
173
d1a890fa
SB		 174static void
175vmxnet3_process_events(struct vmxnet3_adapter *adapter)
176{
09c5088e 177 int i;
e328d410 178 unsigned long flags;
115924b6 179 u32 events = le32_to_cpu(adapter->shared->ecr);
d1a890fa
SB		 180 if (!events)
181 return;
182
183 vmxnet3_ack_events(adapter, events);
184
185 /* Check if link state has changed */
186 if (events & VMXNET3_ECR_LINK)
4a1745fc 187 vmxnet3_check_link(adapter, true);
d1a890fa
SB		 188
189 /* Check if there is an error on xmit/recv queues */
190 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
e328d410 191 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 192 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
193 VMXNET3_CMD_GET_QUEUE_STATUS);
e328d410 194 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa 195
09c5088e
SB		 196 for (i = 0; i < adapter->num_tx_queues; i++)
197 if (adapter->tqd_start[i].status.stopped)
198 dev_err(&adapter->netdev->dev,
199 "%s: tq[%d] error 0x%x\n",
200 adapter->netdev->name, i, le32_to_cpu(
201 adapter->tqd_start[i].status.error));
202 for (i = 0; i < adapter->num_rx_queues; i++)
203 if (adapter->rqd_start[i].status.stopped)
204 dev_err(&adapter->netdev->dev,
205 "%s: rq[%d] error 0x%x\n",
206 adapter->netdev->name, i,
207 adapter->rqd_start[i].status.error);
d1a890fa
SB		 208
209 schedule_work(&adapter->work);
210 }
211}
212
115924b6
SB		 213#ifdef __BIG_ENDIAN_BITFIELD
214/*
215 * The device expects the bitfields in shared structures to be written in
216 * little endian. When CPU is big endian, the following routines are used to
217 * correctly read and write into ABI.
218 * The general technique used here is : double word bitfields are defined in
219 * opposite order for big endian architecture. Then before reading them in
220 * driver the complete double word is translated using le32_to_cpu. Similarly
221 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
222 * double words into required format.
223 * In order to avoid touching bits in shared structure more than once, temporary
224 * descriptors are used. These are passed as srcDesc to following functions.
225 */
226static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
227 struct Vmxnet3_RxDesc *dstDesc)
228{
229 u32 *src = (u32 *)srcDesc + 2;
230 u32 *dst = (u32 *)dstDesc + 2;
231 dstDesc->addr = le64_to_cpu(srcDesc->addr);
232 *dst = le32_to_cpu(*src);
233 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
234}
235
236static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
237 struct Vmxnet3_TxDesc *dstDesc)
238{
239 int i;
240 u32 *src = (u32 *)(srcDesc + 1);
241 u32 *dst = (u32 *)(dstDesc + 1);
242
243 /* Working backwards so that the gen bit is set at the end. */
244 for (i = 2; i > 0; i--) {
245 src--;
246 dst--;
247 *dst = cpu_to_le32(*src);
248 }
249}
250
251
252static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
253 struct Vmxnet3_RxCompDesc *dstDesc)
254{
255 int i = 0;
256 u32 *src = (u32 *)srcDesc;
257 u32 *dst = (u32 *)dstDesc;
258 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
259 *dst = le32_to_cpu(*src);
260 src++;
261 dst++;
262 }
263}
264
265
266/* Used to read bitfield values from double words. */
267static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
268{
269 u32 temp = le32_to_cpu(*bitfield);
270 u32 mask = ((1 << size) - 1) << pos;
271 temp &= mask;
272 temp >>= pos;
273 return temp;
274}
275
276
277
278#endif /* __BIG_ENDIAN_BITFIELD */
279
280#ifdef __BIG_ENDIAN_BITFIELD
281
282# define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
283 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
284 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
285# define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
286 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
287 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
288# define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
289 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
290 VMXNET3_TCD_GEN_SIZE)
291# define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
292 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
293# define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
294 (dstrcd) = (tmp); \
295 vmxnet3_RxCompToCPU((rcd), (tmp)); \
296 } while (0)
297# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
298 (dstrxd) = (tmp); \
299 vmxnet3_RxDescToCPU((rxd), (tmp)); \
300 } while (0)
301
302#else
303
304# define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
305# define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
306# define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
307# define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
308# define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
309# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
310
311#endif /* __BIG_ENDIAN_BITFIELD */
312
d1a890fa
SB		 313
314static void
315vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
316 struct pci_dev *pdev)
317{
318 if (tbi->map_type == VMXNET3_MAP_SINGLE)
319 pci_unmap_single(pdev, tbi->dma_addr, tbi->len,
320 PCI_DMA_TODEVICE);
321 else if (tbi->map_type == VMXNET3_MAP_PAGE)
322 pci_unmap_page(pdev, tbi->dma_addr, tbi->len,
323 PCI_DMA_TODEVICE);
324 else
325 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
326
327 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
328}
329
330
331static int
332vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
333 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
334{
335 struct sk_buff *skb;
336 int entries = 0;
337
338 /* no out of order completion */
339 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
115924b6 340 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
d1a890fa
SB		 341
342 skb = tq->buf_info[eop_idx].skb;
343 BUG_ON(skb == NULL);
344 tq->buf_info[eop_idx].skb = NULL;
345
346 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
347
348 while (tq->tx_ring.next2comp != eop_idx) {
349 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
350 pdev);
351
352 /* update next2comp w/o tx_lock. Since we are marking more,
353 * instead of less, tx ring entries avail, the worst case is
354 * that the tx routine incorrectly re-queues a pkt due to
355 * insufficient tx ring entries.
356 */
357 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
358 entries++;
359 }
360
361 dev_kfree_skb_any(skb);
362 return entries;
363}
364
365
366static int
367vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
368 struct vmxnet3_adapter *adapter)
369{
370 int completed = 0;
371 union Vmxnet3_GenericDesc *gdesc;
372
373 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
115924b6
SB		 374 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
375 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
376 &gdesc->tcd), tq, adapter->pdev,
377 adapter);
d1a890fa
SB		 378
379 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
380 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
381 }
382
383 if (completed) {
384 spin_lock(&tq->tx_lock);
385 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
386 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
387 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
388 netif_carrier_ok(adapter->netdev))) {
389 vmxnet3_tq_wake(tq, adapter);
390 }
391 spin_unlock(&tq->tx_lock);
392 }
393 return completed;
394}
395
396
397static void
398vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
399 struct vmxnet3_adapter *adapter)
400{
401 int i;
402
403 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
404 struct vmxnet3_tx_buf_info *tbi;
d1a890fa
SB		 405
406 tbi = tq->buf_info + tq->tx_ring.next2comp;
d1a890fa
SB		 407
408 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
409 if (tbi->skb) {
410 dev_kfree_skb_any(tbi->skb);
411 tbi->skb = NULL;
412 }
413 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
414 }
415
416 /* sanity check, verify all buffers are indeed unmapped and freed */
417 for (i = 0; i < tq->tx_ring.size; i++) {
418 BUG_ON(tq->buf_info[i].skb != NULL ||
419 tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
420 }
421
422 tq->tx_ring.gen = VMXNET3_INIT_GEN;
423 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
424
425 tq->comp_ring.gen = VMXNET3_INIT_GEN;
426 tq->comp_ring.next2proc = 0;
427}
428
429
09c5088e 430static void
d1a890fa
SB		 431vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
432 struct vmxnet3_adapter *adapter)
433{
434 if (tq->tx_ring.base) {
435 pci_free_consistent(adapter->pdev, tq->tx_ring.size *
436 sizeof(struct Vmxnet3_TxDesc),
437 tq->tx_ring.base, tq->tx_ring.basePA);
438 tq->tx_ring.base = NULL;
439 }
440 if (tq->data_ring.base) {
441 pci_free_consistent(adapter->pdev, tq->data_ring.size *
442 sizeof(struct Vmxnet3_TxDataDesc),
443 tq->data_ring.base, tq->data_ring.basePA);
444 tq->data_ring.base = NULL;
445 }
446 if (tq->comp_ring.base) {
447 pci_free_consistent(adapter->pdev, tq->comp_ring.size *
448 sizeof(struct Vmxnet3_TxCompDesc),
449 tq->comp_ring.base, tq->comp_ring.basePA);
450 tq->comp_ring.base = NULL;
451 }
452 kfree(tq->buf_info);
453 tq->buf_info = NULL;
454}
455
456
09c5088e
SB		 457/* Destroy all tx queues */
458void
459vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
460{
461 int i;
462
463 for (i = 0; i < adapter->num_tx_queues; i++)
464 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
465}
466
467
d1a890fa
SB		 468static void
469vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
470 struct vmxnet3_adapter *adapter)
471{
472 int i;
473
474 /* reset the tx ring contents to 0 and reset the tx ring states */
475 memset(tq->tx_ring.base, 0, tq->tx_ring.size *
476 sizeof(struct Vmxnet3_TxDesc));
477 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
478 tq->tx_ring.gen = VMXNET3_INIT_GEN;
479
480 memset(tq->data_ring.base, 0, tq->data_ring.size *
481 sizeof(struct Vmxnet3_TxDataDesc));
482
483 /* reset the tx comp ring contents to 0 and reset comp ring states */
484 memset(tq->comp_ring.base, 0, tq->comp_ring.size *
485 sizeof(struct Vmxnet3_TxCompDesc));
486 tq->comp_ring.next2proc = 0;
487 tq->comp_ring.gen = VMXNET3_INIT_GEN;
488
489 /* reset the bookkeeping data */
490 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
491 for (i = 0; i < tq->tx_ring.size; i++)
492 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
493
494 /* stats are not reset */
495}
496
497
498static int
499vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
500 struct vmxnet3_adapter *adapter)
501{
502 BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
503 tq->comp_ring.base || tq->buf_info);
504
505 tq->tx_ring.base = pci_alloc_consistent(adapter->pdev, tq->tx_ring.size
506 * sizeof(struct Vmxnet3_TxDesc),
507 &tq->tx_ring.basePA);
508 if (!tq->tx_ring.base) {
204a6e65 509 netdev_err(adapter->netdev, "failed to allocate tx ring\n");
d1a890fa
SB		 510 goto err;
511 }
512
513 tq->data_ring.base = pci_alloc_consistent(adapter->pdev,
514 tq->data_ring.size *
515 sizeof(struct Vmxnet3_TxDataDesc),
516 &tq->data_ring.basePA);
517 if (!tq->data_ring.base) {
204a6e65 518 netdev_err(adapter->netdev, "failed to allocate data ring\n");
d1a890fa
SB		 519 goto err;
520 }
521
522 tq->comp_ring.base = pci_alloc_consistent(adapter->pdev,
523 tq->comp_ring.size *
524 sizeof(struct Vmxnet3_TxCompDesc),
525 &tq->comp_ring.basePA);
526 if (!tq->comp_ring.base) {
204a6e65 527 netdev_err(adapter->netdev, "failed to allocate tx comp ring\n");
d1a890fa
SB		 528 goto err;
529 }
530
531 tq->buf_info = kcalloc(tq->tx_ring.size, sizeof(tq->buf_info[0]),
532 GFP_KERNEL);
e404decb 533 if (!tq->buf_info)
d1a890fa 534 goto err;
d1a890fa
SB		 535
536 return 0;
537
538err:
539 vmxnet3_tq_destroy(tq, adapter);
540 return -ENOMEM;
541}
542
09c5088e
SB		 543static void
544vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
545{
546 int i;
547
548 for (i = 0; i < adapter->num_tx_queues; i++)
549 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
550}
d1a890fa
SB		 551
552/*
553 * starting from ring->next2fill, allocate rx buffers for the given ring
554 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
555 * are allocated or allocation fails
556 */
557
558static int
559vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
560 int num_to_alloc, struct vmxnet3_adapter *adapter)
561{
562 int num_allocated = 0;
563 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
564 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
565 u32 val;
566
5318d809 567 while (num_allocated <= num_to_alloc) {
d1a890fa
SB		 568 struct vmxnet3_rx_buf_info *rbi;
569 union Vmxnet3_GenericDesc *gd;
570
571 rbi = rbi_base + ring->next2fill;
572 gd = ring->base + ring->next2fill;
573
574 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
575 if (rbi->skb == NULL) {
0d735f13
SH		 576 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev,
577 rbi->len,
578 GFP_KERNEL);
d1a890fa
SB		 579 if (unlikely(rbi->skb == NULL)) {
580 rq->stats.rx_buf_alloc_failure++;
581 break;
582 }
d1a890fa 583
d1a890fa
SB		 584 rbi->dma_addr = pci_map_single(adapter->pdev,
585 rbi->skb->data, rbi->len,
586 PCI_DMA_FROMDEVICE);
587 } else {
588 /* rx buffer skipped by the device */
589 }
590 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
591 } else {
592 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
593 rbi->len != PAGE_SIZE);
594
595 if (rbi->page == NULL) {
596 rbi->page = alloc_page(GFP_ATOMIC);
597 if (unlikely(rbi->page == NULL)) {
598 rq->stats.rx_buf_alloc_failure++;
599 break;
600 }
601 rbi->dma_addr = pci_map_page(adapter->pdev,
602 rbi->page, 0, PAGE_SIZE,
603 PCI_DMA_FROMDEVICE);
604 } else {
605 /* rx buffers skipped by the device */
606 }
607 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
608 }
609
610 BUG_ON(rbi->dma_addr == 0);
115924b6 611 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
5318d809 612 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
115924b6 613 | val | rbi->len);
d1a890fa 614
5318d809
SB		 615 /* Fill the last buffer but dont mark it ready, or else the
616 * device will think that the queue is full */
617 if (num_allocated == num_to_alloc)
618 break;
619
620 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
d1a890fa
SB		 621 num_allocated++;
622 vmxnet3_cmd_ring_adv_next2fill(ring);
623 }
d1a890fa 624
fdcd79b9 625 netdev_dbg(adapter->netdev,
69b9a712
SH		 626 "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n",
627 num_allocated, ring->next2fill, ring->next2comp);
d1a890fa
SB		 628
629 /* so that the device can distinguish a full ring and an empty ring */
630 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
631
632 return num_allocated;
633}
634
635
636static void
637vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
638 struct vmxnet3_rx_buf_info *rbi)
639{
640 struct skb_frag_struct *frag = skb_shinfo(skb)->frags +
641 skb_shinfo(skb)->nr_frags;
642
643 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
644
0e0634d2 645 __skb_frag_set_page(frag, rbi->page);
d1a890fa 646 frag->page_offset = 0;
9e903e08
ED		 647 skb_frag_size_set(frag, rcd->len);
648 skb->data_len += rcd->len;
5e6c355c 649 skb->truesize += PAGE_SIZE;
d1a890fa
SB		 650 skb_shinfo(skb)->nr_frags++;
651}
652
653
654static void
655vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
656 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
657 struct vmxnet3_adapter *adapter)
658{
659 u32 dw2, len;
660 unsigned long buf_offset;
661 int i;
662 union Vmxnet3_GenericDesc *gdesc;
663 struct vmxnet3_tx_buf_info *tbi = NULL;
664
665 BUG_ON(ctx->copy_size > skb_headlen(skb));
666
667 /* use the previous gen bit for the SOP desc */
668 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
669
670 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
671 gdesc = ctx->sop_txd; /* both loops below can be skipped */
672
673 /* no need to map the buffer if headers are copied */
674 if (ctx->copy_size) {
115924b6 675 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
d1a890fa 676 tq->tx_ring.next2fill *
115924b6
SB		 677 sizeof(struct Vmxnet3_TxDataDesc));
678 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
d1a890fa
SB		 679 ctx->sop_txd->dword[3] = 0;
680
681 tbi = tq->buf_info + tq->tx_ring.next2fill;
682 tbi->map_type = VMXNET3_MAP_NONE;
683
fdcd79b9 684 netdev_dbg(adapter->netdev,
f6965582 685 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
115924b6
SB		 686 tq->tx_ring.next2fill,
687 le64_to_cpu(ctx->sop_txd->txd.addr),
d1a890fa
SB		 688 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
689 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
690
691 /* use the right gen for non-SOP desc */
692 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
693 }
694
695 /* linear part can use multiple tx desc if it's big */
696 len = skb_headlen(skb) - ctx->copy_size;
697 buf_offset = ctx->copy_size;
698 while (len) {
699 u32 buf_size;
700
1f4b1612
BD		 701 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
702 buf_size = len;
703 dw2 |= len;
704 } else {
705 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
706 /* spec says that for TxDesc.len, 0 == 2^14 */
707 }
d1a890fa
SB		 708
709 tbi = tq->buf_info + tq->tx_ring.next2fill;
710 tbi->map_type = VMXNET3_MAP_SINGLE;
711 tbi->dma_addr = pci_map_single(adapter->pdev,
712 skb->data + buf_offset, buf_size,
713 PCI_DMA_TODEVICE);
714
1f4b1612 715 tbi->len = buf_size;
d1a890fa
SB		 716
717 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
718 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
719
115924b6 720 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
1f4b1612 721 gdesc->dword[2] = cpu_to_le32(dw2);
d1a890fa
SB		 722 gdesc->dword[3] = 0;
723
fdcd79b9 724 netdev_dbg(adapter->netdev,
f6965582 725 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
115924b6
SB		 726 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
727 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
d1a890fa
SB		 728 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
729 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
730
731 len -= buf_size;
732 buf_offset += buf_size;
733 }
734
735 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9e903e08 736 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
a4d7e485 737 u32 buf_size;
d1a890fa 738
a4d7e485
ED		 739 buf_offset = 0;
740 len = skb_frag_size(frag);
741 while (len) {
742 tbi = tq->buf_info + tq->tx_ring.next2fill;
743 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
744 buf_size = len;
745 dw2 |= len;
746 } else {
747 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
748 /* spec says that for TxDesc.len, 0 == 2^14 */
749 }
750 tbi->map_type = VMXNET3_MAP_PAGE;
751 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag,
752 buf_offset, buf_size,
753 DMA_TO_DEVICE);
d1a890fa 754
a4d7e485 755 tbi->len = buf_size;
d1a890fa 756
a4d7e485
ED		 757 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
758 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
d1a890fa 759
a4d7e485
ED		 760 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
761 gdesc->dword[2] = cpu_to_le32(dw2);
762 gdesc->dword[3] = 0;
d1a890fa 763
fdcd79b9 764 netdev_dbg(adapter->netdev,
a4d7e485
ED		 765 "txd[%u]: 0x%llu %u %u\n",
766 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
767 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
768 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
769 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
770
771 len -= buf_size;
772 buf_offset += buf_size;
773 }
d1a890fa
SB		 774 }
775
776 ctx->eop_txd = gdesc;
777
778 /* set the last buf_info for the pkt */
779 tbi->skb = skb;
780 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
781}
782
783
09c5088e
SB		 784/* Init all tx queues */
785static void
786vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
787{
788 int i;
789
790 for (i = 0; i < adapter->num_tx_queues; i++)
791 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
792}
793
794
d1a890fa
SB		 795/*
796 * parse and copy relevant protocol headers:
797 * For a tso pkt, relevant headers are L2/3/4 including options
798 * For a pkt requesting csum offloading, they are L2/3 and may include L4
799 * if it's a TCP/UDP pkt
800 *
801 * Returns:
802 * -1: error happens during parsing
803 * 0: protocol headers parsed, but too big to be copied
804 * 1: protocol headers parsed and copied
805 *
806 * Other effects:
807 * 1. related *ctx fields are updated.
808 * 2. ctx->copy_size is # of bytes copied
809 * 3. the portion copied is guaranteed to be in the linear part
810 *
811 */
812static int
813vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
814 struct vmxnet3_tx_ctx *ctx,
815 struct vmxnet3_adapter *adapter)
816{
817 struct Vmxnet3_TxDataDesc *tdd;
818
0d0b1672 819 if (ctx->mss) { /* TSO */
d1a890fa 820 ctx->eth_ip_hdr_size = skb_transport_offset(skb);
8bca5d1e 821 ctx->l4_hdr_size = tcp_hdrlen(skb);
d1a890fa
SB		 822 ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size;
823 } else {
d1a890fa 824 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 825 ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb);
d1a890fa
SB		 826
827 if (ctx->ipv4) {
8bca5d1e
ED		 828 const struct iphdr *iph = ip_hdr(skb);
829
39d4a96f 830 if (iph->protocol == IPPROTO_TCP)
8bca5d1e 831 ctx->l4_hdr_size = tcp_hdrlen(skb);
39d4a96f 832 else if (iph->protocol == IPPROTO_UDP)
f6a1ad42 833 ctx->l4_hdr_size = sizeof(struct udphdr);
39d4a96f 834 else
d1a890fa 835 ctx->l4_hdr_size = 0;
d1a890fa
SB		 836 } else {
837 /* for simplicity, don't copy L4 headers */
838 ctx->l4_hdr_size = 0;
839 }
b203262d
NH		 840 ctx->copy_size = min(ctx->eth_ip_hdr_size +
841 ctx->l4_hdr_size, skb->len);
d1a890fa
SB		 842 } else {
843 ctx->eth_ip_hdr_size = 0;
844 ctx->l4_hdr_size = 0;
845 /* copy as much as allowed */
846 ctx->copy_size = min((unsigned int)VMXNET3_HDR_COPY_SIZE
847 , skb_headlen(skb));
848 }
849
850 /* make sure headers are accessible directly */
851 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
852 goto err;
853 }
854
855 if (unlikely(ctx->copy_size > VMXNET3_HDR_COPY_SIZE)) {
856 tq->stats.oversized_hdr++;
857 ctx->copy_size = 0;
858 return 0;
859 }
860
861 tdd = tq->data_ring.base + tq->tx_ring.next2fill;
862
863 memcpy(tdd->data, skb->data, ctx->copy_size);
fdcd79b9 864 netdev_dbg(adapter->netdev,
f6965582 865 "copy %u bytes to dataRing[%u]\n",
d1a890fa
SB		 866 ctx->copy_size, tq->tx_ring.next2fill);
867 return 1;
868
869err:
870 return -1;
871}
872
873
874static void
875vmxnet3_prepare_tso(struct sk_buff *skb,
876 struct vmxnet3_tx_ctx *ctx)
877{
8bca5d1e
ED		 878 struct tcphdr *tcph = tcp_hdr(skb);
879
d1a890fa 880 if (ctx->ipv4) {
8bca5d1e
ED		 881 struct iphdr *iph = ip_hdr(skb);
882
d1a890fa
SB		 883 iph->check = 0;
884 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
885 IPPROTO_TCP, 0);
886 } else {
8bca5d1e
ED		 887 struct ipv6hdr *iph = ipv6_hdr(skb);
888
d1a890fa
SB		 889 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
890 IPPROTO_TCP, 0);
891 }
892}
893
a4d7e485
ED		 894static int txd_estimate(const struct sk_buff *skb)
895{
896 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
897 int i;
898
899 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
900 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
901
902 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag));
903 }
904 return count;
905}
d1a890fa
SB		 906
907/*
908 * Transmits a pkt thru a given tq
909 * Returns:
910 * NETDEV_TX_OK: descriptors are setup successfully
25985edc 911 * NETDEV_TX_OK: error occurred, the pkt is dropped
d1a890fa
SB		 912 * NETDEV_TX_BUSY: tx ring is full, queue is stopped
913 *
914 * Side-effects:
915 * 1. tx ring may be changed
916 * 2. tq stats may be updated accordingly
917 * 3. shared->txNumDeferred may be updated
918 */
919
920static int
921vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
922 struct vmxnet3_adapter *adapter, struct net_device *netdev)
923{
924 int ret;
925 u32 count;
926 unsigned long flags;
927 struct vmxnet3_tx_ctx ctx;
928 union Vmxnet3_GenericDesc *gdesc;
115924b6
SB		 929#ifdef __BIG_ENDIAN_BITFIELD
930 /* Use temporary descriptor to avoid touching bits multiple times */
931 union Vmxnet3_GenericDesc tempTxDesc;
932#endif
d1a890fa 933
a4d7e485 934 count = txd_estimate(skb);
d1a890fa 935
72e85c45 936 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
d1a890fa
SB		 937
938 ctx.mss = skb_shinfo(skb)->gso_size;
939 if (ctx.mss) {
940 if (skb_header_cloned(skb)) {
941 if (unlikely(pskb_expand_head(skb, 0, 0,
942 GFP_ATOMIC) != 0)) {
943 tq->stats.drop_tso++;
944 goto drop_pkt;
945 }
946 tq->stats.copy_skb_header++;
947 }
948 vmxnet3_prepare_tso(skb, &ctx);
949 } else {
950 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
951
952 /* non-tso pkts must not use more than
953 * VMXNET3_MAX_TXD_PER_PKT entries
954 */
955 if (skb_linearize(skb) != 0) {
956 tq->stats.drop_too_many_frags++;
957 goto drop_pkt;
958 }
959 tq->stats.linearized++;
960
961 /* recalculate the # of descriptors to use */
962 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
963 }
964 }
965
09c5088e
SB		 966 spin_lock_irqsave(&tq->tx_lock, flags);
967
968 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
969 tq->stats.tx_ring_full++;
fdcd79b9 970 netdev_dbg(adapter->netdev,
09c5088e
SB		 971 "tx queue stopped on %s, next2comp %u"
972 " next2fill %u\n", adapter->netdev->name,
973 tq->tx_ring.next2comp, tq->tx_ring.next2fill);
974
975 vmxnet3_tq_stop(tq, adapter);
976 spin_unlock_irqrestore(&tq->tx_lock, flags);
977 return NETDEV_TX_BUSY;
978 }
979
980
d1a890fa
SB		 981 ret = vmxnet3_parse_and_copy_hdr(skb, tq, &ctx, adapter);
982 if (ret >= 0) {
983 BUG_ON(ret <= 0 && ctx.copy_size != 0);
984 /* hdrs parsed, check against other limits */
985 if (ctx.mss) {
986 if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size >
987 VMXNET3_MAX_TX_BUF_SIZE)) {
988 goto hdr_too_big;
989 }
990 } else {
991 if (skb->ip_summed == CHECKSUM_PARTIAL) {
992 if (unlikely(ctx.eth_ip_hdr_size +
993 skb->csum_offset >
994 VMXNET3_MAX_CSUM_OFFSET)) {
995 goto hdr_too_big;
996 }
997 }
998 }
999 } else {
1000 tq->stats.drop_hdr_inspect_err++;
f955e141 1001 goto unlock_drop_pkt;
d1a890fa
SB		 1002 }
1003
d1a890fa
SB		 1004 /* fill tx descs related to addr & len */
1005 vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter);
1006
1007 /* setup the EOP desc */
115924b6 1008 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
d1a890fa
SB		 1009
1010 /* setup the SOP desc */
115924b6
SB		 1011#ifdef __BIG_ENDIAN_BITFIELD
1012 gdesc = &tempTxDesc;
1013 gdesc->dword[2] = ctx.sop_txd->dword[2];
1014 gdesc->dword[3] = ctx.sop_txd->dword[3];
1015#else
d1a890fa 1016 gdesc = ctx.sop_txd;
115924b6 1017#endif
d1a890fa
SB		 1018 if (ctx.mss) {
1019 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size;
1020 gdesc->txd.om = VMXNET3_OM_TSO;
1021 gdesc->txd.msscof = ctx.mss;
115924b6
SB		 1022 le32_add_cpu(&tq->shared->txNumDeferred, (skb->len -
1023 gdesc->txd.hlen + ctx.mss - 1) / ctx.mss);
d1a890fa
SB		 1024 } else {
1025 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1026 gdesc->txd.hlen = ctx.eth_ip_hdr_size;
1027 gdesc->txd.om = VMXNET3_OM_CSUM;
1028 gdesc->txd.msscof = ctx.eth_ip_hdr_size +
1029 skb->csum_offset;
1030 } else {
1031 gdesc->txd.om = 0;
1032 gdesc->txd.msscof = 0;
1033 }
115924b6 1034 le32_add_cpu(&tq->shared->txNumDeferred, 1);
d1a890fa
SB		 1035 }
1036
1037 if (vlan_tx_tag_present(skb)) {
1038 gdesc->txd.ti = 1;
1039 gdesc->txd.tci = vlan_tx_tag_get(skb);
1040 }
1041
115924b6
SB		 1042 /* finally flips the GEN bit of the SOP desc. */
1043 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1044 VMXNET3_TXD_GEN);
1045#ifdef __BIG_ENDIAN_BITFIELD
1046 /* Finished updating in bitfields of Tx Desc, so write them in original
1047 * place.
1048 */
1049 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1050 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1051 gdesc = ctx.sop_txd;
1052#endif
fdcd79b9 1053 netdev_dbg(adapter->netdev,
f6965582 1054 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
c2fd03a0 1055 (u32)(ctx.sop_txd -
115924b6
SB		 1056 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1057 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
d1a890fa
SB		 1058
1059 spin_unlock_irqrestore(&tq->tx_lock, flags);
1060
115924b6
SB		 1061 if (le32_to_cpu(tq->shared->txNumDeferred) >=
1062 le32_to_cpu(tq->shared->txThreshold)) {
d1a890fa 1063 tq->shared->txNumDeferred = 0;
09c5088e
SB		 1064 VMXNET3_WRITE_BAR0_REG(adapter,
1065 VMXNET3_REG_TXPROD + tq->qid * 8,
d1a890fa
SB		 1066 tq->tx_ring.next2fill);
1067 }
d1a890fa
SB		 1068
1069 return NETDEV_TX_OK;
1070
1071hdr_too_big:
1072 tq->stats.drop_oversized_hdr++;
f955e141
DC		 1073unlock_drop_pkt:
1074 spin_unlock_irqrestore(&tq->tx_lock, flags);
d1a890fa
SB		 1075drop_pkt:
1076 tq->stats.drop_total++;
1077 dev_kfree_skb(skb);
1078 return NETDEV_TX_OK;
1079}
1080
1081
1082static netdev_tx_t
1083vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1084{
1085 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1086
96800ee7 1087 BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1088 return vmxnet3_tq_xmit(skb,
1089 &adapter->tx_queue[skb->queue_mapping],
1090 adapter, netdev);
d1a890fa
SB		 1091}
1092
1093
1094static void
1095vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1096 struct sk_buff *skb,
1097 union Vmxnet3_GenericDesc *gdesc)
1098{
a0d2730c 1099 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
d1a890fa 1100 /* typical case: TCP/UDP over IP and both csums are correct */
115924b6 1101 if ((le32_to_cpu(gdesc->dword[3]) & VMXNET3_RCD_CSUM_OK) ==
d1a890fa
SB		 1102 VMXNET3_RCD_CSUM_OK) {
1103 skb->ip_summed = CHECKSUM_UNNECESSARY;
1104 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
1105 BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6));
1106 BUG_ON(gdesc->rcd.frg);
1107 } else {
1108 if (gdesc->rcd.csum) {
1109 skb->csum = htons(gdesc->rcd.csum);
1110 skb->ip_summed = CHECKSUM_PARTIAL;
1111 } else {
bc8acf2c 1112 skb_checksum_none_assert(skb);
d1a890fa
SB		 1113 }
1114 }
1115 } else {
bc8acf2c 1116 skb_checksum_none_assert(skb);
d1a890fa
SB		 1117 }
1118}
1119
1120
1121static void
1122vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1123 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
1124{
1125 rq->stats.drop_err++;
1126 if (!rcd->fcs)
1127 rq->stats.drop_fcs++;
1128
1129 rq->stats.drop_total++;
1130
1131 /*
1132 * We do not unmap and chain the rx buffer to the skb.
1133 * We basically pretend this buffer is not used and will be recycled
1134 * by vmxnet3_rq_alloc_rx_buf()
1135 */
1136
1137 /*
1138 * ctx->skb may be NULL if this is the first and the only one
1139 * desc for the pkt
1140 */
1141 if (ctx->skb)
1142 dev_kfree_skb_irq(ctx->skb);
1143
1144 ctx->skb = NULL;
1145}
1146
1147
1148static int
1149vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1150 struct vmxnet3_adapter *adapter, int quota)
1151{
215faf9c
JP		 1152 static const u32 rxprod_reg[2] = {
1153 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
1154 };
d1a890fa 1155 u32 num_rxd = 0;
5318d809 1156 bool skip_page_frags = false;
d1a890fa
SB		 1157 struct Vmxnet3_RxCompDesc *rcd;
1158 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
115924b6
SB		 1159#ifdef __BIG_ENDIAN_BITFIELD
1160 struct Vmxnet3_RxDesc rxCmdDesc;
1161 struct Vmxnet3_RxCompDesc rxComp;
1162#endif
1163 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1164 &rxComp);
d1a890fa
SB		 1165 while (rcd->gen == rq->comp_ring.gen) {
1166 struct vmxnet3_rx_buf_info *rbi;
5318d809
SB		 1167 struct sk_buff *skb, *new_skb = NULL;
1168 struct page *new_page = NULL;
d1a890fa
SB		 1169 int num_to_alloc;
1170 struct Vmxnet3_RxDesc *rxd;
1171 u32 idx, ring_idx;
5318d809 1172 struct vmxnet3_cmd_ring *ring = NULL;
d1a890fa
SB		 1173 if (num_rxd >= quota) {
1174 /* we may stop even before we see the EOP desc of
1175 * the current pkt
1176 */
1177 break;
1178 }
1179 num_rxd++;
09c5088e 1180 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2);
d1a890fa 1181 idx = rcd->rxdIdx;
09c5088e 1182 ring_idx = rcd->rqID < adapter->num_rx_queues ? 0 : 1;
5318d809 1183 ring = rq->rx_ring + ring_idx;
115924b6
SB		 1184 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1185 &rxCmdDesc);
d1a890fa
SB		 1186 rbi = rq->buf_info[ring_idx] + idx;
1187
115924b6
SB		 1188 BUG_ON(rxd->addr != rbi->dma_addr ||
1189 rxd->len != rbi->len);
d1a890fa
SB		 1190
1191 if (unlikely(rcd->eop && rcd->err)) {
1192 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1193 goto rcd_done;
1194 }
1195
1196 if (rcd->sop) { /* first buf of the pkt */
1197 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
1198 rcd->rqID != rq->qid);
1199
1200 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
1201 BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1202
1203 if (unlikely(rcd->len == 0)) {
1204 /* Pretend the rx buffer is skipped. */
1205 BUG_ON(!(rcd->sop && rcd->eop));
fdcd79b9 1206 netdev_dbg(adapter->netdev,
f6965582 1207 "rxRing[%u][%u] 0 length\n",
d1a890fa
SB		 1208 ring_idx, idx);
1209 goto rcd_done;
1210 }
1211
5318d809 1212 skip_page_frags = false;
d1a890fa 1213 ctx->skb = rbi->skb;
0d735f13
SH		 1214 new_skb = netdev_alloc_skb_ip_align(adapter->netdev,
1215 rbi->len);
5318d809
SB		 1216 if (new_skb == NULL) {
1217 /* Skb allocation failed, do not handover this
1218 * skb to stack. Reuse it. Drop the existing pkt
1219 */
1220 rq->stats.rx_buf_alloc_failure++;
1221 ctx->skb = NULL;
1222 rq->stats.drop_total++;
1223 skip_page_frags = true;
1224 goto rcd_done;
1225 }
d1a890fa
SB		 1226
1227 pci_unmap_single(adapter->pdev, rbi->dma_addr, rbi->len,
1228 PCI_DMA_FROMDEVICE);
1229
1230 skb_put(ctx->skb, rcd->len);
5318d809
SB		 1231
1232 /* Immediate refill */
5318d809
SB		 1233 rbi->skb = new_skb;
1234 rbi->dma_addr = pci_map_single(adapter->pdev,
96800ee7 1235 rbi->skb->data, rbi->len,
1236 PCI_DMA_FROMDEVICE);
5318d809
SB		 1237 rxd->addr = cpu_to_le64(rbi->dma_addr);
1238 rxd->len = rbi->len;
1239
d1a890fa 1240 } else {
5318d809
SB		 1241 BUG_ON(ctx->skb == NULL && !skip_page_frags);
1242
d1a890fa 1243 /* non SOP buffer must be type 1 in most cases */
5318d809
SB		 1244 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
1245 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
d1a890fa 1246
5318d809
SB		 1247 /* If an sop buffer was dropped, skip all
1248 * following non-sop fragments. They will be reused.
1249 */
1250 if (skip_page_frags)
1251 goto rcd_done;
d1a890fa 1252
5318d809
SB		 1253 new_page = alloc_page(GFP_ATOMIC);
1254 if (unlikely(new_page == NULL)) {
1255 /* Replacement page frag could not be allocated.
1256 * Reuse this page. Drop the pkt and free the
1257 * skb which contained this page as a frag. Skip
1258 * processing all the following non-sop frags.
d1a890fa 1259 */
5318d809
SB		 1260 rq->stats.rx_buf_alloc_failure++;
1261 dev_kfree_skb(ctx->skb);
1262 ctx->skb = NULL;
1263 skip_page_frags = true;
1264 goto rcd_done;
1265 }
1266
1267 if (rcd->len) {
1268 pci_unmap_page(adapter->pdev,
1269 rbi->dma_addr, rbi->len,
1270 PCI_DMA_FROMDEVICE);
1271
1272 vmxnet3_append_frag(ctx->skb, rcd, rbi);
d1a890fa 1273 }
5318d809
SB		 1274
1275 /* Immediate refill */
1276 rbi->page = new_page;
1277 rbi->dma_addr = pci_map_page(adapter->pdev, rbi->page,
1278 0, PAGE_SIZE,
1279 PCI_DMA_FROMDEVICE);
1280 rxd->addr = cpu_to_le64(rbi->dma_addr);
1281 rxd->len = rbi->len;
d1a890fa
SB		 1282 }
1283
5318d809 1284
d1a890fa
SB		 1285 skb = ctx->skb;
1286 if (rcd->eop) {
1287 skb->len += skb->data_len;
d1a890fa
SB		 1288
1289 vmxnet3_rx_csum(adapter, skb,
1290 (union Vmxnet3_GenericDesc *)rcd);
1291 skb->protocol = eth_type_trans(skb, adapter->netdev);
1292
72e85c45
JG		 1293 if (unlikely(rcd->ts))
1294 __vlan_hwaccel_put_tag(skb, rcd->tci);
1295
213ade8c
JG		 1296 if (adapter->netdev->features & NETIF_F_LRO)
1297 netif_receive_skb(skb);
1298 else
1299 napi_gro_receive(&rq->napi, skb);
d1a890fa 1300
d1a890fa
SB		 1301 ctx->skb = NULL;
1302 }
1303
1304rcd_done:
5318d809
SB		 1305 /* device may have skipped some rx descs */
1306 ring->next2comp = idx;
1307 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
1308 ring = rq->rx_ring + ring_idx;
1309 while (num_to_alloc) {
1310 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
1311 &rxCmdDesc);
1312 BUG_ON(!rxd->addr);
1313
1314 /* Recv desc is ready to be used by the device */
1315 rxd->gen = ring->gen;
1316 vmxnet3_cmd_ring_adv_next2fill(ring);
1317 num_to_alloc--;
1318 }
1319
1320 /* if needed, update the register */
1321 if (unlikely(rq->shared->updateRxProd)) {
1322 VMXNET3_WRITE_BAR0_REG(adapter,
96800ee7 1323 rxprod_reg[ring_idx] + rq->qid * 8,
1324 ring->next2fill);
d1a890fa
SB		 1325 }
1326
1327 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
115924b6 1328 vmxnet3_getRxComp(rcd,
96800ee7 1329 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
d1a890fa
SB		 1330 }
1331
1332 return num_rxd;
1333}
1334
1335
1336static void
1337vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1338 struct vmxnet3_adapter *adapter)
1339{
1340 u32 i, ring_idx;
1341 struct Vmxnet3_RxDesc *rxd;
1342
1343 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1344 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
115924b6
SB		 1345#ifdef __BIG_ENDIAN_BITFIELD
1346 struct Vmxnet3_RxDesc rxDesc;
1347#endif
1348 vmxnet3_getRxDesc(rxd,
1349 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
d1a890fa
SB		 1350
1351 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1352 rq->buf_info[ring_idx][i].skb) {
1353 pci_unmap_single(adapter->pdev, rxd->addr,
1354 rxd->len, PCI_DMA_FROMDEVICE);
1355 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1356 rq->buf_info[ring_idx][i].skb = NULL;
1357 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1358 rq->buf_info[ring_idx][i].page) {
1359 pci_unmap_page(adapter->pdev, rxd->addr,
1360 rxd->len, PCI_DMA_FROMDEVICE);
1361 put_page(rq->buf_info[ring_idx][i].page);
1362 rq->buf_info[ring_idx][i].page = NULL;
1363 }
1364 }
1365
1366 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1367 rq->rx_ring[ring_idx].next2fill =
1368 rq->rx_ring[ring_idx].next2comp = 0;
d1a890fa
SB		 1369 }
1370
1371 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1372 rq->comp_ring.next2proc = 0;
1373}
1374
1375
09c5088e
SB		 1376static void
1377vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1378{
1379 int i;
1380
1381 for (i = 0; i < adapter->num_rx_queues; i++)
1382 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1383}
1384
1385
d1a890fa
SB		 1386void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1387 struct vmxnet3_adapter *adapter)
1388{
1389 int i;
1390 int j;
1391
1392 /* all rx buffers must have already been freed */
1393 for (i = 0; i < 2; i++) {
1394 if (rq->buf_info[i]) {
1395 for (j = 0; j < rq->rx_ring[i].size; j++)
1396 BUG_ON(rq->buf_info[i][j].page != NULL);
1397 }
1398 }
1399
1400
1401 kfree(rq->buf_info[0]);
1402
1403 for (i = 0; i < 2; i++) {
1404 if (rq->rx_ring[i].base) {
1405 pci_free_consistent(adapter->pdev, rq->rx_ring[i].size
1406 * sizeof(struct Vmxnet3_RxDesc),
1407 rq->rx_ring[i].base,
1408 rq->rx_ring[i].basePA);
1409 rq->rx_ring[i].base = NULL;
1410 }
1411 rq->buf_info[i] = NULL;
1412 }
1413
1414 if (rq->comp_ring.base) {
1415 pci_free_consistent(adapter->pdev, rq->comp_ring.size *
1416 sizeof(struct Vmxnet3_RxCompDesc),
1417 rq->comp_ring.base, rq->comp_ring.basePA);
1418 rq->comp_ring.base = NULL;
1419 }
1420}
1421
1422
1423static int
1424vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
1425 struct vmxnet3_adapter *adapter)
1426{
1427 int i;
1428
1429 /* initialize buf_info */
1430 for (i = 0; i < rq->rx_ring[0].size; i++) {
1431
1432 /* 1st buf for a pkt is skbuff */
1433 if (i % adapter->rx_buf_per_pkt == 0) {
1434 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
1435 rq->buf_info[0][i].len = adapter->skb_buf_size;
1436 } else { /* subsequent bufs for a pkt is frag */
1437 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
1438 rq->buf_info[0][i].len = PAGE_SIZE;
1439 }
1440 }
1441 for (i = 0; i < rq->rx_ring[1].size; i++) {
1442 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
1443 rq->buf_info[1][i].len = PAGE_SIZE;
1444 }
1445
1446 /* reset internal state and allocate buffers for both rings */
1447 for (i = 0; i < 2; i++) {
1448 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
d1a890fa
SB		 1449
1450 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
1451 sizeof(struct Vmxnet3_RxDesc));
1452 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
1453 }
1454 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
1455 adapter) == 0) {
1456 /* at least has 1 rx buffer for the 1st ring */
1457 return -ENOMEM;
1458 }
1459 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
1460
1461 /* reset the comp ring */
1462 rq->comp_ring.next2proc = 0;
1463 memset(rq->comp_ring.base, 0, rq->comp_ring.size *
1464 sizeof(struct Vmxnet3_RxCompDesc));
1465 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1466
1467 /* reset rxctx */
1468 rq->rx_ctx.skb = NULL;
1469
1470 /* stats are not reset */
1471 return 0;
1472}
1473
1474
09c5088e
SB		 1475static int
1476vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
1477{
1478 int i, err = 0;
1479
1480 for (i = 0; i < adapter->num_rx_queues; i++) {
1481 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
1482 if (unlikely(err)) {
1483 dev_err(&adapter->netdev->dev, "%s: failed to "
1484 "initialize rx queue%i\n",
1485 adapter->netdev->name, i);
1486 break;
1487 }
1488 }
1489 return err;
1490
1491}
1492
1493
d1a890fa
SB		 1494static int
1495vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
1496{
1497 int i;
1498 size_t sz;
1499 struct vmxnet3_rx_buf_info *bi;
1500
1501 for (i = 0; i < 2; i++) {
1502
1503 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
1504 rq->rx_ring[i].base = pci_alloc_consistent(adapter->pdev, sz,
1505 &rq->rx_ring[i].basePA);
1506 if (!rq->rx_ring[i].base) {
204a6e65
SH		 1507 netdev_err(adapter->netdev,
1508 "failed to allocate rx ring %d\n", i);
d1a890fa
SB		 1509 goto err;
1510 }
1511 }
1512
1513 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
1514 rq->comp_ring.base = pci_alloc_consistent(adapter->pdev, sz,
1515 &rq->comp_ring.basePA);
1516 if (!rq->comp_ring.base) {
204a6e65 1517 netdev_err(adapter->netdev, "failed to allocate rx comp ring\n");
d1a890fa
SB		 1518 goto err;
1519 }
1520
1521 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
1522 rq->rx_ring[1].size);
476c609e 1523 bi = kzalloc(sz, GFP_KERNEL);
e404decb 1524 if (!bi)
d1a890fa 1525 goto err;
e404decb 1526
d1a890fa
SB		 1527 rq->buf_info[0] = bi;
1528 rq->buf_info[1] = bi + rq->rx_ring[0].size;
1529
1530 return 0;
1531
1532err:
1533 vmxnet3_rq_destroy(rq, adapter);
1534 return -ENOMEM;
1535}
1536
1537
09c5088e
SB		 1538static int
1539vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
1540{
1541 int i, err = 0;
1542
1543 for (i = 0; i < adapter->num_rx_queues; i++) {
1544 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
1545 if (unlikely(err)) {
1546 dev_err(&adapter->netdev->dev,
1547 "%s: failed to create rx queue%i\n",
1548 adapter->netdev->name, i);
1549 goto err_out;
1550 }
1551 }
1552 return err;
1553err_out:
1554 vmxnet3_rq_destroy_all(adapter);
1555 return err;
1556
1557}
1558
1559/* Multiple queue aware polling function for tx and rx */
1560
d1a890fa
SB		 1561static int
1562vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
1563{
09c5088e 1564 int rcd_done = 0, i;
d1a890fa
SB		 1565 if (unlikely(adapter->shared->ecr))
1566 vmxnet3_process_events(adapter);
09c5088e
SB		 1567 for (i = 0; i < adapter->num_tx_queues; i++)
1568 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
d1a890fa 1569
09c5088e
SB		 1570 for (i = 0; i < adapter->num_rx_queues; i++)
1571 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
1572 adapter, budget);
1573 return rcd_done;
d1a890fa
SB		 1574}
1575
1576
1577static int
1578vmxnet3_poll(struct napi_struct *napi, int budget)
1579{
09c5088e
SB		 1580 struct vmxnet3_rx_queue *rx_queue = container_of(napi,
1581 struct vmxnet3_rx_queue, napi);
1582 int rxd_done;
1583
1584 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
1585
1586 if (rxd_done < budget) {
1587 napi_complete(napi);
1588 vmxnet3_enable_all_intrs(rx_queue->adapter);
1589 }
1590 return rxd_done;
1591}
1592
1593/*
1594 * NAPI polling function for MSI-X mode with multiple Rx queues
1595 * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
1596 */
1597
1598static int
1599vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
1600{
1601 struct vmxnet3_rx_queue *rq = container_of(napi,
1602 struct vmxnet3_rx_queue, napi);
1603 struct vmxnet3_adapter *adapter = rq->adapter;
d1a890fa
SB		 1604 int rxd_done;
1605
09c5088e
SB		 1606 /* When sharing interrupt with corresponding tx queue, process
1607 * tx completions in that queue as well
1608 */
1609 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
1610 struct vmxnet3_tx_queue *tq =
1611 &adapter->tx_queue[rq - adapter->rx_queue];
1612 vmxnet3_tq_tx_complete(tq, adapter);
1613 }
1614
1615 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
d1a890fa
SB		 1616
1617 if (rxd_done < budget) {
1618 napi_complete(napi);
09c5088e 1619 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
d1a890fa
SB		 1620 }
1621 return rxd_done;
1622}
1623
1624
09c5088e
SB		 1625#ifdef CONFIG_PCI_MSI
1626
1627/*
1628 * Handle completion interrupts on tx queues
1629 * Returns whether or not the intr is handled
1630 */
1631
1632static irqreturn_t
1633vmxnet3_msix_tx(int irq, void *data)
1634{
1635 struct vmxnet3_tx_queue *tq = data;
1636 struct vmxnet3_adapter *adapter = tq->adapter;
1637
1638 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1639 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
1640
1641 /* Handle the case where only one irq is allocate for all tx queues */
1642 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1643 int i;
1644 for (i = 0; i < adapter->num_tx_queues; i++) {
1645 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
1646 vmxnet3_tq_tx_complete(txq, adapter);
1647 }
1648 } else {
1649 vmxnet3_tq_tx_complete(tq, adapter);
1650 }
1651 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
1652
1653 return IRQ_HANDLED;
1654}
1655
1656
1657/*
1658 * Handle completion interrupts on rx queues. Returns whether or not the
1659 * intr is handled
1660 */
1661
1662static irqreturn_t
1663vmxnet3_msix_rx(int irq, void *data)
1664{
1665 struct vmxnet3_rx_queue *rq = data;
1666 struct vmxnet3_adapter *adapter = rq->adapter;
1667
1668 /* disable intr if needed */
1669 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1670 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
1671 napi_schedule(&rq->napi);
1672
1673 return IRQ_HANDLED;
1674}
1675
1676/*
1677 *----------------------------------------------------------------------------
1678 *
1679 * vmxnet3_msix_event --
1680 *
1681 * vmxnet3 msix event intr handler
1682 *
1683 * Result:
1684 * whether or not the intr is handled
1685 *
1686 *----------------------------------------------------------------------------
1687 */
1688
1689static irqreturn_t
1690vmxnet3_msix_event(int irq, void *data)
1691{
1692 struct net_device *dev = data;
1693 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1694
1695 /* disable intr if needed */
1696 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1697 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
1698
1699 if (adapter->shared->ecr)
1700 vmxnet3_process_events(adapter);
1701
1702 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
1703
1704 return IRQ_HANDLED;
1705}
1706
1707#endif /* CONFIG_PCI_MSI */
1708
1709
d1a890fa
SB		 1710/* Interrupt handler for vmxnet3 */
1711static irqreturn_t
1712vmxnet3_intr(int irq, void *dev_id)
1713{
1714 struct net_device *dev = dev_id;
1715 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1716
09c5088e 1717 if (adapter->intr.type == VMXNET3_IT_INTX) {
d1a890fa
SB		 1718 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
1719 if (unlikely(icr == 0))
1720 /* not ours */
1721 return IRQ_NONE;
1722 }
1723
1724
1725 /* disable intr if needed */
1726 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
09c5088e 1727 vmxnet3_disable_all_intrs(adapter);
d1a890fa 1728
09c5088e 1729 napi_schedule(&adapter->rx_queue[0].napi);
d1a890fa
SB		 1730
1731 return IRQ_HANDLED;
1732}
1733
1734#ifdef CONFIG_NET_POLL_CONTROLLER
1735
d1a890fa
SB		 1736/* netpoll callback. */
1737static void
1738vmxnet3_netpoll(struct net_device *netdev)
1739{
1740 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1741
09c5088e
SB		 1742 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1743 vmxnet3_disable_all_intrs(adapter);
1744
1745 vmxnet3_do_poll(adapter, adapter->rx_queue[0].rx_ring[0].size);
1746 vmxnet3_enable_all_intrs(adapter);
d1a890fa 1747
d1a890fa 1748}
09c5088e 1749#endif /* CONFIG_NET_POLL_CONTROLLER */
d1a890fa
SB		 1750
1751static int
1752vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
1753{
09c5088e
SB		 1754 struct vmxnet3_intr *intr = &adapter->intr;
1755 int err = 0, i;
1756 int vector = 0;
d1a890fa 1757
8f7e524c 1758#ifdef CONFIG_PCI_MSI
d1a890fa 1759 if (adapter->intr.type == VMXNET3_IT_MSIX) {
09c5088e
SB		 1760 for (i = 0; i < adapter->num_tx_queues; i++) {
1761 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
1762 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
1763 adapter->netdev->name, vector);
1764 err = request_irq(
1765 intr->msix_entries[vector].vector,
1766 vmxnet3_msix_tx, 0,
1767 adapter->tx_queue[i].name,
1768 &adapter->tx_queue[i]);
1769 } else {
1770 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
1771 adapter->netdev->name, vector);
1772 }
1773 if (err) {
1774 dev_err(&adapter->netdev->dev,
1775 "Failed to request irq for MSIX, %s, "
1776 "error %d\n",
1777 adapter->tx_queue[i].name, err);
1778 return err;
1779 }
1780
1781 /* Handle the case where only 1 MSIx was allocated for
1782 * all tx queues */
1783 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1784 for (; i < adapter->num_tx_queues; i++)
1785 adapter->tx_queue[i].comp_ring.intr_idx
1786 = vector;
1787 vector++;
1788 break;
1789 } else {
1790 adapter->tx_queue[i].comp_ring.intr_idx
1791 = vector++;
1792 }
1793 }
1794 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
1795 vector = 0;
1796
1797 for (i = 0; i < adapter->num_rx_queues; i++) {
1798 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
1799 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
1800 adapter->netdev->name, vector);
1801 else
1802 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
1803 adapter->netdev->name, vector);
1804 err = request_irq(intr->msix_entries[vector].vector,
1805 vmxnet3_msix_rx, 0,
1806 adapter->rx_queue[i].name,
1807 &(adapter->rx_queue[i]));
1808 if (err) {
204a6e65
SH		 1809 netdev_err(adapter->netdev,
1810 "Failed to request irq for MSIX, "
1811 "%s, error %d\n",
1812 adapter->rx_queue[i].name, err);
09c5088e
SB		 1813 return err;
1814 }
1815
1816 adapter->rx_queue[i].comp_ring.intr_idx = vector++;
1817 }
1818
1819 sprintf(intr->event_msi_vector_name, "%s-event-%d",
1820 adapter->netdev->name, vector);
1821 err = request_irq(intr->msix_entries[vector].vector,
1822 vmxnet3_msix_event, 0,
1823 intr->event_msi_vector_name, adapter->netdev);
1824 intr->event_intr_idx = vector;
1825
1826 } else if (intr->type == VMXNET3_IT_MSI) {
1827 adapter->num_rx_queues = 1;
d1a890fa
SB		 1828 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
1829 adapter->netdev->name, adapter->netdev);
09c5088e 1830 } else {
115924b6 1831#endif
09c5088e 1832 adapter->num_rx_queues = 1;
d1a890fa
SB		 1833 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
1834 IRQF_SHARED, adapter->netdev->name,
1835 adapter->netdev);
09c5088e 1836#ifdef CONFIG_PCI_MSI
d1a890fa 1837 }
09c5088e
SB		 1838#endif
1839 intr->num_intrs = vector + 1;
1840 if (err) {
204a6e65
SH		 1841 netdev_err(adapter->netdev,
1842 "Failed to request irq (intr type:%d), error %d\n",
1843 intr->type, err);
09c5088e
SB		 1844 } else {
1845 /* Number of rx queues will not change after this */
1846 for (i = 0; i < adapter->num_rx_queues; i++) {
1847 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
1848 rq->qid = i;
1849 rq->qid2 = i + adapter->num_rx_queues;
1850 }
d1a890fa
SB		 1851
1852
d1a890fa 1853
09c5088e
SB		 1854 /* init our intr settings */
1855 for (i = 0; i < intr->num_intrs; i++)
1856 intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
1857 if (adapter->intr.type != VMXNET3_IT_MSIX) {
1858 adapter->intr.event_intr_idx = 0;
1859 for (i = 0; i < adapter->num_tx_queues; i++)
1860 adapter->tx_queue[i].comp_ring.intr_idx = 0;
1861 adapter->rx_queue[0].comp_ring.intr_idx = 0;
1862 }
d1a890fa 1863
204a6e65
SH		 1864 netdev_info(adapter->netdev,
1865 "intr type %u, mode %u, %u vectors allocated\n",
1866 intr->type, intr->mask_mode, intr->num_intrs);
d1a890fa
SB		 1867 }
1868
1869 return err;
1870}
1871
1872
1873static void
1874vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
1875{
09c5088e
SB		 1876 struct vmxnet3_intr *intr = &adapter->intr;
1877 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
d1a890fa 1878
09c5088e 1879 switch (intr->type) {
8f7e524c 1880#ifdef CONFIG_PCI_MSI
d1a890fa
SB		 1881 case VMXNET3_IT_MSIX:
1882 {
09c5088e 1883 int i, vector = 0;
d1a890fa 1884
09c5088e
SB		 1885 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
1886 for (i = 0; i < adapter->num_tx_queues; i++) {
1887 free_irq(intr->msix_entries[vector++].vector,
1888 &(adapter->tx_queue[i]));
1889 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
1890 break;
1891 }
1892 }
1893
1894 for (i = 0; i < adapter->num_rx_queues; i++) {
1895 free_irq(intr->msix_entries[vector++].vector,
1896 &(adapter->rx_queue[i]));
1897 }
1898
1899 free_irq(intr->msix_entries[vector].vector,
1900 adapter->netdev);
1901 BUG_ON(vector >= intr->num_intrs);
d1a890fa
SB		 1902 break;
1903 }
8f7e524c 1904#endif
d1a890fa
SB		 1905 case VMXNET3_IT_MSI:
1906 free_irq(adapter->pdev->irq, adapter->netdev);
1907 break;
1908 case VMXNET3_IT_INTX:
1909 free_irq(adapter->pdev->irq, adapter->netdev);
1910 break;
1911 default:
c068e777 1912 BUG();
d1a890fa
SB		 1913 }
1914}
1915
d1a890fa
SB		 1916
1917static void
1918vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
1919{
72e85c45
JG		 1920 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1921 u16 vid;
d1a890fa 1922
72e85c45
JG		 1923 /* allow untagged pkts */
1924 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
1925
1926 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
1927 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
d1a890fa
SB		 1928}
1929
1930
8e586137 1931static int
d1a890fa
SB		 1932vmxnet3_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1933{
1934 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1935
f6957f88
JG		 1936 if (!(netdev->flags & IFF_PROMISC)) {
1937 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1938 unsigned long flags;
1939
1940 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
1941 spin_lock_irqsave(&adapter->cmd_lock, flags);
1942 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1943 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1944 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
1945 }
72e85c45
JG		 1946
1947 set_bit(vid, adapter->active_vlans);
8e586137
JP		 1948
1949 return 0;
d1a890fa
SB		 1950}
1951
1952
8e586137 1953static int
d1a890fa
SB		 1954vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1955{
1956 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1957
f6957f88
JG		 1958 if (!(netdev->flags & IFF_PROMISC)) {
1959 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1960 unsigned long flags;
1961
1962 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
1963 spin_lock_irqsave(&adapter->cmd_lock, flags);
1964 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1965 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1966 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
1967 }
72e85c45
JG		 1968
1969 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 1970
1971 return 0;
d1a890fa
SB		 1972}
1973
1974
1975static u8 *
1976vmxnet3_copy_mc(struct net_device *netdev)
1977{
1978 u8 *buf = NULL;
4cd24eaf 1979 u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
d1a890fa
SB		 1980
1981 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
1982 if (sz <= 0xffff) {
1983 /* We may be called with BH disabled */
1984 buf = kmalloc(sz, GFP_ATOMIC);
1985 if (buf) {
22bedad3 1986 struct netdev_hw_addr *ha;
567ec874 1987 int i = 0;
d1a890fa 1988
22bedad3
JP		 1989 netdev_for_each_mc_addr(ha, netdev)
1990 memcpy(buf + i++ * ETH_ALEN, ha->addr,
d1a890fa 1991 ETH_ALEN);
d1a890fa
SB		 1992 }
1993 }
1994 return buf;
1995}
1996
1997
1998static void
1999vmxnet3_set_mc(struct net_device *netdev)
2000{
2001 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
83d0feff 2002 unsigned long flags;
d1a890fa
SB		 2003 struct Vmxnet3_RxFilterConf *rxConf =
2004 &adapter->shared->devRead.rxFilterConf;
2005 u8 *new_table = NULL;
2006 u32 new_mode = VMXNET3_RXM_UCAST;
2007
72e85c45
JG		 2008 if (netdev->flags & IFF_PROMISC) {
2009 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2010 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
2011
d1a890fa 2012 new_mode |= VMXNET3_RXM_PROMISC;
72e85c45
JG		 2013 } else {
2014 vmxnet3_restore_vlan(adapter);
2015 }
d1a890fa
SB		 2016
2017 if (netdev->flags & IFF_BROADCAST)
2018 new_mode |= VMXNET3_RXM_BCAST;
2019
2020 if (netdev->flags & IFF_ALLMULTI)
2021 new_mode |= VMXNET3_RXM_ALL_MULTI;
2022 else
4cd24eaf 2023 if (!netdev_mc_empty(netdev)) {
d1a890fa
SB		 2024 new_table = vmxnet3_copy_mc(netdev);
2025 if (new_table) {
2026 new_mode |= VMXNET3_RXM_MCAST;
115924b6 2027 rxConf->mfTableLen = cpu_to_le16(
4cd24eaf 2028 netdev_mc_count(netdev) * ETH_ALEN);
115924b6
SB		 2029 rxConf->mfTablePA = cpu_to_le64(virt_to_phys(
2030 new_table));
d1a890fa 2031 } else {
204a6e65
SH		 2032 netdev_info(netdev, "failed to copy mcast list"
2033 ", setting ALL_MULTI\n");
d1a890fa
SB		 2034 new_mode |= VMXNET3_RXM_ALL_MULTI;
2035 }
2036 }
2037
2038
2039 if (!(new_mode & VMXNET3_RXM_MCAST)) {
2040 rxConf->mfTableLen = 0;
2041 rxConf->mfTablePA = 0;
2042 }
2043
83d0feff 2044 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 2045 if (new_mode != rxConf->rxMode) {
115924b6 2046 rxConf->rxMode = cpu_to_le32(new_mode);
d1a890fa
SB		 2047 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2048 VMXNET3_CMD_UPDATE_RX_MODE);
72e85c45
JG		 2049 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2050 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
d1a890fa
SB		 2051 }
2052
2053 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2054 VMXNET3_CMD_UPDATE_MAC_FILTERS);
83d0feff 2055 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2056
2057 kfree(new_table);
2058}
2059
09c5088e
SB		 2060void
2061vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2062{
2063 int i;
2064
2065 for (i = 0; i < adapter->num_rx_queues; i++)
2066 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2067}
2068
d1a890fa
SB		 2069
2070/*
2071 * Set up driver_shared based on settings in adapter.
2072 */
2073
2074static void
2075vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2076{
2077 struct Vmxnet3_DriverShared *shared = adapter->shared;
2078 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2079 struct Vmxnet3_TxQueueConf *tqc;
2080 struct Vmxnet3_RxQueueConf *rqc;
2081 int i;
2082
2083 memset(shared, 0, sizeof(*shared));
2084
2085 /* driver settings */
115924b6
SB		 2086 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2087 devRead->misc.driverInfo.version = cpu_to_le32(
2088 VMXNET3_DRIVER_VERSION_NUM);
d1a890fa
SB		 2089 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2090 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2091 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
115924b6
SB		 2092 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2093 *((u32 *)&devRead->misc.driverInfo.gos));
2094 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2095 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
d1a890fa 2096
115924b6
SB		 2097 devRead->misc.ddPA = cpu_to_le64(virt_to_phys(adapter));
2098 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
d1a890fa
SB		 2099
2100 /* set up feature flags */
a0d2730c 2101 if (adapter->netdev->features & NETIF_F_RXCSUM)
3843e515 2102 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
d1a890fa 2103
a0d2730c 2104 if (adapter->netdev->features & NETIF_F_LRO) {
3843e515 2105 devRead->misc.uptFeatures |= UPT1_F_LRO;
115924b6 2106 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
d1a890fa 2107 }
54da3d00 2108 if (adapter->netdev->features & NETIF_F_HW_VLAN_RX)
3843e515 2109 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
d1a890fa 2110
115924b6
SB		 2111 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2112 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2113 devRead->misc.queueDescLen = cpu_to_le32(
09c5088e
SB		 2114 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2115 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
d1a890fa
SB		 2116
2117 /* tx queue settings */
09c5088e
SB		 2118 devRead->misc.numTxQueues = adapter->num_tx_queues;
2119 for (i = 0; i < adapter->num_tx_queues; i++) {
2120 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2121 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2122 tqc = &adapter->tqd_start[i].conf;
2123 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
2124 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2125 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
2126 tqc->ddPA = cpu_to_le64(virt_to_phys(tq->buf_info));
2127 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
2128 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
2129 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
2130 tqc->ddLen = cpu_to_le32(
2131 sizeof(struct vmxnet3_tx_buf_info) *
2132 tqc->txRingSize);
2133 tqc->intrIdx = tq->comp_ring.intr_idx;
2134 }
d1a890fa
SB		 2135
2136 /* rx queue settings */
09c5088e
SB		 2137 devRead->misc.numRxQueues = adapter->num_rx_queues;
2138 for (i = 0; i < adapter->num_rx_queues; i++) {
2139 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2140 rqc = &adapter->rqd_start[i].conf;
2141 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2142 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2143 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
2144 rqc->ddPA = cpu_to_le64(virt_to_phys(
2145 rq->buf_info));
2146 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
2147 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
2148 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
2149 rqc->ddLen = cpu_to_le32(
2150 sizeof(struct vmxnet3_rx_buf_info) *
2151 (rqc->rxRingSize[0] +
2152 rqc->rxRingSize[1]));
2153 rqc->intrIdx = rq->comp_ring.intr_idx;
2154 }
2155
2156#ifdef VMXNET3_RSS
2157 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2158
2159 if (adapter->rss) {
2160 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
2161 devRead->misc.uptFeatures |= UPT1_F_RSS;
2162 devRead->misc.numRxQueues = adapter->num_rx_queues;
2163 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2164 UPT1_RSS_HASH_TYPE_IPV4 |
2165 UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2166 UPT1_RSS_HASH_TYPE_IPV6;
2167 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2168 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2169 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
2170 get_random_bytes(&rssConf->hashKey[0], rssConf->hashKeySize);
2171 for (i = 0; i < rssConf->indTableSize; i++)
278bc429
BH		 2172 rssConf->indTable[i] = ethtool_rxfh_indir_default(
2173 i, adapter->num_rx_queues);
09c5088e
SB		 2174
2175 devRead->rssConfDesc.confVer = 1;
2176 devRead->rssConfDesc.confLen = sizeof(*rssConf);
2177 devRead->rssConfDesc.confPA = virt_to_phys(rssConf);
2178 }
2179
2180#endif /* VMXNET3_RSS */
d1a890fa
SB		 2181
2182 /* intr settings */
2183 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2184 VMXNET3_IMM_AUTO;
2185 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2186 for (i = 0; i < adapter->intr.num_intrs; i++)
2187 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2188
2189 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
6929fe8a 2190 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 2191
2192 /* rx filter settings */
2193 devRead->rxFilterConf.rxMode = 0;
2194 vmxnet3_restore_vlan(adapter);
f9f25026
SB		 2195 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2196
d1a890fa
SB		 2197 /* the rest are already zeroed */
2198}
2199
2200
2201int
2202vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
2203{
09c5088e 2204 int err, i;
d1a890fa 2205 u32 ret;
83d0feff 2206 unsigned long flags;
d1a890fa 2207
fdcd79b9 2208 netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
09c5088e
SB		 2209 " ring sizes %u %u %u\n", adapter->netdev->name,
2210 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
2211 adapter->tx_queue[0].tx_ring.size,
2212 adapter->rx_queue[0].rx_ring[0].size,
2213 adapter->rx_queue[0].rx_ring[1].size);
2214
2215 vmxnet3_tq_init_all(adapter);
2216 err = vmxnet3_rq_init_all(adapter);
d1a890fa 2217 if (err) {
204a6e65
SH		 2218 netdev_err(adapter->netdev,
2219 "Failed to init rx queue error %d\n", err);
d1a890fa
SB		 2220 goto rq_err;
2221 }
2222
2223 err = vmxnet3_request_irqs(adapter);
2224 if (err) {
204a6e65
SH		 2225 netdev_err(adapter->netdev,
2226 "Failed to setup irq for error %d\n", err);
d1a890fa
SB		 2227 goto irq_err;
2228 }
2229
2230 vmxnet3_setup_driver_shared(adapter);
2231
115924b6
SB		 2232 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
2233 adapter->shared_pa));
2234 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
2235 adapter->shared_pa));
83d0feff 2236 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2237 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2238 VMXNET3_CMD_ACTIVATE_DEV);
2239 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
83d0feff 2240 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2241
2242 if (ret != 0) {
204a6e65
SH		 2243 netdev_err(adapter->netdev,
2244 "Failed to activate dev: error %u\n", ret);
d1a890fa
SB		 2245 err = -EINVAL;
2246 goto activate_err;
2247 }
09c5088e
SB		 2248
2249 for (i = 0; i < adapter->num_rx_queues; i++) {
2250 VMXNET3_WRITE_BAR0_REG(adapter,
2251 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
2252 adapter->rx_queue[i].rx_ring[0].next2fill);
2253 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
2254 (i * VMXNET3_REG_ALIGN)),
2255 adapter->rx_queue[i].rx_ring[1].next2fill);
2256 }
d1a890fa
SB		 2257
2258 /* Apply the rx filter settins last. */
2259 vmxnet3_set_mc(adapter->netdev);
2260
2261 /*
2262 * Check link state when first activating device. It will start the
2263 * tx queue if the link is up.
2264 */
4a1745fc 2265 vmxnet3_check_link(adapter, true);
09c5088e
SB		 2266 for (i = 0; i < adapter->num_rx_queues; i++)
2267 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2268 vmxnet3_enable_all_intrs(adapter);
2269 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
2270 return 0;
2271
2272activate_err:
2273 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
2274 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
2275 vmxnet3_free_irqs(adapter);
2276irq_err:
2277rq_err:
2278 /* free up buffers we allocated */
09c5088e 2279 vmxnet3_rq_cleanup_all(adapter);
d1a890fa
SB		 2280 return err;
2281}
2282
2283
2284void
2285vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
2286{
83d0feff
SB		 2287 unsigned long flags;
2288 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 2289 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
83d0feff 2290 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2291}
2292
2293
2294int
2295vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
2296{
09c5088e 2297 int i;
83d0feff 2298 unsigned long flags;
d1a890fa
SB		 2299 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
2300 return 0;
2301
2302
83d0feff 2303 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2304 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2305 VMXNET3_CMD_QUIESCE_DEV);
83d0feff 2306 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2307 vmxnet3_disable_all_intrs(adapter);
2308
09c5088e
SB		 2309 for (i = 0; i < adapter->num_rx_queues; i++)
2310 napi_disable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2311 netif_tx_disable(adapter->netdev);
2312 adapter->link_speed = 0;
2313 netif_carrier_off(adapter->netdev);
2314
09c5088e
SB		 2315 vmxnet3_tq_cleanup_all(adapter);
2316 vmxnet3_rq_cleanup_all(adapter);
d1a890fa
SB		 2317 vmxnet3_free_irqs(adapter);
2318 return 0;
2319}
2320
2321
2322static void
2323vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2324{
2325 u32 tmp;
2326
2327 tmp = *(u32 *)mac;
2328 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
2329
2330 tmp = (mac[5] << 8) | mac[4];
2331 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
2332}
2333
2334
2335static int
2336vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
2337{
2338 struct sockaddr *addr = p;
2339 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2340
2341 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2342 vmxnet3_write_mac_addr(adapter, addr->sa_data);
2343
2344 return 0;
2345}
2346
2347
2348/* ==================== initialization and cleanup routines ============ */
2349
2350static int
2351vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64)
2352{
2353 int err;
2354 unsigned long mmio_start, mmio_len;
2355 struct pci_dev *pdev = adapter->pdev;
2356
2357 err = pci_enable_device(pdev);
2358 if (err) {
204a6e65 2359 dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err);
d1a890fa
SB		 2360 return err;
2361 }
2362
2363 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
2364 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
204a6e65
SH		 2365 dev_err(&pdev->dev,
2366 "pci_set_consistent_dma_mask failed\n");
d1a890fa
SB		 2367 err = -EIO;
2368 goto err_set_mask;
2369 }
2370 *dma64 = true;
2371 } else {
2372 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
204a6e65
SH		 2373 dev_err(&pdev->dev,
2374 "pci_set_dma_mask failed\n");
d1a890fa
SB		 2375 err = -EIO;
2376 goto err_set_mask;
2377 }
2378 *dma64 = false;
2379 }
2380
2381 err = pci_request_selected_regions(pdev, (1 << 2) - 1,
2382 vmxnet3_driver_name);
2383 if (err) {
204a6e65
SH		 2384 dev_err(&pdev->dev,
2385 "Failed to request region for adapter: error %d\n", err);
d1a890fa
SB		 2386 goto err_set_mask;
2387 }
2388
2389 pci_set_master(pdev);
2390
2391 mmio_start = pci_resource_start(pdev, 0);
2392 mmio_len = pci_resource_len(pdev, 0);
2393 adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
2394 if (!adapter->hw_addr0) {
204a6e65 2395 dev_err(&pdev->dev, "Failed to map bar0\n");
d1a890fa
SB		 2396 err = -EIO;
2397 goto err_ioremap;
2398 }
2399
2400 mmio_start = pci_resource_start(pdev, 1);
2401 mmio_len = pci_resource_len(pdev, 1);
2402 adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
2403 if (!adapter->hw_addr1) {
204a6e65 2404 dev_err(&pdev->dev, "Failed to map bar1\n");
d1a890fa
SB		 2405 err = -EIO;
2406 goto err_bar1;
2407 }
2408 return 0;
2409
2410err_bar1:
2411 iounmap(adapter->hw_addr0);
2412err_ioremap:
2413 pci_release_selected_regions(pdev, (1 << 2) - 1);
2414err_set_mask:
2415 pci_disable_device(pdev);
2416 return err;
2417}
2418
2419
2420static void
2421vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
2422{
2423 BUG_ON(!adapter->pdev);
2424
2425 iounmap(adapter->hw_addr0);
2426 iounmap(adapter->hw_addr1);
2427 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
2428 pci_disable_device(adapter->pdev);
2429}
2430
2431
2432static void
2433vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
2434{
09c5088e
SB		 2435 size_t sz, i, ring0_size, ring1_size, comp_size;
2436 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[0];
2437
d1a890fa
SB		 2438
2439 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
2440 VMXNET3_MAX_ETH_HDR_SIZE) {
2441 adapter->skb_buf_size = adapter->netdev->mtu +
2442 VMXNET3_MAX_ETH_HDR_SIZE;
2443 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
2444 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
2445
2446 adapter->rx_buf_per_pkt = 1;
2447 } else {
2448 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
2449 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
2450 VMXNET3_MAX_ETH_HDR_SIZE;
2451 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
2452 }
2453
2454 /*
2455 * for simplicity, force the ring0 size to be a multiple of
2456 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
2457 */
2458 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
09c5088e
SB		 2459 ring0_size = adapter->rx_queue[0].rx_ring[0].size;
2460 ring0_size = (ring0_size + sz - 1) / sz * sz;
a53255d3 2461 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
09c5088e
SB		 2462 sz * sz);
2463 ring1_size = adapter->rx_queue[0].rx_ring[1].size;
2464 comp_size = ring0_size + ring1_size;
2465
2466 for (i = 0; i < adapter->num_rx_queues; i++) {
2467 rq = &adapter->rx_queue[i];
2468 rq->rx_ring[0].size = ring0_size;
2469 rq->rx_ring[1].size = ring1_size;
2470 rq->comp_ring.size = comp_size;
2471 }
d1a890fa
SB		 2472}
2473
2474
2475int
2476vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
2477 u32 rx_ring_size, u32 rx_ring2_size)
2478{
09c5088e
SB		 2479 int err = 0, i;
2480
2481 for (i = 0; i < adapter->num_tx_queues; i++) {
2482 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2483 tq->tx_ring.size = tx_ring_size;
2484 tq->data_ring.size = tx_ring_size;
2485 tq->comp_ring.size = tx_ring_size;
2486 tq->shared = &adapter->tqd_start[i].ctrl;
2487 tq->stopped = true;
2488 tq->adapter = adapter;
2489 tq->qid = i;
2490 err = vmxnet3_tq_create(tq, adapter);
2491 /*
2492 * Too late to change num_tx_queues. We cannot do away with
2493 * lesser number of queues than what we asked for
2494 */
2495 if (err)
2496 goto queue_err;
2497 }
d1a890fa 2498
09c5088e
SB		 2499 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
2500 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
d1a890fa 2501 vmxnet3_adjust_rx_ring_size(adapter);
09c5088e
SB		 2502 for (i = 0; i < adapter->num_rx_queues; i++) {
2503 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2504 /* qid and qid2 for rx queues will be assigned later when num
2505 * of rx queues is finalized after allocating intrs */
2506 rq->shared = &adapter->rqd_start[i].ctrl;
2507 rq->adapter = adapter;
2508 err = vmxnet3_rq_create(rq, adapter);
2509 if (err) {
2510 if (i == 0) {
204a6e65
SH		 2511 netdev_err(adapter->netdev,
2512 "Could not allocate any rx queues. "
2513 "Aborting.\n");
09c5088e
SB		 2514 goto queue_err;
2515 } else {
204a6e65
SH		 2516 netdev_info(adapter->netdev,
2517 "Number of rx queues changed "
2518 "to : %d.\n", i);
09c5088e
SB		 2519 adapter->num_rx_queues = i;
2520 err = 0;
2521 break;
2522 }
2523 }
2524 }
2525 return err;
2526queue_err:
2527 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2528 return err;
2529}
2530
2531static int
2532vmxnet3_open(struct net_device *netdev)
2533{
2534 struct vmxnet3_adapter *adapter;
09c5088e 2535 int err, i;
d1a890fa
SB		 2536
2537 adapter = netdev_priv(netdev);
2538
09c5088e
SB		 2539 for (i = 0; i < adapter->num_tx_queues; i++)
2540 spin_lock_init(&adapter->tx_queue[i].tx_lock);
d1a890fa
SB		 2541
2542 err = vmxnet3_create_queues(adapter, VMXNET3_DEF_TX_RING_SIZE,
2543 VMXNET3_DEF_RX_RING_SIZE,
2544 VMXNET3_DEF_RX_RING_SIZE);
2545 if (err)
2546 goto queue_err;
2547
2548 err = vmxnet3_activate_dev(adapter);
2549 if (err)
2550 goto activate_err;
2551
2552 return 0;
2553
2554activate_err:
09c5088e
SB		 2555 vmxnet3_rq_destroy_all(adapter);
2556 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2557queue_err:
2558 return err;
2559}
2560
2561
2562static int
2563vmxnet3_close(struct net_device *netdev)
2564{
2565 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2566
2567 /*
2568 * Reset_work may be in the middle of resetting the device, wait for its
2569 * completion.
2570 */
2571 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2572 msleep(1);
2573
2574 vmxnet3_quiesce_dev(adapter);
2575
09c5088e
SB		 2576 vmxnet3_rq_destroy_all(adapter);
2577 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2578
2579 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2580
2581
2582 return 0;
2583}
2584
2585
2586void
2587vmxnet3_force_close(struct vmxnet3_adapter *adapter)
2588{
09c5088e
SB		 2589 int i;
2590
d1a890fa
SB		 2591 /*
2592 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
2593 * vmxnet3_close() will deadlock.
2594 */
2595 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
2596
2597 /* we need to enable NAPI, otherwise dev_close will deadlock */
09c5088e
SB		 2598 for (i = 0; i < adapter->num_rx_queues; i++)
2599 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2600 dev_close(adapter->netdev);
2601}
2602
2603
2604static int
2605vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
2606{
2607 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2608 int err = 0;
2609
2610 if (new_mtu < VMXNET3_MIN_MTU || new_mtu > VMXNET3_MAX_MTU)
2611 return -EINVAL;
2612
d1a890fa
SB		 2613 netdev->mtu = new_mtu;
2614
2615 /*
2616 * Reset_work may be in the middle of resetting the device, wait for its
2617 * completion.
2618 */
2619 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2620 msleep(1);
2621
2622 if (netif_running(netdev)) {
2623 vmxnet3_quiesce_dev(adapter);
2624 vmxnet3_reset_dev(adapter);
2625
2626 /* we need to re-create the rx queue based on the new mtu */
09c5088e 2627 vmxnet3_rq_destroy_all(adapter);
d1a890fa 2628 vmxnet3_adjust_rx_ring_size(adapter);
09c5088e 2629 err = vmxnet3_rq_create_all(adapter);
d1a890fa 2630 if (err) {
204a6e65
SH		 2631 netdev_err(netdev,
2632 "failed to re-create rx queues, "
2633 " error %d. Closing it.\n", err);
d1a890fa
SB		 2634 goto out;
2635 }
2636
2637 err = vmxnet3_activate_dev(adapter);
2638 if (err) {
204a6e65
SH		 2639 netdev_err(netdev,
2640 "failed to re-activate, error %d. "
2641 "Closing it\n", err);
d1a890fa
SB		 2642 goto out;
2643 }
2644 }
2645
2646out:
2647 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2648 if (err)
2649 vmxnet3_force_close(adapter);
2650
2651 return err;
2652}
2653
2654
2655static void
2656vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
2657{
2658 struct net_device *netdev = adapter->netdev;
2659
a0d2730c
MM		 2660 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
2661 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_TX |
72e85c45
JG		 2662 NETIF_F_HW_VLAN_RX | NETIF_F_TSO | NETIF_F_TSO6 |
2663 NETIF_F_LRO;
a0d2730c 2664 if (dma64)
ebbf9295 2665 netdev->hw_features |= NETIF_F_HIGHDMA;
72e85c45
JG		 2666 netdev->vlan_features = netdev->hw_features &
2667 ~(NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
2668 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_FILTER;
d1a890fa
SB		 2669}
2670
2671
2672static void
2673vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2674{
2675 u32 tmp;
2676
2677 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
2678 *(u32 *)mac = tmp;
2679
2680 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
2681 mac[4] = tmp & 0xff;
2682 mac[5] = (tmp >> 8) & 0xff;
2683}
2684
09c5088e
SB		 2685#ifdef CONFIG_PCI_MSI
2686
2687/*
2688 * Enable MSIx vectors.
2689 * Returns :
2690 * 0 on successful enabling of required vectors,
25985edc 2691 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
09c5088e
SB		 2692 * could be enabled.
2693 * number of vectors which can be enabled otherwise (this number is smaller
2694 * than VMXNET3_LINUX_MIN_MSIX_VECT)
2695 */
2696
2697static int
2698vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter,
2699 int vectors)
2700{
2701 int err = 0, vector_threshold;
2702 vector_threshold = VMXNET3_LINUX_MIN_MSIX_VECT;
2703
2704 while (vectors >= vector_threshold) {
2705 err = pci_enable_msix(adapter->pdev, adapter->intr.msix_entries,
2706 vectors);
2707 if (!err) {
2708 adapter->intr.num_intrs = vectors;
2709 return 0;
2710 } else if (err < 0) {
4bad25fa 2711 dev_err(&adapter->netdev->dev,
4c1dc80a 2712 "Failed to enable MSI-X, error: %d\n", err);
09c5088e
SB		 2713 vectors = 0;
2714 } else if (err < vector_threshold) {
2715 break;
2716 } else {
2717 /* If fails to enable required number of MSI-x vectors
7e96fbf2 2718 * try enabling minimum number of vectors required.
09c5088e 2719 */
4bad25fa
SH		 2720 dev_err(&adapter->netdev->dev,
2721 "Failed to enable %d MSI-X, trying %d instead\n",
4c1dc80a 2722 vectors, vector_threshold);
09c5088e 2723 vectors = vector_threshold;
09c5088e
SB		 2724 }
2725 }
2726
4bad25fa
SH		 2727 dev_info(&adapter->pdev->dev,
2728 "Number of MSI-X interrupts which can be allocated "
2729 "is lower than min threshold required.\n");
09c5088e
SB		 2730 return err;
2731}
2732
2733
2734#endif /* CONFIG_PCI_MSI */
d1a890fa
SB		 2735
2736static void
2737vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
2738{
2739 u32 cfg;
e328d410 2740 unsigned long flags;
d1a890fa
SB		 2741
2742 /* intr settings */
e328d410 2743 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2744 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2745 VMXNET3_CMD_GET_CONF_INTR);
2746 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
e328d410 2747 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2748 adapter->intr.type = cfg & 0x3;
2749 adapter->intr.mask_mode = (cfg >> 2) & 0x3;
2750
2751 if (adapter->intr.type == VMXNET3_IT_AUTO) {
0bdc0d70
SB		 2752 adapter->intr.type = VMXNET3_IT_MSIX;
2753 }
d1a890fa 2754
8f7e524c 2755#ifdef CONFIG_PCI_MSI
0bdc0d70 2756 if (adapter->intr.type == VMXNET3_IT_MSIX) {
09c5088e
SB		 2757 int vector, err = 0;
2758
2759 adapter->intr.num_intrs = (adapter->share_intr ==
2760 VMXNET3_INTR_TXSHARE) ? 1 :
2761 adapter->num_tx_queues;
2762 adapter->intr.num_intrs += (adapter->share_intr ==
2763 VMXNET3_INTR_BUDDYSHARE) ? 0 :
2764 adapter->num_rx_queues;
2765 adapter->intr.num_intrs += 1; /* for link event */
2766
2767 adapter->intr.num_intrs = (adapter->intr.num_intrs >
2768 VMXNET3_LINUX_MIN_MSIX_VECT
2769 ? adapter->intr.num_intrs :
2770 VMXNET3_LINUX_MIN_MSIX_VECT);
2771
2772 for (vector = 0; vector < adapter->intr.num_intrs; vector++)
2773 adapter->intr.msix_entries[vector].entry = vector;
2774
2775 err = vmxnet3_acquire_msix_vectors(adapter,
2776 adapter->intr.num_intrs);
2777 /* If we cannot allocate one MSIx vector per queue
2778 * then limit the number of rx queues to 1
2779 */
2780 if (err == VMXNET3_LINUX_MIN_MSIX_VECT) {
2781 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
7e96fbf2 2782 || adapter->num_rx_queues != 1) {
09c5088e 2783 adapter->share_intr = VMXNET3_INTR_TXSHARE;
204a6e65
SH		 2784 netdev_err(adapter->netdev,
2785 "Number of rx queues : 1\n");
09c5088e
SB		 2786 adapter->num_rx_queues = 1;
2787 adapter->intr.num_intrs =
2788 VMXNET3_LINUX_MIN_MSIX_VECT;
2789 }
d1a890fa
SB		 2790 return;
2791 }
09c5088e
SB		 2792 if (!err)
2793 return;
2794
2795 /* If we cannot allocate MSIx vectors use only one rx queue */
4bad25fa
SH		 2796 dev_info(&adapter->pdev->dev,
2797 "Failed to enable MSI-X, error %d. "
2798 "Limiting #rx queues to 1, try MSI.\n", err);
09c5088e 2799
0bdc0d70
SB		 2800 adapter->intr.type = VMXNET3_IT_MSI;
2801 }
d1a890fa 2802
0bdc0d70
SB		 2803 if (adapter->intr.type == VMXNET3_IT_MSI) {
2804 int err;
d1a890fa
SB		 2805 err = pci_enable_msi(adapter->pdev);
2806 if (!err) {
09c5088e 2807 adapter->num_rx_queues = 1;
d1a890fa 2808 adapter->intr.num_intrs = 1;
d1a890fa
SB		 2809 return;
2810 }
2811 }
0bdc0d70 2812#endif /* CONFIG_PCI_MSI */
d1a890fa 2813
09c5088e 2814 adapter->num_rx_queues = 1;
204a6e65
SH		 2815 dev_info(&adapter->netdev->dev,
2816 "Using INTx interrupt, #Rx queues: 1.\n");
d1a890fa
SB		 2817 adapter->intr.type = VMXNET3_IT_INTX;
2818
2819 /* INT-X related setting */
2820 adapter->intr.num_intrs = 1;
2821}
2822
2823
2824static void
2825vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
2826{
2827 if (adapter->intr.type == VMXNET3_IT_MSIX)
2828 pci_disable_msix(adapter->pdev);
2829 else if (adapter->intr.type == VMXNET3_IT_MSI)
2830 pci_disable_msi(adapter->pdev);
2831 else
2832 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
2833}
2834
2835
2836static void
2837vmxnet3_tx_timeout(struct net_device *netdev)
2838{
2839 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2840 adapter->tx_timeout_count++;
2841
204a6e65 2842 netdev_err(adapter->netdev, "tx hang\n");
d1a890fa 2843 schedule_work(&adapter->work);
09c5088e 2844 netif_wake_queue(adapter->netdev);
d1a890fa
SB		 2845}
2846
2847
2848static void
2849vmxnet3_reset_work(struct work_struct *data)
2850{
2851 struct vmxnet3_adapter *adapter;
2852
2853 adapter = container_of(data, struct vmxnet3_adapter, work);
2854
2855 /* if another thread is resetting the device, no need to proceed */
2856 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2857 return;
2858
2859 /* if the device is closed, we must leave it alone */
d9a5f210 2860 rtnl_lock();
d1a890fa 2861 if (netif_running(adapter->netdev)) {
204a6e65 2862 netdev_notice(adapter->netdev, "resetting\n");
d1a890fa
SB		 2863 vmxnet3_quiesce_dev(adapter);
2864 vmxnet3_reset_dev(adapter);
2865 vmxnet3_activate_dev(adapter);
2866 } else {
204a6e65 2867 netdev_info(adapter->netdev, "already closed\n");
d1a890fa 2868 }
d9a5f210 2869 rtnl_unlock();
d1a890fa
SB		 2870
2871 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2872}
2873
2874
3a4751a3 2875static int
d1a890fa
SB		 2876vmxnet3_probe_device(struct pci_dev *pdev,
2877 const struct pci_device_id *id)
2878{
2879 static const struct net_device_ops vmxnet3_netdev_ops = {
2880 .ndo_open = vmxnet3_open,
2881 .ndo_stop = vmxnet3_close,
2882 .ndo_start_xmit = vmxnet3_xmit_frame,
2883 .ndo_set_mac_address = vmxnet3_set_mac_addr,
2884 .ndo_change_mtu = vmxnet3_change_mtu,
a0d2730c 2885 .ndo_set_features = vmxnet3_set_features,
95305f6c 2886 .ndo_get_stats64 = vmxnet3_get_stats64,
d1a890fa 2887 .ndo_tx_timeout = vmxnet3_tx_timeout,
afc4b13d 2888 .ndo_set_rx_mode = vmxnet3_set_mc,
d1a890fa
SB		 2889 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
2890 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
2891#ifdef CONFIG_NET_POLL_CONTROLLER
2892 .ndo_poll_controller = vmxnet3_netpoll,
2893#endif
2894 };
2895 int err;
2896 bool dma64 = false; /* stupid gcc */
2897 u32 ver;
2898 struct net_device *netdev;
2899 struct vmxnet3_adapter *adapter;
2900 u8 mac[ETH_ALEN];
09c5088e
SB		 2901 int size;
2902 int num_tx_queues;
2903 int num_rx_queues;
2904
e154b639
SB		 2905 if (!pci_msi_enabled())
2906 enable_mq = 0;
2907
09c5088e
SB		 2908#ifdef VMXNET3_RSS
2909 if (enable_mq)
2910 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
2911 (int)num_online_cpus());
2912 else
2913#endif
2914 num_rx_queues = 1;
eebb02b1 2915 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
09c5088e
SB		 2916
2917 if (enable_mq)
2918 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
2919 (int)num_online_cpus());
2920 else
2921 num_tx_queues = 1;
2922
eebb02b1 2923 num_tx_queues = rounddown_pow_of_two(num_tx_queues);
09c5088e
SB		 2924 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
2925 max(num_tx_queues, num_rx_queues));
204a6e65
SH		 2926 dev_info(&pdev->dev,
2927 "# of Tx queues : %d, # of Rx queues : %d\n",
2928 num_tx_queues, num_rx_queues);
d1a890fa 2929
41de8d4c 2930 if (!netdev)
d1a890fa 2931 return -ENOMEM;
d1a890fa
SB		 2932
2933 pci_set_drvdata(pdev, netdev);
2934 adapter = netdev_priv(netdev);
2935 adapter->netdev = netdev;
2936 adapter->pdev = pdev;
2937
83d0feff 2938 spin_lock_init(&adapter->cmd_lock);
d1a890fa 2939 adapter->shared = pci_alloc_consistent(adapter->pdev,
96800ee7 2940 sizeof(struct Vmxnet3_DriverShared),
2941 &adapter->shared_pa);
d1a890fa 2942 if (!adapter->shared) {
204a6e65 2943 dev_err(&pdev->dev, "Failed to allocate memory\n");
d1a890fa
SB		 2944 err = -ENOMEM;
2945 goto err_alloc_shared;
2946 }
2947
09c5088e
SB		 2948 adapter->num_rx_queues = num_rx_queues;
2949 adapter->num_tx_queues = num_tx_queues;
2950
2951 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
2952 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
2953 adapter->tqd_start = pci_alloc_consistent(adapter->pdev, size,
96800ee7 2954 &adapter->queue_desc_pa);
d1a890fa
SB		 2955
2956 if (!adapter->tqd_start) {
204a6e65 2957 dev_err(&pdev->dev, "Failed to allocate memory\n");
d1a890fa
SB		 2958 err = -ENOMEM;
2959 goto err_alloc_queue_desc;
2960 }
09c5088e 2961 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
96800ee7 2962 adapter->num_tx_queues);
d1a890fa
SB		 2963
2964 adapter->pm_conf = kmalloc(sizeof(struct Vmxnet3_PMConf), GFP_KERNEL);
2965 if (adapter->pm_conf == NULL) {
d1a890fa
SB		 2966 err = -ENOMEM;
2967 goto err_alloc_pm;
2968 }
2969
09c5088e
SB		 2970#ifdef VMXNET3_RSS
2971
2972 adapter->rss_conf = kmalloc(sizeof(struct UPT1_RSSConf), GFP_KERNEL);
2973 if (adapter->rss_conf == NULL) {
09c5088e
SB		 2974 err = -ENOMEM;
2975 goto err_alloc_rss;
2976 }
2977#endif /* VMXNET3_RSS */
2978
d1a890fa
SB		 2979 err = vmxnet3_alloc_pci_resources(adapter, &dma64);
2980 if (err < 0)
2981 goto err_alloc_pci;
2982
2983 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
2984 if (ver & 1) {
2985 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_VRRS, 1);
2986 } else {
204a6e65
SH		 2987 dev_err(&pdev->dev,
2988 "Incompatible h/w version (0x%x) for adapter\n", ver);
d1a890fa
SB		 2989 err = -EBUSY;
2990 goto err_ver;
2991 }
2992
2993 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
2994 if (ver & 1) {
2995 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
2996 } else {
204a6e65
SH		 2997 dev_err(&pdev->dev,
2998 "Incompatible upt version (0x%x) for adapter\n", ver);
d1a890fa
SB		 2999 err = -EBUSY;
3000 goto err_ver;
3001 }
3002
e101e7dd 3003 SET_NETDEV_DEV(netdev, &pdev->dev);
d1a890fa
SB		 3004 vmxnet3_declare_features(adapter, dma64);
3005
96800ee7 3006 adapter->share_intr = irq_share_mode;
09c5088e
SB		 3007 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE &&
3008 adapter->num_tx_queues != adapter->num_rx_queues)
3009 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
3010
d1a890fa
SB		 3011 vmxnet3_alloc_intr_resources(adapter);
3012
09c5088e
SB		 3013#ifdef VMXNET3_RSS
3014 if (adapter->num_rx_queues > 1 &&
3015 adapter->intr.type == VMXNET3_IT_MSIX) {
3016 adapter->rss = true;
204a6e65 3017 dev_dbg(&pdev->dev, "RSS is enabled.\n");
09c5088e
SB		 3018 } else {
3019 adapter->rss = false;
3020 }
3021#endif
3022
d1a890fa
SB		 3023 vmxnet3_read_mac_addr(adapter, mac);
3024 memcpy(netdev->dev_addr, mac, netdev->addr_len);
3025
3026 netdev->netdev_ops = &vmxnet3_netdev_ops;
d1a890fa 3027 vmxnet3_set_ethtool_ops(netdev);
09c5088e 3028 netdev->watchdog_timeo = 5 * HZ;
d1a890fa
SB		 3029
3030 INIT_WORK(&adapter->work, vmxnet3_reset_work);
e3bc4ffb 3031 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
d1a890fa 3032
09c5088e
SB		 3033 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3034 int i;
3035 for (i = 0; i < adapter->num_rx_queues; i++) {
3036 netif_napi_add(adapter->netdev,
3037 &adapter->rx_queue[i].napi,
3038 vmxnet3_poll_rx_only, 64);
3039 }
3040 } else {
3041 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
3042 vmxnet3_poll, 64);
3043 }
3044
3045 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
3046 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
3047
d1a890fa
SB		 3048 err = register_netdev(netdev);
3049
3050 if (err) {
204a6e65 3051 dev_err(&pdev->dev, "Failed to register adapter\n");
d1a890fa
SB		 3052 goto err_register;
3053 }
3054
4a1745fc 3055 vmxnet3_check_link(adapter, false);
d1a890fa
SB		 3056 return 0;
3057
3058err_register:
3059 vmxnet3_free_intr_resources(adapter);
3060err_ver:
3061 vmxnet3_free_pci_resources(adapter);
3062err_alloc_pci:
09c5088e
SB		 3063#ifdef VMXNET3_RSS
3064 kfree(adapter->rss_conf);
3065err_alloc_rss:
3066#endif
d1a890fa
SB		 3067 kfree(adapter->pm_conf);
3068err_alloc_pm:
09c5088e
SB		 3069 pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
3070 adapter->queue_desc_pa);
d1a890fa
SB		 3071err_alloc_queue_desc:
3072 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
3073 adapter->shared, adapter->shared_pa);
3074err_alloc_shared:
3075 pci_set_drvdata(pdev, NULL);
3076 free_netdev(netdev);
3077 return err;
3078}
3079
3080
3a4751a3 3081static void
d1a890fa
SB		 3082vmxnet3_remove_device(struct pci_dev *pdev)
3083{
3084 struct net_device *netdev = pci_get_drvdata(pdev);
3085 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
09c5088e
SB		 3086 int size = 0;
3087 int num_rx_queues;
3088
3089#ifdef VMXNET3_RSS
3090 if (enable_mq)
3091 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3092 (int)num_online_cpus());
3093 else
3094#endif
3095 num_rx_queues = 1;
eebb02b1 3096 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
d1a890fa 3097
23f333a2 3098 cancel_work_sync(&adapter->work);
d1a890fa
SB		 3099
3100 unregister_netdev(netdev);
3101
3102 vmxnet3_free_intr_resources(adapter);
3103 vmxnet3_free_pci_resources(adapter);
09c5088e
SB		 3104#ifdef VMXNET3_RSS
3105 kfree(adapter->rss_conf);
3106#endif
d1a890fa 3107 kfree(adapter->pm_conf);
09c5088e
SB		 3108
3109 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3110 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
3111 pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
3112 adapter->queue_desc_pa);
d1a890fa
SB		 3113 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
3114 adapter->shared, adapter->shared_pa);
3115 free_netdev(netdev);
3116}
3117
3118
3119#ifdef CONFIG_PM
3120
3121static int
3122vmxnet3_suspend(struct device *device)
3123{
3124 struct pci_dev *pdev = to_pci_dev(device);
3125 struct net_device *netdev = pci_get_drvdata(pdev);
3126 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3127 struct Vmxnet3_PMConf *pmConf;
3128 struct ethhdr *ehdr;
3129 struct arphdr *ahdr;
3130 u8 *arpreq;
3131 struct in_device *in_dev;
3132 struct in_ifaddr *ifa;
83d0feff 3133 unsigned long flags;
d1a890fa
SB		 3134 int i = 0;
3135
3136 if (!netif_running(netdev))
3137 return 0;
3138
51956cd6
SB		 3139 for (i = 0; i < adapter->num_rx_queues; i++)
3140 napi_disable(&adapter->rx_queue[i].napi);
3141
d1a890fa
SB		 3142 vmxnet3_disable_all_intrs(adapter);
3143 vmxnet3_free_irqs(adapter);
3144 vmxnet3_free_intr_resources(adapter);
3145
3146 netif_device_detach(netdev);
09c5088e 3147 netif_tx_stop_all_queues(netdev);
d1a890fa
SB		 3148
3149 /* Create wake-up filters. */
3150 pmConf = adapter->pm_conf;
3151 memset(pmConf, 0, sizeof(*pmConf));
3152
3153 if (adapter->wol & WAKE_UCAST) {
3154 pmConf->filters[i].patternSize = ETH_ALEN;
3155 pmConf->filters[i].maskSize = 1;
3156 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
3157 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
3158
3843e515 3159 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
d1a890fa
SB		 3160 i++;
3161 }
3162
3163 if (adapter->wol & WAKE_ARP) {
3164 in_dev = in_dev_get(netdev);
3165 if (!in_dev)
3166 goto skip_arp;
3167
3168 ifa = (struct in_ifaddr *)in_dev->ifa_list;
3169 if (!ifa)
3170 goto skip_arp;
3171
3172 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
3173 sizeof(struct arphdr) + /* ARP header */
3174 2 * ETH_ALEN + /* 2 Ethernet addresses*/
3175 2 * sizeof(u32); /*2 IPv4 addresses */
3176 pmConf->filters[i].maskSize =
3177 (pmConf->filters[i].patternSize - 1) / 8 + 1;
3178
3179 /* ETH_P_ARP in Ethernet header. */
3180 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
3181 ehdr->h_proto = htons(ETH_P_ARP);
3182
3183 /* ARPOP_REQUEST in ARP header. */
3184 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
3185 ahdr->ar_op = htons(ARPOP_REQUEST);
3186 arpreq = (u8 *)(ahdr + 1);
3187
3188 /* The Unicast IPv4 address in 'tip' field. */
3189 arpreq += 2 * ETH_ALEN + sizeof(u32);
3190 *(u32 *)arpreq = ifa->ifa_address;
3191
3192 /* The mask for the relevant bits. */
3193 pmConf->filters[i].mask[0] = 0x00;
3194 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
3195 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
3196 pmConf->filters[i].mask[3] = 0x00;
3197 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
3198 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
3199 in_dev_put(in_dev);
3200
3843e515 3201 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
d1a890fa
SB		 3202 i++;
3203 }
3204
3205skip_arp:
3206 if (adapter->wol & WAKE_MAGIC)
3843e515 3207 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
d1a890fa
SB		 3208
3209 pmConf->numFilters = i;
3210
115924b6
SB		 3211 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3212 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3213 *pmConf));
3214 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
3215 pmConf));
d1a890fa 3216
83d0feff 3217 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 3218 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3219 VMXNET3_CMD_UPDATE_PMCFG);
83d0feff 3220 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 3221
3222 pci_save_state(pdev);
3223 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
3224 adapter->wol);
3225 pci_disable_device(pdev);
3226 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
3227
3228 return 0;
3229}
3230
3231
3232static int
3233vmxnet3_resume(struct device *device)
3234{
51956cd6 3235 int err, i = 0;
83d0feff 3236 unsigned long flags;
d1a890fa
SB		 3237 struct pci_dev *pdev = to_pci_dev(device);
3238 struct net_device *netdev = pci_get_drvdata(pdev);
3239 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3240 struct Vmxnet3_PMConf *pmConf;
3241
3242 if (!netif_running(netdev))
3243 return 0;
3244
3245 /* Destroy wake-up filters. */
3246 pmConf = adapter->pm_conf;
3247 memset(pmConf, 0, sizeof(*pmConf));
3248
115924b6
SB		 3249 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3250 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3251 *pmConf));
0561cf3d 3252 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
115924b6 3253 pmConf));
d1a890fa
SB		 3254
3255 netif_device_attach(netdev);
3256 pci_set_power_state(pdev, PCI_D0);
3257 pci_restore_state(pdev);
3258 err = pci_enable_device_mem(pdev);
3259 if (err != 0)
3260 return err;
3261
3262 pci_enable_wake(pdev, PCI_D0, 0);
3263
83d0feff 3264 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 3265 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3266 VMXNET3_CMD_UPDATE_PMCFG);
83d0feff 3267 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 3268 vmxnet3_alloc_intr_resources(adapter);
3269 vmxnet3_request_irqs(adapter);
51956cd6
SB		 3270 for (i = 0; i < adapter->num_rx_queues; i++)
3271 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 3272 vmxnet3_enable_all_intrs(adapter);
3273
3274 return 0;
3275}
3276
47145210 3277static const struct dev_pm_ops vmxnet3_pm_ops = {
d1a890fa
SB		 3278 .suspend = vmxnet3_suspend,
3279 .resume = vmxnet3_resume,
3280};
3281#endif
3282
3283static struct pci_driver vmxnet3_driver = {
3284 .name = vmxnet3_driver_name,
3285 .id_table = vmxnet3_pciid_table,
3286 .probe = vmxnet3_probe_device,
3a4751a3 3287 .remove = vmxnet3_remove_device,
d1a890fa
SB		 3288#ifdef CONFIG_PM
3289 .driver.pm = &vmxnet3_pm_ops,
3290#endif
3291};
3292
3293
3294static int __init
3295vmxnet3_init_module(void)
3296{
204a6e65 3297 pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC,
d1a890fa
SB		 3298 VMXNET3_DRIVER_VERSION_REPORT);
3299 return pci_register_driver(&vmxnet3_driver);
3300}
3301
3302module_init(vmxnet3_init_module);
3303
3304
3305static void
3306vmxnet3_exit_module(void)
3307{
3308 pci_unregister_driver(&vmxnet3_driver);
3309}
3310
3311module_exit(vmxnet3_exit_module);
3312
3313MODULE_AUTHOR("VMware, Inc.");
3314MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
3315MODULE_LICENSE("GPL v2");
3316MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);
kernel source for telekom puls (alcatel/mediatek)