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vmxnet3: set netdev parant device before calling netdev_info
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / vmxnet3 / vmxnet3_drv.c
CommitLineData
d1a890fa
SB		 1/*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
4 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
23 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
24 *
25 */
26
b038b040
SR		 27#include <net/ip6_checksum.h>
28
d1a890fa
SB		 29#include "vmxnet3_int.h"
30
31char vmxnet3_driver_name[] = "vmxnet3";
32#define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
33
d1a890fa
SB		 34/*
35 * PCI Device ID Table
36 * Last entry must be all 0s
37 */
a3aa1884 38static DEFINE_PCI_DEVICE_TABLE(vmxnet3_pciid_table) = {
d1a890fa
SB		 39 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
40 {0}
41};
42
43MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
44
45static atomic_t devices_found;
46
09c5088e
SB		 47#define VMXNET3_MAX_DEVICES 10
48static int enable_mq = 1;
49static int irq_share_mode;
d1a890fa 50
f9f25026
SB		 51static void
52vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
53
d1a890fa
SB		 54/*
55 * Enable/Disable the given intr
56 */
57static void
58vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
59{
60 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
61}
62
63
64static void
65vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
66{
67 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
68}
69
70
71/*
72 * Enable/Disable all intrs used by the device
73 */
74static void
75vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
76{
77 int i;
78
79 for (i = 0; i < adapter->intr.num_intrs; i++)
80 vmxnet3_enable_intr(adapter, i);
6929fe8a
RZ		 81 adapter->shared->devRead.intrConf.intrCtrl &=
82 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 83}
84
85
86static void
87vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
88{
89 int i;
90
6929fe8a
RZ		 91 adapter->shared->devRead.intrConf.intrCtrl |=
92 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 93 for (i = 0; i < adapter->intr.num_intrs; i++)
94 vmxnet3_disable_intr(adapter, i);
95}
96
97
98static void
99vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
100{
101 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
102}
103
104
105static bool
106vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
107{
09c5088e 108 return tq->stopped;
d1a890fa
SB		 109}
110
111
112static void
113vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
114{
115 tq->stopped = false;
09c5088e 116 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
d1a890fa
SB		 117}
118
119
120static void
121vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
122{
123 tq->stopped = false;
09c5088e 124 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
d1a890fa
SB		 125}
126
127
128static void
129vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
130{
131 tq->stopped = true;
132 tq->num_stop++;
09c5088e 133 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
d1a890fa
SB		 134}
135
136
137/*
138 * Check the link state. This may start or stop the tx queue.
139 */
140static void
4a1745fc 141vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
d1a890fa
SB		 142{
143 u32 ret;
09c5088e 144 int i;
83d0feff 145 unsigned long flags;
d1a890fa 146
83d0feff 147 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 148 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
149 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
83d0feff
SB		 150 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
151
d1a890fa
SB		 152 adapter->link_speed = ret >> 16;
153 if (ret & 1) { /* Link is up. */
154 printk(KERN_INFO "%s: NIC Link is Up %d Mbps\n",
155 adapter->netdev->name, adapter->link_speed);
156 if (!netif_carrier_ok(adapter->netdev))
157 netif_carrier_on(adapter->netdev);
158
09c5088e
SB		 159 if (affectTxQueue) {
160 for (i = 0; i < adapter->num_tx_queues; i++)
161 vmxnet3_tq_start(&adapter->tx_queue[i],
162 adapter);
163 }
d1a890fa
SB		 164 } else {
165 printk(KERN_INFO "%s: NIC Link is Down\n",
166 adapter->netdev->name);
167 if (netif_carrier_ok(adapter->netdev))
168 netif_carrier_off(adapter->netdev);
169
09c5088e
SB		 170 if (affectTxQueue) {
171 for (i = 0; i < adapter->num_tx_queues; i++)
172 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
173 }
d1a890fa
SB		 174 }
175}
176
d1a890fa
SB		 177static void
178vmxnet3_process_events(struct vmxnet3_adapter *adapter)
179{
09c5088e 180 int i;
e328d410 181 unsigned long flags;
115924b6 182 u32 events = le32_to_cpu(adapter->shared->ecr);
d1a890fa
SB		 183 if (!events)
184 return;
185
186 vmxnet3_ack_events(adapter, events);
187
188 /* Check if link state has changed */
189 if (events & VMXNET3_ECR_LINK)
4a1745fc 190 vmxnet3_check_link(adapter, true);
d1a890fa
SB		 191
192 /* Check if there is an error on xmit/recv queues */
193 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
e328d410 194 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 195 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
196 VMXNET3_CMD_GET_QUEUE_STATUS);
e328d410 197 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa 198
09c5088e
SB		 199 for (i = 0; i < adapter->num_tx_queues; i++)
200 if (adapter->tqd_start[i].status.stopped)
201 dev_err(&adapter->netdev->dev,
202 "%s: tq[%d] error 0x%x\n",
203 adapter->netdev->name, i, le32_to_cpu(
204 adapter->tqd_start[i].status.error));
205 for (i = 0; i < adapter->num_rx_queues; i++)
206 if (adapter->rqd_start[i].status.stopped)
207 dev_err(&adapter->netdev->dev,
208 "%s: rq[%d] error 0x%x\n",
209 adapter->netdev->name, i,
210 adapter->rqd_start[i].status.error);
d1a890fa
SB		 211
212 schedule_work(&adapter->work);
213 }
214}
215
115924b6
SB		 216#ifdef __BIG_ENDIAN_BITFIELD
217/*
218 * The device expects the bitfields in shared structures to be written in
219 * little endian. When CPU is big endian, the following routines are used to
220 * correctly read and write into ABI.
221 * The general technique used here is : double word bitfields are defined in
222 * opposite order for big endian architecture. Then before reading them in
223 * driver the complete double word is translated using le32_to_cpu. Similarly
224 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
225 * double words into required format.
226 * In order to avoid touching bits in shared structure more than once, temporary
227 * descriptors are used. These are passed as srcDesc to following functions.
228 */
229static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
230 struct Vmxnet3_RxDesc *dstDesc)
231{
232 u32 *src = (u32 *)srcDesc + 2;
233 u32 *dst = (u32 *)dstDesc + 2;
234 dstDesc->addr = le64_to_cpu(srcDesc->addr);
235 *dst = le32_to_cpu(*src);
236 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
237}
238
239static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
240 struct Vmxnet3_TxDesc *dstDesc)
241{
242 int i;
243 u32 *src = (u32 *)(srcDesc + 1);
244 u32 *dst = (u32 *)(dstDesc + 1);
245
246 /* Working backwards so that the gen bit is set at the end. */
247 for (i = 2; i > 0; i--) {
248 src--;
249 dst--;
250 *dst = cpu_to_le32(*src);
251 }
252}
253
254
255static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
256 struct Vmxnet3_RxCompDesc *dstDesc)
257{
258 int i = 0;
259 u32 *src = (u32 *)srcDesc;
260 u32 *dst = (u32 *)dstDesc;
261 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
262 *dst = le32_to_cpu(*src);
263 src++;
264 dst++;
265 }
266}
267
268
269/* Used to read bitfield values from double words. */
270static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
271{
272 u32 temp = le32_to_cpu(*bitfield);
273 u32 mask = ((1 << size) - 1) << pos;
274 temp &= mask;
275 temp >>= pos;
276 return temp;
277}
278
279
280
281#endif /* __BIG_ENDIAN_BITFIELD */
282
283#ifdef __BIG_ENDIAN_BITFIELD
284
285# define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
286 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
287 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
288# define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
289 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
290 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
291# define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
292 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
293 VMXNET3_TCD_GEN_SIZE)
294# define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
295 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
296# define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
297 (dstrcd) = (tmp); \
298 vmxnet3_RxCompToCPU((rcd), (tmp)); \
299 } while (0)
300# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
301 (dstrxd) = (tmp); \
302 vmxnet3_RxDescToCPU((rxd), (tmp)); \
303 } while (0)
304
305#else
306
307# define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
308# define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
309# define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
310# define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
311# define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
312# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
313
314#endif /* __BIG_ENDIAN_BITFIELD */
315
d1a890fa
SB		 316
317static void
318vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
319 struct pci_dev *pdev)
320{
321 if (tbi->map_type == VMXNET3_MAP_SINGLE)
322 pci_unmap_single(pdev, tbi->dma_addr, tbi->len,
323 PCI_DMA_TODEVICE);
324 else if (tbi->map_type == VMXNET3_MAP_PAGE)
325 pci_unmap_page(pdev, tbi->dma_addr, tbi->len,
326 PCI_DMA_TODEVICE);
327 else
328 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
329
330 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
331}
332
333
334static int
335vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
336 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
337{
338 struct sk_buff *skb;
339 int entries = 0;
340
341 /* no out of order completion */
342 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
115924b6 343 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
d1a890fa
SB		 344
345 skb = tq->buf_info[eop_idx].skb;
346 BUG_ON(skb == NULL);
347 tq->buf_info[eop_idx].skb = NULL;
348
349 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
350
351 while (tq->tx_ring.next2comp != eop_idx) {
352 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
353 pdev);
354
355 /* update next2comp w/o tx_lock. Since we are marking more,
356 * instead of less, tx ring entries avail, the worst case is
357 * that the tx routine incorrectly re-queues a pkt due to
358 * insufficient tx ring entries.
359 */
360 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
361 entries++;
362 }
363
364 dev_kfree_skb_any(skb);
365 return entries;
366}
367
368
369static int
370vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
371 struct vmxnet3_adapter *adapter)
372{
373 int completed = 0;
374 union Vmxnet3_GenericDesc *gdesc;
375
376 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
115924b6
SB		 377 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
378 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
379 &gdesc->tcd), tq, adapter->pdev,
380 adapter);
d1a890fa
SB		 381
382 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
383 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
384 }
385
386 if (completed) {
387 spin_lock(&tq->tx_lock);
388 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
389 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
390 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
391 netif_carrier_ok(adapter->netdev))) {
392 vmxnet3_tq_wake(tq, adapter);
393 }
394 spin_unlock(&tq->tx_lock);
395 }
396 return completed;
397}
398
399
400static void
401vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
402 struct vmxnet3_adapter *adapter)
403{
404 int i;
405
406 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
407 struct vmxnet3_tx_buf_info *tbi;
d1a890fa
SB		 408
409 tbi = tq->buf_info + tq->tx_ring.next2comp;
d1a890fa
SB		 410
411 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
412 if (tbi->skb) {
413 dev_kfree_skb_any(tbi->skb);
414 tbi->skb = NULL;
415 }
416 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
417 }
418
419 /* sanity check, verify all buffers are indeed unmapped and freed */
420 for (i = 0; i < tq->tx_ring.size; i++) {
421 BUG_ON(tq->buf_info[i].skb != NULL ||
422 tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
423 }
424
425 tq->tx_ring.gen = VMXNET3_INIT_GEN;
426 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
427
428 tq->comp_ring.gen = VMXNET3_INIT_GEN;
429 tq->comp_ring.next2proc = 0;
430}
431
432
09c5088e 433static void
d1a890fa
SB		 434vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
435 struct vmxnet3_adapter *adapter)
436{
437 if (tq->tx_ring.base) {
438 pci_free_consistent(adapter->pdev, tq->tx_ring.size *
439 sizeof(struct Vmxnet3_TxDesc),
440 tq->tx_ring.base, tq->tx_ring.basePA);
441 tq->tx_ring.base = NULL;
442 }
443 if (tq->data_ring.base) {
444 pci_free_consistent(adapter->pdev, tq->data_ring.size *
445 sizeof(struct Vmxnet3_TxDataDesc),
446 tq->data_ring.base, tq->data_ring.basePA);
447 tq->data_ring.base = NULL;
448 }
449 if (tq->comp_ring.base) {
450 pci_free_consistent(adapter->pdev, tq->comp_ring.size *
451 sizeof(struct Vmxnet3_TxCompDesc),
452 tq->comp_ring.base, tq->comp_ring.basePA);
453 tq->comp_ring.base = NULL;
454 }
455 kfree(tq->buf_info);
456 tq->buf_info = NULL;
457}
458
459
09c5088e
SB		 460/* Destroy all tx queues */
461void
462vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
463{
464 int i;
465
466 for (i = 0; i < adapter->num_tx_queues; i++)
467 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
468}
469
470
d1a890fa
SB		 471static void
472vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
473 struct vmxnet3_adapter *adapter)
474{
475 int i;
476
477 /* reset the tx ring contents to 0 and reset the tx ring states */
478 memset(tq->tx_ring.base, 0, tq->tx_ring.size *
479 sizeof(struct Vmxnet3_TxDesc));
480 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
481 tq->tx_ring.gen = VMXNET3_INIT_GEN;
482
483 memset(tq->data_ring.base, 0, tq->data_ring.size *
484 sizeof(struct Vmxnet3_TxDataDesc));
485
486 /* reset the tx comp ring contents to 0 and reset comp ring states */
487 memset(tq->comp_ring.base, 0, tq->comp_ring.size *
488 sizeof(struct Vmxnet3_TxCompDesc));
489 tq->comp_ring.next2proc = 0;
490 tq->comp_ring.gen = VMXNET3_INIT_GEN;
491
492 /* reset the bookkeeping data */
493 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
494 for (i = 0; i < tq->tx_ring.size; i++)
495 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
496
497 /* stats are not reset */
498}
499
500
501static int
502vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
503 struct vmxnet3_adapter *adapter)
504{
505 BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
506 tq->comp_ring.base || tq->buf_info);
507
508 tq->tx_ring.base = pci_alloc_consistent(adapter->pdev, tq->tx_ring.size
509 * sizeof(struct Vmxnet3_TxDesc),
510 &tq->tx_ring.basePA);
511 if (!tq->tx_ring.base) {
512 printk(KERN_ERR "%s: failed to allocate tx ring\n",
513 adapter->netdev->name);
514 goto err;
515 }
516
517 tq->data_ring.base = pci_alloc_consistent(adapter->pdev,
518 tq->data_ring.size *
519 sizeof(struct Vmxnet3_TxDataDesc),
520 &tq->data_ring.basePA);
521 if (!tq->data_ring.base) {
522 printk(KERN_ERR "%s: failed to allocate data ring\n",
523 adapter->netdev->name);
524 goto err;
525 }
526
527 tq->comp_ring.base = pci_alloc_consistent(adapter->pdev,
528 tq->comp_ring.size *
529 sizeof(struct Vmxnet3_TxCompDesc),
530 &tq->comp_ring.basePA);
531 if (!tq->comp_ring.base) {
532 printk(KERN_ERR "%s: failed to allocate tx comp ring\n",
533 adapter->netdev->name);
534 goto err;
535 }
536
537 tq->buf_info = kcalloc(tq->tx_ring.size, sizeof(tq->buf_info[0]),
538 GFP_KERNEL);
539 if (!tq->buf_info) {
540 printk(KERN_ERR "%s: failed to allocate tx bufinfo\n",
541 adapter->netdev->name);
542 goto err;
543 }
544
545 return 0;
546
547err:
548 vmxnet3_tq_destroy(tq, adapter);
549 return -ENOMEM;
550}
551
09c5088e
SB		 552static void
553vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
554{
555 int i;
556
557 for (i = 0; i < adapter->num_tx_queues; i++)
558 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
559}
d1a890fa
SB		 560
561/*
562 * starting from ring->next2fill, allocate rx buffers for the given ring
563 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
564 * are allocated or allocation fails
565 */
566
567static int
568vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
569 int num_to_alloc, struct vmxnet3_adapter *adapter)
570{
571 int num_allocated = 0;
572 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
573 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
574 u32 val;
575
5318d809 576 while (num_allocated <= num_to_alloc) {
d1a890fa
SB		 577 struct vmxnet3_rx_buf_info *rbi;
578 union Vmxnet3_GenericDesc *gd;
579
580 rbi = rbi_base + ring->next2fill;
581 gd = ring->base + ring->next2fill;
582
583 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
584 if (rbi->skb == NULL) {
585 rbi->skb = dev_alloc_skb(rbi->len +
586 NET_IP_ALIGN);
587 if (unlikely(rbi->skb == NULL)) {
588 rq->stats.rx_buf_alloc_failure++;
589 break;
590 }
591 rbi->skb->dev = adapter->netdev;
592
593 skb_reserve(rbi->skb, NET_IP_ALIGN);
594 rbi->dma_addr = pci_map_single(adapter->pdev,
595 rbi->skb->data, rbi->len,
596 PCI_DMA_FROMDEVICE);
597 } else {
598 /* rx buffer skipped by the device */
599 }
600 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
601 } else {
602 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
603 rbi->len != PAGE_SIZE);
604
605 if (rbi->page == NULL) {
606 rbi->page = alloc_page(GFP_ATOMIC);
607 if (unlikely(rbi->page == NULL)) {
608 rq->stats.rx_buf_alloc_failure++;
609 break;
610 }
611 rbi->dma_addr = pci_map_page(adapter->pdev,
612 rbi->page, 0, PAGE_SIZE,
613 PCI_DMA_FROMDEVICE);
614 } else {
615 /* rx buffers skipped by the device */
616 }
617 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
618 }
619
620 BUG_ON(rbi->dma_addr == 0);
115924b6 621 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
5318d809 622 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
115924b6 623 | val | rbi->len);
d1a890fa 624
5318d809
SB		 625 /* Fill the last buffer but dont mark it ready, or else the
626 * device will think that the queue is full */
627 if (num_allocated == num_to_alloc)
628 break;
629
630 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
d1a890fa
SB		 631 num_allocated++;
632 vmxnet3_cmd_ring_adv_next2fill(ring);
633 }
634 rq->uncommitted[ring_idx] += num_allocated;
635
f6965582
RD		 636 dev_dbg(&adapter->netdev->dev,
637 "alloc_rx_buf: %d allocated, next2fill %u, next2comp "
d1a890fa
SB		 638 "%u, uncommited %u\n", num_allocated, ring->next2fill,
639 ring->next2comp, rq->uncommitted[ring_idx]);
640
641 /* so that the device can distinguish a full ring and an empty ring */
642 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
643
644 return num_allocated;
645}
646
647
648static void
649vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
650 struct vmxnet3_rx_buf_info *rbi)
651{
652 struct skb_frag_struct *frag = skb_shinfo(skb)->frags +
653 skb_shinfo(skb)->nr_frags;
654
655 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
656
657 frag->page = rbi->page;
658 frag->page_offset = 0;
659 frag->size = rcd->len;
660 skb->data_len += frag->size;
661 skb_shinfo(skb)->nr_frags++;
662}
663
664
665static void
666vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
667 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
668 struct vmxnet3_adapter *adapter)
669{
670 u32 dw2, len;
671 unsigned long buf_offset;
672 int i;
673 union Vmxnet3_GenericDesc *gdesc;
674 struct vmxnet3_tx_buf_info *tbi = NULL;
675
676 BUG_ON(ctx->copy_size > skb_headlen(skb));
677
678 /* use the previous gen bit for the SOP desc */
679 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
680
681 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
682 gdesc = ctx->sop_txd; /* both loops below can be skipped */
683
684 /* no need to map the buffer if headers are copied */
685 if (ctx->copy_size) {
115924b6 686 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
d1a890fa 687 tq->tx_ring.next2fill *
115924b6
SB		 688 sizeof(struct Vmxnet3_TxDataDesc));
689 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
d1a890fa
SB		 690 ctx->sop_txd->dword[3] = 0;
691
692 tbi = tq->buf_info + tq->tx_ring.next2fill;
693 tbi->map_type = VMXNET3_MAP_NONE;
694
f6965582
RD		 695 dev_dbg(&adapter->netdev->dev,
696 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
115924b6
SB		 697 tq->tx_ring.next2fill,
698 le64_to_cpu(ctx->sop_txd->txd.addr),
d1a890fa
SB		 699 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
700 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
701
702 /* use the right gen for non-SOP desc */
703 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
704 }
705
706 /* linear part can use multiple tx desc if it's big */
707 len = skb_headlen(skb) - ctx->copy_size;
708 buf_offset = ctx->copy_size;
709 while (len) {
710 u32 buf_size;
711
1f4b1612
BD		 712 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
713 buf_size = len;
714 dw2 |= len;
715 } else {
716 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
717 /* spec says that for TxDesc.len, 0 == 2^14 */
718 }
d1a890fa
SB		 719
720 tbi = tq->buf_info + tq->tx_ring.next2fill;
721 tbi->map_type = VMXNET3_MAP_SINGLE;
722 tbi->dma_addr = pci_map_single(adapter->pdev,
723 skb->data + buf_offset, buf_size,
724 PCI_DMA_TODEVICE);
725
1f4b1612 726 tbi->len = buf_size;
d1a890fa
SB		 727
728 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
729 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
730
115924b6 731 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
1f4b1612 732 gdesc->dword[2] = cpu_to_le32(dw2);
d1a890fa
SB		 733 gdesc->dword[3] = 0;
734
f6965582
RD		 735 dev_dbg(&adapter->netdev->dev,
736 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
115924b6
SB		 737 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
738 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
d1a890fa
SB		 739 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
740 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
741
742 len -= buf_size;
743 buf_offset += buf_size;
744 }
745
746 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
747 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
748
749 tbi = tq->buf_info + tq->tx_ring.next2fill;
750 tbi->map_type = VMXNET3_MAP_PAGE;
751 tbi->dma_addr = pci_map_page(adapter->pdev, frag->page,
752 frag->page_offset, frag->size,
753 PCI_DMA_TODEVICE);
754
755 tbi->len = frag->size;
756
757 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
758 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
759
115924b6
SB		 760 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
761 gdesc->dword[2] = cpu_to_le32(dw2 | frag->size);
d1a890fa
SB		 762 gdesc->dword[3] = 0;
763
f6965582
RD		 764 dev_dbg(&adapter->netdev->dev,
765 "txd[%u]: 0x%llu %u %u\n",
115924b6
SB		 766 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
767 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
d1a890fa
SB		 768 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
769 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
770 }
771
772 ctx->eop_txd = gdesc;
773
774 /* set the last buf_info for the pkt */
775 tbi->skb = skb;
776 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
777}
778
779
09c5088e
SB		 780/* Init all tx queues */
781static void
782vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
783{
784 int i;
785
786 for (i = 0; i < adapter->num_tx_queues; i++)
787 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
788}
789
790
d1a890fa
SB		 791/*
792 * parse and copy relevant protocol headers:
793 * For a tso pkt, relevant headers are L2/3/4 including options
794 * For a pkt requesting csum offloading, they are L2/3 and may include L4
795 * if it's a TCP/UDP pkt
796 *
797 * Returns:
798 * -1: error happens during parsing
799 * 0: protocol headers parsed, but too big to be copied
800 * 1: protocol headers parsed and copied
801 *
802 * Other effects:
803 * 1. related *ctx fields are updated.
804 * 2. ctx->copy_size is # of bytes copied
805 * 3. the portion copied is guaranteed to be in the linear part
806 *
807 */
808static int
809vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
810 struct vmxnet3_tx_ctx *ctx,
811 struct vmxnet3_adapter *adapter)
812{
813 struct Vmxnet3_TxDataDesc *tdd;
814
0d0b1672 815 if (ctx->mss) { /* TSO */
d1a890fa
SB		 816 ctx->eth_ip_hdr_size = skb_transport_offset(skb);
817 ctx->l4_hdr_size = ((struct tcphdr *)
818 skb_transport_header(skb))->doff * 4;
819 ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size;
820 } else {
d1a890fa 821 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 822 ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb);
d1a890fa
SB		 823
824 if (ctx->ipv4) {
825 struct iphdr *iph = (struct iphdr *)
826 skb_network_header(skb);
39d4a96f 827 if (iph->protocol == IPPROTO_TCP)
d1a890fa
SB		 828 ctx->l4_hdr_size = ((struct tcphdr *)
829 skb_transport_header(skb))->doff * 4;
39d4a96f
SB		 830 else if (iph->protocol == IPPROTO_UDP)
831 /*
832 * Use tcp header size so that bytes to
833 * be copied are more than required by
834 * the device.
835 */
d1a890fa 836 ctx->l4_hdr_size =
39d4a96f
SB		 837 sizeof(struct tcphdr);
838 else
d1a890fa 839 ctx->l4_hdr_size = 0;
d1a890fa
SB		 840 } else {
841 /* for simplicity, don't copy L4 headers */
842 ctx->l4_hdr_size = 0;
843 }
844 ctx->copy_size = ctx->eth_ip_hdr_size +
845 ctx->l4_hdr_size;
846 } else {
847 ctx->eth_ip_hdr_size = 0;
848 ctx->l4_hdr_size = 0;
849 /* copy as much as allowed */
850 ctx->copy_size = min((unsigned int)VMXNET3_HDR_COPY_SIZE
851 , skb_headlen(skb));
852 }
853
854 /* make sure headers are accessible directly */
855 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
856 goto err;
857 }
858
859 if (unlikely(ctx->copy_size > VMXNET3_HDR_COPY_SIZE)) {
860 tq->stats.oversized_hdr++;
861 ctx->copy_size = 0;
862 return 0;
863 }
864
865 tdd = tq->data_ring.base + tq->tx_ring.next2fill;
866
867 memcpy(tdd->data, skb->data, ctx->copy_size);
f6965582
RD		 868 dev_dbg(&adapter->netdev->dev,
869 "copy %u bytes to dataRing[%u]\n",
d1a890fa
SB		 870 ctx->copy_size, tq->tx_ring.next2fill);
871 return 1;
872
873err:
874 return -1;
875}
876
877
878static void
879vmxnet3_prepare_tso(struct sk_buff *skb,
880 struct vmxnet3_tx_ctx *ctx)
881{
882 struct tcphdr *tcph = (struct tcphdr *)skb_transport_header(skb);
883 if (ctx->ipv4) {
884 struct iphdr *iph = (struct iphdr *)skb_network_header(skb);
885 iph->check = 0;
886 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
887 IPPROTO_TCP, 0);
888 } else {
889 struct ipv6hdr *iph = (struct ipv6hdr *)skb_network_header(skb);
890 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
891 IPPROTO_TCP, 0);
892 }
893}
894
895
896/*
897 * Transmits a pkt thru a given tq
898 * Returns:
899 * NETDEV_TX_OK: descriptors are setup successfully
25985edc 900 * NETDEV_TX_OK: error occurred, the pkt is dropped
d1a890fa
SB		 901 * NETDEV_TX_BUSY: tx ring is full, queue is stopped
902 *
903 * Side-effects:
904 * 1. tx ring may be changed
905 * 2. tq stats may be updated accordingly
906 * 3. shared->txNumDeferred may be updated
907 */
908
909static int
910vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
911 struct vmxnet3_adapter *adapter, struct net_device *netdev)
912{
913 int ret;
914 u32 count;
915 unsigned long flags;
916 struct vmxnet3_tx_ctx ctx;
917 union Vmxnet3_GenericDesc *gdesc;
115924b6
SB		 918#ifdef __BIG_ENDIAN_BITFIELD
919 /* Use temporary descriptor to avoid touching bits multiple times */
920 union Vmxnet3_GenericDesc tempTxDesc;
921#endif
d1a890fa
SB		 922
923 /* conservatively estimate # of descriptors to use */
924 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) +
925 skb_shinfo(skb)->nr_frags + 1;
926
72e85c45 927 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
d1a890fa
SB		 928
929 ctx.mss = skb_shinfo(skb)->gso_size;
930 if (ctx.mss) {
931 if (skb_header_cloned(skb)) {
932 if (unlikely(pskb_expand_head(skb, 0, 0,
933 GFP_ATOMIC) != 0)) {
934 tq->stats.drop_tso++;
935 goto drop_pkt;
936 }
937 tq->stats.copy_skb_header++;
938 }
939 vmxnet3_prepare_tso(skb, &ctx);
940 } else {
941 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
942
943 /* non-tso pkts must not use more than
944 * VMXNET3_MAX_TXD_PER_PKT entries
945 */
946 if (skb_linearize(skb) != 0) {
947 tq->stats.drop_too_many_frags++;
948 goto drop_pkt;
949 }
950 tq->stats.linearized++;
951
952 /* recalculate the # of descriptors to use */
953 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
954 }
955 }
956
09c5088e
SB		 957 spin_lock_irqsave(&tq->tx_lock, flags);
958
959 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
960 tq->stats.tx_ring_full++;
961 dev_dbg(&adapter->netdev->dev,
962 "tx queue stopped on %s, next2comp %u"
963 " next2fill %u\n", adapter->netdev->name,
964 tq->tx_ring.next2comp, tq->tx_ring.next2fill);
965
966 vmxnet3_tq_stop(tq, adapter);
967 spin_unlock_irqrestore(&tq->tx_lock, flags);
968 return NETDEV_TX_BUSY;
969 }
970
971
d1a890fa
SB		 972 ret = vmxnet3_parse_and_copy_hdr(skb, tq, &ctx, adapter);
973 if (ret >= 0) {
974 BUG_ON(ret <= 0 && ctx.copy_size != 0);
975 /* hdrs parsed, check against other limits */
976 if (ctx.mss) {
977 if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size >
978 VMXNET3_MAX_TX_BUF_SIZE)) {
979 goto hdr_too_big;
980 }
981 } else {
982 if (skb->ip_summed == CHECKSUM_PARTIAL) {
983 if (unlikely(ctx.eth_ip_hdr_size +
984 skb->csum_offset >
985 VMXNET3_MAX_CSUM_OFFSET)) {
986 goto hdr_too_big;
987 }
988 }
989 }
990 } else {
991 tq->stats.drop_hdr_inspect_err++;
f955e141 992 goto unlock_drop_pkt;
d1a890fa
SB		 993 }
994
d1a890fa
SB		 995 /* fill tx descs related to addr & len */
996 vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter);
997
998 /* setup the EOP desc */
115924b6 999 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
d1a890fa
SB		 1000
1001 /* setup the SOP desc */
115924b6
SB		 1002#ifdef __BIG_ENDIAN_BITFIELD
1003 gdesc = &tempTxDesc;
1004 gdesc->dword[2] = ctx.sop_txd->dword[2];
1005 gdesc->dword[3] = ctx.sop_txd->dword[3];
1006#else
d1a890fa 1007 gdesc = ctx.sop_txd;
115924b6 1008#endif
d1a890fa
SB		 1009 if (ctx.mss) {
1010 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size;
1011 gdesc->txd.om = VMXNET3_OM_TSO;
1012 gdesc->txd.msscof = ctx.mss;
115924b6
SB		 1013 le32_add_cpu(&tq->shared->txNumDeferred, (skb->len -
1014 gdesc->txd.hlen + ctx.mss - 1) / ctx.mss);
d1a890fa
SB		 1015 } else {
1016 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1017 gdesc->txd.hlen = ctx.eth_ip_hdr_size;
1018 gdesc->txd.om = VMXNET3_OM_CSUM;
1019 gdesc->txd.msscof = ctx.eth_ip_hdr_size +
1020 skb->csum_offset;
1021 } else {
1022 gdesc->txd.om = 0;
1023 gdesc->txd.msscof = 0;
1024 }
115924b6 1025 le32_add_cpu(&tq->shared->txNumDeferred, 1);
d1a890fa
SB		 1026 }
1027
1028 if (vlan_tx_tag_present(skb)) {
1029 gdesc->txd.ti = 1;
1030 gdesc->txd.tci = vlan_tx_tag_get(skb);
1031 }
1032
115924b6
SB		 1033 /* finally flips the GEN bit of the SOP desc. */
1034 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1035 VMXNET3_TXD_GEN);
1036#ifdef __BIG_ENDIAN_BITFIELD
1037 /* Finished updating in bitfields of Tx Desc, so write them in original
1038 * place.
1039 */
1040 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1041 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1042 gdesc = ctx.sop_txd;
1043#endif
f6965582
RD		 1044 dev_dbg(&adapter->netdev->dev,
1045 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
d1a890fa 1046 (u32)((union Vmxnet3_GenericDesc *)ctx.sop_txd -
115924b6
SB		 1047 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1048 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
d1a890fa
SB		 1049
1050 spin_unlock_irqrestore(&tq->tx_lock, flags);
1051
115924b6
SB		 1052 if (le32_to_cpu(tq->shared->txNumDeferred) >=
1053 le32_to_cpu(tq->shared->txThreshold)) {
d1a890fa 1054 tq->shared->txNumDeferred = 0;
09c5088e
SB		 1055 VMXNET3_WRITE_BAR0_REG(adapter,
1056 VMXNET3_REG_TXPROD + tq->qid * 8,
d1a890fa
SB		 1057 tq->tx_ring.next2fill);
1058 }
d1a890fa
SB		 1059
1060 return NETDEV_TX_OK;
1061
1062hdr_too_big:
1063 tq->stats.drop_oversized_hdr++;
f955e141
DC		 1064unlock_drop_pkt:
1065 spin_unlock_irqrestore(&tq->tx_lock, flags);
d1a890fa
SB		 1066drop_pkt:
1067 tq->stats.drop_total++;
1068 dev_kfree_skb(skb);
1069 return NETDEV_TX_OK;
1070}
1071
1072
1073static netdev_tx_t
1074vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1075{
1076 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1077
09c5088e
SB		 1078 BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1079 return vmxnet3_tq_xmit(skb,
1080 &adapter->tx_queue[skb->queue_mapping],
1081 adapter, netdev);
d1a890fa
SB		 1082}
1083
1084
1085static void
1086vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1087 struct sk_buff *skb,
1088 union Vmxnet3_GenericDesc *gdesc)
1089{
a0d2730c 1090 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
d1a890fa 1091 /* typical case: TCP/UDP over IP and both csums are correct */
115924b6 1092 if ((le32_to_cpu(gdesc->dword[3]) & VMXNET3_RCD_CSUM_OK) ==
d1a890fa
SB		 1093 VMXNET3_RCD_CSUM_OK) {
1094 skb->ip_summed = CHECKSUM_UNNECESSARY;
1095 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
1096 BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6));
1097 BUG_ON(gdesc->rcd.frg);
1098 } else {
1099 if (gdesc->rcd.csum) {
1100 skb->csum = htons(gdesc->rcd.csum);
1101 skb->ip_summed = CHECKSUM_PARTIAL;
1102 } else {
bc8acf2c 1103 skb_checksum_none_assert(skb);
d1a890fa
SB		 1104 }
1105 }
1106 } else {
bc8acf2c 1107 skb_checksum_none_assert(skb);
d1a890fa
SB		 1108 }
1109}
1110
1111
1112static void
1113vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1114 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
1115{
1116 rq->stats.drop_err++;
1117 if (!rcd->fcs)
1118 rq->stats.drop_fcs++;
1119
1120 rq->stats.drop_total++;
1121
1122 /*
1123 * We do not unmap and chain the rx buffer to the skb.
1124 * We basically pretend this buffer is not used and will be recycled
1125 * by vmxnet3_rq_alloc_rx_buf()
1126 */
1127
1128 /*
1129 * ctx->skb may be NULL if this is the first and the only one
1130 * desc for the pkt
1131 */
1132 if (ctx->skb)
1133 dev_kfree_skb_irq(ctx->skb);
1134
1135 ctx->skb = NULL;
1136}
1137
1138
1139static int
1140vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1141 struct vmxnet3_adapter *adapter, int quota)
1142{
215faf9c
JP		 1143 static const u32 rxprod_reg[2] = {
1144 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
1145 };
d1a890fa 1146 u32 num_rxd = 0;
5318d809 1147 bool skip_page_frags = false;
d1a890fa
SB		 1148 struct Vmxnet3_RxCompDesc *rcd;
1149 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
115924b6
SB		 1150#ifdef __BIG_ENDIAN_BITFIELD
1151 struct Vmxnet3_RxDesc rxCmdDesc;
1152 struct Vmxnet3_RxCompDesc rxComp;
1153#endif
1154 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1155 &rxComp);
d1a890fa
SB		 1156 while (rcd->gen == rq->comp_ring.gen) {
1157 struct vmxnet3_rx_buf_info *rbi;
5318d809
SB		 1158 struct sk_buff *skb, *new_skb = NULL;
1159 struct page *new_page = NULL;
d1a890fa
SB		 1160 int num_to_alloc;
1161 struct Vmxnet3_RxDesc *rxd;
1162 u32 idx, ring_idx;
5318d809 1163 struct vmxnet3_cmd_ring *ring = NULL;
d1a890fa
SB		 1164 if (num_rxd >= quota) {
1165 /* we may stop even before we see the EOP desc of
1166 * the current pkt
1167 */
1168 break;
1169 }
1170 num_rxd++;
09c5088e 1171 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2);
d1a890fa 1172 idx = rcd->rxdIdx;
09c5088e 1173 ring_idx = rcd->rqID < adapter->num_rx_queues ? 0 : 1;
5318d809 1174 ring = rq->rx_ring + ring_idx;
115924b6
SB		 1175 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1176 &rxCmdDesc);
d1a890fa
SB		 1177 rbi = rq->buf_info[ring_idx] + idx;
1178
115924b6
SB		 1179 BUG_ON(rxd->addr != rbi->dma_addr ||
1180 rxd->len != rbi->len);
d1a890fa
SB		 1181
1182 if (unlikely(rcd->eop && rcd->err)) {
1183 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1184 goto rcd_done;
1185 }
1186
1187 if (rcd->sop) { /* first buf of the pkt */
1188 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
1189 rcd->rqID != rq->qid);
1190
1191 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
1192 BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1193
1194 if (unlikely(rcd->len == 0)) {
1195 /* Pretend the rx buffer is skipped. */
1196 BUG_ON(!(rcd->sop && rcd->eop));
f6965582
RD		 1197 dev_dbg(&adapter->netdev->dev,
1198 "rxRing[%u][%u] 0 length\n",
d1a890fa
SB		 1199 ring_idx, idx);
1200 goto rcd_done;
1201 }
1202
5318d809 1203 skip_page_frags = false;
d1a890fa 1204 ctx->skb = rbi->skb;
5318d809
SB		 1205 new_skb = dev_alloc_skb(rbi->len + NET_IP_ALIGN);
1206 if (new_skb == NULL) {
1207 /* Skb allocation failed, do not handover this
1208 * skb to stack. Reuse it. Drop the existing pkt
1209 */
1210 rq->stats.rx_buf_alloc_failure++;
1211 ctx->skb = NULL;
1212 rq->stats.drop_total++;
1213 skip_page_frags = true;
1214 goto rcd_done;
1215 }
d1a890fa
SB		 1216
1217 pci_unmap_single(adapter->pdev, rbi->dma_addr, rbi->len,
1218 PCI_DMA_FROMDEVICE);
1219
1220 skb_put(ctx->skb, rcd->len);
5318d809
SB		 1221
1222 /* Immediate refill */
1223 new_skb->dev = adapter->netdev;
1224 skb_reserve(new_skb, NET_IP_ALIGN);
1225 rbi->skb = new_skb;
1226 rbi->dma_addr = pci_map_single(adapter->pdev,
1227 rbi->skb->data, rbi->len,
1228 PCI_DMA_FROMDEVICE);
1229 rxd->addr = cpu_to_le64(rbi->dma_addr);
1230 rxd->len = rbi->len;
1231
d1a890fa 1232 } else {
5318d809
SB		 1233 BUG_ON(ctx->skb == NULL && !skip_page_frags);
1234
d1a890fa 1235 /* non SOP buffer must be type 1 in most cases */
5318d809
SB		 1236 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
1237 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
d1a890fa 1238
5318d809
SB		 1239 /* If an sop buffer was dropped, skip all
1240 * following non-sop fragments. They will be reused.
1241 */
1242 if (skip_page_frags)
1243 goto rcd_done;
d1a890fa 1244
5318d809
SB		 1245 new_page = alloc_page(GFP_ATOMIC);
1246 if (unlikely(new_page == NULL)) {
1247 /* Replacement page frag could not be allocated.
1248 * Reuse this page. Drop the pkt and free the
1249 * skb which contained this page as a frag. Skip
1250 * processing all the following non-sop frags.
d1a890fa 1251 */
5318d809
SB		 1252 rq->stats.rx_buf_alloc_failure++;
1253 dev_kfree_skb(ctx->skb);
1254 ctx->skb = NULL;
1255 skip_page_frags = true;
1256 goto rcd_done;
1257 }
1258
1259 if (rcd->len) {
1260 pci_unmap_page(adapter->pdev,
1261 rbi->dma_addr, rbi->len,
1262 PCI_DMA_FROMDEVICE);
1263
1264 vmxnet3_append_frag(ctx->skb, rcd, rbi);
d1a890fa 1265 }
5318d809
SB		 1266
1267 /* Immediate refill */
1268 rbi->page = new_page;
1269 rbi->dma_addr = pci_map_page(adapter->pdev, rbi->page,
1270 0, PAGE_SIZE,
1271 PCI_DMA_FROMDEVICE);
1272 rxd->addr = cpu_to_le64(rbi->dma_addr);
1273 rxd->len = rbi->len;
d1a890fa
SB		 1274 }
1275
5318d809 1276
d1a890fa
SB		 1277 skb = ctx->skb;
1278 if (rcd->eop) {
1279 skb->len += skb->data_len;
1280 skb->truesize += skb->data_len;
1281
1282 vmxnet3_rx_csum(adapter, skb,
1283 (union Vmxnet3_GenericDesc *)rcd);
1284 skb->protocol = eth_type_trans(skb, adapter->netdev);
1285
72e85c45
JG		 1286 if (unlikely(rcd->ts))
1287 __vlan_hwaccel_put_tag(skb, rcd->tci);
1288
213ade8c
JG		 1289 if (adapter->netdev->features & NETIF_F_LRO)
1290 netif_receive_skb(skb);
1291 else
1292 napi_gro_receive(&rq->napi, skb);
d1a890fa 1293
d1a890fa
SB		 1294 ctx->skb = NULL;
1295 }
1296
1297rcd_done:
5318d809
SB		 1298 /* device may have skipped some rx descs */
1299 ring->next2comp = idx;
1300 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
1301 ring = rq->rx_ring + ring_idx;
1302 while (num_to_alloc) {
1303 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
1304 &rxCmdDesc);
1305 BUG_ON(!rxd->addr);
1306
1307 /* Recv desc is ready to be used by the device */
1308 rxd->gen = ring->gen;
1309 vmxnet3_cmd_ring_adv_next2fill(ring);
1310 num_to_alloc--;
1311 }
1312
1313 /* if needed, update the register */
1314 if (unlikely(rq->shared->updateRxProd)) {
1315 VMXNET3_WRITE_BAR0_REG(adapter,
1316 rxprod_reg[ring_idx] + rq->qid * 8,
1317 ring->next2fill);
1318 rq->uncommitted[ring_idx] = 0;
d1a890fa
SB		 1319 }
1320
1321 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
115924b6
SB		 1322 vmxnet3_getRxComp(rcd,
1323 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
d1a890fa
SB		 1324 }
1325
1326 return num_rxd;
1327}
1328
1329
1330static void
1331vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1332 struct vmxnet3_adapter *adapter)
1333{
1334 u32 i, ring_idx;
1335 struct Vmxnet3_RxDesc *rxd;
1336
1337 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1338 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
115924b6
SB		 1339#ifdef __BIG_ENDIAN_BITFIELD
1340 struct Vmxnet3_RxDesc rxDesc;
1341#endif
1342 vmxnet3_getRxDesc(rxd,
1343 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
d1a890fa
SB		 1344
1345 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1346 rq->buf_info[ring_idx][i].skb) {
1347 pci_unmap_single(adapter->pdev, rxd->addr,
1348 rxd->len, PCI_DMA_FROMDEVICE);
1349 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1350 rq->buf_info[ring_idx][i].skb = NULL;
1351 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1352 rq->buf_info[ring_idx][i].page) {
1353 pci_unmap_page(adapter->pdev, rxd->addr,
1354 rxd->len, PCI_DMA_FROMDEVICE);
1355 put_page(rq->buf_info[ring_idx][i].page);
1356 rq->buf_info[ring_idx][i].page = NULL;
1357 }
1358 }
1359
1360 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1361 rq->rx_ring[ring_idx].next2fill =
1362 rq->rx_ring[ring_idx].next2comp = 0;
1363 rq->uncommitted[ring_idx] = 0;
1364 }
1365
1366 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1367 rq->comp_ring.next2proc = 0;
1368}
1369
1370
09c5088e
SB		 1371static void
1372vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1373{
1374 int i;
1375
1376 for (i = 0; i < adapter->num_rx_queues; i++)
1377 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1378}
1379
1380
d1a890fa
SB		 1381void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1382 struct vmxnet3_adapter *adapter)
1383{
1384 int i;
1385 int j;
1386
1387 /* all rx buffers must have already been freed */
1388 for (i = 0; i < 2; i++) {
1389 if (rq->buf_info[i]) {
1390 for (j = 0; j < rq->rx_ring[i].size; j++)
1391 BUG_ON(rq->buf_info[i][j].page != NULL);
1392 }
1393 }
1394
1395
1396 kfree(rq->buf_info[0]);
1397
1398 for (i = 0; i < 2; i++) {
1399 if (rq->rx_ring[i].base) {
1400 pci_free_consistent(adapter->pdev, rq->rx_ring[i].size
1401 * sizeof(struct Vmxnet3_RxDesc),
1402 rq->rx_ring[i].base,
1403 rq->rx_ring[i].basePA);
1404 rq->rx_ring[i].base = NULL;
1405 }
1406 rq->buf_info[i] = NULL;
1407 }
1408
1409 if (rq->comp_ring.base) {
1410 pci_free_consistent(adapter->pdev, rq->comp_ring.size *
1411 sizeof(struct Vmxnet3_RxCompDesc),
1412 rq->comp_ring.base, rq->comp_ring.basePA);
1413 rq->comp_ring.base = NULL;
1414 }
1415}
1416
1417
1418static int
1419vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
1420 struct vmxnet3_adapter *adapter)
1421{
1422 int i;
1423
1424 /* initialize buf_info */
1425 for (i = 0; i < rq->rx_ring[0].size; i++) {
1426
1427 /* 1st buf for a pkt is skbuff */
1428 if (i % adapter->rx_buf_per_pkt == 0) {
1429 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
1430 rq->buf_info[0][i].len = adapter->skb_buf_size;
1431 } else { /* subsequent bufs for a pkt is frag */
1432 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
1433 rq->buf_info[0][i].len = PAGE_SIZE;
1434 }
1435 }
1436 for (i = 0; i < rq->rx_ring[1].size; i++) {
1437 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
1438 rq->buf_info[1][i].len = PAGE_SIZE;
1439 }
1440
1441 /* reset internal state and allocate buffers for both rings */
1442 for (i = 0; i < 2; i++) {
1443 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
1444 rq->uncommitted[i] = 0;
1445
1446 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
1447 sizeof(struct Vmxnet3_RxDesc));
1448 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
1449 }
1450 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
1451 adapter) == 0) {
1452 /* at least has 1 rx buffer for the 1st ring */
1453 return -ENOMEM;
1454 }
1455 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
1456
1457 /* reset the comp ring */
1458 rq->comp_ring.next2proc = 0;
1459 memset(rq->comp_ring.base, 0, rq->comp_ring.size *
1460 sizeof(struct Vmxnet3_RxCompDesc));
1461 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1462
1463 /* reset rxctx */
1464 rq->rx_ctx.skb = NULL;
1465
1466 /* stats are not reset */
1467 return 0;
1468}
1469
1470
09c5088e
SB		 1471static int
1472vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
1473{
1474 int i, err = 0;
1475
1476 for (i = 0; i < adapter->num_rx_queues; i++) {
1477 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
1478 if (unlikely(err)) {
1479 dev_err(&adapter->netdev->dev, "%s: failed to "
1480 "initialize rx queue%i\n",
1481 adapter->netdev->name, i);
1482 break;
1483 }
1484 }
1485 return err;
1486
1487}
1488
1489
d1a890fa
SB		 1490static int
1491vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
1492{
1493 int i;
1494 size_t sz;
1495 struct vmxnet3_rx_buf_info *bi;
1496
1497 for (i = 0; i < 2; i++) {
1498
1499 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
1500 rq->rx_ring[i].base = pci_alloc_consistent(adapter->pdev, sz,
1501 &rq->rx_ring[i].basePA);
1502 if (!rq->rx_ring[i].base) {
1503 printk(KERN_ERR "%s: failed to allocate rx ring %d\n",
1504 adapter->netdev->name, i);
1505 goto err;
1506 }
1507 }
1508
1509 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
1510 rq->comp_ring.base = pci_alloc_consistent(adapter->pdev, sz,
1511 &rq->comp_ring.basePA);
1512 if (!rq->comp_ring.base) {
1513 printk(KERN_ERR "%s: failed to allocate rx comp ring\n",
1514 adapter->netdev->name);
1515 goto err;
1516 }
1517
1518 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
1519 rq->rx_ring[1].size);
476c609e 1520 bi = kzalloc(sz, GFP_KERNEL);
d1a890fa
SB		 1521 if (!bi) {
1522 printk(KERN_ERR "%s: failed to allocate rx bufinfo\n",
1523 adapter->netdev->name);
1524 goto err;
1525 }
d1a890fa
SB		 1526 rq->buf_info[0] = bi;
1527 rq->buf_info[1] = bi + rq->rx_ring[0].size;
1528
1529 return 0;
1530
1531err:
1532 vmxnet3_rq_destroy(rq, adapter);
1533 return -ENOMEM;
1534}
1535
1536
09c5088e
SB		 1537static int
1538vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
1539{
1540 int i, err = 0;
1541
1542 for (i = 0; i < adapter->num_rx_queues; i++) {
1543 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
1544 if (unlikely(err)) {
1545 dev_err(&adapter->netdev->dev,
1546 "%s: failed to create rx queue%i\n",
1547 adapter->netdev->name, i);
1548 goto err_out;
1549 }
1550 }
1551 return err;
1552err_out:
1553 vmxnet3_rq_destroy_all(adapter);
1554 return err;
1555
1556}
1557
1558/* Multiple queue aware polling function for tx and rx */
1559
d1a890fa
SB		 1560static int
1561vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
1562{
09c5088e 1563 int rcd_done = 0, i;
d1a890fa
SB		 1564 if (unlikely(adapter->shared->ecr))
1565 vmxnet3_process_events(adapter);
09c5088e
SB		 1566 for (i = 0; i < adapter->num_tx_queues; i++)
1567 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
d1a890fa 1568
09c5088e
SB		 1569 for (i = 0; i < adapter->num_rx_queues; i++)
1570 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
1571 adapter, budget);
1572 return rcd_done;
d1a890fa
SB		 1573}
1574
1575
1576static int
1577vmxnet3_poll(struct napi_struct *napi, int budget)
1578{
09c5088e
SB		 1579 struct vmxnet3_rx_queue *rx_queue = container_of(napi,
1580 struct vmxnet3_rx_queue, napi);
1581 int rxd_done;
1582
1583 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
1584
1585 if (rxd_done < budget) {
1586 napi_complete(napi);
1587 vmxnet3_enable_all_intrs(rx_queue->adapter);
1588 }
1589 return rxd_done;
1590}
1591
1592/*
1593 * NAPI polling function for MSI-X mode with multiple Rx queues
1594 * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
1595 */
1596
1597static int
1598vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
1599{
1600 struct vmxnet3_rx_queue *rq = container_of(napi,
1601 struct vmxnet3_rx_queue, napi);
1602 struct vmxnet3_adapter *adapter = rq->adapter;
d1a890fa
SB		 1603 int rxd_done;
1604
09c5088e
SB		 1605 /* When sharing interrupt with corresponding tx queue, process
1606 * tx completions in that queue as well
1607 */
1608 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
1609 struct vmxnet3_tx_queue *tq =
1610 &adapter->tx_queue[rq - adapter->rx_queue];
1611 vmxnet3_tq_tx_complete(tq, adapter);
1612 }
1613
1614 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
d1a890fa
SB		 1615
1616 if (rxd_done < budget) {
1617 napi_complete(napi);
09c5088e 1618 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
d1a890fa
SB		 1619 }
1620 return rxd_done;
1621}
1622
1623
09c5088e
SB		 1624#ifdef CONFIG_PCI_MSI
1625
1626/*
1627 * Handle completion interrupts on tx queues
1628 * Returns whether or not the intr is handled
1629 */
1630
1631static irqreturn_t
1632vmxnet3_msix_tx(int irq, void *data)
1633{
1634 struct vmxnet3_tx_queue *tq = data;
1635 struct vmxnet3_adapter *adapter = tq->adapter;
1636
1637 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1638 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
1639
1640 /* Handle the case where only one irq is allocate for all tx queues */
1641 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1642 int i;
1643 for (i = 0; i < adapter->num_tx_queues; i++) {
1644 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
1645 vmxnet3_tq_tx_complete(txq, adapter);
1646 }
1647 } else {
1648 vmxnet3_tq_tx_complete(tq, adapter);
1649 }
1650 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
1651
1652 return IRQ_HANDLED;
1653}
1654
1655
1656/*
1657 * Handle completion interrupts on rx queues. Returns whether or not the
1658 * intr is handled
1659 */
1660
1661static irqreturn_t
1662vmxnet3_msix_rx(int irq, void *data)
1663{
1664 struct vmxnet3_rx_queue *rq = data;
1665 struct vmxnet3_adapter *adapter = rq->adapter;
1666
1667 /* disable intr if needed */
1668 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1669 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
1670 napi_schedule(&rq->napi);
1671
1672 return IRQ_HANDLED;
1673}
1674
1675/*
1676 *----------------------------------------------------------------------------
1677 *
1678 * vmxnet3_msix_event --
1679 *
1680 * vmxnet3 msix event intr handler
1681 *
1682 * Result:
1683 * whether or not the intr is handled
1684 *
1685 *----------------------------------------------------------------------------
1686 */
1687
1688static irqreturn_t
1689vmxnet3_msix_event(int irq, void *data)
1690{
1691 struct net_device *dev = data;
1692 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1693
1694 /* disable intr if needed */
1695 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1696 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
1697
1698 if (adapter->shared->ecr)
1699 vmxnet3_process_events(adapter);
1700
1701 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
1702
1703 return IRQ_HANDLED;
1704}
1705
1706#endif /* CONFIG_PCI_MSI */
1707
1708
d1a890fa
SB		 1709/* Interrupt handler for vmxnet3 */
1710static irqreturn_t
1711vmxnet3_intr(int irq, void *dev_id)
1712{
1713 struct net_device *dev = dev_id;
1714 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1715
09c5088e 1716 if (adapter->intr.type == VMXNET3_IT_INTX) {
d1a890fa
SB		 1717 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
1718 if (unlikely(icr == 0))
1719 /* not ours */
1720 return IRQ_NONE;
1721 }
1722
1723
1724 /* disable intr if needed */
1725 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
09c5088e 1726 vmxnet3_disable_all_intrs(adapter);
d1a890fa 1727
09c5088e 1728 napi_schedule(&adapter->rx_queue[0].napi);
d1a890fa
SB		 1729
1730 return IRQ_HANDLED;
1731}
1732
1733#ifdef CONFIG_NET_POLL_CONTROLLER
1734
d1a890fa
SB		 1735/* netpoll callback. */
1736static void
1737vmxnet3_netpoll(struct net_device *netdev)
1738{
1739 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1740
09c5088e
SB		 1741 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1742 vmxnet3_disable_all_intrs(adapter);
1743
1744 vmxnet3_do_poll(adapter, adapter->rx_queue[0].rx_ring[0].size);
1745 vmxnet3_enable_all_intrs(adapter);
d1a890fa 1746
d1a890fa 1747}
09c5088e 1748#endif /* CONFIG_NET_POLL_CONTROLLER */
d1a890fa
SB		 1749
1750static int
1751vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
1752{
09c5088e
SB		 1753 struct vmxnet3_intr *intr = &adapter->intr;
1754 int err = 0, i;
1755 int vector = 0;
d1a890fa 1756
8f7e524c 1757#ifdef CONFIG_PCI_MSI
d1a890fa 1758 if (adapter->intr.type == VMXNET3_IT_MSIX) {
09c5088e
SB		 1759 for (i = 0; i < adapter->num_tx_queues; i++) {
1760 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
1761 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
1762 adapter->netdev->name, vector);
1763 err = request_irq(
1764 intr->msix_entries[vector].vector,
1765 vmxnet3_msix_tx, 0,
1766 adapter->tx_queue[i].name,
1767 &adapter->tx_queue[i]);
1768 } else {
1769 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
1770 adapter->netdev->name, vector);
1771 }
1772 if (err) {
1773 dev_err(&adapter->netdev->dev,
1774 "Failed to request irq for MSIX, %s, "
1775 "error %d\n",
1776 adapter->tx_queue[i].name, err);
1777 return err;
1778 }
1779
1780 /* Handle the case where only 1 MSIx was allocated for
1781 * all tx queues */
1782 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1783 for (; i < adapter->num_tx_queues; i++)
1784 adapter->tx_queue[i].comp_ring.intr_idx
1785 = vector;
1786 vector++;
1787 break;
1788 } else {
1789 adapter->tx_queue[i].comp_ring.intr_idx
1790 = vector++;
1791 }
1792 }
1793 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
1794 vector = 0;
1795
1796 for (i = 0; i < adapter->num_rx_queues; i++) {
1797 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
1798 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
1799 adapter->netdev->name, vector);
1800 else
1801 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
1802 adapter->netdev->name, vector);
1803 err = request_irq(intr->msix_entries[vector].vector,
1804 vmxnet3_msix_rx, 0,
1805 adapter->rx_queue[i].name,
1806 &(adapter->rx_queue[i]));
1807 if (err) {
1808 printk(KERN_ERR "Failed to request irq for MSIX"
1809 ", %s, error %d\n",
1810 adapter->rx_queue[i].name, err);
1811 return err;
1812 }
1813
1814 adapter->rx_queue[i].comp_ring.intr_idx = vector++;
1815 }
1816
1817 sprintf(intr->event_msi_vector_name, "%s-event-%d",
1818 adapter->netdev->name, vector);
1819 err = request_irq(intr->msix_entries[vector].vector,
1820 vmxnet3_msix_event, 0,
1821 intr->event_msi_vector_name, adapter->netdev);
1822 intr->event_intr_idx = vector;
1823
1824 } else if (intr->type == VMXNET3_IT_MSI) {
1825 adapter->num_rx_queues = 1;
d1a890fa
SB		 1826 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
1827 adapter->netdev->name, adapter->netdev);
09c5088e 1828 } else {
115924b6 1829#endif
09c5088e 1830 adapter->num_rx_queues = 1;
d1a890fa
SB		 1831 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
1832 IRQF_SHARED, adapter->netdev->name,
1833 adapter->netdev);
09c5088e 1834#ifdef CONFIG_PCI_MSI
d1a890fa 1835 }
09c5088e
SB		 1836#endif
1837 intr->num_intrs = vector + 1;
1838 if (err) {
d1a890fa 1839 printk(KERN_ERR "Failed to request irq %s (intr type:%d), error"
09c5088e
SB		 1840 ":%d\n", adapter->netdev->name, intr->type, err);
1841 } else {
1842 /* Number of rx queues will not change after this */
1843 for (i = 0; i < adapter->num_rx_queues; i++) {
1844 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
1845 rq->qid = i;
1846 rq->qid2 = i + adapter->num_rx_queues;
1847 }
d1a890fa
SB		 1848
1849
d1a890fa 1850
09c5088e
SB		 1851 /* init our intr settings */
1852 for (i = 0; i < intr->num_intrs; i++)
1853 intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
1854 if (adapter->intr.type != VMXNET3_IT_MSIX) {
1855 adapter->intr.event_intr_idx = 0;
1856 for (i = 0; i < adapter->num_tx_queues; i++)
1857 adapter->tx_queue[i].comp_ring.intr_idx = 0;
1858 adapter->rx_queue[0].comp_ring.intr_idx = 0;
1859 }
d1a890fa
SB		 1860
1861 printk(KERN_INFO "%s: intr type %u, mode %u, %u vectors "
09c5088e
SB		 1862 "allocated\n", adapter->netdev->name, intr->type,
1863 intr->mask_mode, intr->num_intrs);
d1a890fa
SB		 1864 }
1865
1866 return err;
1867}
1868
1869
1870static void
1871vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
1872{
09c5088e
SB		 1873 struct vmxnet3_intr *intr = &adapter->intr;
1874 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
d1a890fa 1875
09c5088e 1876 switch (intr->type) {
8f7e524c 1877#ifdef CONFIG_PCI_MSI
d1a890fa
SB		 1878 case VMXNET3_IT_MSIX:
1879 {
09c5088e 1880 int i, vector = 0;
d1a890fa 1881
09c5088e
SB		 1882 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
1883 for (i = 0; i < adapter->num_tx_queues; i++) {
1884 free_irq(intr->msix_entries[vector++].vector,
1885 &(adapter->tx_queue[i]));
1886 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
1887 break;
1888 }
1889 }
1890
1891 for (i = 0; i < adapter->num_rx_queues; i++) {
1892 free_irq(intr->msix_entries[vector++].vector,
1893 &(adapter->rx_queue[i]));
1894 }
1895
1896 free_irq(intr->msix_entries[vector].vector,
1897 adapter->netdev);
1898 BUG_ON(vector >= intr->num_intrs);
d1a890fa
SB		 1899 break;
1900 }
8f7e524c 1901#endif
d1a890fa
SB		 1902 case VMXNET3_IT_MSI:
1903 free_irq(adapter->pdev->irq, adapter->netdev);
1904 break;
1905 case VMXNET3_IT_INTX:
1906 free_irq(adapter->pdev->irq, adapter->netdev);
1907 break;
1908 default:
1909 BUG_ON(true);
1910 }
1911}
1912
d1a890fa
SB		 1913
1914static void
1915vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
1916{
72e85c45
JG		 1917 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1918 u16 vid;
d1a890fa 1919
72e85c45
JG		 1920 /* allow untagged pkts */
1921 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
1922
1923 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
1924 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
d1a890fa
SB		 1925}
1926
1927
1928static void
1929vmxnet3_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1930{
1931 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1932 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
83d0feff 1933 unsigned long flags;
d1a890fa
SB		 1934
1935 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
83d0feff 1936 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 1937 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1938 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
83d0feff 1939 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
72e85c45
JG		 1940
1941 set_bit(vid, adapter->active_vlans);
d1a890fa
SB		 1942}
1943
1944
1945static void
1946vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1947{
1948 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1949 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
83d0feff 1950 unsigned long flags;
d1a890fa
SB		 1951
1952 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
83d0feff 1953 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 1954 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1955 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
83d0feff 1956 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
72e85c45
JG		 1957
1958 clear_bit(vid, adapter->active_vlans);
d1a890fa
SB		 1959}
1960
1961
1962static u8 *
1963vmxnet3_copy_mc(struct net_device *netdev)
1964{
1965 u8 *buf = NULL;
4cd24eaf 1966 u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
d1a890fa
SB		 1967
1968 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
1969 if (sz <= 0xffff) {
1970 /* We may be called with BH disabled */
1971 buf = kmalloc(sz, GFP_ATOMIC);
1972 if (buf) {
22bedad3 1973 struct netdev_hw_addr *ha;
567ec874 1974 int i = 0;
d1a890fa 1975
22bedad3
JP		 1976 netdev_for_each_mc_addr(ha, netdev)
1977 memcpy(buf + i++ * ETH_ALEN, ha->addr,
d1a890fa 1978 ETH_ALEN);
d1a890fa
SB		 1979 }
1980 }
1981 return buf;
1982}
1983
1984
1985static void
1986vmxnet3_set_mc(struct net_device *netdev)
1987{
1988 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
83d0feff 1989 unsigned long flags;
d1a890fa
SB		 1990 struct Vmxnet3_RxFilterConf *rxConf =
1991 &adapter->shared->devRead.rxFilterConf;
1992 u8 *new_table = NULL;
1993 u32 new_mode = VMXNET3_RXM_UCAST;
1994
72e85c45
JG		 1995 if (netdev->flags & IFF_PROMISC) {
1996 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1997 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
1998
d1a890fa 1999 new_mode |= VMXNET3_RXM_PROMISC;
72e85c45
JG		 2000 } else {
2001 vmxnet3_restore_vlan(adapter);
2002 }
d1a890fa
SB		 2003
2004 if (netdev->flags & IFF_BROADCAST)
2005 new_mode |= VMXNET3_RXM_BCAST;
2006
2007 if (netdev->flags & IFF_ALLMULTI)
2008 new_mode |= VMXNET3_RXM_ALL_MULTI;
2009 else
4cd24eaf 2010 if (!netdev_mc_empty(netdev)) {
d1a890fa
SB		 2011 new_table = vmxnet3_copy_mc(netdev);
2012 if (new_table) {
2013 new_mode |= VMXNET3_RXM_MCAST;
115924b6 2014 rxConf->mfTableLen = cpu_to_le16(
4cd24eaf 2015 netdev_mc_count(netdev) * ETH_ALEN);
115924b6
SB		 2016 rxConf->mfTablePA = cpu_to_le64(virt_to_phys(
2017 new_table));
d1a890fa
SB		 2018 } else {
2019 printk(KERN_INFO "%s: failed to copy mcast list"
2020 ", setting ALL_MULTI\n", netdev->name);
2021 new_mode |= VMXNET3_RXM_ALL_MULTI;
2022 }
2023 }
2024
2025
2026 if (!(new_mode & VMXNET3_RXM_MCAST)) {
2027 rxConf->mfTableLen = 0;
2028 rxConf->mfTablePA = 0;
2029 }
2030
83d0feff 2031 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 2032 if (new_mode != rxConf->rxMode) {
115924b6 2033 rxConf->rxMode = cpu_to_le32(new_mode);
d1a890fa
SB		 2034 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2035 VMXNET3_CMD_UPDATE_RX_MODE);
72e85c45
JG		 2036 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2037 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
d1a890fa
SB		 2038 }
2039
2040 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2041 VMXNET3_CMD_UPDATE_MAC_FILTERS);
83d0feff 2042 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2043
2044 kfree(new_table);
2045}
2046
09c5088e
SB		 2047void
2048vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2049{
2050 int i;
2051
2052 for (i = 0; i < adapter->num_rx_queues; i++)
2053 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2054}
2055
d1a890fa
SB		 2056
2057/*
2058 * Set up driver_shared based on settings in adapter.
2059 */
2060
2061static void
2062vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2063{
2064 struct Vmxnet3_DriverShared *shared = adapter->shared;
2065 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2066 struct Vmxnet3_TxQueueConf *tqc;
2067 struct Vmxnet3_RxQueueConf *rqc;
2068 int i;
2069
2070 memset(shared, 0, sizeof(*shared));
2071
2072 /* driver settings */
115924b6
SB		 2073 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2074 devRead->misc.driverInfo.version = cpu_to_le32(
2075 VMXNET3_DRIVER_VERSION_NUM);
d1a890fa
SB		 2076 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2077 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2078 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
115924b6
SB		 2079 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2080 *((u32 *)&devRead->misc.driverInfo.gos));
2081 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2082 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
d1a890fa 2083
115924b6
SB		 2084 devRead->misc.ddPA = cpu_to_le64(virt_to_phys(adapter));
2085 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
d1a890fa
SB		 2086
2087 /* set up feature flags */
a0d2730c 2088 if (adapter->netdev->features & NETIF_F_RXCSUM)
3843e515 2089 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
d1a890fa 2090
a0d2730c 2091 if (adapter->netdev->features & NETIF_F_LRO) {
3843e515 2092 devRead->misc.uptFeatures |= UPT1_F_LRO;
115924b6 2093 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
d1a890fa 2094 }
54da3d00 2095 if (adapter->netdev->features & NETIF_F_HW_VLAN_RX)
3843e515 2096 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
d1a890fa 2097
115924b6
SB		 2098 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2099 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2100 devRead->misc.queueDescLen = cpu_to_le32(
09c5088e
SB		 2101 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2102 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
d1a890fa
SB		 2103
2104 /* tx queue settings */
09c5088e
SB		 2105 devRead->misc.numTxQueues = adapter->num_tx_queues;
2106 for (i = 0; i < adapter->num_tx_queues; i++) {
2107 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2108 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2109 tqc = &adapter->tqd_start[i].conf;
2110 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
2111 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2112 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
2113 tqc->ddPA = cpu_to_le64(virt_to_phys(tq->buf_info));
2114 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
2115 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
2116 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
2117 tqc->ddLen = cpu_to_le32(
2118 sizeof(struct vmxnet3_tx_buf_info) *
2119 tqc->txRingSize);
2120 tqc->intrIdx = tq->comp_ring.intr_idx;
2121 }
d1a890fa
SB		 2122
2123 /* rx queue settings */
09c5088e
SB		 2124 devRead->misc.numRxQueues = adapter->num_rx_queues;
2125 for (i = 0; i < adapter->num_rx_queues; i++) {
2126 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2127 rqc = &adapter->rqd_start[i].conf;
2128 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2129 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2130 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
2131 rqc->ddPA = cpu_to_le64(virt_to_phys(
2132 rq->buf_info));
2133 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
2134 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
2135 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
2136 rqc->ddLen = cpu_to_le32(
2137 sizeof(struct vmxnet3_rx_buf_info) *
2138 (rqc->rxRingSize[0] +
2139 rqc->rxRingSize[1]));
2140 rqc->intrIdx = rq->comp_ring.intr_idx;
2141 }
2142
2143#ifdef VMXNET3_RSS
2144 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2145
2146 if (adapter->rss) {
2147 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
2148 devRead->misc.uptFeatures |= UPT1_F_RSS;
2149 devRead->misc.numRxQueues = adapter->num_rx_queues;
2150 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2151 UPT1_RSS_HASH_TYPE_IPV4 |
2152 UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2153 UPT1_RSS_HASH_TYPE_IPV6;
2154 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2155 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2156 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
2157 get_random_bytes(&rssConf->hashKey[0], rssConf->hashKeySize);
2158 for (i = 0; i < rssConf->indTableSize; i++)
2159 rssConf->indTable[i] = i % adapter->num_rx_queues;
2160
2161 devRead->rssConfDesc.confVer = 1;
2162 devRead->rssConfDesc.confLen = sizeof(*rssConf);
2163 devRead->rssConfDesc.confPA = virt_to_phys(rssConf);
2164 }
2165
2166#endif /* VMXNET3_RSS */
d1a890fa
SB		 2167
2168 /* intr settings */
2169 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2170 VMXNET3_IMM_AUTO;
2171 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2172 for (i = 0; i < adapter->intr.num_intrs; i++)
2173 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2174
2175 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
6929fe8a 2176 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 2177
2178 /* rx filter settings */
2179 devRead->rxFilterConf.rxMode = 0;
2180 vmxnet3_restore_vlan(adapter);
f9f25026
SB		 2181 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2182
d1a890fa
SB		 2183 /* the rest are already zeroed */
2184}
2185
2186
2187int
2188vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
2189{
09c5088e 2190 int err, i;
d1a890fa 2191 u32 ret;
83d0feff 2192 unsigned long flags;
d1a890fa 2193
09c5088e
SB		 2194 dev_dbg(&adapter->netdev->dev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
2195 " ring sizes %u %u %u\n", adapter->netdev->name,
2196 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
2197 adapter->tx_queue[0].tx_ring.size,
2198 adapter->rx_queue[0].rx_ring[0].size,
2199 adapter->rx_queue[0].rx_ring[1].size);
2200
2201 vmxnet3_tq_init_all(adapter);
2202 err = vmxnet3_rq_init_all(adapter);
d1a890fa
SB		 2203 if (err) {
2204 printk(KERN_ERR "Failed to init rx queue for %s: error %d\n",
2205 adapter->netdev->name, err);
2206 goto rq_err;
2207 }
2208
2209 err = vmxnet3_request_irqs(adapter);
2210 if (err) {
2211 printk(KERN_ERR "Failed to setup irq for %s: error %d\n",
2212 adapter->netdev->name, err);
2213 goto irq_err;
2214 }
2215
2216 vmxnet3_setup_driver_shared(adapter);
2217
115924b6
SB		 2218 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
2219 adapter->shared_pa));
2220 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
2221 adapter->shared_pa));
83d0feff 2222 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2223 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2224 VMXNET3_CMD_ACTIVATE_DEV);
2225 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
83d0feff 2226 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2227
2228 if (ret != 0) {
2229 printk(KERN_ERR "Failed to activate dev %s: error %u\n",
2230 adapter->netdev->name, ret);
2231 err = -EINVAL;
2232 goto activate_err;
2233 }
09c5088e
SB		 2234
2235 for (i = 0; i < adapter->num_rx_queues; i++) {
2236 VMXNET3_WRITE_BAR0_REG(adapter,
2237 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
2238 adapter->rx_queue[i].rx_ring[0].next2fill);
2239 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
2240 (i * VMXNET3_REG_ALIGN)),
2241 adapter->rx_queue[i].rx_ring[1].next2fill);
2242 }
d1a890fa
SB		 2243
2244 /* Apply the rx filter settins last. */
2245 vmxnet3_set_mc(adapter->netdev);
2246
2247 /*
2248 * Check link state when first activating device. It will start the
2249 * tx queue if the link is up.
2250 */
4a1745fc 2251 vmxnet3_check_link(adapter, true);
09c5088e
SB		 2252 for (i = 0; i < adapter->num_rx_queues; i++)
2253 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2254 vmxnet3_enable_all_intrs(adapter);
2255 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
2256 return 0;
2257
2258activate_err:
2259 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
2260 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
2261 vmxnet3_free_irqs(adapter);
2262irq_err:
2263rq_err:
2264 /* free up buffers we allocated */
09c5088e 2265 vmxnet3_rq_cleanup_all(adapter);
d1a890fa
SB		 2266 return err;
2267}
2268
2269
2270void
2271vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
2272{
83d0feff
SB		 2273 unsigned long flags;
2274 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 2275 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
83d0feff 2276 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2277}
2278
2279
2280int
2281vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
2282{
09c5088e 2283 int i;
83d0feff 2284 unsigned long flags;
d1a890fa
SB		 2285 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
2286 return 0;
2287
2288
83d0feff 2289 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2290 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2291 VMXNET3_CMD_QUIESCE_DEV);
83d0feff 2292 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2293 vmxnet3_disable_all_intrs(adapter);
2294
09c5088e
SB		 2295 for (i = 0; i < adapter->num_rx_queues; i++)
2296 napi_disable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2297 netif_tx_disable(adapter->netdev);
2298 adapter->link_speed = 0;
2299 netif_carrier_off(adapter->netdev);
2300
09c5088e
SB		 2301 vmxnet3_tq_cleanup_all(adapter);
2302 vmxnet3_rq_cleanup_all(adapter);
d1a890fa
SB		 2303 vmxnet3_free_irqs(adapter);
2304 return 0;
2305}
2306
2307
2308static void
2309vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2310{
2311 u32 tmp;
2312
2313 tmp = *(u32 *)mac;
2314 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
2315
2316 tmp = (mac[5] << 8) | mac[4];
2317 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
2318}
2319
2320
2321static int
2322vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
2323{
2324 struct sockaddr *addr = p;
2325 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2326
2327 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2328 vmxnet3_write_mac_addr(adapter, addr->sa_data);
2329
2330 return 0;
2331}
2332
2333
2334/* ==================== initialization and cleanup routines ============ */
2335
2336static int
2337vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64)
2338{
2339 int err;
2340 unsigned long mmio_start, mmio_len;
2341 struct pci_dev *pdev = adapter->pdev;
2342
2343 err = pci_enable_device(pdev);
2344 if (err) {
2345 printk(KERN_ERR "Failed to enable adapter %s: error %d\n",
2346 pci_name(pdev), err);
2347 return err;
2348 }
2349
2350 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
2351 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
2352 printk(KERN_ERR "pci_set_consistent_dma_mask failed "
2353 "for adapter %s\n", pci_name(pdev));
2354 err = -EIO;
2355 goto err_set_mask;
2356 }
2357 *dma64 = true;
2358 } else {
2359 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
2360 printk(KERN_ERR "pci_set_dma_mask failed for adapter "
2361 "%s\n", pci_name(pdev));
2362 err = -EIO;
2363 goto err_set_mask;
2364 }
2365 *dma64 = false;
2366 }
2367
2368 err = pci_request_selected_regions(pdev, (1 << 2) - 1,
2369 vmxnet3_driver_name);
2370 if (err) {
2371 printk(KERN_ERR "Failed to request region for adapter %s: "
2372 "error %d\n", pci_name(pdev), err);
2373 goto err_set_mask;
2374 }
2375
2376 pci_set_master(pdev);
2377
2378 mmio_start = pci_resource_start(pdev, 0);
2379 mmio_len = pci_resource_len(pdev, 0);
2380 adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
2381 if (!adapter->hw_addr0) {
2382 printk(KERN_ERR "Failed to map bar0 for adapter %s\n",
2383 pci_name(pdev));
2384 err = -EIO;
2385 goto err_ioremap;
2386 }
2387
2388 mmio_start = pci_resource_start(pdev, 1);
2389 mmio_len = pci_resource_len(pdev, 1);
2390 adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
2391 if (!adapter->hw_addr1) {
2392 printk(KERN_ERR "Failed to map bar1 for adapter %s\n",
2393 pci_name(pdev));
2394 err = -EIO;
2395 goto err_bar1;
2396 }
2397 return 0;
2398
2399err_bar1:
2400 iounmap(adapter->hw_addr0);
2401err_ioremap:
2402 pci_release_selected_regions(pdev, (1 << 2) - 1);
2403err_set_mask:
2404 pci_disable_device(pdev);
2405 return err;
2406}
2407
2408
2409static void
2410vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
2411{
2412 BUG_ON(!adapter->pdev);
2413
2414 iounmap(adapter->hw_addr0);
2415 iounmap(adapter->hw_addr1);
2416 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
2417 pci_disable_device(adapter->pdev);
2418}
2419
2420
2421static void
2422vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
2423{
09c5088e
SB		 2424 size_t sz, i, ring0_size, ring1_size, comp_size;
2425 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[0];
2426
d1a890fa
SB		 2427
2428 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
2429 VMXNET3_MAX_ETH_HDR_SIZE) {
2430 adapter->skb_buf_size = adapter->netdev->mtu +
2431 VMXNET3_MAX_ETH_HDR_SIZE;
2432 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
2433 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
2434
2435 adapter->rx_buf_per_pkt = 1;
2436 } else {
2437 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
2438 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
2439 VMXNET3_MAX_ETH_HDR_SIZE;
2440 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
2441 }
2442
2443 /*
2444 * for simplicity, force the ring0 size to be a multiple of
2445 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
2446 */
2447 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
09c5088e
SB		 2448 ring0_size = adapter->rx_queue[0].rx_ring[0].size;
2449 ring0_size = (ring0_size + sz - 1) / sz * sz;
a53255d3 2450 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
09c5088e
SB		 2451 sz * sz);
2452 ring1_size = adapter->rx_queue[0].rx_ring[1].size;
2453 comp_size = ring0_size + ring1_size;
2454
2455 for (i = 0; i < adapter->num_rx_queues; i++) {
2456 rq = &adapter->rx_queue[i];
2457 rq->rx_ring[0].size = ring0_size;
2458 rq->rx_ring[1].size = ring1_size;
2459 rq->comp_ring.size = comp_size;
2460 }
d1a890fa
SB		 2461}
2462
2463
2464int
2465vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
2466 u32 rx_ring_size, u32 rx_ring2_size)
2467{
09c5088e
SB		 2468 int err = 0, i;
2469
2470 for (i = 0; i < adapter->num_tx_queues; i++) {
2471 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2472 tq->tx_ring.size = tx_ring_size;
2473 tq->data_ring.size = tx_ring_size;
2474 tq->comp_ring.size = tx_ring_size;
2475 tq->shared = &adapter->tqd_start[i].ctrl;
2476 tq->stopped = true;
2477 tq->adapter = adapter;
2478 tq->qid = i;
2479 err = vmxnet3_tq_create(tq, adapter);
2480 /*
2481 * Too late to change num_tx_queues. We cannot do away with
2482 * lesser number of queues than what we asked for
2483 */
2484 if (err)
2485 goto queue_err;
2486 }
d1a890fa 2487
09c5088e
SB		 2488 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
2489 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
d1a890fa 2490 vmxnet3_adjust_rx_ring_size(adapter);
09c5088e
SB		 2491 for (i = 0; i < adapter->num_rx_queues; i++) {
2492 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2493 /* qid and qid2 for rx queues will be assigned later when num
2494 * of rx queues is finalized after allocating intrs */
2495 rq->shared = &adapter->rqd_start[i].ctrl;
2496 rq->adapter = adapter;
2497 err = vmxnet3_rq_create(rq, adapter);
2498 if (err) {
2499 if (i == 0) {
2500 printk(KERN_ERR "Could not allocate any rx"
2501 "queues. Aborting.\n");
2502 goto queue_err;
2503 } else {
2504 printk(KERN_INFO "Number of rx queues changed "
2505 "to : %d.\n", i);
2506 adapter->num_rx_queues = i;
2507 err = 0;
2508 break;
2509 }
2510 }
2511 }
2512 return err;
2513queue_err:
2514 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2515 return err;
2516}
2517
2518static int
2519vmxnet3_open(struct net_device *netdev)
2520{
2521 struct vmxnet3_adapter *adapter;
09c5088e 2522 int err, i;
d1a890fa
SB		 2523
2524 adapter = netdev_priv(netdev);
2525
09c5088e
SB		 2526 for (i = 0; i < adapter->num_tx_queues; i++)
2527 spin_lock_init(&adapter->tx_queue[i].tx_lock);
d1a890fa
SB		 2528
2529 err = vmxnet3_create_queues(adapter, VMXNET3_DEF_TX_RING_SIZE,
2530 VMXNET3_DEF_RX_RING_SIZE,
2531 VMXNET3_DEF_RX_RING_SIZE);
2532 if (err)
2533 goto queue_err;
2534
2535 err = vmxnet3_activate_dev(adapter);
2536 if (err)
2537 goto activate_err;
2538
2539 return 0;
2540
2541activate_err:
09c5088e
SB		 2542 vmxnet3_rq_destroy_all(adapter);
2543 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2544queue_err:
2545 return err;
2546}
2547
2548
2549static int
2550vmxnet3_close(struct net_device *netdev)
2551{
2552 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2553
2554 /*
2555 * Reset_work may be in the middle of resetting the device, wait for its
2556 * completion.
2557 */
2558 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2559 msleep(1);
2560
2561 vmxnet3_quiesce_dev(adapter);
2562
09c5088e
SB		 2563 vmxnet3_rq_destroy_all(adapter);
2564 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2565
2566 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2567
2568
2569 return 0;
2570}
2571
2572
2573void
2574vmxnet3_force_close(struct vmxnet3_adapter *adapter)
2575{
09c5088e
SB		 2576 int i;
2577
d1a890fa
SB		 2578 /*
2579 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
2580 * vmxnet3_close() will deadlock.
2581 */
2582 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
2583
2584 /* we need to enable NAPI, otherwise dev_close will deadlock */
09c5088e
SB		 2585 for (i = 0; i < adapter->num_rx_queues; i++)
2586 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2587 dev_close(adapter->netdev);
2588}
2589
2590
2591static int
2592vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
2593{
2594 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2595 int err = 0;
2596
2597 if (new_mtu < VMXNET3_MIN_MTU || new_mtu > VMXNET3_MAX_MTU)
2598 return -EINVAL;
2599
d1a890fa
SB		 2600 netdev->mtu = new_mtu;
2601
2602 /*
2603 * Reset_work may be in the middle of resetting the device, wait for its
2604 * completion.
2605 */
2606 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2607 msleep(1);
2608
2609 if (netif_running(netdev)) {
2610 vmxnet3_quiesce_dev(adapter);
2611 vmxnet3_reset_dev(adapter);
2612
2613 /* we need to re-create the rx queue based on the new mtu */
09c5088e 2614 vmxnet3_rq_destroy_all(adapter);
d1a890fa 2615 vmxnet3_adjust_rx_ring_size(adapter);
09c5088e 2616 err = vmxnet3_rq_create_all(adapter);
d1a890fa 2617 if (err) {
09c5088e 2618 printk(KERN_ERR "%s: failed to re-create rx queues,"
d1a890fa
SB		 2619 " error %d. Closing it.\n", netdev->name, err);
2620 goto out;
2621 }
2622
2623 err = vmxnet3_activate_dev(adapter);
2624 if (err) {
2625 printk(KERN_ERR "%s: failed to re-activate, error %d. "
2626 "Closing it\n", netdev->name, err);
2627 goto out;
2628 }
2629 }
2630
2631out:
2632 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2633 if (err)
2634 vmxnet3_force_close(adapter);
2635
2636 return err;
2637}
2638
2639
2640static void
2641vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
2642{
2643 struct net_device *netdev = adapter->netdev;
2644
a0d2730c
MM		 2645 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
2646 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_TX |
72e85c45
JG		 2647 NETIF_F_HW_VLAN_RX | NETIF_F_TSO | NETIF_F_TSO6 |
2648 NETIF_F_LRO;
a0d2730c 2649 if (dma64)
d1a890fa 2650 netdev->features |= NETIF_F_HIGHDMA;
72e85c45
JG		 2651 netdev->vlan_features = netdev->hw_features &
2652 ~(NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
2653 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_FILTER;
d1a890fa 2654
a0d2730c
MM		 2655 netdev_info(adapter->netdev,
2656 "features: sg csum vlan jf tso tsoIPv6 lro%s\n",
2657 dma64 ? " highDMA" : "");
d1a890fa
SB		 2658}
2659
2660
2661static void
2662vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2663{
2664 u32 tmp;
2665
2666 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
2667 *(u32 *)mac = tmp;
2668
2669 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
2670 mac[4] = tmp & 0xff;
2671 mac[5] = (tmp >> 8) & 0xff;
2672}
2673
09c5088e
SB		 2674#ifdef CONFIG_PCI_MSI
2675
2676/*
2677 * Enable MSIx vectors.
2678 * Returns :
2679 * 0 on successful enabling of required vectors,
25985edc 2680 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
09c5088e
SB		 2681 * could be enabled.
2682 * number of vectors which can be enabled otherwise (this number is smaller
2683 * than VMXNET3_LINUX_MIN_MSIX_VECT)
2684 */
2685
2686static int
2687vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter,
2688 int vectors)
2689{
2690 int err = 0, vector_threshold;
2691 vector_threshold = VMXNET3_LINUX_MIN_MSIX_VECT;
2692
2693 while (vectors >= vector_threshold) {
2694 err = pci_enable_msix(adapter->pdev, adapter->intr.msix_entries,
2695 vectors);
2696 if (!err) {
2697 adapter->intr.num_intrs = vectors;
2698 return 0;
2699 } else if (err < 0) {
2700 printk(KERN_ERR "Failed to enable MSI-X for %s, error"
2701 " %d\n", adapter->netdev->name, err);
2702 vectors = 0;
2703 } else if (err < vector_threshold) {
2704 break;
2705 } else {
2706 /* If fails to enable required number of MSI-x vectors
7e96fbf2 2707 * try enabling minimum number of vectors required.
09c5088e
SB		 2708 */
2709 vectors = vector_threshold;
2710 printk(KERN_ERR "Failed to enable %d MSI-X for %s, try"
2711 " %d instead\n", vectors, adapter->netdev->name,
2712 vector_threshold);
2713 }
2714 }
2715
2716 printk(KERN_INFO "Number of MSI-X interrupts which can be allocatedi"
2717 " are lower than min threshold required.\n");
2718 return err;
2719}
2720
2721
2722#endif /* CONFIG_PCI_MSI */
d1a890fa
SB		 2723
2724static void
2725vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
2726{
2727 u32 cfg;
e328d410 2728 unsigned long flags;
d1a890fa
SB		 2729
2730 /* intr settings */
e328d410 2731 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2732 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2733 VMXNET3_CMD_GET_CONF_INTR);
2734 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
e328d410 2735 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2736 adapter->intr.type = cfg & 0x3;
2737 adapter->intr.mask_mode = (cfg >> 2) & 0x3;
2738
2739 if (adapter->intr.type == VMXNET3_IT_AUTO) {
0bdc0d70
SB		 2740 adapter->intr.type = VMXNET3_IT_MSIX;
2741 }
d1a890fa 2742
8f7e524c 2743#ifdef CONFIG_PCI_MSI
0bdc0d70 2744 if (adapter->intr.type == VMXNET3_IT_MSIX) {
09c5088e
SB		 2745 int vector, err = 0;
2746
2747 adapter->intr.num_intrs = (adapter->share_intr ==
2748 VMXNET3_INTR_TXSHARE) ? 1 :
2749 adapter->num_tx_queues;
2750 adapter->intr.num_intrs += (adapter->share_intr ==
2751 VMXNET3_INTR_BUDDYSHARE) ? 0 :
2752 adapter->num_rx_queues;
2753 adapter->intr.num_intrs += 1; /* for link event */
2754
2755 adapter->intr.num_intrs = (adapter->intr.num_intrs >
2756 VMXNET3_LINUX_MIN_MSIX_VECT
2757 ? adapter->intr.num_intrs :
2758 VMXNET3_LINUX_MIN_MSIX_VECT);
2759
2760 for (vector = 0; vector < adapter->intr.num_intrs; vector++)
2761 adapter->intr.msix_entries[vector].entry = vector;
2762
2763 err = vmxnet3_acquire_msix_vectors(adapter,
2764 adapter->intr.num_intrs);
2765 /* If we cannot allocate one MSIx vector per queue
2766 * then limit the number of rx queues to 1
2767 */
2768 if (err == VMXNET3_LINUX_MIN_MSIX_VECT) {
2769 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
7e96fbf2 2770 || adapter->num_rx_queues != 1) {
09c5088e
SB		 2771 adapter->share_intr = VMXNET3_INTR_TXSHARE;
2772 printk(KERN_ERR "Number of rx queues : 1\n");
2773 adapter->num_rx_queues = 1;
2774 adapter->intr.num_intrs =
2775 VMXNET3_LINUX_MIN_MSIX_VECT;
2776 }
d1a890fa
SB		 2777 return;
2778 }
09c5088e
SB		 2779 if (!err)
2780 return;
2781
2782 /* If we cannot allocate MSIx vectors use only one rx queue */
2783 printk(KERN_INFO "Failed to enable MSI-X for %s, error %d."
2784 "#rx queues : 1, try MSI\n", adapter->netdev->name, err);
2785
0bdc0d70
SB		 2786 adapter->intr.type = VMXNET3_IT_MSI;
2787 }
d1a890fa 2788
0bdc0d70
SB		 2789 if (adapter->intr.type == VMXNET3_IT_MSI) {
2790 int err;
d1a890fa
SB		 2791 err = pci_enable_msi(adapter->pdev);
2792 if (!err) {
09c5088e 2793 adapter->num_rx_queues = 1;
d1a890fa 2794 adapter->intr.num_intrs = 1;
d1a890fa
SB		 2795 return;
2796 }
2797 }
0bdc0d70 2798#endif /* CONFIG_PCI_MSI */
d1a890fa 2799
09c5088e
SB		 2800 adapter->num_rx_queues = 1;
2801 printk(KERN_INFO "Using INTx interrupt, #Rx queues: 1.\n");
d1a890fa
SB		 2802 adapter->intr.type = VMXNET3_IT_INTX;
2803
2804 /* INT-X related setting */
2805 adapter->intr.num_intrs = 1;
2806}
2807
2808
2809static void
2810vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
2811{
2812 if (adapter->intr.type == VMXNET3_IT_MSIX)
2813 pci_disable_msix(adapter->pdev);
2814 else if (adapter->intr.type == VMXNET3_IT_MSI)
2815 pci_disable_msi(adapter->pdev);
2816 else
2817 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
2818}
2819
2820
2821static void
2822vmxnet3_tx_timeout(struct net_device *netdev)
2823{
2824 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2825 adapter->tx_timeout_count++;
2826
2827 printk(KERN_ERR "%s: tx hang\n", adapter->netdev->name);
2828 schedule_work(&adapter->work);
09c5088e 2829 netif_wake_queue(adapter->netdev);
d1a890fa
SB		 2830}
2831
2832
2833static void
2834vmxnet3_reset_work(struct work_struct *data)
2835{
2836 struct vmxnet3_adapter *adapter;
2837
2838 adapter = container_of(data, struct vmxnet3_adapter, work);
2839
2840 /* if another thread is resetting the device, no need to proceed */
2841 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2842 return;
2843
2844 /* if the device is closed, we must leave it alone */
d9a5f210 2845 rtnl_lock();
d1a890fa
SB		 2846 if (netif_running(adapter->netdev)) {
2847 printk(KERN_INFO "%s: resetting\n", adapter->netdev->name);
2848 vmxnet3_quiesce_dev(adapter);
2849 vmxnet3_reset_dev(adapter);
2850 vmxnet3_activate_dev(adapter);
2851 } else {
2852 printk(KERN_INFO "%s: already closed\n", adapter->netdev->name);
2853 }
d9a5f210 2854 rtnl_unlock();
d1a890fa
SB		 2855
2856 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2857}
2858
2859
2860static int __devinit
2861vmxnet3_probe_device(struct pci_dev *pdev,
2862 const struct pci_device_id *id)
2863{
2864 static const struct net_device_ops vmxnet3_netdev_ops = {
2865 .ndo_open = vmxnet3_open,
2866 .ndo_stop = vmxnet3_close,
2867 .ndo_start_xmit = vmxnet3_xmit_frame,
2868 .ndo_set_mac_address = vmxnet3_set_mac_addr,
2869 .ndo_change_mtu = vmxnet3_change_mtu,
a0d2730c 2870 .ndo_set_features = vmxnet3_set_features,
95305f6c 2871 .ndo_get_stats64 = vmxnet3_get_stats64,
d1a890fa
SB		 2872 .ndo_tx_timeout = vmxnet3_tx_timeout,
2873 .ndo_set_multicast_list = vmxnet3_set_mc,
d1a890fa
SB		 2874 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
2875 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
2876#ifdef CONFIG_NET_POLL_CONTROLLER
2877 .ndo_poll_controller = vmxnet3_netpoll,
2878#endif
2879 };
2880 int err;
2881 bool dma64 = false; /* stupid gcc */
2882 u32 ver;
2883 struct net_device *netdev;
2884 struct vmxnet3_adapter *adapter;
2885 u8 mac[ETH_ALEN];
09c5088e
SB		 2886 int size;
2887 int num_tx_queues;
2888 int num_rx_queues;
2889
e154b639
SB		 2890 if (!pci_msi_enabled())
2891 enable_mq = 0;
2892
09c5088e
SB		 2893#ifdef VMXNET3_RSS
2894 if (enable_mq)
2895 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
2896 (int)num_online_cpus());
2897 else
2898#endif
2899 num_rx_queues = 1;
eebb02b1 2900 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
09c5088e
SB		 2901
2902 if (enable_mq)
2903 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
2904 (int)num_online_cpus());
2905 else
2906 num_tx_queues = 1;
2907
eebb02b1 2908 num_tx_queues = rounddown_pow_of_two(num_tx_queues);
09c5088e
SB		 2909 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
2910 max(num_tx_queues, num_rx_queues));
2911 printk(KERN_INFO "# of Tx queues : %d, # of Rx queues : %d\n",
2912 num_tx_queues, num_rx_queues);
d1a890fa 2913
d1a890fa
SB		 2914 if (!netdev) {
2915 printk(KERN_ERR "Failed to alloc ethernet device for adapter "
2916 "%s\n", pci_name(pdev));
2917 return -ENOMEM;
2918 }
2919
2920 pci_set_drvdata(pdev, netdev);
2921 adapter = netdev_priv(netdev);
2922 adapter->netdev = netdev;
2923 adapter->pdev = pdev;
2924
83d0feff 2925 spin_lock_init(&adapter->cmd_lock);
d1a890fa
SB		 2926 adapter->shared = pci_alloc_consistent(adapter->pdev,
2927 sizeof(struct Vmxnet3_DriverShared),
2928 &adapter->shared_pa);
2929 if (!adapter->shared) {
2930 printk(KERN_ERR "Failed to allocate memory for %s\n",
2931 pci_name(pdev));
2932 err = -ENOMEM;
2933 goto err_alloc_shared;
2934 }
2935
09c5088e
SB		 2936 adapter->num_rx_queues = num_rx_queues;
2937 adapter->num_tx_queues = num_tx_queues;
2938
2939 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
2940 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
2941 adapter->tqd_start = pci_alloc_consistent(adapter->pdev, size,
d1a890fa
SB		 2942 &adapter->queue_desc_pa);
2943
2944 if (!adapter->tqd_start) {
2945 printk(KERN_ERR "Failed to allocate memory for %s\n",
2946 pci_name(pdev));
2947 err = -ENOMEM;
2948 goto err_alloc_queue_desc;
2949 }
09c5088e
SB		 2950 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
2951 adapter->num_tx_queues);
d1a890fa
SB		 2952
2953 adapter->pm_conf = kmalloc(sizeof(struct Vmxnet3_PMConf), GFP_KERNEL);
2954 if (adapter->pm_conf == NULL) {
2955 printk(KERN_ERR "Failed to allocate memory for %s\n",
2956 pci_name(pdev));
2957 err = -ENOMEM;
2958 goto err_alloc_pm;
2959 }
2960
09c5088e
SB		 2961#ifdef VMXNET3_RSS
2962
2963 adapter->rss_conf = kmalloc(sizeof(struct UPT1_RSSConf), GFP_KERNEL);
2964 if (adapter->rss_conf == NULL) {
2965 printk(KERN_ERR "Failed to allocate memory for %s\n",
2966 pci_name(pdev));
2967 err = -ENOMEM;
2968 goto err_alloc_rss;
2969 }
2970#endif /* VMXNET3_RSS */
2971
d1a890fa
SB		 2972 err = vmxnet3_alloc_pci_resources(adapter, &dma64);
2973 if (err < 0)
2974 goto err_alloc_pci;
2975
2976 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
2977 if (ver & 1) {
2978 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_VRRS, 1);
2979 } else {
2980 printk(KERN_ERR "Incompatible h/w version (0x%x) for adapter"
2981 " %s\n", ver, pci_name(pdev));
2982 err = -EBUSY;
2983 goto err_ver;
2984 }
2985
2986 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
2987 if (ver & 1) {
2988 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
2989 } else {
2990 printk(KERN_ERR "Incompatible upt version (0x%x) for "
2991 "adapter %s\n", ver, pci_name(pdev));
2992 err = -EBUSY;
2993 goto err_ver;
2994 }
2995
e101e7dd 2996 SET_NETDEV_DEV(netdev, &pdev->dev);
d1a890fa
SB		 2997 vmxnet3_declare_features(adapter, dma64);
2998
2999 adapter->dev_number = atomic_read(&devices_found);
09c5088e
SB		 3000
3001 adapter->share_intr = irq_share_mode;
3002 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE &&
3003 adapter->num_tx_queues != adapter->num_rx_queues)
3004 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
3005
d1a890fa
SB		 3006 vmxnet3_alloc_intr_resources(adapter);
3007
09c5088e
SB		 3008#ifdef VMXNET3_RSS
3009 if (adapter->num_rx_queues > 1 &&
3010 adapter->intr.type == VMXNET3_IT_MSIX) {
3011 adapter->rss = true;
3012 printk(KERN_INFO "RSS is enabled.\n");
3013 } else {
3014 adapter->rss = false;
3015 }
3016#endif
3017
d1a890fa
SB		 3018 vmxnet3_read_mac_addr(adapter, mac);
3019 memcpy(netdev->dev_addr, mac, netdev->addr_len);
3020
3021 netdev->netdev_ops = &vmxnet3_netdev_ops;
d1a890fa 3022 vmxnet3_set_ethtool_ops(netdev);
09c5088e 3023 netdev->watchdog_timeo = 5 * HZ;
d1a890fa
SB		 3024
3025 INIT_WORK(&adapter->work, vmxnet3_reset_work);
3026
09c5088e
SB		 3027 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3028 int i;
3029 for (i = 0; i < adapter->num_rx_queues; i++) {
3030 netif_napi_add(adapter->netdev,
3031 &adapter->rx_queue[i].napi,
3032 vmxnet3_poll_rx_only, 64);
3033 }
3034 } else {
3035 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
3036 vmxnet3_poll, 64);
3037 }
3038
3039 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
3040 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
3041
d1a890fa
SB		 3042 err = register_netdev(netdev);
3043
3044 if (err) {
3045 printk(KERN_ERR "Failed to register adapter %s\n",
3046 pci_name(pdev));
3047 goto err_register;
3048 }
3049
3050 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
4a1745fc 3051 vmxnet3_check_link(adapter, false);
d1a890fa
SB		 3052 atomic_inc(&devices_found);
3053 return 0;
3054
3055err_register:
3056 vmxnet3_free_intr_resources(adapter);
3057err_ver:
3058 vmxnet3_free_pci_resources(adapter);
3059err_alloc_pci:
09c5088e
SB		 3060#ifdef VMXNET3_RSS
3061 kfree(adapter->rss_conf);
3062err_alloc_rss:
3063#endif
d1a890fa
SB		 3064 kfree(adapter->pm_conf);
3065err_alloc_pm:
09c5088e
SB		 3066 pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
3067 adapter->queue_desc_pa);
d1a890fa
SB		 3068err_alloc_queue_desc:
3069 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
3070 adapter->shared, adapter->shared_pa);
3071err_alloc_shared:
3072 pci_set_drvdata(pdev, NULL);
3073 free_netdev(netdev);
3074 return err;
3075}
3076
3077
3078static void __devexit
3079vmxnet3_remove_device(struct pci_dev *pdev)
3080{
3081 struct net_device *netdev = pci_get_drvdata(pdev);
3082 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
09c5088e
SB		 3083 int size = 0;
3084 int num_rx_queues;
3085
3086#ifdef VMXNET3_RSS
3087 if (enable_mq)
3088 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3089 (int)num_online_cpus());
3090 else
3091#endif
3092 num_rx_queues = 1;
eebb02b1 3093 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
d1a890fa 3094
23f333a2 3095 cancel_work_sync(&adapter->work);
d1a890fa
SB		 3096
3097 unregister_netdev(netdev);
3098
3099 vmxnet3_free_intr_resources(adapter);
3100 vmxnet3_free_pci_resources(adapter);
09c5088e
SB		 3101#ifdef VMXNET3_RSS
3102 kfree(adapter->rss_conf);
3103#endif
d1a890fa 3104 kfree(adapter->pm_conf);
09c5088e
SB		 3105
3106 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3107 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
3108 pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
3109 adapter->queue_desc_pa);
d1a890fa
SB		 3110 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
3111 adapter->shared, adapter->shared_pa);
3112 free_netdev(netdev);
3113}
3114
3115
3116#ifdef CONFIG_PM
3117
3118static int
3119vmxnet3_suspend(struct device *device)
3120{
3121 struct pci_dev *pdev = to_pci_dev(device);
3122 struct net_device *netdev = pci_get_drvdata(pdev);
3123 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3124 struct Vmxnet3_PMConf *pmConf;
3125 struct ethhdr *ehdr;
3126 struct arphdr *ahdr;
3127 u8 *arpreq;
3128 struct in_device *in_dev;
3129 struct in_ifaddr *ifa;
83d0feff 3130 unsigned long flags;
d1a890fa
SB		 3131 int i = 0;
3132
3133 if (!netif_running(netdev))
3134 return 0;
3135
51956cd6
SB		 3136 for (i = 0; i < adapter->num_rx_queues; i++)
3137 napi_disable(&adapter->rx_queue[i].napi);
3138
d1a890fa
SB		 3139 vmxnet3_disable_all_intrs(adapter);
3140 vmxnet3_free_irqs(adapter);
3141 vmxnet3_free_intr_resources(adapter);
3142
3143 netif_device_detach(netdev);
09c5088e 3144 netif_tx_stop_all_queues(netdev);
d1a890fa
SB		 3145
3146 /* Create wake-up filters. */
3147 pmConf = adapter->pm_conf;
3148 memset(pmConf, 0, sizeof(*pmConf));
3149
3150 if (adapter->wol & WAKE_UCAST) {
3151 pmConf->filters[i].patternSize = ETH_ALEN;
3152 pmConf->filters[i].maskSize = 1;
3153 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
3154 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
3155
3843e515 3156 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
d1a890fa
SB		 3157 i++;
3158 }
3159
3160 if (adapter->wol & WAKE_ARP) {
3161 in_dev = in_dev_get(netdev);
3162 if (!in_dev)
3163 goto skip_arp;
3164
3165 ifa = (struct in_ifaddr *)in_dev->ifa_list;
3166 if (!ifa)
3167 goto skip_arp;
3168
3169 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
3170 sizeof(struct arphdr) + /* ARP header */
3171 2 * ETH_ALEN + /* 2 Ethernet addresses*/
3172 2 * sizeof(u32); /*2 IPv4 addresses */
3173 pmConf->filters[i].maskSize =
3174 (pmConf->filters[i].patternSize - 1) / 8 + 1;
3175
3176 /* ETH_P_ARP in Ethernet header. */
3177 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
3178 ehdr->h_proto = htons(ETH_P_ARP);
3179
3180 /* ARPOP_REQUEST in ARP header. */
3181 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
3182 ahdr->ar_op = htons(ARPOP_REQUEST);
3183 arpreq = (u8 *)(ahdr + 1);
3184
3185 /* The Unicast IPv4 address in 'tip' field. */
3186 arpreq += 2 * ETH_ALEN + sizeof(u32);
3187 *(u32 *)arpreq = ifa->ifa_address;
3188
3189 /* The mask for the relevant bits. */
3190 pmConf->filters[i].mask[0] = 0x00;
3191 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
3192 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
3193 pmConf->filters[i].mask[3] = 0x00;
3194 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
3195 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
3196 in_dev_put(in_dev);
3197
3843e515 3198 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
d1a890fa
SB		 3199 i++;
3200 }
3201
3202skip_arp:
3203 if (adapter->wol & WAKE_MAGIC)
3843e515 3204 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
d1a890fa
SB		 3205
3206 pmConf->numFilters = i;
3207
115924b6
SB		 3208 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3209 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3210 *pmConf));
3211 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
3212 pmConf));
d1a890fa 3213
83d0feff 3214 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 3215 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3216 VMXNET3_CMD_UPDATE_PMCFG);
83d0feff 3217 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 3218
3219 pci_save_state(pdev);
3220 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
3221 adapter->wol);
3222 pci_disable_device(pdev);
3223 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
3224
3225 return 0;
3226}
3227
3228
3229static int
3230vmxnet3_resume(struct device *device)
3231{
51956cd6 3232 int err, i = 0;
83d0feff 3233 unsigned long flags;
d1a890fa
SB		 3234 struct pci_dev *pdev = to_pci_dev(device);
3235 struct net_device *netdev = pci_get_drvdata(pdev);
3236 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3237 struct Vmxnet3_PMConf *pmConf;
3238
3239 if (!netif_running(netdev))
3240 return 0;
3241
3242 /* Destroy wake-up filters. */
3243 pmConf = adapter->pm_conf;
3244 memset(pmConf, 0, sizeof(*pmConf));
3245
115924b6
SB		 3246 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3247 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3248 *pmConf));
0561cf3d 3249 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
115924b6 3250 pmConf));
d1a890fa
SB		 3251
3252 netif_device_attach(netdev);
3253 pci_set_power_state(pdev, PCI_D0);
3254 pci_restore_state(pdev);
3255 err = pci_enable_device_mem(pdev);
3256 if (err != 0)
3257 return err;
3258
3259 pci_enable_wake(pdev, PCI_D0, 0);
3260
83d0feff 3261 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 3262 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3263 VMXNET3_CMD_UPDATE_PMCFG);
83d0feff 3264 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 3265 vmxnet3_alloc_intr_resources(adapter);
3266 vmxnet3_request_irqs(adapter);
51956cd6
SB		 3267 for (i = 0; i < adapter->num_rx_queues; i++)
3268 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 3269 vmxnet3_enable_all_intrs(adapter);
3270
3271 return 0;
3272}
3273
47145210 3274static const struct dev_pm_ops vmxnet3_pm_ops = {
d1a890fa
SB		 3275 .suspend = vmxnet3_suspend,
3276 .resume = vmxnet3_resume,
3277};
3278#endif
3279
3280static struct pci_driver vmxnet3_driver = {
3281 .name = vmxnet3_driver_name,
3282 .id_table = vmxnet3_pciid_table,
3283 .probe = vmxnet3_probe_device,
3284 .remove = __devexit_p(vmxnet3_remove_device),
3285#ifdef CONFIG_PM
3286 .driver.pm = &vmxnet3_pm_ops,
3287#endif
3288};
3289
3290
3291static int __init
3292vmxnet3_init_module(void)
3293{
3294 printk(KERN_INFO "%s - version %s\n", VMXNET3_DRIVER_DESC,
3295 VMXNET3_DRIVER_VERSION_REPORT);
3296 return pci_register_driver(&vmxnet3_driver);
3297}
3298
3299module_init(vmxnet3_init_module);
3300
3301
3302static void
3303vmxnet3_exit_module(void)
3304{
3305 pci_unregister_driver(&vmxnet3_driver);
3306}
3307
3308module_exit(vmxnet3_exit_module);
3309
3310MODULE_AUTHOR("VMware, Inc.");
3311MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
3312MODULE_LICENSE("GPL v2");
3313MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);
kernel source for telekom puls (alcatel/mediatek)