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vmxnet3: use netdev_alloc_skb_ip_align
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / vmxnet3 / vmxnet3_drv.c
CommitLineData
d1a890fa
SB		 1/*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
4 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
23 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
24 *
25 */
26
9d9779e7 27#include <linux/module.h>
b038b040
SR		 28#include <net/ip6_checksum.h>
29
d1a890fa
SB		 30#include "vmxnet3_int.h"
31
32char vmxnet3_driver_name[] = "vmxnet3";
33#define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
34
d1a890fa
SB		 35/*
36 * PCI Device ID Table
37 * Last entry must be all 0s
38 */
a3aa1884 39static DEFINE_PCI_DEVICE_TABLE(vmxnet3_pciid_table) = {
d1a890fa
SB		 40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
41 {0}
42};
43
44MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
45
46static atomic_t devices_found;
47
09c5088e
SB		 48#define VMXNET3_MAX_DEVICES 10
49static int enable_mq = 1;
50static int irq_share_mode;
d1a890fa 51
f9f25026
SB		 52static void
53vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
54
d1a890fa
SB		 55/*
56 * Enable/Disable the given intr
57 */
58static void
59vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
60{
61 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
62}
63
64
65static void
66vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
67{
68 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
69}
70
71
72/*
73 * Enable/Disable all intrs used by the device
74 */
75static void
76vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
77{
78 int i;
79
80 for (i = 0; i < adapter->intr.num_intrs; i++)
81 vmxnet3_enable_intr(adapter, i);
6929fe8a
RZ		 82 adapter->shared->devRead.intrConf.intrCtrl &=
83 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 84}
85
86
87static void
88vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
89{
90 int i;
91
6929fe8a
RZ		 92 adapter->shared->devRead.intrConf.intrCtrl |=
93 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 94 for (i = 0; i < adapter->intr.num_intrs; i++)
95 vmxnet3_disable_intr(adapter, i);
96}
97
98
99static void
100vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
101{
102 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
103}
104
105
106static bool
107vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
108{
09c5088e 109 return tq->stopped;
d1a890fa
SB		 110}
111
112
113static void
114vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
115{
116 tq->stopped = false;
09c5088e 117 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
d1a890fa
SB		 118}
119
120
121static void
122vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
123{
124 tq->stopped = false;
09c5088e 125 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
d1a890fa
SB		 126}
127
128
129static void
130vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
131{
132 tq->stopped = true;
133 tq->num_stop++;
09c5088e 134 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
d1a890fa
SB		 135}
136
137
138/*
139 * Check the link state. This may start or stop the tx queue.
140 */
141static void
4a1745fc 142vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
d1a890fa
SB		 143{
144 u32 ret;
09c5088e 145 int i;
83d0feff 146 unsigned long flags;
d1a890fa 147
83d0feff 148 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 149 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
150 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
83d0feff
SB		 151 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
152
d1a890fa
SB		 153 adapter->link_speed = ret >> 16;
154 if (ret & 1) { /* Link is up. */
155 printk(KERN_INFO "%s: NIC Link is Up %d Mbps\n",
156 adapter->netdev->name, adapter->link_speed);
157 if (!netif_carrier_ok(adapter->netdev))
158 netif_carrier_on(adapter->netdev);
159
09c5088e
SB		 160 if (affectTxQueue) {
161 for (i = 0; i < adapter->num_tx_queues; i++)
162 vmxnet3_tq_start(&adapter->tx_queue[i],
163 adapter);
164 }
d1a890fa
SB		 165 } else {
166 printk(KERN_INFO "%s: NIC Link is Down\n",
167 adapter->netdev->name);
168 if (netif_carrier_ok(adapter->netdev))
169 netif_carrier_off(adapter->netdev);
170
09c5088e
SB		 171 if (affectTxQueue) {
172 for (i = 0; i < adapter->num_tx_queues; i++)
173 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
174 }
d1a890fa
SB		 175 }
176}
177
d1a890fa
SB		 178static void
179vmxnet3_process_events(struct vmxnet3_adapter *adapter)
180{
09c5088e 181 int i;
e328d410 182 unsigned long flags;
115924b6 183 u32 events = le32_to_cpu(adapter->shared->ecr);
d1a890fa
SB		 184 if (!events)
185 return;
186
187 vmxnet3_ack_events(adapter, events);
188
189 /* Check if link state has changed */
190 if (events & VMXNET3_ECR_LINK)
4a1745fc 191 vmxnet3_check_link(adapter, true);
d1a890fa
SB		 192
193 /* Check if there is an error on xmit/recv queues */
194 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
e328d410 195 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 196 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
197 VMXNET3_CMD_GET_QUEUE_STATUS);
e328d410 198 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa 199
09c5088e
SB		 200 for (i = 0; i < adapter->num_tx_queues; i++)
201 if (adapter->tqd_start[i].status.stopped)
202 dev_err(&adapter->netdev->dev,
203 "%s: tq[%d] error 0x%x\n",
204 adapter->netdev->name, i, le32_to_cpu(
205 adapter->tqd_start[i].status.error));
206 for (i = 0; i < adapter->num_rx_queues; i++)
207 if (adapter->rqd_start[i].status.stopped)
208 dev_err(&adapter->netdev->dev,
209 "%s: rq[%d] error 0x%x\n",
210 adapter->netdev->name, i,
211 adapter->rqd_start[i].status.error);
d1a890fa
SB		 212
213 schedule_work(&adapter->work);
214 }
215}
216
115924b6
SB		 217#ifdef __BIG_ENDIAN_BITFIELD
218/*
219 * The device expects the bitfields in shared structures to be written in
220 * little endian. When CPU is big endian, the following routines are used to
221 * correctly read and write into ABI.
222 * The general technique used here is : double word bitfields are defined in
223 * opposite order for big endian architecture. Then before reading them in
224 * driver the complete double word is translated using le32_to_cpu. Similarly
225 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
226 * double words into required format.
227 * In order to avoid touching bits in shared structure more than once, temporary
228 * descriptors are used. These are passed as srcDesc to following functions.
229 */
230static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
231 struct Vmxnet3_RxDesc *dstDesc)
232{
233 u32 *src = (u32 *)srcDesc + 2;
234 u32 *dst = (u32 *)dstDesc + 2;
235 dstDesc->addr = le64_to_cpu(srcDesc->addr);
236 *dst = le32_to_cpu(*src);
237 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
238}
239
240static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
241 struct Vmxnet3_TxDesc *dstDesc)
242{
243 int i;
244 u32 *src = (u32 *)(srcDesc + 1);
245 u32 *dst = (u32 *)(dstDesc + 1);
246
247 /* Working backwards so that the gen bit is set at the end. */
248 for (i = 2; i > 0; i--) {
249 src--;
250 dst--;
251 *dst = cpu_to_le32(*src);
252 }
253}
254
255
256static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
257 struct Vmxnet3_RxCompDesc *dstDesc)
258{
259 int i = 0;
260 u32 *src = (u32 *)srcDesc;
261 u32 *dst = (u32 *)dstDesc;
262 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
263 *dst = le32_to_cpu(*src);
264 src++;
265 dst++;
266 }
267}
268
269
270/* Used to read bitfield values from double words. */
271static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
272{
273 u32 temp = le32_to_cpu(*bitfield);
274 u32 mask = ((1 << size) - 1) << pos;
275 temp &= mask;
276 temp >>= pos;
277 return temp;
278}
279
280
281
282#endif /* __BIG_ENDIAN_BITFIELD */
283
284#ifdef __BIG_ENDIAN_BITFIELD
285
286# define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
287 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
288 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
289# define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
290 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
291 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
292# define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
293 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
294 VMXNET3_TCD_GEN_SIZE)
295# define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
296 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
297# define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
298 (dstrcd) = (tmp); \
299 vmxnet3_RxCompToCPU((rcd), (tmp)); \
300 } while (0)
301# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
302 (dstrxd) = (tmp); \
303 vmxnet3_RxDescToCPU((rxd), (tmp)); \
304 } while (0)
305
306#else
307
308# define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
309# define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
310# define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
311# define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
312# define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
313# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
314
315#endif /* __BIG_ENDIAN_BITFIELD */
316
d1a890fa
SB		 317
318static void
319vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
320 struct pci_dev *pdev)
321{
322 if (tbi->map_type == VMXNET3_MAP_SINGLE)
323 pci_unmap_single(pdev, tbi->dma_addr, tbi->len,
324 PCI_DMA_TODEVICE);
325 else if (tbi->map_type == VMXNET3_MAP_PAGE)
326 pci_unmap_page(pdev, tbi->dma_addr, tbi->len,
327 PCI_DMA_TODEVICE);
328 else
329 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
330
331 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
332}
333
334
335static int
336vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
337 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
338{
339 struct sk_buff *skb;
340 int entries = 0;
341
342 /* no out of order completion */
343 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
115924b6 344 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
d1a890fa
SB		 345
346 skb = tq->buf_info[eop_idx].skb;
347 BUG_ON(skb == NULL);
348 tq->buf_info[eop_idx].skb = NULL;
349
350 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
351
352 while (tq->tx_ring.next2comp != eop_idx) {
353 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
354 pdev);
355
356 /* update next2comp w/o tx_lock. Since we are marking more,
357 * instead of less, tx ring entries avail, the worst case is
358 * that the tx routine incorrectly re-queues a pkt due to
359 * insufficient tx ring entries.
360 */
361 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
362 entries++;
363 }
364
365 dev_kfree_skb_any(skb);
366 return entries;
367}
368
369
370static int
371vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
372 struct vmxnet3_adapter *adapter)
373{
374 int completed = 0;
375 union Vmxnet3_GenericDesc *gdesc;
376
377 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
115924b6
SB		 378 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
379 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
380 &gdesc->tcd), tq, adapter->pdev,
381 adapter);
d1a890fa
SB		 382
383 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
384 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
385 }
386
387 if (completed) {
388 spin_lock(&tq->tx_lock);
389 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
390 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
391 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
392 netif_carrier_ok(adapter->netdev))) {
393 vmxnet3_tq_wake(tq, adapter);
394 }
395 spin_unlock(&tq->tx_lock);
396 }
397 return completed;
398}
399
400
401static void
402vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
403 struct vmxnet3_adapter *adapter)
404{
405 int i;
406
407 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
408 struct vmxnet3_tx_buf_info *tbi;
d1a890fa
SB		 409
410 tbi = tq->buf_info + tq->tx_ring.next2comp;
d1a890fa
SB		 411
412 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
413 if (tbi->skb) {
414 dev_kfree_skb_any(tbi->skb);
415 tbi->skb = NULL;
416 }
417 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
418 }
419
420 /* sanity check, verify all buffers are indeed unmapped and freed */
421 for (i = 0; i < tq->tx_ring.size; i++) {
422 BUG_ON(tq->buf_info[i].skb != NULL ||
423 tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
424 }
425
426 tq->tx_ring.gen = VMXNET3_INIT_GEN;
427 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
428
429 tq->comp_ring.gen = VMXNET3_INIT_GEN;
430 tq->comp_ring.next2proc = 0;
431}
432
433
09c5088e 434static void
d1a890fa
SB		 435vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
436 struct vmxnet3_adapter *adapter)
437{
438 if (tq->tx_ring.base) {
439 pci_free_consistent(adapter->pdev, tq->tx_ring.size *
440 sizeof(struct Vmxnet3_TxDesc),
441 tq->tx_ring.base, tq->tx_ring.basePA);
442 tq->tx_ring.base = NULL;
443 }
444 if (tq->data_ring.base) {
445 pci_free_consistent(adapter->pdev, tq->data_ring.size *
446 sizeof(struct Vmxnet3_TxDataDesc),
447 tq->data_ring.base, tq->data_ring.basePA);
448 tq->data_ring.base = NULL;
449 }
450 if (tq->comp_ring.base) {
451 pci_free_consistent(adapter->pdev, tq->comp_ring.size *
452 sizeof(struct Vmxnet3_TxCompDesc),
453 tq->comp_ring.base, tq->comp_ring.basePA);
454 tq->comp_ring.base = NULL;
455 }
456 kfree(tq->buf_info);
457 tq->buf_info = NULL;
458}
459
460
09c5088e
SB		 461/* Destroy all tx queues */
462void
463vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
464{
465 int i;
466
467 for (i = 0; i < adapter->num_tx_queues; i++)
468 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
469}
470
471
d1a890fa
SB		 472static void
473vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
474 struct vmxnet3_adapter *adapter)
475{
476 int i;
477
478 /* reset the tx ring contents to 0 and reset the tx ring states */
479 memset(tq->tx_ring.base, 0, tq->tx_ring.size *
480 sizeof(struct Vmxnet3_TxDesc));
481 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
482 tq->tx_ring.gen = VMXNET3_INIT_GEN;
483
484 memset(tq->data_ring.base, 0, tq->data_ring.size *
485 sizeof(struct Vmxnet3_TxDataDesc));
486
487 /* reset the tx comp ring contents to 0 and reset comp ring states */
488 memset(tq->comp_ring.base, 0, tq->comp_ring.size *
489 sizeof(struct Vmxnet3_TxCompDesc));
490 tq->comp_ring.next2proc = 0;
491 tq->comp_ring.gen = VMXNET3_INIT_GEN;
492
493 /* reset the bookkeeping data */
494 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
495 for (i = 0; i < tq->tx_ring.size; i++)
496 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
497
498 /* stats are not reset */
499}
500
501
502static int
503vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
504 struct vmxnet3_adapter *adapter)
505{
506 BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
507 tq->comp_ring.base || tq->buf_info);
508
509 tq->tx_ring.base = pci_alloc_consistent(adapter->pdev, tq->tx_ring.size
510 * sizeof(struct Vmxnet3_TxDesc),
511 &tq->tx_ring.basePA);
512 if (!tq->tx_ring.base) {
513 printk(KERN_ERR "%s: failed to allocate tx ring\n",
514 adapter->netdev->name);
515 goto err;
516 }
517
518 tq->data_ring.base = pci_alloc_consistent(adapter->pdev,
519 tq->data_ring.size *
520 sizeof(struct Vmxnet3_TxDataDesc),
521 &tq->data_ring.basePA);
522 if (!tq->data_ring.base) {
523 printk(KERN_ERR "%s: failed to allocate data ring\n",
524 adapter->netdev->name);
525 goto err;
526 }
527
528 tq->comp_ring.base = pci_alloc_consistent(adapter->pdev,
529 tq->comp_ring.size *
530 sizeof(struct Vmxnet3_TxCompDesc),
531 &tq->comp_ring.basePA);
532 if (!tq->comp_ring.base) {
533 printk(KERN_ERR "%s: failed to allocate tx comp ring\n",
534 adapter->netdev->name);
535 goto err;
536 }
537
538 tq->buf_info = kcalloc(tq->tx_ring.size, sizeof(tq->buf_info[0]),
539 GFP_KERNEL);
e404decb 540 if (!tq->buf_info)
d1a890fa 541 goto err;
d1a890fa
SB		 542
543 return 0;
544
545err:
546 vmxnet3_tq_destroy(tq, adapter);
547 return -ENOMEM;
548}
549
09c5088e
SB		 550static void
551vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
552{
553 int i;
554
555 for (i = 0; i < adapter->num_tx_queues; i++)
556 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
557}
d1a890fa
SB		 558
559/*
560 * starting from ring->next2fill, allocate rx buffers for the given ring
561 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
562 * are allocated or allocation fails
563 */
564
565static int
566vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
567 int num_to_alloc, struct vmxnet3_adapter *adapter)
568{
569 int num_allocated = 0;
570 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
571 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
572 u32 val;
573
5318d809 574 while (num_allocated <= num_to_alloc) {
d1a890fa
SB		 575 struct vmxnet3_rx_buf_info *rbi;
576 union Vmxnet3_GenericDesc *gd;
577
578 rbi = rbi_base + ring->next2fill;
579 gd = ring->base + ring->next2fill;
580
581 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
582 if (rbi->skb == NULL) {
0d735f13
SH		 583 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev,
584 rbi->len,
585 GFP_KERNEL);
d1a890fa
SB		 586 if (unlikely(rbi->skb == NULL)) {
587 rq->stats.rx_buf_alloc_failure++;
588 break;
589 }
d1a890fa 590
d1a890fa
SB		 591 rbi->dma_addr = pci_map_single(adapter->pdev,
592 rbi->skb->data, rbi->len,
593 PCI_DMA_FROMDEVICE);
594 } else {
595 /* rx buffer skipped by the device */
596 }
597 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
598 } else {
599 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
600 rbi->len != PAGE_SIZE);
601
602 if (rbi->page == NULL) {
603 rbi->page = alloc_page(GFP_ATOMIC);
604 if (unlikely(rbi->page == NULL)) {
605 rq->stats.rx_buf_alloc_failure++;
606 break;
607 }
608 rbi->dma_addr = pci_map_page(adapter->pdev,
609 rbi->page, 0, PAGE_SIZE,
610 PCI_DMA_FROMDEVICE);
611 } else {
612 /* rx buffers skipped by the device */
613 }
614 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
615 }
616
617 BUG_ON(rbi->dma_addr == 0);
115924b6 618 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
5318d809 619 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
115924b6 620 | val | rbi->len);
d1a890fa 621
5318d809
SB		 622 /* Fill the last buffer but dont mark it ready, or else the
623 * device will think that the queue is full */
624 if (num_allocated == num_to_alloc)
625 break;
626
627 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
d1a890fa
SB		 628 num_allocated++;
629 vmxnet3_cmd_ring_adv_next2fill(ring);
630 }
631 rq->uncommitted[ring_idx] += num_allocated;
632
f6965582
RD		 633 dev_dbg(&adapter->netdev->dev,
634 "alloc_rx_buf: %d allocated, next2fill %u, next2comp "
c3ca881f 635 "%u, uncommitted %u\n", num_allocated, ring->next2fill,
d1a890fa
SB		 636 ring->next2comp, rq->uncommitted[ring_idx]);
637
638 /* so that the device can distinguish a full ring and an empty ring */
639 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
640
641 return num_allocated;
642}
643
644
645static void
646vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
647 struct vmxnet3_rx_buf_info *rbi)
648{
649 struct skb_frag_struct *frag = skb_shinfo(skb)->frags +
650 skb_shinfo(skb)->nr_frags;
651
652 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
653
0e0634d2 654 __skb_frag_set_page(frag, rbi->page);
d1a890fa 655 frag->page_offset = 0;
9e903e08
ED		 656 skb_frag_size_set(frag, rcd->len);
657 skb->data_len += rcd->len;
5e6c355c 658 skb->truesize += PAGE_SIZE;
d1a890fa
SB		 659 skb_shinfo(skb)->nr_frags++;
660}
661
662
663static void
664vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
665 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
666 struct vmxnet3_adapter *adapter)
667{
668 u32 dw2, len;
669 unsigned long buf_offset;
670 int i;
671 union Vmxnet3_GenericDesc *gdesc;
672 struct vmxnet3_tx_buf_info *tbi = NULL;
673
674 BUG_ON(ctx->copy_size > skb_headlen(skb));
675
676 /* use the previous gen bit for the SOP desc */
677 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
678
679 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
680 gdesc = ctx->sop_txd; /* both loops below can be skipped */
681
682 /* no need to map the buffer if headers are copied */
683 if (ctx->copy_size) {
115924b6 684 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
d1a890fa 685 tq->tx_ring.next2fill *
115924b6
SB		 686 sizeof(struct Vmxnet3_TxDataDesc));
687 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
d1a890fa
SB		 688 ctx->sop_txd->dword[3] = 0;
689
690 tbi = tq->buf_info + tq->tx_ring.next2fill;
691 tbi->map_type = VMXNET3_MAP_NONE;
692
f6965582
RD		 693 dev_dbg(&adapter->netdev->dev,
694 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
115924b6
SB		 695 tq->tx_ring.next2fill,
696 le64_to_cpu(ctx->sop_txd->txd.addr),
d1a890fa
SB		 697 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
698 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
699
700 /* use the right gen for non-SOP desc */
701 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
702 }
703
704 /* linear part can use multiple tx desc if it's big */
705 len = skb_headlen(skb) - ctx->copy_size;
706 buf_offset = ctx->copy_size;
707 while (len) {
708 u32 buf_size;
709
1f4b1612
BD		 710 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
711 buf_size = len;
712 dw2 |= len;
713 } else {
714 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
715 /* spec says that for TxDesc.len, 0 == 2^14 */
716 }
d1a890fa
SB		 717
718 tbi = tq->buf_info + tq->tx_ring.next2fill;
719 tbi->map_type = VMXNET3_MAP_SINGLE;
720 tbi->dma_addr = pci_map_single(adapter->pdev,
721 skb->data + buf_offset, buf_size,
722 PCI_DMA_TODEVICE);
723
1f4b1612 724 tbi->len = buf_size;
d1a890fa
SB		 725
726 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
727 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
728
115924b6 729 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
1f4b1612 730 gdesc->dword[2] = cpu_to_le32(dw2);
d1a890fa
SB		 731 gdesc->dword[3] = 0;
732
f6965582
RD		 733 dev_dbg(&adapter->netdev->dev,
734 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
115924b6
SB		 735 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
736 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
d1a890fa
SB		 737 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
738 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
739
740 len -= buf_size;
741 buf_offset += buf_size;
742 }
743
744 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9e903e08 745 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
a4d7e485 746 u32 buf_size;
d1a890fa 747
a4d7e485
ED		 748 buf_offset = 0;
749 len = skb_frag_size(frag);
750 while (len) {
751 tbi = tq->buf_info + tq->tx_ring.next2fill;
752 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
753 buf_size = len;
754 dw2 |= len;
755 } else {
756 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
757 /* spec says that for TxDesc.len, 0 == 2^14 */
758 }
759 tbi->map_type = VMXNET3_MAP_PAGE;
760 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag,
761 buf_offset, buf_size,
762 DMA_TO_DEVICE);
d1a890fa 763
a4d7e485 764 tbi->len = buf_size;
d1a890fa 765
a4d7e485
ED		 766 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
767 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
d1a890fa 768
a4d7e485
ED		 769 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
770 gdesc->dword[2] = cpu_to_le32(dw2);
771 gdesc->dword[3] = 0;
d1a890fa 772
a4d7e485
ED		 773 dev_dbg(&adapter->netdev->dev,
774 "txd[%u]: 0x%llu %u %u\n",
775 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
776 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
777 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
778 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
779
780 len -= buf_size;
781 buf_offset += buf_size;
782 }
d1a890fa
SB		 783 }
784
785 ctx->eop_txd = gdesc;
786
787 /* set the last buf_info for the pkt */
788 tbi->skb = skb;
789 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
790}
791
792
09c5088e
SB		 793/* Init all tx queues */
794static void
795vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
796{
797 int i;
798
799 for (i = 0; i < adapter->num_tx_queues; i++)
800 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
801}
802
803
d1a890fa
SB		 804/*
805 * parse and copy relevant protocol headers:
806 * For a tso pkt, relevant headers are L2/3/4 including options
807 * For a pkt requesting csum offloading, they are L2/3 and may include L4
808 * if it's a TCP/UDP pkt
809 *
810 * Returns:
811 * -1: error happens during parsing
812 * 0: protocol headers parsed, but too big to be copied
813 * 1: protocol headers parsed and copied
814 *
815 * Other effects:
816 * 1. related *ctx fields are updated.
817 * 2. ctx->copy_size is # of bytes copied
818 * 3. the portion copied is guaranteed to be in the linear part
819 *
820 */
821static int
822vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
823 struct vmxnet3_tx_ctx *ctx,
824 struct vmxnet3_adapter *adapter)
825{
826 struct Vmxnet3_TxDataDesc *tdd;
827
0d0b1672 828 if (ctx->mss) { /* TSO */
d1a890fa 829 ctx->eth_ip_hdr_size = skb_transport_offset(skb);
8bca5d1e 830 ctx->l4_hdr_size = tcp_hdrlen(skb);
d1a890fa
SB		 831 ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size;
832 } else {
d1a890fa 833 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 834 ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb);
d1a890fa
SB		 835
836 if (ctx->ipv4) {
8bca5d1e
ED		 837 const struct iphdr *iph = ip_hdr(skb);
838
39d4a96f 839 if (iph->protocol == IPPROTO_TCP)
8bca5d1e 840 ctx->l4_hdr_size = tcp_hdrlen(skb);
39d4a96f 841 else if (iph->protocol == IPPROTO_UDP)
f6a1ad42 842 ctx->l4_hdr_size = sizeof(struct udphdr);
39d4a96f 843 else
d1a890fa 844 ctx->l4_hdr_size = 0;
d1a890fa
SB		 845 } else {
846 /* for simplicity, don't copy L4 headers */
847 ctx->l4_hdr_size = 0;
848 }
b203262d
NH		 849 ctx->copy_size = min(ctx->eth_ip_hdr_size +
850 ctx->l4_hdr_size, skb->len);
d1a890fa
SB		 851 } else {
852 ctx->eth_ip_hdr_size = 0;
853 ctx->l4_hdr_size = 0;
854 /* copy as much as allowed */
855 ctx->copy_size = min((unsigned int)VMXNET3_HDR_COPY_SIZE
856 , skb_headlen(skb));
857 }
858
859 /* make sure headers are accessible directly */
860 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
861 goto err;
862 }
863
864 if (unlikely(ctx->copy_size > VMXNET3_HDR_COPY_SIZE)) {
865 tq->stats.oversized_hdr++;
866 ctx->copy_size = 0;
867 return 0;
868 }
869
870 tdd = tq->data_ring.base + tq->tx_ring.next2fill;
871
872 memcpy(tdd->data, skb->data, ctx->copy_size);
f6965582
RD		 873 dev_dbg(&adapter->netdev->dev,
874 "copy %u bytes to dataRing[%u]\n",
d1a890fa
SB		 875 ctx->copy_size, tq->tx_ring.next2fill);
876 return 1;
877
878err:
879 return -1;
880}
881
882
883static void
884vmxnet3_prepare_tso(struct sk_buff *skb,
885 struct vmxnet3_tx_ctx *ctx)
886{
8bca5d1e
ED		 887 struct tcphdr *tcph = tcp_hdr(skb);
888
d1a890fa 889 if (ctx->ipv4) {
8bca5d1e
ED		 890 struct iphdr *iph = ip_hdr(skb);
891
d1a890fa
SB		 892 iph->check = 0;
893 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
894 IPPROTO_TCP, 0);
895 } else {
8bca5d1e
ED		 896 struct ipv6hdr *iph = ipv6_hdr(skb);
897
d1a890fa
SB		 898 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
899 IPPROTO_TCP, 0);
900 }
901}
902
a4d7e485
ED		 903static int txd_estimate(const struct sk_buff *skb)
904{
905 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
906 int i;
907
908 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
909 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
910
911 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag));
912 }
913 return count;
914}
d1a890fa
SB		 915
916/*
917 * Transmits a pkt thru a given tq
918 * Returns:
919 * NETDEV_TX_OK: descriptors are setup successfully
25985edc 920 * NETDEV_TX_OK: error occurred, the pkt is dropped
d1a890fa
SB		 921 * NETDEV_TX_BUSY: tx ring is full, queue is stopped
922 *
923 * Side-effects:
924 * 1. tx ring may be changed
925 * 2. tq stats may be updated accordingly
926 * 3. shared->txNumDeferred may be updated
927 */
928
929static int
930vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
931 struct vmxnet3_adapter *adapter, struct net_device *netdev)
932{
933 int ret;
934 u32 count;
935 unsigned long flags;
936 struct vmxnet3_tx_ctx ctx;
937 union Vmxnet3_GenericDesc *gdesc;
115924b6
SB		 938#ifdef __BIG_ENDIAN_BITFIELD
939 /* Use temporary descriptor to avoid touching bits multiple times */
940 union Vmxnet3_GenericDesc tempTxDesc;
941#endif
d1a890fa 942
a4d7e485 943 count = txd_estimate(skb);
d1a890fa 944
72e85c45 945 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
d1a890fa
SB		 946
947 ctx.mss = skb_shinfo(skb)->gso_size;
948 if (ctx.mss) {
949 if (skb_header_cloned(skb)) {
950 if (unlikely(pskb_expand_head(skb, 0, 0,
951 GFP_ATOMIC) != 0)) {
952 tq->stats.drop_tso++;
953 goto drop_pkt;
954 }
955 tq->stats.copy_skb_header++;
956 }
957 vmxnet3_prepare_tso(skb, &ctx);
958 } else {
959 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
960
961 /* non-tso pkts must not use more than
962 * VMXNET3_MAX_TXD_PER_PKT entries
963 */
964 if (skb_linearize(skb) != 0) {
965 tq->stats.drop_too_many_frags++;
966 goto drop_pkt;
967 }
968 tq->stats.linearized++;
969
970 /* recalculate the # of descriptors to use */
971 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
972 }
973 }
974
09c5088e
SB		 975 spin_lock_irqsave(&tq->tx_lock, flags);
976
977 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
978 tq->stats.tx_ring_full++;
979 dev_dbg(&adapter->netdev->dev,
980 "tx queue stopped on %s, next2comp %u"
981 " next2fill %u\n", adapter->netdev->name,
982 tq->tx_ring.next2comp, tq->tx_ring.next2fill);
983
984 vmxnet3_tq_stop(tq, adapter);
985 spin_unlock_irqrestore(&tq->tx_lock, flags);
986 return NETDEV_TX_BUSY;
987 }
988
989
d1a890fa
SB		 990 ret = vmxnet3_parse_and_copy_hdr(skb, tq, &ctx, adapter);
991 if (ret >= 0) {
992 BUG_ON(ret <= 0 && ctx.copy_size != 0);
993 /* hdrs parsed, check against other limits */
994 if (ctx.mss) {
995 if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size >
996 VMXNET3_MAX_TX_BUF_SIZE)) {
997 goto hdr_too_big;
998 }
999 } else {
1000 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1001 if (unlikely(ctx.eth_ip_hdr_size +
1002 skb->csum_offset >
1003 VMXNET3_MAX_CSUM_OFFSET)) {
1004 goto hdr_too_big;
1005 }
1006 }
1007 }
1008 } else {
1009 tq->stats.drop_hdr_inspect_err++;
f955e141 1010 goto unlock_drop_pkt;
d1a890fa
SB		 1011 }
1012
d1a890fa
SB		 1013 /* fill tx descs related to addr & len */
1014 vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter);
1015
1016 /* setup the EOP desc */
115924b6 1017 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
d1a890fa
SB		 1018
1019 /* setup the SOP desc */
115924b6
SB		 1020#ifdef __BIG_ENDIAN_BITFIELD
1021 gdesc = &tempTxDesc;
1022 gdesc->dword[2] = ctx.sop_txd->dword[2];
1023 gdesc->dword[3] = ctx.sop_txd->dword[3];
1024#else
d1a890fa 1025 gdesc = ctx.sop_txd;
115924b6 1026#endif
d1a890fa
SB		 1027 if (ctx.mss) {
1028 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size;
1029 gdesc->txd.om = VMXNET3_OM_TSO;
1030 gdesc->txd.msscof = ctx.mss;
115924b6
SB		 1031 le32_add_cpu(&tq->shared->txNumDeferred, (skb->len -
1032 gdesc->txd.hlen + ctx.mss - 1) / ctx.mss);
d1a890fa
SB		 1033 } else {
1034 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1035 gdesc->txd.hlen = ctx.eth_ip_hdr_size;
1036 gdesc->txd.om = VMXNET3_OM_CSUM;
1037 gdesc->txd.msscof = ctx.eth_ip_hdr_size +
1038 skb->csum_offset;
1039 } else {
1040 gdesc->txd.om = 0;
1041 gdesc->txd.msscof = 0;
1042 }
115924b6 1043 le32_add_cpu(&tq->shared->txNumDeferred, 1);
d1a890fa
SB		 1044 }
1045
1046 if (vlan_tx_tag_present(skb)) {
1047 gdesc->txd.ti = 1;
1048 gdesc->txd.tci = vlan_tx_tag_get(skb);
1049 }
1050
115924b6
SB		 1051 /* finally flips the GEN bit of the SOP desc. */
1052 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1053 VMXNET3_TXD_GEN);
1054#ifdef __BIG_ENDIAN_BITFIELD
1055 /* Finished updating in bitfields of Tx Desc, so write them in original
1056 * place.
1057 */
1058 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1059 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1060 gdesc = ctx.sop_txd;
1061#endif
f6965582
RD		 1062 dev_dbg(&adapter->netdev->dev,
1063 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
c2fd03a0 1064 (u32)(ctx.sop_txd -
115924b6
SB		 1065 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1066 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
d1a890fa
SB		 1067
1068 spin_unlock_irqrestore(&tq->tx_lock, flags);
1069
115924b6
SB		 1070 if (le32_to_cpu(tq->shared->txNumDeferred) >=
1071 le32_to_cpu(tq->shared->txThreshold)) {
d1a890fa 1072 tq->shared->txNumDeferred = 0;
09c5088e
SB		 1073 VMXNET3_WRITE_BAR0_REG(adapter,
1074 VMXNET3_REG_TXPROD + tq->qid * 8,
d1a890fa
SB		 1075 tq->tx_ring.next2fill);
1076 }
d1a890fa
SB		 1077
1078 return NETDEV_TX_OK;
1079
1080hdr_too_big:
1081 tq->stats.drop_oversized_hdr++;
f955e141
DC		 1082unlock_drop_pkt:
1083 spin_unlock_irqrestore(&tq->tx_lock, flags);
d1a890fa
SB		 1084drop_pkt:
1085 tq->stats.drop_total++;
1086 dev_kfree_skb(skb);
1087 return NETDEV_TX_OK;
1088}
1089
1090
1091static netdev_tx_t
1092vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1093{
1094 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1095
96800ee7 1096 BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1097 return vmxnet3_tq_xmit(skb,
1098 &adapter->tx_queue[skb->queue_mapping],
1099 adapter, netdev);
d1a890fa
SB		 1100}
1101
1102
1103static void
1104vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1105 struct sk_buff *skb,
1106 union Vmxnet3_GenericDesc *gdesc)
1107{
a0d2730c 1108 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
d1a890fa 1109 /* typical case: TCP/UDP over IP and both csums are correct */
115924b6 1110 if ((le32_to_cpu(gdesc->dword[3]) & VMXNET3_RCD_CSUM_OK) ==
d1a890fa
SB		 1111 VMXNET3_RCD_CSUM_OK) {
1112 skb->ip_summed = CHECKSUM_UNNECESSARY;
1113 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
1114 BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6));
1115 BUG_ON(gdesc->rcd.frg);
1116 } else {
1117 if (gdesc->rcd.csum) {
1118 skb->csum = htons(gdesc->rcd.csum);
1119 skb->ip_summed = CHECKSUM_PARTIAL;
1120 } else {
bc8acf2c 1121 skb_checksum_none_assert(skb);
d1a890fa
SB		 1122 }
1123 }
1124 } else {
bc8acf2c 1125 skb_checksum_none_assert(skb);
d1a890fa
SB		 1126 }
1127}
1128
1129
1130static void
1131vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1132 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
1133{
1134 rq->stats.drop_err++;
1135 if (!rcd->fcs)
1136 rq->stats.drop_fcs++;
1137
1138 rq->stats.drop_total++;
1139
1140 /*
1141 * We do not unmap and chain the rx buffer to the skb.
1142 * We basically pretend this buffer is not used and will be recycled
1143 * by vmxnet3_rq_alloc_rx_buf()
1144 */
1145
1146 /*
1147 * ctx->skb may be NULL if this is the first and the only one
1148 * desc for the pkt
1149 */
1150 if (ctx->skb)
1151 dev_kfree_skb_irq(ctx->skb);
1152
1153 ctx->skb = NULL;
1154}
1155
1156
1157static int
1158vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1159 struct vmxnet3_adapter *adapter, int quota)
1160{
215faf9c
JP		 1161 static const u32 rxprod_reg[2] = {
1162 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
1163 };
d1a890fa 1164 u32 num_rxd = 0;
5318d809 1165 bool skip_page_frags = false;
d1a890fa
SB		 1166 struct Vmxnet3_RxCompDesc *rcd;
1167 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
115924b6
SB		 1168#ifdef __BIG_ENDIAN_BITFIELD
1169 struct Vmxnet3_RxDesc rxCmdDesc;
1170 struct Vmxnet3_RxCompDesc rxComp;
1171#endif
1172 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1173 &rxComp);
d1a890fa
SB		 1174 while (rcd->gen == rq->comp_ring.gen) {
1175 struct vmxnet3_rx_buf_info *rbi;
5318d809
SB		 1176 struct sk_buff *skb, *new_skb = NULL;
1177 struct page *new_page = NULL;
d1a890fa
SB		 1178 int num_to_alloc;
1179 struct Vmxnet3_RxDesc *rxd;
1180 u32 idx, ring_idx;
5318d809 1181 struct vmxnet3_cmd_ring *ring = NULL;
d1a890fa
SB		 1182 if (num_rxd >= quota) {
1183 /* we may stop even before we see the EOP desc of
1184 * the current pkt
1185 */
1186 break;
1187 }
1188 num_rxd++;
09c5088e 1189 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2);
d1a890fa 1190 idx = rcd->rxdIdx;
09c5088e 1191 ring_idx = rcd->rqID < adapter->num_rx_queues ? 0 : 1;
5318d809 1192 ring = rq->rx_ring + ring_idx;
115924b6
SB		 1193 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1194 &rxCmdDesc);
d1a890fa
SB		 1195 rbi = rq->buf_info[ring_idx] + idx;
1196
115924b6
SB		 1197 BUG_ON(rxd->addr != rbi->dma_addr ||
1198 rxd->len != rbi->len);
d1a890fa
SB		 1199
1200 if (unlikely(rcd->eop && rcd->err)) {
1201 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1202 goto rcd_done;
1203 }
1204
1205 if (rcd->sop) { /* first buf of the pkt */
1206 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
1207 rcd->rqID != rq->qid);
1208
1209 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
1210 BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1211
1212 if (unlikely(rcd->len == 0)) {
1213 /* Pretend the rx buffer is skipped. */
1214 BUG_ON(!(rcd->sop && rcd->eop));
f6965582
RD		 1215 dev_dbg(&adapter->netdev->dev,
1216 "rxRing[%u][%u] 0 length\n",
d1a890fa
SB		 1217 ring_idx, idx);
1218 goto rcd_done;
1219 }
1220
5318d809 1221 skip_page_frags = false;
d1a890fa 1222 ctx->skb = rbi->skb;
0d735f13
SH		 1223 new_skb = netdev_alloc_skb_ip_align(adapter->netdev,
1224 rbi->len);
5318d809
SB		 1225 if (new_skb == NULL) {
1226 /* Skb allocation failed, do not handover this
1227 * skb to stack. Reuse it. Drop the existing pkt
1228 */
1229 rq->stats.rx_buf_alloc_failure++;
1230 ctx->skb = NULL;
1231 rq->stats.drop_total++;
1232 skip_page_frags = true;
1233 goto rcd_done;
1234 }
d1a890fa
SB		 1235
1236 pci_unmap_single(adapter->pdev, rbi->dma_addr, rbi->len,
1237 PCI_DMA_FROMDEVICE);
1238
1239 skb_put(ctx->skb, rcd->len);
5318d809
SB		 1240
1241 /* Immediate refill */
5318d809
SB		 1242 rbi->skb = new_skb;
1243 rbi->dma_addr = pci_map_single(adapter->pdev,
96800ee7 1244 rbi->skb->data, rbi->len,
1245 PCI_DMA_FROMDEVICE);
5318d809
SB		 1246 rxd->addr = cpu_to_le64(rbi->dma_addr);
1247 rxd->len = rbi->len;
1248
d1a890fa 1249 } else {
5318d809
SB		 1250 BUG_ON(ctx->skb == NULL && !skip_page_frags);
1251
d1a890fa 1252 /* non SOP buffer must be type 1 in most cases */
5318d809
SB		 1253 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
1254 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
d1a890fa 1255
5318d809
SB		 1256 /* If an sop buffer was dropped, skip all
1257 * following non-sop fragments. They will be reused.
1258 */
1259 if (skip_page_frags)
1260 goto rcd_done;
d1a890fa 1261
5318d809
SB		 1262 new_page = alloc_page(GFP_ATOMIC);
1263 if (unlikely(new_page == NULL)) {
1264 /* Replacement page frag could not be allocated.
1265 * Reuse this page. Drop the pkt and free the
1266 * skb which contained this page as a frag. Skip
1267 * processing all the following non-sop frags.
d1a890fa 1268 */
5318d809
SB		 1269 rq->stats.rx_buf_alloc_failure++;
1270 dev_kfree_skb(ctx->skb);
1271 ctx->skb = NULL;
1272 skip_page_frags = true;
1273 goto rcd_done;
1274 }
1275
1276 if (rcd->len) {
1277 pci_unmap_page(adapter->pdev,
1278 rbi->dma_addr, rbi->len,
1279 PCI_DMA_FROMDEVICE);
1280
1281 vmxnet3_append_frag(ctx->skb, rcd, rbi);
d1a890fa 1282 }
5318d809
SB		 1283
1284 /* Immediate refill */
1285 rbi->page = new_page;
1286 rbi->dma_addr = pci_map_page(adapter->pdev, rbi->page,
1287 0, PAGE_SIZE,
1288 PCI_DMA_FROMDEVICE);
1289 rxd->addr = cpu_to_le64(rbi->dma_addr);
1290 rxd->len = rbi->len;
d1a890fa
SB		 1291 }
1292
5318d809 1293
d1a890fa
SB		 1294 skb = ctx->skb;
1295 if (rcd->eop) {
1296 skb->len += skb->data_len;
d1a890fa
SB		 1297
1298 vmxnet3_rx_csum(adapter, skb,
1299 (union Vmxnet3_GenericDesc *)rcd);
1300 skb->protocol = eth_type_trans(skb, adapter->netdev);
1301
72e85c45
JG		 1302 if (unlikely(rcd->ts))
1303 __vlan_hwaccel_put_tag(skb, rcd->tci);
1304
213ade8c
JG		 1305 if (adapter->netdev->features & NETIF_F_LRO)
1306 netif_receive_skb(skb);
1307 else
1308 napi_gro_receive(&rq->napi, skb);
d1a890fa 1309
d1a890fa
SB		 1310 ctx->skb = NULL;
1311 }
1312
1313rcd_done:
5318d809
SB		 1314 /* device may have skipped some rx descs */
1315 ring->next2comp = idx;
1316 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
1317 ring = rq->rx_ring + ring_idx;
1318 while (num_to_alloc) {
1319 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
1320 &rxCmdDesc);
1321 BUG_ON(!rxd->addr);
1322
1323 /* Recv desc is ready to be used by the device */
1324 rxd->gen = ring->gen;
1325 vmxnet3_cmd_ring_adv_next2fill(ring);
1326 num_to_alloc--;
1327 }
1328
1329 /* if needed, update the register */
1330 if (unlikely(rq->shared->updateRxProd)) {
1331 VMXNET3_WRITE_BAR0_REG(adapter,
96800ee7 1332 rxprod_reg[ring_idx] + rq->qid * 8,
1333 ring->next2fill);
5318d809 1334 rq->uncommitted[ring_idx] = 0;
d1a890fa
SB		 1335 }
1336
1337 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
115924b6 1338 vmxnet3_getRxComp(rcd,
96800ee7 1339 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
d1a890fa
SB		 1340 }
1341
1342 return num_rxd;
1343}
1344
1345
1346static void
1347vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1348 struct vmxnet3_adapter *adapter)
1349{
1350 u32 i, ring_idx;
1351 struct Vmxnet3_RxDesc *rxd;
1352
1353 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1354 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
115924b6
SB		 1355#ifdef __BIG_ENDIAN_BITFIELD
1356 struct Vmxnet3_RxDesc rxDesc;
1357#endif
1358 vmxnet3_getRxDesc(rxd,
1359 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
d1a890fa
SB		 1360
1361 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1362 rq->buf_info[ring_idx][i].skb) {
1363 pci_unmap_single(adapter->pdev, rxd->addr,
1364 rxd->len, PCI_DMA_FROMDEVICE);
1365 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1366 rq->buf_info[ring_idx][i].skb = NULL;
1367 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1368 rq->buf_info[ring_idx][i].page) {
1369 pci_unmap_page(adapter->pdev, rxd->addr,
1370 rxd->len, PCI_DMA_FROMDEVICE);
1371 put_page(rq->buf_info[ring_idx][i].page);
1372 rq->buf_info[ring_idx][i].page = NULL;
1373 }
1374 }
1375
1376 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1377 rq->rx_ring[ring_idx].next2fill =
1378 rq->rx_ring[ring_idx].next2comp = 0;
1379 rq->uncommitted[ring_idx] = 0;
1380 }
1381
1382 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1383 rq->comp_ring.next2proc = 0;
1384}
1385
1386
09c5088e
SB		 1387static void
1388vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1389{
1390 int i;
1391
1392 for (i = 0; i < adapter->num_rx_queues; i++)
1393 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1394}
1395
1396
d1a890fa
SB		 1397void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1398 struct vmxnet3_adapter *adapter)
1399{
1400 int i;
1401 int j;
1402
1403 /* all rx buffers must have already been freed */
1404 for (i = 0; i < 2; i++) {
1405 if (rq->buf_info[i]) {
1406 for (j = 0; j < rq->rx_ring[i].size; j++)
1407 BUG_ON(rq->buf_info[i][j].page != NULL);
1408 }
1409 }
1410
1411
1412 kfree(rq->buf_info[0]);
1413
1414 for (i = 0; i < 2; i++) {
1415 if (rq->rx_ring[i].base) {
1416 pci_free_consistent(adapter->pdev, rq->rx_ring[i].size
1417 * sizeof(struct Vmxnet3_RxDesc),
1418 rq->rx_ring[i].base,
1419 rq->rx_ring[i].basePA);
1420 rq->rx_ring[i].base = NULL;
1421 }
1422 rq->buf_info[i] = NULL;
1423 }
1424
1425 if (rq->comp_ring.base) {
1426 pci_free_consistent(adapter->pdev, rq->comp_ring.size *
1427 sizeof(struct Vmxnet3_RxCompDesc),
1428 rq->comp_ring.base, rq->comp_ring.basePA);
1429 rq->comp_ring.base = NULL;
1430 }
1431}
1432
1433
1434static int
1435vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
1436 struct vmxnet3_adapter *adapter)
1437{
1438 int i;
1439
1440 /* initialize buf_info */
1441 for (i = 0; i < rq->rx_ring[0].size; i++) {
1442
1443 /* 1st buf for a pkt is skbuff */
1444 if (i % adapter->rx_buf_per_pkt == 0) {
1445 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
1446 rq->buf_info[0][i].len = adapter->skb_buf_size;
1447 } else { /* subsequent bufs for a pkt is frag */
1448 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
1449 rq->buf_info[0][i].len = PAGE_SIZE;
1450 }
1451 }
1452 for (i = 0; i < rq->rx_ring[1].size; i++) {
1453 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
1454 rq->buf_info[1][i].len = PAGE_SIZE;
1455 }
1456
1457 /* reset internal state and allocate buffers for both rings */
1458 for (i = 0; i < 2; i++) {
1459 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
1460 rq->uncommitted[i] = 0;
1461
1462 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
1463 sizeof(struct Vmxnet3_RxDesc));
1464 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
1465 }
1466 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
1467 adapter) == 0) {
1468 /* at least has 1 rx buffer for the 1st ring */
1469 return -ENOMEM;
1470 }
1471 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
1472
1473 /* reset the comp ring */
1474 rq->comp_ring.next2proc = 0;
1475 memset(rq->comp_ring.base, 0, rq->comp_ring.size *
1476 sizeof(struct Vmxnet3_RxCompDesc));
1477 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1478
1479 /* reset rxctx */
1480 rq->rx_ctx.skb = NULL;
1481
1482 /* stats are not reset */
1483 return 0;
1484}
1485
1486
09c5088e
SB		 1487static int
1488vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
1489{
1490 int i, err = 0;
1491
1492 for (i = 0; i < adapter->num_rx_queues; i++) {
1493 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
1494 if (unlikely(err)) {
1495 dev_err(&adapter->netdev->dev, "%s: failed to "
1496 "initialize rx queue%i\n",
1497 adapter->netdev->name, i);
1498 break;
1499 }
1500 }
1501 return err;
1502
1503}
1504
1505
d1a890fa
SB		 1506static int
1507vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
1508{
1509 int i;
1510 size_t sz;
1511 struct vmxnet3_rx_buf_info *bi;
1512
1513 for (i = 0; i < 2; i++) {
1514
1515 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
1516 rq->rx_ring[i].base = pci_alloc_consistent(adapter->pdev, sz,
1517 &rq->rx_ring[i].basePA);
1518 if (!rq->rx_ring[i].base) {
1519 printk(KERN_ERR "%s: failed to allocate rx ring %d\n",
1520 adapter->netdev->name, i);
1521 goto err;
1522 }
1523 }
1524
1525 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
1526 rq->comp_ring.base = pci_alloc_consistent(adapter->pdev, sz,
1527 &rq->comp_ring.basePA);
1528 if (!rq->comp_ring.base) {
1529 printk(KERN_ERR "%s: failed to allocate rx comp ring\n",
1530 adapter->netdev->name);
1531 goto err;
1532 }
1533
1534 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
1535 rq->rx_ring[1].size);
476c609e 1536 bi = kzalloc(sz, GFP_KERNEL);
e404decb 1537 if (!bi)
d1a890fa 1538 goto err;
e404decb 1539
d1a890fa
SB		 1540 rq->buf_info[0] = bi;
1541 rq->buf_info[1] = bi + rq->rx_ring[0].size;
1542
1543 return 0;
1544
1545err:
1546 vmxnet3_rq_destroy(rq, adapter);
1547 return -ENOMEM;
1548}
1549
1550
09c5088e
SB		 1551static int
1552vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
1553{
1554 int i, err = 0;
1555
1556 for (i = 0; i < adapter->num_rx_queues; i++) {
1557 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
1558 if (unlikely(err)) {
1559 dev_err(&adapter->netdev->dev,
1560 "%s: failed to create rx queue%i\n",
1561 adapter->netdev->name, i);
1562 goto err_out;
1563 }
1564 }
1565 return err;
1566err_out:
1567 vmxnet3_rq_destroy_all(adapter);
1568 return err;
1569
1570}
1571
1572/* Multiple queue aware polling function for tx and rx */
1573
d1a890fa
SB		 1574static int
1575vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
1576{
09c5088e 1577 int rcd_done = 0, i;
d1a890fa
SB		 1578 if (unlikely(adapter->shared->ecr))
1579 vmxnet3_process_events(adapter);
09c5088e
SB		 1580 for (i = 0; i < adapter->num_tx_queues; i++)
1581 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
d1a890fa 1582
09c5088e
SB		 1583 for (i = 0; i < adapter->num_rx_queues; i++)
1584 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
1585 adapter, budget);
1586 return rcd_done;
d1a890fa
SB		 1587}
1588
1589
1590static int
1591vmxnet3_poll(struct napi_struct *napi, int budget)
1592{
09c5088e
SB		 1593 struct vmxnet3_rx_queue *rx_queue = container_of(napi,
1594 struct vmxnet3_rx_queue, napi);
1595 int rxd_done;
1596
1597 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
1598
1599 if (rxd_done < budget) {
1600 napi_complete(napi);
1601 vmxnet3_enable_all_intrs(rx_queue->adapter);
1602 }
1603 return rxd_done;
1604}
1605
1606/*
1607 * NAPI polling function for MSI-X mode with multiple Rx queues
1608 * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
1609 */
1610
1611static int
1612vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
1613{
1614 struct vmxnet3_rx_queue *rq = container_of(napi,
1615 struct vmxnet3_rx_queue, napi);
1616 struct vmxnet3_adapter *adapter = rq->adapter;
d1a890fa
SB		 1617 int rxd_done;
1618
09c5088e
SB		 1619 /* When sharing interrupt with corresponding tx queue, process
1620 * tx completions in that queue as well
1621 */
1622 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
1623 struct vmxnet3_tx_queue *tq =
1624 &adapter->tx_queue[rq - adapter->rx_queue];
1625 vmxnet3_tq_tx_complete(tq, adapter);
1626 }
1627
1628 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
d1a890fa
SB		 1629
1630 if (rxd_done < budget) {
1631 napi_complete(napi);
09c5088e 1632 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
d1a890fa
SB		 1633 }
1634 return rxd_done;
1635}
1636
1637
09c5088e
SB		 1638#ifdef CONFIG_PCI_MSI
1639
1640/*
1641 * Handle completion interrupts on tx queues
1642 * Returns whether or not the intr is handled
1643 */
1644
1645static irqreturn_t
1646vmxnet3_msix_tx(int irq, void *data)
1647{
1648 struct vmxnet3_tx_queue *tq = data;
1649 struct vmxnet3_adapter *adapter = tq->adapter;
1650
1651 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1652 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
1653
1654 /* Handle the case where only one irq is allocate for all tx queues */
1655 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1656 int i;
1657 for (i = 0; i < adapter->num_tx_queues; i++) {
1658 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
1659 vmxnet3_tq_tx_complete(txq, adapter);
1660 }
1661 } else {
1662 vmxnet3_tq_tx_complete(tq, adapter);
1663 }
1664 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
1665
1666 return IRQ_HANDLED;
1667}
1668
1669
1670/*
1671 * Handle completion interrupts on rx queues. Returns whether or not the
1672 * intr is handled
1673 */
1674
1675static irqreturn_t
1676vmxnet3_msix_rx(int irq, void *data)
1677{
1678 struct vmxnet3_rx_queue *rq = data;
1679 struct vmxnet3_adapter *adapter = rq->adapter;
1680
1681 /* disable intr if needed */
1682 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1683 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
1684 napi_schedule(&rq->napi);
1685
1686 return IRQ_HANDLED;
1687}
1688
1689/*
1690 *----------------------------------------------------------------------------
1691 *
1692 * vmxnet3_msix_event --
1693 *
1694 * vmxnet3 msix event intr handler
1695 *
1696 * Result:
1697 * whether or not the intr is handled
1698 *
1699 *----------------------------------------------------------------------------
1700 */
1701
1702static irqreturn_t
1703vmxnet3_msix_event(int irq, void *data)
1704{
1705 struct net_device *dev = data;
1706 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1707
1708 /* disable intr if needed */
1709 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1710 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
1711
1712 if (adapter->shared->ecr)
1713 vmxnet3_process_events(adapter);
1714
1715 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
1716
1717 return IRQ_HANDLED;
1718}
1719
1720#endif /* CONFIG_PCI_MSI */
1721
1722
d1a890fa
SB		 1723/* Interrupt handler for vmxnet3 */
1724static irqreturn_t
1725vmxnet3_intr(int irq, void *dev_id)
1726{
1727 struct net_device *dev = dev_id;
1728 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1729
09c5088e 1730 if (adapter->intr.type == VMXNET3_IT_INTX) {
d1a890fa
SB		 1731 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
1732 if (unlikely(icr == 0))
1733 /* not ours */
1734 return IRQ_NONE;
1735 }
1736
1737
1738 /* disable intr if needed */
1739 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
09c5088e 1740 vmxnet3_disable_all_intrs(adapter);
d1a890fa 1741
09c5088e 1742 napi_schedule(&adapter->rx_queue[0].napi);
d1a890fa
SB		 1743
1744 return IRQ_HANDLED;
1745}
1746
1747#ifdef CONFIG_NET_POLL_CONTROLLER
1748
d1a890fa
SB		 1749/* netpoll callback. */
1750static void
1751vmxnet3_netpoll(struct net_device *netdev)
1752{
1753 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1754
09c5088e
SB		 1755 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1756 vmxnet3_disable_all_intrs(adapter);
1757
1758 vmxnet3_do_poll(adapter, adapter->rx_queue[0].rx_ring[0].size);
1759 vmxnet3_enable_all_intrs(adapter);
d1a890fa 1760
d1a890fa 1761}
09c5088e 1762#endif /* CONFIG_NET_POLL_CONTROLLER */
d1a890fa
SB		 1763
1764static int
1765vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
1766{
09c5088e
SB		 1767 struct vmxnet3_intr *intr = &adapter->intr;
1768 int err = 0, i;
1769 int vector = 0;
d1a890fa 1770
8f7e524c 1771#ifdef CONFIG_PCI_MSI
d1a890fa 1772 if (adapter->intr.type == VMXNET3_IT_MSIX) {
09c5088e
SB		 1773 for (i = 0; i < adapter->num_tx_queues; i++) {
1774 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
1775 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
1776 adapter->netdev->name, vector);
1777 err = request_irq(
1778 intr->msix_entries[vector].vector,
1779 vmxnet3_msix_tx, 0,
1780 adapter->tx_queue[i].name,
1781 &adapter->tx_queue[i]);
1782 } else {
1783 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
1784 adapter->netdev->name, vector);
1785 }
1786 if (err) {
1787 dev_err(&adapter->netdev->dev,
1788 "Failed to request irq for MSIX, %s, "
1789 "error %d\n",
1790 adapter->tx_queue[i].name, err);
1791 return err;
1792 }
1793
1794 /* Handle the case where only 1 MSIx was allocated for
1795 * all tx queues */
1796 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1797 for (; i < adapter->num_tx_queues; i++)
1798 adapter->tx_queue[i].comp_ring.intr_idx
1799 = vector;
1800 vector++;
1801 break;
1802 } else {
1803 adapter->tx_queue[i].comp_ring.intr_idx
1804 = vector++;
1805 }
1806 }
1807 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
1808 vector = 0;
1809
1810 for (i = 0; i < adapter->num_rx_queues; i++) {
1811 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
1812 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
1813 adapter->netdev->name, vector);
1814 else
1815 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
1816 adapter->netdev->name, vector);
1817 err = request_irq(intr->msix_entries[vector].vector,
1818 vmxnet3_msix_rx, 0,
1819 adapter->rx_queue[i].name,
1820 &(adapter->rx_queue[i]));
1821 if (err) {
1822 printk(KERN_ERR "Failed to request irq for MSIX"
1823 ", %s, error %d\n",
1824 adapter->rx_queue[i].name, err);
1825 return err;
1826 }
1827
1828 adapter->rx_queue[i].comp_ring.intr_idx = vector++;
1829 }
1830
1831 sprintf(intr->event_msi_vector_name, "%s-event-%d",
1832 adapter->netdev->name, vector);
1833 err = request_irq(intr->msix_entries[vector].vector,
1834 vmxnet3_msix_event, 0,
1835 intr->event_msi_vector_name, adapter->netdev);
1836 intr->event_intr_idx = vector;
1837
1838 } else if (intr->type == VMXNET3_IT_MSI) {
1839 adapter->num_rx_queues = 1;
d1a890fa
SB		 1840 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
1841 adapter->netdev->name, adapter->netdev);
09c5088e 1842 } else {
115924b6 1843#endif
09c5088e 1844 adapter->num_rx_queues = 1;
d1a890fa
SB		 1845 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
1846 IRQF_SHARED, adapter->netdev->name,
1847 adapter->netdev);
09c5088e 1848#ifdef CONFIG_PCI_MSI
d1a890fa 1849 }
09c5088e
SB		 1850#endif
1851 intr->num_intrs = vector + 1;
1852 if (err) {
d1a890fa 1853 printk(KERN_ERR "Failed to request irq %s (intr type:%d), error"
09c5088e
SB		 1854 ":%d\n", adapter->netdev->name, intr->type, err);
1855 } else {
1856 /* Number of rx queues will not change after this */
1857 for (i = 0; i < adapter->num_rx_queues; i++) {
1858 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
1859 rq->qid = i;
1860 rq->qid2 = i + adapter->num_rx_queues;
1861 }
d1a890fa
SB		 1862
1863
d1a890fa 1864
09c5088e
SB		 1865 /* init our intr settings */
1866 for (i = 0; i < intr->num_intrs; i++)
1867 intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
1868 if (adapter->intr.type != VMXNET3_IT_MSIX) {
1869 adapter->intr.event_intr_idx = 0;
1870 for (i = 0; i < adapter->num_tx_queues; i++)
1871 adapter->tx_queue[i].comp_ring.intr_idx = 0;
1872 adapter->rx_queue[0].comp_ring.intr_idx = 0;
1873 }
d1a890fa
SB		 1874
1875 printk(KERN_INFO "%s: intr type %u, mode %u, %u vectors "
09c5088e
SB		 1876 "allocated\n", adapter->netdev->name, intr->type,
1877 intr->mask_mode, intr->num_intrs);
d1a890fa
SB		 1878 }
1879
1880 return err;
1881}
1882
1883
1884static void
1885vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
1886{
09c5088e
SB		 1887 struct vmxnet3_intr *intr = &adapter->intr;
1888 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
d1a890fa 1889
09c5088e 1890 switch (intr->type) {
8f7e524c 1891#ifdef CONFIG_PCI_MSI
d1a890fa
SB		 1892 case VMXNET3_IT_MSIX:
1893 {
09c5088e 1894 int i, vector = 0;
d1a890fa 1895
09c5088e
SB		 1896 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
1897 for (i = 0; i < adapter->num_tx_queues; i++) {
1898 free_irq(intr->msix_entries[vector++].vector,
1899 &(adapter->tx_queue[i]));
1900 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
1901 break;
1902 }
1903 }
1904
1905 for (i = 0; i < adapter->num_rx_queues; i++) {
1906 free_irq(intr->msix_entries[vector++].vector,
1907 &(adapter->rx_queue[i]));
1908 }
1909
1910 free_irq(intr->msix_entries[vector].vector,
1911 adapter->netdev);
1912 BUG_ON(vector >= intr->num_intrs);
d1a890fa
SB		 1913 break;
1914 }
8f7e524c 1915#endif
d1a890fa
SB		 1916 case VMXNET3_IT_MSI:
1917 free_irq(adapter->pdev->irq, adapter->netdev);
1918 break;
1919 case VMXNET3_IT_INTX:
1920 free_irq(adapter->pdev->irq, adapter->netdev);
1921 break;
1922 default:
c068e777 1923 BUG();
d1a890fa
SB		 1924 }
1925}
1926
d1a890fa
SB		 1927
1928static void
1929vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
1930{
72e85c45
JG		 1931 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1932 u16 vid;
d1a890fa 1933
72e85c45
JG		 1934 /* allow untagged pkts */
1935 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
1936
1937 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
1938 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
d1a890fa
SB		 1939}
1940
1941
8e586137 1942static int
d1a890fa
SB		 1943vmxnet3_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1944{
1945 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1946
f6957f88
JG		 1947 if (!(netdev->flags & IFF_PROMISC)) {
1948 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1949 unsigned long flags;
1950
1951 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
1952 spin_lock_irqsave(&adapter->cmd_lock, flags);
1953 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1954 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1955 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
1956 }
72e85c45
JG		 1957
1958 set_bit(vid, adapter->active_vlans);
8e586137
JP		 1959
1960 return 0;
d1a890fa
SB		 1961}
1962
1963
8e586137 1964static int
d1a890fa
SB		 1965vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1966{
1967 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1968
f6957f88
JG		 1969 if (!(netdev->flags & IFF_PROMISC)) {
1970 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1971 unsigned long flags;
1972
1973 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
1974 spin_lock_irqsave(&adapter->cmd_lock, flags);
1975 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1976 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1977 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
1978 }
72e85c45
JG		 1979
1980 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 1981
1982 return 0;
d1a890fa
SB		 1983}
1984
1985
1986static u8 *
1987vmxnet3_copy_mc(struct net_device *netdev)
1988{
1989 u8 *buf = NULL;
4cd24eaf 1990 u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
d1a890fa
SB		 1991
1992 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
1993 if (sz <= 0xffff) {
1994 /* We may be called with BH disabled */
1995 buf = kmalloc(sz, GFP_ATOMIC);
1996 if (buf) {
22bedad3 1997 struct netdev_hw_addr *ha;
567ec874 1998 int i = 0;
d1a890fa 1999
22bedad3
JP		 2000 netdev_for_each_mc_addr(ha, netdev)
2001 memcpy(buf + i++ * ETH_ALEN, ha->addr,
d1a890fa 2002 ETH_ALEN);
d1a890fa
SB		 2003 }
2004 }
2005 return buf;
2006}
2007
2008
2009static void
2010vmxnet3_set_mc(struct net_device *netdev)
2011{
2012 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
83d0feff 2013 unsigned long flags;
d1a890fa
SB		 2014 struct Vmxnet3_RxFilterConf *rxConf =
2015 &adapter->shared->devRead.rxFilterConf;
2016 u8 *new_table = NULL;
2017 u32 new_mode = VMXNET3_RXM_UCAST;
2018
72e85c45
JG		 2019 if (netdev->flags & IFF_PROMISC) {
2020 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2021 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
2022
d1a890fa 2023 new_mode |= VMXNET3_RXM_PROMISC;
72e85c45
JG		 2024 } else {
2025 vmxnet3_restore_vlan(adapter);
2026 }
d1a890fa
SB		 2027
2028 if (netdev->flags & IFF_BROADCAST)
2029 new_mode |= VMXNET3_RXM_BCAST;
2030
2031 if (netdev->flags & IFF_ALLMULTI)
2032 new_mode |= VMXNET3_RXM_ALL_MULTI;
2033 else
4cd24eaf 2034 if (!netdev_mc_empty(netdev)) {
d1a890fa
SB		 2035 new_table = vmxnet3_copy_mc(netdev);
2036 if (new_table) {
2037 new_mode |= VMXNET3_RXM_MCAST;
115924b6 2038 rxConf->mfTableLen = cpu_to_le16(
4cd24eaf 2039 netdev_mc_count(netdev) * ETH_ALEN);
115924b6
SB		 2040 rxConf->mfTablePA = cpu_to_le64(virt_to_phys(
2041 new_table));
d1a890fa
SB		 2042 } else {
2043 printk(KERN_INFO "%s: failed to copy mcast list"
2044 ", setting ALL_MULTI\n", netdev->name);
2045 new_mode |= VMXNET3_RXM_ALL_MULTI;
2046 }
2047 }
2048
2049
2050 if (!(new_mode & VMXNET3_RXM_MCAST)) {
2051 rxConf->mfTableLen = 0;
2052 rxConf->mfTablePA = 0;
2053 }
2054
83d0feff 2055 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 2056 if (new_mode != rxConf->rxMode) {
115924b6 2057 rxConf->rxMode = cpu_to_le32(new_mode);
d1a890fa
SB		 2058 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2059 VMXNET3_CMD_UPDATE_RX_MODE);
72e85c45
JG		 2060 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2061 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
d1a890fa
SB		 2062 }
2063
2064 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2065 VMXNET3_CMD_UPDATE_MAC_FILTERS);
83d0feff 2066 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2067
2068 kfree(new_table);
2069}
2070
09c5088e
SB		 2071void
2072vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2073{
2074 int i;
2075
2076 for (i = 0; i < adapter->num_rx_queues; i++)
2077 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2078}
2079
d1a890fa
SB		 2080
2081/*
2082 * Set up driver_shared based on settings in adapter.
2083 */
2084
2085static void
2086vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2087{
2088 struct Vmxnet3_DriverShared *shared = adapter->shared;
2089 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2090 struct Vmxnet3_TxQueueConf *tqc;
2091 struct Vmxnet3_RxQueueConf *rqc;
2092 int i;
2093
2094 memset(shared, 0, sizeof(*shared));
2095
2096 /* driver settings */
115924b6
SB		 2097 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2098 devRead->misc.driverInfo.version = cpu_to_le32(
2099 VMXNET3_DRIVER_VERSION_NUM);
d1a890fa
SB		 2100 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2101 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2102 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
115924b6
SB		 2103 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2104 *((u32 *)&devRead->misc.driverInfo.gos));
2105 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2106 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
d1a890fa 2107
115924b6
SB		 2108 devRead->misc.ddPA = cpu_to_le64(virt_to_phys(adapter));
2109 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
d1a890fa
SB		 2110
2111 /* set up feature flags */
a0d2730c 2112 if (adapter->netdev->features & NETIF_F_RXCSUM)
3843e515 2113 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
d1a890fa 2114
a0d2730c 2115 if (adapter->netdev->features & NETIF_F_LRO) {
3843e515 2116 devRead->misc.uptFeatures |= UPT1_F_LRO;
115924b6 2117 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
d1a890fa 2118 }
54da3d00 2119 if (adapter->netdev->features & NETIF_F_HW_VLAN_RX)
3843e515 2120 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
d1a890fa 2121
115924b6
SB		 2122 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2123 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2124 devRead->misc.queueDescLen = cpu_to_le32(
09c5088e
SB		 2125 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2126 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
d1a890fa
SB		 2127
2128 /* tx queue settings */
09c5088e
SB		 2129 devRead->misc.numTxQueues = adapter->num_tx_queues;
2130 for (i = 0; i < adapter->num_tx_queues; i++) {
2131 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2132 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2133 tqc = &adapter->tqd_start[i].conf;
2134 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
2135 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2136 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
2137 tqc->ddPA = cpu_to_le64(virt_to_phys(tq->buf_info));
2138 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
2139 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
2140 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
2141 tqc->ddLen = cpu_to_le32(
2142 sizeof(struct vmxnet3_tx_buf_info) *
2143 tqc->txRingSize);
2144 tqc->intrIdx = tq->comp_ring.intr_idx;
2145 }
d1a890fa
SB		 2146
2147 /* rx queue settings */
09c5088e
SB		 2148 devRead->misc.numRxQueues = adapter->num_rx_queues;
2149 for (i = 0; i < adapter->num_rx_queues; i++) {
2150 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2151 rqc = &adapter->rqd_start[i].conf;
2152 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2153 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2154 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
2155 rqc->ddPA = cpu_to_le64(virt_to_phys(
2156 rq->buf_info));
2157 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
2158 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
2159 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
2160 rqc->ddLen = cpu_to_le32(
2161 sizeof(struct vmxnet3_rx_buf_info) *
2162 (rqc->rxRingSize[0] +
2163 rqc->rxRingSize[1]));
2164 rqc->intrIdx = rq->comp_ring.intr_idx;
2165 }
2166
2167#ifdef VMXNET3_RSS
2168 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2169
2170 if (adapter->rss) {
2171 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
2172 devRead->misc.uptFeatures |= UPT1_F_RSS;
2173 devRead->misc.numRxQueues = adapter->num_rx_queues;
2174 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2175 UPT1_RSS_HASH_TYPE_IPV4 |
2176 UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2177 UPT1_RSS_HASH_TYPE_IPV6;
2178 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2179 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2180 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
2181 get_random_bytes(&rssConf->hashKey[0], rssConf->hashKeySize);
2182 for (i = 0; i < rssConf->indTableSize; i++)
278bc429
BH		 2183 rssConf->indTable[i] = ethtool_rxfh_indir_default(
2184 i, adapter->num_rx_queues);
09c5088e
SB		 2185
2186 devRead->rssConfDesc.confVer = 1;
2187 devRead->rssConfDesc.confLen = sizeof(*rssConf);
2188 devRead->rssConfDesc.confPA = virt_to_phys(rssConf);
2189 }
2190
2191#endif /* VMXNET3_RSS */
d1a890fa
SB		 2192
2193 /* intr settings */
2194 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2195 VMXNET3_IMM_AUTO;
2196 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2197 for (i = 0; i < adapter->intr.num_intrs; i++)
2198 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2199
2200 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
6929fe8a 2201 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 2202
2203 /* rx filter settings */
2204 devRead->rxFilterConf.rxMode = 0;
2205 vmxnet3_restore_vlan(adapter);
f9f25026
SB		 2206 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2207
d1a890fa
SB		 2208 /* the rest are already zeroed */
2209}
2210
2211
2212int
2213vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
2214{
09c5088e 2215 int err, i;
d1a890fa 2216 u32 ret;
83d0feff 2217 unsigned long flags;
d1a890fa 2218
09c5088e
SB		 2219 dev_dbg(&adapter->netdev->dev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
2220 " ring sizes %u %u %u\n", adapter->netdev->name,
2221 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
2222 adapter->tx_queue[0].tx_ring.size,
2223 adapter->rx_queue[0].rx_ring[0].size,
2224 adapter->rx_queue[0].rx_ring[1].size);
2225
2226 vmxnet3_tq_init_all(adapter);
2227 err = vmxnet3_rq_init_all(adapter);
d1a890fa
SB		 2228 if (err) {
2229 printk(KERN_ERR "Failed to init rx queue for %s: error %d\n",
2230 adapter->netdev->name, err);
2231 goto rq_err;
2232 }
2233
2234 err = vmxnet3_request_irqs(adapter);
2235 if (err) {
2236 printk(KERN_ERR "Failed to setup irq for %s: error %d\n",
2237 adapter->netdev->name, err);
2238 goto irq_err;
2239 }
2240
2241 vmxnet3_setup_driver_shared(adapter);
2242
115924b6
SB		 2243 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
2244 adapter->shared_pa));
2245 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
2246 adapter->shared_pa));
83d0feff 2247 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2248 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2249 VMXNET3_CMD_ACTIVATE_DEV);
2250 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
83d0feff 2251 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2252
2253 if (ret != 0) {
2254 printk(KERN_ERR "Failed to activate dev %s: error %u\n",
2255 adapter->netdev->name, ret);
2256 err = -EINVAL;
2257 goto activate_err;
2258 }
09c5088e
SB		 2259
2260 for (i = 0; i < adapter->num_rx_queues; i++) {
2261 VMXNET3_WRITE_BAR0_REG(adapter,
2262 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
2263 adapter->rx_queue[i].rx_ring[0].next2fill);
2264 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
2265 (i * VMXNET3_REG_ALIGN)),
2266 adapter->rx_queue[i].rx_ring[1].next2fill);
2267 }
d1a890fa
SB		 2268
2269 /* Apply the rx filter settins last. */
2270 vmxnet3_set_mc(adapter->netdev);
2271
2272 /*
2273 * Check link state when first activating device. It will start the
2274 * tx queue if the link is up.
2275 */
4a1745fc 2276 vmxnet3_check_link(adapter, true);
09c5088e
SB		 2277 for (i = 0; i < adapter->num_rx_queues; i++)
2278 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2279 vmxnet3_enable_all_intrs(adapter);
2280 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
2281 return 0;
2282
2283activate_err:
2284 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
2285 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
2286 vmxnet3_free_irqs(adapter);
2287irq_err:
2288rq_err:
2289 /* free up buffers we allocated */
09c5088e 2290 vmxnet3_rq_cleanup_all(adapter);
d1a890fa
SB		 2291 return err;
2292}
2293
2294
2295void
2296vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
2297{
83d0feff
SB		 2298 unsigned long flags;
2299 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 2300 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
83d0feff 2301 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2302}
2303
2304
2305int
2306vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
2307{
09c5088e 2308 int i;
83d0feff 2309 unsigned long flags;
d1a890fa
SB		 2310 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
2311 return 0;
2312
2313
83d0feff 2314 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2315 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2316 VMXNET3_CMD_QUIESCE_DEV);
83d0feff 2317 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2318 vmxnet3_disable_all_intrs(adapter);
2319
09c5088e
SB		 2320 for (i = 0; i < adapter->num_rx_queues; i++)
2321 napi_disable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2322 netif_tx_disable(adapter->netdev);
2323 adapter->link_speed = 0;
2324 netif_carrier_off(adapter->netdev);
2325
09c5088e
SB		 2326 vmxnet3_tq_cleanup_all(adapter);
2327 vmxnet3_rq_cleanup_all(adapter);
d1a890fa
SB		 2328 vmxnet3_free_irqs(adapter);
2329 return 0;
2330}
2331
2332
2333static void
2334vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2335{
2336 u32 tmp;
2337
2338 tmp = *(u32 *)mac;
2339 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
2340
2341 tmp = (mac[5] << 8) | mac[4];
2342 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
2343}
2344
2345
2346static int
2347vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
2348{
2349 struct sockaddr *addr = p;
2350 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2351
2352 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2353 vmxnet3_write_mac_addr(adapter, addr->sa_data);
2354
2355 return 0;
2356}
2357
2358
2359/* ==================== initialization and cleanup routines ============ */
2360
2361static int
2362vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64)
2363{
2364 int err;
2365 unsigned long mmio_start, mmio_len;
2366 struct pci_dev *pdev = adapter->pdev;
2367
2368 err = pci_enable_device(pdev);
2369 if (err) {
2370 printk(KERN_ERR "Failed to enable adapter %s: error %d\n",
2371 pci_name(pdev), err);
2372 return err;
2373 }
2374
2375 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
2376 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
2377 printk(KERN_ERR "pci_set_consistent_dma_mask failed "
2378 "for adapter %s\n", pci_name(pdev));
2379 err = -EIO;
2380 goto err_set_mask;
2381 }
2382 *dma64 = true;
2383 } else {
2384 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
2385 printk(KERN_ERR "pci_set_dma_mask failed for adapter "
2386 "%s\n", pci_name(pdev));
2387 err = -EIO;
2388 goto err_set_mask;
2389 }
2390 *dma64 = false;
2391 }
2392
2393 err = pci_request_selected_regions(pdev, (1 << 2) - 1,
2394 vmxnet3_driver_name);
2395 if (err) {
2396 printk(KERN_ERR "Failed to request region for adapter %s: "
2397 "error %d\n", pci_name(pdev), err);
2398 goto err_set_mask;
2399 }
2400
2401 pci_set_master(pdev);
2402
2403 mmio_start = pci_resource_start(pdev, 0);
2404 mmio_len = pci_resource_len(pdev, 0);
2405 adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
2406 if (!adapter->hw_addr0) {
2407 printk(KERN_ERR "Failed to map bar0 for adapter %s\n",
2408 pci_name(pdev));
2409 err = -EIO;
2410 goto err_ioremap;
2411 }
2412
2413 mmio_start = pci_resource_start(pdev, 1);
2414 mmio_len = pci_resource_len(pdev, 1);
2415 adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
2416 if (!adapter->hw_addr1) {
2417 printk(KERN_ERR "Failed to map bar1 for adapter %s\n",
2418 pci_name(pdev));
2419 err = -EIO;
2420 goto err_bar1;
2421 }
2422 return 0;
2423
2424err_bar1:
2425 iounmap(adapter->hw_addr0);
2426err_ioremap:
2427 pci_release_selected_regions(pdev, (1 << 2) - 1);
2428err_set_mask:
2429 pci_disable_device(pdev);
2430 return err;
2431}
2432
2433
2434static void
2435vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
2436{
2437 BUG_ON(!adapter->pdev);
2438
2439 iounmap(adapter->hw_addr0);
2440 iounmap(adapter->hw_addr1);
2441 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
2442 pci_disable_device(adapter->pdev);
2443}
2444
2445
2446static void
2447vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
2448{
09c5088e
SB		 2449 size_t sz, i, ring0_size, ring1_size, comp_size;
2450 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[0];
2451
d1a890fa
SB		 2452
2453 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
2454 VMXNET3_MAX_ETH_HDR_SIZE) {
2455 adapter->skb_buf_size = adapter->netdev->mtu +
2456 VMXNET3_MAX_ETH_HDR_SIZE;
2457 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
2458 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
2459
2460 adapter->rx_buf_per_pkt = 1;
2461 } else {
2462 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
2463 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
2464 VMXNET3_MAX_ETH_HDR_SIZE;
2465 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
2466 }
2467
2468 /*
2469 * for simplicity, force the ring0 size to be a multiple of
2470 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
2471 */
2472 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
09c5088e
SB		 2473 ring0_size = adapter->rx_queue[0].rx_ring[0].size;
2474 ring0_size = (ring0_size + sz - 1) / sz * sz;
a53255d3 2475 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
09c5088e
SB		 2476 sz * sz);
2477 ring1_size = adapter->rx_queue[0].rx_ring[1].size;
2478 comp_size = ring0_size + ring1_size;
2479
2480 for (i = 0; i < adapter->num_rx_queues; i++) {
2481 rq = &adapter->rx_queue[i];
2482 rq->rx_ring[0].size = ring0_size;
2483 rq->rx_ring[1].size = ring1_size;
2484 rq->comp_ring.size = comp_size;
2485 }
d1a890fa
SB		 2486}
2487
2488
2489int
2490vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
2491 u32 rx_ring_size, u32 rx_ring2_size)
2492{
09c5088e
SB		 2493 int err = 0, i;
2494
2495 for (i = 0; i < adapter->num_tx_queues; i++) {
2496 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2497 tq->tx_ring.size = tx_ring_size;
2498 tq->data_ring.size = tx_ring_size;
2499 tq->comp_ring.size = tx_ring_size;
2500 tq->shared = &adapter->tqd_start[i].ctrl;
2501 tq->stopped = true;
2502 tq->adapter = adapter;
2503 tq->qid = i;
2504 err = vmxnet3_tq_create(tq, adapter);
2505 /*
2506 * Too late to change num_tx_queues. We cannot do away with
2507 * lesser number of queues than what we asked for
2508 */
2509 if (err)
2510 goto queue_err;
2511 }
d1a890fa 2512
09c5088e
SB		 2513 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
2514 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
d1a890fa 2515 vmxnet3_adjust_rx_ring_size(adapter);
09c5088e
SB		 2516 for (i = 0; i < adapter->num_rx_queues; i++) {
2517 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2518 /* qid and qid2 for rx queues will be assigned later when num
2519 * of rx queues is finalized after allocating intrs */
2520 rq->shared = &adapter->rqd_start[i].ctrl;
2521 rq->adapter = adapter;
2522 err = vmxnet3_rq_create(rq, adapter);
2523 if (err) {
2524 if (i == 0) {
2525 printk(KERN_ERR "Could not allocate any rx"
2526 "queues. Aborting.\n");
2527 goto queue_err;
2528 } else {
2529 printk(KERN_INFO "Number of rx queues changed "
2530 "to : %d.\n", i);
2531 adapter->num_rx_queues = i;
2532 err = 0;
2533 break;
2534 }
2535 }
2536 }
2537 return err;
2538queue_err:
2539 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2540 return err;
2541}
2542
2543static int
2544vmxnet3_open(struct net_device *netdev)
2545{
2546 struct vmxnet3_adapter *adapter;
09c5088e 2547 int err, i;
d1a890fa
SB		 2548
2549 adapter = netdev_priv(netdev);
2550
09c5088e
SB		 2551 for (i = 0; i < adapter->num_tx_queues; i++)
2552 spin_lock_init(&adapter->tx_queue[i].tx_lock);
d1a890fa
SB		 2553
2554 err = vmxnet3_create_queues(adapter, VMXNET3_DEF_TX_RING_SIZE,
2555 VMXNET3_DEF_RX_RING_SIZE,
2556 VMXNET3_DEF_RX_RING_SIZE);
2557 if (err)
2558 goto queue_err;
2559
2560 err = vmxnet3_activate_dev(adapter);
2561 if (err)
2562 goto activate_err;
2563
2564 return 0;
2565
2566activate_err:
09c5088e
SB		 2567 vmxnet3_rq_destroy_all(adapter);
2568 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2569queue_err:
2570 return err;
2571}
2572
2573
2574static int
2575vmxnet3_close(struct net_device *netdev)
2576{
2577 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2578
2579 /*
2580 * Reset_work may be in the middle of resetting the device, wait for its
2581 * completion.
2582 */
2583 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2584 msleep(1);
2585
2586 vmxnet3_quiesce_dev(adapter);
2587
09c5088e
SB		 2588 vmxnet3_rq_destroy_all(adapter);
2589 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2590
2591 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2592
2593
2594 return 0;
2595}
2596
2597
2598void
2599vmxnet3_force_close(struct vmxnet3_adapter *adapter)
2600{
09c5088e
SB		 2601 int i;
2602
d1a890fa
SB		 2603 /*
2604 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
2605 * vmxnet3_close() will deadlock.
2606 */
2607 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
2608
2609 /* we need to enable NAPI, otherwise dev_close will deadlock */
09c5088e
SB		 2610 for (i = 0; i < adapter->num_rx_queues; i++)
2611 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2612 dev_close(adapter->netdev);
2613}
2614
2615
2616static int
2617vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
2618{
2619 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2620 int err = 0;
2621
2622 if (new_mtu < VMXNET3_MIN_MTU || new_mtu > VMXNET3_MAX_MTU)
2623 return -EINVAL;
2624
d1a890fa
SB		 2625 netdev->mtu = new_mtu;
2626
2627 /*
2628 * Reset_work may be in the middle of resetting the device, wait for its
2629 * completion.
2630 */
2631 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2632 msleep(1);
2633
2634 if (netif_running(netdev)) {
2635 vmxnet3_quiesce_dev(adapter);
2636 vmxnet3_reset_dev(adapter);
2637
2638 /* we need to re-create the rx queue based on the new mtu */
09c5088e 2639 vmxnet3_rq_destroy_all(adapter);
d1a890fa 2640 vmxnet3_adjust_rx_ring_size(adapter);
09c5088e 2641 err = vmxnet3_rq_create_all(adapter);
d1a890fa 2642 if (err) {
09c5088e 2643 printk(KERN_ERR "%s: failed to re-create rx queues,"
d1a890fa
SB		 2644 " error %d. Closing it.\n", netdev->name, err);
2645 goto out;
2646 }
2647
2648 err = vmxnet3_activate_dev(adapter);
2649 if (err) {
2650 printk(KERN_ERR "%s: failed to re-activate, error %d. "
2651 "Closing it\n", netdev->name, err);
2652 goto out;
2653 }
2654 }
2655
2656out:
2657 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2658 if (err)
2659 vmxnet3_force_close(adapter);
2660
2661 return err;
2662}
2663
2664
2665static void
2666vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
2667{
2668 struct net_device *netdev = adapter->netdev;
2669
a0d2730c
MM		 2670 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
2671 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_TX |
72e85c45
JG		 2672 NETIF_F_HW_VLAN_RX | NETIF_F_TSO | NETIF_F_TSO6 |
2673 NETIF_F_LRO;
a0d2730c 2674 if (dma64)
ebbf9295 2675 netdev->hw_features |= NETIF_F_HIGHDMA;
72e85c45
JG		 2676 netdev->vlan_features = netdev->hw_features &
2677 ~(NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
2678 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_FILTER;
d1a890fa 2679
a0d2730c
MM		 2680 netdev_info(adapter->netdev,
2681 "features: sg csum vlan jf tso tsoIPv6 lro%s\n",
2682 dma64 ? " highDMA" : "");
d1a890fa
SB		 2683}
2684
2685
2686static void
2687vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2688{
2689 u32 tmp;
2690
2691 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
2692 *(u32 *)mac = tmp;
2693
2694 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
2695 mac[4] = tmp & 0xff;
2696 mac[5] = (tmp >> 8) & 0xff;
2697}
2698
09c5088e
SB		 2699#ifdef CONFIG_PCI_MSI
2700
2701/*
2702 * Enable MSIx vectors.
2703 * Returns :
2704 * 0 on successful enabling of required vectors,
25985edc 2705 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
09c5088e
SB		 2706 * could be enabled.
2707 * number of vectors which can be enabled otherwise (this number is smaller
2708 * than VMXNET3_LINUX_MIN_MSIX_VECT)
2709 */
2710
2711static int
2712vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter,
2713 int vectors)
2714{
2715 int err = 0, vector_threshold;
2716 vector_threshold = VMXNET3_LINUX_MIN_MSIX_VECT;
2717
2718 while (vectors >= vector_threshold) {
2719 err = pci_enable_msix(adapter->pdev, adapter->intr.msix_entries,
2720 vectors);
2721 if (!err) {
2722 adapter->intr.num_intrs = vectors;
2723 return 0;
2724 } else if (err < 0) {
4c1dc80a
SB		 2725 netdev_err(adapter->netdev,
2726 "Failed to enable MSI-X, error: %d\n", err);
09c5088e
SB		 2727 vectors = 0;
2728 } else if (err < vector_threshold) {
2729 break;
2730 } else {
2731 /* If fails to enable required number of MSI-x vectors
7e96fbf2 2732 * try enabling minimum number of vectors required.
09c5088e 2733 */
4c1dc80a
SB		 2734 netdev_err(adapter->netdev,
2735 "Failed to enable %d MSI-X, trying %d instead\n",
2736 vectors, vector_threshold);
09c5088e 2737 vectors = vector_threshold;
09c5088e
SB		 2738 }
2739 }
2740
4c1dc80a
SB		 2741 netdev_info(adapter->netdev,
2742 "Number of MSI-X interrupts which can be allocated are lower than min threshold required.\n");
09c5088e
SB		 2743 return err;
2744}
2745
2746
2747#endif /* CONFIG_PCI_MSI */
d1a890fa
SB		 2748
2749static void
2750vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
2751{
2752 u32 cfg;
e328d410 2753 unsigned long flags;
d1a890fa
SB		 2754
2755 /* intr settings */
e328d410 2756 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2757 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2758 VMXNET3_CMD_GET_CONF_INTR);
2759 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
e328d410 2760 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2761 adapter->intr.type = cfg & 0x3;
2762 adapter->intr.mask_mode = (cfg >> 2) & 0x3;
2763
2764 if (adapter->intr.type == VMXNET3_IT_AUTO) {
0bdc0d70
SB		 2765 adapter->intr.type = VMXNET3_IT_MSIX;
2766 }
d1a890fa 2767
8f7e524c 2768#ifdef CONFIG_PCI_MSI
0bdc0d70 2769 if (adapter->intr.type == VMXNET3_IT_MSIX) {
09c5088e
SB		 2770 int vector, err = 0;
2771
2772 adapter->intr.num_intrs = (adapter->share_intr ==
2773 VMXNET3_INTR_TXSHARE) ? 1 :
2774 adapter->num_tx_queues;
2775 adapter->intr.num_intrs += (adapter->share_intr ==
2776 VMXNET3_INTR_BUDDYSHARE) ? 0 :
2777 adapter->num_rx_queues;
2778 adapter->intr.num_intrs += 1; /* for link event */
2779
2780 adapter->intr.num_intrs = (adapter->intr.num_intrs >
2781 VMXNET3_LINUX_MIN_MSIX_VECT
2782 ? adapter->intr.num_intrs :
2783 VMXNET3_LINUX_MIN_MSIX_VECT);
2784
2785 for (vector = 0; vector < adapter->intr.num_intrs; vector++)
2786 adapter->intr.msix_entries[vector].entry = vector;
2787
2788 err = vmxnet3_acquire_msix_vectors(adapter,
2789 adapter->intr.num_intrs);
2790 /* If we cannot allocate one MSIx vector per queue
2791 * then limit the number of rx queues to 1
2792 */
2793 if (err == VMXNET3_LINUX_MIN_MSIX_VECT) {
2794 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
7e96fbf2 2795 || adapter->num_rx_queues != 1) {
09c5088e
SB		 2796 adapter->share_intr = VMXNET3_INTR_TXSHARE;
2797 printk(KERN_ERR "Number of rx queues : 1\n");
2798 adapter->num_rx_queues = 1;
2799 adapter->intr.num_intrs =
2800 VMXNET3_LINUX_MIN_MSIX_VECT;
2801 }
d1a890fa
SB		 2802 return;
2803 }
09c5088e
SB		 2804 if (!err)
2805 return;
2806
2807 /* If we cannot allocate MSIx vectors use only one rx queue */
4c1dc80a
SB		 2808 netdev_info(adapter->netdev,
2809 "Failed to enable MSI-X, error %d . Limiting #rx queues to 1, try MSI.\n",
2810 err);
09c5088e 2811
0bdc0d70
SB		 2812 adapter->intr.type = VMXNET3_IT_MSI;
2813 }
d1a890fa 2814
0bdc0d70
SB		 2815 if (adapter->intr.type == VMXNET3_IT_MSI) {
2816 int err;
d1a890fa
SB		 2817 err = pci_enable_msi(adapter->pdev);
2818 if (!err) {
09c5088e 2819 adapter->num_rx_queues = 1;
d1a890fa 2820 adapter->intr.num_intrs = 1;
d1a890fa
SB		 2821 return;
2822 }
2823 }
0bdc0d70 2824#endif /* CONFIG_PCI_MSI */
d1a890fa 2825
09c5088e
SB		 2826 adapter->num_rx_queues = 1;
2827 printk(KERN_INFO "Using INTx interrupt, #Rx queues: 1.\n");
d1a890fa
SB		 2828 adapter->intr.type = VMXNET3_IT_INTX;
2829
2830 /* INT-X related setting */
2831 adapter->intr.num_intrs = 1;
2832}
2833
2834
2835static void
2836vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
2837{
2838 if (adapter->intr.type == VMXNET3_IT_MSIX)
2839 pci_disable_msix(adapter->pdev);
2840 else if (adapter->intr.type == VMXNET3_IT_MSI)
2841 pci_disable_msi(adapter->pdev);
2842 else
2843 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
2844}
2845
2846
2847static void
2848vmxnet3_tx_timeout(struct net_device *netdev)
2849{
2850 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2851 adapter->tx_timeout_count++;
2852
2853 printk(KERN_ERR "%s: tx hang\n", adapter->netdev->name);
2854 schedule_work(&adapter->work);
09c5088e 2855 netif_wake_queue(adapter->netdev);
d1a890fa
SB		 2856}
2857
2858
2859static void
2860vmxnet3_reset_work(struct work_struct *data)
2861{
2862 struct vmxnet3_adapter *adapter;
2863
2864 adapter = container_of(data, struct vmxnet3_adapter, work);
2865
2866 /* if another thread is resetting the device, no need to proceed */
2867 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2868 return;
2869
2870 /* if the device is closed, we must leave it alone */
d9a5f210 2871 rtnl_lock();
d1a890fa
SB		 2872 if (netif_running(adapter->netdev)) {
2873 printk(KERN_INFO "%s: resetting\n", adapter->netdev->name);
2874 vmxnet3_quiesce_dev(adapter);
2875 vmxnet3_reset_dev(adapter);
2876 vmxnet3_activate_dev(adapter);
2877 } else {
2878 printk(KERN_INFO "%s: already closed\n", adapter->netdev->name);
2879 }
d9a5f210 2880 rtnl_unlock();
d1a890fa
SB		 2881
2882 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2883}
2884
2885
3a4751a3 2886static int
d1a890fa
SB		 2887vmxnet3_probe_device(struct pci_dev *pdev,
2888 const struct pci_device_id *id)
2889{
2890 static const struct net_device_ops vmxnet3_netdev_ops = {
2891 .ndo_open = vmxnet3_open,
2892 .ndo_stop = vmxnet3_close,
2893 .ndo_start_xmit = vmxnet3_xmit_frame,
2894 .ndo_set_mac_address = vmxnet3_set_mac_addr,
2895 .ndo_change_mtu = vmxnet3_change_mtu,
a0d2730c 2896 .ndo_set_features = vmxnet3_set_features,
95305f6c 2897 .ndo_get_stats64 = vmxnet3_get_stats64,
d1a890fa 2898 .ndo_tx_timeout = vmxnet3_tx_timeout,
afc4b13d 2899 .ndo_set_rx_mode = vmxnet3_set_mc,
d1a890fa
SB		 2900 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
2901 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
2902#ifdef CONFIG_NET_POLL_CONTROLLER
2903 .ndo_poll_controller = vmxnet3_netpoll,
2904#endif
2905 };
2906 int err;
2907 bool dma64 = false; /* stupid gcc */
2908 u32 ver;
2909 struct net_device *netdev;
2910 struct vmxnet3_adapter *adapter;
2911 u8 mac[ETH_ALEN];
09c5088e
SB		 2912 int size;
2913 int num_tx_queues;
2914 int num_rx_queues;
2915
e154b639
SB		 2916 if (!pci_msi_enabled())
2917 enable_mq = 0;
2918
09c5088e
SB		 2919#ifdef VMXNET3_RSS
2920 if (enable_mq)
2921 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
2922 (int)num_online_cpus());
2923 else
2924#endif
2925 num_rx_queues = 1;
eebb02b1 2926 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
09c5088e
SB		 2927
2928 if (enable_mq)
2929 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
2930 (int)num_online_cpus());
2931 else
2932 num_tx_queues = 1;
2933
eebb02b1 2934 num_tx_queues = rounddown_pow_of_two(num_tx_queues);
09c5088e
SB		 2935 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
2936 max(num_tx_queues, num_rx_queues));
2937 printk(KERN_INFO "# of Tx queues : %d, # of Rx queues : %d\n",
2938 num_tx_queues, num_rx_queues);
d1a890fa 2939
41de8d4c 2940 if (!netdev)
d1a890fa 2941 return -ENOMEM;
d1a890fa
SB		 2942
2943 pci_set_drvdata(pdev, netdev);
2944 adapter = netdev_priv(netdev);
2945 adapter->netdev = netdev;
2946 adapter->pdev = pdev;
2947
83d0feff 2948 spin_lock_init(&adapter->cmd_lock);
d1a890fa 2949 adapter->shared = pci_alloc_consistent(adapter->pdev,
96800ee7 2950 sizeof(struct Vmxnet3_DriverShared),
2951 &adapter->shared_pa);
d1a890fa
SB		 2952 if (!adapter->shared) {
2953 printk(KERN_ERR "Failed to allocate memory for %s\n",
96800ee7 2954 pci_name(pdev));
d1a890fa
SB		 2955 err = -ENOMEM;
2956 goto err_alloc_shared;
2957 }
2958
09c5088e
SB		 2959 adapter->num_rx_queues = num_rx_queues;
2960 adapter->num_tx_queues = num_tx_queues;
2961
2962 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
2963 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
2964 adapter->tqd_start = pci_alloc_consistent(adapter->pdev, size,
96800ee7 2965 &adapter->queue_desc_pa);
d1a890fa
SB		 2966
2967 if (!adapter->tqd_start) {
2968 printk(KERN_ERR "Failed to allocate memory for %s\n",
96800ee7 2969 pci_name(pdev));
d1a890fa
SB		 2970 err = -ENOMEM;
2971 goto err_alloc_queue_desc;
2972 }
09c5088e 2973 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
96800ee7 2974 adapter->num_tx_queues);
d1a890fa
SB		 2975
2976 adapter->pm_conf = kmalloc(sizeof(struct Vmxnet3_PMConf), GFP_KERNEL);
2977 if (adapter->pm_conf == NULL) {
d1a890fa
SB		 2978 err = -ENOMEM;
2979 goto err_alloc_pm;
2980 }
2981
09c5088e
SB		 2982#ifdef VMXNET3_RSS
2983
2984 adapter->rss_conf = kmalloc(sizeof(struct UPT1_RSSConf), GFP_KERNEL);
2985 if (adapter->rss_conf == NULL) {
09c5088e
SB		 2986 err = -ENOMEM;
2987 goto err_alloc_rss;
2988 }
2989#endif /* VMXNET3_RSS */
2990
d1a890fa
SB		 2991 err = vmxnet3_alloc_pci_resources(adapter, &dma64);
2992 if (err < 0)
2993 goto err_alloc_pci;
2994
2995 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
2996 if (ver & 1) {
2997 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_VRRS, 1);
2998 } else {
2999 printk(KERN_ERR "Incompatible h/w version (0x%x) for adapter"
3000 " %s\n", ver, pci_name(pdev));
3001 err = -EBUSY;
3002 goto err_ver;
3003 }
3004
3005 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
3006 if (ver & 1) {
3007 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
3008 } else {
3009 printk(KERN_ERR "Incompatible upt version (0x%x) for "
3010 "adapter %s\n", ver, pci_name(pdev));
3011 err = -EBUSY;
3012 goto err_ver;
3013 }
3014
e101e7dd 3015 SET_NETDEV_DEV(netdev, &pdev->dev);
d1a890fa
SB		 3016 vmxnet3_declare_features(adapter, dma64);
3017
3018 adapter->dev_number = atomic_read(&devices_found);
09c5088e 3019
96800ee7 3020 adapter->share_intr = irq_share_mode;
09c5088e
SB		 3021 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE &&
3022 adapter->num_tx_queues != adapter->num_rx_queues)
3023 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
3024
d1a890fa
SB		 3025 vmxnet3_alloc_intr_resources(adapter);
3026
09c5088e
SB		 3027#ifdef VMXNET3_RSS
3028 if (adapter->num_rx_queues > 1 &&
3029 adapter->intr.type == VMXNET3_IT_MSIX) {
3030 adapter->rss = true;
3031 printk(KERN_INFO "RSS is enabled.\n");
3032 } else {
3033 adapter->rss = false;
3034 }
3035#endif
3036
d1a890fa
SB		 3037 vmxnet3_read_mac_addr(adapter, mac);
3038 memcpy(netdev->dev_addr, mac, netdev->addr_len);
3039
3040 netdev->netdev_ops = &vmxnet3_netdev_ops;
d1a890fa 3041 vmxnet3_set_ethtool_ops(netdev);
09c5088e 3042 netdev->watchdog_timeo = 5 * HZ;
d1a890fa
SB		 3043
3044 INIT_WORK(&adapter->work, vmxnet3_reset_work);
e3bc4ffb 3045 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
d1a890fa 3046
09c5088e
SB		 3047 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3048 int i;
3049 for (i = 0; i < adapter->num_rx_queues; i++) {
3050 netif_napi_add(adapter->netdev,
3051 &adapter->rx_queue[i].napi,
3052 vmxnet3_poll_rx_only, 64);
3053 }
3054 } else {
3055 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
3056 vmxnet3_poll, 64);
3057 }
3058
3059 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
3060 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
3061
d1a890fa
SB		 3062 err = register_netdev(netdev);
3063
3064 if (err) {
3065 printk(KERN_ERR "Failed to register adapter %s\n",
96800ee7 3066 pci_name(pdev));
d1a890fa
SB		 3067 goto err_register;
3068 }
3069
4a1745fc 3070 vmxnet3_check_link(adapter, false);
d1a890fa
SB		 3071 atomic_inc(&devices_found);
3072 return 0;
3073
3074err_register:
3075 vmxnet3_free_intr_resources(adapter);
3076err_ver:
3077 vmxnet3_free_pci_resources(adapter);
3078err_alloc_pci:
09c5088e
SB		 3079#ifdef VMXNET3_RSS
3080 kfree(adapter->rss_conf);
3081err_alloc_rss:
3082#endif
d1a890fa
SB		 3083 kfree(adapter->pm_conf);
3084err_alloc_pm:
09c5088e
SB		 3085 pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
3086 adapter->queue_desc_pa);
d1a890fa
SB		 3087err_alloc_queue_desc:
3088 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
3089 adapter->shared, adapter->shared_pa);
3090err_alloc_shared:
3091 pci_set_drvdata(pdev, NULL);
3092 free_netdev(netdev);
3093 return err;
3094}
3095
3096
3a4751a3 3097static void
d1a890fa
SB		 3098vmxnet3_remove_device(struct pci_dev *pdev)
3099{
3100 struct net_device *netdev = pci_get_drvdata(pdev);
3101 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
09c5088e
SB		 3102 int size = 0;
3103 int num_rx_queues;
3104
3105#ifdef VMXNET3_RSS
3106 if (enable_mq)
3107 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3108 (int)num_online_cpus());
3109 else
3110#endif
3111 num_rx_queues = 1;
eebb02b1 3112 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
d1a890fa 3113
23f333a2 3114 cancel_work_sync(&adapter->work);
d1a890fa
SB		 3115
3116 unregister_netdev(netdev);
3117
3118 vmxnet3_free_intr_resources(adapter);
3119 vmxnet3_free_pci_resources(adapter);
09c5088e
SB		 3120#ifdef VMXNET3_RSS
3121 kfree(adapter->rss_conf);
3122#endif
d1a890fa 3123 kfree(adapter->pm_conf);
09c5088e
SB		 3124
3125 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3126 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
3127 pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
3128 adapter->queue_desc_pa);
d1a890fa
SB		 3129 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
3130 adapter->shared, adapter->shared_pa);
3131 free_netdev(netdev);
3132}
3133
3134
3135#ifdef CONFIG_PM
3136
3137static int
3138vmxnet3_suspend(struct device *device)
3139{
3140 struct pci_dev *pdev = to_pci_dev(device);
3141 struct net_device *netdev = pci_get_drvdata(pdev);
3142 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3143 struct Vmxnet3_PMConf *pmConf;
3144 struct ethhdr *ehdr;
3145 struct arphdr *ahdr;
3146 u8 *arpreq;
3147 struct in_device *in_dev;
3148 struct in_ifaddr *ifa;
83d0feff 3149 unsigned long flags;
d1a890fa
SB		 3150 int i = 0;
3151
3152 if (!netif_running(netdev))
3153 return 0;
3154
51956cd6
SB		 3155 for (i = 0; i < adapter->num_rx_queues; i++)
3156 napi_disable(&adapter->rx_queue[i].napi);
3157
d1a890fa
SB		 3158 vmxnet3_disable_all_intrs(adapter);
3159 vmxnet3_free_irqs(adapter);
3160 vmxnet3_free_intr_resources(adapter);
3161
3162 netif_device_detach(netdev);
09c5088e 3163 netif_tx_stop_all_queues(netdev);
d1a890fa
SB		 3164
3165 /* Create wake-up filters. */
3166 pmConf = adapter->pm_conf;
3167 memset(pmConf, 0, sizeof(*pmConf));
3168
3169 if (adapter->wol & WAKE_UCAST) {
3170 pmConf->filters[i].patternSize = ETH_ALEN;
3171 pmConf->filters[i].maskSize = 1;
3172 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
3173 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
3174
3843e515 3175 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
d1a890fa
SB		 3176 i++;
3177 }
3178
3179 if (adapter->wol & WAKE_ARP) {
3180 in_dev = in_dev_get(netdev);
3181 if (!in_dev)
3182 goto skip_arp;
3183
3184 ifa = (struct in_ifaddr *)in_dev->ifa_list;
3185 if (!ifa)
3186 goto skip_arp;
3187
3188 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
3189 sizeof(struct arphdr) + /* ARP header */
3190 2 * ETH_ALEN + /* 2 Ethernet addresses*/
3191 2 * sizeof(u32); /*2 IPv4 addresses */
3192 pmConf->filters[i].maskSize =
3193 (pmConf->filters[i].patternSize - 1) / 8 + 1;
3194
3195 /* ETH_P_ARP in Ethernet header. */
3196 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
3197 ehdr->h_proto = htons(ETH_P_ARP);
3198
3199 /* ARPOP_REQUEST in ARP header. */
3200 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
3201 ahdr->ar_op = htons(ARPOP_REQUEST);
3202 arpreq = (u8 *)(ahdr + 1);
3203
3204 /* The Unicast IPv4 address in 'tip' field. */
3205 arpreq += 2 * ETH_ALEN + sizeof(u32);
3206 *(u32 *)arpreq = ifa->ifa_address;
3207
3208 /* The mask for the relevant bits. */
3209 pmConf->filters[i].mask[0] = 0x00;
3210 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
3211 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
3212 pmConf->filters[i].mask[3] = 0x00;
3213 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
3214 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
3215 in_dev_put(in_dev);
3216
3843e515 3217 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
d1a890fa
SB		 3218 i++;
3219 }
3220
3221skip_arp:
3222 if (adapter->wol & WAKE_MAGIC)
3843e515 3223 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
d1a890fa
SB		 3224
3225 pmConf->numFilters = i;
3226
115924b6
SB		 3227 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3228 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3229 *pmConf));
3230 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
3231 pmConf));
d1a890fa 3232
83d0feff 3233 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 3234 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3235 VMXNET3_CMD_UPDATE_PMCFG);
83d0feff 3236 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 3237
3238 pci_save_state(pdev);
3239 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
3240 adapter->wol);
3241 pci_disable_device(pdev);
3242 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
3243
3244 return 0;
3245}
3246
3247
3248static int
3249vmxnet3_resume(struct device *device)
3250{
51956cd6 3251 int err, i = 0;
83d0feff 3252 unsigned long flags;
d1a890fa
SB		 3253 struct pci_dev *pdev = to_pci_dev(device);
3254 struct net_device *netdev = pci_get_drvdata(pdev);
3255 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3256 struct Vmxnet3_PMConf *pmConf;
3257
3258 if (!netif_running(netdev))
3259 return 0;
3260
3261 /* Destroy wake-up filters. */
3262 pmConf = adapter->pm_conf;
3263 memset(pmConf, 0, sizeof(*pmConf));
3264
115924b6
SB		 3265 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3266 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3267 *pmConf));
0561cf3d 3268 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
115924b6 3269 pmConf));
d1a890fa
SB		 3270
3271 netif_device_attach(netdev);
3272 pci_set_power_state(pdev, PCI_D0);
3273 pci_restore_state(pdev);
3274 err = pci_enable_device_mem(pdev);
3275 if (err != 0)
3276 return err;
3277
3278 pci_enable_wake(pdev, PCI_D0, 0);
3279
83d0feff 3280 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 3281 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3282 VMXNET3_CMD_UPDATE_PMCFG);
83d0feff 3283 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 3284 vmxnet3_alloc_intr_resources(adapter);
3285 vmxnet3_request_irqs(adapter);
51956cd6
SB		 3286 for (i = 0; i < adapter->num_rx_queues; i++)
3287 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 3288 vmxnet3_enable_all_intrs(adapter);
3289
3290 return 0;
3291}
3292
47145210 3293static const struct dev_pm_ops vmxnet3_pm_ops = {
d1a890fa
SB		 3294 .suspend = vmxnet3_suspend,
3295 .resume = vmxnet3_resume,
3296};
3297#endif
3298
3299static struct pci_driver vmxnet3_driver = {
3300 .name = vmxnet3_driver_name,
3301 .id_table = vmxnet3_pciid_table,
3302 .probe = vmxnet3_probe_device,
3a4751a3 3303 .remove = vmxnet3_remove_device,
d1a890fa
SB		 3304#ifdef CONFIG_PM
3305 .driver.pm = &vmxnet3_pm_ops,
3306#endif
3307};
3308
3309
3310static int __init
3311vmxnet3_init_module(void)
3312{
3313 printk(KERN_INFO "%s - version %s\n", VMXNET3_DRIVER_DESC,
3314 VMXNET3_DRIVER_VERSION_REPORT);
3315 return pci_register_driver(&vmxnet3_driver);
3316}
3317
3318module_init(vmxnet3_init_module);
3319
3320
3321static void
3322vmxnet3_exit_module(void)
3323{
3324 pci_unregister_driver(&vmxnet3_driver);
3325}
3326
3327module_exit(vmxnet3_exit_module);
3328
3329MODULE_AUTHOR("VMware, Inc.");
3330MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
3331MODULE_LICENSE("GPL v2");
3332MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);
kernel source for telekom puls (alcatel/mediatek)