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stmmac: update the driver's module version
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
41
42#include <linux/mlx4/device.h>
43#include <linux/mlx4/doorbell.h>
44
45#include "mlx4.h"
46#include "fw.h"
47#include "icm.h"
48
49MODULE_AUTHOR("Roland Dreier");
50MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
51MODULE_LICENSE("Dual BSD/GPL");
52MODULE_VERSION(DRV_VERSION);
53
27bf91d6
YP		 54struct workqueue_struct *mlx4_wq;
55
225c7b1f
RD		 56#ifdef CONFIG_MLX4_DEBUG
57
58int mlx4_debug_level = 0;
59module_param_named(debug_level, mlx4_debug_level, int, 0644);
60MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
61
62#endif /* CONFIG_MLX4_DEBUG */
63
64#ifdef CONFIG_PCI_MSI
65
08fb1055 66static int msi_x = 1;
225c7b1f
RD		 67module_param(msi_x, int, 0444);
68MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
69
70#else /* CONFIG_PCI_MSI */
71
72#define msi_x (0)
73
74#endif /* CONFIG_PCI_MSI */
75
f33afc26 76static char mlx4_version[] __devinitdata =
225c7b1f
RD		 77 DRV_NAME ": Mellanox ConnectX core driver v"
78 DRV_VERSION " (" DRV_RELDATE ")\n";
79
80static struct mlx4_profile default_profile = {
9b1f3851 81 .num_qp = 1 << 17,
225c7b1f 82 .num_srq = 1 << 16,
c9f2ba5e 83 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 84 .num_cq = 1 << 16,
85 .num_mcg = 1 << 13,
86 .num_mpt = 1 << 17,
87 .num_mtt = 1 << 20,
88};
89
93fc9e1b
YP		 90static int log_num_mac = 2;
91module_param_named(log_num_mac, log_num_mac, int, 0444);
92MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
93
94static int log_num_vlan;
95module_param_named(log_num_vlan, log_num_vlan, int, 0444);
96MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
97
98static int use_prio;
99module_param_named(use_prio, use_prio, bool, 0444);
100MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
101 "(0/1, default 0)");
102
ab6bf42e
EC		 103static int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
104module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
105MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-5)");
106
27bf91d6
YP		 107int mlx4_check_port_params(struct mlx4_dev *dev,
108 enum mlx4_port_type *port_type)
7ff93f8b
YP		 109{
110 int i;
111
112 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 113 if (port_type[i] != port_type[i + 1]) {
114 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
115 mlx4_err(dev, "Only same port types supported "
116 "on this HCA, aborting.\n");
117 return -EINVAL;
118 }
119 if (port_type[i] == MLX4_PORT_TYPE_ETH &&
120 port_type[i + 1] == MLX4_PORT_TYPE_IB)
121 return -EINVAL;
7ff93f8b
YP		 122 }
123 }
7ff93f8b
YP		 124
125 for (i = 0; i < dev->caps.num_ports; i++) {
126 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
127 mlx4_err(dev, "Requested port type for port %d is not "
128 "supported on this HCA\n", i + 1);
129 return -EINVAL;
130 }
131 }
132 return 0;
133}
134
135static void mlx4_set_port_mask(struct mlx4_dev *dev)
136{
137 int i;
138
139 dev->caps.port_mask = 0;
140 for (i = 1; i <= dev->caps.num_ports; ++i)
141 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_IB)
142 dev->caps.port_mask |= 1 << (i - 1);
143}
3d73c288 144static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 145{
146 int err;
5ae2a7a8 147 int i;
225c7b1f
RD		 148
149 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
150 if (err) {
151 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
152 return err;
153 }
154
155 if (dev_cap->min_page_sz > PAGE_SIZE) {
156 mlx4_err(dev, "HCA minimum page size of %d bigger than "
157 "kernel PAGE_SIZE of %ld, aborting.\n",
158 dev_cap->min_page_sz, PAGE_SIZE);
159 return -ENODEV;
160 }
161 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
162 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
163 "aborting.\n",
164 dev_cap->num_ports, MLX4_MAX_PORTS);
165 return -ENODEV;
166 }
167
168 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
169 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
170 "PCI resource 2 size of 0x%llx, aborting.\n",
171 dev_cap->uar_size,
172 (unsigned long long) pci_resource_len(dev->pdev, 2));
173 return -ENODEV;
174 }
175
176 dev->caps.num_ports = dev_cap->num_ports;
5ae2a7a8
RD		 177 for (i = 1; i <= dev->caps.num_ports; ++i) {
178 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 179 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
5ae2a7a8
RD		 180 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
181 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
182 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 183 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
184 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 185 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
5ae2a7a8
RD		 186 }
187
225c7b1f 188 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 189 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
190 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
191 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
192 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
193 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
194 dev->caps.max_wqes = dev_cap->max_qp_sz;
195 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 196 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
197 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
198 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
199 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
200 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
201 dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM;
202 /*
203 * Subtract 1 from the limit because we need to allocate a
204 * spare CQE so the HCA HW can tell the difference between an
205 * empty CQ and a full CQ.
206 */
207 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
208 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
209 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
ab6bf42e 210 dev->caps.mtts_per_seg = 1 << log_mtts_per_seg;
121964ec 211 dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
ab6bf42e 212 dev->caps.mtts_per_seg);
225c7b1f
RD		 213 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
214 dev->caps.reserved_uars = dev_cap->reserved_uars;
215 dev->caps.reserved_pds = dev_cap->reserved_pds;
ab6bf42e 216 dev->caps.mtt_entry_sz = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz;
149983af 217 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 218 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
219 dev->caps.flags = dev_cap->flags;
95d04f07
RD		 220 dev->caps.bmme_flags = dev_cap->bmme_flags;
221 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 222 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 223 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
225c7b1f 224
93fc9e1b
YP		 225 dev->caps.log_num_macs = log_num_mac;
226 dev->caps.log_num_vlans = log_num_vlan;
227 dev->caps.log_num_prios = use_prio ? 3 : 0;
228
229 for (i = 1; i <= dev->caps.num_ports; ++i) {
7ff93f8b
YP		 230 if (dev->caps.supported_type[i] != MLX4_PORT_TYPE_ETH)
231 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
232 else
233 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 234 dev->caps.possible_type[i] = dev->caps.port_type[i];
235 mlx4_priv(dev)->sense.sense_allowed[i] =
236 dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO;
7ff93f8b 237
93fc9e1b
YP		 238 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
239 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
240 mlx4_warn(dev, "Requested number of MACs is too much "
241 "for port %d, reducing to %d.\n",
242 i, 1 << dev->caps.log_num_macs);
243 }
244 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
245 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
246 mlx4_warn(dev, "Requested number of VLANs is too much "
247 "for port %d, reducing to %d.\n",
248 i, 1 << dev->caps.log_num_vlans);
249 }
250 }
251
7ff93f8b
YP		 252 mlx4_set_port_mask(dev);
253
93fc9e1b
YP		 254 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
255 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
256 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
257 (1 << dev->caps.log_num_macs) *
258 (1 << dev->caps.log_num_vlans) *
259 (1 << dev->caps.log_num_prios) *
260 dev->caps.num_ports;
261 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
262
263 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
264 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
265 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
266 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
267
225c7b1f
RD		 268 return 0;
269}
270
7ff93f8b
YP		 271/*
272 * Change the port configuration of the device.
273 * Every user of this function must hold the port mutex.
274 */
27bf91d6
YP		 275int mlx4_change_port_types(struct mlx4_dev *dev,
276 enum mlx4_port_type *port_types)
7ff93f8b
YP		 277{
278 int err = 0;
279 int change = 0;
280 int port;
281
282 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 283 /* Change the port type only if the new type is different
284 * from the current, and not set to Auto */
7ff93f8b
YP		 285 if (port_types[port] != dev->caps.port_type[port + 1]) {
286 change = 1;
287 dev->caps.port_type[port + 1] = port_types[port];
288 }
289 }
290 if (change) {
291 mlx4_unregister_device(dev);
292 for (port = 1; port <= dev->caps.num_ports; port++) {
293 mlx4_CLOSE_PORT(dev, port);
294 err = mlx4_SET_PORT(dev, port);
295 if (err) {
296 mlx4_err(dev, "Failed to set port %d, "
297 "aborting\n", port);
298 goto out;
299 }
300 }
301 mlx4_set_port_mask(dev);
302 err = mlx4_register_device(dev);
303 }
304
305out:
306 return err;
307}
308
309static ssize_t show_port_type(struct device *dev,
310 struct device_attribute *attr,
311 char *buf)
312{
313 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
314 port_attr);
315 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 316 char type[8];
317
318 sprintf(type, "%s",
319 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
320 "ib" : "eth");
321 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
322 sprintf(buf, "auto (%s)\n", type);
323 else
324 sprintf(buf, "%s\n", type);
7ff93f8b 325
27bf91d6 326 return strlen(buf);
7ff93f8b
YP		 327}
328
329static ssize_t set_port_type(struct device *dev,
330 struct device_attribute *attr,
331 const char *buf, size_t count)
332{
333 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
334 port_attr);
335 struct mlx4_dev *mdev = info->dev;
336 struct mlx4_priv *priv = mlx4_priv(mdev);
337 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 338 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 339 int i;
340 int err = 0;
341
342 if (!strcmp(buf, "ib\n"))
343 info->tmp_type = MLX4_PORT_TYPE_IB;
344 else if (!strcmp(buf, "eth\n"))
345 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 346 else if (!strcmp(buf, "auto\n"))
347 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 348 else {
349 mlx4_err(mdev, "%s is not supported port type\n", buf);
350 return -EINVAL;
351 }
352
27bf91d6 353 mlx4_stop_sense(mdev);
7ff93f8b 354 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 355 /* Possible type is always the one that was delivered */
356 mdev->caps.possible_type[info->port] = info->tmp_type;
357
358 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 359 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 360 mdev->caps.possible_type[i+1];
361 if (types[i] == MLX4_PORT_TYPE_AUTO)
362 types[i] = mdev->caps.port_type[i+1];
363 }
7ff93f8b 364
27bf91d6
YP		 365 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
366 for (i = 1; i <= mdev->caps.num_ports; i++) {
367 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
368 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
369 err = -EINVAL;
370 }
371 }
372 }
373 if (err) {
374 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
375 "Set only 'eth' or 'ib' for both ports "
376 "(should be the same)\n");
377 goto out;
378 }
379
380 mlx4_do_sense_ports(mdev, new_types, types);
381
382 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 383 if (err)
384 goto out;
385
27bf91d6
YP		 386 /* We are about to apply the changes after the configuration
387 * was verified, no need to remember the temporary types
388 * any more */
389 for (i = 0; i < mdev->caps.num_ports; i++)
390 priv->port[i + 1].tmp_type = 0;
7ff93f8b 391
27bf91d6 392 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 393
394out:
27bf91d6 395 mlx4_start_sense(mdev);
7ff93f8b
YP		 396 mutex_unlock(&priv->port_mutex);
397 return err ? err : count;
398}
399
e8f9b2ed 400static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 401{
402 struct mlx4_priv *priv = mlx4_priv(dev);
403 int err;
404
405 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 406 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 407 if (!priv->fw.fw_icm) {
408 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
409 return -ENOMEM;
410 }
411
412 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
413 if (err) {
414 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
415 goto err_free;
416 }
417
418 err = mlx4_RUN_FW(dev);
419 if (err) {
420 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
421 goto err_unmap_fa;
422 }
423
424 return 0;
425
426err_unmap_fa:
427 mlx4_UNMAP_FA(dev);
428
429err_free:
5b0bf5e2 430 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 431 return err;
432}
433
e8f9b2ed
RD		 434static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
435 int cmpt_entry_sz)
225c7b1f
RD		 436{
437 struct mlx4_priv *priv = mlx4_priv(dev);
438 int err;
439
440 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
441 cmpt_base +
442 ((u64) (MLX4_CMPT_TYPE_QP *
443 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
444 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 445 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
446 0, 0);
225c7b1f
RD		 447 if (err)
448 goto err;
449
450 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
451 cmpt_base +
452 ((u64) (MLX4_CMPT_TYPE_SRQ *
453 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
454 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 455 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 456 if (err)
457 goto err_qp;
458
459 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
460 cmpt_base +
461 ((u64) (MLX4_CMPT_TYPE_CQ *
462 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
463 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 464 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 465 if (err)
466 goto err_srq;
467
468 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
469 cmpt_base +
470 ((u64) (MLX4_CMPT_TYPE_EQ *
471 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
472 cmpt_entry_sz,
b8dd786f 473 dev->caps.num_eqs, dev->caps.num_eqs, 0, 0);
225c7b1f
RD		 474 if (err)
475 goto err_cq;
476
477 return 0;
478
479err_cq:
480 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
481
482err_srq:
483 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
484
485err_qp:
486 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
487
488err:
489 return err;
490}
491
3d73c288
RD		 492static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
493 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 494{
495 struct mlx4_priv *priv = mlx4_priv(dev);
496 u64 aux_pages;
497 int err;
498
499 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
500 if (err) {
501 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
502 return err;
503 }
504
505 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
506 (unsigned long long) icm_size >> 10,
507 (unsigned long long) aux_pages << 2);
508
509 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 510 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 511 if (!priv->fw.aux_icm) {
512 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
513 return -ENOMEM;
514 }
515
516 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
517 if (err) {
518 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
519 goto err_free_aux;
520 }
521
522 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
523 if (err) {
524 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
525 goto err_unmap_aux;
526 }
527
fa0681d2
RD		 528 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
529 init_hca->eqc_base, dev_cap->eqc_entry_sz,
530 dev->caps.num_eqs, dev->caps.num_eqs,
531 0, 0);
225c7b1f
RD		 532 if (err) {
533 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
534 goto err_unmap_cmpt;
535 }
536
d7bb58fb
JM		 537 /*
538 * Reserved MTT entries must be aligned up to a cacheline
539 * boundary, since the FW will write to them, while the driver
540 * writes to all other MTT entries. (The variable
541 * dev->caps.mtt_entry_sz below is really the MTT segment
542 * size, not the raw entry size)
543 */
544 dev->caps.reserved_mtts =
545 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
546 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
547
225c7b1f
RD		 548 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
549 init_hca->mtt_base,
550 dev->caps.mtt_entry_sz,
551 dev->caps.num_mtt_segs,
5b0bf5e2 552 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 553 if (err) {
554 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
555 goto err_unmap_eq;
556 }
557
558 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
559 init_hca->dmpt_base,
560 dev_cap->dmpt_entry_sz,
561 dev->caps.num_mpts,
5b0bf5e2 562 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 563 if (err) {
564 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
565 goto err_unmap_mtt;
566 }
567
568 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
569 init_hca->qpc_base,
570 dev_cap->qpc_entry_sz,
571 dev->caps.num_qps,
93fc9e1b
YP		 572 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
573 0, 0);
225c7b1f
RD		 574 if (err) {
575 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
576 goto err_unmap_dmpt;
577 }
578
579 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
580 init_hca->auxc_base,
581 dev_cap->aux_entry_sz,
582 dev->caps.num_qps,
93fc9e1b
YP		 583 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
584 0, 0);
225c7b1f
RD		 585 if (err) {
586 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
587 goto err_unmap_qp;
588 }
589
590 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
591 init_hca->altc_base,
592 dev_cap->altc_entry_sz,
593 dev->caps.num_qps,
93fc9e1b
YP		 594 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
595 0, 0);
225c7b1f
RD		 596 if (err) {
597 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
598 goto err_unmap_auxc;
599 }
600
601 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
602 init_hca->rdmarc_base,
603 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
604 dev->caps.num_qps,
93fc9e1b
YP		 605 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
606 0, 0);
225c7b1f
RD		 607 if (err) {
608 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
609 goto err_unmap_altc;
610 }
611
612 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
613 init_hca->cqc_base,
614 dev_cap->cqc_entry_sz,
615 dev->caps.num_cqs,
5b0bf5e2 616 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 617 if (err) {
618 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
619 goto err_unmap_rdmarc;
620 }
621
622 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
623 init_hca->srqc_base,
624 dev_cap->srq_entry_sz,
625 dev->caps.num_srqs,
5b0bf5e2 626 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 627 if (err) {
628 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
629 goto err_unmap_cq;
630 }
631
632 /*
633 * It's not strictly required, but for simplicity just map the
634 * whole multicast group table now. The table isn't very big
635 * and it's a lot easier than trying to track ref counts.
636 */
637 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
638 init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
639 dev->caps.num_mgms + dev->caps.num_amgms,
640 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 641 0, 0);
225c7b1f
RD		 642 if (err) {
643 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
644 goto err_unmap_srq;
645 }
646
647 return 0;
648
649err_unmap_srq:
650 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
651
652err_unmap_cq:
653 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
654
655err_unmap_rdmarc:
656 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
657
658err_unmap_altc:
659 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
660
661err_unmap_auxc:
662 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
663
664err_unmap_qp:
665 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
666
667err_unmap_dmpt:
668 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
669
670err_unmap_mtt:
671 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
672
673err_unmap_eq:
fa0681d2 674 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 675
676err_unmap_cmpt:
677 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
678 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
679 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
680 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
681
682err_unmap_aux:
683 mlx4_UNMAP_ICM_AUX(dev);
684
685err_free_aux:
5b0bf5e2 686 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 687
688 return err;
689}
690
691static void mlx4_free_icms(struct mlx4_dev *dev)
692{
693 struct mlx4_priv *priv = mlx4_priv(dev);
694
695 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
696 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
697 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
698 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
699 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
700 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
701 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
702 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
703 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 704 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 705 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
706 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
707 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
708 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 709
710 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 711 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 712}
713
714static void mlx4_close_hca(struct mlx4_dev *dev)
715{
716 mlx4_CLOSE_HCA(dev, 0);
717 mlx4_free_icms(dev);
718 mlx4_UNMAP_FA(dev);
5b0bf5e2 719 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
225c7b1f
RD		 720}
721
3d73c288 722static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 723{
724 struct mlx4_priv *priv = mlx4_priv(dev);
725 struct mlx4_adapter adapter;
726 struct mlx4_dev_cap dev_cap;
2d928651 727 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 728 struct mlx4_profile profile;
729 struct mlx4_init_hca_param init_hca;
730 u64 icm_size;
731 int err;
732
733 err = mlx4_QUERY_FW(dev);
734 if (err) {
cc4ac2e7
YP		 735 if (err == -EACCES)
736 mlx4_info(dev, "non-primary physical function, skipping.\n");
737 else
738 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
225c7b1f
RD		 739 return err;
740 }
741
742 err = mlx4_load_fw(dev);
743 if (err) {
744 mlx4_err(dev, "Failed to start FW, aborting.\n");
745 return err;
746 }
747
2d928651
VS		 748 mlx4_cfg.log_pg_sz_m = 1;
749 mlx4_cfg.log_pg_sz = 0;
750 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
751 if (err)
752 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
753
225c7b1f
RD		 754 err = mlx4_dev_cap(dev, &dev_cap);
755 if (err) {
756 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
757 goto err_stop_fw;
758 }
759
760 profile = default_profile;
761
762 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
763 if ((long long) icm_size < 0) {
764 err = icm_size;
765 goto err_stop_fw;
766 }
767
768 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
769
770 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
771 if (err)
772 goto err_stop_fw;
773
774 err = mlx4_INIT_HCA(dev, &init_hca);
775 if (err) {
776 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
777 goto err_free_icm;
778 }
779
780 err = mlx4_QUERY_ADAPTER(dev, &adapter);
781 if (err) {
782 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
783 goto err_close;
784 }
785
786 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 787 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 788
789 return 0;
790
791err_close:
1af92e2a 792 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 793
794err_free_icm:
795 mlx4_free_icms(dev);
796
797err_stop_fw:
798 mlx4_UNMAP_FA(dev);
5b0bf5e2 799 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 800
801 return err;
802}
803
3d73c288 804static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 805{
806 struct mlx4_priv *priv = mlx4_priv(dev);
807 int err;
7ff93f8b 808 int port;
9a5aa622 809 __be32 ib_port_default_caps;
225c7b1f 810
225c7b1f
RD		 811 err = mlx4_init_uar_table(dev);
812 if (err) {
813 mlx4_err(dev, "Failed to initialize "
814 "user access region table, aborting.\n");
815 return err;
816 }
817
818 err = mlx4_uar_alloc(dev, &priv->driver_uar);
819 if (err) {
820 mlx4_err(dev, "Failed to allocate driver access region, "
821 "aborting.\n");
822 goto err_uar_table_free;
823 }
824
825 priv->kar = ioremap(priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
826 if (!priv->kar) {
827 mlx4_err(dev, "Couldn't map kernel access region, "
828 "aborting.\n");
829 err = -ENOMEM;
830 goto err_uar_free;
831 }
832
833 err = mlx4_init_pd_table(dev);
834 if (err) {
835 mlx4_err(dev, "Failed to initialize "
836 "protection domain table, aborting.\n");
837 goto err_kar_unmap;
838 }
839
840 err = mlx4_init_mr_table(dev);
841 if (err) {
842 mlx4_err(dev, "Failed to initialize "
843 "memory region table, aborting.\n");
844 goto err_pd_table_free;
845 }
846
225c7b1f
RD		 847 err = mlx4_init_eq_table(dev);
848 if (err) {
849 mlx4_err(dev, "Failed to initialize "
850 "event queue table, aborting.\n");
ee49bd93 851 goto err_mr_table_free;
225c7b1f
RD		 852 }
853
854 err = mlx4_cmd_use_events(dev);
855 if (err) {
856 mlx4_err(dev, "Failed to switch to event-driven "
857 "firmware commands, aborting.\n");
858 goto err_eq_table_free;
859 }
860
861 err = mlx4_NOP(dev);
862 if (err) {
08fb1055
MT		 863 if (dev->flags & MLX4_FLAG_MSI_X) {
864 mlx4_warn(dev, "NOP command failed to generate MSI-X "
865 "interrupt IRQ %d).\n",
b8dd786f 866 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
08fb1055
MT		 867 mlx4_warn(dev, "Trying again without MSI-X.\n");
868 } else {
869 mlx4_err(dev, "NOP command failed to generate interrupt "
870 "(IRQ %d), aborting.\n",
b8dd786f 871 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 872 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 873 }
225c7b1f
RD		 874
875 goto err_cmd_poll;
876 }
877
878 mlx4_dbg(dev, "NOP command IRQ test passed\n");
879
880 err = mlx4_init_cq_table(dev);
881 if (err) {
882 mlx4_err(dev, "Failed to initialize "
883 "completion queue table, aborting.\n");
884 goto err_cmd_poll;
885 }
886
887 err = mlx4_init_srq_table(dev);
888 if (err) {
889 mlx4_err(dev, "Failed to initialize "
890 "shared receive queue table, aborting.\n");
891 goto err_cq_table_free;
892 }
893
894 err = mlx4_init_qp_table(dev);
895 if (err) {
896 mlx4_err(dev, "Failed to initialize "
897 "queue pair table, aborting.\n");
898 goto err_srq_table_free;
899 }
900
901 err = mlx4_init_mcg_table(dev);
902 if (err) {
903 mlx4_err(dev, "Failed to initialize "
904 "multicast group table, aborting.\n");
905 goto err_qp_table_free;
906 }
907
7ff93f8b 908 for (port = 1; port <= dev->caps.num_ports; port++) {
9a5aa622
JM		 909 ib_port_default_caps = 0;
910 err = mlx4_get_port_ib_caps(dev, port, &ib_port_default_caps);
911 if (err)
912 mlx4_warn(dev, "failed to get port %d default "
913 "ib capabilities (%d). Continuing with "
914 "caps = 0\n", port, err);
915 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
7ff93f8b
YP		 916 err = mlx4_SET_PORT(dev, port);
917 if (err) {
918 mlx4_err(dev, "Failed to set port %d, aborting\n",
919 port);
920 goto err_mcg_table_free;
921 }
922 }
923
225c7b1f
RD		 924 return 0;
925
7ff93f8b
YP		 926err_mcg_table_free:
927 mlx4_cleanup_mcg_table(dev);
928
225c7b1f
RD		 929err_qp_table_free:
930 mlx4_cleanup_qp_table(dev);
931
932err_srq_table_free:
933 mlx4_cleanup_srq_table(dev);
934
935err_cq_table_free:
936 mlx4_cleanup_cq_table(dev);
937
938err_cmd_poll:
939 mlx4_cmd_use_polling(dev);
940
941err_eq_table_free:
942 mlx4_cleanup_eq_table(dev);
943
ee49bd93 944err_mr_table_free:
225c7b1f
RD		 945 mlx4_cleanup_mr_table(dev);
946
947err_pd_table_free:
948 mlx4_cleanup_pd_table(dev);
949
950err_kar_unmap:
951 iounmap(priv->kar);
952
953err_uar_free:
954 mlx4_uar_free(dev, &priv->driver_uar);
955
956err_uar_table_free:
957 mlx4_cleanup_uar_table(dev);
958 return err;
959}
960
e8f9b2ed 961static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 962{
963 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f
YP		 964 struct msix_entry *entries;
965 int nreq;
225c7b1f
RD		 966 int err;
967 int i;
968
969 if (msi_x) {
70cb9253
RD		 970 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
971 num_possible_cpus() + 1);
b8dd786f
YP		 972 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
973 if (!entries)
974 goto no_msi;
975
976 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 977 entries[i].entry = i;
978
b8dd786f
YP		 979 retry:
980 err = pci_enable_msix(dev->pdev, entries, nreq);
225c7b1f 981 if (err) {
b8dd786f
YP		 982 /* Try again if at least 2 vectors are available */
983 if (err > 1) {
984 mlx4_info(dev, "Requested %d vectors, "
985 "but only %d MSI-X vectors available, "
986 "trying again\n", nreq, err);
987 nreq = err;
988 goto retry;
989 }
5bf0da7d 990 kfree(entries);
225c7b1f
RD		 991 goto no_msi;
992 }
993
b8dd786f
YP		 994 dev->caps.num_comp_vectors = nreq - 1;
995 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 996 priv->eq_table.eq[i].irq = entries[i].vector;
997
998 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 999
1000 kfree(entries);
225c7b1f
RD		 1001 return;
1002 }
1003
1004no_msi:
b8dd786f
YP		 1005 dev->caps.num_comp_vectors = 1;
1006
1007 for (i = 0; i < 2; ++i)
225c7b1f
RD		 1008 priv->eq_table.eq[i].irq = dev->pdev->irq;
1009}
1010
7ff93f8b 1011static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 1012{
1013 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 1014 int err = 0;
2a2336f8
YP		 1015
1016 info->dev = dev;
1017 info->port = port;
1018 mlx4_init_mac_table(dev, &info->mac_table);
1019 mlx4_init_vlan_table(dev, &info->vlan_table);
7ff93f8b
YP		 1020
1021 sprintf(info->dev_name, "mlx4_port%d", port);
1022 info->port_attr.attr.name = info->dev_name;
1023 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1024 info->port_attr.show = show_port_type;
1025 info->port_attr.store = set_port_type;
1026
1027 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1028 if (err) {
1029 mlx4_err(dev, "Failed to create file for port %d\n", port);
1030 info->port = -1;
1031 }
1032
1033 return err;
1034}
1035
1036static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1037{
1038 if (info->port < 0)
1039 return;
1040
1041 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2a2336f8
YP		 1042}
1043
3d73c288 1044static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
225c7b1f 1045{
225c7b1f
RD		 1046 struct mlx4_priv *priv;
1047 struct mlx4_dev *dev;
1048 int err;
2a2336f8 1049 int port;
225c7b1f 1050
225c7b1f
RD		 1051 printk(KERN_INFO PFX "Initializing %s\n",
1052 pci_name(pdev));
1053
1054 err = pci_enable_device(pdev);
1055 if (err) {
1056 dev_err(&pdev->dev, "Cannot enable PCI device, "
1057 "aborting.\n");
1058 return err;
1059 }
1060
1061 /*
4ff08a76 1062 * Check for BARs. We expect 0: 1MB
225c7b1f
RD		 1063 */
1064 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
1065 pci_resource_len(pdev, 0) != 1 << 20) {
1066 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
1067 err = -ENODEV;
1068 goto err_disable_pdev;
1069 }
1070 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1071 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1072 err = -ENODEV;
1073 goto err_disable_pdev;
1074 }
1075
a01df0fe 1076 err = pci_request_regions(pdev, DRV_NAME);
225c7b1f 1077 if (err) {
a01df0fe 1078 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
225c7b1f
RD		 1079 goto err_disable_pdev;
1080 }
1081
225c7b1f
RD		 1082 pci_set_master(pdev);
1083
6a35528a 1084 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 1085 if (err) {
1086 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
284901a9 1087 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 1088 if (err) {
1089 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
a01df0fe 1090 goto err_release_regions;
225c7b1f
RD		 1091 }
1092 }
6a35528a 1093 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 1094 if (err) {
1095 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1096 "consistent PCI DMA mask.\n");
284901a9 1097 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 1098 if (err) {
1099 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1100 "aborting.\n");
a01df0fe 1101 goto err_release_regions;
225c7b1f
RD		 1102 }
1103 }
1104
1105 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1106 if (!priv) {
1107 dev_err(&pdev->dev, "Device struct alloc failed, "
1108 "aborting.\n");
1109 err = -ENOMEM;
a01df0fe 1110 goto err_release_regions;
225c7b1f
RD		 1111 }
1112
1113 dev = &priv->dev;
1114 dev->pdev = pdev;
b581401e
RD		 1115 INIT_LIST_HEAD(&priv->ctx_list);
1116 spin_lock_init(&priv->ctx_lock);
225c7b1f 1117
7ff93f8b
YP		 1118 mutex_init(&priv->port_mutex);
1119
6296883c
YP		 1120 INIT_LIST_HEAD(&priv->pgdir_list);
1121 mutex_init(&priv->pgdir_mutex);
1122
225c7b1f
RD		 1123 /*
1124 * Now reset the HCA before we touch the PCI capabilities or
1125 * attempt a firmware command, since a boot ROM may have left
1126 * the HCA in an undefined state.
1127 */
1128 err = mlx4_reset(dev);
1129 if (err) {
1130 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1131 goto err_free_dev;
1132 }
1133
225c7b1f
RD		 1134 if (mlx4_cmd_init(dev)) {
1135 mlx4_err(dev, "Failed to init command interface, aborting.\n");
1136 goto err_free_dev;
1137 }
1138
1139 err = mlx4_init_hca(dev);
1140 if (err)
1141 goto err_cmd;
1142
b8dd786f
YP		 1143 err = mlx4_alloc_eq_table(dev);
1144 if (err)
1145 goto err_close;
1146
08fb1055
MT		 1147 mlx4_enable_msi_x(dev);
1148
225c7b1f 1149 err = mlx4_setup_hca(dev);
08fb1055
MT		 1150 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
1151 dev->flags &= ~MLX4_FLAG_MSI_X;
1152 pci_disable_msix(pdev);
1153 err = mlx4_setup_hca(dev);
1154 }
1155
225c7b1f 1156 if (err)
b8dd786f 1157 goto err_free_eq;
225c7b1f 1158
7ff93f8b
YP		 1159 for (port = 1; port <= dev->caps.num_ports; port++) {
1160 err = mlx4_init_port_info(dev, port);
1161 if (err)
1162 goto err_port;
1163 }
2a2336f8 1164
225c7b1f
RD		 1165 err = mlx4_register_device(dev);
1166 if (err)
7ff93f8b 1167 goto err_port;
225c7b1f 1168
27bf91d6
YP		 1169 mlx4_sense_init(dev);
1170 mlx4_start_sense(dev);
1171
225c7b1f
RD		 1172 pci_set_drvdata(pdev, dev);
1173
1174 return 0;
1175
7ff93f8b
YP		 1176err_port:
1177 for (port = 1; port <= dev->caps.num_ports; port++)
1178 mlx4_cleanup_port_info(&priv->port[port]);
1179
225c7b1f
RD		 1180 mlx4_cleanup_mcg_table(dev);
1181 mlx4_cleanup_qp_table(dev);
1182 mlx4_cleanup_srq_table(dev);
1183 mlx4_cleanup_cq_table(dev);
1184 mlx4_cmd_use_polling(dev);
1185 mlx4_cleanup_eq_table(dev);
225c7b1f
RD		 1186 mlx4_cleanup_mr_table(dev);
1187 mlx4_cleanup_pd_table(dev);
1188 mlx4_cleanup_uar_table(dev);
1189
b8dd786f
YP		 1190err_free_eq:
1191 mlx4_free_eq_table(dev);
1192
225c7b1f 1193err_close:
08fb1055
MT		 1194 if (dev->flags & MLX4_FLAG_MSI_X)
1195 pci_disable_msix(pdev);
1196
225c7b1f
RD		 1197 mlx4_close_hca(dev);
1198
1199err_cmd:
1200 mlx4_cmd_cleanup(dev);
1201
1202err_free_dev:
225c7b1f
RD		 1203 kfree(priv);
1204
a01df0fe
RD		 1205err_release_regions:
1206 pci_release_regions(pdev);
225c7b1f
RD		 1207
1208err_disable_pdev:
1209 pci_disable_device(pdev);
1210 pci_set_drvdata(pdev, NULL);
1211 return err;
1212}
1213
3d73c288
RD		 1214static int __devinit mlx4_init_one(struct pci_dev *pdev,
1215 const struct pci_device_id *id)
1216{
1217 static int mlx4_version_printed;
1218
1219 if (!mlx4_version_printed) {
1220 printk(KERN_INFO "%s", mlx4_version);
1221 ++mlx4_version_printed;
1222 }
1223
b027cacd 1224 return __mlx4_init_one(pdev, id);
3d73c288
RD		 1225}
1226
1227static void mlx4_remove_one(struct pci_dev *pdev)
225c7b1f
RD		 1228{
1229 struct mlx4_dev *dev = pci_get_drvdata(pdev);
1230 struct mlx4_priv *priv = mlx4_priv(dev);
1231 int p;
1232
1233 if (dev) {
27bf91d6 1234 mlx4_stop_sense(dev);
225c7b1f
RD		 1235 mlx4_unregister_device(dev);
1236
7ff93f8b
YP		 1237 for (p = 1; p <= dev->caps.num_ports; p++) {
1238 mlx4_cleanup_port_info(&priv->port[p]);
225c7b1f 1239 mlx4_CLOSE_PORT(dev, p);
7ff93f8b 1240 }
225c7b1f
RD		 1241
1242 mlx4_cleanup_mcg_table(dev);
1243 mlx4_cleanup_qp_table(dev);
1244 mlx4_cleanup_srq_table(dev);
1245 mlx4_cleanup_cq_table(dev);
1246 mlx4_cmd_use_polling(dev);
1247 mlx4_cleanup_eq_table(dev);
225c7b1f
RD		 1248 mlx4_cleanup_mr_table(dev);
1249 mlx4_cleanup_pd_table(dev);
1250
1251 iounmap(priv->kar);
1252 mlx4_uar_free(dev, &priv->driver_uar);
1253 mlx4_cleanup_uar_table(dev);
b8dd786f 1254 mlx4_free_eq_table(dev);
225c7b1f
RD		 1255 mlx4_close_hca(dev);
1256 mlx4_cmd_cleanup(dev);
1257
1258 if (dev->flags & MLX4_FLAG_MSI_X)
1259 pci_disable_msix(pdev);
1260
1261 kfree(priv);
a01df0fe 1262 pci_release_regions(pdev);
225c7b1f
RD		 1263 pci_disable_device(pdev);
1264 pci_set_drvdata(pdev, NULL);
1265 }
1266}
1267
ee49bd93
JM		 1268int mlx4_restart_one(struct pci_dev *pdev)
1269{
1270 mlx4_remove_one(pdev);
3d73c288 1271 return __mlx4_init_one(pdev, NULL);
ee49bd93
JM		 1272}
1273
225c7b1f
RD		 1274static struct pci_device_id mlx4_pci_table[] = {
1275 { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
1276 { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
1277 { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
786f238e
JM		 1278 { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
1279 { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
57893d1c
YP		 1280 { PCI_VDEVICE(MELLANOX, 0x6368) }, /* MT25408 "Hermon" EN 10GigE */
1281 { PCI_VDEVICE(MELLANOX, 0x6750) }, /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
085343b4
JM		 1282 { PCI_VDEVICE(MELLANOX, 0x6372) }, /* MT25458 ConnectX EN 10GBASE-T 10GigE */
1283 { PCI_VDEVICE(MELLANOX, 0x675a) }, /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
92bd3bbf 1284 { PCI_VDEVICE(MELLANOX, 0x6764) }, /* MT26468 ConnectX EN 10GigE PCIe gen2*/
06c3aa5e 1285 { PCI_VDEVICE(MELLANOX, 0x6746) }, /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
e76d0b67 1286 { PCI_VDEVICE(MELLANOX, 0x676e) }, /* MT26478 ConnectX2 40GigE PCIe gen2 */
225c7b1f
RD		 1287 { 0, }
1288};
1289
1290MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
1291
1292static struct pci_driver mlx4_driver = {
1293 .name = DRV_NAME,
1294 .id_table = mlx4_pci_table,
1295 .probe = mlx4_init_one,
1296 .remove = __devexit_p(mlx4_remove_one)
1297};
1298
7ff93f8b
YP		 1299static int __init mlx4_verify_params(void)
1300{
1301 if ((log_num_mac < 0) || (log_num_mac > 7)) {
1302 printk(KERN_WARNING "mlx4_core: bad num_mac: %d\n", log_num_mac);
1303 return -1;
1304 }
1305
1306 if ((log_num_vlan < 0) || (log_num_vlan > 7)) {
1307 printk(KERN_WARNING "mlx4_core: bad num_vlan: %d\n", log_num_vlan);
1308 return -1;
1309 }
1310
ab6bf42e
EC		 1311 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 5)) {
1312 printk(KERN_WARNING "mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
1313 return -1;
1314 }
1315
7ff93f8b
YP		 1316 return 0;
1317}
1318
225c7b1f
RD		 1319static int __init mlx4_init(void)
1320{
1321 int ret;
1322
7ff93f8b
YP		 1323 if (mlx4_verify_params())
1324 return -EINVAL;
1325
27bf91d6
YP		 1326 mlx4_catas_init();
1327
1328 mlx4_wq = create_singlethread_workqueue("mlx4");
1329 if (!mlx4_wq)
1330 return -ENOMEM;
ee49bd93 1331
225c7b1f
RD		 1332 ret = pci_register_driver(&mlx4_driver);
1333 return ret < 0 ? ret : 0;
1334}
1335
1336static void __exit mlx4_cleanup(void)
1337{
1338 pci_unregister_driver(&mlx4_driver);
27bf91d6 1339 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 1340}
1341
1342module_init(mlx4_init);
1343module_exit(mlx4_cleanup);
kernel source for telekom puls (alcatel/mediatek)