projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
fs/romfs: return f_fsid for statfs(2)
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
41
42#include <linux/mlx4/device.h>
43#include <linux/mlx4/doorbell.h>
44
45#include "mlx4.h"
46#include "fw.h"
47#include "icm.h"
48
49MODULE_AUTHOR("Roland Dreier");
50MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
51MODULE_LICENSE("Dual BSD/GPL");
52MODULE_VERSION(DRV_VERSION);
53
27bf91d6
YP		 54struct workqueue_struct *mlx4_wq;
55
225c7b1f
RD		 56#ifdef CONFIG_MLX4_DEBUG
57
58int mlx4_debug_level = 0;
59module_param_named(debug_level, mlx4_debug_level, int, 0644);
60MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
61
62#endif /* CONFIG_MLX4_DEBUG */
63
64#ifdef CONFIG_PCI_MSI
65
08fb1055 66static int msi_x = 1;
225c7b1f
RD		 67module_param(msi_x, int, 0444);
68MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
69
70#else /* CONFIG_PCI_MSI */
71
72#define msi_x (0)
73
74#endif /* CONFIG_PCI_MSI */
75
f33afc26 76static char mlx4_version[] __devinitdata =
225c7b1f
RD		 77 DRV_NAME ": Mellanox ConnectX core driver v"
78 DRV_VERSION " (" DRV_RELDATE ")\n";
79
80static struct mlx4_profile default_profile = {
9b1f3851 81 .num_qp = 1 << 17,
225c7b1f 82 .num_srq = 1 << 16,
c9f2ba5e 83 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 84 .num_cq = 1 << 16,
85 .num_mcg = 1 << 13,
86 .num_mpt = 1 << 17,
87 .num_mtt = 1 << 20,
88};
89
93fc9e1b
YP		 90static int log_num_mac = 2;
91module_param_named(log_num_mac, log_num_mac, int, 0444);
92MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
93
94static int log_num_vlan;
95module_param_named(log_num_vlan, log_num_vlan, int, 0444);
96MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
97
98static int use_prio;
99module_param_named(use_prio, use_prio, bool, 0444);
100MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
101 "(0/1, default 0)");
102
27bf91d6
YP		 103int mlx4_check_port_params(struct mlx4_dev *dev,
104 enum mlx4_port_type *port_type)
7ff93f8b
YP		 105{
106 int i;
107
108 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 109 if (port_type[i] != port_type[i + 1]) {
110 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
111 mlx4_err(dev, "Only same port types supported "
112 "on this HCA, aborting.\n");
113 return -EINVAL;
114 }
115 if (port_type[i] == MLX4_PORT_TYPE_ETH &&
116 port_type[i + 1] == MLX4_PORT_TYPE_IB)
117 return -EINVAL;
7ff93f8b
YP		 118 }
119 }
7ff93f8b
YP		 120
121 for (i = 0; i < dev->caps.num_ports; i++) {
122 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
123 mlx4_err(dev, "Requested port type for port %d is not "
124 "supported on this HCA\n", i + 1);
125 return -EINVAL;
126 }
127 }
128 return 0;
129}
130
131static void mlx4_set_port_mask(struct mlx4_dev *dev)
132{
133 int i;
134
135 dev->caps.port_mask = 0;
136 for (i = 1; i <= dev->caps.num_ports; ++i)
137 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_IB)
138 dev->caps.port_mask |= 1 << (i - 1);
139}
3d73c288 140static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 141{
142 int err;
5ae2a7a8 143 int i;
225c7b1f
RD		 144
145 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
146 if (err) {
147 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
148 return err;
149 }
150
151 if (dev_cap->min_page_sz > PAGE_SIZE) {
152 mlx4_err(dev, "HCA minimum page size of %d bigger than "
153 "kernel PAGE_SIZE of %ld, aborting.\n",
154 dev_cap->min_page_sz, PAGE_SIZE);
155 return -ENODEV;
156 }
157 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
158 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
159 "aborting.\n",
160 dev_cap->num_ports, MLX4_MAX_PORTS);
161 return -ENODEV;
162 }
163
164 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
165 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
166 "PCI resource 2 size of 0x%llx, aborting.\n",
167 dev_cap->uar_size,
168 (unsigned long long) pci_resource_len(dev->pdev, 2));
169 return -ENODEV;
170 }
171
172 dev->caps.num_ports = dev_cap->num_ports;
5ae2a7a8
RD		 173 for (i = 1; i <= dev->caps.num_ports; ++i) {
174 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 175 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
5ae2a7a8
RD		 176 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
177 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
178 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 179 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
180 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 181 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
5ae2a7a8
RD		 182 }
183
225c7b1f 184 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 185 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
186 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
187 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
188 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
189 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
190 dev->caps.max_wqes = dev_cap->max_qp_sz;
191 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 192 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
193 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
194 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
195 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
196 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
197 dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM;
198 /*
199 * Subtract 1 from the limit because we need to allocate a
200 * spare CQE so the HCA HW can tell the difference between an
201 * empty CQ and a full CQ.
202 */
203 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
204 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
205 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
121964ec
RD		 206 dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
207 MLX4_MTT_ENTRY_PER_SEG);
225c7b1f
RD		 208 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
209 dev->caps.reserved_uars = dev_cap->reserved_uars;
210 dev->caps.reserved_pds = dev_cap->reserved_pds;
225c7b1f 211 dev->caps.mtt_entry_sz = MLX4_MTT_ENTRY_PER_SEG * dev_cap->mtt_entry_sz;
149983af 212 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 213 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
214 dev->caps.flags = dev_cap->flags;
95d04f07
RD		 215 dev->caps.bmme_flags = dev_cap->bmme_flags;
216 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 217 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 218 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
225c7b1f 219
93fc9e1b
YP		 220 dev->caps.log_num_macs = log_num_mac;
221 dev->caps.log_num_vlans = log_num_vlan;
222 dev->caps.log_num_prios = use_prio ? 3 : 0;
223
224 for (i = 1; i <= dev->caps.num_ports; ++i) {
7ff93f8b
YP		 225 if (dev->caps.supported_type[i] != MLX4_PORT_TYPE_ETH)
226 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
227 else
228 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 229 dev->caps.possible_type[i] = dev->caps.port_type[i];
230 mlx4_priv(dev)->sense.sense_allowed[i] =
231 dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO;
7ff93f8b 232
93fc9e1b
YP		 233 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
234 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
235 mlx4_warn(dev, "Requested number of MACs is too much "
236 "for port %d, reducing to %d.\n",
237 i, 1 << dev->caps.log_num_macs);
238 }
239 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
240 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
241 mlx4_warn(dev, "Requested number of VLANs is too much "
242 "for port %d, reducing to %d.\n",
243 i, 1 << dev->caps.log_num_vlans);
244 }
245 }
246
7ff93f8b
YP		 247 mlx4_set_port_mask(dev);
248
93fc9e1b
YP		 249 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
250 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
251 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
252 (1 << dev->caps.log_num_macs) *
253 (1 << dev->caps.log_num_vlans) *
254 (1 << dev->caps.log_num_prios) *
255 dev->caps.num_ports;
256 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
257
258 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
259 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
260 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
261 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
262
225c7b1f
RD		 263 return 0;
264}
265
7ff93f8b
YP		 266/*
267 * Change the port configuration of the device.
268 * Every user of this function must hold the port mutex.
269 */
27bf91d6
YP		 270int mlx4_change_port_types(struct mlx4_dev *dev,
271 enum mlx4_port_type *port_types)
7ff93f8b
YP		 272{
273 int err = 0;
274 int change = 0;
275 int port;
276
277 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 278 /* Change the port type only if the new type is different
279 * from the current, and not set to Auto */
7ff93f8b
YP		 280 if (port_types[port] != dev->caps.port_type[port + 1]) {
281 change = 1;
282 dev->caps.port_type[port + 1] = port_types[port];
283 }
284 }
285 if (change) {
286 mlx4_unregister_device(dev);
287 for (port = 1; port <= dev->caps.num_ports; port++) {
288 mlx4_CLOSE_PORT(dev, port);
289 err = mlx4_SET_PORT(dev, port);
290 if (err) {
291 mlx4_err(dev, "Failed to set port %d, "
292 "aborting\n", port);
293 goto out;
294 }
295 }
296 mlx4_set_port_mask(dev);
297 err = mlx4_register_device(dev);
298 }
299
300out:
301 return err;
302}
303
304static ssize_t show_port_type(struct device *dev,
305 struct device_attribute *attr,
306 char *buf)
307{
308 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
309 port_attr);
310 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 311 char type[8];
312
313 sprintf(type, "%s",
314 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
315 "ib" : "eth");
316 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
317 sprintf(buf, "auto (%s)\n", type);
318 else
319 sprintf(buf, "%s\n", type);
7ff93f8b 320
27bf91d6 321 return strlen(buf);
7ff93f8b
YP		 322}
323
324static ssize_t set_port_type(struct device *dev,
325 struct device_attribute *attr,
326 const char *buf, size_t count)
327{
328 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
329 port_attr);
330 struct mlx4_dev *mdev = info->dev;
331 struct mlx4_priv *priv = mlx4_priv(mdev);
332 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 333 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 334 int i;
335 int err = 0;
336
337 if (!strcmp(buf, "ib\n"))
338 info->tmp_type = MLX4_PORT_TYPE_IB;
339 else if (!strcmp(buf, "eth\n"))
340 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 341 else if (!strcmp(buf, "auto\n"))
342 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 343 else {
344 mlx4_err(mdev, "%s is not supported port type\n", buf);
345 return -EINVAL;
346 }
347
27bf91d6 348 mlx4_stop_sense(mdev);
7ff93f8b 349 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 350 /* Possible type is always the one that was delivered */
351 mdev->caps.possible_type[info->port] = info->tmp_type;
352
353 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 354 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 355 mdev->caps.possible_type[i+1];
356 if (types[i] == MLX4_PORT_TYPE_AUTO)
357 types[i] = mdev->caps.port_type[i+1];
358 }
7ff93f8b 359
27bf91d6
YP		 360 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
361 for (i = 1; i <= mdev->caps.num_ports; i++) {
362 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
363 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
364 err = -EINVAL;
365 }
366 }
367 }
368 if (err) {
369 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
370 "Set only 'eth' or 'ib' for both ports "
371 "(should be the same)\n");
372 goto out;
373 }
374
375 mlx4_do_sense_ports(mdev, new_types, types);
376
377 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 378 if (err)
379 goto out;
380
27bf91d6
YP		 381 /* We are about to apply the changes after the configuration
382 * was verified, no need to remember the temporary types
383 * any more */
384 for (i = 0; i < mdev->caps.num_ports; i++)
385 priv->port[i + 1].tmp_type = 0;
7ff93f8b 386
27bf91d6 387 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 388
389out:
27bf91d6 390 mlx4_start_sense(mdev);
7ff93f8b
YP		 391 mutex_unlock(&priv->port_mutex);
392 return err ? err : count;
393}
394
e8f9b2ed 395static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 396{
397 struct mlx4_priv *priv = mlx4_priv(dev);
398 int err;
399
400 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 401 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 402 if (!priv->fw.fw_icm) {
403 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
404 return -ENOMEM;
405 }
406
407 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
408 if (err) {
409 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
410 goto err_free;
411 }
412
413 err = mlx4_RUN_FW(dev);
414 if (err) {
415 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
416 goto err_unmap_fa;
417 }
418
419 return 0;
420
421err_unmap_fa:
422 mlx4_UNMAP_FA(dev);
423
424err_free:
5b0bf5e2 425 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 426 return err;
427}
428
e8f9b2ed
RD		 429static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
430 int cmpt_entry_sz)
225c7b1f
RD		 431{
432 struct mlx4_priv *priv = mlx4_priv(dev);
433 int err;
434
435 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
436 cmpt_base +
437 ((u64) (MLX4_CMPT_TYPE_QP *
438 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
439 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 440 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
441 0, 0);
225c7b1f
RD		 442 if (err)
443 goto err;
444
445 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
446 cmpt_base +
447 ((u64) (MLX4_CMPT_TYPE_SRQ *
448 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
449 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 450 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 451 if (err)
452 goto err_qp;
453
454 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
455 cmpt_base +
456 ((u64) (MLX4_CMPT_TYPE_CQ *
457 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
458 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 459 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 460 if (err)
461 goto err_srq;
462
463 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
464 cmpt_base +
465 ((u64) (MLX4_CMPT_TYPE_EQ *
466 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
467 cmpt_entry_sz,
b8dd786f 468 dev->caps.num_eqs, dev->caps.num_eqs, 0, 0);
225c7b1f
RD		 469 if (err)
470 goto err_cq;
471
472 return 0;
473
474err_cq:
475 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
476
477err_srq:
478 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
479
480err_qp:
481 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
482
483err:
484 return err;
485}
486
3d73c288
RD		 487static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
488 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 489{
490 struct mlx4_priv *priv = mlx4_priv(dev);
491 u64 aux_pages;
492 int err;
493
494 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
495 if (err) {
496 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
497 return err;
498 }
499
500 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
501 (unsigned long long) icm_size >> 10,
502 (unsigned long long) aux_pages << 2);
503
504 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 505 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 506 if (!priv->fw.aux_icm) {
507 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
508 return -ENOMEM;
509 }
510
511 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
512 if (err) {
513 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
514 goto err_free_aux;
515 }
516
517 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
518 if (err) {
519 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
520 goto err_unmap_aux;
521 }
522
523 err = mlx4_map_eq_icm(dev, init_hca->eqc_base);
524 if (err) {
525 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
526 goto err_unmap_cmpt;
527 }
528
d7bb58fb
JM		 529 /*
530 * Reserved MTT entries must be aligned up to a cacheline
531 * boundary, since the FW will write to them, while the driver
532 * writes to all other MTT entries. (The variable
533 * dev->caps.mtt_entry_sz below is really the MTT segment
534 * size, not the raw entry size)
535 */
536 dev->caps.reserved_mtts =
537 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
538 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
539
225c7b1f
RD		 540 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
541 init_hca->mtt_base,
542 dev->caps.mtt_entry_sz,
543 dev->caps.num_mtt_segs,
5b0bf5e2 544 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 545 if (err) {
546 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
547 goto err_unmap_eq;
548 }
549
550 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
551 init_hca->dmpt_base,
552 dev_cap->dmpt_entry_sz,
553 dev->caps.num_mpts,
5b0bf5e2 554 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 555 if (err) {
556 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
557 goto err_unmap_mtt;
558 }
559
560 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
561 init_hca->qpc_base,
562 dev_cap->qpc_entry_sz,
563 dev->caps.num_qps,
93fc9e1b
YP		 564 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
565 0, 0);
225c7b1f
RD		 566 if (err) {
567 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
568 goto err_unmap_dmpt;
569 }
570
571 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
572 init_hca->auxc_base,
573 dev_cap->aux_entry_sz,
574 dev->caps.num_qps,
93fc9e1b
YP		 575 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
576 0, 0);
225c7b1f
RD		 577 if (err) {
578 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
579 goto err_unmap_qp;
580 }
581
582 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
583 init_hca->altc_base,
584 dev_cap->altc_entry_sz,
585 dev->caps.num_qps,
93fc9e1b
YP		 586 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
587 0, 0);
225c7b1f
RD		 588 if (err) {
589 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
590 goto err_unmap_auxc;
591 }
592
593 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
594 init_hca->rdmarc_base,
595 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
596 dev->caps.num_qps,
93fc9e1b
YP		 597 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
598 0, 0);
225c7b1f
RD		 599 if (err) {
600 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
601 goto err_unmap_altc;
602 }
603
604 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
605 init_hca->cqc_base,
606 dev_cap->cqc_entry_sz,
607 dev->caps.num_cqs,
5b0bf5e2 608 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 609 if (err) {
610 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
611 goto err_unmap_rdmarc;
612 }
613
614 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
615 init_hca->srqc_base,
616 dev_cap->srq_entry_sz,
617 dev->caps.num_srqs,
5b0bf5e2 618 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 619 if (err) {
620 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
621 goto err_unmap_cq;
622 }
623
624 /*
625 * It's not strictly required, but for simplicity just map the
626 * whole multicast group table now. The table isn't very big
627 * and it's a lot easier than trying to track ref counts.
628 */
629 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
630 init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
631 dev->caps.num_mgms + dev->caps.num_amgms,
632 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 633 0, 0);
225c7b1f
RD		 634 if (err) {
635 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
636 goto err_unmap_srq;
637 }
638
639 return 0;
640
641err_unmap_srq:
642 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
643
644err_unmap_cq:
645 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
646
647err_unmap_rdmarc:
648 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
649
650err_unmap_altc:
651 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
652
653err_unmap_auxc:
654 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
655
656err_unmap_qp:
657 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
658
659err_unmap_dmpt:
660 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
661
662err_unmap_mtt:
663 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
664
665err_unmap_eq:
666 mlx4_unmap_eq_icm(dev);
667
668err_unmap_cmpt:
669 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
670 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
671 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
672 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
673
674err_unmap_aux:
675 mlx4_UNMAP_ICM_AUX(dev);
676
677err_free_aux:
5b0bf5e2 678 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 679
680 return err;
681}
682
683static void mlx4_free_icms(struct mlx4_dev *dev)
684{
685 struct mlx4_priv *priv = mlx4_priv(dev);
686
687 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
688 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
689 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
690 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
691 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
692 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
693 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
694 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
695 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
696 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
697 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
698 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
699 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
700 mlx4_unmap_eq_icm(dev);
701
702 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 703 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 704}
705
706static void mlx4_close_hca(struct mlx4_dev *dev)
707{
708 mlx4_CLOSE_HCA(dev, 0);
709 mlx4_free_icms(dev);
710 mlx4_UNMAP_FA(dev);
5b0bf5e2 711 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
225c7b1f
RD		 712}
713
3d73c288 714static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 715{
716 struct mlx4_priv *priv = mlx4_priv(dev);
717 struct mlx4_adapter adapter;
718 struct mlx4_dev_cap dev_cap;
2d928651 719 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 720 struct mlx4_profile profile;
721 struct mlx4_init_hca_param init_hca;
722 u64 icm_size;
723 int err;
724
725 err = mlx4_QUERY_FW(dev);
726 if (err) {
727 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
728 return err;
729 }
730
731 err = mlx4_load_fw(dev);
732 if (err) {
733 mlx4_err(dev, "Failed to start FW, aborting.\n");
734 return err;
735 }
736
2d928651
VS		 737 mlx4_cfg.log_pg_sz_m = 1;
738 mlx4_cfg.log_pg_sz = 0;
739 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
740 if (err)
741 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
742
225c7b1f
RD		 743 err = mlx4_dev_cap(dev, &dev_cap);
744 if (err) {
745 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
746 goto err_stop_fw;
747 }
748
749 profile = default_profile;
750
751 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
752 if ((long long) icm_size < 0) {
753 err = icm_size;
754 goto err_stop_fw;
755 }
756
757 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
758
759 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
760 if (err)
761 goto err_stop_fw;
762
763 err = mlx4_INIT_HCA(dev, &init_hca);
764 if (err) {
765 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
766 goto err_free_icm;
767 }
768
769 err = mlx4_QUERY_ADAPTER(dev, &adapter);
770 if (err) {
771 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
772 goto err_close;
773 }
774
775 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 776 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 777
778 return 0;
779
780err_close:
781 mlx4_close_hca(dev);
782
783err_free_icm:
784 mlx4_free_icms(dev);
785
786err_stop_fw:
787 mlx4_UNMAP_FA(dev);
5b0bf5e2 788 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 789
790 return err;
791}
792
3d73c288 793static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 794{
795 struct mlx4_priv *priv = mlx4_priv(dev);
796 int err;
7ff93f8b 797 int port;
9a5aa622 798 __be32 ib_port_default_caps;
225c7b1f 799
225c7b1f
RD		 800 err = mlx4_init_uar_table(dev);
801 if (err) {
802 mlx4_err(dev, "Failed to initialize "
803 "user access region table, aborting.\n");
804 return err;
805 }
806
807 err = mlx4_uar_alloc(dev, &priv->driver_uar);
808 if (err) {
809 mlx4_err(dev, "Failed to allocate driver access region, "
810 "aborting.\n");
811 goto err_uar_table_free;
812 }
813
814 priv->kar = ioremap(priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
815 if (!priv->kar) {
816 mlx4_err(dev, "Couldn't map kernel access region, "
817 "aborting.\n");
818 err = -ENOMEM;
819 goto err_uar_free;
820 }
821
822 err = mlx4_init_pd_table(dev);
823 if (err) {
824 mlx4_err(dev, "Failed to initialize "
825 "protection domain table, aborting.\n");
826 goto err_kar_unmap;
827 }
828
829 err = mlx4_init_mr_table(dev);
830 if (err) {
831 mlx4_err(dev, "Failed to initialize "
832 "memory region table, aborting.\n");
833 goto err_pd_table_free;
834 }
835
225c7b1f
RD		 836 err = mlx4_init_eq_table(dev);
837 if (err) {
838 mlx4_err(dev, "Failed to initialize "
839 "event queue table, aborting.\n");
ee49bd93 840 goto err_mr_table_free;
225c7b1f
RD		 841 }
842
843 err = mlx4_cmd_use_events(dev);
844 if (err) {
845 mlx4_err(dev, "Failed to switch to event-driven "
846 "firmware commands, aborting.\n");
847 goto err_eq_table_free;
848 }
849
850 err = mlx4_NOP(dev);
851 if (err) {
08fb1055
MT		 852 if (dev->flags & MLX4_FLAG_MSI_X) {
853 mlx4_warn(dev, "NOP command failed to generate MSI-X "
854 "interrupt IRQ %d).\n",
b8dd786f 855 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
08fb1055
MT		 856 mlx4_warn(dev, "Trying again without MSI-X.\n");
857 } else {
858 mlx4_err(dev, "NOP command failed to generate interrupt "
859 "(IRQ %d), aborting.\n",
b8dd786f 860 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 861 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 862 }
225c7b1f
RD		 863
864 goto err_cmd_poll;
865 }
866
867 mlx4_dbg(dev, "NOP command IRQ test passed\n");
868
869 err = mlx4_init_cq_table(dev);
870 if (err) {
871 mlx4_err(dev, "Failed to initialize "
872 "completion queue table, aborting.\n");
873 goto err_cmd_poll;
874 }
875
876 err = mlx4_init_srq_table(dev);
877 if (err) {
878 mlx4_err(dev, "Failed to initialize "
879 "shared receive queue table, aborting.\n");
880 goto err_cq_table_free;
881 }
882
883 err = mlx4_init_qp_table(dev);
884 if (err) {
885 mlx4_err(dev, "Failed to initialize "
886 "queue pair table, aborting.\n");
887 goto err_srq_table_free;
888 }
889
890 err = mlx4_init_mcg_table(dev);
891 if (err) {
892 mlx4_err(dev, "Failed to initialize "
893 "multicast group table, aborting.\n");
894 goto err_qp_table_free;
895 }
896
7ff93f8b 897 for (port = 1; port <= dev->caps.num_ports; port++) {
9a5aa622
JM		 898 ib_port_default_caps = 0;
899 err = mlx4_get_port_ib_caps(dev, port, &ib_port_default_caps);
900 if (err)
901 mlx4_warn(dev, "failed to get port %d default "
902 "ib capabilities (%d). Continuing with "
903 "caps = 0\n", port, err);
904 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
7ff93f8b
YP		 905 err = mlx4_SET_PORT(dev, port);
906 if (err) {
907 mlx4_err(dev, "Failed to set port %d, aborting\n",
908 port);
909 goto err_mcg_table_free;
910 }
911 }
912
225c7b1f
RD		 913 return 0;
914
7ff93f8b
YP		 915err_mcg_table_free:
916 mlx4_cleanup_mcg_table(dev);
917
225c7b1f
RD		 918err_qp_table_free:
919 mlx4_cleanup_qp_table(dev);
920
921err_srq_table_free:
922 mlx4_cleanup_srq_table(dev);
923
924err_cq_table_free:
925 mlx4_cleanup_cq_table(dev);
926
927err_cmd_poll:
928 mlx4_cmd_use_polling(dev);
929
930err_eq_table_free:
931 mlx4_cleanup_eq_table(dev);
932
ee49bd93 933err_mr_table_free:
225c7b1f
RD		 934 mlx4_cleanup_mr_table(dev);
935
936err_pd_table_free:
937 mlx4_cleanup_pd_table(dev);
938
939err_kar_unmap:
940 iounmap(priv->kar);
941
942err_uar_free:
943 mlx4_uar_free(dev, &priv->driver_uar);
944
945err_uar_table_free:
946 mlx4_cleanup_uar_table(dev);
947 return err;
948}
949
e8f9b2ed 950static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 951{
952 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f
YP		 953 struct msix_entry *entries;
954 int nreq;
225c7b1f
RD		 955 int err;
956 int i;
957
958 if (msi_x) {
70cb9253
RD		 959 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
960 num_possible_cpus() + 1);
b8dd786f
YP		 961 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
962 if (!entries)
963 goto no_msi;
964
965 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 966 entries[i].entry = i;
967
b8dd786f
YP		 968 retry:
969 err = pci_enable_msix(dev->pdev, entries, nreq);
225c7b1f 970 if (err) {
b8dd786f
YP		 971 /* Try again if at least 2 vectors are available */
972 if (err > 1) {
973 mlx4_info(dev, "Requested %d vectors, "
974 "but only %d MSI-X vectors available, "
975 "trying again\n", nreq, err);
976 nreq = err;
977 goto retry;
978 }
979
225c7b1f
RD		 980 goto no_msi;
981 }
982
b8dd786f
YP		 983 dev->caps.num_comp_vectors = nreq - 1;
984 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 985 priv->eq_table.eq[i].irq = entries[i].vector;
986
987 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 988
989 kfree(entries);
225c7b1f
RD		 990 return;
991 }
992
993no_msi:
b8dd786f
YP		 994 dev->caps.num_comp_vectors = 1;
995
996 for (i = 0; i < 2; ++i)
225c7b1f
RD		 997 priv->eq_table.eq[i].irq = dev->pdev->irq;
998}
999
7ff93f8b 1000static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 1001{
1002 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 1003 int err = 0;
2a2336f8
YP		 1004
1005 info->dev = dev;
1006 info->port = port;
1007 mlx4_init_mac_table(dev, &info->mac_table);
1008 mlx4_init_vlan_table(dev, &info->vlan_table);
7ff93f8b
YP		 1009
1010 sprintf(info->dev_name, "mlx4_port%d", port);
1011 info->port_attr.attr.name = info->dev_name;
1012 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1013 info->port_attr.show = show_port_type;
1014 info->port_attr.store = set_port_type;
1015
1016 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1017 if (err) {
1018 mlx4_err(dev, "Failed to create file for port %d\n", port);
1019 info->port = -1;
1020 }
1021
1022 return err;
1023}
1024
1025static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1026{
1027 if (info->port < 0)
1028 return;
1029
1030 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2a2336f8
YP		 1031}
1032
3d73c288 1033static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
225c7b1f 1034{
225c7b1f
RD		 1035 struct mlx4_priv *priv;
1036 struct mlx4_dev *dev;
1037 int err;
2a2336f8 1038 int port;
225c7b1f 1039
225c7b1f
RD		 1040 printk(KERN_INFO PFX "Initializing %s\n",
1041 pci_name(pdev));
1042
1043 err = pci_enable_device(pdev);
1044 if (err) {
1045 dev_err(&pdev->dev, "Cannot enable PCI device, "
1046 "aborting.\n");
1047 return err;
1048 }
1049
1050 /*
4ff08a76 1051 * Check for BARs. We expect 0: 1MB
225c7b1f
RD		 1052 */
1053 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
1054 pci_resource_len(pdev, 0) != 1 << 20) {
1055 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
1056 err = -ENODEV;
1057 goto err_disable_pdev;
1058 }
1059 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1060 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1061 err = -ENODEV;
1062 goto err_disable_pdev;
1063 }
1064
1065 err = pci_request_region(pdev, 0, DRV_NAME);
1066 if (err) {
1067 dev_err(&pdev->dev, "Cannot request control region, aborting.\n");
1068 goto err_disable_pdev;
1069 }
1070
1071 err = pci_request_region(pdev, 2, DRV_NAME);
1072 if (err) {
1073 dev_err(&pdev->dev, "Cannot request UAR region, aborting.\n");
1074 goto err_release_bar0;
1075 }
1076
1077 pci_set_master(pdev);
1078
1079 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1080 if (err) {
1081 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
1082 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1083 if (err) {
1084 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
1085 goto err_release_bar2;
1086 }
1087 }
1088 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1089 if (err) {
1090 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1091 "consistent PCI DMA mask.\n");
1092 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1093 if (err) {
1094 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1095 "aborting.\n");
1096 goto err_release_bar2;
1097 }
1098 }
1099
1100 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1101 if (!priv) {
1102 dev_err(&pdev->dev, "Device struct alloc failed, "
1103 "aborting.\n");
1104 err = -ENOMEM;
1105 goto err_release_bar2;
1106 }
1107
1108 dev = &priv->dev;
1109 dev->pdev = pdev;
b581401e
RD		 1110 INIT_LIST_HEAD(&priv->ctx_list);
1111 spin_lock_init(&priv->ctx_lock);
225c7b1f 1112
7ff93f8b
YP		 1113 mutex_init(&priv->port_mutex);
1114
6296883c
YP		 1115 INIT_LIST_HEAD(&priv->pgdir_list);
1116 mutex_init(&priv->pgdir_mutex);
1117
225c7b1f
RD		 1118 /*
1119 * Now reset the HCA before we touch the PCI capabilities or
1120 * attempt a firmware command, since a boot ROM may have left
1121 * the HCA in an undefined state.
1122 */
1123 err = mlx4_reset(dev);
1124 if (err) {
1125 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1126 goto err_free_dev;
1127 }
1128
225c7b1f
RD		 1129 if (mlx4_cmd_init(dev)) {
1130 mlx4_err(dev, "Failed to init command interface, aborting.\n");
1131 goto err_free_dev;
1132 }
1133
1134 err = mlx4_init_hca(dev);
1135 if (err)
1136 goto err_cmd;
1137
b8dd786f
YP		 1138 err = mlx4_alloc_eq_table(dev);
1139 if (err)
1140 goto err_close;
1141
08fb1055
MT		 1142 mlx4_enable_msi_x(dev);
1143
225c7b1f 1144 err = mlx4_setup_hca(dev);
08fb1055
MT		 1145 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
1146 dev->flags &= ~MLX4_FLAG_MSI_X;
1147 pci_disable_msix(pdev);
1148 err = mlx4_setup_hca(dev);
1149 }
1150
225c7b1f 1151 if (err)
b8dd786f 1152 goto err_free_eq;
225c7b1f 1153
7ff93f8b
YP		 1154 for (port = 1; port <= dev->caps.num_ports; port++) {
1155 err = mlx4_init_port_info(dev, port);
1156 if (err)
1157 goto err_port;
1158 }
2a2336f8 1159
225c7b1f
RD		 1160 err = mlx4_register_device(dev);
1161 if (err)
7ff93f8b 1162 goto err_port;
225c7b1f 1163
27bf91d6
YP		 1164 mlx4_sense_init(dev);
1165 mlx4_start_sense(dev);
1166
225c7b1f
RD		 1167 pci_set_drvdata(pdev, dev);
1168
1169 return 0;
1170
7ff93f8b
YP		 1171err_port:
1172 for (port = 1; port <= dev->caps.num_ports; port++)
1173 mlx4_cleanup_port_info(&priv->port[port]);
1174
225c7b1f
RD		 1175 mlx4_cleanup_mcg_table(dev);
1176 mlx4_cleanup_qp_table(dev);
1177 mlx4_cleanup_srq_table(dev);
1178 mlx4_cleanup_cq_table(dev);
1179 mlx4_cmd_use_polling(dev);
1180 mlx4_cleanup_eq_table(dev);
225c7b1f
RD		 1181 mlx4_cleanup_mr_table(dev);
1182 mlx4_cleanup_pd_table(dev);
1183 mlx4_cleanup_uar_table(dev);
1184
b8dd786f
YP		 1185err_free_eq:
1186 mlx4_free_eq_table(dev);
1187
225c7b1f 1188err_close:
08fb1055
MT		 1189 if (dev->flags & MLX4_FLAG_MSI_X)
1190 pci_disable_msix(pdev);
1191
225c7b1f
RD		 1192 mlx4_close_hca(dev);
1193
1194err_cmd:
1195 mlx4_cmd_cleanup(dev);
1196
1197err_free_dev:
225c7b1f
RD		 1198 kfree(priv);
1199
1200err_release_bar2:
1201 pci_release_region(pdev, 2);
1202
1203err_release_bar0:
1204 pci_release_region(pdev, 0);
1205
1206err_disable_pdev:
1207 pci_disable_device(pdev);
1208 pci_set_drvdata(pdev, NULL);
1209 return err;
1210}
1211
3d73c288
RD		 1212static int __devinit mlx4_init_one(struct pci_dev *pdev,
1213 const struct pci_device_id *id)
1214{
1215 static int mlx4_version_printed;
1216
1217 if (!mlx4_version_printed) {
1218 printk(KERN_INFO "%s", mlx4_version);
1219 ++mlx4_version_printed;
1220 }
1221
b027cacd 1222 return __mlx4_init_one(pdev, id);
3d73c288
RD		 1223}
1224
1225static void mlx4_remove_one(struct pci_dev *pdev)
225c7b1f
RD		 1226{
1227 struct mlx4_dev *dev = pci_get_drvdata(pdev);
1228 struct mlx4_priv *priv = mlx4_priv(dev);
1229 int p;
1230
1231 if (dev) {
27bf91d6 1232 mlx4_stop_sense(dev);
225c7b1f
RD		 1233 mlx4_unregister_device(dev);
1234
7ff93f8b
YP		 1235 for (p = 1; p <= dev->caps.num_ports; p++) {
1236 mlx4_cleanup_port_info(&priv->port[p]);
225c7b1f 1237 mlx4_CLOSE_PORT(dev, p);
7ff93f8b 1238 }
225c7b1f
RD		 1239
1240 mlx4_cleanup_mcg_table(dev);
1241 mlx4_cleanup_qp_table(dev);
1242 mlx4_cleanup_srq_table(dev);
1243 mlx4_cleanup_cq_table(dev);
1244 mlx4_cmd_use_polling(dev);
1245 mlx4_cleanup_eq_table(dev);
225c7b1f
RD		 1246 mlx4_cleanup_mr_table(dev);
1247 mlx4_cleanup_pd_table(dev);
1248
1249 iounmap(priv->kar);
1250 mlx4_uar_free(dev, &priv->driver_uar);
1251 mlx4_cleanup_uar_table(dev);
b8dd786f 1252 mlx4_free_eq_table(dev);
225c7b1f
RD		 1253 mlx4_close_hca(dev);
1254 mlx4_cmd_cleanup(dev);
1255
1256 if (dev->flags & MLX4_FLAG_MSI_X)
1257 pci_disable_msix(pdev);
1258
1259 kfree(priv);
1260 pci_release_region(pdev, 2);
1261 pci_release_region(pdev, 0);
1262 pci_disable_device(pdev);
1263 pci_set_drvdata(pdev, NULL);
1264 }
1265}
1266
ee49bd93
JM		 1267int mlx4_restart_one(struct pci_dev *pdev)
1268{
1269 mlx4_remove_one(pdev);
3d73c288 1270 return __mlx4_init_one(pdev, NULL);
ee49bd93
JM		 1271}
1272
225c7b1f
RD		 1273static struct pci_device_id mlx4_pci_table[] = {
1274 { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
1275 { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
1276 { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
786f238e
JM		 1277 { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
1278 { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
57893d1c
YP		 1279 { PCI_VDEVICE(MELLANOX, 0x6368) }, /* MT25408 "Hermon" EN 10GigE */
1280 { PCI_VDEVICE(MELLANOX, 0x6750) }, /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
085343b4
JM		 1281 { PCI_VDEVICE(MELLANOX, 0x6372) }, /* MT25458 ConnectX EN 10GBASE-T 10GigE */
1282 { PCI_VDEVICE(MELLANOX, 0x675a) }, /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
225c7b1f
RD		 1283 { 0, }
1284};
1285
1286MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
1287
1288static struct pci_driver mlx4_driver = {
1289 .name = DRV_NAME,
1290 .id_table = mlx4_pci_table,
1291 .probe = mlx4_init_one,
1292 .remove = __devexit_p(mlx4_remove_one)
1293};
1294
7ff93f8b
YP		 1295static int __init mlx4_verify_params(void)
1296{
1297 if ((log_num_mac < 0) || (log_num_mac > 7)) {
1298 printk(KERN_WARNING "mlx4_core: bad num_mac: %d\n", log_num_mac);
1299 return -1;
1300 }
1301
1302 if ((log_num_vlan < 0) || (log_num_vlan > 7)) {
1303 printk(KERN_WARNING "mlx4_core: bad num_vlan: %d\n", log_num_vlan);
1304 return -1;
1305 }
1306
1307 return 0;
1308}
1309
225c7b1f
RD		 1310static int __init mlx4_init(void)
1311{
1312 int ret;
1313
7ff93f8b
YP		 1314 if (mlx4_verify_params())
1315 return -EINVAL;
1316
27bf91d6
YP		 1317 mlx4_catas_init();
1318
1319 mlx4_wq = create_singlethread_workqueue("mlx4");
1320 if (!mlx4_wq)
1321 return -ENOMEM;
ee49bd93 1322
225c7b1f
RD		 1323 ret = pci_register_driver(&mlx4_driver);
1324 return ret < 0 ? ret : 0;
1325}
1326
1327static void __exit mlx4_cleanup(void)
1328{
1329 pci_unregister_driver(&mlx4_driver);
27bf91d6 1330 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 1331}
1332
1333module_init(mlx4_init);
1334module_exit(mlx4_cleanup);
kernel source for telekom puls (alcatel/mediatek)