projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Linux 2.6.28-rc7
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
41
42#include <linux/mlx4/device.h>
43#include <linux/mlx4/doorbell.h>
44
45#include "mlx4.h"
46#include "fw.h"
47#include "icm.h"
48
49MODULE_AUTHOR("Roland Dreier");
50MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
51MODULE_LICENSE("Dual BSD/GPL");
52MODULE_VERSION(DRV_VERSION);
53
54#ifdef CONFIG_MLX4_DEBUG
55
56int mlx4_debug_level = 0;
57module_param_named(debug_level, mlx4_debug_level, int, 0644);
58MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
59
60#endif /* CONFIG_MLX4_DEBUG */
61
62#ifdef CONFIG_PCI_MSI
63
08fb1055 64static int msi_x = 1;
225c7b1f
RD		 65module_param(msi_x, int, 0444);
66MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
67
68#else /* CONFIG_PCI_MSI */
69
70#define msi_x (0)
71
72#endif /* CONFIG_PCI_MSI */
73
f33afc26 74static char mlx4_version[] __devinitdata =
225c7b1f
RD		 75 DRV_NAME ": Mellanox ConnectX core driver v"
76 DRV_VERSION " (" DRV_RELDATE ")\n";
77
78static struct mlx4_profile default_profile = {
9b1f3851 79 .num_qp = 1 << 17,
225c7b1f 80 .num_srq = 1 << 16,
c9f2ba5e 81 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 82 .num_cq = 1 << 16,
83 .num_mcg = 1 << 13,
84 .num_mpt = 1 << 17,
85 .num_mtt = 1 << 20,
86};
87
93fc9e1b
YP		 88static int log_num_mac = 2;
89module_param_named(log_num_mac, log_num_mac, int, 0444);
90MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
91
92static int log_num_vlan;
93module_param_named(log_num_vlan, log_num_vlan, int, 0444);
94MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
95
96static int use_prio;
97module_param_named(use_prio, use_prio, bool, 0444);
98MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
99 "(0/1, default 0)");
100
7ff93f8b
YP		 101static int mlx4_check_port_params(struct mlx4_dev *dev,
102 enum mlx4_port_type *port_type)
103{
104 int i;
105
106 for (i = 0; i < dev->caps.num_ports - 1; i++) {
107 if (port_type[i] != port_type[i+1] &&
108 !(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
109 mlx4_err(dev, "Only same port types supported "
110 "on this HCA, aborting.\n");
111 return -EINVAL;
112 }
113 }
114 if ((port_type[0] == MLX4_PORT_TYPE_ETH) &&
115 (port_type[1] == MLX4_PORT_TYPE_IB)) {
116 mlx4_err(dev, "eth-ib configuration is not supported.\n");
117 return -EINVAL;
118 }
119
120 for (i = 0; i < dev->caps.num_ports; i++) {
121 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
122 mlx4_err(dev, "Requested port type for port %d is not "
123 "supported on this HCA\n", i + 1);
124 return -EINVAL;
125 }
126 }
127 return 0;
128}
129
130static void mlx4_set_port_mask(struct mlx4_dev *dev)
131{
132 int i;
133
134 dev->caps.port_mask = 0;
135 for (i = 1; i <= dev->caps.num_ports; ++i)
136 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_IB)
137 dev->caps.port_mask |= 1 << (i - 1);
138}
3d73c288 139static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 140{
141 int err;
5ae2a7a8 142 int i;
225c7b1f
RD		 143
144 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
145 if (err) {
146 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
147 return err;
148 }
149
150 if (dev_cap->min_page_sz > PAGE_SIZE) {
151 mlx4_err(dev, "HCA minimum page size of %d bigger than "
152 "kernel PAGE_SIZE of %ld, aborting.\n",
153 dev_cap->min_page_sz, PAGE_SIZE);
154 return -ENODEV;
155 }
156 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
157 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
158 "aborting.\n",
159 dev_cap->num_ports, MLX4_MAX_PORTS);
160 return -ENODEV;
161 }
162
163 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
164 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
165 "PCI resource 2 size of 0x%llx, aborting.\n",
166 dev_cap->uar_size,
167 (unsigned long long) pci_resource_len(dev->pdev, 2));
168 return -ENODEV;
169 }
170
171 dev->caps.num_ports = dev_cap->num_ports;
5ae2a7a8
RD		 172 for (i = 1; i <= dev->caps.num_ports; ++i) {
173 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 174 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
5ae2a7a8
RD		 175 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
176 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
177 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 178 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
179 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 180 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
5ae2a7a8
RD		 181 }
182
225c7b1f 183 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 184 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
185 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
186 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
187 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
188 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
189 dev->caps.max_wqes = dev_cap->max_qp_sz;
190 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 191 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
192 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
193 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
194 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
195 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
196 dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM;
197 /*
198 * Subtract 1 from the limit because we need to allocate a
199 * spare CQE so the HCA HW can tell the difference between an
200 * empty CQ and a full CQ.
201 */
202 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
203 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
204 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
121964ec
RD		 205 dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
206 MLX4_MTT_ENTRY_PER_SEG);
225c7b1f
RD		 207 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
208 dev->caps.reserved_uars = dev_cap->reserved_uars;
209 dev->caps.reserved_pds = dev_cap->reserved_pds;
225c7b1f 210 dev->caps.mtt_entry_sz = MLX4_MTT_ENTRY_PER_SEG * dev_cap->mtt_entry_sz;
149983af 211 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 212 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
213 dev->caps.flags = dev_cap->flags;
95d04f07
RD		 214 dev->caps.bmme_flags = dev_cap->bmme_flags;
215 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 216 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 217 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
225c7b1f 218
93fc9e1b
YP		 219 dev->caps.log_num_macs = log_num_mac;
220 dev->caps.log_num_vlans = log_num_vlan;
221 dev->caps.log_num_prios = use_prio ? 3 : 0;
222
223 for (i = 1; i <= dev->caps.num_ports; ++i) {
7ff93f8b
YP		 224 if (dev->caps.supported_type[i] != MLX4_PORT_TYPE_ETH)
225 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
226 else
227 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
228
93fc9e1b
YP		 229 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
230 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
231 mlx4_warn(dev, "Requested number of MACs is too much "
232 "for port %d, reducing to %d.\n",
233 i, 1 << dev->caps.log_num_macs);
234 }
235 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
236 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
237 mlx4_warn(dev, "Requested number of VLANs is too much "
238 "for port %d, reducing to %d.\n",
239 i, 1 << dev->caps.log_num_vlans);
240 }
241 }
242
7ff93f8b
YP		 243 mlx4_set_port_mask(dev);
244
93fc9e1b
YP		 245 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
246 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
247 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
248 (1 << dev->caps.log_num_macs) *
249 (1 << dev->caps.log_num_vlans) *
250 (1 << dev->caps.log_num_prios) *
251 dev->caps.num_ports;
252 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
253
254 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
255 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
256 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
257 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
258
225c7b1f
RD		 259 return 0;
260}
261
7ff93f8b
YP		 262/*
263 * Change the port configuration of the device.
264 * Every user of this function must hold the port mutex.
265 */
266static int mlx4_change_port_types(struct mlx4_dev *dev,
267 enum mlx4_port_type *port_types)
268{
269 int err = 0;
270 int change = 0;
271 int port;
272
273 for (port = 0; port < dev->caps.num_ports; port++) {
274 if (port_types[port] != dev->caps.port_type[port + 1]) {
275 change = 1;
276 dev->caps.port_type[port + 1] = port_types[port];
277 }
278 }
279 if (change) {
280 mlx4_unregister_device(dev);
281 for (port = 1; port <= dev->caps.num_ports; port++) {
282 mlx4_CLOSE_PORT(dev, port);
283 err = mlx4_SET_PORT(dev, port);
284 if (err) {
285 mlx4_err(dev, "Failed to set port %d, "
286 "aborting\n", port);
287 goto out;
288 }
289 }
290 mlx4_set_port_mask(dev);
291 err = mlx4_register_device(dev);
292 }
293
294out:
295 return err;
296}
297
298static ssize_t show_port_type(struct device *dev,
299 struct device_attribute *attr,
300 char *buf)
301{
302 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
303 port_attr);
304 struct mlx4_dev *mdev = info->dev;
305
306 return sprintf(buf, "%s\n",
307 mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB ?
308 "ib" : "eth");
309}
310
311static ssize_t set_port_type(struct device *dev,
312 struct device_attribute *attr,
313 const char *buf, size_t count)
314{
315 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
316 port_attr);
317 struct mlx4_dev *mdev = info->dev;
318 struct mlx4_priv *priv = mlx4_priv(mdev);
319 enum mlx4_port_type types[MLX4_MAX_PORTS];
320 int i;
321 int err = 0;
322
323 if (!strcmp(buf, "ib\n"))
324 info->tmp_type = MLX4_PORT_TYPE_IB;
325 else if (!strcmp(buf, "eth\n"))
326 info->tmp_type = MLX4_PORT_TYPE_ETH;
327 else {
328 mlx4_err(mdev, "%s is not supported port type\n", buf);
329 return -EINVAL;
330 }
331
332 mutex_lock(&priv->port_mutex);
333 for (i = 0; i < mdev->caps.num_ports; i++)
334 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
335 mdev->caps.port_type[i+1];
336
337 err = mlx4_check_port_params(mdev, types);
338 if (err)
339 goto out;
340
341 for (i = 1; i <= mdev->caps.num_ports; i++)
342 priv->port[i].tmp_type = 0;
343
344 err = mlx4_change_port_types(mdev, types);
345
346out:
347 mutex_unlock(&priv->port_mutex);
348 return err ? err : count;
349}
350
e8f9b2ed 351static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 352{
353 struct mlx4_priv *priv = mlx4_priv(dev);
354 int err;
355
356 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 357 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 358 if (!priv->fw.fw_icm) {
359 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
360 return -ENOMEM;
361 }
362
363 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
364 if (err) {
365 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
366 goto err_free;
367 }
368
369 err = mlx4_RUN_FW(dev);
370 if (err) {
371 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
372 goto err_unmap_fa;
373 }
374
375 return 0;
376
377err_unmap_fa:
378 mlx4_UNMAP_FA(dev);
379
380err_free:
5b0bf5e2 381 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 382 return err;
383}
384
e8f9b2ed
RD		 385static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
386 int cmpt_entry_sz)
225c7b1f
RD		 387{
388 struct mlx4_priv *priv = mlx4_priv(dev);
389 int err;
390
391 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
392 cmpt_base +
393 ((u64) (MLX4_CMPT_TYPE_QP *
394 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
395 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 396 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
397 0, 0);
225c7b1f
RD		 398 if (err)
399 goto err;
400
401 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
402 cmpt_base +
403 ((u64) (MLX4_CMPT_TYPE_SRQ *
404 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
405 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 406 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 407 if (err)
408 goto err_qp;
409
410 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
411 cmpt_base +
412 ((u64) (MLX4_CMPT_TYPE_CQ *
413 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
414 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 415 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 416 if (err)
417 goto err_srq;
418
419 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
420 cmpt_base +
421 ((u64) (MLX4_CMPT_TYPE_EQ *
422 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
423 cmpt_entry_sz,
424 roundup_pow_of_two(MLX4_NUM_EQ +
425 dev->caps.reserved_eqs),
5b0bf5e2 426 MLX4_NUM_EQ + dev->caps.reserved_eqs, 0, 0);
225c7b1f
RD		 427 if (err)
428 goto err_cq;
429
430 return 0;
431
432err_cq:
433 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
434
435err_srq:
436 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
437
438err_qp:
439 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
440
441err:
442 return err;
443}
444
3d73c288
RD		 445static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
446 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 447{
448 struct mlx4_priv *priv = mlx4_priv(dev);
449 u64 aux_pages;
450 int err;
451
452 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
453 if (err) {
454 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
455 return err;
456 }
457
458 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
459 (unsigned long long) icm_size >> 10,
460 (unsigned long long) aux_pages << 2);
461
462 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 463 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 464 if (!priv->fw.aux_icm) {
465 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
466 return -ENOMEM;
467 }
468
469 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
470 if (err) {
471 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
472 goto err_free_aux;
473 }
474
475 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
476 if (err) {
477 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
478 goto err_unmap_aux;
479 }
480
481 err = mlx4_map_eq_icm(dev, init_hca->eqc_base);
482 if (err) {
483 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
484 goto err_unmap_cmpt;
485 }
486
d7bb58fb
JM		 487 /*
488 * Reserved MTT entries must be aligned up to a cacheline
489 * boundary, since the FW will write to them, while the driver
490 * writes to all other MTT entries. (The variable
491 * dev->caps.mtt_entry_sz below is really the MTT segment
492 * size, not the raw entry size)
493 */
494 dev->caps.reserved_mtts =
495 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
496 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
497
225c7b1f
RD		 498 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
499 init_hca->mtt_base,
500 dev->caps.mtt_entry_sz,
501 dev->caps.num_mtt_segs,
5b0bf5e2 502 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 503 if (err) {
504 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
505 goto err_unmap_eq;
506 }
507
508 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
509 init_hca->dmpt_base,
510 dev_cap->dmpt_entry_sz,
511 dev->caps.num_mpts,
5b0bf5e2 512 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 513 if (err) {
514 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
515 goto err_unmap_mtt;
516 }
517
518 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
519 init_hca->qpc_base,
520 dev_cap->qpc_entry_sz,
521 dev->caps.num_qps,
93fc9e1b
YP		 522 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
523 0, 0);
225c7b1f
RD		 524 if (err) {
525 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
526 goto err_unmap_dmpt;
527 }
528
529 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
530 init_hca->auxc_base,
531 dev_cap->aux_entry_sz,
532 dev->caps.num_qps,
93fc9e1b
YP		 533 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
534 0, 0);
225c7b1f
RD		 535 if (err) {
536 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
537 goto err_unmap_qp;
538 }
539
540 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
541 init_hca->altc_base,
542 dev_cap->altc_entry_sz,
543 dev->caps.num_qps,
93fc9e1b
YP		 544 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
545 0, 0);
225c7b1f
RD		 546 if (err) {
547 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
548 goto err_unmap_auxc;
549 }
550
551 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
552 init_hca->rdmarc_base,
553 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
554 dev->caps.num_qps,
93fc9e1b
YP		 555 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
556 0, 0);
225c7b1f
RD		 557 if (err) {
558 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
559 goto err_unmap_altc;
560 }
561
562 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
563 init_hca->cqc_base,
564 dev_cap->cqc_entry_sz,
565 dev->caps.num_cqs,
5b0bf5e2 566 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 567 if (err) {
568 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
569 goto err_unmap_rdmarc;
570 }
571
572 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
573 init_hca->srqc_base,
574 dev_cap->srq_entry_sz,
575 dev->caps.num_srqs,
5b0bf5e2 576 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 577 if (err) {
578 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
579 goto err_unmap_cq;
580 }
581
582 /*
583 * It's not strictly required, but for simplicity just map the
584 * whole multicast group table now. The table isn't very big
585 * and it's a lot easier than trying to track ref counts.
586 */
587 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
588 init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
589 dev->caps.num_mgms + dev->caps.num_amgms,
590 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 591 0, 0);
225c7b1f
RD		 592 if (err) {
593 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
594 goto err_unmap_srq;
595 }
596
597 return 0;
598
599err_unmap_srq:
600 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
601
602err_unmap_cq:
603 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
604
605err_unmap_rdmarc:
606 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
607
608err_unmap_altc:
609 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
610
611err_unmap_auxc:
612 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
613
614err_unmap_qp:
615 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
616
617err_unmap_dmpt:
618 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
619
620err_unmap_mtt:
621 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
622
623err_unmap_eq:
624 mlx4_unmap_eq_icm(dev);
625
626err_unmap_cmpt:
627 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
628 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
629 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
630 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
631
632err_unmap_aux:
633 mlx4_UNMAP_ICM_AUX(dev);
634
635err_free_aux:
5b0bf5e2 636 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 637
638 return err;
639}
640
641static void mlx4_free_icms(struct mlx4_dev *dev)
642{
643 struct mlx4_priv *priv = mlx4_priv(dev);
644
645 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
646 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
647 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
648 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
649 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
650 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
651 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
652 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
653 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
654 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
655 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
656 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
657 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
658 mlx4_unmap_eq_icm(dev);
659
660 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 661 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 662}
663
664static void mlx4_close_hca(struct mlx4_dev *dev)
665{
666 mlx4_CLOSE_HCA(dev, 0);
667 mlx4_free_icms(dev);
668 mlx4_UNMAP_FA(dev);
5b0bf5e2 669 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
225c7b1f
RD		 670}
671
3d73c288 672static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 673{
674 struct mlx4_priv *priv = mlx4_priv(dev);
675 struct mlx4_adapter adapter;
676 struct mlx4_dev_cap dev_cap;
2d928651 677 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 678 struct mlx4_profile profile;
679 struct mlx4_init_hca_param init_hca;
680 u64 icm_size;
681 int err;
682
683 err = mlx4_QUERY_FW(dev);
684 if (err) {
685 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
686 return err;
687 }
688
689 err = mlx4_load_fw(dev);
690 if (err) {
691 mlx4_err(dev, "Failed to start FW, aborting.\n");
692 return err;
693 }
694
2d928651
VS		 695 mlx4_cfg.log_pg_sz_m = 1;
696 mlx4_cfg.log_pg_sz = 0;
697 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
698 if (err)
699 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
700
225c7b1f
RD		 701 err = mlx4_dev_cap(dev, &dev_cap);
702 if (err) {
703 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
704 goto err_stop_fw;
705 }
706
707 profile = default_profile;
708
709 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
710 if ((long long) icm_size < 0) {
711 err = icm_size;
712 goto err_stop_fw;
713 }
714
715 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
716
717 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
718 if (err)
719 goto err_stop_fw;
720
721 err = mlx4_INIT_HCA(dev, &init_hca);
722 if (err) {
723 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
724 goto err_free_icm;
725 }
726
727 err = mlx4_QUERY_ADAPTER(dev, &adapter);
728 if (err) {
729 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
730 goto err_close;
731 }
732
733 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 734 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 735
736 return 0;
737
738err_close:
739 mlx4_close_hca(dev);
740
741err_free_icm:
742 mlx4_free_icms(dev);
743
744err_stop_fw:
745 mlx4_UNMAP_FA(dev);
5b0bf5e2 746 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 747
748 return err;
749}
750
3d73c288 751static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 752{
753 struct mlx4_priv *priv = mlx4_priv(dev);
754 int err;
7ff93f8b 755 int port;
9a5aa622 756 __be32 ib_port_default_caps;
225c7b1f 757
225c7b1f
RD		 758 err = mlx4_init_uar_table(dev);
759 if (err) {
760 mlx4_err(dev, "Failed to initialize "
761 "user access region table, aborting.\n");
762 return err;
763 }
764
765 err = mlx4_uar_alloc(dev, &priv->driver_uar);
766 if (err) {
767 mlx4_err(dev, "Failed to allocate driver access region, "
768 "aborting.\n");
769 goto err_uar_table_free;
770 }
771
772 priv->kar = ioremap(priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
773 if (!priv->kar) {
774 mlx4_err(dev, "Couldn't map kernel access region, "
775 "aborting.\n");
776 err = -ENOMEM;
777 goto err_uar_free;
778 }
779
780 err = mlx4_init_pd_table(dev);
781 if (err) {
782 mlx4_err(dev, "Failed to initialize "
783 "protection domain table, aborting.\n");
784 goto err_kar_unmap;
785 }
786
787 err = mlx4_init_mr_table(dev);
788 if (err) {
789 mlx4_err(dev, "Failed to initialize "
790 "memory region table, aborting.\n");
791 goto err_pd_table_free;
792 }
793
225c7b1f
RD		 794 err = mlx4_init_eq_table(dev);
795 if (err) {
796 mlx4_err(dev, "Failed to initialize "
797 "event queue table, aborting.\n");
ee49bd93 798 goto err_mr_table_free;
225c7b1f
RD		 799 }
800
801 err = mlx4_cmd_use_events(dev);
802 if (err) {
803 mlx4_err(dev, "Failed to switch to event-driven "
804 "firmware commands, aborting.\n");
805 goto err_eq_table_free;
806 }
807
808 err = mlx4_NOP(dev);
809 if (err) {
08fb1055
MT		 810 if (dev->flags & MLX4_FLAG_MSI_X) {
811 mlx4_warn(dev, "NOP command failed to generate MSI-X "
812 "interrupt IRQ %d).\n",
813 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
814 mlx4_warn(dev, "Trying again without MSI-X.\n");
815 } else {
816 mlx4_err(dev, "NOP command failed to generate interrupt "
817 "(IRQ %d), aborting.\n",
818 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
225c7b1f 819 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 820 }
225c7b1f
RD		 821
822 goto err_cmd_poll;
823 }
824
825 mlx4_dbg(dev, "NOP command IRQ test passed\n");
826
827 err = mlx4_init_cq_table(dev);
828 if (err) {
829 mlx4_err(dev, "Failed to initialize "
830 "completion queue table, aborting.\n");
831 goto err_cmd_poll;
832 }
833
834 err = mlx4_init_srq_table(dev);
835 if (err) {
836 mlx4_err(dev, "Failed to initialize "
837 "shared receive queue table, aborting.\n");
838 goto err_cq_table_free;
839 }
840
841 err = mlx4_init_qp_table(dev);
842 if (err) {
843 mlx4_err(dev, "Failed to initialize "
844 "queue pair table, aborting.\n");
845 goto err_srq_table_free;
846 }
847
848 err = mlx4_init_mcg_table(dev);
849 if (err) {
850 mlx4_err(dev, "Failed to initialize "
851 "multicast group table, aborting.\n");
852 goto err_qp_table_free;
853 }
854
7ff93f8b 855 for (port = 1; port <= dev->caps.num_ports; port++) {
9a5aa622
JM		 856 ib_port_default_caps = 0;
857 err = mlx4_get_port_ib_caps(dev, port, &ib_port_default_caps);
858 if (err)
859 mlx4_warn(dev, "failed to get port %d default "
860 "ib capabilities (%d). Continuing with "
861 "caps = 0\n", port, err);
862 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
7ff93f8b
YP		 863 err = mlx4_SET_PORT(dev, port);
864 if (err) {
865 mlx4_err(dev, "Failed to set port %d, aborting\n",
866 port);
867 goto err_mcg_table_free;
868 }
869 }
870
225c7b1f
RD		 871 return 0;
872
7ff93f8b
YP		 873err_mcg_table_free:
874 mlx4_cleanup_mcg_table(dev);
875
225c7b1f
RD		 876err_qp_table_free:
877 mlx4_cleanup_qp_table(dev);
878
879err_srq_table_free:
880 mlx4_cleanup_srq_table(dev);
881
882err_cq_table_free:
883 mlx4_cleanup_cq_table(dev);
884
885err_cmd_poll:
886 mlx4_cmd_use_polling(dev);
887
888err_eq_table_free:
889 mlx4_cleanup_eq_table(dev);
890
ee49bd93 891err_mr_table_free:
225c7b1f
RD		 892 mlx4_cleanup_mr_table(dev);
893
894err_pd_table_free:
895 mlx4_cleanup_pd_table(dev);
896
897err_kar_unmap:
898 iounmap(priv->kar);
899
900err_uar_free:
901 mlx4_uar_free(dev, &priv->driver_uar);
902
903err_uar_table_free:
904 mlx4_cleanup_uar_table(dev);
905 return err;
906}
907
e8f9b2ed 908static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 909{
910 struct mlx4_priv *priv = mlx4_priv(dev);
911 struct msix_entry entries[MLX4_NUM_EQ];
912 int err;
913 int i;
914
915 if (msi_x) {
916 for (i = 0; i < MLX4_NUM_EQ; ++i)
917 entries[i].entry = i;
918
919 err = pci_enable_msix(dev->pdev, entries, ARRAY_SIZE(entries));
920 if (err) {
921 if (err > 0)
922 mlx4_info(dev, "Only %d MSI-X vectors available, "
923 "not using MSI-X\n", err);
924 goto no_msi;
925 }
926
927 for (i = 0; i < MLX4_NUM_EQ; ++i)
928 priv->eq_table.eq[i].irq = entries[i].vector;
929
930 dev->flags |= MLX4_FLAG_MSI_X;
931 return;
932 }
933
934no_msi:
935 for (i = 0; i < MLX4_NUM_EQ; ++i)
936 priv->eq_table.eq[i].irq = dev->pdev->irq;
937}
938
7ff93f8b 939static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 940{
941 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 942 int err = 0;
2a2336f8
YP		 943
944 info->dev = dev;
945 info->port = port;
946 mlx4_init_mac_table(dev, &info->mac_table);
947 mlx4_init_vlan_table(dev, &info->vlan_table);
7ff93f8b
YP		 948
949 sprintf(info->dev_name, "mlx4_port%d", port);
950 info->port_attr.attr.name = info->dev_name;
951 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
952 info->port_attr.show = show_port_type;
953 info->port_attr.store = set_port_type;
954
955 err = device_create_file(&dev->pdev->dev, &info->port_attr);
956 if (err) {
957 mlx4_err(dev, "Failed to create file for port %d\n", port);
958 info->port = -1;
959 }
960
961 return err;
962}
963
964static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
965{
966 if (info->port < 0)
967 return;
968
969 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2a2336f8
YP		 970}
971
3d73c288 972static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
225c7b1f 973{
225c7b1f
RD		 974 struct mlx4_priv *priv;
975 struct mlx4_dev *dev;
976 int err;
2a2336f8 977 int port;
225c7b1f 978
225c7b1f
RD		 979 printk(KERN_INFO PFX "Initializing %s\n",
980 pci_name(pdev));
981
982 err = pci_enable_device(pdev);
983 if (err) {
984 dev_err(&pdev->dev, "Cannot enable PCI device, "
985 "aborting.\n");
986 return err;
987 }
988
989 /*
4ff08a76 990 * Check for BARs. We expect 0: 1MB
225c7b1f
RD		 991 */
992 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
993 pci_resource_len(pdev, 0) != 1 << 20) {
994 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
995 err = -ENODEV;
996 goto err_disable_pdev;
997 }
998 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
999 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1000 err = -ENODEV;
1001 goto err_disable_pdev;
1002 }
1003
1004 err = pci_request_region(pdev, 0, DRV_NAME);
1005 if (err) {
1006 dev_err(&pdev->dev, "Cannot request control region, aborting.\n");
1007 goto err_disable_pdev;
1008 }
1009
1010 err = pci_request_region(pdev, 2, DRV_NAME);
1011 if (err) {
1012 dev_err(&pdev->dev, "Cannot request UAR region, aborting.\n");
1013 goto err_release_bar0;
1014 }
1015
1016 pci_set_master(pdev);
1017
1018 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1019 if (err) {
1020 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
1021 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1022 if (err) {
1023 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
1024 goto err_release_bar2;
1025 }
1026 }
1027 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1028 if (err) {
1029 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1030 "consistent PCI DMA mask.\n");
1031 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1032 if (err) {
1033 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1034 "aborting.\n");
1035 goto err_release_bar2;
1036 }
1037 }
1038
1039 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1040 if (!priv) {
1041 dev_err(&pdev->dev, "Device struct alloc failed, "
1042 "aborting.\n");
1043 err = -ENOMEM;
1044 goto err_release_bar2;
1045 }
1046
1047 dev = &priv->dev;
1048 dev->pdev = pdev;
b581401e
RD		 1049 INIT_LIST_HEAD(&priv->ctx_list);
1050 spin_lock_init(&priv->ctx_lock);
225c7b1f 1051
7ff93f8b
YP		 1052 mutex_init(&priv->port_mutex);
1053
6296883c
YP		 1054 INIT_LIST_HEAD(&priv->pgdir_list);
1055 mutex_init(&priv->pgdir_mutex);
1056
225c7b1f
RD		 1057 /*
1058 * Now reset the HCA before we touch the PCI capabilities or
1059 * attempt a firmware command, since a boot ROM may have left
1060 * the HCA in an undefined state.
1061 */
1062 err = mlx4_reset(dev);
1063 if (err) {
1064 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1065 goto err_free_dev;
1066 }
1067
225c7b1f
RD		 1068 if (mlx4_cmd_init(dev)) {
1069 mlx4_err(dev, "Failed to init command interface, aborting.\n");
1070 goto err_free_dev;
1071 }
1072
1073 err = mlx4_init_hca(dev);
1074 if (err)
1075 goto err_cmd;
1076
08fb1055
MT		 1077 mlx4_enable_msi_x(dev);
1078
225c7b1f 1079 err = mlx4_setup_hca(dev);
08fb1055
MT		 1080 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
1081 dev->flags &= ~MLX4_FLAG_MSI_X;
1082 pci_disable_msix(pdev);
1083 err = mlx4_setup_hca(dev);
1084 }
1085
225c7b1f
RD		 1086 if (err)
1087 goto err_close;
1088
7ff93f8b
YP		 1089 for (port = 1; port <= dev->caps.num_ports; port++) {
1090 err = mlx4_init_port_info(dev, port);
1091 if (err)
1092 goto err_port;
1093 }
2a2336f8 1094
225c7b1f
RD		 1095 err = mlx4_register_device(dev);
1096 if (err)
7ff93f8b 1097 goto err_port;
225c7b1f
RD		 1098
1099 pci_set_drvdata(pdev, dev);
1100
1101 return 0;
1102
7ff93f8b
YP		 1103err_port:
1104 for (port = 1; port <= dev->caps.num_ports; port++)
1105 mlx4_cleanup_port_info(&priv->port[port]);
1106
225c7b1f
RD		 1107 mlx4_cleanup_mcg_table(dev);
1108 mlx4_cleanup_qp_table(dev);
1109 mlx4_cleanup_srq_table(dev);
1110 mlx4_cleanup_cq_table(dev);
1111 mlx4_cmd_use_polling(dev);
1112 mlx4_cleanup_eq_table(dev);
225c7b1f
RD		 1113 mlx4_cleanup_mr_table(dev);
1114 mlx4_cleanup_pd_table(dev);
1115 mlx4_cleanup_uar_table(dev);
1116
1117err_close:
08fb1055
MT		 1118 if (dev->flags & MLX4_FLAG_MSI_X)
1119 pci_disable_msix(pdev);
1120
225c7b1f
RD		 1121 mlx4_close_hca(dev);
1122
1123err_cmd:
1124 mlx4_cmd_cleanup(dev);
1125
1126err_free_dev:
225c7b1f
RD		 1127 kfree(priv);
1128
1129err_release_bar2:
1130 pci_release_region(pdev, 2);
1131
1132err_release_bar0:
1133 pci_release_region(pdev, 0);
1134
1135err_disable_pdev:
1136 pci_disable_device(pdev);
1137 pci_set_drvdata(pdev, NULL);
1138 return err;
1139}
1140
3d73c288
RD		 1141static int __devinit mlx4_init_one(struct pci_dev *pdev,
1142 const struct pci_device_id *id)
1143{
1144 static int mlx4_version_printed;
1145
1146 if (!mlx4_version_printed) {
1147 printk(KERN_INFO "%s", mlx4_version);
1148 ++mlx4_version_printed;
1149 }
1150
b027cacd 1151 return __mlx4_init_one(pdev, id);
3d73c288
RD		 1152}
1153
1154static void mlx4_remove_one(struct pci_dev *pdev)
225c7b1f
RD		 1155{
1156 struct mlx4_dev *dev = pci_get_drvdata(pdev);
1157 struct mlx4_priv *priv = mlx4_priv(dev);
1158 int p;
1159
1160 if (dev) {
1161 mlx4_unregister_device(dev);
1162
7ff93f8b
YP		 1163 for (p = 1; p <= dev->caps.num_ports; p++) {
1164 mlx4_cleanup_port_info(&priv->port[p]);
225c7b1f 1165 mlx4_CLOSE_PORT(dev, p);
7ff93f8b 1166 }
225c7b1f
RD		 1167
1168 mlx4_cleanup_mcg_table(dev);
1169 mlx4_cleanup_qp_table(dev);
1170 mlx4_cleanup_srq_table(dev);
1171 mlx4_cleanup_cq_table(dev);
1172 mlx4_cmd_use_polling(dev);
1173 mlx4_cleanup_eq_table(dev);
225c7b1f
RD		 1174 mlx4_cleanup_mr_table(dev);
1175 mlx4_cleanup_pd_table(dev);
1176
1177 iounmap(priv->kar);
1178 mlx4_uar_free(dev, &priv->driver_uar);
1179 mlx4_cleanup_uar_table(dev);
1180 mlx4_close_hca(dev);
1181 mlx4_cmd_cleanup(dev);
1182
1183 if (dev->flags & MLX4_FLAG_MSI_X)
1184 pci_disable_msix(pdev);
1185
1186 kfree(priv);
1187 pci_release_region(pdev, 2);
1188 pci_release_region(pdev, 0);
1189 pci_disable_device(pdev);
1190 pci_set_drvdata(pdev, NULL);
1191 }
1192}
1193
ee49bd93
JM		 1194int mlx4_restart_one(struct pci_dev *pdev)
1195{
1196 mlx4_remove_one(pdev);
3d73c288 1197 return __mlx4_init_one(pdev, NULL);
ee49bd93
JM		 1198}
1199
225c7b1f
RD		 1200static struct pci_device_id mlx4_pci_table[] = {
1201 { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
1202 { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
1203 { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
786f238e
JM		 1204 { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
1205 { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
57893d1c
YP		 1206 { PCI_VDEVICE(MELLANOX, 0x6368) }, /* MT25408 "Hermon" EN 10GigE */
1207 { PCI_VDEVICE(MELLANOX, 0x6750) }, /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
225c7b1f
RD		 1208 { 0, }
1209};
1210
1211MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
1212
1213static struct pci_driver mlx4_driver = {
1214 .name = DRV_NAME,
1215 .id_table = mlx4_pci_table,
1216 .probe = mlx4_init_one,
1217 .remove = __devexit_p(mlx4_remove_one)
1218};
1219
7ff93f8b
YP		 1220static int __init mlx4_verify_params(void)
1221{
1222 if ((log_num_mac < 0) || (log_num_mac > 7)) {
1223 printk(KERN_WARNING "mlx4_core: bad num_mac: %d\n", log_num_mac);
1224 return -1;
1225 }
1226
1227 if ((log_num_vlan < 0) || (log_num_vlan > 7)) {
1228 printk(KERN_WARNING "mlx4_core: bad num_vlan: %d\n", log_num_vlan);
1229 return -1;
1230 }
1231
1232 return 0;
1233}
1234
225c7b1f
RD		 1235static int __init mlx4_init(void)
1236{
1237 int ret;
1238
7ff93f8b
YP		 1239 if (mlx4_verify_params())
1240 return -EINVAL;
1241
ee49bd93
JM		 1242 ret = mlx4_catas_init();
1243 if (ret)
1244 return ret;
1245
225c7b1f
RD		 1246 ret = pci_register_driver(&mlx4_driver);
1247 return ret < 0 ? ret : 0;
1248}
1249
1250static void __exit mlx4_cleanup(void)
1251{
1252 pci_unregister_driver(&mlx4_driver);
ee49bd93 1253 mlx4_catas_cleanup();
225c7b1f
RD		 1254}
1255
1256module_init(mlx4_init);
1257module_exit(mlx4_cleanup);
kernel source for telekom puls (alcatel/mediatek)