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mmc: sdhci-pxav3: add IRQ wake up support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
df673b22 47static unsigned int debug_quirks = 0;
66fd8ad5 48static unsigned int debug_quirks2;
67435274 49
d129bceb
PO		 50static void sdhci_finish_data(struct sdhci_host *);
51
52static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 55static void sdhci_tuning_timer(unsigned long data);
d129bceb 56
66fd8ad5
AH		 57#ifdef CONFIG_PM_RUNTIME
58static int sdhci_runtime_pm_get(struct sdhci_host *host);
59static int sdhci_runtime_pm_put(struct sdhci_host *host);
60#else
61static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
62{
63 return 0;
64}
65static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
66{
67 return 0;
68}
69#endif
70
d129bceb
PO		 71static void sdhci_dumpregs(struct sdhci_host *host)
72{
a3c76eb9 73 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 74 mmc_hostname(host->mmc));
d129bceb 75
a3c76eb9 76 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 77 sdhci_readl(host, SDHCI_DMA_ADDRESS),
78 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 79 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 80 sdhci_readw(host, SDHCI_BLOCK_SIZE),
81 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 82 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 83 sdhci_readl(host, SDHCI_ARGUMENT),
84 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 85 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 86 sdhci_readl(host, SDHCI_PRESENT_STATE),
87 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 88 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 89 sdhci_readb(host, SDHCI_POWER_CONTROL),
90 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 91 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 92 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
93 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 94 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 95 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
96 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 97 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 98 sdhci_readl(host, SDHCI_INT_ENABLE),
99 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 100 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 101 sdhci_readw(host, SDHCI_ACMD12_ERR),
102 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 103 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 104 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 105 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 106 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 107 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 108 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 109 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 110 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 111
be3f4ae0 112 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 113 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 114 readl(host->ioaddr + SDHCI_ADMA_ERROR),
115 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
116
a3c76eb9 117 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 118}
119
120/*****************************************************************************\
121 * *
122 * Low level functions *
123 * *
124\*****************************************************************************/
125
7260cf5e
AV		 126static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
127{
128 u32 ier;
129
130 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
131 ier &= ~clear;
132 ier |= set;
133 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
134 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
135}
136
137static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
138{
139 sdhci_clear_set_irqs(host, 0, irqs);
140}
141
142static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
143{
144 sdhci_clear_set_irqs(host, irqs, 0);
145}
146
147static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
148{
d25928d1 149 u32 present, irqs;
7260cf5e 150
c79396c1 151 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 152 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 153 return;
154
d25928d1
SG		 155 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
156 SDHCI_CARD_PRESENT;
157 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
158
7260cf5e
AV		 159 if (enable)
160 sdhci_unmask_irqs(host, irqs);
161 else
162 sdhci_mask_irqs(host, irqs);
163}
164
165static void sdhci_enable_card_detection(struct sdhci_host *host)
166{
167 sdhci_set_card_detection(host, true);
168}
169
170static void sdhci_disable_card_detection(struct sdhci_host *host)
171{
172 sdhci_set_card_detection(host, false);
173}
174
d129bceb
PO		 175static void sdhci_reset(struct sdhci_host *host, u8 mask)
176{
e16514d8 177 unsigned long timeout;
063a9dbb 178 u32 uninitialized_var(ier);
e16514d8 179
b8c86fc5 180 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 181 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 182 SDHCI_CARD_PRESENT))
183 return;
184 }
185
063a9dbb
AV		 186 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
187 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
188
393c1a34
PR		 189 if (host->ops->platform_reset_enter)
190 host->ops->platform_reset_enter(host, mask);
191
4e4141a5 192 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 193
e16514d8 194 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 195 host->clock = 0;
196
e16514d8
PO		 197 /* Wait max 100 ms */
198 timeout = 100;
199
200 /* hw clears the bit when it's done */
4e4141a5 201 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 202 if (timeout == 0) {
a3c76eb9 203 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 204 mmc_hostname(host->mmc), (int)mask);
205 sdhci_dumpregs(host);
206 return;
207 }
208 timeout--;
209 mdelay(1);
d129bceb 210 }
063a9dbb 211
393c1a34
PR		 212 if (host->ops->platform_reset_exit)
213 host->ops->platform_reset_exit(host, mask);
214
063a9dbb
AV		 215 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
216 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
3abc1e80
SX		 217
218 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
219 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
220 host->ops->enable_dma(host);
221 }
d129bceb
PO		 222}
223
2f4cbb3d
NP		 224static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
225
226static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 227{
2f4cbb3d
NP		 228 if (soft)
229 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
230 else
231 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 232
7260cf5e
AV		 233 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
234 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 235 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
236 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 237 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 238
239 if (soft) {
240 /* force clock reconfiguration */
241 host->clock = 0;
242 sdhci_set_ios(host->mmc, &host->mmc->ios);
243 }
7260cf5e 244}
d129bceb 245
7260cf5e
AV		 246static void sdhci_reinit(struct sdhci_host *host)
247{
2f4cbb3d 248 sdhci_init(host, 0);
b67c6b41
AL		 249 /*
250 * Retuning stuffs are affected by different cards inserted and only
251 * applicable to UHS-I cards. So reset these fields to their initial
252 * value when card is removed.
253 */
973905fe
AL		 254 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
255 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
256
b67c6b41
AL		 257 del_timer_sync(&host->tuning_timer);
258 host->flags &= ~SDHCI_NEEDS_RETUNING;
259 host->mmc->max_blk_count =
260 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
261 }
7260cf5e 262 sdhci_enable_card_detection(host);
d129bceb
PO		 263}
264
265static void sdhci_activate_led(struct sdhci_host *host)
266{
267 u8 ctrl;
268
4e4141a5 269 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 270 ctrl |= SDHCI_CTRL_LED;
4e4141a5 271 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 272}
273
274static void sdhci_deactivate_led(struct sdhci_host *host)
275{
276 u8 ctrl;
277
4e4141a5 278 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 279 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 280 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 281}
282
f9134319 283#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 284static void sdhci_led_control(struct led_classdev *led,
285 enum led_brightness brightness)
286{
287 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
288 unsigned long flags;
289
290 spin_lock_irqsave(&host->lock, flags);
291
66fd8ad5
AH		 292 if (host->runtime_suspended)
293 goto out;
294
2f730fec
PO		 295 if (brightness == LED_OFF)
296 sdhci_deactivate_led(host);
297 else
298 sdhci_activate_led(host);
66fd8ad5 299out:
2f730fec
PO		 300 spin_unlock_irqrestore(&host->lock, flags);
301}
302#endif
303
d129bceb
PO		 304/*****************************************************************************\
305 * *
306 * Core functions *
307 * *
308\*****************************************************************************/
309
a406f5a3 310static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 311{
7659150c
PO		 312 unsigned long flags;
313 size_t blksize, len, chunk;
7244b85b 314 u32 uninitialized_var(scratch);
7659150c 315 u8 *buf;
d129bceb 316
a406f5a3 317 DBG("PIO reading\n");
d129bceb 318
a406f5a3 319 blksize = host->data->blksz;
7659150c 320 chunk = 0;
d129bceb 321
7659150c 322 local_irq_save(flags);
d129bceb 323
a406f5a3 324 while (blksize) {
7659150c
PO		 325 if (!sg_miter_next(&host->sg_miter))
326 BUG();
d129bceb 327
7659150c 328 len = min(host->sg_miter.length, blksize);
d129bceb 329
7659150c
PO		 330 blksize -= len;
331 host->sg_miter.consumed = len;
14d836e7 332
7659150c 333 buf = host->sg_miter.addr;
d129bceb 334
7659150c
PO		 335 while (len) {
336 if (chunk == 0) {
4e4141a5 337 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 338 chunk = 4;
a406f5a3 339 }
7659150c
PO		 340
341 *buf = scratch & 0xFF;
342
343 buf++;
344 scratch >>= 8;
345 chunk--;
346 len--;
d129bceb 347 }
a406f5a3 348 }
7659150c
PO		 349
350 sg_miter_stop(&host->sg_miter);
351
352 local_irq_restore(flags);
a406f5a3 353}
d129bceb 354
a406f5a3
PO		 355static void sdhci_write_block_pio(struct sdhci_host *host)
356{
7659150c
PO		 357 unsigned long flags;
358 size_t blksize, len, chunk;
359 u32 scratch;
360 u8 *buf;
d129bceb 361
a406f5a3
PO		 362 DBG("PIO writing\n");
363
364 blksize = host->data->blksz;
7659150c
PO		 365 chunk = 0;
366 scratch = 0;
d129bceb 367
7659150c 368 local_irq_save(flags);
d129bceb 369
a406f5a3 370 while (blksize) {
7659150c
PO		 371 if (!sg_miter_next(&host->sg_miter))
372 BUG();
a406f5a3 373
7659150c
PO		 374 len = min(host->sg_miter.length, blksize);
375
376 blksize -= len;
377 host->sg_miter.consumed = len;
378
379 buf = host->sg_miter.addr;
d129bceb 380
7659150c
PO		 381 while (len) {
382 scratch |= (u32)*buf << (chunk * 8);
383
384 buf++;
385 chunk++;
386 len--;
387
388 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 389 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 390 chunk = 0;
391 scratch = 0;
d129bceb 392 }
d129bceb
PO		 393 }
394 }
7659150c
PO		 395
396 sg_miter_stop(&host->sg_miter);
397
398 local_irq_restore(flags);
a406f5a3
PO		 399}
400
401static void sdhci_transfer_pio(struct sdhci_host *host)
402{
403 u32 mask;
404
405 BUG_ON(!host->data);
406
7659150c 407 if (host->blocks == 0)
a406f5a3
PO		 408 return;
409
410 if (host->data->flags & MMC_DATA_READ)
411 mask = SDHCI_DATA_AVAILABLE;
412 else
413 mask = SDHCI_SPACE_AVAILABLE;
414
4a3cba32
PO		 415 /*
416 * Some controllers (JMicron JMB38x) mess up the buffer bits
417 * for transfers < 4 bytes. As long as it is just one block,
418 * we can ignore the bits.
419 */
420 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
421 (host->data->blocks == 1))
422 mask = ~0;
423
4e4141a5 424 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 425 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
426 udelay(100);
427
a406f5a3
PO		 428 if (host->data->flags & MMC_DATA_READ)
429 sdhci_read_block_pio(host);
430 else
431 sdhci_write_block_pio(host);
d129bceb 432
7659150c
PO		 433 host->blocks--;
434 if (host->blocks == 0)
a406f5a3 435 break;
a406f5a3 436 }
d129bceb 437
a406f5a3 438 DBG("PIO transfer complete.\n");
d129bceb
PO		 439}
440
2134a922
PO		 441static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
442{
443 local_irq_save(*flags);
482fce99 444 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 445}
446
447static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
448{
482fce99 449 kunmap_atomic(buffer);
2134a922
PO		 450 local_irq_restore(*flags);
451}
452
118cd17d
BD		 453static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
454{
9e506f35
BD		 455 __le32 *dataddr = (__le32 __force *)(desc + 4);
456 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 457
9e506f35
BD		 458 /* SDHCI specification says ADMA descriptors should be 4 byte
459 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 460
9e506f35
BD		 461 cmdlen[0] = cpu_to_le16(cmd);
462 cmdlen[1] = cpu_to_le16(len);
463
464 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 465}
466
8f1934ce 467static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 468 struct mmc_data *data)
469{
470 int direction;
471
472 u8 *desc;
473 u8 *align;
474 dma_addr_t addr;
475 dma_addr_t align_addr;
476 int len, offset;
477
478 struct scatterlist *sg;
479 int i;
480 char *buffer;
481 unsigned long flags;
482
483 /*
484 * The spec does not specify endianness of descriptor table.
485 * We currently guess that it is LE.
486 */
487
488 if (data->flags & MMC_DATA_READ)
489 direction = DMA_FROM_DEVICE;
490 else
491 direction = DMA_TO_DEVICE;
492
493 /*
494 * The ADMA descriptor table is mapped further down as we
495 * need to fill it with data first.
496 */
497
498 host->align_addr = dma_map_single(mmc_dev(host->mmc),
499 host->align_buffer, 128 * 4, direction);
8d8bb39b 500 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 501 goto fail;
2134a922
PO		 502 BUG_ON(host->align_addr & 0x3);
503
504 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
505 data->sg, data->sg_len, direction);
8f1934ce
PO		 506 if (host->sg_count == 0)
507 goto unmap_align;
2134a922
PO		 508
509 desc = host->adma_desc;
510 align = host->align_buffer;
511
512 align_addr = host->align_addr;
513
514 for_each_sg(data->sg, sg, host->sg_count, i) {
515 addr = sg_dma_address(sg);
516 len = sg_dma_len(sg);
517
518 /*
519 * The SDHCI specification states that ADMA
520 * addresses must be 32-bit aligned. If they
521 * aren't, then we use a bounce buffer for
522 * the (up to three) bytes that screw up the
523 * alignment.
524 */
525 offset = (4 - (addr & 0x3)) & 0x3;
526 if (offset) {
527 if (data->flags & MMC_DATA_WRITE) {
528 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 529 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 530 memcpy(align, buffer, offset);
531 sdhci_kunmap_atomic(buffer, &flags);
532 }
533
118cd17d
BD		 534 /* tran, valid */
535 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 536
537 BUG_ON(offset > 65536);
538
2134a922
PO		 539 align += 4;
540 align_addr += 4;
541
542 desc += 8;
543
544 addr += offset;
545 len -= offset;
546 }
547
2134a922
PO		 548 BUG_ON(len > 65536);
549
118cd17d
BD		 550 /* tran, valid */
551 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 552 desc += 8;
553
554 /*
555 * If this triggers then we have a calculation bug
556 * somewhere. :/
557 */
558 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
559 }
560
70764a90
TA		 561 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
562 /*
563 * Mark the last descriptor as the terminating descriptor
564 */
565 if (desc != host->adma_desc) {
566 desc -= 8;
567 desc[0] |= 0x2; /* end */
568 }
569 } else {
570 /*
571 * Add a terminating entry.
572 */
2134a922 573
70764a90
TA		 574 /* nop, end, valid */
575 sdhci_set_adma_desc(desc, 0, 0, 0x3);
576 }
2134a922
PO		 577
578 /*
579 * Resync align buffer as we might have changed it.
580 */
581 if (data->flags & MMC_DATA_WRITE) {
582 dma_sync_single_for_device(mmc_dev(host->mmc),
583 host->align_addr, 128 * 4, direction);
584 }
585
586 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
587 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 588 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 589 goto unmap_entries;
2134a922 590 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 591
592 return 0;
593
594unmap_entries:
595 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
596 data->sg_len, direction);
597unmap_align:
598 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
599 128 * 4, direction);
600fail:
601 return -EINVAL;
2134a922
PO		 602}
603
604static void sdhci_adma_table_post(struct sdhci_host *host,
605 struct mmc_data *data)
606{
607 int direction;
608
609 struct scatterlist *sg;
610 int i, size;
611 u8 *align;
612 char *buffer;
613 unsigned long flags;
614
615 if (data->flags & MMC_DATA_READ)
616 direction = DMA_FROM_DEVICE;
617 else
618 direction = DMA_TO_DEVICE;
619
620 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
621 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
622
623 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
624 128 * 4, direction);
625
626 if (data->flags & MMC_DATA_READ) {
627 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
628 data->sg_len, direction);
629
630 align = host->align_buffer;
631
632 for_each_sg(data->sg, sg, host->sg_count, i) {
633 if (sg_dma_address(sg) & 0x3) {
634 size = 4 - (sg_dma_address(sg) & 0x3);
635
636 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 637 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 638 memcpy(buffer, align, size);
639 sdhci_kunmap_atomic(buffer, &flags);
640
641 align += 4;
642 }
643 }
644 }
645
646 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
647 data->sg_len, direction);
648}
649
a3c7778f 650static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 651{
1c8cde92 652 u8 count;
a3c7778f 653 struct mmc_data *data = cmd->data;
1c8cde92 654 unsigned target_timeout, current_timeout;
d129bceb 655
ee53ab5d
PO		 656 /*
657 * If the host controller provides us with an incorrect timeout
658 * value, just skip the check and use 0xE. The hardware may take
659 * longer to time out, but that's much better than having a too-short
660 * timeout value.
661 */
11a2f1b7 662 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 663 return 0xE;
e538fbe8 664
a3c7778f
AW		 665 /* Unspecified timeout, assume max */
666 if (!data && !cmd->cmd_timeout_ms)
667 return 0xE;
d129bceb 668
a3c7778f
AW		 669 /* timeout in us */
670 if (!data)
671 target_timeout = cmd->cmd_timeout_ms * 1000;
78a2ca27
AS		 672 else {
673 target_timeout = data->timeout_ns / 1000;
674 if (host->clock)
675 target_timeout += data->timeout_clks / host->clock;
676 }
81b39802 677
1c8cde92
PO		 678 /*
679 * Figure out needed cycles.
680 * We do this in steps in order to fit inside a 32 bit int.
681 * The first step is the minimum timeout, which will have a
682 * minimum resolution of 6 bits:
683 * (1) 2^13*1000 > 2^22,
684 * (2) host->timeout_clk < 2^16
685 * =>
686 * (1) / (2) > 2^6
687 */
688 count = 0;
689 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
690 while (current_timeout < target_timeout) {
691 count++;
692 current_timeout <<= 1;
693 if (count >= 0xF)
694 break;
695 }
696
697 if (count >= 0xF) {
09eeff52
CB		 698 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
699 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 700 count = 0xE;
701 }
702
ee53ab5d
PO		 703 return count;
704}
705
6aa943ab
AV		 706static void sdhci_set_transfer_irqs(struct sdhci_host *host)
707{
708 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
709 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
710
711 if (host->flags & SDHCI_REQ_USE_DMA)
712 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
713 else
714 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
715}
716
a3c7778f 717static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 718{
719 u8 count;
2134a922 720 u8 ctrl;
a3c7778f 721 struct mmc_data *data = cmd->data;
8f1934ce 722 int ret;
ee53ab5d
PO		 723
724 WARN_ON(host->data);
725
a3c7778f
AW		 726 if (data || (cmd->flags & MMC_RSP_BUSY)) {
727 count = sdhci_calc_timeout(host, cmd);
728 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
729 }
730
731 if (!data)
ee53ab5d
PO		 732 return;
733
734 /* Sanity checks */
735 BUG_ON(data->blksz * data->blocks > 524288);
736 BUG_ON(data->blksz > host->mmc->max_blk_size);
737 BUG_ON(data->blocks > 65535);
738
739 host->data = data;
740 host->data_early = 0;
f6a03cbf 741 host->data->bytes_xfered = 0;
ee53ab5d 742
a13abc7b 743 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 744 host->flags |= SDHCI_REQ_USE_DMA;
745
2134a922
PO		 746 /*
747 * FIXME: This doesn't account for merging when mapping the
748 * scatterlist.
749 */
750 if (host->flags & SDHCI_REQ_USE_DMA) {
751 int broken, i;
752 struct scatterlist *sg;
753
754 broken = 0;
755 if (host->flags & SDHCI_USE_ADMA) {
756 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
757 broken = 1;
758 } else {
759 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
760 broken = 1;
761 }
762
763 if (unlikely(broken)) {
764 for_each_sg(data->sg, sg, data->sg_len, i) {
765 if (sg->length & 0x3) {
766 DBG("Reverting to PIO because of "
767 "transfer size (%d)\n",
768 sg->length);
769 host->flags &= ~SDHCI_REQ_USE_DMA;
770 break;
771 }
772 }
773 }
c9fddbc4
PO		 774 }
775
776 /*
777 * The assumption here being that alignment is the same after
778 * translation to device address space.
779 */
2134a922
PO		 780 if (host->flags & SDHCI_REQ_USE_DMA) {
781 int broken, i;
782 struct scatterlist *sg;
783
784 broken = 0;
785 if (host->flags & SDHCI_USE_ADMA) {
786 /*
787 * As we use 3 byte chunks to work around
788 * alignment problems, we need to check this
789 * quirk.
790 */
791 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
792 broken = 1;
793 } else {
794 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
795 broken = 1;
796 }
797
798 if (unlikely(broken)) {
799 for_each_sg(data->sg, sg, data->sg_len, i) {
800 if (sg->offset & 0x3) {
801 DBG("Reverting to PIO because of "
802 "bad alignment\n");
803 host->flags &= ~SDHCI_REQ_USE_DMA;
804 break;
805 }
806 }
807 }
808 }
809
8f1934ce
PO		 810 if (host->flags & SDHCI_REQ_USE_DMA) {
811 if (host->flags & SDHCI_USE_ADMA) {
812 ret = sdhci_adma_table_pre(host, data);
813 if (ret) {
814 /*
815 * This only happens when someone fed
816 * us an invalid request.
817 */
818 WARN_ON(1);
ebd6d357 819 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 820 } else {
4e4141a5
AV		 821 sdhci_writel(host, host->adma_addr,
822 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 823 }
824 } else {
c8b3e02e 825 int sg_cnt;
8f1934ce 826
c8b3e02e 827 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 828 data->sg, data->sg_len,
829 (data->flags & MMC_DATA_READ) ?
830 DMA_FROM_DEVICE :
831 DMA_TO_DEVICE);
c8b3e02e 832 if (sg_cnt == 0) {
8f1934ce
PO		 833 /*
834 * This only happens when someone fed
835 * us an invalid request.
836 */
837 WARN_ON(1);
ebd6d357 838 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 839 } else {
719a61b4 840 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 841 sdhci_writel(host, sg_dma_address(data->sg),
842 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 843 }
844 }
845 }
846
2134a922
PO		 847 /*
848 * Always adjust the DMA selection as some controllers
849 * (e.g. JMicron) can't do PIO properly when the selection
850 * is ADMA.
851 */
852 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 853 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 854 ctrl &= ~SDHCI_CTRL_DMA_MASK;
855 if ((host->flags & SDHCI_REQ_USE_DMA) &&
856 (host->flags & SDHCI_USE_ADMA))
857 ctrl |= SDHCI_CTRL_ADMA32;
858 else
859 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 860 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 861 }
862
8f1934ce 863 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 864 int flags;
865
866 flags = SG_MITER_ATOMIC;
867 if (host->data->flags & MMC_DATA_READ)
868 flags |= SG_MITER_TO_SG;
869 else
870 flags |= SG_MITER_FROM_SG;
871 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 872 host->blocks = data->blocks;
d129bceb 873 }
c7fa9963 874
6aa943ab
AV		 875 sdhci_set_transfer_irqs(host);
876
f6a03cbf
MV		 877 /* Set the DMA boundary value and block size */
878 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
879 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 880 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 881}
882
883static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 884 struct mmc_command *cmd)
c7fa9963
PO		 885{
886 u16 mode;
e89d456f 887 struct mmc_data *data = cmd->data;
c7fa9963 888
c7fa9963
PO		 889 if (data == NULL)
890 return;
891
e538fbe8
PO		 892 WARN_ON(!host->data);
893
c7fa9963 894 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 895 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
896 mode |= SDHCI_TRNS_MULTI;
897 /*
898 * If we are sending CMD23, CMD12 never gets sent
899 * on successful completion (so no Auto-CMD12).
900 */
901 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
902 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 903 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
904 mode |= SDHCI_TRNS_AUTO_CMD23;
905 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
906 }
c4512f79 907 }
8edf6371 908
c7fa9963
PO		 909 if (data->flags & MMC_DATA_READ)
910 mode |= SDHCI_TRNS_READ;
c9fddbc4 911 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 912 mode |= SDHCI_TRNS_DMA;
913
4e4141a5 914 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 915}
916
917static void sdhci_finish_data(struct sdhci_host *host)
918{
919 struct mmc_data *data;
d129bceb
PO		 920
921 BUG_ON(!host->data);
922
923 data = host->data;
924 host->data = NULL;
925
c9fddbc4 926 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 927 if (host->flags & SDHCI_USE_ADMA)
928 sdhci_adma_table_post(host, data);
929 else {
930 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
931 data->sg_len, (data->flags & MMC_DATA_READ) ?
932 DMA_FROM_DEVICE : DMA_TO_DEVICE);
933 }
d129bceb
PO		 934 }
935
936 /*
c9b74c5b
PO		 937 * The specification states that the block count register must
938 * be updated, but it does not specify at what point in the
939 * data flow. That makes the register entirely useless to read
940 * back so we have to assume that nothing made it to the card
941 * in the event of an error.
d129bceb 942 */
c9b74c5b
PO		 943 if (data->error)
944 data->bytes_xfered = 0;
d129bceb 945 else
c9b74c5b 946 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 947
e89d456f
AW		 948 /*
949 * Need to send CMD12 if -
950 * a) open-ended multiblock transfer (no CMD23)
951 * b) error in multiblock transfer
952 */
953 if (data->stop &&
954 (data->error ||
955 !host->mrq->sbc)) {
956
d129bceb
PO		 957 /*
958 * The controller needs a reset of internal state machines
959 * upon error conditions.
960 */
17b0429d 961 if (data->error) {
d129bceb
PO		 962 sdhci_reset(host, SDHCI_RESET_CMD);
963 sdhci_reset(host, SDHCI_RESET_DATA);
964 }
965
966 sdhci_send_command(host, data->stop);
967 } else
968 tasklet_schedule(&host->finish_tasklet);
969}
970
971static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
972{
973 int flags;
fd2208d7 974 u32 mask;
7cb2c76f 975 unsigned long timeout;
d129bceb
PO		 976
977 WARN_ON(host->cmd);
978
d129bceb 979 /* Wait max 10 ms */
7cb2c76f 980 timeout = 10;
fd2208d7
PO		 981
982 mask = SDHCI_CMD_INHIBIT;
983 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
984 mask |= SDHCI_DATA_INHIBIT;
985
986 /* We shouldn't wait for data inihibit for stop commands, even
987 though they might use busy signaling */
988 if (host->mrq->data && (cmd == host->mrq->data->stop))
989 mask &= ~SDHCI_DATA_INHIBIT;
990
4e4141a5 991 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 992 if (timeout == 0) {
a3c76eb9 993 pr_err("%s: Controller never released "
acf1da45 994 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 995 sdhci_dumpregs(host);
17b0429d 996 cmd->error = -EIO;
d129bceb
PO		 997 tasklet_schedule(&host->finish_tasklet);
998 return;
999 }
7cb2c76f
PO		 1000 timeout--;
1001 mdelay(1);
1002 }
d129bceb
PO		 1003
1004 mod_timer(&host->timer, jiffies + 10 * HZ);
1005
1006 host->cmd = cmd;
1007
a3c7778f 1008 sdhci_prepare_data(host, cmd);
d129bceb 1009
4e4141a5 1010 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1011
e89d456f 1012 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1013
d129bceb 1014 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1015 pr_err("%s: Unsupported response type!\n",
d129bceb 1016 mmc_hostname(host->mmc));
17b0429d 1017 cmd->error = -EINVAL;
d129bceb
PO		 1018 tasklet_schedule(&host->finish_tasklet);
1019 return;
1020 }
1021
1022 if (!(cmd->flags & MMC_RSP_PRESENT))
1023 flags = SDHCI_CMD_RESP_NONE;
1024 else if (cmd->flags & MMC_RSP_136)
1025 flags = SDHCI_CMD_RESP_LONG;
1026 else if (cmd->flags & MMC_RSP_BUSY)
1027 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1028 else
1029 flags = SDHCI_CMD_RESP_SHORT;
1030
1031 if (cmd->flags & MMC_RSP_CRC)
1032 flags |= SDHCI_CMD_CRC;
1033 if (cmd->flags & MMC_RSP_OPCODE)
1034 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1035
1036 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1037 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1038 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1039 flags |= SDHCI_CMD_DATA;
1040
4e4141a5 1041 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 1042}
1043
1044static void sdhci_finish_command(struct sdhci_host *host)
1045{
1046 int i;
1047
1048 BUG_ON(host->cmd == NULL);
1049
1050 if (host->cmd->flags & MMC_RSP_PRESENT) {
1051 if (host->cmd->flags & MMC_RSP_136) {
1052 /* CRC is stripped so we need to do some shifting. */
1053 for (i = 0;i < 4;i++) {
4e4141a5 1054 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1055 SDHCI_RESPONSE + (3-i)*4) << 8;
1056 if (i != 3)
1057 host->cmd->resp[i] |=
4e4141a5 1058 sdhci_readb(host,
d129bceb
PO		 1059 SDHCI_RESPONSE + (3-i)*4-1);
1060 }
1061 } else {
4e4141a5 1062 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1063 }
1064 }
1065
17b0429d 1066 host->cmd->error = 0;
d129bceb 1067
e89d456f
AW		 1068 /* Finished CMD23, now send actual command. */
1069 if (host->cmd == host->mrq->sbc) {
1070 host->cmd = NULL;
1071 sdhci_send_command(host, host->mrq->cmd);
1072 } else {
e538fbe8 1073
e89d456f
AW		 1074 /* Processed actual command. */
1075 if (host->data && host->data_early)
1076 sdhci_finish_data(host);
d129bceb 1077
e89d456f
AW		 1078 if (!host->cmd->data)
1079 tasklet_schedule(&host->finish_tasklet);
1080
1081 host->cmd = NULL;
1082 }
d129bceb
PO		 1083}
1084
1085static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1086{
c3ed3877 1087 int div = 0; /* Initialized for compiler warning */
df16219f 1088 int real_div = div, clk_mul = 1;
c3ed3877 1089 u16 clk = 0;
7cb2c76f 1090 unsigned long timeout;
d129bceb 1091
30832ab5 1092 if (clock && clock == host->clock)
d129bceb
PO		 1093 return;
1094
df16219f
GC		 1095 host->mmc->actual_clock = 0;
1096
8114634c
AV		 1097 if (host->ops->set_clock) {
1098 host->ops->set_clock(host, clock);
1099 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1100 return;
1101 }
1102
4e4141a5 1103 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1104
1105 if (clock == 0)
1106 goto out;
1107
85105c53 1108 if (host->version >= SDHCI_SPEC_300) {
c3ed3877
AN		 1109 /*
1110 * Check if the Host Controller supports Programmable Clock
1111 * Mode.
1112 */
1113 if (host->clk_mul) {
1114 u16 ctrl;
1115
1116 /*
1117 * We need to figure out whether the Host Driver needs
1118 * to select Programmable Clock Mode, or the value can
1119 * be set automatically by the Host Controller based on
1120 * the Preset Value registers.
1121 */
1122 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1123 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1124 for (div = 1; div <= 1024; div++) {
1125 if (((host->max_clk * host->clk_mul) /
1126 div) <= clock)
1127 break;
1128 }
1129 /*
1130 * Set Programmable Clock Mode in the Clock
1131 * Control register.
1132 */
1133 clk = SDHCI_PROG_CLOCK_MODE;
df16219f
GC		 1134 real_div = div;
1135 clk_mul = host->clk_mul;
c3ed3877
AN		 1136 div--;
1137 }
1138 } else {
1139 /* Version 3.00 divisors must be a multiple of 2. */
1140 if (host->max_clk <= clock)
1141 div = 1;
1142 else {
1143 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1144 div += 2) {
1145 if ((host->max_clk / div) <= clock)
1146 break;
1147 }
85105c53 1148 }
df16219f 1149 real_div = div;
c3ed3877 1150 div >>= 1;
85105c53
ZG		 1151 }
1152 } else {
1153 /* Version 2.00 divisors must be a power of 2. */
0397526d 1154 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1155 if ((host->max_clk / div) <= clock)
1156 break;
1157 }
df16219f 1158 real_div = div;
c3ed3877 1159 div >>= 1;
d129bceb 1160 }
d129bceb 1161
df16219f
GC		 1162 if (real_div)
1163 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1164
c3ed3877 1165 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1166 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1167 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1168 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1169 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1170
27f6cb16
CB		 1171 /* Wait max 20 ms */
1172 timeout = 20;
4e4141a5 1173 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1174 & SDHCI_CLOCK_INT_STABLE)) {
1175 if (timeout == 0) {
a3c76eb9 1176 pr_err("%s: Internal clock never "
acf1da45 1177 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1178 sdhci_dumpregs(host);
1179 return;
1180 }
7cb2c76f
PO		 1181 timeout--;
1182 mdelay(1);
1183 }
d129bceb
PO		 1184
1185 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1186 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1187
1188out:
1189 host->clock = clock;
1190}
1191
ceb6143b 1192static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1193{
8364248a 1194 u8 pwr = 0;
146ad66e 1195
8364248a 1196 if (power != (unsigned short)-1) {
ae628903
PO		 1197 switch (1 << power) {
1198 case MMC_VDD_165_195:
1199 pwr = SDHCI_POWER_180;
1200 break;
1201 case MMC_VDD_29_30:
1202 case MMC_VDD_30_31:
1203 pwr = SDHCI_POWER_300;
1204 break;
1205 case MMC_VDD_32_33:
1206 case MMC_VDD_33_34:
1207 pwr = SDHCI_POWER_330;
1208 break;
1209 default:
1210 BUG();
1211 }
1212 }
1213
1214 if (host->pwr == pwr)
ceb6143b 1215 return -1;
146ad66e 1216
ae628903
PO		 1217 host->pwr = pwr;
1218
1219 if (pwr == 0) {
4e4141a5 1220 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ceb6143b 1221 return 0;
9e9dc5f2
DS		 1222 }
1223
1224 /*
1225 * Spec says that we should clear the power reg before setting
1226 * a new value. Some controllers don't seem to like this though.
1227 */
b8c86fc5 1228 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1229 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1230
e08c1694 1231 /*
c71f6512 1232 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1233 * and set turn on power at the same time, so set the voltage first.
1234 */
11a2f1b7 1235 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1236 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1237
ae628903 1238 pwr |= SDHCI_POWER_ON;
146ad66e 1239
ae628903 1240 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1241
1242 /*
1243 * Some controllers need an extra 10ms delay of 10ms before they
1244 * can apply clock after applying power
1245 */
11a2f1b7 1246 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1247 mdelay(10);
ceb6143b
AH		 1248
1249 return power;
146ad66e
PO		 1250}
1251
d129bceb
PO		 1252/*****************************************************************************\
1253 * *
1254 * MMC callbacks *
1255 * *
1256\*****************************************************************************/
1257
1258static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1259{
1260 struct sdhci_host *host;
505a8680 1261 int present;
d129bceb 1262 unsigned long flags;
473b095a 1263 u32 tuning_opcode;
d129bceb
PO		 1264
1265 host = mmc_priv(mmc);
1266
66fd8ad5
AH		 1267 sdhci_runtime_pm_get(host);
1268
d129bceb
PO		 1269 spin_lock_irqsave(&host->lock, flags);
1270
1271 WARN_ON(host->mrq != NULL);
1272
f9134319 1273#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1274 sdhci_activate_led(host);
2f730fec 1275#endif
e89d456f
AW		 1276
1277 /*
1278 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1279 * requests if Auto-CMD12 is enabled.
1280 */
1281 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1282 if (mrq->stop) {
1283 mrq->data->stop = NULL;
1284 mrq->stop = NULL;
1285 }
1286 }
d129bceb
PO		 1287
1288 host->mrq = mrq;
1289
505a8680
SG		 1290 /*
1291 * Firstly check card presence from cd-gpio. The return could
1292 * be one of the following possibilities:
1293 * negative: cd-gpio is not available
1294 * zero: cd-gpio is used, and card is removed
1295 * one: cd-gpio is used, and card is present
1296 */
1297 present = mmc_gpio_get_cd(host->mmc);
1298 if (present < 0) {
1299 /* If polling, assume that the card is always present. */
1300 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1301 present = 1;
1302 else
1303 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1304 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1305 }
1306
68d1fb7e 1307 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1308 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1309 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1310 } else {
1311 u32 present_state;
1312
1313 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1314 /*
1315 * Check if the re-tuning timer has already expired and there
1316 * is no on-going data transfer. If so, we need to execute
1317 * tuning procedure before sending command.
1318 */
1319 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1320 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
14efd957
CB		 1321 if (mmc->card) {
1322 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1323 tuning_opcode =
1324 mmc->card->type == MMC_TYPE_MMC ?
1325 MMC_SEND_TUNING_BLOCK_HS200 :
1326 MMC_SEND_TUNING_BLOCK;
1327 spin_unlock_irqrestore(&host->lock, flags);
1328 sdhci_execute_tuning(mmc, tuning_opcode);
1329 spin_lock_irqsave(&host->lock, flags);
1330
1331 /* Restore original mmc_request structure */
1332 host->mrq = mrq;
1333 }
cf2b5eea
AN		 1334 }
1335
8edf6371 1336 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1337 sdhci_send_command(host, mrq->sbc);
1338 else
1339 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1340 }
d129bceb 1341
5f25a66f 1342 mmiowb();
d129bceb
PO		 1343 spin_unlock_irqrestore(&host->lock, flags);
1344}
1345
66fd8ad5 1346static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1347{
d129bceb 1348 unsigned long flags;
ceb6143b 1349 int vdd_bit = -1;
d129bceb
PO		 1350 u8 ctrl;
1351
d129bceb
PO		 1352 spin_lock_irqsave(&host->lock, flags);
1353
ceb6143b
AH		 1354 if (host->flags & SDHCI_DEVICE_DEAD) {
1355 spin_unlock_irqrestore(&host->lock, flags);
1356 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1357 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1358 return;
1359 }
1e72859e 1360
d129bceb
PO		 1361 /*
1362 * Reset the chip on each power off.
1363 * Should clear out any weird states.
1364 */
1365 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1366 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1367 sdhci_reinit(host);
d129bceb
PO		 1368 }
1369
1370 sdhci_set_clock(host, ios->clock);
1371
1372 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1373 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1374 else
ceb6143b
AH		 1375 vdd_bit = sdhci_set_power(host, ios->vdd);
1376
1377 if (host->vmmc && vdd_bit != -1) {
1378 spin_unlock_irqrestore(&host->lock, flags);
1379 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1380 spin_lock_irqsave(&host->lock, flags);
1381 }
d129bceb 1382
643a81ff
PR		 1383 if (host->ops->platform_send_init_74_clocks)
1384 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1385
15ec4461
PR		 1386 /*
1387 * If your platform has 8-bit width support but is not a v3 controller,
1388 * or if it requires special setup code, you should implement that in
1389 * platform_8bit_width().
1390 */
1391 if (host->ops->platform_8bit_width)
1392 host->ops->platform_8bit_width(host, ios->bus_width);
1393 else {
1394 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1395 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1396 ctrl &= ~SDHCI_CTRL_4BITBUS;
1397 if (host->version >= SDHCI_SPEC_300)
1398 ctrl |= SDHCI_CTRL_8BITBUS;
1399 } else {
1400 if (host->version >= SDHCI_SPEC_300)
1401 ctrl &= ~SDHCI_CTRL_8BITBUS;
1402 if (ios->bus_width == MMC_BUS_WIDTH_4)
1403 ctrl |= SDHCI_CTRL_4BITBUS;
1404 else
1405 ctrl &= ~SDHCI_CTRL_4BITBUS;
1406 }
1407 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1408 }
ae6d6c92 1409
15ec4461 1410 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1411
3ab9c8da
PR		 1412 if ((ios->timing == MMC_TIMING_SD_HS ||
1413 ios->timing == MMC_TIMING_MMC_HS)
1414 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1415 ctrl |= SDHCI_CTRL_HISPD;
1416 else
1417 ctrl &= ~SDHCI_CTRL_HISPD;
1418
d6d50a15 1419 if (host->version >= SDHCI_SPEC_300) {
49c468fc
AN		 1420 u16 clk, ctrl_2;
1421 unsigned int clock;
1422
1423 /* In case of UHS-I modes, set High Speed Enable */
069c9f14
G		 1424 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1425 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1426 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1427 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1428 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1429 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1430
1431 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1432 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1433 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1434 /*
1435 * We only need to set Driver Strength if the
1436 * preset value enable is not set.
1437 */
1438 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1439 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1440 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1441 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1442 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1443
1444 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1445 } else {
1446 /*
1447 * According to SDHC Spec v3.00, if the Preset Value
1448 * Enable in the Host Control 2 register is set, we
1449 * need to reset SD Clock Enable before changing High
1450 * Speed Enable to avoid generating clock gliches.
1451 */
758535c4
AN		 1452
1453 /* Reset SD Clock Enable */
1454 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1455 clk &= ~SDHCI_CLOCK_CARD_EN;
1456 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1457
1458 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1459
1460 /* Re-enable SD Clock */
1461 clock = host->clock;
1462 host->clock = 0;
1463 sdhci_set_clock(host, clock);
d6d50a15 1464 }
49c468fc 1465
49c468fc
AN		 1466
1467 /* Reset SD Clock Enable */
1468 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1469 clk &= ~SDHCI_CLOCK_CARD_EN;
1470 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1471
6322cdd0
PR		 1472 if (host->ops->set_uhs_signaling)
1473 host->ops->set_uhs_signaling(host, ios->timing);
1474 else {
1475 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1476 /* Select Bus Speed Mode for host */
1477 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
069c9f14
G		 1478 if (ios->timing == MMC_TIMING_MMC_HS200)
1479 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1480 else if (ios->timing == MMC_TIMING_UHS_SDR12)
6322cdd0
PR		 1481 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1482 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1483 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1484 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1485 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1486 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1487 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1488 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1489 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1490 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1491 }
49c468fc
AN		 1492
1493 /* Re-enable SD Clock */
1494 clock = host->clock;
1495 host->clock = 0;
1496 sdhci_set_clock(host, clock);
758535c4
AN		 1497 } else
1498 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1499
b8352260
LD		 1500 /*
1501 * Some (ENE) controllers go apeshit on some ios operation,
1502 * signalling timeout and CRC errors even on CMD0. Resetting
1503 * it on each ios seems to solve the problem.
1504 */
b8c86fc5 1505 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1506 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1507
5f25a66f 1508 mmiowb();
d129bceb
PO		 1509 spin_unlock_irqrestore(&host->lock, flags);
1510}
1511
66fd8ad5
AH		 1512static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1513{
1514 struct sdhci_host *host = mmc_priv(mmc);
1515
1516 sdhci_runtime_pm_get(host);
1517 sdhci_do_set_ios(host, ios);
1518 sdhci_runtime_pm_put(host);
1519}
1520
1521static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1522{
d129bceb 1523 unsigned long flags;
2dfb579c 1524 int is_readonly;
d129bceb 1525
d129bceb
PO		 1526 spin_lock_irqsave(&host->lock, flags);
1527
1e72859e 1528 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1529 is_readonly = 0;
1530 else if (host->ops->get_ro)
1531 is_readonly = host->ops->get_ro(host);
1e72859e 1532 else
2dfb579c
WS		 1533 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1534 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1535
1536 spin_unlock_irqrestore(&host->lock, flags);
1537
2dfb579c
WS		 1538 /* This quirk needs to be replaced by a callback-function later */
1539 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1540 !is_readonly : is_readonly;
d129bceb
PO		 1541}
1542
82b0e23a
TI		 1543#define SAMPLE_COUNT 5
1544
66fd8ad5 1545static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1546{
82b0e23a
TI		 1547 int i, ro_count;
1548
82b0e23a 1549 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1550 return sdhci_check_ro(host);
82b0e23a
TI		 1551
1552 ro_count = 0;
1553 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1554 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1555 if (++ro_count > SAMPLE_COUNT / 2)
1556 return 1;
1557 }
1558 msleep(30);
1559 }
1560 return 0;
1561}
1562
20758b66
AH		 1563static void sdhci_hw_reset(struct mmc_host *mmc)
1564{
1565 struct sdhci_host *host = mmc_priv(mmc);
1566
1567 if (host->ops && host->ops->hw_reset)
1568 host->ops->hw_reset(host);
1569}
1570
66fd8ad5 1571static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1572{
66fd8ad5
AH		 1573 struct sdhci_host *host = mmc_priv(mmc);
1574 int ret;
f75979b7 1575
66fd8ad5
AH		 1576 sdhci_runtime_pm_get(host);
1577 ret = sdhci_do_get_ro(host);
1578 sdhci_runtime_pm_put(host);
1579 return ret;
1580}
f75979b7 1581
66fd8ad5
AH		 1582static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1583{
1e72859e
PO		 1584 if (host->flags & SDHCI_DEVICE_DEAD)
1585 goto out;
1586
66fd8ad5
AH		 1587 if (enable)
1588 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1589 else
1590 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1591
1592 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1593 if (host->runtime_suspended)
1594 goto out;
1595
f75979b7 1596 if (enable)
7260cf5e
AV		 1597 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1598 else
1599 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1600out:
f75979b7 1601 mmiowb();
66fd8ad5
AH		 1602}
1603
1604static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1605{
1606 struct sdhci_host *host = mmc_priv(mmc);
1607 unsigned long flags;
f75979b7 1608
66fd8ad5
AH		 1609 spin_lock_irqsave(&host->lock, flags);
1610 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1611 spin_unlock_irqrestore(&host->lock, flags);
1612}
1613
6231f3de
PR		 1614static int sdhci_do_3_3v_signal_voltage_switch(struct sdhci_host *host,
1615 u16 ctrl)
f2119df6 1616{
6231f3de 1617 int ret;
f2119df6 1618
6231f3de
PR		 1619 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1620 ctrl &= ~SDHCI_CTRL_VDD_180;
1621 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1622
6231f3de 1623 if (host->vqmmc) {
cec2e216 1624 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
6231f3de
PR		 1625 if (ret) {
1626 pr_warning("%s: Switching to 3.3V signalling voltage "
1627 " failed\n", mmc_hostname(host->mmc));
1628 return -EIO;
1629 }
1630 }
1631 /* Wait for 5ms */
1632 usleep_range(5000, 5500);
1633
1634 /* 3.3V regulator output should be stable within 5 ms */
f2119df6 1635 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
6231f3de
PR		 1636 if (!(ctrl & SDHCI_CTRL_VDD_180))
1637 return 0;
f2119df6 1638
6231f3de
PR		 1639 pr_warning("%s: 3.3V regulator output did not became stable\n",
1640 mmc_hostname(host->mmc));
f2119df6 1641
6231f3de
PR		 1642 return -EIO;
1643}
f2119df6 1644
6231f3de
PR		 1645static int sdhci_do_1_8v_signal_voltage_switch(struct sdhci_host *host,
1646 u16 ctrl)
1647{
1648 u8 pwr;
1649 u16 clk;
1650 u32 present_state;
1651 int ret;
1652
1653 /* Stop SDCLK */
1654 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1655 clk &= ~SDHCI_CLOCK_CARD_EN;
1656 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1657
1658 /* Check whether DAT[3:0] is 0000 */
1659 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1660 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1661 SDHCI_DATA_LVL_SHIFT)) {
1662 /*
1663 * Enable 1.8V Signal Enable in the Host Control2
1664 * register
1665 */
1666 if (host->vqmmc)
1667 ret = regulator_set_voltage(host->vqmmc,
cec2e216 1668 1700000, 1950000);
6231f3de
PR		 1669 else
1670 ret = 0;
1671
1672 if (!ret) {
f2119df6
AN		 1673 ctrl |= SDHCI_CTRL_VDD_180;
1674 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1675
1676 /* Wait for 5ms */
1677 usleep_range(5000, 5500);
1678
1679 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1680 if (ctrl & SDHCI_CTRL_VDD_180) {
6231f3de 1681 /* Provide SDCLK again and wait for 1ms */
f2119df6
AN		 1682 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1683 clk |= SDHCI_CLOCK_CARD_EN;
1684 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1685 usleep_range(1000, 1500);
1686
1687 /*
1688 * If DAT[3:0] level is 1111b, then the card
1689 * was successfully switched to 1.8V signaling.
1690 */
1691 present_state = sdhci_readl(host,
1692 SDHCI_PRESENT_STATE);
1693 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1694 SDHCI_DATA_LVL_MASK)
1695 return 0;
1696 }
1697 }
6231f3de 1698 }
f2119df6 1699
6231f3de
PR		 1700 /*
1701 * If we are here, that means the switch to 1.8V signaling
1702 * failed. We power cycle the card, and retry initialization
1703 * sequence by setting S18R to 0.
1704 */
1705 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1706 pwr &= ~SDHCI_POWER_ON;
1707 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1708 if (host->vmmc)
1709 regulator_disable(host->vmmc);
f2119df6 1710
6231f3de
PR		 1711 /* Wait for 1ms as per the spec */
1712 usleep_range(1000, 1500);
1713 pwr |= SDHCI_POWER_ON;
1714 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1715 if (host->vmmc)
1716 regulator_enable(host->vmmc);
f2119df6 1717
6231f3de
PR		 1718 pr_warning("%s: Switching to 1.8V signalling voltage failed, "
1719 "retrying with S18R set to 0\n", mmc_hostname(host->mmc));
1720
1721 return -EAGAIN;
1722}
1723
1724static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1725 struct mmc_ios *ios)
1726{
1727 u16 ctrl;
1728
1729 /*
1730 * Signal Voltage Switching is only applicable for Host Controllers
1731 * v3.00 and above.
1732 */
1733 if (host->version < SDHCI_SPEC_300)
1734 return 0;
1735
1736 /*
1737 * We first check whether the request is to set signalling voltage
1738 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1739 */
1740 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1741 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1742 return sdhci_do_3_3v_signal_voltage_switch(host, ctrl);
1743 else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1744 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180))
1745 return sdhci_do_1_8v_signal_voltage_switch(host, ctrl);
1746 else
f2119df6
AN		 1747 /* No signal voltage switch required */
1748 return 0;
1749}
1750
66fd8ad5
AH		 1751static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1752 struct mmc_ios *ios)
1753{
1754 struct sdhci_host *host = mmc_priv(mmc);
1755 int err;
1756
1757 if (host->version < SDHCI_SPEC_300)
1758 return 0;
1759 sdhci_runtime_pm_get(host);
1760 err = sdhci_do_start_signal_voltage_switch(host, ios);
1761 sdhci_runtime_pm_put(host);
1762 return err;
1763}
1764
069c9f14 1765static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25
AN		 1766{
1767 struct sdhci_host *host;
1768 u16 ctrl;
1769 u32 ier;
1770 int tuning_loop_counter = MAX_TUNING_LOOP;
1771 unsigned long timeout;
1772 int err = 0;
069c9f14 1773 bool requires_tuning_nonuhs = false;
b513ea25
AN		 1774
1775 host = mmc_priv(mmc);
1776
66fd8ad5 1777 sdhci_runtime_pm_get(host);
b513ea25
AN		 1778 disable_irq(host->irq);
1779 spin_lock(&host->lock);
1780
1781 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1782
1783 /*
069c9f14
G		 1784 * The Host Controller needs tuning only in case of SDR104 mode
1785 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1786 * Capabilities register.
069c9f14
G		 1787 * If the Host Controller supports the HS200 mode then the
1788 * tuning function has to be executed.
b513ea25 1789 */
069c9f14
G		 1790 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1791 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1792 host->flags & SDHCI_HS200_NEEDS_TUNING))
1793 requires_tuning_nonuhs = true;
1794
b513ea25 1795 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
069c9f14 1796 requires_tuning_nonuhs)
b513ea25
AN		 1797 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1798 else {
1799 spin_unlock(&host->lock);
1800 enable_irq(host->irq);
66fd8ad5 1801 sdhci_runtime_pm_put(host);
b513ea25
AN		 1802 return 0;
1803 }
1804
1805 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1806
1807 /*
1808 * As per the Host Controller spec v3.00, tuning command
1809 * generates Buffer Read Ready interrupt, so enable that.
1810 *
1811 * Note: The spec clearly says that when tuning sequence
1812 * is being performed, the controller does not generate
1813 * interrupts other than Buffer Read Ready interrupt. But
1814 * to make sure we don't hit a controller bug, we _only_
1815 * enable Buffer Read Ready interrupt here.
1816 */
1817 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1818 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1819
1820 /*
1821 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1822 * of loops reaches 40 times or a timeout of 150ms occurs.
1823 */
1824 timeout = 150;
1825 do {
1826 struct mmc_command cmd = {0};
66fd8ad5 1827 struct mmc_request mrq = {NULL};
b513ea25
AN		 1828
1829 if (!tuning_loop_counter && !timeout)
1830 break;
1831
069c9f14 1832 cmd.opcode = opcode;
b513ea25
AN		 1833 cmd.arg = 0;
1834 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1835 cmd.retries = 0;
1836 cmd.data = NULL;
1837 cmd.error = 0;
1838
1839 mrq.cmd = &cmd;
1840 host->mrq = &mrq;
1841
1842 /*
1843 * In response to CMD19, the card sends 64 bytes of tuning
1844 * block to the Host Controller. So we set the block size
1845 * to 64 here.
1846 */
069c9f14
G		 1847 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1848 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1849 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1850 SDHCI_BLOCK_SIZE);
1851 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1852 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1853 SDHCI_BLOCK_SIZE);
1854 } else {
1855 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1856 SDHCI_BLOCK_SIZE);
1857 }
b513ea25
AN		 1858
1859 /*
1860 * The tuning block is sent by the card to the host controller.
1861 * So we set the TRNS_READ bit in the Transfer Mode register.
1862 * This also takes care of setting DMA Enable and Multi Block
1863 * Select in the same register to 0.
1864 */
1865 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1866
1867 sdhci_send_command(host, &cmd);
1868
1869 host->cmd = NULL;
1870 host->mrq = NULL;
1871
1872 spin_unlock(&host->lock);
1873 enable_irq(host->irq);
1874
1875 /* Wait for Buffer Read Ready interrupt */
1876 wait_event_interruptible_timeout(host->buf_ready_int,
1877 (host->tuning_done == 1),
1878 msecs_to_jiffies(50));
1879 disable_irq(host->irq);
1880 spin_lock(&host->lock);
1881
1882 if (!host->tuning_done) {
a3c76eb9 1883 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1884 "Buffer Read Ready interrupt during tuning "
1885 "procedure, falling back to fixed sampling "
1886 "clock\n");
1887 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1888 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1889 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1890 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1891
1892 err = -EIO;
1893 goto out;
1894 }
1895
1896 host->tuning_done = 0;
1897
1898 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1899 tuning_loop_counter--;
1900 timeout--;
1901 mdelay(1);
1902 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1903
1904 /*
1905 * The Host Driver has exhausted the maximum number of loops allowed,
1906 * so use fixed sampling frequency.
1907 */
1908 if (!tuning_loop_counter || !timeout) {
1909 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1910 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1911 } else {
1912 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1913 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1914 " failed, falling back to fixed sampling"
1915 " clock\n");
1916 err = -EIO;
1917 }
1918 }
1919
1920out:
cf2b5eea
AN		 1921 /*
1922 * If this is the very first time we are here, we start the retuning
1923 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1924 * flag won't be set, we check this condition before actually starting
1925 * the timer.
1926 */
1927 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1928 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 1929 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 1930 mod_timer(&host->tuning_timer, jiffies +
1931 host->tuning_count * HZ);
1932 /* Tuning mode 1 limits the maximum data length to 4MB */
1933 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1934 } else {
1935 host->flags &= ~SDHCI_NEEDS_RETUNING;
1936 /* Reload the new initial value for timer */
1937 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1938 mod_timer(&host->tuning_timer, jiffies +
1939 host->tuning_count * HZ);
1940 }
1941
1942 /*
1943 * In case tuning fails, host controllers which support re-tuning can
1944 * try tuning again at a later time, when the re-tuning timer expires.
1945 * So for these controllers, we return 0. Since there might be other
1946 * controllers who do not have this capability, we return error for
973905fe
AL		 1947 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
1948 * a retuning timer to do the retuning for the card.
cf2b5eea 1949 */
973905fe 1950 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 1951 err = 0;
1952
b513ea25
AN		 1953 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1954 spin_unlock(&host->lock);
1955 enable_irq(host->irq);
66fd8ad5 1956 sdhci_runtime_pm_put(host);
b513ea25
AN		 1957
1958 return err;
1959}
1960
66fd8ad5 1961static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 1962{
4d55c5a1
AN		 1963 u16 ctrl;
1964 unsigned long flags;
1965
4d55c5a1
AN		 1966 /* Host Controller v3.00 defines preset value registers */
1967 if (host->version < SDHCI_SPEC_300)
1968 return;
1969
1970 spin_lock_irqsave(&host->lock, flags);
1971
1972 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1973
1974 /*
1975 * We only enable or disable Preset Value if they are not already
1976 * enabled or disabled respectively. Otherwise, we bail out.
1977 */
1978 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1979 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1980 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 1981 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 1982 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1983 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1984 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 1985 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1
AN		 1986 }
1987
1988 spin_unlock_irqrestore(&host->lock, flags);
1989}
1990
66fd8ad5
AH		 1991static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1992{
1993 struct sdhci_host *host = mmc_priv(mmc);
1994
1995 sdhci_runtime_pm_get(host);
1996 sdhci_do_enable_preset_value(host, enable);
1997 sdhci_runtime_pm_put(host);
1998}
1999
71e69211 2000static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2001{
71e69211 2002 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2003 unsigned long flags;
2004
d129bceb
PO		 2005 spin_lock_irqsave(&host->lock, flags);
2006
66fd8ad5
AH		 2007 /* Check host->mrq first in case we are runtime suspended */
2008 if (host->mrq &&
2009 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
a3c76eb9 2010 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2011 mmc_hostname(host->mmc));
a3c76eb9 2012 pr_err("%s: Resetting controller.\n",
66fd8ad5 2013 mmc_hostname(host->mmc));
d129bceb 2014
66fd8ad5
AH		 2015 sdhci_reset(host, SDHCI_RESET_CMD);
2016 sdhci_reset(host, SDHCI_RESET_DATA);
d129bceb 2017
66fd8ad5
AH		 2018 host->mrq->cmd->error = -ENOMEDIUM;
2019 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2020 }
2021
2022 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2023}
2024
2025static const struct mmc_host_ops sdhci_ops = {
2026 .request = sdhci_request,
2027 .set_ios = sdhci_set_ios,
2028 .get_ro = sdhci_get_ro,
2029 .hw_reset = sdhci_hw_reset,
2030 .enable_sdio_irq = sdhci_enable_sdio_irq,
2031 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2032 .execute_tuning = sdhci_execute_tuning,
2033 .enable_preset_value = sdhci_enable_preset_value,
2034 .card_event = sdhci_card_event,
2035};
2036
2037/*****************************************************************************\
2038 * *
2039 * Tasklets *
2040 * *
2041\*****************************************************************************/
2042
2043static void sdhci_tasklet_card(unsigned long param)
2044{
2045 struct sdhci_host *host = (struct sdhci_host*)param;
2046
2047 sdhci_card_event(host->mmc);
d129bceb 2048
04cf585d 2049 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 2050}
2051
2052static void sdhci_tasklet_finish(unsigned long param)
2053{
2054 struct sdhci_host *host;
2055 unsigned long flags;
2056 struct mmc_request *mrq;
2057
2058 host = (struct sdhci_host*)param;
2059
66fd8ad5
AH		 2060 spin_lock_irqsave(&host->lock, flags);
2061
0c9c99a7
CB		 2062 /*
2063 * If this tasklet gets rescheduled while running, it will
2064 * be run again afterwards but without any active request.
2065 */
66fd8ad5
AH		 2066 if (!host->mrq) {
2067 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2068 return;
66fd8ad5 2069 }
d129bceb
PO		 2070
2071 del_timer(&host->timer);
2072
2073 mrq = host->mrq;
2074
d129bceb
PO		 2075 /*
2076 * The controller needs a reset of internal state machines
2077 * upon error conditions.
2078 */
1e72859e 2079 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2080 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2081 (mrq->data && (mrq->data->error ||
2082 (mrq->data->stop && mrq->data->stop->error))) ||
2083 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2084
2085 /* Some controllers need this kick or reset won't work here */
b8c86fc5 2086 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 2087 unsigned int clock;
2088
2089 /* This is to force an update */
2090 clock = host->clock;
2091 host->clock = 0;
2092 sdhci_set_clock(host, clock);
2093 }
2094
2095 /* Spec says we should do both at the same time, but Ricoh
2096 controllers do not like that. */
d129bceb
PO		 2097 sdhci_reset(host, SDHCI_RESET_CMD);
2098 sdhci_reset(host, SDHCI_RESET_DATA);
2099 }
2100
2101 host->mrq = NULL;
2102 host->cmd = NULL;
2103 host->data = NULL;
2104
f9134319 2105#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2106 sdhci_deactivate_led(host);
2f730fec 2107#endif
d129bceb 2108
5f25a66f 2109 mmiowb();
d129bceb
PO		 2110 spin_unlock_irqrestore(&host->lock, flags);
2111
2112 mmc_request_done(host->mmc, mrq);
66fd8ad5 2113 sdhci_runtime_pm_put(host);
d129bceb
PO		 2114}
2115
2116static void sdhci_timeout_timer(unsigned long data)
2117{
2118 struct sdhci_host *host;
2119 unsigned long flags;
2120
2121 host = (struct sdhci_host*)data;
2122
2123 spin_lock_irqsave(&host->lock, flags);
2124
2125 if (host->mrq) {
a3c76eb9 2126 pr_err("%s: Timeout waiting for hardware "
acf1da45 2127 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2128 sdhci_dumpregs(host);
2129
2130 if (host->data) {
17b0429d 2131 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2132 sdhci_finish_data(host);
2133 } else {
2134 if (host->cmd)
17b0429d 2135 host->cmd->error = -ETIMEDOUT;
d129bceb 2136 else
17b0429d 2137 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2138
2139 tasklet_schedule(&host->finish_tasklet);
2140 }
2141 }
2142
5f25a66f 2143 mmiowb();
d129bceb
PO		 2144 spin_unlock_irqrestore(&host->lock, flags);
2145}
2146
cf2b5eea
AN		 2147static void sdhci_tuning_timer(unsigned long data)
2148{
2149 struct sdhci_host *host;
2150 unsigned long flags;
2151
2152 host = (struct sdhci_host *)data;
2153
2154 spin_lock_irqsave(&host->lock, flags);
2155
2156 host->flags |= SDHCI_NEEDS_RETUNING;
2157
2158 spin_unlock_irqrestore(&host->lock, flags);
2159}
2160
d129bceb
PO		 2161/*****************************************************************************\
2162 * *
2163 * Interrupt handling *
2164 * *
2165\*****************************************************************************/
2166
2167static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2168{
2169 BUG_ON(intmask == 0);
2170
2171 if (!host->cmd) {
a3c76eb9 2172 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2173 "though no command operation was in progress.\n",
2174 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2175 sdhci_dumpregs(host);
2176 return;
2177 }
2178
43b58b36 2179 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2180 host->cmd->error = -ETIMEDOUT;
2181 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2182 SDHCI_INT_INDEX))
2183 host->cmd->error = -EILSEQ;
43b58b36 2184
e809517f 2185 if (host->cmd->error) {
d129bceb 2186 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2187 return;
2188 }
2189
2190 /*
2191 * The host can send and interrupt when the busy state has
2192 * ended, allowing us to wait without wasting CPU cycles.
2193 * Unfortunately this is overloaded on the "data complete"
2194 * interrupt, so we need to take some care when handling
2195 * it.
2196 *
2197 * Note: The 1.0 specification is a bit ambiguous about this
2198 * feature so there might be some problems with older
2199 * controllers.
2200 */
2201 if (host->cmd->flags & MMC_RSP_BUSY) {
2202 if (host->cmd->data)
2203 DBG("Cannot wait for busy signal when also "
2204 "doing a data transfer");
f945405c 2205 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2206 return;
f945405c
BD		 2207
2208 /* The controller does not support the end-of-busy IRQ,
2209 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2210 }
2211
2212 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2213 sdhci_finish_command(host);
d129bceb
PO		 2214}
2215
0957c333 2216#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2217static void sdhci_show_adma_error(struct sdhci_host *host)
2218{
2219 const char *name = mmc_hostname(host->mmc);
2220 u8 *desc = host->adma_desc;
2221 __le32 *dma;
2222 __le16 *len;
2223 u8 attr;
2224
2225 sdhci_dumpregs(host);
2226
2227 while (true) {
2228 dma = (__le32 *)(desc + 4);
2229 len = (__le16 *)(desc + 2);
2230 attr = *desc;
2231
2232 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2233 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2234
2235 desc += 8;
2236
2237 if (attr & 2)
2238 break;
2239 }
2240}
2241#else
2242static void sdhci_show_adma_error(struct sdhci_host *host) { }
2243#endif
2244
d129bceb
PO		 2245static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2246{
069c9f14 2247 u32 command;
d129bceb
PO		 2248 BUG_ON(intmask == 0);
2249
b513ea25
AN		 2250 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2251 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2252 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2253 if (command == MMC_SEND_TUNING_BLOCK ||
2254 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2255 host->tuning_done = 1;
2256 wake_up(&host->buf_ready_int);
2257 return;
2258 }
2259 }
2260
d129bceb
PO		 2261 if (!host->data) {
2262 /*
e809517f
PO		 2263 * The "data complete" interrupt is also used to
2264 * indicate that a busy state has ended. See comment
2265 * above in sdhci_cmd_irq().
d129bceb 2266 */
e809517f
PO		 2267 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2268 if (intmask & SDHCI_INT_DATA_END) {
2269 sdhci_finish_command(host);
2270 return;
2271 }
2272 }
d129bceb 2273
a3c76eb9 2274 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2275 "though no data operation was in progress.\n",
2276 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2277 sdhci_dumpregs(host);
2278
2279 return;
2280 }
2281
2282 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2283 host->data->error = -ETIMEDOUT;
22113efd
AL		 2284 else if (intmask & SDHCI_INT_DATA_END_BIT)
2285 host->data->error = -EILSEQ;
2286 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2287 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2288 != MMC_BUS_TEST_R)
17b0429d 2289 host->data->error = -EILSEQ;
6882a8c0 2290 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2291 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2292 sdhci_show_adma_error(host);
2134a922 2293 host->data->error = -EIO;
a4071fbb
HZ		 2294 if (host->ops->adma_workaround)
2295 host->ops->adma_workaround(host, intmask);
6882a8c0 2296 }
d129bceb 2297
17b0429d 2298 if (host->data->error)
d129bceb
PO		 2299 sdhci_finish_data(host);
2300 else {
a406f5a3 2301 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2302 sdhci_transfer_pio(host);
2303
6ba736a1
PO		 2304 /*
2305 * We currently don't do anything fancy with DMA
2306 * boundaries, but as we can't disable the feature
2307 * we need to at least restart the transfer.
f6a03cbf
MV		 2308 *
2309 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2310 * should return a valid address to continue from, but as
2311 * some controllers are faulty, don't trust them.
6ba736a1 2312 */
f6a03cbf
MV		 2313 if (intmask & SDHCI_INT_DMA_END) {
2314 u32 dmastart, dmanow;
2315 dmastart = sg_dma_address(host->data->sg);
2316 dmanow = dmastart + host->data->bytes_xfered;
2317 /*
2318 * Force update to the next DMA block boundary.
2319 */
2320 dmanow = (dmanow &
2321 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2322 SDHCI_DEFAULT_BOUNDARY_SIZE;
2323 host->data->bytes_xfered = dmanow - dmastart;
2324 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2325 " next 0x%08x\n",
2326 mmc_hostname(host->mmc), dmastart,
2327 host->data->bytes_xfered, dmanow);
2328 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2329 }
6ba736a1 2330
e538fbe8
PO		 2331 if (intmask & SDHCI_INT_DATA_END) {
2332 if (host->cmd) {
2333 /*
2334 * Data managed to finish before the
2335 * command completed. Make sure we do
2336 * things in the proper order.
2337 */
2338 host->data_early = 1;
2339 } else {
2340 sdhci_finish_data(host);
2341 }
2342 }
d129bceb
PO		 2343 }
2344}
2345
7d12e780 2346static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2347{
2348 irqreturn_t result;
66fd8ad5 2349 struct sdhci_host *host = dev_id;
6379b237
AS		 2350 u32 intmask, unexpected = 0;
2351 int cardint = 0, max_loops = 16;
d129bceb
PO		 2352
2353 spin_lock(&host->lock);
2354
66fd8ad5
AH		 2355 if (host->runtime_suspended) {
2356 spin_unlock(&host->lock);
a3c76eb9 2357 pr_warning("%s: got irq while runtime suspended\n",
66fd8ad5
AH		 2358 mmc_hostname(host->mmc));
2359 return IRQ_HANDLED;
2360 }
2361
4e4141a5 2362 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2363
62df67a5 2364 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2365 result = IRQ_NONE;
2366 goto out;
2367 }
2368
6379b237 2369again:
b69c9058
PO		 2370 DBG("*** %s got interrupt: 0x%08x\n",
2371 mmc_hostname(host->mmc), intmask);
d129bceb 2372
3192a28f 2373 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d25928d1
SG		 2374 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2375 SDHCI_CARD_PRESENT;
2376
2377 /*
2378 * There is a observation on i.mx esdhc. INSERT bit will be
2379 * immediately set again when it gets cleared, if a card is
2380 * inserted. We have to mask the irq to prevent interrupt
2381 * storm which will freeze the system. And the REMOVE gets
2382 * the same situation.
2383 *
2384 * More testing are needed here to ensure it works for other
2385 * platforms though.
2386 */
2387 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2388 SDHCI_INT_CARD_REMOVE);
2389 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2390 SDHCI_INT_CARD_INSERT);
2391
4e4141a5 2392 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
d25928d1
SG		 2393 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2394 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2395 tasklet_schedule(&host->card_tasklet);
3192a28f 2396 }
d129bceb 2397
3192a28f 2398 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2399 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2400 SDHCI_INT_STATUS);
3192a28f 2401 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2402 }
2403
2404 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2405 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2406 SDHCI_INT_STATUS);
3192a28f 2407 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2408 }
2409
2410 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2411
964f9ce2
PO		 2412 intmask &= ~SDHCI_INT_ERROR;
2413
d129bceb 2414 if (intmask & SDHCI_INT_BUS_POWER) {
a3c76eb9 2415 pr_err("%s: Card is consuming too much power!\n",
d129bceb 2416 mmc_hostname(host->mmc));
4e4141a5 2417 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2418 }
2419
9d26a5d3 2420 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2421
f75979b7
PO		 2422 if (intmask & SDHCI_INT_CARD_INT)
2423 cardint = 1;
2424
2425 intmask &= ~SDHCI_INT_CARD_INT;
2426
3192a28f 2427 if (intmask) {
6379b237 2428 unexpected |= intmask;
4e4141a5 2429 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2430 }
d129bceb
PO		 2431
2432 result = IRQ_HANDLED;
2433
6379b237
AS		 2434 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2435 if (intmask && --max_loops)
2436 goto again;
d129bceb
PO		 2437out:
2438 spin_unlock(&host->lock);
2439
6379b237
AS		 2440 if (unexpected) {
2441 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2442 mmc_hostname(host->mmc), unexpected);
2443 sdhci_dumpregs(host);
2444 }
f75979b7
PO		 2445 /*
2446 * We have to delay this as it calls back into the driver.
2447 */
2448 if (cardint)
2449 mmc_signal_sdio_irq(host->mmc);
2450
d129bceb
PO		 2451 return result;
2452}
2453
2454/*****************************************************************************\
2455 * *
2456 * Suspend/resume *
2457 * *
2458\*****************************************************************************/
2459
2460#ifdef CONFIG_PM
ad080d79
KL		 2461void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2462{
2463 u8 val;
2464 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2465 | SDHCI_WAKE_ON_INT;
2466
2467 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2468 val |= mask ;
2469 /* Avoid fake wake up */
2470 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2471 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2472 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2473}
2474EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2475
2476void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2477{
2478 u8 val;
2479 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2480 | SDHCI_WAKE_ON_INT;
2481
2482 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2483 val &= ~mask;
2484 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2485}
2486EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
d129bceb 2487
29495aa0 2488int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2489{
b8c86fc5 2490 int ret;
a715dfc7 2491
a1b13b4e
CB		 2492 if (host->ops->platform_suspend)
2493 host->ops->platform_suspend(host);
2494
7260cf5e
AV		 2495 sdhci_disable_card_detection(host);
2496
cf2b5eea 2497 /* Disable tuning since we are suspending */
973905fe 2498 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2499 del_timer_sync(&host->tuning_timer);
cf2b5eea 2500 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2501 }
2502
1a13f8fa 2503 ret = mmc_suspend_host(host->mmc);
38a60ea2 2504 if (ret) {
973905fe 2505 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
38a60ea2
AL		 2506 host->flags |= SDHCI_NEEDS_RETUNING;
2507 mod_timer(&host->tuning_timer, jiffies +
2508 host->tuning_count * HZ);
2509 }
2510
2511 sdhci_enable_card_detection(host);
2512
b8c86fc5 2513 return ret;
38a60ea2 2514 }
a715dfc7 2515
ad080d79
KL		 2516 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2517 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2518 free_irq(host->irq, host);
2519 } else {
2520 sdhci_enable_irq_wakeups(host);
2521 enable_irq_wake(host->irq);
2522 }
9bea3c85 2523 return ret;
d129bceb
PO		 2524}
2525
b8c86fc5 2526EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2527
b8c86fc5
PO		 2528int sdhci_resume_host(struct sdhci_host *host)
2529{
2530 int ret;
d129bceb 2531
a13abc7b 2532 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2533 if (host->ops->enable_dma)
2534 host->ops->enable_dma(host);
2535 }
d129bceb 2536
ad080d79
KL		 2537 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2538 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2539 mmc_hostname(host->mmc), host);
2540 if (ret)
2541 return ret;
2542 } else {
2543 sdhci_disable_irq_wakeups(host);
2544 disable_irq_wake(host->irq);
2545 }
d129bceb 2546
6308d290
AH		 2547 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2548 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2549 /* Card keeps power but host controller does not */
2550 sdhci_init(host, 0);
2551 host->pwr = 0;
2552 host->clock = 0;
2553 sdhci_do_set_ios(host, &host->mmc->ios);
2554 } else {
2555 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2556 mmiowb();
2557 }
b8c86fc5
PO		 2558
2559 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2560 sdhci_enable_card_detection(host);
2561
a1b13b4e
CB		 2562 if (host->ops->platform_resume)
2563 host->ops->platform_resume(host);
2564
cf2b5eea 2565 /* Set the re-tuning expiration flag */
973905fe 2566 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2567 host->flags |= SDHCI_NEEDS_RETUNING;
2568
2f4cbb3d 2569 return ret;
d129bceb
PO		 2570}
2571
b8c86fc5 2572EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2573#endif /* CONFIG_PM */
2574
66fd8ad5
AH		 2575#ifdef CONFIG_PM_RUNTIME
2576
2577static int sdhci_runtime_pm_get(struct sdhci_host *host)
2578{
2579 return pm_runtime_get_sync(host->mmc->parent);
2580}
2581
2582static int sdhci_runtime_pm_put(struct sdhci_host *host)
2583{
2584 pm_runtime_mark_last_busy(host->mmc->parent);
2585 return pm_runtime_put_autosuspend(host->mmc->parent);
2586}
2587
2588int sdhci_runtime_suspend_host(struct sdhci_host *host)
2589{
2590 unsigned long flags;
2591 int ret = 0;
2592
2593 /* Disable tuning since we are suspending */
973905fe 2594 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2595 del_timer_sync(&host->tuning_timer);
2596 host->flags &= ~SDHCI_NEEDS_RETUNING;
2597 }
2598
2599 spin_lock_irqsave(&host->lock, flags);
2600 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2601 spin_unlock_irqrestore(&host->lock, flags);
2602
2603 synchronize_irq(host->irq);
2604
2605 spin_lock_irqsave(&host->lock, flags);
2606 host->runtime_suspended = true;
2607 spin_unlock_irqrestore(&host->lock, flags);
2608
2609 return ret;
2610}
2611EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2612
2613int sdhci_runtime_resume_host(struct sdhci_host *host)
2614{
2615 unsigned long flags;
2616 int ret = 0, host_flags = host->flags;
2617
2618 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2619 if (host->ops->enable_dma)
2620 host->ops->enable_dma(host);
2621 }
2622
2623 sdhci_init(host, 0);
2624
2625 /* Force clock and power re-program */
2626 host->pwr = 0;
2627 host->clock = 0;
2628 sdhci_do_set_ios(host, &host->mmc->ios);
2629
2630 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2631 if (host_flags & SDHCI_PV_ENABLED)
2632 sdhci_do_enable_preset_value(host, true);
2633
2634 /* Set the re-tuning expiration flag */
973905fe 2635 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2636 host->flags |= SDHCI_NEEDS_RETUNING;
2637
2638 spin_lock_irqsave(&host->lock, flags);
2639
2640 host->runtime_suspended = false;
2641
2642 /* Enable SDIO IRQ */
2643 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2644 sdhci_enable_sdio_irq_nolock(host, true);
2645
2646 /* Enable Card Detection */
2647 sdhci_enable_card_detection(host);
2648
2649 spin_unlock_irqrestore(&host->lock, flags);
2650
2651 return ret;
2652}
2653EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2654
2655#endif
2656
d129bceb
PO		 2657/*****************************************************************************\
2658 * *
b8c86fc5 2659 * Device allocation/registration *
d129bceb
PO		 2660 * *
2661\*****************************************************************************/
2662
b8c86fc5
PO		 2663struct sdhci_host *sdhci_alloc_host(struct device *dev,
2664 size_t priv_size)
d129bceb 2665{
d129bceb
PO		 2666 struct mmc_host *mmc;
2667 struct sdhci_host *host;
2668
b8c86fc5 2669 WARN_ON(dev == NULL);
d129bceb 2670
b8c86fc5 2671 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2672 if (!mmc)
b8c86fc5 2673 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2674
2675 host = mmc_priv(mmc);
2676 host->mmc = mmc;
2677
b8c86fc5
PO		 2678 return host;
2679}
8a4da143 2680
b8c86fc5 2681EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2682
b8c86fc5
PO		 2683int sdhci_add_host(struct sdhci_host *host)
2684{
2685 struct mmc_host *mmc;
bd6a8c30 2686 u32 caps[2] = {0, 0};
f2119df6
AN		 2687 u32 max_current_caps;
2688 unsigned int ocr_avail;
b8c86fc5 2689 int ret;
d129bceb 2690
b8c86fc5
PO		 2691 WARN_ON(host == NULL);
2692 if (host == NULL)
2693 return -EINVAL;
d129bceb 2694
b8c86fc5 2695 mmc = host->mmc;
d129bceb 2696
b8c86fc5
PO		 2697 if (debug_quirks)
2698 host->quirks = debug_quirks;
66fd8ad5
AH		 2699 if (debug_quirks2)
2700 host->quirks2 = debug_quirks2;
d129bceb 2701
d96649ed
PO		 2702 sdhci_reset(host, SDHCI_RESET_ALL);
2703
4e4141a5 2704 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2705 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2706 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2707 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2708 pr_err("%s: Unknown controller version (%d). "
b69c9058 2709 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2710 host->version);
4a965505
PO		 2711 }
2712
f2119df6 2713 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2714 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2715
bd6a8c30
PR		 2716 if (host->version >= SDHCI_SPEC_300)
2717 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2718 host->caps1 :
2719 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2720
b8c86fc5 2721 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2722 host->flags |= SDHCI_USE_SDMA;
f2119df6 2723 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2724 DBG("Controller doesn't have SDMA capability\n");
67435274 2725 else
a13abc7b 2726 host->flags |= SDHCI_USE_SDMA;
d129bceb 2727
b8c86fc5 2728 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2729 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2730 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2731 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2732 }
2733
f2119df6
AN		 2734 if ((host->version >= SDHCI_SPEC_200) &&
2735 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2736 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2737
2738 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2739 (host->flags & SDHCI_USE_ADMA)) {
2740 DBG("Disabling ADMA as it is marked broken\n");
2741 host->flags &= ~SDHCI_USE_ADMA;
2742 }
2743
a13abc7b 2744 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2745 if (host->ops->enable_dma) {
2746 if (host->ops->enable_dma(host)) {
a3c76eb9 2747 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2748 "available. Falling back to PIO.\n",
2749 mmc_hostname(mmc));
a13abc7b
RR		 2750 host->flags &=
2751 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2752 }
d129bceb
PO		 2753 }
2754 }
2755
2134a922
PO		 2756 if (host->flags & SDHCI_USE_ADMA) {
2757 /*
2758 * We need to allocate descriptors for all sg entries
2759 * (128) and potentially one alignment transfer for
2760 * each of those entries.
2761 */
2762 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2763 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2764 if (!host->adma_desc || !host->align_buffer) {
2765 kfree(host->adma_desc);
2766 kfree(host->align_buffer);
a3c76eb9 2767 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2768 "buffers. Falling back to standard DMA.\n",
2769 mmc_hostname(mmc));
2770 host->flags &= ~SDHCI_USE_ADMA;
2771 }
2772 }
2773
7659150c
PO		 2774 /*
2775 * If we use DMA, then it's up to the caller to set the DMA
2776 * mask, but PIO does not need the hw shim so we set a new
2777 * mask here in that case.
2778 */
a13abc7b 2779 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2780 host->dma_mask = DMA_BIT_MASK(64);
2781 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2782 }
d129bceb 2783
c4687d5f 2784 if (host->version >= SDHCI_SPEC_300)
f2119df6 2785 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2786 >> SDHCI_CLOCK_BASE_SHIFT;
2787 else
f2119df6 2788 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2789 >> SDHCI_CLOCK_BASE_SHIFT;
2790
4240ff0a 2791 host->max_clk *= 1000000;
f27f47ef
AV		 2792 if (host->max_clk == 0 || host->quirks &
2793 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2794 if (!host->ops->get_max_clock) {
a3c76eb9 2795 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2796 "frequency.\n", mmc_hostname(mmc));
2797 return -ENODEV;
2798 }
2799 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2800 }
d129bceb 2801
c3ed3877
AN		 2802 /*
2803 * In case of Host Controller v3.00, find out whether clock
2804 * multiplier is supported.
2805 */
2806 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2807 SDHCI_CLOCK_MUL_SHIFT;
2808
2809 /*
2810 * In case the value in Clock Multiplier is 0, then programmable
2811 * clock mode is not supported, otherwise the actual clock
2812 * multiplier is one more than the value of Clock Multiplier
2813 * in the Capabilities Register.
2814 */
2815 if (host->clk_mul)
2816 host->clk_mul += 1;
2817
d129bceb
PO		 2818 /*
2819 * Set host parameters.
2820 */
2821 mmc->ops = &sdhci_ops;
c3ed3877 2822 mmc->f_max = host->max_clk;
ce5f036b 2823 if (host->ops->get_min_clock)
a9e58f25 2824 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2825 else if (host->version >= SDHCI_SPEC_300) {
2826 if (host->clk_mul) {
2827 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2828 mmc->f_max = host->max_clk * host->clk_mul;
2829 } else
2830 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2831 } else
0397526d 2832 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2833
272308ca
AS		 2834 host->timeout_clk =
2835 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2836 if (host->timeout_clk == 0) {
2837 if (host->ops->get_timeout_clock) {
2838 host->timeout_clk = host->ops->get_timeout_clock(host);
2839 } else if (!(host->quirks &
2840 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2841 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2842 "frequency.\n", mmc_hostname(mmc));
2843 return -ENODEV;
2844 }
2845 }
2846 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2847 host->timeout_clk *= 1000;
2848
2849 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2850 host->timeout_clk = mmc->f_max / 1000;
272308ca 2851
65be3fef 2852 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
58d1246d 2853
e89d456f
AW		 2854 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2855
2856 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2857 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2858
8edf6371 2859 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2860 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2861 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2862 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2863 host->flags |= SDHCI_AUTO_CMD23;
2864 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2865 } else {
2866 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2867 }
2868
15ec4461
PR		 2869 /*
2870 * A controller may support 8-bit width, but the board itself
2871 * might not have the pins brought out. Boards that support
2872 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2873 * their platform code before calling sdhci_add_host(), and we
2874 * won't assume 8-bit width for hosts without that CAP.
2875 */
5fe23c7f 2876 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2877 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2878
63ef5d8c
JH		 2879 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2880 mmc->caps &= ~MMC_CAP_CMD23;
2881
f2119df6 2882 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2883 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2884
176d1ed4 2885 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
eb6d5ae1 2886 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 2887 mmc->caps |= MMC_CAP_NEEDS_POLL;
2888
6231f3de
PR		 2889 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2890 host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc");
657d5982
KL		 2891 if (IS_ERR_OR_NULL(host->vqmmc)) {
2892 if (PTR_ERR(host->vqmmc) < 0) {
2893 pr_info("%s: no vqmmc regulator found\n",
2894 mmc_hostname(mmc));
2895 host->vqmmc = NULL;
2896 }
8363c374 2897 } else {
6231f3de 2898 regulator_enable(host->vqmmc);
cec2e216
KL		 2899 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2900 1950000))
8363c374
KL		 2901 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2902 SDHCI_SUPPORT_SDR50 |
2903 SDHCI_SUPPORT_DDR50);
2904 }
6231f3de 2905
6a66180a
DD		 2906 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2907 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2908 SDHCI_SUPPORT_DDR50);
2909
4188bba0
AC		 2910 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2911 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2912 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 2913 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2914
2915 /* SDR104 supports also implies SDR50 support */
2916 if (caps[1] & SDHCI_SUPPORT_SDR104)
2917 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2918 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2919 mmc->caps |= MMC_CAP_UHS_SDR50;
2920
2921 if (caps[1] & SDHCI_SUPPORT_DDR50)
2922 mmc->caps |= MMC_CAP_UHS_DDR50;
2923
069c9f14 2924 /* Does the host need tuning for SDR50? */
b513ea25
AN		 2925 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2926 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2927
069c9f14
G		 2928 /* Does the host need tuning for HS200? */
2929 if (mmc->caps2 & MMC_CAP2_HS200)
2930 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2931
d6d50a15
AN		 2932 /* Driver Type(s) (A, C, D) supported by the host */
2933 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2934 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2935 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2936 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2937 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2938 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2939
cf2b5eea
AN		 2940 /* Initial value for re-tuning timer count */
2941 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2942 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2943
2944 /*
2945 * In case Re-tuning Timer is not disabled, the actual value of
2946 * re-tuning timer will be 2 ^ (n - 1).
2947 */
2948 if (host->tuning_count)
2949 host->tuning_count = 1 << (host->tuning_count - 1);
2950
2951 /* Re-tuning mode supported by the Host Controller */
2952 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2953 SDHCI_RETUNING_MODE_SHIFT;
2954
8f230f45 2955 ocr_avail = 0;
bad37e1a
PR		 2956
2957 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
657d5982
KL		 2958 if (IS_ERR_OR_NULL(host->vmmc)) {
2959 if (PTR_ERR(host->vmmc) < 0) {
2960 pr_info("%s: no vmmc regulator found\n",
2961 mmc_hostname(mmc));
2962 host->vmmc = NULL;
2963 }
8363c374 2964 }
bad37e1a 2965
68737043
PR		 2966#ifdef CONFIG_REGULATOR
2967 if (host->vmmc) {
cec2e216
KL		 2968 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
2969 3600000);
68737043
PR		 2970 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
2971 caps[0] &= ~SDHCI_CAN_VDD_330;
68737043
PR		 2972 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
2973 caps[0] &= ~SDHCI_CAN_VDD_300;
cec2e216
KL		 2974 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
2975 1950000);
68737043
PR		 2976 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
2977 caps[0] &= ~SDHCI_CAN_VDD_180;
2978 }
2979#endif /* CONFIG_REGULATOR */
2980
f2119df6
AN		 2981 /*
2982 * According to SD Host Controller spec v3.00, if the Host System
2983 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2984 * the value is meaningful only if Voltage Support in the Capabilities
2985 * register is set. The actual current value is 4 times the register
2986 * value.
2987 */
2988 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
bad37e1a
PR		 2989 if (!max_current_caps && host->vmmc) {
2990 u32 curr = regulator_get_current_limit(host->vmmc);
2991 if (curr > 0) {
2992
2993 /* convert to SDHCI_MAX_CURRENT format */
2994 curr = curr/1000; /* convert to mA */
2995 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
2996
2997 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
2998 max_current_caps =
2999 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3000 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3001 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3002 }
3003 }
f2119df6
AN		 3004
3005 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3006 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3007
55c4665e 3008 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3009 SDHCI_MAX_CURRENT_330_MASK) >>
3010 SDHCI_MAX_CURRENT_330_SHIFT) *
3011 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3012 }
3013 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3014 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3015
55c4665e 3016 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3017 SDHCI_MAX_CURRENT_300_MASK) >>
3018 SDHCI_MAX_CURRENT_300_SHIFT) *
3019 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3020 }
3021 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3022 ocr_avail |= MMC_VDD_165_195;
3023
55c4665e 3024 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3025 SDHCI_MAX_CURRENT_180_MASK) >>
3026 SDHCI_MAX_CURRENT_180_SHIFT) *
3027 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3028 }
3029
8f230f45
TI		 3030 mmc->ocr_avail = ocr_avail;
3031 mmc->ocr_avail_sdio = ocr_avail;
3032 if (host->ocr_avail_sdio)
3033 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3034 mmc->ocr_avail_sd = ocr_avail;
3035 if (host->ocr_avail_sd)
3036 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3037 else /* normal SD controllers don't support 1.8V */
3038 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3039 mmc->ocr_avail_mmc = ocr_avail;
3040 if (host->ocr_avail_mmc)
3041 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3042
3043 if (mmc->ocr_avail == 0) {
a3c76eb9 3044 pr_err("%s: Hardware doesn't report any "
b69c9058 3045 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3046 return -ENODEV;
146ad66e
PO		 3047 }
3048
d129bceb
PO		 3049 spin_lock_init(&host->lock);
3050
3051 /*
2134a922
PO		 3052 * Maximum number of segments. Depends on if the hardware
3053 * can do scatter/gather or not.
d129bceb 3054 */
2134a922 3055 if (host->flags & SDHCI_USE_ADMA)
a36274e0 3056 mmc->max_segs = 128;
a13abc7b 3057 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3058 mmc->max_segs = 1;
2134a922 3059 else /* PIO */
a36274e0 3060 mmc->max_segs = 128;
d129bceb
PO		 3061
3062 /*
bab76961 3063 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3064 * size (512KiB).
d129bceb 3065 */
55db890a 3066 mmc->max_req_size = 524288;
d129bceb
PO		 3067
3068 /*
3069 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3070 * of bytes. When doing hardware scatter/gather, each entry cannot
3071 * be larger than 64 KiB though.
d129bceb 3072 */
30652aa3
OJ		 3073 if (host->flags & SDHCI_USE_ADMA) {
3074 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3075 mmc->max_seg_size = 65535;
3076 else
3077 mmc->max_seg_size = 65536;
3078 } else {
2134a922 3079 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3080 }
d129bceb 3081
fe4a3c7a
PO		 3082 /*
3083 * Maximum block size. This varies from controller to controller and
3084 * is specified in the capabilities register.
3085 */
0633f654
AV		 3086 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3087 mmc->max_blk_size = 2;
3088 } else {
f2119df6 3089 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3090 SDHCI_MAX_BLOCK_SHIFT;
3091 if (mmc->max_blk_size >= 3) {
a3c76eb9 3092 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 3093 "assuming 512 bytes\n", mmc_hostname(mmc));
3094 mmc->max_blk_size = 0;
3095 }
3096 }
3097
3098 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3099
55db890a
PO		 3100 /*
3101 * Maximum block count.
3102 */
1388eefd 3103 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3104
d129bceb
PO		 3105 /*
3106 * Init tasklets.
3107 */
3108 tasklet_init(&host->card_tasklet,
3109 sdhci_tasklet_card, (unsigned long)host);
3110 tasklet_init(&host->finish_tasklet,
3111 sdhci_tasklet_finish, (unsigned long)host);
3112
e4cad1b5 3113 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3114
cf2b5eea 3115 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3116 init_waitqueue_head(&host->buf_ready_int);
3117
cf2b5eea
AN		 3118 /* Initialize re-tuning timer */
3119 init_timer(&host->tuning_timer);
3120 host->tuning_timer.data = (unsigned long)host;
3121 host->tuning_timer.function = sdhci_tuning_timer;
3122 }
3123
dace1453 3124 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 3125 mmc_hostname(mmc), host);
0fc81ee3
MB		 3126 if (ret) {
3127 pr_err("%s: Failed to request IRQ %d: %d\n",
3128 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3129 goto untasklet;
0fc81ee3 3130 }
d129bceb 3131
2f4cbb3d 3132 sdhci_init(host, 0);
d129bceb
PO		 3133
3134#ifdef CONFIG_MMC_DEBUG
3135 sdhci_dumpregs(host);
3136#endif
3137
f9134319 3138#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3139 snprintf(host->led_name, sizeof(host->led_name),
3140 "%s::", mmc_hostname(mmc));
3141 host->led.name = host->led_name;
2f730fec
PO		 3142 host->led.brightness = LED_OFF;
3143 host->led.default_trigger = mmc_hostname(mmc);
3144 host->led.brightness_set = sdhci_led_control;
3145
b8c86fc5 3146 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3147 if (ret) {
3148 pr_err("%s: Failed to register LED device: %d\n",
3149 mmc_hostname(mmc), ret);
2f730fec 3150 goto reset;
0fc81ee3 3151 }
2f730fec
PO		 3152#endif
3153
5f25a66f
PO		 3154 mmiowb();
3155
d129bceb
PO		 3156 mmc_add_host(mmc);
3157
a3c76eb9 3158 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3159 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3160 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3161 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3162
7260cf5e
AV		 3163 sdhci_enable_card_detection(host);
3164
d129bceb
PO		 3165 return 0;
3166
f9134319 3167#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3168reset:
3169 sdhci_reset(host, SDHCI_RESET_ALL);
b0a8dece 3170 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2f730fec
PO		 3171 free_irq(host->irq, host);
3172#endif
8ef1a143 3173untasklet:
d129bceb
PO		 3174 tasklet_kill(&host->card_tasklet);
3175 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3176
3177 return ret;
3178}
3179
b8c86fc5 3180EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3181
1e72859e 3182void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3183{
1e72859e
PO		 3184 unsigned long flags;
3185
3186 if (dead) {
3187 spin_lock_irqsave(&host->lock, flags);
3188
3189 host->flags |= SDHCI_DEVICE_DEAD;
3190
3191 if (host->mrq) {
a3c76eb9 3192 pr_err("%s: Controller removed during "
1e72859e
PO		 3193 " transfer!\n", mmc_hostname(host->mmc));
3194
3195 host->mrq->cmd->error = -ENOMEDIUM;
3196 tasklet_schedule(&host->finish_tasklet);
3197 }
3198
3199 spin_unlock_irqrestore(&host->lock, flags);
3200 }
3201
7260cf5e
AV		 3202 sdhci_disable_card_detection(host);
3203
b8c86fc5 3204 mmc_remove_host(host->mmc);
d129bceb 3205
f9134319 3206#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3207 led_classdev_unregister(&host->led);
3208#endif
3209
1e72859e
PO		 3210 if (!dead)
3211 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 3212
b0a8dece 3213 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
d129bceb
PO		 3214 free_irq(host->irq, host);
3215
3216 del_timer_sync(&host->timer);
3217
3218 tasklet_kill(&host->card_tasklet);
3219 tasklet_kill(&host->finish_tasklet);
2134a922 3220
77dcb3f4
PR		 3221 if (host->vmmc) {
3222 regulator_disable(host->vmmc);
9bea3c85 3223 regulator_put(host->vmmc);
77dcb3f4 3224 }
9bea3c85 3225
6231f3de
PR		 3226 if (host->vqmmc) {
3227 regulator_disable(host->vqmmc);
3228 regulator_put(host->vqmmc);
3229 }
3230
2134a922
PO		 3231 kfree(host->adma_desc);
3232 kfree(host->align_buffer);
3233
3234 host->adma_desc = NULL;
3235 host->align_buffer = NULL;
d129bceb
PO		 3236}
3237
b8c86fc5 3238EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3239
b8c86fc5 3240void sdhci_free_host(struct sdhci_host *host)
d129bceb 3241{
b8c86fc5 3242 mmc_free_host(host->mmc);
d129bceb
PO		 3243}
3244
b8c86fc5 3245EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3246
3247/*****************************************************************************\
3248 * *
3249 * Driver init/exit *
3250 * *
3251\*****************************************************************************/
3252
3253static int __init sdhci_drv_init(void)
3254{
a3c76eb9 3255 pr_info(DRIVER_NAME
52fbf9c9 3256 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3257 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3258
b8c86fc5 3259 return 0;
d129bceb
PO		 3260}
3261
3262static void __exit sdhci_drv_exit(void)
3263{
d129bceb
PO		 3264}
3265
3266module_init(sdhci_drv_init);
3267module_exit(sdhci_drv_exit);
3268
df673b22 3269module_param(debug_quirks, uint, 0444);
66fd8ad5 3270module_param(debug_quirks2, uint, 0444);
67435274 3271
32710e8f 3272MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3273MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3274MODULE_LICENSE("GPL");
67435274 3275
df673b22 3276MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3277MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
kernel source for telekom puls (alcatel/mediatek)