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mmc: core: Add option to prevent eMMC sleep command
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
d129bceb 30
d129bceb
PO		 31#include "sdhci.h"
32
33#define DRIVER_NAME "sdhci"
d129bceb 34
d129bceb 35#define DBG(f, x...) \
c6563178 36 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 37
f9134319
PO		 38#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
39 defined(CONFIG_MMC_SDHCI_MODULE))
40#define SDHCI_USE_LEDS_CLASS
41#endif
42
b513ea25
AN		 43#define MAX_TUNING_LOOP 40
44
df673b22 45static unsigned int debug_quirks = 0;
66fd8ad5 46static unsigned int debug_quirks2;
67435274 47
d129bceb
PO		 48static void sdhci_finish_data(struct sdhci_host *);
49
50static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
51static void sdhci_finish_command(struct sdhci_host *);
cf2b5eea
AN		 52static int sdhci_execute_tuning(struct mmc_host *mmc);
53static void sdhci_tuning_timer(unsigned long data);
d129bceb 54
66fd8ad5
AH		 55#ifdef CONFIG_PM_RUNTIME
56static int sdhci_runtime_pm_get(struct sdhci_host *host);
57static int sdhci_runtime_pm_put(struct sdhci_host *host);
58#else
59static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
60{
61 return 0;
62}
63static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
64{
65 return 0;
66}
67#endif
68
d129bceb
PO		 69static void sdhci_dumpregs(struct sdhci_host *host)
70{
a3c76eb9 71 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 72 mmc_hostname(host->mmc));
d129bceb 73
a3c76eb9 74 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 75 sdhci_readl(host, SDHCI_DMA_ADDRESS),
76 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 77 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 78 sdhci_readw(host, SDHCI_BLOCK_SIZE),
79 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 80 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 81 sdhci_readl(host, SDHCI_ARGUMENT),
82 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 83 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 84 sdhci_readl(host, SDHCI_PRESENT_STATE),
85 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 86 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 87 sdhci_readb(host, SDHCI_POWER_CONTROL),
88 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 89 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 90 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
91 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 92 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 93 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
94 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 95 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 96 sdhci_readl(host, SDHCI_INT_ENABLE),
97 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 98 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 99 sdhci_readw(host, SDHCI_ACMD12_ERR),
100 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 101 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 102 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 103 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 104 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 105 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 106 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 107 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 108 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 109
be3f4ae0 110 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 111 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 112 readl(host->ioaddr + SDHCI_ADMA_ERROR),
113 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
114
a3c76eb9 115 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 116}
117
118/*****************************************************************************\
119 * *
120 * Low level functions *
121 * *
122\*****************************************************************************/
123
7260cf5e
AV		 124static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
125{
126 u32 ier;
127
128 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
129 ier &= ~clear;
130 ier |= set;
131 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
132 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
133}
134
135static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
136{
137 sdhci_clear_set_irqs(host, 0, irqs);
138}
139
140static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
141{
142 sdhci_clear_set_irqs(host, irqs, 0);
143}
144
145static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
146{
d25928d1 147 u32 present, irqs;
7260cf5e 148
c79396c1 149 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
c79396c1 150 !mmc_card_is_removable(host->mmc))
66fd8ad5
AH		 151 return;
152
d25928d1
SG		 153 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
154 SDHCI_CARD_PRESENT;
155 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
156
7260cf5e
AV		 157 if (enable)
158 sdhci_unmask_irqs(host, irqs);
159 else
160 sdhci_mask_irqs(host, irqs);
161}
162
163static void sdhci_enable_card_detection(struct sdhci_host *host)
164{
165 sdhci_set_card_detection(host, true);
166}
167
168static void sdhci_disable_card_detection(struct sdhci_host *host)
169{
170 sdhci_set_card_detection(host, false);
171}
172
d129bceb
PO		 173static void sdhci_reset(struct sdhci_host *host, u8 mask)
174{
e16514d8 175 unsigned long timeout;
063a9dbb 176 u32 uninitialized_var(ier);
e16514d8 177
b8c86fc5 178 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 179 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 180 SDHCI_CARD_PRESENT))
181 return;
182 }
183
063a9dbb
AV		 184 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
185 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
186
393c1a34
PR		 187 if (host->ops->platform_reset_enter)
188 host->ops->platform_reset_enter(host, mask);
189
4e4141a5 190 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 191
e16514d8 192 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 193 host->clock = 0;
194
e16514d8
PO		 195 /* Wait max 100 ms */
196 timeout = 100;
197
198 /* hw clears the bit when it's done */
4e4141a5 199 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 200 if (timeout == 0) {
a3c76eb9 201 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 202 mmc_hostname(host->mmc), (int)mask);
203 sdhci_dumpregs(host);
204 return;
205 }
206 timeout--;
207 mdelay(1);
d129bceb 208 }
063a9dbb 209
393c1a34
PR		 210 if (host->ops->platform_reset_exit)
211 host->ops->platform_reset_exit(host, mask);
212
063a9dbb
AV		 213 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
214 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
d129bceb
PO		 215}
216
2f4cbb3d
NP		 217static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
218
219static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 220{
2f4cbb3d
NP		 221 if (soft)
222 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
223 else
224 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 225
7260cf5e
AV		 226 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
227 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 228 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
229 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 230 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 231
232 if (soft) {
233 /* force clock reconfiguration */
234 host->clock = 0;
235 sdhci_set_ios(host->mmc, &host->mmc->ios);
236 }
7260cf5e 237}
d129bceb 238
7260cf5e
AV		 239static void sdhci_reinit(struct sdhci_host *host)
240{
2f4cbb3d 241 sdhci_init(host, 0);
7260cf5e 242 sdhci_enable_card_detection(host);
d129bceb
PO		 243}
244
245static void sdhci_activate_led(struct sdhci_host *host)
246{
247 u8 ctrl;
248
4e4141a5 249 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 250 ctrl |= SDHCI_CTRL_LED;
4e4141a5 251 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 252}
253
254static void sdhci_deactivate_led(struct sdhci_host *host)
255{
256 u8 ctrl;
257
4e4141a5 258 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 259 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 260 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 261}
262
f9134319 263#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 264static void sdhci_led_control(struct led_classdev *led,
265 enum led_brightness brightness)
266{
267 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
268 unsigned long flags;
269
270 spin_lock_irqsave(&host->lock, flags);
271
66fd8ad5
AH		 272 if (host->runtime_suspended)
273 goto out;
274
2f730fec
PO		 275 if (brightness == LED_OFF)
276 sdhci_deactivate_led(host);
277 else
278 sdhci_activate_led(host);
66fd8ad5 279out:
2f730fec
PO		 280 spin_unlock_irqrestore(&host->lock, flags);
281}
282#endif
283
d129bceb
PO		 284/*****************************************************************************\
285 * *
286 * Core functions *
287 * *
288\*****************************************************************************/
289
a406f5a3 290static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 291{
7659150c
PO		 292 unsigned long flags;
293 size_t blksize, len, chunk;
7244b85b 294 u32 uninitialized_var(scratch);
7659150c 295 u8 *buf;
d129bceb 296
a406f5a3 297 DBG("PIO reading\n");
d129bceb 298
a406f5a3 299 blksize = host->data->blksz;
7659150c 300 chunk = 0;
d129bceb 301
7659150c 302 local_irq_save(flags);
d129bceb 303
a406f5a3 304 while (blksize) {
7659150c
PO		 305 if (!sg_miter_next(&host->sg_miter))
306 BUG();
d129bceb 307
7659150c 308 len = min(host->sg_miter.length, blksize);
d129bceb 309
7659150c
PO		 310 blksize -= len;
311 host->sg_miter.consumed = len;
14d836e7 312
7659150c 313 buf = host->sg_miter.addr;
d129bceb 314
7659150c
PO		 315 while (len) {
316 if (chunk == 0) {
4e4141a5 317 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 318 chunk = 4;
a406f5a3 319 }
7659150c
PO		 320
321 *buf = scratch & 0xFF;
322
323 buf++;
324 scratch >>= 8;
325 chunk--;
326 len--;
d129bceb 327 }
a406f5a3 328 }
7659150c
PO		 329
330 sg_miter_stop(&host->sg_miter);
331
332 local_irq_restore(flags);
a406f5a3 333}
d129bceb 334
a406f5a3
PO		 335static void sdhci_write_block_pio(struct sdhci_host *host)
336{
7659150c
PO		 337 unsigned long flags;
338 size_t blksize, len, chunk;
339 u32 scratch;
340 u8 *buf;
d129bceb 341
a406f5a3
PO		 342 DBG("PIO writing\n");
343
344 blksize = host->data->blksz;
7659150c
PO		 345 chunk = 0;
346 scratch = 0;
d129bceb 347
7659150c 348 local_irq_save(flags);
d129bceb 349
a406f5a3 350 while (blksize) {
7659150c
PO		 351 if (!sg_miter_next(&host->sg_miter))
352 BUG();
a406f5a3 353
7659150c
PO		 354 len = min(host->sg_miter.length, blksize);
355
356 blksize -= len;
357 host->sg_miter.consumed = len;
358
359 buf = host->sg_miter.addr;
d129bceb 360
7659150c
PO		 361 while (len) {
362 scratch |= (u32)*buf << (chunk * 8);
363
364 buf++;
365 chunk++;
366 len--;
367
368 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 369 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 370 chunk = 0;
371 scratch = 0;
d129bceb 372 }
d129bceb
PO		 373 }
374 }
7659150c
PO		 375
376 sg_miter_stop(&host->sg_miter);
377
378 local_irq_restore(flags);
a406f5a3
PO		 379}
380
381static void sdhci_transfer_pio(struct sdhci_host *host)
382{
383 u32 mask;
384
385 BUG_ON(!host->data);
386
7659150c 387 if (host->blocks == 0)
a406f5a3
PO		 388 return;
389
390 if (host->data->flags & MMC_DATA_READ)
391 mask = SDHCI_DATA_AVAILABLE;
392 else
393 mask = SDHCI_SPACE_AVAILABLE;
394
4a3cba32
PO		 395 /*
396 * Some controllers (JMicron JMB38x) mess up the buffer bits
397 * for transfers < 4 bytes. As long as it is just one block,
398 * we can ignore the bits.
399 */
400 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
401 (host->data->blocks == 1))
402 mask = ~0;
403
4e4141a5 404 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 405 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
406 udelay(100);
407
a406f5a3
PO		 408 if (host->data->flags & MMC_DATA_READ)
409 sdhci_read_block_pio(host);
410 else
411 sdhci_write_block_pio(host);
d129bceb 412
7659150c
PO		 413 host->blocks--;
414 if (host->blocks == 0)
a406f5a3 415 break;
a406f5a3 416 }
d129bceb 417
a406f5a3 418 DBG("PIO transfer complete.\n");
d129bceb
PO		 419}
420
2134a922
PO		 421static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
422{
423 local_irq_save(*flags);
482fce99 424 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 425}
426
427static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
428{
482fce99 429 kunmap_atomic(buffer);
2134a922
PO		 430 local_irq_restore(*flags);
431}
432
118cd17d
BD		 433static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
434{
9e506f35
BD		 435 __le32 *dataddr = (__le32 __force *)(desc + 4);
436 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 437
9e506f35
BD		 438 /* SDHCI specification says ADMA descriptors should be 4 byte
439 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 440
9e506f35
BD		 441 cmdlen[0] = cpu_to_le16(cmd);
442 cmdlen[1] = cpu_to_le16(len);
443
444 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 445}
446
8f1934ce 447static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 448 struct mmc_data *data)
449{
450 int direction;
451
452 u8 *desc;
453 u8 *align;
454 dma_addr_t addr;
455 dma_addr_t align_addr;
456 int len, offset;
457
458 struct scatterlist *sg;
459 int i;
460 char *buffer;
461 unsigned long flags;
462
463 /*
464 * The spec does not specify endianness of descriptor table.
465 * We currently guess that it is LE.
466 */
467
468 if (data->flags & MMC_DATA_READ)
469 direction = DMA_FROM_DEVICE;
470 else
471 direction = DMA_TO_DEVICE;
472
473 /*
474 * The ADMA descriptor table is mapped further down as we
475 * need to fill it with data first.
476 */
477
478 host->align_addr = dma_map_single(mmc_dev(host->mmc),
479 host->align_buffer, 128 * 4, direction);
8d8bb39b 480 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 481 goto fail;
2134a922
PO		 482 BUG_ON(host->align_addr & 0x3);
483
484 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
485 data->sg, data->sg_len, direction);
8f1934ce
PO		 486 if (host->sg_count == 0)
487 goto unmap_align;
2134a922
PO		 488
489 desc = host->adma_desc;
490 align = host->align_buffer;
491
492 align_addr = host->align_addr;
493
494 for_each_sg(data->sg, sg, host->sg_count, i) {
495 addr = sg_dma_address(sg);
496 len = sg_dma_len(sg);
497
498 /*
499 * The SDHCI specification states that ADMA
500 * addresses must be 32-bit aligned. If they
501 * aren't, then we use a bounce buffer for
502 * the (up to three) bytes that screw up the
503 * alignment.
504 */
505 offset = (4 - (addr & 0x3)) & 0x3;
506 if (offset) {
507 if (data->flags & MMC_DATA_WRITE) {
508 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 509 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 510 memcpy(align, buffer, offset);
511 sdhci_kunmap_atomic(buffer, &flags);
512 }
513
118cd17d
BD		 514 /* tran, valid */
515 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 516
517 BUG_ON(offset > 65536);
518
2134a922
PO		 519 align += 4;
520 align_addr += 4;
521
522 desc += 8;
523
524 addr += offset;
525 len -= offset;
526 }
527
2134a922
PO		 528 BUG_ON(len > 65536);
529
118cd17d
BD		 530 /* tran, valid */
531 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 532 desc += 8;
533
534 /*
535 * If this triggers then we have a calculation bug
536 * somewhere. :/
537 */
538 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
539 }
540
70764a90
TA		 541 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
542 /*
543 * Mark the last descriptor as the terminating descriptor
544 */
545 if (desc != host->adma_desc) {
546 desc -= 8;
547 desc[0] |= 0x2; /* end */
548 }
549 } else {
550 /*
551 * Add a terminating entry.
552 */
2134a922 553
70764a90
TA		 554 /* nop, end, valid */
555 sdhci_set_adma_desc(desc, 0, 0, 0x3);
556 }
2134a922
PO		 557
558 /*
559 * Resync align buffer as we might have changed it.
560 */
561 if (data->flags & MMC_DATA_WRITE) {
562 dma_sync_single_for_device(mmc_dev(host->mmc),
563 host->align_addr, 128 * 4, direction);
564 }
565
566 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
567 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 568 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 569 goto unmap_entries;
2134a922 570 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 571
572 return 0;
573
574unmap_entries:
575 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
576 data->sg_len, direction);
577unmap_align:
578 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
579 128 * 4, direction);
580fail:
581 return -EINVAL;
2134a922
PO		 582}
583
584static void sdhci_adma_table_post(struct sdhci_host *host,
585 struct mmc_data *data)
586{
587 int direction;
588
589 struct scatterlist *sg;
590 int i, size;
591 u8 *align;
592 char *buffer;
593 unsigned long flags;
594
595 if (data->flags & MMC_DATA_READ)
596 direction = DMA_FROM_DEVICE;
597 else
598 direction = DMA_TO_DEVICE;
599
600 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
601 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
602
603 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
604 128 * 4, direction);
605
606 if (data->flags & MMC_DATA_READ) {
607 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
608 data->sg_len, direction);
609
610 align = host->align_buffer;
611
612 for_each_sg(data->sg, sg, host->sg_count, i) {
613 if (sg_dma_address(sg) & 0x3) {
614 size = 4 - (sg_dma_address(sg) & 0x3);
615
616 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 617 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 618 memcpy(buffer, align, size);
619 sdhci_kunmap_atomic(buffer, &flags);
620
621 align += 4;
622 }
623 }
624 }
625
626 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
627 data->sg_len, direction);
628}
629
a3c7778f 630static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 631{
1c8cde92 632 u8 count;
a3c7778f 633 struct mmc_data *data = cmd->data;
1c8cde92 634 unsigned target_timeout, current_timeout;
d129bceb 635
ee53ab5d
PO		 636 /*
637 * If the host controller provides us with an incorrect timeout
638 * value, just skip the check and use 0xE. The hardware may take
639 * longer to time out, but that's much better than having a too-short
640 * timeout value.
641 */
11a2f1b7 642 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 643 return 0xE;
e538fbe8 644
a3c7778f
AW		 645 /* Unspecified timeout, assume max */
646 if (!data && !cmd->cmd_timeout_ms)
647 return 0xE;
d129bceb 648
a3c7778f
AW		 649 /* timeout in us */
650 if (!data)
651 target_timeout = cmd->cmd_timeout_ms * 1000;
78a2ca27
AS		 652 else {
653 target_timeout = data->timeout_ns / 1000;
654 if (host->clock)
655 target_timeout += data->timeout_clks / host->clock;
656 }
81b39802 657
1c8cde92
PO		 658 /*
659 * Figure out needed cycles.
660 * We do this in steps in order to fit inside a 32 bit int.
661 * The first step is the minimum timeout, which will have a
662 * minimum resolution of 6 bits:
663 * (1) 2^13*1000 > 2^22,
664 * (2) host->timeout_clk < 2^16
665 * =>
666 * (1) / (2) > 2^6
667 */
668 count = 0;
669 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
670 while (current_timeout < target_timeout) {
671 count++;
672 current_timeout <<= 1;
673 if (count >= 0xF)
674 break;
675 }
676
677 if (count >= 0xF) {
a3c76eb9 678 pr_warning("%s: Too large timeout requested for CMD%d!\n",
a3c7778f 679 mmc_hostname(host->mmc), cmd->opcode);
1c8cde92
PO		 680 count = 0xE;
681 }
682
ee53ab5d
PO		 683 return count;
684}
685
6aa943ab
AV		 686static void sdhci_set_transfer_irqs(struct sdhci_host *host)
687{
688 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
689 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
690
691 if (host->flags & SDHCI_REQ_USE_DMA)
692 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
693 else
694 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
695}
696
a3c7778f 697static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 698{
699 u8 count;
2134a922 700 u8 ctrl;
a3c7778f 701 struct mmc_data *data = cmd->data;
8f1934ce 702 int ret;
ee53ab5d
PO		 703
704 WARN_ON(host->data);
705
a3c7778f
AW		 706 if (data || (cmd->flags & MMC_RSP_BUSY)) {
707 count = sdhci_calc_timeout(host, cmd);
708 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
709 }
710
711 if (!data)
ee53ab5d
PO		 712 return;
713
714 /* Sanity checks */
715 BUG_ON(data->blksz * data->blocks > 524288);
716 BUG_ON(data->blksz > host->mmc->max_blk_size);
717 BUG_ON(data->blocks > 65535);
718
719 host->data = data;
720 host->data_early = 0;
f6a03cbf 721 host->data->bytes_xfered = 0;
ee53ab5d 722
a13abc7b 723 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 724 host->flags |= SDHCI_REQ_USE_DMA;
725
2134a922
PO		 726 /*
727 * FIXME: This doesn't account for merging when mapping the
728 * scatterlist.
729 */
730 if (host->flags & SDHCI_REQ_USE_DMA) {
731 int broken, i;
732 struct scatterlist *sg;
733
734 broken = 0;
735 if (host->flags & SDHCI_USE_ADMA) {
736 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
737 broken = 1;
738 } else {
739 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
740 broken = 1;
741 }
742
743 if (unlikely(broken)) {
744 for_each_sg(data->sg, sg, data->sg_len, i) {
745 if (sg->length & 0x3) {
746 DBG("Reverting to PIO because of "
747 "transfer size (%d)\n",
748 sg->length);
749 host->flags &= ~SDHCI_REQ_USE_DMA;
750 break;
751 }
752 }
753 }
c9fddbc4
PO		 754 }
755
756 /*
757 * The assumption here being that alignment is the same after
758 * translation to device address space.
759 */
2134a922
PO		 760 if (host->flags & SDHCI_REQ_USE_DMA) {
761 int broken, i;
762 struct scatterlist *sg;
763
764 broken = 0;
765 if (host->flags & SDHCI_USE_ADMA) {
766 /*
767 * As we use 3 byte chunks to work around
768 * alignment problems, we need to check this
769 * quirk.
770 */
771 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
772 broken = 1;
773 } else {
774 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
775 broken = 1;
776 }
777
778 if (unlikely(broken)) {
779 for_each_sg(data->sg, sg, data->sg_len, i) {
780 if (sg->offset & 0x3) {
781 DBG("Reverting to PIO because of "
782 "bad alignment\n");
783 host->flags &= ~SDHCI_REQ_USE_DMA;
784 break;
785 }
786 }
787 }
788 }
789
8f1934ce
PO		 790 if (host->flags & SDHCI_REQ_USE_DMA) {
791 if (host->flags & SDHCI_USE_ADMA) {
792 ret = sdhci_adma_table_pre(host, data);
793 if (ret) {
794 /*
795 * This only happens when someone fed
796 * us an invalid request.
797 */
798 WARN_ON(1);
ebd6d357 799 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 800 } else {
4e4141a5
AV		 801 sdhci_writel(host, host->adma_addr,
802 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 803 }
804 } else {
c8b3e02e 805 int sg_cnt;
8f1934ce 806
c8b3e02e 807 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 808 data->sg, data->sg_len,
809 (data->flags & MMC_DATA_READ) ?
810 DMA_FROM_DEVICE :
811 DMA_TO_DEVICE);
c8b3e02e 812 if (sg_cnt == 0) {
8f1934ce
PO		 813 /*
814 * This only happens when someone fed
815 * us an invalid request.
816 */
817 WARN_ON(1);
ebd6d357 818 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 819 } else {
719a61b4 820 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 821 sdhci_writel(host, sg_dma_address(data->sg),
822 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 823 }
824 }
825 }
826
2134a922
PO		 827 /*
828 * Always adjust the DMA selection as some controllers
829 * (e.g. JMicron) can't do PIO properly when the selection
830 * is ADMA.
831 */
832 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 833 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 834 ctrl &= ~SDHCI_CTRL_DMA_MASK;
835 if ((host->flags & SDHCI_REQ_USE_DMA) &&
836 (host->flags & SDHCI_USE_ADMA))
837 ctrl |= SDHCI_CTRL_ADMA32;
838 else
839 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 840 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 841 }
842
8f1934ce 843 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 844 int flags;
845
846 flags = SG_MITER_ATOMIC;
847 if (host->data->flags & MMC_DATA_READ)
848 flags |= SG_MITER_TO_SG;
849 else
850 flags |= SG_MITER_FROM_SG;
851 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 852 host->blocks = data->blocks;
d129bceb 853 }
c7fa9963 854
6aa943ab
AV		 855 sdhci_set_transfer_irqs(host);
856
f6a03cbf
MV		 857 /* Set the DMA boundary value and block size */
858 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
859 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 860 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 861}
862
863static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 864 struct mmc_command *cmd)
c7fa9963
PO		 865{
866 u16 mode;
e89d456f 867 struct mmc_data *data = cmd->data;
c7fa9963 868
c7fa9963
PO		 869 if (data == NULL)
870 return;
871
e538fbe8
PO		 872 WARN_ON(!host->data);
873
c7fa9963 874 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 875 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
876 mode |= SDHCI_TRNS_MULTI;
877 /*
878 * If we are sending CMD23, CMD12 never gets sent
879 * on successful completion (so no Auto-CMD12).
880 */
881 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
882 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 883 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
884 mode |= SDHCI_TRNS_AUTO_CMD23;
885 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
886 }
c4512f79 887 }
8edf6371 888
c7fa9963
PO		 889 if (data->flags & MMC_DATA_READ)
890 mode |= SDHCI_TRNS_READ;
c9fddbc4 891 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 892 mode |= SDHCI_TRNS_DMA;
893
4e4141a5 894 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 895}
896
897static void sdhci_finish_data(struct sdhci_host *host)
898{
899 struct mmc_data *data;
d129bceb
PO		 900
901 BUG_ON(!host->data);
902
903 data = host->data;
904 host->data = NULL;
905
c9fddbc4 906 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 907 if (host->flags & SDHCI_USE_ADMA)
908 sdhci_adma_table_post(host, data);
909 else {
910 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
911 data->sg_len, (data->flags & MMC_DATA_READ) ?
912 DMA_FROM_DEVICE : DMA_TO_DEVICE);
913 }
d129bceb
PO		 914 }
915
916 /*
c9b74c5b
PO		 917 * The specification states that the block count register must
918 * be updated, but it does not specify at what point in the
919 * data flow. That makes the register entirely useless to read
920 * back so we have to assume that nothing made it to the card
921 * in the event of an error.
d129bceb 922 */
c9b74c5b
PO		 923 if (data->error)
924 data->bytes_xfered = 0;
d129bceb 925 else
c9b74c5b 926 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 927
e89d456f
AW		 928 /*
929 * Need to send CMD12 if -
930 * a) open-ended multiblock transfer (no CMD23)
931 * b) error in multiblock transfer
932 */
933 if (data->stop &&
934 (data->error ||
935 !host->mrq->sbc)) {
936
d129bceb
PO		 937 /*
938 * The controller needs a reset of internal state machines
939 * upon error conditions.
940 */
17b0429d 941 if (data->error) {
d129bceb
PO		 942 sdhci_reset(host, SDHCI_RESET_CMD);
943 sdhci_reset(host, SDHCI_RESET_DATA);
944 }
945
946 sdhci_send_command(host, data->stop);
947 } else
948 tasklet_schedule(&host->finish_tasklet);
949}
950
951static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
952{
953 int flags;
fd2208d7 954 u32 mask;
7cb2c76f 955 unsigned long timeout;
d129bceb
PO		 956
957 WARN_ON(host->cmd);
958
d129bceb 959 /* Wait max 10 ms */
7cb2c76f 960 timeout = 10;
fd2208d7
PO		 961
962 mask = SDHCI_CMD_INHIBIT;
963 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
964 mask |= SDHCI_DATA_INHIBIT;
965
966 /* We shouldn't wait for data inihibit for stop commands, even
967 though they might use busy signaling */
968 if (host->mrq->data && (cmd == host->mrq->data->stop))
969 mask &= ~SDHCI_DATA_INHIBIT;
970
4e4141a5 971 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 972 if (timeout == 0) {
a3c76eb9 973 pr_err("%s: Controller never released "
acf1da45 974 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 975 sdhci_dumpregs(host);
17b0429d 976 cmd->error = -EIO;
d129bceb
PO		 977 tasklet_schedule(&host->finish_tasklet);
978 return;
979 }
7cb2c76f
PO		 980 timeout--;
981 mdelay(1);
982 }
d129bceb
PO		 983
984 mod_timer(&host->timer, jiffies + 10 * HZ);
985
986 host->cmd = cmd;
987
a3c7778f 988 sdhci_prepare_data(host, cmd);
d129bceb 989
4e4141a5 990 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 991
e89d456f 992 sdhci_set_transfer_mode(host, cmd);
c7fa9963 993
d129bceb 994 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 995 pr_err("%s: Unsupported response type!\n",
d129bceb 996 mmc_hostname(host->mmc));
17b0429d 997 cmd->error = -EINVAL;
d129bceb
PO		 998 tasklet_schedule(&host->finish_tasklet);
999 return;
1000 }
1001
1002 if (!(cmd->flags & MMC_RSP_PRESENT))
1003 flags = SDHCI_CMD_RESP_NONE;
1004 else if (cmd->flags & MMC_RSP_136)
1005 flags = SDHCI_CMD_RESP_LONG;
1006 else if (cmd->flags & MMC_RSP_BUSY)
1007 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1008 else
1009 flags = SDHCI_CMD_RESP_SHORT;
1010
1011 if (cmd->flags & MMC_RSP_CRC)
1012 flags |= SDHCI_CMD_CRC;
1013 if (cmd->flags & MMC_RSP_OPCODE)
1014 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1015
1016 /* CMD19 is special in that the Data Present Select should be set */
1017 if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
d129bceb
PO		 1018 flags |= SDHCI_CMD_DATA;
1019
4e4141a5 1020 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 1021}
1022
1023static void sdhci_finish_command(struct sdhci_host *host)
1024{
1025 int i;
1026
1027 BUG_ON(host->cmd == NULL);
1028
1029 if (host->cmd->flags & MMC_RSP_PRESENT) {
1030 if (host->cmd->flags & MMC_RSP_136) {
1031 /* CRC is stripped so we need to do some shifting. */
1032 for (i = 0;i < 4;i++) {
4e4141a5 1033 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1034 SDHCI_RESPONSE + (3-i)*4) << 8;
1035 if (i != 3)
1036 host->cmd->resp[i] |=
4e4141a5 1037 sdhci_readb(host,
d129bceb
PO		 1038 SDHCI_RESPONSE + (3-i)*4-1);
1039 }
1040 } else {
4e4141a5 1041 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1042 }
1043 }
1044
17b0429d 1045 host->cmd->error = 0;
d129bceb 1046
e89d456f
AW		 1047 /* Finished CMD23, now send actual command. */
1048 if (host->cmd == host->mrq->sbc) {
1049 host->cmd = NULL;
1050 sdhci_send_command(host, host->mrq->cmd);
1051 } else {
e538fbe8 1052
e89d456f
AW		 1053 /* Processed actual command. */
1054 if (host->data && host->data_early)
1055 sdhci_finish_data(host);
d129bceb 1056
e89d456f
AW		 1057 if (!host->cmd->data)
1058 tasklet_schedule(&host->finish_tasklet);
1059
1060 host->cmd = NULL;
1061 }
d129bceb
PO		 1062}
1063
1064static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1065{
c3ed3877 1066 int div = 0; /* Initialized for compiler warning */
df16219f 1067 int real_div = div, clk_mul = 1;
c3ed3877 1068 u16 clk = 0;
7cb2c76f 1069 unsigned long timeout;
d129bceb 1070
30832ab5 1071 if (clock && clock == host->clock)
d129bceb
PO		 1072 return;
1073
df16219f
GC		 1074 host->mmc->actual_clock = 0;
1075
8114634c
AV		 1076 if (host->ops->set_clock) {
1077 host->ops->set_clock(host, clock);
1078 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1079 return;
1080 }
1081
4e4141a5 1082 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1083
1084 if (clock == 0)
1085 goto out;
1086
85105c53 1087 if (host->version >= SDHCI_SPEC_300) {
c3ed3877
AN		 1088 /*
1089 * Check if the Host Controller supports Programmable Clock
1090 * Mode.
1091 */
1092 if (host->clk_mul) {
1093 u16 ctrl;
1094
1095 /*
1096 * We need to figure out whether the Host Driver needs
1097 * to select Programmable Clock Mode, or the value can
1098 * be set automatically by the Host Controller based on
1099 * the Preset Value registers.
1100 */
1101 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1102 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1103 for (div = 1; div <= 1024; div++) {
1104 if (((host->max_clk * host->clk_mul) /
1105 div) <= clock)
1106 break;
1107 }
1108 /*
1109 * Set Programmable Clock Mode in the Clock
1110 * Control register.
1111 */
1112 clk = SDHCI_PROG_CLOCK_MODE;
df16219f
GC		 1113 real_div = div;
1114 clk_mul = host->clk_mul;
c3ed3877
AN		 1115 div--;
1116 }
1117 } else {
1118 /* Version 3.00 divisors must be a multiple of 2. */
1119 if (host->max_clk <= clock)
1120 div = 1;
1121 else {
1122 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1123 div += 2) {
1124 if ((host->max_clk / div) <= clock)
1125 break;
1126 }
85105c53 1127 }
df16219f 1128 real_div = div;
c3ed3877 1129 div >>= 1;
85105c53
ZG		 1130 }
1131 } else {
1132 /* Version 2.00 divisors must be a power of 2. */
0397526d 1133 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1134 if ((host->max_clk / div) <= clock)
1135 break;
1136 }
df16219f 1137 real_div = div;
c3ed3877 1138 div >>= 1;
d129bceb 1139 }
d129bceb 1140
df16219f
GC		 1141 if (real_div)
1142 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1143
c3ed3877 1144 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1145 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1146 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1147 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1148 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1149
27f6cb16
CB		 1150 /* Wait max 20 ms */
1151 timeout = 20;
4e4141a5 1152 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1153 & SDHCI_CLOCK_INT_STABLE)) {
1154 if (timeout == 0) {
a3c76eb9 1155 pr_err("%s: Internal clock never "
acf1da45 1156 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1157 sdhci_dumpregs(host);
1158 return;
1159 }
7cb2c76f
PO		 1160 timeout--;
1161 mdelay(1);
1162 }
d129bceb
PO		 1163
1164 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1165 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1166
1167out:
1168 host->clock = clock;
1169}
1170
ceb6143b 1171static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1172{
8364248a 1173 u8 pwr = 0;
146ad66e 1174
8364248a 1175 if (power != (unsigned short)-1) {
ae628903
PO		 1176 switch (1 << power) {
1177 case MMC_VDD_165_195:
1178 pwr = SDHCI_POWER_180;
1179 break;
1180 case MMC_VDD_29_30:
1181 case MMC_VDD_30_31:
1182 pwr = SDHCI_POWER_300;
1183 break;
1184 case MMC_VDD_32_33:
1185 case MMC_VDD_33_34:
1186 pwr = SDHCI_POWER_330;
1187 break;
1188 default:
1189 BUG();
1190 }
1191 }
1192
1193 if (host->pwr == pwr)
ceb6143b 1194 return -1;
146ad66e 1195
ae628903
PO		 1196 host->pwr = pwr;
1197
1198 if (pwr == 0) {
4e4141a5 1199 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ceb6143b 1200 return 0;
9e9dc5f2
DS		 1201 }
1202
1203 /*
1204 * Spec says that we should clear the power reg before setting
1205 * a new value. Some controllers don't seem to like this though.
1206 */
b8c86fc5 1207 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1208 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1209
e08c1694 1210 /*
c71f6512 1211 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1212 * and set turn on power at the same time, so set the voltage first.
1213 */
11a2f1b7 1214 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1215 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1216
ae628903 1217 pwr |= SDHCI_POWER_ON;
146ad66e 1218
ae628903 1219 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1220
1221 /*
1222 * Some controllers need an extra 10ms delay of 10ms before they
1223 * can apply clock after applying power
1224 */
11a2f1b7 1225 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1226 mdelay(10);
ceb6143b
AH		 1227
1228 return power;
146ad66e
PO		 1229}
1230
d129bceb
PO		 1231/*****************************************************************************\
1232 * *
1233 * MMC callbacks *
1234 * *
1235\*****************************************************************************/
1236
1237static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1238{
1239 struct sdhci_host *host;
68d1fb7e 1240 bool present;
d129bceb
PO		 1241 unsigned long flags;
1242
1243 host = mmc_priv(mmc);
1244
66fd8ad5
AH		 1245 sdhci_runtime_pm_get(host);
1246
d129bceb
PO		 1247 spin_lock_irqsave(&host->lock, flags);
1248
1249 WARN_ON(host->mrq != NULL);
1250
f9134319 1251#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1252 sdhci_activate_led(host);
2f730fec 1253#endif
e89d456f
AW		 1254
1255 /*
1256 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1257 * requests if Auto-CMD12 is enabled.
1258 */
1259 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1260 if (mrq->stop) {
1261 mrq->data->stop = NULL;
1262 mrq->stop = NULL;
1263 }
1264 }
d129bceb
PO		 1265
1266 host->mrq = mrq;
1267
68d1fb7e
AV		 1268 /* If polling, assume that the card is always present. */
1269 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1270 present = true;
1271 else
1272 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1273 SDHCI_CARD_PRESENT;
1274
1275 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1276 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1277 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1278 } else {
1279 u32 present_state;
1280
1281 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1282 /*
1283 * Check if the re-tuning timer has already expired and there
1284 * is no on-going data transfer. If so, we need to execute
1285 * tuning procedure before sending command.
1286 */
1287 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1288 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1289 spin_unlock_irqrestore(&host->lock, flags);
1290 sdhci_execute_tuning(mmc);
1291 spin_lock_irqsave(&host->lock, flags);
1292
1293 /* Restore original mmc_request structure */
1294 host->mrq = mrq;
1295 }
1296
8edf6371 1297 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1298 sdhci_send_command(host, mrq->sbc);
1299 else
1300 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1301 }
d129bceb 1302
5f25a66f 1303 mmiowb();
d129bceb
PO		 1304 spin_unlock_irqrestore(&host->lock, flags);
1305}
1306
66fd8ad5 1307static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1308{
d129bceb 1309 unsigned long flags;
ceb6143b 1310 int vdd_bit = -1;
d129bceb
PO		 1311 u8 ctrl;
1312
d129bceb
PO		 1313 spin_lock_irqsave(&host->lock, flags);
1314
ceb6143b
AH		 1315 if (host->flags & SDHCI_DEVICE_DEAD) {
1316 spin_unlock_irqrestore(&host->lock, flags);
1317 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1318 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1319 return;
1320 }
1e72859e 1321
d129bceb
PO		 1322 /*
1323 * Reset the chip on each power off.
1324 * Should clear out any weird states.
1325 */
1326 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1327 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1328 sdhci_reinit(host);
d129bceb
PO		 1329 }
1330
1331 sdhci_set_clock(host, ios->clock);
1332
1333 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1334 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1335 else
ceb6143b
AH		 1336 vdd_bit = sdhci_set_power(host, ios->vdd);
1337
1338 if (host->vmmc && vdd_bit != -1) {
1339 spin_unlock_irqrestore(&host->lock, flags);
1340 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1341 spin_lock_irqsave(&host->lock, flags);
1342 }
d129bceb 1343
643a81ff
PR		 1344 if (host->ops->platform_send_init_74_clocks)
1345 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1346
15ec4461
PR		 1347 /*
1348 * If your platform has 8-bit width support but is not a v3 controller,
1349 * or if it requires special setup code, you should implement that in
1350 * platform_8bit_width().
1351 */
1352 if (host->ops->platform_8bit_width)
1353 host->ops->platform_8bit_width(host, ios->bus_width);
1354 else {
1355 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1356 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1357 ctrl &= ~SDHCI_CTRL_4BITBUS;
1358 if (host->version >= SDHCI_SPEC_300)
1359 ctrl |= SDHCI_CTRL_8BITBUS;
1360 } else {
1361 if (host->version >= SDHCI_SPEC_300)
1362 ctrl &= ~SDHCI_CTRL_8BITBUS;
1363 if (ios->bus_width == MMC_BUS_WIDTH_4)
1364 ctrl |= SDHCI_CTRL_4BITBUS;
1365 else
1366 ctrl &= ~SDHCI_CTRL_4BITBUS;
1367 }
1368 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1369 }
ae6d6c92 1370
15ec4461 1371 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1372
3ab9c8da
PR		 1373 if ((ios->timing == MMC_TIMING_SD_HS ||
1374 ios->timing == MMC_TIMING_MMC_HS)
1375 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1376 ctrl |= SDHCI_CTRL_HISPD;
1377 else
1378 ctrl &= ~SDHCI_CTRL_HISPD;
1379
d6d50a15 1380 if (host->version >= SDHCI_SPEC_300) {
49c468fc
AN		 1381 u16 clk, ctrl_2;
1382 unsigned int clock;
1383
1384 /* In case of UHS-I modes, set High Speed Enable */
1385 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1386 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1387 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1388 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1389 (ios->timing == MMC_TIMING_UHS_SDR12))
1390 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1391
1392 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1393 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1394 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1395 /*
1396 * We only need to set Driver Strength if the
1397 * preset value enable is not set.
1398 */
1399 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1400 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1401 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1402 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1403 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1404
1405 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1406 } else {
1407 /*
1408 * According to SDHC Spec v3.00, if the Preset Value
1409 * Enable in the Host Control 2 register is set, we
1410 * need to reset SD Clock Enable before changing High
1411 * Speed Enable to avoid generating clock gliches.
1412 */
758535c4
AN		 1413
1414 /* Reset SD Clock Enable */
1415 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1416 clk &= ~SDHCI_CLOCK_CARD_EN;
1417 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1418
1419 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1420
1421 /* Re-enable SD Clock */
1422 clock = host->clock;
1423 host->clock = 0;
1424 sdhci_set_clock(host, clock);
d6d50a15 1425 }
49c468fc 1426
49c468fc
AN		 1427
1428 /* Reset SD Clock Enable */
1429 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1430 clk &= ~SDHCI_CLOCK_CARD_EN;
1431 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1432
6322cdd0
PR		 1433 if (host->ops->set_uhs_signaling)
1434 host->ops->set_uhs_signaling(host, ios->timing);
1435 else {
1436 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1437 /* Select Bus Speed Mode for host */
1438 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1439 if (ios->timing == MMC_TIMING_UHS_SDR12)
1440 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1441 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1442 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1443 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1444 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1445 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1446 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1447 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1448 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1449 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1450 }
49c468fc
AN		 1451
1452 /* Re-enable SD Clock */
1453 clock = host->clock;
1454 host->clock = 0;
1455 sdhci_set_clock(host, clock);
758535c4
AN		 1456 } else
1457 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1458
b8352260
LD		 1459 /*
1460 * Some (ENE) controllers go apeshit on some ios operation,
1461 * signalling timeout and CRC errors even on CMD0. Resetting
1462 * it on each ios seems to solve the problem.
1463 */
b8c86fc5 1464 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1465 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1466
5f25a66f 1467 mmiowb();
d129bceb
PO		 1468 spin_unlock_irqrestore(&host->lock, flags);
1469}
1470
66fd8ad5
AH		 1471static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1472{
1473 struct sdhci_host *host = mmc_priv(mmc);
1474
1475 sdhci_runtime_pm_get(host);
1476 sdhci_do_set_ios(host, ios);
1477 sdhci_runtime_pm_put(host);
1478}
1479
1480static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1481{
d129bceb 1482 unsigned long flags;
2dfb579c 1483 int is_readonly;
d129bceb 1484
d129bceb
PO		 1485 spin_lock_irqsave(&host->lock, flags);
1486
1e72859e 1487 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1488 is_readonly = 0;
1489 else if (host->ops->get_ro)
1490 is_readonly = host->ops->get_ro(host);
1e72859e 1491 else
2dfb579c
WS		 1492 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1493 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1494
1495 spin_unlock_irqrestore(&host->lock, flags);
1496
2dfb579c
WS		 1497 /* This quirk needs to be replaced by a callback-function later */
1498 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1499 !is_readonly : is_readonly;
d129bceb
PO		 1500}
1501
82b0e23a
TI		 1502#define SAMPLE_COUNT 5
1503
66fd8ad5 1504static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1505{
82b0e23a
TI		 1506 int i, ro_count;
1507
82b0e23a 1508 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1509 return sdhci_check_ro(host);
82b0e23a
TI		 1510
1511 ro_count = 0;
1512 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1513 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1514 if (++ro_count > SAMPLE_COUNT / 2)
1515 return 1;
1516 }
1517 msleep(30);
1518 }
1519 return 0;
1520}
1521
20758b66
AH		 1522static void sdhci_hw_reset(struct mmc_host *mmc)
1523{
1524 struct sdhci_host *host = mmc_priv(mmc);
1525
1526 if (host->ops && host->ops->hw_reset)
1527 host->ops->hw_reset(host);
1528}
1529
66fd8ad5 1530static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1531{
66fd8ad5
AH		 1532 struct sdhci_host *host = mmc_priv(mmc);
1533 int ret;
f75979b7 1534
66fd8ad5
AH		 1535 sdhci_runtime_pm_get(host);
1536 ret = sdhci_do_get_ro(host);
1537 sdhci_runtime_pm_put(host);
1538 return ret;
1539}
f75979b7 1540
66fd8ad5
AH		 1541static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1542{
1e72859e
PO		 1543 if (host->flags & SDHCI_DEVICE_DEAD)
1544 goto out;
1545
66fd8ad5
AH		 1546 if (enable)
1547 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1548 else
1549 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1550
1551 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1552 if (host->runtime_suspended)
1553 goto out;
1554
f75979b7 1555 if (enable)
7260cf5e
AV		 1556 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1557 else
1558 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1559out:
f75979b7 1560 mmiowb();
66fd8ad5
AH		 1561}
1562
1563static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1564{
1565 struct sdhci_host *host = mmc_priv(mmc);
1566 unsigned long flags;
f75979b7 1567
66fd8ad5
AH		 1568 spin_lock_irqsave(&host->lock, flags);
1569 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1570 spin_unlock_irqrestore(&host->lock, flags);
1571}
1572
66fd8ad5
AH		 1573static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1574 struct mmc_ios *ios)
f2119df6 1575{
f2119df6
AN		 1576 u8 pwr;
1577 u16 clk, ctrl;
1578 u32 present_state;
1579
f2119df6
AN		 1580 /*
1581 * Signal Voltage Switching is only applicable for Host Controllers
1582 * v3.00 and above.
1583 */
1584 if (host->version < SDHCI_SPEC_300)
1585 return 0;
1586
1587 /*
1588 * We first check whether the request is to set signalling voltage
1589 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1590 */
1591 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1592 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1593 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1594 ctrl &= ~SDHCI_CTRL_VDD_180;
1595 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1596
1597 /* Wait for 5ms */
1598 usleep_range(5000, 5500);
1599
1600 /* 3.3V regulator output should be stable within 5 ms */
1601 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1602 if (!(ctrl & SDHCI_CTRL_VDD_180))
1603 return 0;
1604 else {
a3c76eb9 1605 pr_info(DRIVER_NAME ": Switching to 3.3V "
f2119df6
AN		 1606 "signalling voltage failed\n");
1607 return -EIO;
1608 }
1609 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1610 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1611 /* Stop SDCLK */
1612 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1613 clk &= ~SDHCI_CLOCK_CARD_EN;
1614 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1615
1616 /* Check whether DAT[3:0] is 0000 */
1617 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1618 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1619 SDHCI_DATA_LVL_SHIFT)) {
1620 /*
1621 * Enable 1.8V Signal Enable in the Host Control2
1622 * register
1623 */
1624 ctrl |= SDHCI_CTRL_VDD_180;
1625 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1626
1627 /* Wait for 5ms */
1628 usleep_range(5000, 5500);
1629
1630 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1631 if (ctrl & SDHCI_CTRL_VDD_180) {
1632 /* Provide SDCLK again and wait for 1ms*/
1633 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1634 clk |= SDHCI_CLOCK_CARD_EN;
1635 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1636 usleep_range(1000, 1500);
1637
1638 /*
1639 * If DAT[3:0] level is 1111b, then the card
1640 * was successfully switched to 1.8V signaling.
1641 */
1642 present_state = sdhci_readl(host,
1643 SDHCI_PRESENT_STATE);
1644 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1645 SDHCI_DATA_LVL_MASK)
1646 return 0;
1647 }
1648 }
1649
1650 /*
1651 * If we are here, that means the switch to 1.8V signaling
1652 * failed. We power cycle the card, and retry initialization
1653 * sequence by setting S18R to 0.
1654 */
1655 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1656 pwr &= ~SDHCI_POWER_ON;
1657 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1658
1659 /* Wait for 1ms as per the spec */
1660 usleep_range(1000, 1500);
1661 pwr |= SDHCI_POWER_ON;
1662 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1663
a3c76eb9 1664 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
f2119df6
AN		 1665 "voltage failed, retrying with S18R set to 0\n");
1666 return -EAGAIN;
1667 } else
1668 /* No signal voltage switch required */
1669 return 0;
1670}
1671
66fd8ad5
AH		 1672static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1673 struct mmc_ios *ios)
1674{
1675 struct sdhci_host *host = mmc_priv(mmc);
1676 int err;
1677
1678 if (host->version < SDHCI_SPEC_300)
1679 return 0;
1680 sdhci_runtime_pm_get(host);
1681 err = sdhci_do_start_signal_voltage_switch(host, ios);
1682 sdhci_runtime_pm_put(host);
1683 return err;
1684}
1685
b513ea25
AN		 1686static int sdhci_execute_tuning(struct mmc_host *mmc)
1687{
1688 struct sdhci_host *host;
1689 u16 ctrl;
1690 u32 ier;
1691 int tuning_loop_counter = MAX_TUNING_LOOP;
1692 unsigned long timeout;
1693 int err = 0;
1694
1695 host = mmc_priv(mmc);
1696
66fd8ad5 1697 sdhci_runtime_pm_get(host);
b513ea25
AN		 1698 disable_irq(host->irq);
1699 spin_lock(&host->lock);
1700
1701 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1702
1703 /*
1704 * Host Controller needs tuning only in case of SDR104 mode
1705 * and for SDR50 mode when Use Tuning for SDR50 is set in
1706 * Capabilities register.
1707 */
1708 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1709 (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1710 (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1711 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1712 else {
1713 spin_unlock(&host->lock);
1714 enable_irq(host->irq);
66fd8ad5 1715 sdhci_runtime_pm_put(host);
b513ea25
AN		 1716 return 0;
1717 }
1718
1719 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1720
1721 /*
1722 * As per the Host Controller spec v3.00, tuning command
1723 * generates Buffer Read Ready interrupt, so enable that.
1724 *
1725 * Note: The spec clearly says that when tuning sequence
1726 * is being performed, the controller does not generate
1727 * interrupts other than Buffer Read Ready interrupt. But
1728 * to make sure we don't hit a controller bug, we _only_
1729 * enable Buffer Read Ready interrupt here.
1730 */
1731 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1732 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1733
1734 /*
1735 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1736 * of loops reaches 40 times or a timeout of 150ms occurs.
1737 */
1738 timeout = 150;
1739 do {
1740 struct mmc_command cmd = {0};
66fd8ad5 1741 struct mmc_request mrq = {NULL};
b513ea25
AN		 1742
1743 if (!tuning_loop_counter && !timeout)
1744 break;
1745
1746 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1747 cmd.arg = 0;
1748 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1749 cmd.retries = 0;
1750 cmd.data = NULL;
1751 cmd.error = 0;
1752
1753 mrq.cmd = &cmd;
1754 host->mrq = &mrq;
1755
1756 /*
1757 * In response to CMD19, the card sends 64 bytes of tuning
1758 * block to the Host Controller. So we set the block size
1759 * to 64 here.
1760 */
1761 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1762
1763 /*
1764 * The tuning block is sent by the card to the host controller.
1765 * So we set the TRNS_READ bit in the Transfer Mode register.
1766 * This also takes care of setting DMA Enable and Multi Block
1767 * Select in the same register to 0.
1768 */
1769 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1770
1771 sdhci_send_command(host, &cmd);
1772
1773 host->cmd = NULL;
1774 host->mrq = NULL;
1775
1776 spin_unlock(&host->lock);
1777 enable_irq(host->irq);
1778
1779 /* Wait for Buffer Read Ready interrupt */
1780 wait_event_interruptible_timeout(host->buf_ready_int,
1781 (host->tuning_done == 1),
1782 msecs_to_jiffies(50));
1783 disable_irq(host->irq);
1784 spin_lock(&host->lock);
1785
1786 if (!host->tuning_done) {
a3c76eb9 1787 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1788 "Buffer Read Ready interrupt during tuning "
1789 "procedure, falling back to fixed sampling "
1790 "clock\n");
1791 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1792 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1793 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1794 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1795
1796 err = -EIO;
1797 goto out;
1798 }
1799
1800 host->tuning_done = 0;
1801
1802 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1803 tuning_loop_counter--;
1804 timeout--;
1805 mdelay(1);
1806 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1807
1808 /*
1809 * The Host Driver has exhausted the maximum number of loops allowed,
1810 * so use fixed sampling frequency.
1811 */
1812 if (!tuning_loop_counter || !timeout) {
1813 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1814 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1815 } else {
1816 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1817 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1818 " failed, falling back to fixed sampling"
1819 " clock\n");
1820 err = -EIO;
1821 }
1822 }
1823
1824out:
cf2b5eea
AN		 1825 /*
1826 * If this is the very first time we are here, we start the retuning
1827 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1828 * flag won't be set, we check this condition before actually starting
1829 * the timer.
1830 */
1831 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1832 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1833 mod_timer(&host->tuning_timer, jiffies +
1834 host->tuning_count * HZ);
1835 /* Tuning mode 1 limits the maximum data length to 4MB */
1836 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1837 } else {
1838 host->flags &= ~SDHCI_NEEDS_RETUNING;
1839 /* Reload the new initial value for timer */
1840 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1841 mod_timer(&host->tuning_timer, jiffies +
1842 host->tuning_count * HZ);
1843 }
1844
1845 /*
1846 * In case tuning fails, host controllers which support re-tuning can
1847 * try tuning again at a later time, when the re-tuning timer expires.
1848 * So for these controllers, we return 0. Since there might be other
1849 * controllers who do not have this capability, we return error for
1850 * them.
1851 */
1852 if (err && host->tuning_count &&
1853 host->tuning_mode == SDHCI_TUNING_MODE_1)
1854 err = 0;
1855
b513ea25
AN		 1856 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1857 spin_unlock(&host->lock);
1858 enable_irq(host->irq);
66fd8ad5 1859 sdhci_runtime_pm_put(host);
b513ea25
AN		 1860
1861 return err;
1862}
1863
66fd8ad5 1864static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 1865{
4d55c5a1
AN		 1866 u16 ctrl;
1867 unsigned long flags;
1868
4d55c5a1
AN		 1869 /* Host Controller v3.00 defines preset value registers */
1870 if (host->version < SDHCI_SPEC_300)
1871 return;
1872
1873 spin_lock_irqsave(&host->lock, flags);
1874
1875 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1876
1877 /*
1878 * We only enable or disable Preset Value if they are not already
1879 * enabled or disabled respectively. Otherwise, we bail out.
1880 */
1881 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1882 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1883 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 1884 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 1885 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1886 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1887 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 1888 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1
AN		 1889 }
1890
1891 spin_unlock_irqrestore(&host->lock, flags);
1892}
1893
66fd8ad5
AH		 1894static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1895{
1896 struct sdhci_host *host = mmc_priv(mmc);
1897
1898 sdhci_runtime_pm_get(host);
1899 sdhci_do_enable_preset_value(host, enable);
1900 sdhci_runtime_pm_put(host);
1901}
1902
ab7aefd0 1903static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1904 .request = sdhci_request,
1905 .set_ios = sdhci_set_ios,
1906 .get_ro = sdhci_get_ro,
20758b66 1907 .hw_reset = sdhci_hw_reset,
f75979b7 1908 .enable_sdio_irq = sdhci_enable_sdio_irq,
f2119df6 1909 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b513ea25 1910 .execute_tuning = sdhci_execute_tuning,
4d55c5a1 1911 .enable_preset_value = sdhci_enable_preset_value,
d129bceb
PO		 1912};
1913
1914/*****************************************************************************\
1915 * *
1916 * Tasklets *
1917 * *
1918\*****************************************************************************/
1919
1920static void sdhci_tasklet_card(unsigned long param)
1921{
1922 struct sdhci_host *host;
1923 unsigned long flags;
1924
1925 host = (struct sdhci_host*)param;
1926
1927 spin_lock_irqsave(&host->lock, flags);
1928
66fd8ad5
AH		 1929 /* Check host->mrq first in case we are runtime suspended */
1930 if (host->mrq &&
1931 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
a3c76eb9 1932 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 1933 mmc_hostname(host->mmc));
a3c76eb9 1934 pr_err("%s: Resetting controller.\n",
66fd8ad5 1935 mmc_hostname(host->mmc));
d129bceb 1936
66fd8ad5
AH		 1937 sdhci_reset(host, SDHCI_RESET_CMD);
1938 sdhci_reset(host, SDHCI_RESET_DATA);
d129bceb 1939
66fd8ad5
AH		 1940 host->mrq->cmd->error = -ENOMEDIUM;
1941 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 1942 }
1943
1944 spin_unlock_irqrestore(&host->lock, flags);
1945
04cf585d 1946 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1947}
1948
1949static void sdhci_tasklet_finish(unsigned long param)
1950{
1951 struct sdhci_host *host;
1952 unsigned long flags;
1953 struct mmc_request *mrq;
1954
1955 host = (struct sdhci_host*)param;
1956
66fd8ad5
AH		 1957 spin_lock_irqsave(&host->lock, flags);
1958
0c9c99a7
CB		 1959 /*
1960 * If this tasklet gets rescheduled while running, it will
1961 * be run again afterwards but without any active request.
1962 */
66fd8ad5
AH		 1963 if (!host->mrq) {
1964 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 1965 return;
66fd8ad5 1966 }
d129bceb
PO		 1967
1968 del_timer(&host->timer);
1969
1970 mrq = host->mrq;
1971
d129bceb
PO		 1972 /*
1973 * The controller needs a reset of internal state machines
1974 * upon error conditions.
1975 */
1e72859e 1976 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 1977 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 1978 (mrq->data && (mrq->data->error ||
1979 (mrq->data->stop && mrq->data->stop->error))) ||
1980 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1981
1982 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1983 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1984 unsigned int clock;
1985
1986 /* This is to force an update */
1987 clock = host->clock;
1988 host->clock = 0;
1989 sdhci_set_clock(host, clock);
1990 }
1991
1992 /* Spec says we should do both at the same time, but Ricoh
1993 controllers do not like that. */
d129bceb
PO		 1994 sdhci_reset(host, SDHCI_RESET_CMD);
1995 sdhci_reset(host, SDHCI_RESET_DATA);
1996 }
1997
1998 host->mrq = NULL;
1999 host->cmd = NULL;
2000 host->data = NULL;
2001
f9134319 2002#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2003 sdhci_deactivate_led(host);
2f730fec 2004#endif
d129bceb 2005
5f25a66f 2006 mmiowb();
d129bceb
PO		 2007 spin_unlock_irqrestore(&host->lock, flags);
2008
2009 mmc_request_done(host->mmc, mrq);
66fd8ad5 2010 sdhci_runtime_pm_put(host);
d129bceb
PO		 2011}
2012
2013static void sdhci_timeout_timer(unsigned long data)
2014{
2015 struct sdhci_host *host;
2016 unsigned long flags;
2017
2018 host = (struct sdhci_host*)data;
2019
2020 spin_lock_irqsave(&host->lock, flags);
2021
2022 if (host->mrq) {
a3c76eb9 2023 pr_err("%s: Timeout waiting for hardware "
acf1da45 2024 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2025 sdhci_dumpregs(host);
2026
2027 if (host->data) {
17b0429d 2028 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2029 sdhci_finish_data(host);
2030 } else {
2031 if (host->cmd)
17b0429d 2032 host->cmd->error = -ETIMEDOUT;
d129bceb 2033 else
17b0429d 2034 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2035
2036 tasklet_schedule(&host->finish_tasklet);
2037 }
2038 }
2039
5f25a66f 2040 mmiowb();
d129bceb
PO		 2041 spin_unlock_irqrestore(&host->lock, flags);
2042}
2043
cf2b5eea
AN		 2044static void sdhci_tuning_timer(unsigned long data)
2045{
2046 struct sdhci_host *host;
2047 unsigned long flags;
2048
2049 host = (struct sdhci_host *)data;
2050
2051 spin_lock_irqsave(&host->lock, flags);
2052
2053 host->flags |= SDHCI_NEEDS_RETUNING;
2054
2055 spin_unlock_irqrestore(&host->lock, flags);
2056}
2057
d129bceb
PO		 2058/*****************************************************************************\
2059 * *
2060 * Interrupt handling *
2061 * *
2062\*****************************************************************************/
2063
2064static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2065{
2066 BUG_ON(intmask == 0);
2067
2068 if (!host->cmd) {
a3c76eb9 2069 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2070 "though no command operation was in progress.\n",
2071 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2072 sdhci_dumpregs(host);
2073 return;
2074 }
2075
43b58b36 2076 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2077 host->cmd->error = -ETIMEDOUT;
2078 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2079 SDHCI_INT_INDEX))
2080 host->cmd->error = -EILSEQ;
43b58b36 2081
e809517f 2082 if (host->cmd->error) {
d129bceb 2083 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2084 return;
2085 }
2086
2087 /*
2088 * The host can send and interrupt when the busy state has
2089 * ended, allowing us to wait without wasting CPU cycles.
2090 * Unfortunately this is overloaded on the "data complete"
2091 * interrupt, so we need to take some care when handling
2092 * it.
2093 *
2094 * Note: The 1.0 specification is a bit ambiguous about this
2095 * feature so there might be some problems with older
2096 * controllers.
2097 */
2098 if (host->cmd->flags & MMC_RSP_BUSY) {
2099 if (host->cmd->data)
2100 DBG("Cannot wait for busy signal when also "
2101 "doing a data transfer");
f945405c 2102 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2103 return;
f945405c
BD		 2104
2105 /* The controller does not support the end-of-busy IRQ,
2106 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2107 }
2108
2109 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2110 sdhci_finish_command(host);
d129bceb
PO		 2111}
2112
0957c333 2113#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2114static void sdhci_show_adma_error(struct sdhci_host *host)
2115{
2116 const char *name = mmc_hostname(host->mmc);
2117 u8 *desc = host->adma_desc;
2118 __le32 *dma;
2119 __le16 *len;
2120 u8 attr;
2121
2122 sdhci_dumpregs(host);
2123
2124 while (true) {
2125 dma = (__le32 *)(desc + 4);
2126 len = (__le16 *)(desc + 2);
2127 attr = *desc;
2128
2129 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2130 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2131
2132 desc += 8;
2133
2134 if (attr & 2)
2135 break;
2136 }
2137}
2138#else
2139static void sdhci_show_adma_error(struct sdhci_host *host) { }
2140#endif
2141
d129bceb
PO		 2142static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2143{
2144 BUG_ON(intmask == 0);
2145
b513ea25
AN		 2146 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2147 if (intmask & SDHCI_INT_DATA_AVAIL) {
2148 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2149 MMC_SEND_TUNING_BLOCK) {
2150 host->tuning_done = 1;
2151 wake_up(&host->buf_ready_int);
2152 return;
2153 }
2154 }
2155
d129bceb
PO		 2156 if (!host->data) {
2157 /*
e809517f
PO		 2158 * The "data complete" interrupt is also used to
2159 * indicate that a busy state has ended. See comment
2160 * above in sdhci_cmd_irq().
d129bceb 2161 */
e809517f
PO		 2162 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2163 if (intmask & SDHCI_INT_DATA_END) {
2164 sdhci_finish_command(host);
2165 return;
2166 }
2167 }
d129bceb 2168
a3c76eb9 2169 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2170 "though no data operation was in progress.\n",
2171 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2172 sdhci_dumpregs(host);
2173
2174 return;
2175 }
2176
2177 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2178 host->data->error = -ETIMEDOUT;
22113efd
AL		 2179 else if (intmask & SDHCI_INT_DATA_END_BIT)
2180 host->data->error = -EILSEQ;
2181 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2182 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2183 != MMC_BUS_TEST_R)
17b0429d 2184 host->data->error = -EILSEQ;
6882a8c0 2185 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2186 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2187 sdhci_show_adma_error(host);
2134a922 2188 host->data->error = -EIO;
6882a8c0 2189 }
d129bceb 2190
17b0429d 2191 if (host->data->error)
d129bceb
PO		 2192 sdhci_finish_data(host);
2193 else {
a406f5a3 2194 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2195 sdhci_transfer_pio(host);
2196
6ba736a1
PO		 2197 /*
2198 * We currently don't do anything fancy with DMA
2199 * boundaries, but as we can't disable the feature
2200 * we need to at least restart the transfer.
f6a03cbf
MV		 2201 *
2202 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2203 * should return a valid address to continue from, but as
2204 * some controllers are faulty, don't trust them.
6ba736a1 2205 */
f6a03cbf
MV		 2206 if (intmask & SDHCI_INT_DMA_END) {
2207 u32 dmastart, dmanow;
2208 dmastart = sg_dma_address(host->data->sg);
2209 dmanow = dmastart + host->data->bytes_xfered;
2210 /*
2211 * Force update to the next DMA block boundary.
2212 */
2213 dmanow = (dmanow &
2214 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2215 SDHCI_DEFAULT_BOUNDARY_SIZE;
2216 host->data->bytes_xfered = dmanow - dmastart;
2217 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2218 " next 0x%08x\n",
2219 mmc_hostname(host->mmc), dmastart,
2220 host->data->bytes_xfered, dmanow);
2221 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2222 }
6ba736a1 2223
e538fbe8
PO		 2224 if (intmask & SDHCI_INT_DATA_END) {
2225 if (host->cmd) {
2226 /*
2227 * Data managed to finish before the
2228 * command completed. Make sure we do
2229 * things in the proper order.
2230 */
2231 host->data_early = 1;
2232 } else {
2233 sdhci_finish_data(host);
2234 }
2235 }
d129bceb
PO		 2236 }
2237}
2238
7d12e780 2239static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2240{
2241 irqreturn_t result;
66fd8ad5 2242 struct sdhci_host *host = dev_id;
d129bceb 2243 u32 intmask;
f75979b7 2244 int cardint = 0;
d129bceb
PO		 2245
2246 spin_lock(&host->lock);
2247
66fd8ad5
AH		 2248 if (host->runtime_suspended) {
2249 spin_unlock(&host->lock);
a3c76eb9 2250 pr_warning("%s: got irq while runtime suspended\n",
66fd8ad5
AH		 2251 mmc_hostname(host->mmc));
2252 return IRQ_HANDLED;
2253 }
2254
4e4141a5 2255 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2256
62df67a5 2257 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2258 result = IRQ_NONE;
2259 goto out;
2260 }
2261
b69c9058
PO		 2262 DBG("*** %s got interrupt: 0x%08x\n",
2263 mmc_hostname(host->mmc), intmask);
d129bceb 2264
3192a28f 2265 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d25928d1
SG		 2266 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2267 SDHCI_CARD_PRESENT;
2268
2269 /*
2270 * There is a observation on i.mx esdhc. INSERT bit will be
2271 * immediately set again when it gets cleared, if a card is
2272 * inserted. We have to mask the irq to prevent interrupt
2273 * storm which will freeze the system. And the REMOVE gets
2274 * the same situation.
2275 *
2276 * More testing are needed here to ensure it works for other
2277 * platforms though.
2278 */
2279 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2280 SDHCI_INT_CARD_REMOVE);
2281 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2282 SDHCI_INT_CARD_INSERT);
2283
4e4141a5 2284 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
d25928d1
SG		 2285 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2286 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2287 tasklet_schedule(&host->card_tasklet);
3192a28f 2288 }
d129bceb 2289
3192a28f 2290 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2291 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2292 SDHCI_INT_STATUS);
3192a28f 2293 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2294 }
2295
2296 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2297 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2298 SDHCI_INT_STATUS);
3192a28f 2299 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2300 }
2301
2302 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2303
964f9ce2
PO		 2304 intmask &= ~SDHCI_INT_ERROR;
2305
d129bceb 2306 if (intmask & SDHCI_INT_BUS_POWER) {
a3c76eb9 2307 pr_err("%s: Card is consuming too much power!\n",
d129bceb 2308 mmc_hostname(host->mmc));
4e4141a5 2309 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2310 }
2311
9d26a5d3 2312 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2313
f75979b7
PO		 2314 if (intmask & SDHCI_INT_CARD_INT)
2315 cardint = 1;
2316
2317 intmask &= ~SDHCI_INT_CARD_INT;
2318
3192a28f 2319 if (intmask) {
a3c76eb9 2320 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3192a28f 2321 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 2322 sdhci_dumpregs(host);
2323
4e4141a5 2324 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2325 }
d129bceb
PO		 2326
2327 result = IRQ_HANDLED;
2328
5f25a66f 2329 mmiowb();
d129bceb
PO		 2330out:
2331 spin_unlock(&host->lock);
2332
f75979b7
PO		 2333 /*
2334 * We have to delay this as it calls back into the driver.
2335 */
2336 if (cardint)
2337 mmc_signal_sdio_irq(host->mmc);
2338
d129bceb
PO		 2339 return result;
2340}
2341
2342/*****************************************************************************\
2343 * *
2344 * Suspend/resume *
2345 * *
2346\*****************************************************************************/
2347
2348#ifdef CONFIG_PM
2349
29495aa0 2350int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2351{
b8c86fc5 2352 int ret;
a715dfc7 2353
7260cf5e
AV		 2354 sdhci_disable_card_detection(host);
2355
cf2b5eea
AN		 2356 /* Disable tuning since we are suspending */
2357 if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2358 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2359 host->flags &= ~SDHCI_NEEDS_RETUNING;
2360 mod_timer(&host->tuning_timer, jiffies +
2361 host->tuning_count * HZ);
2362 }
2363
1a13f8fa 2364 ret = mmc_suspend_host(host->mmc);
b8c86fc5
PO		 2365 if (ret)
2366 return ret;
a715dfc7 2367
b8c86fc5 2368 free_irq(host->irq, host);
d129bceb 2369
9bea3c85 2370 return ret;
d129bceb
PO		 2371}
2372
b8c86fc5 2373EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2374
b8c86fc5
PO		 2375int sdhci_resume_host(struct sdhci_host *host)
2376{
2377 int ret;
d129bceb 2378
a13abc7b 2379 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2380 if (host->ops->enable_dma)
2381 host->ops->enable_dma(host);
2382 }
d129bceb 2383
b8c86fc5
PO		 2384 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2385 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 2386 if (ret)
2387 return ret;
d129bceb 2388
2f4cbb3d 2389 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
b8c86fc5
PO		 2390 mmiowb();
2391
2392 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2393 sdhci_enable_card_detection(host);
2394
cf2b5eea
AN		 2395 /* Set the re-tuning expiration flag */
2396 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2397 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2398 host->flags |= SDHCI_NEEDS_RETUNING;
2399
2f4cbb3d 2400 return ret;
d129bceb
PO		 2401}
2402
b8c86fc5 2403EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb 2404
5f619704
DD		 2405void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2406{
2407 u8 val;
2408 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2409 val |= SDHCI_WAKE_ON_INT;
2410 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2411}
2412
2413EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2414
d129bceb
PO		 2415#endif /* CONFIG_PM */
2416
66fd8ad5
AH		 2417#ifdef CONFIG_PM_RUNTIME
2418
2419static int sdhci_runtime_pm_get(struct sdhci_host *host)
2420{
2421 return pm_runtime_get_sync(host->mmc->parent);
2422}
2423
2424static int sdhci_runtime_pm_put(struct sdhci_host *host)
2425{
2426 pm_runtime_mark_last_busy(host->mmc->parent);
2427 return pm_runtime_put_autosuspend(host->mmc->parent);
2428}
2429
2430int sdhci_runtime_suspend_host(struct sdhci_host *host)
2431{
2432 unsigned long flags;
2433 int ret = 0;
2434
2435 /* Disable tuning since we are suspending */
2436 if (host->version >= SDHCI_SPEC_300 &&
2437 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2438 del_timer_sync(&host->tuning_timer);
2439 host->flags &= ~SDHCI_NEEDS_RETUNING;
2440 }
2441
2442 spin_lock_irqsave(&host->lock, flags);
2443 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2444 spin_unlock_irqrestore(&host->lock, flags);
2445
2446 synchronize_irq(host->irq);
2447
2448 spin_lock_irqsave(&host->lock, flags);
2449 host->runtime_suspended = true;
2450 spin_unlock_irqrestore(&host->lock, flags);
2451
2452 return ret;
2453}
2454EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2455
2456int sdhci_runtime_resume_host(struct sdhci_host *host)
2457{
2458 unsigned long flags;
2459 int ret = 0, host_flags = host->flags;
2460
2461 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2462 if (host->ops->enable_dma)
2463 host->ops->enable_dma(host);
2464 }
2465
2466 sdhci_init(host, 0);
2467
2468 /* Force clock and power re-program */
2469 host->pwr = 0;
2470 host->clock = 0;
2471 sdhci_do_set_ios(host, &host->mmc->ios);
2472
2473 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2474 if (host_flags & SDHCI_PV_ENABLED)
2475 sdhci_do_enable_preset_value(host, true);
2476
2477 /* Set the re-tuning expiration flag */
2478 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2479 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2480 host->flags |= SDHCI_NEEDS_RETUNING;
2481
2482 spin_lock_irqsave(&host->lock, flags);
2483
2484 host->runtime_suspended = false;
2485
2486 /* Enable SDIO IRQ */
2487 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2488 sdhci_enable_sdio_irq_nolock(host, true);
2489
2490 /* Enable Card Detection */
2491 sdhci_enable_card_detection(host);
2492
2493 spin_unlock_irqrestore(&host->lock, flags);
2494
2495 return ret;
2496}
2497EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2498
2499#endif
2500
d129bceb
PO		 2501/*****************************************************************************\
2502 * *
b8c86fc5 2503 * Device allocation/registration *
d129bceb
PO		 2504 * *
2505\*****************************************************************************/
2506
b8c86fc5
PO		 2507struct sdhci_host *sdhci_alloc_host(struct device *dev,
2508 size_t priv_size)
d129bceb 2509{
d129bceb
PO		 2510 struct mmc_host *mmc;
2511 struct sdhci_host *host;
2512
b8c86fc5 2513 WARN_ON(dev == NULL);
d129bceb 2514
b8c86fc5 2515 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2516 if (!mmc)
b8c86fc5 2517 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2518
2519 host = mmc_priv(mmc);
2520 host->mmc = mmc;
2521
b8c86fc5
PO		 2522 return host;
2523}
8a4da143 2524
b8c86fc5 2525EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2526
b8c86fc5
PO		 2527int sdhci_add_host(struct sdhci_host *host)
2528{
2529 struct mmc_host *mmc;
f2119df6
AN		 2530 u32 caps[2];
2531 u32 max_current_caps;
2532 unsigned int ocr_avail;
b8c86fc5 2533 int ret;
d129bceb 2534
b8c86fc5
PO		 2535 WARN_ON(host == NULL);
2536 if (host == NULL)
2537 return -EINVAL;
d129bceb 2538
b8c86fc5 2539 mmc = host->mmc;
d129bceb 2540
b8c86fc5
PO		 2541 if (debug_quirks)
2542 host->quirks = debug_quirks;
66fd8ad5
AH		 2543 if (debug_quirks2)
2544 host->quirks2 = debug_quirks2;
d129bceb 2545
d96649ed
PO		 2546 sdhci_reset(host, SDHCI_RESET_ALL);
2547
4e4141a5 2548 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2549 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2550 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2551 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2552 pr_err("%s: Unknown controller version (%d). "
b69c9058 2553 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2554 host->version);
4a965505
PO		 2555 }
2556
f2119df6 2557 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2558 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2559
f2119df6
AN		 2560 caps[1] = (host->version >= SDHCI_SPEC_300) ?
2561 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2562
b8c86fc5 2563 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2564 host->flags |= SDHCI_USE_SDMA;
f2119df6 2565 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2566 DBG("Controller doesn't have SDMA capability\n");
67435274 2567 else
a13abc7b 2568 host->flags |= SDHCI_USE_SDMA;
d129bceb 2569
b8c86fc5 2570 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2571 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2572 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2573 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2574 }
2575
f2119df6
AN		 2576 if ((host->version >= SDHCI_SPEC_200) &&
2577 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2578 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2579
2580 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2581 (host->flags & SDHCI_USE_ADMA)) {
2582 DBG("Disabling ADMA as it is marked broken\n");
2583 host->flags &= ~SDHCI_USE_ADMA;
2584 }
2585
a13abc7b 2586 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2587 if (host->ops->enable_dma) {
2588 if (host->ops->enable_dma(host)) {
a3c76eb9 2589 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2590 "available. Falling back to PIO.\n",
2591 mmc_hostname(mmc));
a13abc7b
RR		 2592 host->flags &=
2593 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2594 }
d129bceb
PO		 2595 }
2596 }
2597
2134a922
PO		 2598 if (host->flags & SDHCI_USE_ADMA) {
2599 /*
2600 * We need to allocate descriptors for all sg entries
2601 * (128) and potentially one alignment transfer for
2602 * each of those entries.
2603 */
2604 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2605 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2606 if (!host->adma_desc || !host->align_buffer) {
2607 kfree(host->adma_desc);
2608 kfree(host->align_buffer);
a3c76eb9 2609 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2610 "buffers. Falling back to standard DMA.\n",
2611 mmc_hostname(mmc));
2612 host->flags &= ~SDHCI_USE_ADMA;
2613 }
2614 }
2615
7659150c
PO		 2616 /*
2617 * If we use DMA, then it's up to the caller to set the DMA
2618 * mask, but PIO does not need the hw shim so we set a new
2619 * mask here in that case.
2620 */
a13abc7b 2621 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2622 host->dma_mask = DMA_BIT_MASK(64);
2623 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2624 }
d129bceb 2625
c4687d5f 2626 if (host->version >= SDHCI_SPEC_300)
f2119df6 2627 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2628 >> SDHCI_CLOCK_BASE_SHIFT;
2629 else
f2119df6 2630 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2631 >> SDHCI_CLOCK_BASE_SHIFT;
2632
4240ff0a 2633 host->max_clk *= 1000000;
f27f47ef
AV		 2634 if (host->max_clk == 0 || host->quirks &
2635 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2636 if (!host->ops->get_max_clock) {
a3c76eb9 2637 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2638 "frequency.\n", mmc_hostname(mmc));
2639 return -ENODEV;
2640 }
2641 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2642 }
d129bceb 2643
c3ed3877
AN		 2644 /*
2645 * In case of Host Controller v3.00, find out whether clock
2646 * multiplier is supported.
2647 */
2648 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2649 SDHCI_CLOCK_MUL_SHIFT;
2650
2651 /*
2652 * In case the value in Clock Multiplier is 0, then programmable
2653 * clock mode is not supported, otherwise the actual clock
2654 * multiplier is one more than the value of Clock Multiplier
2655 * in the Capabilities Register.
2656 */
2657 if (host->clk_mul)
2658 host->clk_mul += 1;
2659
d129bceb
PO		 2660 /*
2661 * Set host parameters.
2662 */
2663 mmc->ops = &sdhci_ops;
c3ed3877 2664 mmc->f_max = host->max_clk;
ce5f036b 2665 if (host->ops->get_min_clock)
a9e58f25 2666 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2667 else if (host->version >= SDHCI_SPEC_300) {
2668 if (host->clk_mul) {
2669 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2670 mmc->f_max = host->max_clk * host->clk_mul;
2671 } else
2672 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2673 } else
0397526d 2674 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2675
272308ca
AS		 2676 host->timeout_clk =
2677 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2678 if (host->timeout_clk == 0) {
2679 if (host->ops->get_timeout_clock) {
2680 host->timeout_clk = host->ops->get_timeout_clock(host);
2681 } else if (!(host->quirks &
2682 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2683 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2684 "frequency.\n", mmc_hostname(mmc));
2685 return -ENODEV;
2686 }
2687 }
2688 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2689 host->timeout_clk *= 1000;
2690
2691 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2692 host->timeout_clk = mmc->f_max / 1000;
272308ca 2693
65be3fef 2694 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
58d1246d 2695
e89d456f
AW		 2696 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2697
2698 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2699 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2700
8edf6371 2701 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2702 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2703 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2704 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2705 host->flags |= SDHCI_AUTO_CMD23;
2706 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2707 } else {
2708 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2709 }
2710
15ec4461
PR		 2711 /*
2712 * A controller may support 8-bit width, but the board itself
2713 * might not have the pins brought out. Boards that support
2714 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2715 * their platform code before calling sdhci_add_host(), and we
2716 * won't assume 8-bit width for hosts without that CAP.
2717 */
5fe23c7f 2718 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2719 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2720
f2119df6 2721 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2722 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2723
176d1ed4
JC		 2724 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2725 mmc_card_is_removable(mmc))
68d1fb7e
AV		 2726 mmc->caps |= MMC_CAP_NEEDS_POLL;
2727
f2119df6
AN		 2728 /* UHS-I mode(s) supported by the host controller. */
2729 if (host->version >= SDHCI_SPEC_300)
2730 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2731
2732 /* SDR104 supports also implies SDR50 support */
2733 if (caps[1] & SDHCI_SUPPORT_SDR104)
2734 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2735 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2736 mmc->caps |= MMC_CAP_UHS_SDR50;
2737
2738 if (caps[1] & SDHCI_SUPPORT_DDR50)
2739 mmc->caps |= MMC_CAP_UHS_DDR50;
2740
b513ea25
AN		 2741 /* Does the host needs tuning for SDR50? */
2742 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2743 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2744
d6d50a15
AN		 2745 /* Driver Type(s) (A, C, D) supported by the host */
2746 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2747 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2748 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2749 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2750 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2751 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2752
bec8726a
G		 2753 /*
2754 * If Power Off Notify capability is enabled by the host,
2755 * set notify to short power off notify timeout value.
2756 */
2757 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2758 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2759 else
2760 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2761
cf2b5eea
AN		 2762 /* Initial value for re-tuning timer count */
2763 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2764 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2765
2766 /*
2767 * In case Re-tuning Timer is not disabled, the actual value of
2768 * re-tuning timer will be 2 ^ (n - 1).
2769 */
2770 if (host->tuning_count)
2771 host->tuning_count = 1 << (host->tuning_count - 1);
2772
2773 /* Re-tuning mode supported by the Host Controller */
2774 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2775 SDHCI_RETUNING_MODE_SHIFT;
2776
8f230f45 2777 ocr_avail = 0;
f2119df6
AN		 2778 /*
2779 * According to SD Host Controller spec v3.00, if the Host System
2780 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2781 * the value is meaningful only if Voltage Support in the Capabilities
2782 * register is set. The actual current value is 4 times the register
2783 * value.
2784 */
2785 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2786
2787 if (caps[0] & SDHCI_CAN_VDD_330) {
2788 int max_current_330;
2789
8f230f45 2790 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6
AN		 2791
2792 max_current_330 = ((max_current_caps &
2793 SDHCI_MAX_CURRENT_330_MASK) >>
2794 SDHCI_MAX_CURRENT_330_SHIFT) *
2795 SDHCI_MAX_CURRENT_MULTIPLIER;
2796
2797 if (max_current_330 > 150)
2798 mmc->caps |= MMC_CAP_SET_XPC_330;
2799 }
2800 if (caps[0] & SDHCI_CAN_VDD_300) {
2801 int max_current_300;
2802
8f230f45 2803 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6
AN		 2804
2805 max_current_300 = ((max_current_caps &
2806 SDHCI_MAX_CURRENT_300_MASK) >>
2807 SDHCI_MAX_CURRENT_300_SHIFT) *
2808 SDHCI_MAX_CURRENT_MULTIPLIER;
2809
2810 if (max_current_300 > 150)
2811 mmc->caps |= MMC_CAP_SET_XPC_300;
2812 }
2813 if (caps[0] & SDHCI_CAN_VDD_180) {
2814 int max_current_180;
2815
8f230f45
TI		 2816 ocr_avail |= MMC_VDD_165_195;
2817
f2119df6
AN		 2818 max_current_180 = ((max_current_caps &
2819 SDHCI_MAX_CURRENT_180_MASK) >>
2820 SDHCI_MAX_CURRENT_180_SHIFT) *
2821 SDHCI_MAX_CURRENT_MULTIPLIER;
2822
2823 if (max_current_180 > 150)
2824 mmc->caps |= MMC_CAP_SET_XPC_180;
5371c927
AN		 2825
2826 /* Maximum current capabilities of the host at 1.8V */
2827 if (max_current_180 >= 800)
2828 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2829 else if (max_current_180 >= 600)
2830 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2831 else if (max_current_180 >= 400)
2832 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2833 else
2834 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
f2119df6
AN		 2835 }
2836
8f230f45
TI		 2837 mmc->ocr_avail = ocr_avail;
2838 mmc->ocr_avail_sdio = ocr_avail;
2839 if (host->ocr_avail_sdio)
2840 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2841 mmc->ocr_avail_sd = ocr_avail;
2842 if (host->ocr_avail_sd)
2843 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2844 else /* normal SD controllers don't support 1.8V */
2845 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2846 mmc->ocr_avail_mmc = ocr_avail;
2847 if (host->ocr_avail_mmc)
2848 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 2849
2850 if (mmc->ocr_avail == 0) {
a3c76eb9 2851 pr_err("%s: Hardware doesn't report any "
b69c9058 2852 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 2853 return -ENODEV;
146ad66e
PO		 2854 }
2855
d129bceb
PO		 2856 spin_lock_init(&host->lock);
2857
2858 /*
2134a922
PO		 2859 * Maximum number of segments. Depends on if the hardware
2860 * can do scatter/gather or not.
d129bceb 2861 */
2134a922 2862 if (host->flags & SDHCI_USE_ADMA)
a36274e0 2863 mmc->max_segs = 128;
a13abc7b 2864 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 2865 mmc->max_segs = 1;
2134a922 2866 else /* PIO */
a36274e0 2867 mmc->max_segs = 128;
d129bceb
PO		 2868
2869 /*
bab76961 2870 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 2871 * size (512KiB).
d129bceb 2872 */
55db890a 2873 mmc->max_req_size = 524288;
d129bceb
PO		 2874
2875 /*
2876 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 2877 * of bytes. When doing hardware scatter/gather, each entry cannot
2878 * be larger than 64 KiB though.
d129bceb 2879 */
30652aa3
OJ		 2880 if (host->flags & SDHCI_USE_ADMA) {
2881 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2882 mmc->max_seg_size = 65535;
2883 else
2884 mmc->max_seg_size = 65536;
2885 } else {
2134a922 2886 mmc->max_seg_size = mmc->max_req_size;
30652aa3 2887 }
d129bceb 2888
fe4a3c7a
PO		 2889 /*
2890 * Maximum block size. This varies from controller to controller and
2891 * is specified in the capabilities register.
2892 */
0633f654
AV		 2893 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2894 mmc->max_blk_size = 2;
2895 } else {
f2119df6 2896 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 2897 SDHCI_MAX_BLOCK_SHIFT;
2898 if (mmc->max_blk_size >= 3) {
a3c76eb9 2899 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 2900 "assuming 512 bytes\n", mmc_hostname(mmc));
2901 mmc->max_blk_size = 0;
2902 }
2903 }
2904
2905 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 2906
55db890a
PO		 2907 /*
2908 * Maximum block count.
2909 */
1388eefd 2910 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 2911
d129bceb
PO		 2912 /*
2913 * Init tasklets.
2914 */
2915 tasklet_init(&host->card_tasklet,
2916 sdhci_tasklet_card, (unsigned long)host);
2917 tasklet_init(&host->finish_tasklet,
2918 sdhci_tasklet_finish, (unsigned long)host);
2919
e4cad1b5 2920 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 2921
cf2b5eea 2922 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 2923 init_waitqueue_head(&host->buf_ready_int);
2924
cf2b5eea
AN		 2925 /* Initialize re-tuning timer */
2926 init_timer(&host->tuning_timer);
2927 host->tuning_timer.data = (unsigned long)host;
2928 host->tuning_timer.function = sdhci_tuning_timer;
2929 }
2930
dace1453 2931 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 2932 mmc_hostname(mmc), host);
d129bceb 2933 if (ret)
8ef1a143 2934 goto untasklet;
d129bceb 2935
9bea3c85
MS		 2936 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2937 if (IS_ERR(host->vmmc)) {
a3c76eb9 2938 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
9bea3c85 2939 host->vmmc = NULL;
9bea3c85
MS		 2940 }
2941
2f4cbb3d 2942 sdhci_init(host, 0);
d129bceb
PO		 2943
2944#ifdef CONFIG_MMC_DEBUG
2945 sdhci_dumpregs(host);
2946#endif
2947
f9134319 2948#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 2949 snprintf(host->led_name, sizeof(host->led_name),
2950 "%s::", mmc_hostname(mmc));
2951 host->led.name = host->led_name;
2f730fec
PO		 2952 host->led.brightness = LED_OFF;
2953 host->led.default_trigger = mmc_hostname(mmc);
2954 host->led.brightness_set = sdhci_led_control;
2955
b8c86fc5 2956 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 2957 if (ret)
2958 goto reset;
2959#endif
2960
5f25a66f
PO		 2961 mmiowb();
2962
d129bceb
PO		 2963 mmc_add_host(mmc);
2964
a3c76eb9 2965 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 2966 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 2967 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2968 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 2969
7260cf5e
AV		 2970 sdhci_enable_card_detection(host);
2971
d129bceb
PO		 2972 return 0;
2973
f9134319 2974#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2975reset:
2976 sdhci_reset(host, SDHCI_RESET_ALL);
2977 free_irq(host->irq, host);
2978#endif
8ef1a143 2979untasklet:
d129bceb
PO		 2980 tasklet_kill(&host->card_tasklet);
2981 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 2982
2983 return ret;
2984}
2985
b8c86fc5 2986EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 2987
1e72859e 2988void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 2989{
1e72859e
PO		 2990 unsigned long flags;
2991
2992 if (dead) {
2993 spin_lock_irqsave(&host->lock, flags);
2994
2995 host->flags |= SDHCI_DEVICE_DEAD;
2996
2997 if (host->mrq) {
a3c76eb9 2998 pr_err("%s: Controller removed during "
1e72859e
PO		 2999 " transfer!\n", mmc_hostname(host->mmc));
3000
3001 host->mrq->cmd->error = -ENOMEDIUM;
3002 tasklet_schedule(&host->finish_tasklet);
3003 }
3004
3005 spin_unlock_irqrestore(&host->lock, flags);
3006 }
3007
7260cf5e
AV		 3008 sdhci_disable_card_detection(host);
3009
b8c86fc5 3010 mmc_remove_host(host->mmc);
d129bceb 3011
f9134319 3012#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3013 led_classdev_unregister(&host->led);
3014#endif
3015
1e72859e
PO		 3016 if (!dead)
3017 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 3018
3019 free_irq(host->irq, host);
3020
3021 del_timer_sync(&host->timer);
cf2b5eea
AN		 3022 if (host->version >= SDHCI_SPEC_300)
3023 del_timer_sync(&host->tuning_timer);
d129bceb
PO		 3024
3025 tasklet_kill(&host->card_tasklet);
3026 tasklet_kill(&host->finish_tasklet);
2134a922 3027
ceb6143b 3028 if (host->vmmc)
9bea3c85 3029 regulator_put(host->vmmc);
9bea3c85 3030
2134a922
PO		 3031 kfree(host->adma_desc);
3032 kfree(host->align_buffer);
3033
3034 host->adma_desc = NULL;
3035 host->align_buffer = NULL;
d129bceb
PO		 3036}
3037
b8c86fc5 3038EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3039
b8c86fc5 3040void sdhci_free_host(struct sdhci_host *host)
d129bceb 3041{
b8c86fc5 3042 mmc_free_host(host->mmc);
d129bceb
PO		 3043}
3044
b8c86fc5 3045EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3046
3047/*****************************************************************************\
3048 * *
3049 * Driver init/exit *
3050 * *
3051\*****************************************************************************/
3052
3053static int __init sdhci_drv_init(void)
3054{
a3c76eb9 3055 pr_info(DRIVER_NAME
52fbf9c9 3056 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3057 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3058
b8c86fc5 3059 return 0;
d129bceb
PO		 3060}
3061
3062static void __exit sdhci_drv_exit(void)
3063{
d129bceb
PO		 3064}
3065
3066module_init(sdhci_drv_init);
3067module_exit(sdhci_drv_exit);
3068
df673b22 3069module_param(debug_quirks, uint, 0444);
66fd8ad5 3070module_param(debug_quirks2, uint, 0444);
67435274 3071
32710e8f 3072MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3073MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3074MODULE_LICENSE("GPL");
67435274 3075
df673b22 3076MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3077MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
kernel source for telekom puls (alcatel/mediatek)