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sdhci-s3c: add SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK quirk
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
d129bceb 19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
11763609 21#include <linux/scatterlist.h>
d129bceb 22
2f730fec
PO		 23#include <linux/leds.h>
24
d129bceb 25#include <linux/mmc/host.h>
d129bceb 26
d129bceb
PO		 27#include "sdhci.h"
28
29#define DRIVER_NAME "sdhci"
d129bceb 30
d129bceb 31#define DBG(f, x...) \
c6563178 32 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 33
f9134319
PO		 34#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
35 defined(CONFIG_MMC_SDHCI_MODULE))
36#define SDHCI_USE_LEDS_CLASS
37#endif
38
df673b22 39static unsigned int debug_quirks = 0;
67435274 40
d129bceb
PO		 41static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
42static void sdhci_finish_data(struct sdhci_host *);
43
44static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
45static void sdhci_finish_command(struct sdhci_host *);
46
47static void sdhci_dumpregs(struct sdhci_host *host)
48{
49 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
50
51 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 52 sdhci_readl(host, SDHCI_DMA_ADDRESS),
53 sdhci_readw(host, SDHCI_HOST_VERSION));
d129bceb 54 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 55 sdhci_readw(host, SDHCI_BLOCK_SIZE),
56 sdhci_readw(host, SDHCI_BLOCK_COUNT));
d129bceb 57 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 58 sdhci_readl(host, SDHCI_ARGUMENT),
59 sdhci_readw(host, SDHCI_TRANSFER_MODE));
d129bceb 60 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 61 sdhci_readl(host, SDHCI_PRESENT_STATE),
62 sdhci_readb(host, SDHCI_HOST_CONTROL));
d129bceb 63 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 64 sdhci_readb(host, SDHCI_POWER_CONTROL),
65 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
d129bceb 66 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 67 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
68 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
d129bceb 69 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 70 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
71 sdhci_readl(host, SDHCI_INT_STATUS));
d129bceb 72 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 73 sdhci_readl(host, SDHCI_INT_ENABLE),
74 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
d129bceb 75 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 76 sdhci_readw(host, SDHCI_ACMD12_ERR),
77 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
d129bceb 78 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
4e4141a5
AV		 79 sdhci_readl(host, SDHCI_CAPABILITIES),
80 sdhci_readl(host, SDHCI_MAX_CURRENT));
d129bceb 81
be3f4ae0
BD		 82 if (host->flags & SDHCI_USE_ADMA)
83 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
84 readl(host->ioaddr + SDHCI_ADMA_ERROR),
85 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
86
d129bceb
PO		 87 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
88}
89
90/*****************************************************************************\
91 * *
92 * Low level functions *
93 * *
94\*****************************************************************************/
95
7260cf5e
AV		 96static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
97{
98 u32 ier;
99
100 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
101 ier &= ~clear;
102 ier |= set;
103 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
104 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
105}
106
107static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
108{
109 sdhci_clear_set_irqs(host, 0, irqs);
110}
111
112static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
113{
114 sdhci_clear_set_irqs(host, irqs, 0);
115}
116
117static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
118{
119 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
120
68d1fb7e
AV		 121 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
122 return;
123
7260cf5e
AV		 124 if (enable)
125 sdhci_unmask_irqs(host, irqs);
126 else
127 sdhci_mask_irqs(host, irqs);
128}
129
130static void sdhci_enable_card_detection(struct sdhci_host *host)
131{
132 sdhci_set_card_detection(host, true);
133}
134
135static void sdhci_disable_card_detection(struct sdhci_host *host)
136{
137 sdhci_set_card_detection(host, false);
138}
139
d129bceb
PO		 140static void sdhci_reset(struct sdhci_host *host, u8 mask)
141{
e16514d8 142 unsigned long timeout;
063a9dbb 143 u32 uninitialized_var(ier);
e16514d8 144
b8c86fc5 145 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 146 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 147 SDHCI_CARD_PRESENT))
148 return;
149 }
150
063a9dbb
AV		 151 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
152 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
153
4e4141a5 154 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 155
e16514d8 156 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 157 host->clock = 0;
158
e16514d8
PO		 159 /* Wait max 100 ms */
160 timeout = 100;
161
162 /* hw clears the bit when it's done */
4e4141a5 163 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 164 if (timeout == 0) {
acf1da45 165 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 166 mmc_hostname(host->mmc), (int)mask);
167 sdhci_dumpregs(host);
168 return;
169 }
170 timeout--;
171 mdelay(1);
d129bceb 172 }
063a9dbb
AV		 173
174 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
175 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
d129bceb
PO		 176}
177
2f4cbb3d
NP		 178static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
179
180static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 181{
2f4cbb3d
NP		 182 if (soft)
183 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
184 else
185 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 186
7260cf5e
AV		 187 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
188 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 189 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
190 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 191 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 192
193 if (soft) {
194 /* force clock reconfiguration */
195 host->clock = 0;
196 sdhci_set_ios(host->mmc, &host->mmc->ios);
197 }
7260cf5e 198}
d129bceb 199
7260cf5e
AV		 200static void sdhci_reinit(struct sdhci_host *host)
201{
2f4cbb3d 202 sdhci_init(host, 0);
7260cf5e 203 sdhci_enable_card_detection(host);
d129bceb
PO		 204}
205
206static void sdhci_activate_led(struct sdhci_host *host)
207{
208 u8 ctrl;
209
4e4141a5 210 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 211 ctrl |= SDHCI_CTRL_LED;
4e4141a5 212 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 213}
214
215static void sdhci_deactivate_led(struct sdhci_host *host)
216{
217 u8 ctrl;
218
4e4141a5 219 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 220 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 221 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 222}
223
f9134319 224#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 225static void sdhci_led_control(struct led_classdev *led,
226 enum led_brightness brightness)
227{
228 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
229 unsigned long flags;
230
231 spin_lock_irqsave(&host->lock, flags);
232
233 if (brightness == LED_OFF)
234 sdhci_deactivate_led(host);
235 else
236 sdhci_activate_led(host);
237
238 spin_unlock_irqrestore(&host->lock, flags);
239}
240#endif
241
d129bceb
PO		 242/*****************************************************************************\
243 * *
244 * Core functions *
245 * *
246\*****************************************************************************/
247
a406f5a3 248static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 249{
7659150c
PO		 250 unsigned long flags;
251 size_t blksize, len, chunk;
7244b85b 252 u32 uninitialized_var(scratch);
7659150c 253 u8 *buf;
d129bceb 254
a406f5a3 255 DBG("PIO reading\n");
d129bceb 256
a406f5a3 257 blksize = host->data->blksz;
7659150c 258 chunk = 0;
d129bceb 259
7659150c 260 local_irq_save(flags);
d129bceb 261
a406f5a3 262 while (blksize) {
7659150c
PO		 263 if (!sg_miter_next(&host->sg_miter))
264 BUG();
d129bceb 265
7659150c 266 len = min(host->sg_miter.length, blksize);
d129bceb 267
7659150c
PO		 268 blksize -= len;
269 host->sg_miter.consumed = len;
14d836e7 270
7659150c 271 buf = host->sg_miter.addr;
d129bceb 272
7659150c
PO		 273 while (len) {
274 if (chunk == 0) {
4e4141a5 275 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 276 chunk = 4;
a406f5a3 277 }
7659150c
PO		 278
279 *buf = scratch & 0xFF;
280
281 buf++;
282 scratch >>= 8;
283 chunk--;
284 len--;
d129bceb 285 }
a406f5a3 286 }
7659150c
PO		 287
288 sg_miter_stop(&host->sg_miter);
289
290 local_irq_restore(flags);
a406f5a3 291}
d129bceb 292
a406f5a3
PO		 293static void sdhci_write_block_pio(struct sdhci_host *host)
294{
7659150c
PO		 295 unsigned long flags;
296 size_t blksize, len, chunk;
297 u32 scratch;
298 u8 *buf;
d129bceb 299
a406f5a3
PO		 300 DBG("PIO writing\n");
301
302 blksize = host->data->blksz;
7659150c
PO		 303 chunk = 0;
304 scratch = 0;
d129bceb 305
7659150c 306 local_irq_save(flags);
d129bceb 307
a406f5a3 308 while (blksize) {
7659150c
PO		 309 if (!sg_miter_next(&host->sg_miter))
310 BUG();
a406f5a3 311
7659150c
PO		 312 len = min(host->sg_miter.length, blksize);
313
314 blksize -= len;
315 host->sg_miter.consumed = len;
316
317 buf = host->sg_miter.addr;
d129bceb 318
7659150c
PO		 319 while (len) {
320 scratch |= (u32)*buf << (chunk * 8);
321
322 buf++;
323 chunk++;
324 len--;
325
326 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 327 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 328 chunk = 0;
329 scratch = 0;
d129bceb 330 }
d129bceb
PO		 331 }
332 }
7659150c
PO		 333
334 sg_miter_stop(&host->sg_miter);
335
336 local_irq_restore(flags);
a406f5a3
PO		 337}
338
339static void sdhci_transfer_pio(struct sdhci_host *host)
340{
341 u32 mask;
342
343 BUG_ON(!host->data);
344
7659150c 345 if (host->blocks == 0)
a406f5a3
PO		 346 return;
347
348 if (host->data->flags & MMC_DATA_READ)
349 mask = SDHCI_DATA_AVAILABLE;
350 else
351 mask = SDHCI_SPACE_AVAILABLE;
352
4a3cba32
PO		 353 /*
354 * Some controllers (JMicron JMB38x) mess up the buffer bits
355 * for transfers < 4 bytes. As long as it is just one block,
356 * we can ignore the bits.
357 */
358 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
359 (host->data->blocks == 1))
360 mask = ~0;
361
4e4141a5 362 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 363 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
364 udelay(100);
365
a406f5a3
PO		 366 if (host->data->flags & MMC_DATA_READ)
367 sdhci_read_block_pio(host);
368 else
369 sdhci_write_block_pio(host);
d129bceb 370
7659150c
PO		 371 host->blocks--;
372 if (host->blocks == 0)
a406f5a3 373 break;
a406f5a3 374 }
d129bceb 375
a406f5a3 376 DBG("PIO transfer complete.\n");
d129bceb
PO		 377}
378
2134a922
PO		 379static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
380{
381 local_irq_save(*flags);
382 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
383}
384
385static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
386{
387 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
388 local_irq_restore(*flags);
389}
390
118cd17d
BD		 391static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
392{
9e506f35
BD		 393 __le32 *dataddr = (__le32 __force *)(desc + 4);
394 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 395
9e506f35
BD		 396 /* SDHCI specification says ADMA descriptors should be 4 byte
397 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 398
9e506f35
BD		 399 cmdlen[0] = cpu_to_le16(cmd);
400 cmdlen[1] = cpu_to_le16(len);
401
402 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 403}
404
8f1934ce 405static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 406 struct mmc_data *data)
407{
408 int direction;
409
410 u8 *desc;
411 u8 *align;
412 dma_addr_t addr;
413 dma_addr_t align_addr;
414 int len, offset;
415
416 struct scatterlist *sg;
417 int i;
418 char *buffer;
419 unsigned long flags;
420
421 /*
422 * The spec does not specify endianness of descriptor table.
423 * We currently guess that it is LE.
424 */
425
426 if (data->flags & MMC_DATA_READ)
427 direction = DMA_FROM_DEVICE;
428 else
429 direction = DMA_TO_DEVICE;
430
431 /*
432 * The ADMA descriptor table is mapped further down as we
433 * need to fill it with data first.
434 */
435
436 host->align_addr = dma_map_single(mmc_dev(host->mmc),
437 host->align_buffer, 128 * 4, direction);
8d8bb39b 438 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 439 goto fail;
2134a922
PO		 440 BUG_ON(host->align_addr & 0x3);
441
442 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
443 data->sg, data->sg_len, direction);
8f1934ce
PO		 444 if (host->sg_count == 0)
445 goto unmap_align;
2134a922
PO		 446
447 desc = host->adma_desc;
448 align = host->align_buffer;
449
450 align_addr = host->align_addr;
451
452 for_each_sg(data->sg, sg, host->sg_count, i) {
453 addr = sg_dma_address(sg);
454 len = sg_dma_len(sg);
455
456 /*
457 * The SDHCI specification states that ADMA
458 * addresses must be 32-bit aligned. If they
459 * aren't, then we use a bounce buffer for
460 * the (up to three) bytes that screw up the
461 * alignment.
462 */
463 offset = (4 - (addr & 0x3)) & 0x3;
464 if (offset) {
465 if (data->flags & MMC_DATA_WRITE) {
466 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 467 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 468 memcpy(align, buffer, offset);
469 sdhci_kunmap_atomic(buffer, &flags);
470 }
471
118cd17d
BD		 472 /* tran, valid */
473 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 474
475 BUG_ON(offset > 65536);
476
2134a922
PO		 477 align += 4;
478 align_addr += 4;
479
480 desc += 8;
481
482 addr += offset;
483 len -= offset;
484 }
485
2134a922
PO		 486 BUG_ON(len > 65536);
487
118cd17d
BD		 488 /* tran, valid */
489 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 490 desc += 8;
491
492 /*
493 * If this triggers then we have a calculation bug
494 * somewhere. :/
495 */
496 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
497 }
498
70764a90
TA		 499 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
500 /*
501 * Mark the last descriptor as the terminating descriptor
502 */
503 if (desc != host->adma_desc) {
504 desc -= 8;
505 desc[0] |= 0x2; /* end */
506 }
507 } else {
508 /*
509 * Add a terminating entry.
510 */
2134a922 511
70764a90
TA		 512 /* nop, end, valid */
513 sdhci_set_adma_desc(desc, 0, 0, 0x3);
514 }
2134a922
PO		 515
516 /*
517 * Resync align buffer as we might have changed it.
518 */
519 if (data->flags & MMC_DATA_WRITE) {
520 dma_sync_single_for_device(mmc_dev(host->mmc),
521 host->align_addr, 128 * 4, direction);
522 }
523
524 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
525 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 526 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 527 goto unmap_entries;
2134a922 528 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 529
530 return 0;
531
532unmap_entries:
533 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
534 data->sg_len, direction);
535unmap_align:
536 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
537 128 * 4, direction);
538fail:
539 return -EINVAL;
2134a922
PO		 540}
541
542static void sdhci_adma_table_post(struct sdhci_host *host,
543 struct mmc_data *data)
544{
545 int direction;
546
547 struct scatterlist *sg;
548 int i, size;
549 u8 *align;
550 char *buffer;
551 unsigned long flags;
552
553 if (data->flags & MMC_DATA_READ)
554 direction = DMA_FROM_DEVICE;
555 else
556 direction = DMA_TO_DEVICE;
557
558 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
559 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
560
561 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
562 128 * 4, direction);
563
564 if (data->flags & MMC_DATA_READ) {
565 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
566 data->sg_len, direction);
567
568 align = host->align_buffer;
569
570 for_each_sg(data->sg, sg, host->sg_count, i) {
571 if (sg_dma_address(sg) & 0x3) {
572 size = 4 - (sg_dma_address(sg) & 0x3);
573
574 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 575 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 576 memcpy(buffer, align, size);
577 sdhci_kunmap_atomic(buffer, &flags);
578
579 align += 4;
580 }
581 }
582 }
583
584 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
585 data->sg_len, direction);
586}
587
ee53ab5d 588static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
d129bceb 589{
1c8cde92
PO		 590 u8 count;
591 unsigned target_timeout, current_timeout;
d129bceb 592
ee53ab5d
PO		 593 /*
594 * If the host controller provides us with an incorrect timeout
595 * value, just skip the check and use 0xE. The hardware may take
596 * longer to time out, but that's much better than having a too-short
597 * timeout value.
598 */
11a2f1b7 599 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 600 return 0xE;
e538fbe8 601
1c8cde92
PO		 602 /* timeout in us */
603 target_timeout = data->timeout_ns / 1000 +
604 data->timeout_clks / host->clock;
d129bceb 605
81b39802
AV		 606 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
607 host->timeout_clk = host->clock / 1000;
608
1c8cde92
PO		 609 /*
610 * Figure out needed cycles.
611 * We do this in steps in order to fit inside a 32 bit int.
612 * The first step is the minimum timeout, which will have a
613 * minimum resolution of 6 bits:
614 * (1) 2^13*1000 > 2^22,
615 * (2) host->timeout_clk < 2^16
616 * =>
617 * (1) / (2) > 2^6
618 */
619 count = 0;
620 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
621 while (current_timeout < target_timeout) {
622 count++;
623 current_timeout <<= 1;
624 if (count >= 0xF)
625 break;
626 }
627
628 if (count >= 0xF) {
629 printk(KERN_WARNING "%s: Too large timeout requested!\n",
630 mmc_hostname(host->mmc));
631 count = 0xE;
632 }
633
ee53ab5d
PO		 634 return count;
635}
636
6aa943ab
AV		 637static void sdhci_set_transfer_irqs(struct sdhci_host *host)
638{
639 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
640 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
641
642 if (host->flags & SDHCI_REQ_USE_DMA)
643 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
644 else
645 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
646}
647
ee53ab5d
PO		 648static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
649{
650 u8 count;
2134a922 651 u8 ctrl;
8f1934ce 652 int ret;
ee53ab5d
PO		 653
654 WARN_ON(host->data);
655
656 if (data == NULL)
657 return;
658
659 /* Sanity checks */
660 BUG_ON(data->blksz * data->blocks > 524288);
661 BUG_ON(data->blksz > host->mmc->max_blk_size);
662 BUG_ON(data->blocks > 65535);
663
664 host->data = data;
665 host->data_early = 0;
666
667 count = sdhci_calc_timeout(host, data);
4e4141a5 668 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
d129bceb 669
a13abc7b 670 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 671 host->flags |= SDHCI_REQ_USE_DMA;
672
2134a922
PO		 673 /*
674 * FIXME: This doesn't account for merging when mapping the
675 * scatterlist.
676 */
677 if (host->flags & SDHCI_REQ_USE_DMA) {
678 int broken, i;
679 struct scatterlist *sg;
680
681 broken = 0;
682 if (host->flags & SDHCI_USE_ADMA) {
683 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
684 broken = 1;
685 } else {
686 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
687 broken = 1;
688 }
689
690 if (unlikely(broken)) {
691 for_each_sg(data->sg, sg, data->sg_len, i) {
692 if (sg->length & 0x3) {
693 DBG("Reverting to PIO because of "
694 "transfer size (%d)\n",
695 sg->length);
696 host->flags &= ~SDHCI_REQ_USE_DMA;
697 break;
698 }
699 }
700 }
c9fddbc4
PO		 701 }
702
703 /*
704 * The assumption here being that alignment is the same after
705 * translation to device address space.
706 */
2134a922
PO		 707 if (host->flags & SDHCI_REQ_USE_DMA) {
708 int broken, i;
709 struct scatterlist *sg;
710
711 broken = 0;
712 if (host->flags & SDHCI_USE_ADMA) {
713 /*
714 * As we use 3 byte chunks to work around
715 * alignment problems, we need to check this
716 * quirk.
717 */
718 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
719 broken = 1;
720 } else {
721 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
722 broken = 1;
723 }
724
725 if (unlikely(broken)) {
726 for_each_sg(data->sg, sg, data->sg_len, i) {
727 if (sg->offset & 0x3) {
728 DBG("Reverting to PIO because of "
729 "bad alignment\n");
730 host->flags &= ~SDHCI_REQ_USE_DMA;
731 break;
732 }
733 }
734 }
735 }
736
8f1934ce
PO		 737 if (host->flags & SDHCI_REQ_USE_DMA) {
738 if (host->flags & SDHCI_USE_ADMA) {
739 ret = sdhci_adma_table_pre(host, data);
740 if (ret) {
741 /*
742 * This only happens when someone fed
743 * us an invalid request.
744 */
745 WARN_ON(1);
ebd6d357 746 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 747 } else {
4e4141a5
AV		 748 sdhci_writel(host, host->adma_addr,
749 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 750 }
751 } else {
c8b3e02e 752 int sg_cnt;
8f1934ce 753
c8b3e02e 754 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 755 data->sg, data->sg_len,
756 (data->flags & MMC_DATA_READ) ?
757 DMA_FROM_DEVICE :
758 DMA_TO_DEVICE);
c8b3e02e 759 if (sg_cnt == 0) {
8f1934ce
PO		 760 /*
761 * This only happens when someone fed
762 * us an invalid request.
763 */
764 WARN_ON(1);
ebd6d357 765 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 766 } else {
719a61b4 767 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 768 sdhci_writel(host, sg_dma_address(data->sg),
769 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 770 }
771 }
772 }
773
2134a922
PO		 774 /*
775 * Always adjust the DMA selection as some controllers
776 * (e.g. JMicron) can't do PIO properly when the selection
777 * is ADMA.
778 */
779 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 780 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 781 ctrl &= ~SDHCI_CTRL_DMA_MASK;
782 if ((host->flags & SDHCI_REQ_USE_DMA) &&
783 (host->flags & SDHCI_USE_ADMA))
784 ctrl |= SDHCI_CTRL_ADMA32;
785 else
786 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 787 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 788 }
789
8f1934ce 790 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 791 int flags;
792
793 flags = SG_MITER_ATOMIC;
794 if (host->data->flags & MMC_DATA_READ)
795 flags |= SG_MITER_TO_SG;
796 else
797 flags |= SG_MITER_FROM_SG;
798 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 799 host->blocks = data->blocks;
d129bceb 800 }
c7fa9963 801
6aa943ab
AV		 802 sdhci_set_transfer_irqs(host);
803
bab76961 804 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
4e4141a5
AV		 805 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
806 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 807}
808
809static void sdhci_set_transfer_mode(struct sdhci_host *host,
810 struct mmc_data *data)
811{
812 u16 mode;
813
c7fa9963
PO		 814 if (data == NULL)
815 return;
816
e538fbe8
PO		 817 WARN_ON(!host->data);
818
c7fa9963
PO		 819 mode = SDHCI_TRNS_BLK_CNT_EN;
820 if (data->blocks > 1)
821 mode |= SDHCI_TRNS_MULTI;
822 if (data->flags & MMC_DATA_READ)
823 mode |= SDHCI_TRNS_READ;
c9fddbc4 824 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 825 mode |= SDHCI_TRNS_DMA;
826
4e4141a5 827 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 828}
829
830static void sdhci_finish_data(struct sdhci_host *host)
831{
832 struct mmc_data *data;
d129bceb
PO		 833
834 BUG_ON(!host->data);
835
836 data = host->data;
837 host->data = NULL;
838
c9fddbc4 839 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 840 if (host->flags & SDHCI_USE_ADMA)
841 sdhci_adma_table_post(host, data);
842 else {
843 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
844 data->sg_len, (data->flags & MMC_DATA_READ) ?
845 DMA_FROM_DEVICE : DMA_TO_DEVICE);
846 }
d129bceb
PO		 847 }
848
849 /*
c9b74c5b
PO		 850 * The specification states that the block count register must
851 * be updated, but it does not specify at what point in the
852 * data flow. That makes the register entirely useless to read
853 * back so we have to assume that nothing made it to the card
854 * in the event of an error.
d129bceb 855 */
c9b74c5b
PO		 856 if (data->error)
857 data->bytes_xfered = 0;
d129bceb 858 else
c9b74c5b 859 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 860
d129bceb
PO		 861 if (data->stop) {
862 /*
863 * The controller needs a reset of internal state machines
864 * upon error conditions.
865 */
17b0429d 866 if (data->error) {
d129bceb
PO		 867 sdhci_reset(host, SDHCI_RESET_CMD);
868 sdhci_reset(host, SDHCI_RESET_DATA);
869 }
870
871 sdhci_send_command(host, data->stop);
872 } else
873 tasklet_schedule(&host->finish_tasklet);
874}
875
876static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
877{
878 int flags;
fd2208d7 879 u32 mask;
7cb2c76f 880 unsigned long timeout;
d129bceb
PO		 881
882 WARN_ON(host->cmd);
883
d129bceb 884 /* Wait max 10 ms */
7cb2c76f 885 timeout = 10;
fd2208d7
PO		 886
887 mask = SDHCI_CMD_INHIBIT;
888 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
889 mask |= SDHCI_DATA_INHIBIT;
890
891 /* We shouldn't wait for data inihibit for stop commands, even
892 though they might use busy signaling */
893 if (host->mrq->data && (cmd == host->mrq->data->stop))
894 mask &= ~SDHCI_DATA_INHIBIT;
895
4e4141a5 896 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 897 if (timeout == 0) {
d129bceb 898 printk(KERN_ERR "%s: Controller never released "
acf1da45 899 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 900 sdhci_dumpregs(host);
17b0429d 901 cmd->error = -EIO;
d129bceb
PO		 902 tasklet_schedule(&host->finish_tasklet);
903 return;
904 }
7cb2c76f
PO		 905 timeout--;
906 mdelay(1);
907 }
d129bceb
PO		 908
909 mod_timer(&host->timer, jiffies + 10 * HZ);
910
911 host->cmd = cmd;
912
913 sdhci_prepare_data(host, cmd->data);
914
4e4141a5 915 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 916
c7fa9963
PO		 917 sdhci_set_transfer_mode(host, cmd->data);
918
d129bceb 919 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 920 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 921 mmc_hostname(host->mmc));
17b0429d 922 cmd->error = -EINVAL;
d129bceb
PO		 923 tasklet_schedule(&host->finish_tasklet);
924 return;
925 }
926
927 if (!(cmd->flags & MMC_RSP_PRESENT))
928 flags = SDHCI_CMD_RESP_NONE;
929 else if (cmd->flags & MMC_RSP_136)
930 flags = SDHCI_CMD_RESP_LONG;
931 else if (cmd->flags & MMC_RSP_BUSY)
932 flags = SDHCI_CMD_RESP_SHORT_BUSY;
933 else
934 flags = SDHCI_CMD_RESP_SHORT;
935
936 if (cmd->flags & MMC_RSP_CRC)
937 flags |= SDHCI_CMD_CRC;
938 if (cmd->flags & MMC_RSP_OPCODE)
939 flags |= SDHCI_CMD_INDEX;
940 if (cmd->data)
941 flags |= SDHCI_CMD_DATA;
942
4e4141a5 943 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 944}
945
946static void sdhci_finish_command(struct sdhci_host *host)
947{
948 int i;
949
950 BUG_ON(host->cmd == NULL);
951
952 if (host->cmd->flags & MMC_RSP_PRESENT) {
953 if (host->cmd->flags & MMC_RSP_136) {
954 /* CRC is stripped so we need to do some shifting. */
955 for (i = 0;i < 4;i++) {
4e4141a5 956 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 957 SDHCI_RESPONSE + (3-i)*4) << 8;
958 if (i != 3)
959 host->cmd->resp[i] |=
4e4141a5 960 sdhci_readb(host,
d129bceb
PO		 961 SDHCI_RESPONSE + (3-i)*4-1);
962 }
963 } else {
4e4141a5 964 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 965 }
966 }
967
17b0429d 968 host->cmd->error = 0;
d129bceb 969
e538fbe8
PO		 970 if (host->data && host->data_early)
971 sdhci_finish_data(host);
972
973 if (!host->cmd->data)
d129bceb
PO		 974 tasklet_schedule(&host->finish_tasklet);
975
976 host->cmd = NULL;
977}
978
979static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
980{
981 int div;
982 u16 clk;
7cb2c76f 983 unsigned long timeout;
d129bceb
PO		 984
985 if (clock == host->clock)
986 return;
987
8114634c
AV		 988 if (host->ops->set_clock) {
989 host->ops->set_clock(host, clock);
990 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
991 return;
992 }
993
4e4141a5 994 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 995
996 if (clock == 0)
997 goto out;
998
999 for (div = 1;div < 256;div *= 2) {
1000 if ((host->max_clk / div) <= clock)
1001 break;
1002 }
1003 div >>= 1;
1004
1005 clk = div << SDHCI_DIVIDER_SHIFT;
1006 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1007 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1008
27f6cb16
CB		 1009 /* Wait max 20 ms */
1010 timeout = 20;
4e4141a5 1011 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1012 & SDHCI_CLOCK_INT_STABLE)) {
1013 if (timeout == 0) {
acf1da45
PO		 1014 printk(KERN_ERR "%s: Internal clock never "
1015 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1016 sdhci_dumpregs(host);
1017 return;
1018 }
7cb2c76f
PO		 1019 timeout--;
1020 mdelay(1);
1021 }
d129bceb
PO		 1022
1023 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1024 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1025
1026out:
1027 host->clock = clock;
1028}
1029
146ad66e
PO		 1030static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1031{
1032 u8 pwr;
1033
ae628903
PO		 1034 if (power == (unsigned short)-1)
1035 pwr = 0;
1036 else {
1037 switch (1 << power) {
1038 case MMC_VDD_165_195:
1039 pwr = SDHCI_POWER_180;
1040 break;
1041 case MMC_VDD_29_30:
1042 case MMC_VDD_30_31:
1043 pwr = SDHCI_POWER_300;
1044 break;
1045 case MMC_VDD_32_33:
1046 case MMC_VDD_33_34:
1047 pwr = SDHCI_POWER_330;
1048 break;
1049 default:
1050 BUG();
1051 }
1052 }
1053
1054 if (host->pwr == pwr)
146ad66e
PO		 1055 return;
1056
ae628903
PO		 1057 host->pwr = pwr;
1058
1059 if (pwr == 0) {
4e4141a5 1060 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ae628903 1061 return;
9e9dc5f2
DS		 1062 }
1063
1064 /*
1065 * Spec says that we should clear the power reg before setting
1066 * a new value. Some controllers don't seem to like this though.
1067 */
b8c86fc5 1068 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1069 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1070
e08c1694 1071 /*
c71f6512 1072 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1073 * and set turn on power at the same time, so set the voltage first.
1074 */
11a2f1b7 1075 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1076 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1077
ae628903 1078 pwr |= SDHCI_POWER_ON;
146ad66e 1079
ae628903 1080 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1081
1082 /*
1083 * Some controllers need an extra 10ms delay of 10ms before they
1084 * can apply clock after applying power
1085 */
11a2f1b7 1086 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1087 mdelay(10);
146ad66e
PO		 1088}
1089
d129bceb
PO		 1090/*****************************************************************************\
1091 * *
1092 * MMC callbacks *
1093 * *
1094\*****************************************************************************/
1095
1096static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1097{
1098 struct sdhci_host *host;
68d1fb7e 1099 bool present;
d129bceb
PO		 1100 unsigned long flags;
1101
1102 host = mmc_priv(mmc);
1103
1104 spin_lock_irqsave(&host->lock, flags);
1105
1106 WARN_ON(host->mrq != NULL);
1107
f9134319 1108#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1109 sdhci_activate_led(host);
2f730fec 1110#endif
d129bceb
PO		 1111
1112 host->mrq = mrq;
1113
68d1fb7e
AV		 1114 /* If polling, assume that the card is always present. */
1115 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1116 present = true;
1117 else
1118 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1119 SDHCI_CARD_PRESENT;
1120
1121 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1122 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1123 tasklet_schedule(&host->finish_tasklet);
1124 } else
1125 sdhci_send_command(host, mrq->cmd);
1126
5f25a66f 1127 mmiowb();
d129bceb
PO		 1128 spin_unlock_irqrestore(&host->lock, flags);
1129}
1130
1131static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1132{
1133 struct sdhci_host *host;
1134 unsigned long flags;
1135 u8 ctrl;
1136
1137 host = mmc_priv(mmc);
1138
1139 spin_lock_irqsave(&host->lock, flags);
1140
1e72859e
PO		 1141 if (host->flags & SDHCI_DEVICE_DEAD)
1142 goto out;
1143
d129bceb
PO		 1144 /*
1145 * Reset the chip on each power off.
1146 * Should clear out any weird states.
1147 */
1148 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1149 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1150 sdhci_reinit(host);
d129bceb
PO		 1151 }
1152
1153 sdhci_set_clock(host, ios->clock);
1154
1155 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1156 sdhci_set_power(host, -1);
d129bceb 1157 else
146ad66e 1158 sdhci_set_power(host, ios->vdd);
d129bceb 1159
4e4141a5 1160 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1161
ae6d6c92
KP		 1162 if (ios->bus_width == MMC_BUS_WIDTH_8)
1163 ctrl |= SDHCI_CTRL_8BITBUS;
1164 else
1165 ctrl &= ~SDHCI_CTRL_8BITBUS;
1166
d129bceb
PO		 1167 if (ios->bus_width == MMC_BUS_WIDTH_4)
1168 ctrl |= SDHCI_CTRL_4BITBUS;
1169 else
1170 ctrl &= ~SDHCI_CTRL_4BITBUS;
cd9277c0
PO		 1171
1172 if (ios->timing == MMC_TIMING_SD_HS)
1173 ctrl |= SDHCI_CTRL_HISPD;
1174 else
1175 ctrl &= ~SDHCI_CTRL_HISPD;
1176
4e4141a5 1177 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb 1178
b8352260
LD		 1179 /*
1180 * Some (ENE) controllers go apeshit on some ios operation,
1181 * signalling timeout and CRC errors even on CMD0. Resetting
1182 * it on each ios seems to solve the problem.
1183 */
b8c86fc5 1184 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1185 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1186
1e72859e 1187out:
5f25a66f 1188 mmiowb();
d129bceb
PO		 1189 spin_unlock_irqrestore(&host->lock, flags);
1190}
1191
1192static int sdhci_get_ro(struct mmc_host *mmc)
1193{
1194 struct sdhci_host *host;
1195 unsigned long flags;
1196 int present;
1197
1198 host = mmc_priv(mmc);
1199
1200 spin_lock_irqsave(&host->lock, flags);
1201
1e72859e
PO		 1202 if (host->flags & SDHCI_DEVICE_DEAD)
1203 present = 0;
1204 else
4e4141a5 1205 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
d129bceb
PO		 1206
1207 spin_unlock_irqrestore(&host->lock, flags);
1208
c5075a10
AV		 1209 if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT)
1210 return !!(present & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1211 return !(present & SDHCI_WRITE_PROTECT);
1212}
1213
f75979b7
PO		 1214static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1215{
1216 struct sdhci_host *host;
1217 unsigned long flags;
f75979b7
PO		 1218
1219 host = mmc_priv(mmc);
1220
1221 spin_lock_irqsave(&host->lock, flags);
1222
1e72859e
PO		 1223 if (host->flags & SDHCI_DEVICE_DEAD)
1224 goto out;
1225
f75979b7 1226 if (enable)
7260cf5e
AV		 1227 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1228 else
1229 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1230out:
f75979b7
PO		 1231 mmiowb();
1232
1233 spin_unlock_irqrestore(&host->lock, flags);
1234}
1235
ab7aefd0 1236static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1237 .request = sdhci_request,
1238 .set_ios = sdhci_set_ios,
1239 .get_ro = sdhci_get_ro,
f75979b7 1240 .enable_sdio_irq = sdhci_enable_sdio_irq,
d129bceb
PO		 1241};
1242
1243/*****************************************************************************\
1244 * *
1245 * Tasklets *
1246 * *
1247\*****************************************************************************/
1248
1249static void sdhci_tasklet_card(unsigned long param)
1250{
1251 struct sdhci_host *host;
1252 unsigned long flags;
1253
1254 host = (struct sdhci_host*)param;
1255
1256 spin_lock_irqsave(&host->lock, flags);
1257
4e4141a5 1258 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
d129bceb
PO		 1259 if (host->mrq) {
1260 printk(KERN_ERR "%s: Card removed during transfer!\n",
1261 mmc_hostname(host->mmc));
1262 printk(KERN_ERR "%s: Resetting controller.\n",
1263 mmc_hostname(host->mmc));
1264
1265 sdhci_reset(host, SDHCI_RESET_CMD);
1266 sdhci_reset(host, SDHCI_RESET_DATA);
1267
17b0429d 1268 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1269 tasklet_schedule(&host->finish_tasklet);
1270 }
1271 }
1272
1273 spin_unlock_irqrestore(&host->lock, flags);
1274
04cf585d 1275 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1276}
1277
1278static void sdhci_tasklet_finish(unsigned long param)
1279{
1280 struct sdhci_host *host;
1281 unsigned long flags;
1282 struct mmc_request *mrq;
1283
1284 host = (struct sdhci_host*)param;
1285
1286 spin_lock_irqsave(&host->lock, flags);
1287
1288 del_timer(&host->timer);
1289
1290 mrq = host->mrq;
1291
d129bceb
PO		 1292 /*
1293 * The controller needs a reset of internal state machines
1294 * upon error conditions.
1295 */
1e72859e
PO		 1296 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1297 (mrq->cmd->error ||
1298 (mrq->data && (mrq->data->error ||
1299 (mrq->data->stop && mrq->data->stop->error))) ||
1300 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1301
1302 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1303 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1304 unsigned int clock;
1305
1306 /* This is to force an update */
1307 clock = host->clock;
1308 host->clock = 0;
1309 sdhci_set_clock(host, clock);
1310 }
1311
1312 /* Spec says we should do both at the same time, but Ricoh
1313 controllers do not like that. */
d129bceb
PO		 1314 sdhci_reset(host, SDHCI_RESET_CMD);
1315 sdhci_reset(host, SDHCI_RESET_DATA);
1316 }
1317
1318 host->mrq = NULL;
1319 host->cmd = NULL;
1320 host->data = NULL;
1321
f9134319 1322#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1323 sdhci_deactivate_led(host);
2f730fec 1324#endif
d129bceb 1325
5f25a66f 1326 mmiowb();
d129bceb
PO		 1327 spin_unlock_irqrestore(&host->lock, flags);
1328
1329 mmc_request_done(host->mmc, mrq);
1330}
1331
1332static void sdhci_timeout_timer(unsigned long data)
1333{
1334 struct sdhci_host *host;
1335 unsigned long flags;
1336
1337 host = (struct sdhci_host*)data;
1338
1339 spin_lock_irqsave(&host->lock, flags);
1340
1341 if (host->mrq) {
acf1da45
PO		 1342 printk(KERN_ERR "%s: Timeout waiting for hardware "
1343 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1344 sdhci_dumpregs(host);
1345
1346 if (host->data) {
17b0429d 1347 host->data->error = -ETIMEDOUT;
d129bceb
PO		 1348 sdhci_finish_data(host);
1349 } else {
1350 if (host->cmd)
17b0429d 1351 host->cmd->error = -ETIMEDOUT;
d129bceb 1352 else
17b0429d 1353 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 1354
1355 tasklet_schedule(&host->finish_tasklet);
1356 }
1357 }
1358
5f25a66f 1359 mmiowb();
d129bceb
PO		 1360 spin_unlock_irqrestore(&host->lock, flags);
1361}
1362
1363/*****************************************************************************\
1364 * *
1365 * Interrupt handling *
1366 * *
1367\*****************************************************************************/
1368
1369static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1370{
1371 BUG_ON(intmask == 0);
1372
1373 if (!host->cmd) {
b67ac3f3
PO		 1374 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1375 "though no command operation was in progress.\n",
1376 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1377 sdhci_dumpregs(host);
1378 return;
1379 }
1380
43b58b36 1381 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 1382 host->cmd->error = -ETIMEDOUT;
1383 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1384 SDHCI_INT_INDEX))
1385 host->cmd->error = -EILSEQ;
43b58b36 1386
e809517f 1387 if (host->cmd->error) {
d129bceb 1388 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 1389 return;
1390 }
1391
1392 /*
1393 * The host can send and interrupt when the busy state has
1394 * ended, allowing us to wait without wasting CPU cycles.
1395 * Unfortunately this is overloaded on the "data complete"
1396 * interrupt, so we need to take some care when handling
1397 * it.
1398 *
1399 * Note: The 1.0 specification is a bit ambiguous about this
1400 * feature so there might be some problems with older
1401 * controllers.
1402 */
1403 if (host->cmd->flags & MMC_RSP_BUSY) {
1404 if (host->cmd->data)
1405 DBG("Cannot wait for busy signal when also "
1406 "doing a data transfer");
f945405c 1407 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 1408 return;
f945405c
BD		 1409
1410 /* The controller does not support the end-of-busy IRQ,
1411 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 1412 }
1413
1414 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 1415 sdhci_finish_command(host);
d129bceb
PO		 1416}
1417
6882a8c0
BD		 1418#ifdef DEBUG
1419static void sdhci_show_adma_error(struct sdhci_host *host)
1420{
1421 const char *name = mmc_hostname(host->mmc);
1422 u8 *desc = host->adma_desc;
1423 __le32 *dma;
1424 __le16 *len;
1425 u8 attr;
1426
1427 sdhci_dumpregs(host);
1428
1429 while (true) {
1430 dma = (__le32 *)(desc + 4);
1431 len = (__le16 *)(desc + 2);
1432 attr = *desc;
1433
1434 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1435 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1436
1437 desc += 8;
1438
1439 if (attr & 2)
1440 break;
1441 }
1442}
1443#else
1444static void sdhci_show_adma_error(struct sdhci_host *host) { }
1445#endif
1446
d129bceb
PO		 1447static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1448{
1449 BUG_ON(intmask == 0);
1450
1451 if (!host->data) {
1452 /*
e809517f
PO		 1453 * The "data complete" interrupt is also used to
1454 * indicate that a busy state has ended. See comment
1455 * above in sdhci_cmd_irq().
d129bceb 1456 */
e809517f
PO		 1457 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1458 if (intmask & SDHCI_INT_DATA_END) {
1459 sdhci_finish_command(host);
1460 return;
1461 }
1462 }
d129bceb 1463
b67ac3f3
PO		 1464 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1465 "though no data operation was in progress.\n",
1466 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1467 sdhci_dumpregs(host);
1468
1469 return;
1470 }
1471
1472 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d
PO		 1473 host->data->error = -ETIMEDOUT;
1474 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1475 host->data->error = -EILSEQ;
6882a8c0
BD		 1476 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1477 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1478 sdhci_show_adma_error(host);
2134a922 1479 host->data->error = -EIO;
6882a8c0 1480 }
d129bceb 1481
17b0429d 1482 if (host->data->error)
d129bceb
PO		 1483 sdhci_finish_data(host);
1484 else {
a406f5a3 1485 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 1486 sdhci_transfer_pio(host);
1487
6ba736a1
PO		 1488 /*
1489 * We currently don't do anything fancy with DMA
1490 * boundaries, but as we can't disable the feature
1491 * we need to at least restart the transfer.
1492 */
1493 if (intmask & SDHCI_INT_DMA_END)
4e4141a5
AV		 1494 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1495 SDHCI_DMA_ADDRESS);
6ba736a1 1496
e538fbe8
PO		 1497 if (intmask & SDHCI_INT_DATA_END) {
1498 if (host->cmd) {
1499 /*
1500 * Data managed to finish before the
1501 * command completed. Make sure we do
1502 * things in the proper order.
1503 */
1504 host->data_early = 1;
1505 } else {
1506 sdhci_finish_data(host);
1507 }
1508 }
d129bceb
PO		 1509 }
1510}
1511
7d12e780 1512static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 1513{
1514 irqreturn_t result;
1515 struct sdhci_host* host = dev_id;
1516 u32 intmask;
f75979b7 1517 int cardint = 0;
d129bceb
PO		 1518
1519 spin_lock(&host->lock);
1520
4e4141a5 1521 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 1522
62df67a5 1523 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 1524 result = IRQ_NONE;
1525 goto out;
1526 }
1527
b69c9058
PO		 1528 DBG("*** %s got interrupt: 0x%08x\n",
1529 mmc_hostname(host->mmc), intmask);
d129bceb 1530
3192a28f 1531 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
4e4141a5
AV		 1532 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1533 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
d129bceb 1534 tasklet_schedule(&host->card_tasklet);
3192a28f 1535 }
d129bceb 1536
3192a28f 1537 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1538
3192a28f 1539 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 1540 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1541 SDHCI_INT_STATUS);
3192a28f 1542 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1543 }
1544
1545 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 1546 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1547 SDHCI_INT_STATUS);
3192a28f 1548 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1549 }
1550
1551 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1552
964f9ce2
PO		 1553 intmask &= ~SDHCI_INT_ERROR;
1554
d129bceb 1555 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1556 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1557 mmc_hostname(host->mmc));
4e4141a5 1558 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 1559 }
1560
9d26a5d3 1561 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 1562
f75979b7
PO		 1563 if (intmask & SDHCI_INT_CARD_INT)
1564 cardint = 1;
1565
1566 intmask &= ~SDHCI_INT_CARD_INT;
1567
3192a28f 1568 if (intmask) {
acf1da45 1569 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 1570 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1571 sdhci_dumpregs(host);
1572
4e4141a5 1573 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 1574 }
d129bceb
PO		 1575
1576 result = IRQ_HANDLED;
1577
5f25a66f 1578 mmiowb();
d129bceb
PO		 1579out:
1580 spin_unlock(&host->lock);
1581
f75979b7
PO		 1582 /*
1583 * We have to delay this as it calls back into the driver.
1584 */
1585 if (cardint)
1586 mmc_signal_sdio_irq(host->mmc);
1587
d129bceb
PO		 1588 return result;
1589}
1590
1591/*****************************************************************************\
1592 * *
1593 * Suspend/resume *
1594 * *
1595\*****************************************************************************/
1596
1597#ifdef CONFIG_PM
1598
b8c86fc5 1599int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
d129bceb 1600{
b8c86fc5 1601 int ret;
a715dfc7 1602
7260cf5e
AV		 1603 sdhci_disable_card_detection(host);
1604
1a13f8fa 1605 ret = mmc_suspend_host(host->mmc);
b8c86fc5
PO		 1606 if (ret)
1607 return ret;
a715dfc7 1608
b8c86fc5 1609 free_irq(host->irq, host);
d129bceb
PO		 1610
1611 return 0;
1612}
1613
b8c86fc5 1614EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 1615
b8c86fc5
PO		 1616int sdhci_resume_host(struct sdhci_host *host)
1617{
1618 int ret;
d129bceb 1619
a13abc7b 1620 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 1621 if (host->ops->enable_dma)
1622 host->ops->enable_dma(host);
1623 }
d129bceb 1624
b8c86fc5
PO		 1625 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1626 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 1627 if (ret)
1628 return ret;
d129bceb 1629
2f4cbb3d 1630 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
b8c86fc5
PO		 1631 mmiowb();
1632
1633 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 1634 sdhci_enable_card_detection(host);
1635
2f4cbb3d 1636 return ret;
d129bceb
PO		 1637}
1638
b8c86fc5 1639EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 1640
1641#endif /* CONFIG_PM */
1642
1643/*****************************************************************************\
1644 * *
b8c86fc5 1645 * Device allocation/registration *
d129bceb
PO		 1646 * *
1647\*****************************************************************************/
1648
b8c86fc5
PO		 1649struct sdhci_host *sdhci_alloc_host(struct device *dev,
1650 size_t priv_size)
d129bceb 1651{
d129bceb
PO		 1652 struct mmc_host *mmc;
1653 struct sdhci_host *host;
1654
b8c86fc5 1655 WARN_ON(dev == NULL);
d129bceb 1656
b8c86fc5 1657 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 1658 if (!mmc)
b8c86fc5 1659 return ERR_PTR(-ENOMEM);
d129bceb
PO		 1660
1661 host = mmc_priv(mmc);
1662 host->mmc = mmc;
1663
b8c86fc5
PO		 1664 return host;
1665}
8a4da143 1666
b8c86fc5 1667EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 1668
b8c86fc5
PO		 1669int sdhci_add_host(struct sdhci_host *host)
1670{
1671 struct mmc_host *mmc;
1672 unsigned int caps;
b8c86fc5 1673 int ret;
d129bceb 1674
b8c86fc5
PO		 1675 WARN_ON(host == NULL);
1676 if (host == NULL)
1677 return -EINVAL;
d129bceb 1678
b8c86fc5 1679 mmc = host->mmc;
d129bceb 1680
b8c86fc5
PO		 1681 if (debug_quirks)
1682 host->quirks = debug_quirks;
d129bceb 1683
d96649ed
PO		 1684 sdhci_reset(host, SDHCI_RESET_ALL);
1685
4e4141a5 1686 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 1687 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1688 >> SDHCI_SPEC_VER_SHIFT;
1689 if (host->version > SDHCI_SPEC_200) {
4a965505 1690 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 1691 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 1692 host->version);
4a965505
PO		 1693 }
1694
ccc92c23
ML		 1695 caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
1696 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 1697
b8c86fc5 1698 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b
RR		 1699 host->flags |= SDHCI_USE_SDMA;
1700 else if (!(caps & SDHCI_CAN_DO_SDMA))
1701 DBG("Controller doesn't have SDMA capability\n");
67435274 1702 else
a13abc7b 1703 host->flags |= SDHCI_USE_SDMA;
d129bceb 1704
b8c86fc5 1705 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 1706 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 1707 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 1708 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 1709 }
1710
a13abc7b
RR		 1711 if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
1712 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 1713
1714 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1715 (host->flags & SDHCI_USE_ADMA)) {
1716 DBG("Disabling ADMA as it is marked broken\n");
1717 host->flags &= ~SDHCI_USE_ADMA;
1718 }
1719
a13abc7b 1720 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 1721 if (host->ops->enable_dma) {
1722 if (host->ops->enable_dma(host)) {
1723 printk(KERN_WARNING "%s: No suitable DMA "
1724 "available. Falling back to PIO.\n",
1725 mmc_hostname(mmc));
a13abc7b
RR		 1726 host->flags &=
1727 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 1728 }
d129bceb
PO		 1729 }
1730 }
1731
2134a922
PO		 1732 if (host->flags & SDHCI_USE_ADMA) {
1733 /*
1734 * We need to allocate descriptors for all sg entries
1735 * (128) and potentially one alignment transfer for
1736 * each of those entries.
1737 */
1738 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1739 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1740 if (!host->adma_desc || !host->align_buffer) {
1741 kfree(host->adma_desc);
1742 kfree(host->align_buffer);
1743 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1744 "buffers. Falling back to standard DMA.\n",
1745 mmc_hostname(mmc));
1746 host->flags &= ~SDHCI_USE_ADMA;
1747 }
1748 }
1749
7659150c
PO		 1750 /*
1751 * If we use DMA, then it's up to the caller to set the DMA
1752 * mask, but PIO does not need the hw shim so we set a new
1753 * mask here in that case.
1754 */
a13abc7b 1755 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 1756 host->dma_mask = DMA_BIT_MASK(64);
1757 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1758 }
d129bceb 1759
8ef1a143
PO		 1760 host->max_clk =
1761 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
4240ff0a 1762 host->max_clk *= 1000000;
f27f47ef
AV		 1763 if (host->max_clk == 0 || host->quirks &
1764 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a
BD		 1765 if (!host->ops->get_max_clock) {
1766 printk(KERN_ERR
1767 "%s: Hardware doesn't specify base clock "
1768 "frequency.\n", mmc_hostname(mmc));
1769 return -ENODEV;
1770 }
1771 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 1772 }
d129bceb 1773
1c8cde92
PO		 1774 host->timeout_clk =
1775 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1776 if (host->timeout_clk == 0) {
81b39802
AV		 1777 if (host->ops->get_timeout_clock) {
1778 host->timeout_clk = host->ops->get_timeout_clock(host);
1779 } else if (!(host->quirks &
1780 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4240ff0a
BD		 1781 printk(KERN_ERR
1782 "%s: Hardware doesn't specify timeout clock "
1783 "frequency.\n", mmc_hostname(mmc));
1784 return -ENODEV;
1785 }
1c8cde92
PO		 1786 }
1787 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1788 host->timeout_clk *= 1000;
d129bceb
PO		 1789
1790 /*
1791 * Set host parameters.
1792 */
1793 mmc->ops = &sdhci_ops;
e9510176 1794 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK &&
cfd1f82f 1795 host->ops->get_min_clock)
a9e58f25
AV		 1796 mmc->f_min = host->ops->get_min_clock(host);
1797 else
1798 mmc->f_min = host->max_clk / 256;
d129bceb 1799 mmc->f_max = host->max_clk;
c1f5977c 1800 mmc->caps |= MMC_CAP_SDIO_IRQ;
5fe23c7f
AV		 1801
1802 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
1803 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 1804
86a6a874 1805 if (caps & SDHCI_CAN_DO_HISPD)
cd9277c0
PO		 1806 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1807
68d1fb7e
AV		 1808 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1809 mmc->caps |= MMC_CAP_NEEDS_POLL;
1810
146ad66e
PO		 1811 mmc->ocr_avail = 0;
1812 if (caps & SDHCI_CAN_VDD_330)
1813 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
c70840e8 1814 if (caps & SDHCI_CAN_VDD_300)
146ad66e 1815 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
c70840e8 1816 if (caps & SDHCI_CAN_VDD_180)
55556da0 1817 mmc->ocr_avail |= MMC_VDD_165_195;
146ad66e
PO		 1818
1819 if (mmc->ocr_avail == 0) {
1820 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 1821 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 1822 return -ENODEV;
146ad66e
PO		 1823 }
1824
d129bceb
PO		 1825 spin_lock_init(&host->lock);
1826
1827 /*
2134a922
PO		 1828 * Maximum number of segments. Depends on if the hardware
1829 * can do scatter/gather or not.
d129bceb 1830 */
2134a922
PO		 1831 if (host->flags & SDHCI_USE_ADMA)
1832 mmc->max_hw_segs = 128;
a13abc7b 1833 else if (host->flags & SDHCI_USE_SDMA)
d129bceb 1834 mmc->max_hw_segs = 1;
2134a922
PO		 1835 else /* PIO */
1836 mmc->max_hw_segs = 128;
1837 mmc->max_phys_segs = 128;
d129bceb
PO		 1838
1839 /*
bab76961 1840 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 1841 * size (512KiB).
d129bceb 1842 */
55db890a 1843 mmc->max_req_size = 524288;
d129bceb
PO		 1844
1845 /*
1846 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 1847 * of bytes. When doing hardware scatter/gather, each entry cannot
1848 * be larger than 64 KiB though.
d129bceb 1849 */
2134a922
PO		 1850 if (host->flags & SDHCI_USE_ADMA)
1851 mmc->max_seg_size = 65536;
1852 else
1853 mmc->max_seg_size = mmc->max_req_size;
d129bceb 1854
fe4a3c7a
PO		 1855 /*
1856 * Maximum block size. This varies from controller to controller and
1857 * is specified in the capabilities register.
1858 */
0633f654
AV		 1859 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1860 mmc->max_blk_size = 2;
1861 } else {
1862 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1863 SDHCI_MAX_BLOCK_SHIFT;
1864 if (mmc->max_blk_size >= 3) {
1865 printk(KERN_WARNING "%s: Invalid maximum block size, "
1866 "assuming 512 bytes\n", mmc_hostname(mmc));
1867 mmc->max_blk_size = 0;
1868 }
1869 }
1870
1871 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 1872
55db890a
PO		 1873 /*
1874 * Maximum block count.
1875 */
1388eefd 1876 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 1877
d129bceb
PO		 1878 /*
1879 * Init tasklets.
1880 */
1881 tasklet_init(&host->card_tasklet,
1882 sdhci_tasklet_card, (unsigned long)host);
1883 tasklet_init(&host->finish_tasklet,
1884 sdhci_tasklet_finish, (unsigned long)host);
1885
e4cad1b5 1886 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 1887
dace1453 1888 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 1889 mmc_hostname(mmc), host);
d129bceb 1890 if (ret)
8ef1a143 1891 goto untasklet;
d129bceb 1892
2f4cbb3d 1893 sdhci_init(host, 0);
d129bceb
PO		 1894
1895#ifdef CONFIG_MMC_DEBUG
1896 sdhci_dumpregs(host);
1897#endif
1898
f9134319 1899#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 1900 snprintf(host->led_name, sizeof(host->led_name),
1901 "%s::", mmc_hostname(mmc));
1902 host->led.name = host->led_name;
2f730fec
PO		 1903 host->led.brightness = LED_OFF;
1904 host->led.default_trigger = mmc_hostname(mmc);
1905 host->led.brightness_set = sdhci_led_control;
1906
b8c86fc5 1907 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 1908 if (ret)
1909 goto reset;
1910#endif
1911
5f25a66f
PO		 1912 mmiowb();
1913
d129bceb
PO		 1914 mmc_add_host(mmc);
1915
a13abc7b 1916 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 1917 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 1918 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
1919 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 1920
7260cf5e
AV		 1921 sdhci_enable_card_detection(host);
1922
d129bceb
PO		 1923 return 0;
1924
f9134319 1925#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 1926reset:
1927 sdhci_reset(host, SDHCI_RESET_ALL);
1928 free_irq(host->irq, host);
1929#endif
8ef1a143 1930untasklet:
d129bceb
PO		 1931 tasklet_kill(&host->card_tasklet);
1932 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 1933
1934 return ret;
1935}
1936
b8c86fc5 1937EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 1938
1e72859e 1939void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 1940{
1e72859e
PO		 1941 unsigned long flags;
1942
1943 if (dead) {
1944 spin_lock_irqsave(&host->lock, flags);
1945
1946 host->flags |= SDHCI_DEVICE_DEAD;
1947
1948 if (host->mrq) {
1949 printk(KERN_ERR "%s: Controller removed during "
1950 " transfer!\n", mmc_hostname(host->mmc));
1951
1952 host->mrq->cmd->error = -ENOMEDIUM;
1953 tasklet_schedule(&host->finish_tasklet);
1954 }
1955
1956 spin_unlock_irqrestore(&host->lock, flags);
1957 }
1958
7260cf5e
AV		 1959 sdhci_disable_card_detection(host);
1960
b8c86fc5 1961 mmc_remove_host(host->mmc);
d129bceb 1962
f9134319 1963#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 1964 led_classdev_unregister(&host->led);
1965#endif
1966
1e72859e
PO		 1967 if (!dead)
1968 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 1969
1970 free_irq(host->irq, host);
1971
1972 del_timer_sync(&host->timer);
1973
1974 tasklet_kill(&host->card_tasklet);
1975 tasklet_kill(&host->finish_tasklet);
2134a922
PO		 1976
1977 kfree(host->adma_desc);
1978 kfree(host->align_buffer);
1979
1980 host->adma_desc = NULL;
1981 host->align_buffer = NULL;
d129bceb
PO		 1982}
1983
b8c86fc5 1984EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 1985
b8c86fc5 1986void sdhci_free_host(struct sdhci_host *host)
d129bceb 1987{
b8c86fc5 1988 mmc_free_host(host->mmc);
d129bceb
PO		 1989}
1990
b8c86fc5 1991EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 1992
1993/*****************************************************************************\
1994 * *
1995 * Driver init/exit *
1996 * *
1997\*****************************************************************************/
1998
1999static int __init sdhci_drv_init(void)
2000{
2001 printk(KERN_INFO DRIVER_NAME
52fbf9c9 2002 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 2003 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2004
b8c86fc5 2005 return 0;
d129bceb
PO		 2006}
2007
2008static void __exit sdhci_drv_exit(void)
2009{
d129bceb
PO		 2010}
2011
2012module_init(sdhci_drv_init);
2013module_exit(sdhci_drv_exit);
2014
df673b22 2015module_param(debug_quirks, uint, 0444);
67435274 2016
32710e8f 2017MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 2018MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 2019MODULE_LICENSE("GPL");
67435274 2020
df673b22 2021MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
kernel source for telekom puls (alcatel/mediatek)