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mfd: ab8500-gpadc: Add gpadc hw conversion
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mfd / ab8500-core.c
CommitLineData
62579266
RV		 1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
6 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
adceed62 7 * Author: Mattias Wallin <mattias.wallin@stericsson.com>
62579266
RV		 8 */
9
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/init.h>
13#include <linux/irq.h>
06e589ef 14#include <linux/irqdomain.h>
62579266
RV		 15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/mfd/core.h>
47c16975 20#include <linux/mfd/abx500.h>
ee66e653 21#include <linux/mfd/abx500/ab8500.h>
00441b5e 22#include <linux/mfd/abx500/ab8500-bm.h>
d28f1db8 23#include <linux/mfd/dbx500-prcmu.h>
549931f9 24#include <linux/regulator/ab8500.h>
6bc4a568
LJ		 25#include <linux/of.h>
26#include <linux/of_device.h>
62579266
RV		 27
28/*
29 * Interrupt register offsets
30 * Bank : 0x0E
31 */
47c16975
MW		 32#define AB8500_IT_SOURCE1_REG 0x00
33#define AB8500_IT_SOURCE2_REG 0x01
34#define AB8500_IT_SOURCE3_REG 0x02
35#define AB8500_IT_SOURCE4_REG 0x03
36#define AB8500_IT_SOURCE5_REG 0x04
37#define AB8500_IT_SOURCE6_REG 0x05
38#define AB8500_IT_SOURCE7_REG 0x06
39#define AB8500_IT_SOURCE8_REG 0x07
d6255529 40#define AB9540_IT_SOURCE13_REG 0x0C
47c16975
MW		 41#define AB8500_IT_SOURCE19_REG 0x12
42#define AB8500_IT_SOURCE20_REG 0x13
43#define AB8500_IT_SOURCE21_REG 0x14
44#define AB8500_IT_SOURCE22_REG 0x15
45#define AB8500_IT_SOURCE23_REG 0x16
46#define AB8500_IT_SOURCE24_REG 0x17
62579266
RV		 47
48/*
49 * latch registers
50 */
47c16975
MW		 51#define AB8500_IT_LATCH1_REG 0x20
52#define AB8500_IT_LATCH2_REG 0x21
53#define AB8500_IT_LATCH3_REG 0x22
54#define AB8500_IT_LATCH4_REG 0x23
55#define AB8500_IT_LATCH5_REG 0x24
56#define AB8500_IT_LATCH6_REG 0x25
57#define AB8500_IT_LATCH7_REG 0x26
58#define AB8500_IT_LATCH8_REG 0x27
59#define AB8500_IT_LATCH9_REG 0x28
60#define AB8500_IT_LATCH10_REG 0x29
92d50a41 61#define AB8500_IT_LATCH12_REG 0x2B
d6255529 62#define AB9540_IT_LATCH13_REG 0x2C
47c16975
MW		 63#define AB8500_IT_LATCH19_REG 0x32
64#define AB8500_IT_LATCH20_REG 0x33
65#define AB8500_IT_LATCH21_REG 0x34
66#define AB8500_IT_LATCH22_REG 0x35
67#define AB8500_IT_LATCH23_REG 0x36
68#define AB8500_IT_LATCH24_REG 0x37
62579266
RV		 69
70/*
71 * mask registers
72 */
73
47c16975
MW		 74#define AB8500_IT_MASK1_REG 0x40
75#define AB8500_IT_MASK2_REG 0x41
76#define AB8500_IT_MASK3_REG 0x42
77#define AB8500_IT_MASK4_REG 0x43
78#define AB8500_IT_MASK5_REG 0x44
79#define AB8500_IT_MASK6_REG 0x45
80#define AB8500_IT_MASK7_REG 0x46
81#define AB8500_IT_MASK8_REG 0x47
82#define AB8500_IT_MASK9_REG 0x48
83#define AB8500_IT_MASK10_REG 0x49
84#define AB8500_IT_MASK11_REG 0x4A
85#define AB8500_IT_MASK12_REG 0x4B
86#define AB8500_IT_MASK13_REG 0x4C
87#define AB8500_IT_MASK14_REG 0x4D
88#define AB8500_IT_MASK15_REG 0x4E
89#define AB8500_IT_MASK16_REG 0x4F
90#define AB8500_IT_MASK17_REG 0x50
91#define AB8500_IT_MASK18_REG 0x51
92#define AB8500_IT_MASK19_REG 0x52
93#define AB8500_IT_MASK20_REG 0x53
94#define AB8500_IT_MASK21_REG 0x54
95#define AB8500_IT_MASK22_REG 0x55
96#define AB8500_IT_MASK23_REG 0x56
97#define AB8500_IT_MASK24_REG 0x57
98
7ccfe9b1
MJ		 99/*
100 * latch hierarchy registers
101 */
102#define AB8500_IT_LATCHHIER1_REG 0x60
103#define AB8500_IT_LATCHHIER2_REG 0x61
104#define AB8500_IT_LATCHHIER3_REG 0x62
105
106#define AB8500_IT_LATCHHIER_NUM 3
107
47c16975 108#define AB8500_REV_REG 0x80
0f620837 109#define AB8500_IC_NAME_REG 0x82
e5c238c3 110#define AB8500_SWITCH_OFF_STATUS 0x00
62579266 111
b4a31037
AL		 112#define AB8500_TURN_ON_STATUS 0x00
113
f04a9d8a
RK		 114#define AB8500_CH_USBCH_STAT1_REG 0x02
115#define VBUS_DET_DBNC100 0x02
116#define VBUS_DET_DBNC1 0x01
117
118static DEFINE_SPINLOCK(on_stat_lock);
119static u8 turn_on_stat_mask = 0xFF;
120static u8 turn_on_stat_set;
6ef9418c
RA		 121static bool no_bm; /* No battery management */
122module_param(no_bm, bool, S_IRUGO);
123
d6255529
LW		 124#define AB9540_MODEM_CTRL2_REG 0x23
125#define AB9540_MODEM_CTRL2_SWDBBRSTN_BIT BIT(2)
126
62579266
RV		 127/*
128 * Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
2ced445e
LW		 129 * numbers are indexed into this array with (num / 8). The interupts are
130 * defined in linux/mfd/ab8500.h
62579266
RV		 131 *
132 * This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at
133 * offset 0.
134 */
2ced445e 135/* AB8500 support */
62579266 136static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = {
92d50a41 137 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21,
62579266
RV		 138};
139
d6255529
LW		 140/* AB9540 support */
141static const int ab9540_irq_regoffset[AB9540_NUM_IRQ_REGS] = {
142 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21, 12, 13, 24,
143};
144
0f620837
LW		 145static const char ab8500_version_str[][7] = {
146 [AB8500_VERSION_AB8500] = "AB8500",
147 [AB8500_VERSION_AB8505] = "AB8505",
148 [AB8500_VERSION_AB9540] = "AB9540",
149 [AB8500_VERSION_AB8540] = "AB8540",
150};
151
822672a7 152static int ab8500_prcmu_write(struct ab8500 *ab8500, u16 addr, u8 data)
d28f1db8
LJ		 153{
154 int ret;
155
156 ret = prcmu_abb_write((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1);
157 if (ret < 0)
158 dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
159 return ret;
160}
161
822672a7 162static int ab8500_prcmu_write_masked(struct ab8500 *ab8500, u16 addr, u8 mask,
d28f1db8
LJ		 163 u8 data)
164{
165 int ret;
166
167 ret = prcmu_abb_write_masked((u8)(addr >> 8), (u8)(addr & 0xFF), &data,
168 &mask, 1);
169 if (ret < 0)
170 dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
171 return ret;
172}
173
822672a7 174static int ab8500_prcmu_read(struct ab8500 *ab8500, u16 addr)
d28f1db8
LJ		 175{
176 int ret;
177 u8 data;
178
179 ret = prcmu_abb_read((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1);
180 if (ret < 0) {
181 dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
182 return ret;
183 }
184 return (int)data;
185}
186
47c16975
MW		 187static int ab8500_get_chip_id(struct device *dev)
188{
6bce7bf1
MW		 189 struct ab8500 *ab8500;
190
191 if (!dev)
192 return -EINVAL;
193 ab8500 = dev_get_drvdata(dev->parent);
194 return ab8500 ? (int)ab8500->chip_id : -EINVAL;
47c16975
MW		 195}
196
197static int set_register_interruptible(struct ab8500 *ab8500, u8 bank,
198 u8 reg, u8 data)
62579266
RV		 199{
200 int ret;
47c16975
MW		 201 /*
202 * Put the u8 bank and u8 register together into a an u16.
203 * The bank on higher 8 bits and register in lower 8 bits.
204 * */
205 u16 addr = ((u16)bank) << 8 | reg;
62579266
RV		 206
207 dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data);
208
392cbd1e 209 mutex_lock(&ab8500->lock);
47c16975 210
62579266
RV		 211 ret = ab8500->write(ab8500, addr, data);
212 if (ret < 0)
213 dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
214 addr, ret);
47c16975 215 mutex_unlock(&ab8500->lock);
62579266
RV		 216
217 return ret;
218}
219
47c16975
MW		 220static int ab8500_set_register(struct device *dev, u8 bank,
221 u8 reg, u8 value)
62579266 222{
112a80d2 223 int ret;
47c16975 224 struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
62579266 225
112a80d2
JA		 226 atomic_inc(&ab8500->transfer_ongoing);
227 ret = set_register_interruptible(ab8500, bank, reg, value);
228 atomic_dec(&ab8500->transfer_ongoing);
229 return ret;
62579266 230}
62579266 231
47c16975
MW		 232static int get_register_interruptible(struct ab8500 *ab8500, u8 bank,
233 u8 reg, u8 *value)
62579266
RV		 234{
235 int ret;
47c16975
MW		 236 /* put the u8 bank and u8 reg together into a an u16.
237 * bank on higher 8 bits and reg in lower */
238 u16 addr = ((u16)bank) << 8 | reg;
239
392cbd1e 240 mutex_lock(&ab8500->lock);
62579266
RV		 241
242 ret = ab8500->read(ab8500, addr);
243 if (ret < 0)
244 dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
245 addr, ret);
47c16975
MW		 246 else
247 *value = ret;
62579266 248
47c16975 249 mutex_unlock(&ab8500->lock);
62579266
RV		 250 dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret);
251
252 return ret;
253}
254
47c16975
MW		 255static int ab8500_get_register(struct device *dev, u8 bank,
256 u8 reg, u8 *value)
62579266 257{
112a80d2 258 int ret;
47c16975 259 struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
62579266 260
112a80d2
JA		 261 atomic_inc(&ab8500->transfer_ongoing);
262 ret = get_register_interruptible(ab8500, bank, reg, value);
263 atomic_dec(&ab8500->transfer_ongoing);
264 return ret;
62579266 265}
47c16975
MW		 266
267static int mask_and_set_register_interruptible(struct ab8500 *ab8500, u8 bank,
268 u8 reg, u8 bitmask, u8 bitvalues)
62579266
RV		 269{
270 int ret;
47c16975
MW		 271 /* put the u8 bank and u8 reg together into a an u16.
272 * bank on higher 8 bits and reg in lower */
273 u16 addr = ((u16)bank) << 8 | reg;
62579266 274
392cbd1e 275 mutex_lock(&ab8500->lock);
62579266 276
bc628fd1
MN		 277 if (ab8500->write_masked == NULL) {
278 u8 data;
62579266 279
bc628fd1
MN		 280 ret = ab8500->read(ab8500, addr);
281 if (ret < 0) {
282 dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
283 addr, ret);
284 goto out;
285 }
62579266 286
bc628fd1
MN		 287 data = (u8)ret;
288 data = (~bitmask & data) | (bitmask & bitvalues);
289
290 ret = ab8500->write(ab8500, addr, data);
291 if (ret < 0)
292 dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
293 addr, ret);
62579266 294
bc628fd1
MN		 295 dev_vdbg(ab8500->dev, "mask: addr %#x => data %#x\n", addr,
296 data);
297 goto out;
298 }
299 ret = ab8500->write_masked(ab8500, addr, bitmask, bitvalues);
300 if (ret < 0)
301 dev_err(ab8500->dev, "failed to modify reg %#x: %d\n", addr,
302 ret);
62579266
RV		 303out:
304 mutex_unlock(&ab8500->lock);
305 return ret;
306}
47c16975
MW		 307
308static int ab8500_mask_and_set_register(struct device *dev,
309 u8 bank, u8 reg, u8 bitmask, u8 bitvalues)
310{
112a80d2 311 int ret;
47c16975
MW		 312 struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
313
112a80d2
JA		 314 atomic_inc(&ab8500->transfer_ongoing);
315 ret= mask_and_set_register_interruptible(ab8500, bank, reg,
316 bitmask, bitvalues);
317 atomic_dec(&ab8500->transfer_ongoing);
318 return ret;
47c16975
MW		 319}
320
321static struct abx500_ops ab8500_ops = {
322 .get_chip_id = ab8500_get_chip_id,
323 .get_register = ab8500_get_register,
324 .set_register = ab8500_set_register,
325 .get_register_page = NULL,
326 .set_register_page = NULL,
327 .mask_and_set_register = ab8500_mask_and_set_register,
328 .event_registers_startup_state_get = NULL,
329 .startup_irq_enabled = NULL,
1d843a6c 330 .dump_all_banks = ab8500_dump_all_banks,
47c16975 331};
62579266 332
9505a0a0 333static void ab8500_irq_lock(struct irq_data *data)
62579266 334{
9505a0a0 335 struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
62579266
RV		 336
337 mutex_lock(&ab8500->irq_lock);
112a80d2 338 atomic_inc(&ab8500->transfer_ongoing);
62579266
RV		 339}
340
9505a0a0 341static void ab8500_irq_sync_unlock(struct irq_data *data)
62579266 342{
9505a0a0 343 struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
62579266
RV		 344 int i;
345
2ced445e 346 for (i = 0; i < ab8500->mask_size; i++) {
62579266
RV		 347 u8 old = ab8500->oldmask[i];
348 u8 new = ab8500->mask[i];
349 int reg;
350
351 if (new == old)
352 continue;
353
0f620837
LW		 354 /*
355 * Interrupt register 12 doesn't exist prior to AB8500 version
356 * 2.0
357 */
358 if (ab8500->irq_reg_offset[i] == 11 &&
359 is_ab8500_1p1_or_earlier(ab8500))
92d50a41
MW		 360 continue;
361
62579266
RV		 362 ab8500->oldmask[i] = new;
363
2ced445e 364 reg = AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i];
47c16975 365 set_register_interruptible(ab8500, AB8500_INTERRUPT, reg, new);
62579266 366 }
112a80d2 367 atomic_dec(&ab8500->transfer_ongoing);
62579266
RV		 368 mutex_unlock(&ab8500->irq_lock);
369}
370
9505a0a0 371static void ab8500_irq_mask(struct irq_data *data)
62579266 372{
9505a0a0 373 struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
06e589ef 374 int offset = data->hwirq;
62579266
RV		 375 int index = offset / 8;
376 int mask = 1 << (offset % 8);
377
378 ab8500->mask[index] |= mask;
9c677b9b
LJ		 379
380 /* The AB8500 GPIOs have two interrupts each (rising & falling). */
381 if (offset >= AB8500_INT_GPIO6R && offset <= AB8500_INT_GPIO41R)
382 ab8500->mask[index + 2] |= mask;
383 if (offset >= AB9540_INT_GPIO50R && offset <= AB9540_INT_GPIO54R)
384 ab8500->mask[index + 1] |= mask;
385 if (offset == AB8540_INT_GPIO43R || offset == AB8540_INT_GPIO44R)
e2ddf46a
LW		 386 /* Here the falling IRQ is one bit lower */
387 ab8500->mask[index] |= (mask << 1);
62579266
RV		 388}
389
9505a0a0 390static void ab8500_irq_unmask(struct irq_data *data)
62579266 391{
9505a0a0 392 struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
9c677b9b 393 unsigned int type = irqd_get_trigger_type(data);
06e589ef 394 int offset = data->hwirq;
62579266
RV		 395 int index = offset / 8;
396 int mask = 1 << (offset % 8);
397
9c677b9b
LJ		 398 if (type & IRQ_TYPE_EDGE_RISING)
399 ab8500->mask[index] &= ~mask;
400
401 /* The AB8500 GPIOs have two interrupts each (rising & falling). */
402 if (type & IRQ_TYPE_EDGE_FALLING) {
403 if (offset >= AB8500_INT_GPIO6R && offset <= AB8500_INT_GPIO41R)
404 ab8500->mask[index + 2] &= ~mask;
405 else if (offset >= AB9540_INT_GPIO50R && offset <= AB9540_INT_GPIO54R)
406 ab8500->mask[index + 1] &= ~mask;
407 else if (offset == AB8540_INT_GPIO43R || offset == AB8540_INT_GPIO44R)
e2ddf46a
LW		 408 /* Here the falling IRQ is one bit lower */
409 ab8500->mask[index] &= ~(mask << 1);
9c677b9b
LJ		 410 else
411 ab8500->mask[index] &= ~mask;
e2ddf46a 412 } else {
9c677b9b
LJ		 413 /* Satisfies the case where type is not set. */
414 ab8500->mask[index] &= ~mask;
e2ddf46a 415 }
62579266
RV		 416}
417
40f6e5a2
LJ		 418static int ab8500_irq_set_type(struct irq_data *data, unsigned int type)
419{
420 return 0;
62579266
RV		 421}
422
423static struct irq_chip ab8500_irq_chip = {
424 .name = "ab8500",
9505a0a0
MB		 425 .irq_bus_lock = ab8500_irq_lock,
426 .irq_bus_sync_unlock = ab8500_irq_sync_unlock,
427 .irq_mask = ab8500_irq_mask,
e6f9306e 428 .irq_disable = ab8500_irq_mask,
9505a0a0 429 .irq_unmask = ab8500_irq_unmask,
40f6e5a2 430 .irq_set_type = ab8500_irq_set_type,
62579266
RV		 431};
432
7ccfe9b1
MJ		 433static int ab8500_handle_hierarchical_line(struct ab8500 *ab8500,
434 int latch_offset, u8 latch_val)
435{
436 int int_bit = __ffs(latch_val);
437 int line, i;
438
439 do {
440 int_bit = __ffs(latch_val);
441
442 for (i = 0; i < ab8500->mask_size; i++)
443 if (ab8500->irq_reg_offset[i] == latch_offset)
444 break;
445
446 if (i >= ab8500->mask_size) {
447 dev_err(ab8500->dev, "Register offset 0x%2x not declared\n",
448 latch_offset);
449 return -ENXIO;
450 }
451
452 line = (i << 3) + int_bit;
453 latch_val &= ~(1 << int_bit);
454
e2ddf46a
LW		 455 /*
456 * This handles the falling edge hwirqs from the GPIO
457 * lines. Route them back to the line registered for the
458 * rising IRQ, as this is merely a flag for the same IRQ
459 * in linux terms.
460 */
461 if (line >= AB8500_INT_GPIO6F && line <= AB8500_INT_GPIO41F)
462 line -= 16;
463 if (line >= AB9540_INT_GPIO50F && line <= AB9540_INT_GPIO54F)
464 line -= 8;
465 if (line == AB8540_INT_GPIO43F || line == AB8540_INT_GPIO44F)
466 line += 1;
467
7ccfe9b1
MJ		 468 handle_nested_irq(ab8500->irq_base + line);
469 } while (latch_val);
470
471 return 0;
472}
473
474static int ab8500_handle_hierarchical_latch(struct ab8500 *ab8500,
475 int hier_offset, u8 hier_val)
476{
477 int latch_bit, status;
478 u8 latch_offset, latch_val;
479
480 do {
481 latch_bit = __ffs(hier_val);
482 latch_offset = (hier_offset << 3) + latch_bit;
483
484 /* Fix inconsistent ITFromLatch25 bit mapping... */
485 if (unlikely(latch_offset == 17))
486 latch_offset = 24;
487
488 status = get_register_interruptible(ab8500,
489 AB8500_INTERRUPT,
490 AB8500_IT_LATCH1_REG + latch_offset,
491 &latch_val);
492 if (status < 0 || latch_val == 0)
493 goto discard;
494
495 status = ab8500_handle_hierarchical_line(ab8500,
496 latch_offset, latch_val);
497 if (status < 0)
498 return status;
499discard:
500 hier_val &= ~(1 << latch_bit);
501 } while (hier_val);
502
503 return 0;
504}
505
506static irqreturn_t ab8500_hierarchical_irq(int irq, void *dev)
507{
508 struct ab8500 *ab8500 = dev;
509 u8 i;
510
511 dev_vdbg(ab8500->dev, "interrupt\n");
512
513 /* Hierarchical interrupt version */
514 for (i = 0; i < AB8500_IT_LATCHHIER_NUM; i++) {
515 int status;
516 u8 hier_val;
517
518 status = get_register_interruptible(ab8500, AB8500_INTERRUPT,
519 AB8500_IT_LATCHHIER1_REG + i, &hier_val);
520 if (status < 0 || hier_val == 0)
521 continue;
522
523 status = ab8500_handle_hierarchical_latch(ab8500, i, hier_val);
524 if (status < 0)
525 break;
526 }
527 return IRQ_HANDLED;
528}
529
80633f05
LJ		 530/**
531 * ab8500_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
532 *
533 * @ab8500: ab8500_irq controller to operate on.
534 * @irq: index of the interrupt requested in the chip IRQs
535 *
536 * Useful for drivers to request their own IRQs.
537 */
538static int ab8500_irq_get_virq(struct ab8500 *ab8500, int irq)
539{
540 if (!ab8500)
541 return -EINVAL;
542
543 return irq_create_mapping(ab8500->domain, irq);
544}
545
62579266
RV		 546static irqreturn_t ab8500_irq(int irq, void *dev)
547{
548 struct ab8500 *ab8500 = dev;
549 int i;
550
551 dev_vdbg(ab8500->dev, "interrupt\n");
552
112a80d2
JA		 553 atomic_inc(&ab8500->transfer_ongoing);
554
2ced445e
LW		 555 for (i = 0; i < ab8500->mask_size; i++) {
556 int regoffset = ab8500->irq_reg_offset[i];
62579266 557 int status;
47c16975 558 u8 value;
62579266 559
0f620837
LW		 560 /*
561 * Interrupt register 12 doesn't exist prior to AB8500 version
562 * 2.0
563 */
564 if (regoffset == 11 && is_ab8500_1p1_or_earlier(ab8500))
92d50a41
MW		 565 continue;
566
47c16975
MW		 567 status = get_register_interruptible(ab8500, AB8500_INTERRUPT,
568 AB8500_IT_LATCH1_REG + regoffset, &value);
569 if (status < 0 || value == 0)
62579266
RV		 570 continue;
571
572 do {
88aec4f7 573 int bit = __ffs(value);
62579266 574 int line = i * 8 + bit;
0a37fc56 575 int virq = ab8500_irq_get_virq(ab8500, line);
62579266 576
0a37fc56 577 handle_nested_irq(virq);
8f0eb43b 578 ab8500_debug_register_interrupt(line);
47c16975 579 value &= ~(1 << bit);
112a80d2 580
47c16975 581 } while (value);
62579266 582 }
112a80d2 583 atomic_dec(&ab8500->transfer_ongoing);
62579266
RV		 584 return IRQ_HANDLED;
585}
586
06e589ef
LJ		 587static int ab8500_irq_map(struct irq_domain *d, unsigned int virq,
588 irq_hw_number_t hwirq)
589{
590 struct ab8500 *ab8500 = d->host_data;
591
592 if (!ab8500)
593 return -EINVAL;
594
595 irq_set_chip_data(virq, ab8500);
596 irq_set_chip_and_handler(virq, &ab8500_irq_chip,
597 handle_simple_irq);
598 irq_set_nested_thread(virq, 1);
62579266 599#ifdef CONFIG_ARM
06e589ef 600 set_irq_flags(virq, IRQF_VALID);
62579266 601#else
06e589ef 602 irq_set_noprobe(virq);
62579266 603#endif
62579266
RV		 604
605 return 0;
606}
607
06e589ef
LJ		 608static struct irq_domain_ops ab8500_irq_ops = {
609 .map = ab8500_irq_map,
610 .xlate = irq_domain_xlate_twocell,
611};
612
613static int ab8500_irq_init(struct ab8500 *ab8500, struct device_node *np)
62579266 614{
2ced445e
LW		 615 int num_irqs;
616
d6255529
LW		 617 if (is_ab9540(ab8500))
618 num_irqs = AB9540_NR_IRQS;
a982362c
BJ		 619 else if (is_ab8505(ab8500))
620 num_irqs = AB8505_NR_IRQS;
d6255529
LW		 621 else
622 num_irqs = AB8500_NR_IRQS;
62579266 623
f1d11f39
LW		 624 /* If ->irq_base is zero this will give a linear mapping */
625 ab8500->domain = irq_domain_add_simple(NULL,
626 num_irqs, ab8500->irq_base,
627 &ab8500_irq_ops, ab8500);
06e589ef
LJ		 628
629 if (!ab8500->domain) {
630 dev_err(ab8500->dev, "Failed to create irqdomain\n");
631 return -ENOSYS;
632 }
633
634 return 0;
62579266
RV		 635}
636
112a80d2
JA		 637int ab8500_suspend(struct ab8500 *ab8500)
638{
639 if (atomic_read(&ab8500->transfer_ongoing))
640 return -EINVAL;
641 else
642 return 0;
643}
644
a9e9ce4c 645static struct resource ab8500_gpadc_resources[] = {
62579266
RV		 646 {
647 .name = "HW_CONV_END",
648 .start = AB8500_INT_GP_HW_ADC_CONV_END,
649 .end = AB8500_INT_GP_HW_ADC_CONV_END,
650 .flags = IORESOURCE_IRQ,
651 },
652 {
653 .name = "SW_CONV_END",
654 .start = AB8500_INT_GP_SW_ADC_CONV_END,
655 .end = AB8500_INT_GP_SW_ADC_CONV_END,
656 .flags = IORESOURCE_IRQ,
657 },
658};
659
a9e9ce4c 660static struct resource ab8500_rtc_resources[] = {
62579266
RV		 661 {
662 .name = "60S",
663 .start = AB8500_INT_RTC_60S,
664 .end = AB8500_INT_RTC_60S,
665 .flags = IORESOURCE_IRQ,
666 },
667 {
668 .name = "ALARM",
669 .start = AB8500_INT_RTC_ALARM,
670 .end = AB8500_INT_RTC_ALARM,
671 .flags = IORESOURCE_IRQ,
672 },
673};
674
a9e9ce4c 675static struct resource ab8500_poweronkey_db_resources[] = {
77686517
SI		 676 {
677 .name = "ONKEY_DBF",
678 .start = AB8500_INT_PON_KEY1DB_F,
679 .end = AB8500_INT_PON_KEY1DB_F,
680 .flags = IORESOURCE_IRQ,
681 },
682 {
683 .name = "ONKEY_DBR",
684 .start = AB8500_INT_PON_KEY1DB_R,
685 .end = AB8500_INT_PON_KEY1DB_R,
686 .flags = IORESOURCE_IRQ,
687 },
688};
689
a9e9ce4c 690static struct resource ab8500_av_acc_detect_resources[] = {
e098aded 691 {
6af75ecd
LW		 692 .name = "ACC_DETECT_1DB_F",
693 .start = AB8500_INT_ACC_DETECT_1DB_F,
694 .end = AB8500_INT_ACC_DETECT_1DB_F,
695 .flags = IORESOURCE_IRQ,
e098aded
MW		 696 },
697 {
6af75ecd
LW		 698 .name = "ACC_DETECT_1DB_R",
699 .start = AB8500_INT_ACC_DETECT_1DB_R,
700 .end = AB8500_INT_ACC_DETECT_1DB_R,
701 .flags = IORESOURCE_IRQ,
702 },
703 {
704 .name = "ACC_DETECT_21DB_F",
705 .start = AB8500_INT_ACC_DETECT_21DB_F,
706 .end = AB8500_INT_ACC_DETECT_21DB_F,
707 .flags = IORESOURCE_IRQ,
708 },
709 {
710 .name = "ACC_DETECT_21DB_R",
711 .start = AB8500_INT_ACC_DETECT_21DB_R,
712 .end = AB8500_INT_ACC_DETECT_21DB_R,
713 .flags = IORESOURCE_IRQ,
714 },
715 {
716 .name = "ACC_DETECT_22DB_F",
717 .start = AB8500_INT_ACC_DETECT_22DB_F,
718 .end = AB8500_INT_ACC_DETECT_22DB_F,
719 .flags = IORESOURCE_IRQ,
e098aded 720 },
6af75ecd
LW		 721 {
722 .name = "ACC_DETECT_22DB_R",
723 .start = AB8500_INT_ACC_DETECT_22DB_R,
724 .end = AB8500_INT_ACC_DETECT_22DB_R,
725 .flags = IORESOURCE_IRQ,
726 },
727};
728
a9e9ce4c 729static struct resource ab8500_charger_resources[] = {
e098aded
MW		 730 {
731 .name = "MAIN_CH_UNPLUG_DET",
732 .start = AB8500_INT_MAIN_CH_UNPLUG_DET,
733 .end = AB8500_INT_MAIN_CH_UNPLUG_DET,
734 .flags = IORESOURCE_IRQ,
735 },
736 {
737 .name = "MAIN_CHARGE_PLUG_DET",
738 .start = AB8500_INT_MAIN_CH_PLUG_DET,
739 .end = AB8500_INT_MAIN_CH_PLUG_DET,
740 .flags = IORESOURCE_IRQ,
741 },
e098aded
MW		 742 {
743 .name = "VBUS_DET_R",
744 .start = AB8500_INT_VBUS_DET_R,
745 .end = AB8500_INT_VBUS_DET_R,
746 .flags = IORESOURCE_IRQ,
747 },
748 {
6af75ecd
LW		 749 .name = "VBUS_DET_F",
750 .start = AB8500_INT_VBUS_DET_F,
751 .end = AB8500_INT_VBUS_DET_F,
e098aded
MW		 752 .flags = IORESOURCE_IRQ,
753 },
754 {
6af75ecd
LW		 755 .name = "USB_LINK_STATUS",
756 .start = AB8500_INT_USB_LINK_STATUS,
757 .end = AB8500_INT_USB_LINK_STATUS,
758 .flags = IORESOURCE_IRQ,
759 },
e098aded
MW		 760 {
761 .name = "VBUS_OVV",
762 .start = AB8500_INT_VBUS_OVV,
763 .end = AB8500_INT_VBUS_OVV,
764 .flags = IORESOURCE_IRQ,
765 },
766 {
6af75ecd
LW		 767 .name = "USB_CH_TH_PROT_R",
768 .start = AB8500_INT_USB_CH_TH_PROT_R,
769 .end = AB8500_INT_USB_CH_TH_PROT_R,
e098aded
MW		 770 .flags = IORESOURCE_IRQ,
771 },
772 {
6af75ecd
LW		 773 .name = "USB_CH_TH_PROT_F",
774 .start = AB8500_INT_USB_CH_TH_PROT_F,
775 .end = AB8500_INT_USB_CH_TH_PROT_F,
e098aded
MW		 776 .flags = IORESOURCE_IRQ,
777 },
778 {
6af75ecd
LW		 779 .name = "MAIN_EXT_CH_NOT_OK",
780 .start = AB8500_INT_MAIN_EXT_CH_NOT_OK,
781 .end = AB8500_INT_MAIN_EXT_CH_NOT_OK,
782 .flags = IORESOURCE_IRQ,
783 },
784 {
785 .name = "MAIN_CH_TH_PROT_R",
786 .start = AB8500_INT_MAIN_CH_TH_PROT_R,
787 .end = AB8500_INT_MAIN_CH_TH_PROT_R,
788 .flags = IORESOURCE_IRQ,
789 },
790 {
791 .name = "MAIN_CH_TH_PROT_F",
792 .start = AB8500_INT_MAIN_CH_TH_PROT_F,
793 .end = AB8500_INT_MAIN_CH_TH_PROT_F,
794 .flags = IORESOURCE_IRQ,
795 },
796 {
797 .name = "USB_CHARGER_NOT_OKR",
a982362c
BJ		 798 .start = AB8500_INT_USB_CHARGER_NOT_OKR,
799 .end = AB8500_INT_USB_CHARGER_NOT_OKR,
6af75ecd
LW		 800 .flags = IORESOURCE_IRQ,
801 },
802 {
803 .name = "CH_WD_EXP",
804 .start = AB8500_INT_CH_WD_EXP,
805 .end = AB8500_INT_CH_WD_EXP,
806 .flags = IORESOURCE_IRQ,
807 },
34c11a70
POH		 808 {
809 .name = "VBUS_CH_DROP_END",
810 .start = AB8500_INT_VBUS_CH_DROP_END,
811 .end = AB8500_INT_VBUS_CH_DROP_END,
812 .flags = IORESOURCE_IRQ,
813 },
6af75ecd
LW		 814};
815
a9e9ce4c 816static struct resource ab8500_btemp_resources[] = {
6af75ecd
LW		 817 {
818 .name = "BAT_CTRL_INDB",
819 .start = AB8500_INT_BAT_CTRL_INDB,
820 .end = AB8500_INT_BAT_CTRL_INDB,
e098aded
MW		 821 .flags = IORESOURCE_IRQ,
822 },
823 {
824 .name = "BTEMP_LOW",
825 .start = AB8500_INT_BTEMP_LOW,
826 .end = AB8500_INT_BTEMP_LOW,
827 .flags = IORESOURCE_IRQ,
828 },
829 {
830 .name = "BTEMP_HIGH",
831 .start = AB8500_INT_BTEMP_HIGH,
832 .end = AB8500_INT_BTEMP_HIGH,
833 .flags = IORESOURCE_IRQ,
834 },
835 {
6af75ecd
LW		 836 .name = "BTEMP_LOW_MEDIUM",
837 .start = AB8500_INT_BTEMP_LOW_MEDIUM,
838 .end = AB8500_INT_BTEMP_LOW_MEDIUM,
e098aded
MW		 839 .flags = IORESOURCE_IRQ,
840 },
841 {
6af75ecd
LW		 842 .name = "BTEMP_MEDIUM_HIGH",
843 .start = AB8500_INT_BTEMP_MEDIUM_HIGH,
844 .end = AB8500_INT_BTEMP_MEDIUM_HIGH,
e098aded
MW		 845 .flags = IORESOURCE_IRQ,
846 },
6af75ecd
LW		 847};
848
a9e9ce4c 849static struct resource ab8500_fg_resources[] = {
e098aded 850 {
6af75ecd
LW		 851 .name = "NCONV_ACCU",
852 .start = AB8500_INT_CCN_CONV_ACC,
853 .end = AB8500_INT_CCN_CONV_ACC,
e098aded
MW		 854 .flags = IORESOURCE_IRQ,
855 },
856 {
6af75ecd
LW		 857 .name = "BATT_OVV",
858 .start = AB8500_INT_BATT_OVV,
859 .end = AB8500_INT_BATT_OVV,
e098aded
MW		 860 .flags = IORESOURCE_IRQ,
861 },
862 {
6af75ecd
LW		 863 .name = "LOW_BAT_F",
864 .start = AB8500_INT_LOW_BAT_F,
865 .end = AB8500_INT_LOW_BAT_F,
866 .flags = IORESOURCE_IRQ,
867 },
868 {
869 .name = "LOW_BAT_R",
870 .start = AB8500_INT_LOW_BAT_R,
871 .end = AB8500_INT_LOW_BAT_R,
872 .flags = IORESOURCE_IRQ,
873 },
874 {
875 .name = "CC_INT_CALIB",
876 .start = AB8500_INT_CC_INT_CALIB,
877 .end = AB8500_INT_CC_INT_CALIB,
e098aded
MW		 878 .flags = IORESOURCE_IRQ,
879 },
a982362c
BJ		 880 {
881 .name = "CCEOC",
882 .start = AB8500_INT_CCEOC,
883 .end = AB8500_INT_CCEOC,
884 .flags = IORESOURCE_IRQ,
885 },
e098aded
MW		 886};
887
a9e9ce4c 888static struct resource ab8500_chargalg_resources[] = {};
6af75ecd 889
df720647 890#ifdef CONFIG_DEBUG_FS
a9e9ce4c 891static struct resource ab8500_debug_resources[] = {
e098aded
MW		 892 {
893 .name = "IRQ_FIRST",
894 .start = AB8500_INT_MAIN_EXT_CH_NOT_OK,
895 .end = AB8500_INT_MAIN_EXT_CH_NOT_OK,
896 .flags = IORESOURCE_IRQ,
897 },
898 {
899 .name = "IRQ_LAST",
a982362c
BJ		 900 .start = AB8500_INT_XTAL32K_KO,
901 .end = AB8500_INT_XTAL32K_KO,
e098aded
MW		 902 .flags = IORESOURCE_IRQ,
903 },
904};
df720647 905#endif
e098aded 906
a9e9ce4c 907static struct resource ab8500_usb_resources[] = {
e098aded
MW		 908 {
909 .name = "ID_WAKEUP_R",
910 .start = AB8500_INT_ID_WAKEUP_R,
911 .end = AB8500_INT_ID_WAKEUP_R,
912 .flags = IORESOURCE_IRQ,
913 },
914 {
915 .name = "ID_WAKEUP_F",
916 .start = AB8500_INT_ID_WAKEUP_F,
917 .end = AB8500_INT_ID_WAKEUP_F,
918 .flags = IORESOURCE_IRQ,
919 },
920 {
921 .name = "VBUS_DET_F",
922 .start = AB8500_INT_VBUS_DET_F,
923 .end = AB8500_INT_VBUS_DET_F,
924 .flags = IORESOURCE_IRQ,
925 },
926 {
927 .name = "VBUS_DET_R",
928 .start = AB8500_INT_VBUS_DET_R,
929 .end = AB8500_INT_VBUS_DET_R,
930 .flags = IORESOURCE_IRQ,
931 },
92d50a41
MW		 932 {
933 .name = "USB_LINK_STATUS",
934 .start = AB8500_INT_USB_LINK_STATUS,
935 .end = AB8500_INT_USB_LINK_STATUS,
936 .flags = IORESOURCE_IRQ,
937 },
6af75ecd
LW		 938 {
939 .name = "USB_ADP_PROBE_PLUG",
940 .start = AB8500_INT_ADP_PROBE_PLUG,
941 .end = AB8500_INT_ADP_PROBE_PLUG,
942 .flags = IORESOURCE_IRQ,
943 },
944 {
945 .name = "USB_ADP_PROBE_UNPLUG",
946 .start = AB8500_INT_ADP_PROBE_UNPLUG,
947 .end = AB8500_INT_ADP_PROBE_UNPLUG,
948 .flags = IORESOURCE_IRQ,
949 },
e098aded
MW		 950};
951
a9e9ce4c 952static struct resource ab8505_iddet_resources[] = {
44f72e53
VS		 953 {
954 .name = "KeyDeglitch",
955 .start = AB8505_INT_KEYDEGLITCH,
956 .end = AB8505_INT_KEYDEGLITCH,
957 .flags = IORESOURCE_IRQ,
958 },
959 {
960 .name = "KP",
961 .start = AB8505_INT_KP,
962 .end = AB8505_INT_KP,
963 .flags = IORESOURCE_IRQ,
964 },
965 {
966 .name = "IKP",
967 .start = AB8505_INT_IKP,
968 .end = AB8505_INT_IKP,
969 .flags = IORESOURCE_IRQ,
970 },
971 {
972 .name = "IKR",
973 .start = AB8505_INT_IKR,
974 .end = AB8505_INT_IKR,
975 .flags = IORESOURCE_IRQ,
976 },
977 {
978 .name = "KeyStuck",
979 .start = AB8505_INT_KEYSTUCK,
980 .end = AB8505_INT_KEYSTUCK,
981 .flags = IORESOURCE_IRQ,
982 },
983};
984
a9e9ce4c 985static struct resource ab8500_temp_resources[] = {
e098aded 986 {
151621a7 987 .name = "ABX500_TEMP_WARM",
e098aded
MW		 988 .start = AB8500_INT_TEMP_WARM,
989 .end = AB8500_INT_TEMP_WARM,
990 .flags = IORESOURCE_IRQ,
991 },
992};
993
a9e9ce4c 994static struct mfd_cell abx500_common_devs[] = {
5814fc35
MW		 995#ifdef CONFIG_DEBUG_FS
996 {
997 .name = "ab8500-debug",
bad76991 998 .of_compatible = "stericsson,ab8500-debug",
e098aded
MW		 999 .num_resources = ARRAY_SIZE(ab8500_debug_resources),
1000 .resources = ab8500_debug_resources,
5814fc35
MW		 1001 },
1002#endif
e098aded
MW		 1003 {
1004 .name = "ab8500-sysctrl",
bad76991 1005 .of_compatible = "stericsson,ab8500-sysctrl",
e098aded
MW		 1006 },
1007 {
1008 .name = "ab8500-regulator",
bad76991 1009 .of_compatible = "stericsson,ab8500-regulator",
e098aded 1010 },
916a871c
UH		 1011 {
1012 .name = "abx500-clk",
1013 .of_compatible = "stericsson,abx500-clk",
1014 },
62579266
RV		 1015 {
1016 .name = "ab8500-gpadc",
bad76991 1017 .of_compatible = "stericsson,ab8500-gpadc",
62579266
RV		 1018 .num_resources = ARRAY_SIZE(ab8500_gpadc_resources),
1019 .resources = ab8500_gpadc_resources,
1020 },
1021 {
1022 .name = "ab8500-rtc",
bad76991 1023 .of_compatible = "stericsson,ab8500-rtc",
62579266
RV		 1024 .num_resources = ARRAY_SIZE(ab8500_rtc_resources),
1025 .resources = ab8500_rtc_resources,
1026 },
6af75ecd
LW		 1027 {
1028 .name = "ab8500-acc-det",
bad76991 1029 .of_compatible = "stericsson,ab8500-acc-det",
6af75ecd
LW		 1030 .num_resources = ARRAY_SIZE(ab8500_av_acc_detect_resources),
1031 .resources = ab8500_av_acc_detect_resources,
1032 },
e098aded
MW		 1033 {
1034 .name = "ab8500-poweron-key",
bad76991 1035 .of_compatible = "stericsson,ab8500-poweron-key",
e098aded
MW		 1036 .num_resources = ARRAY_SIZE(ab8500_poweronkey_db_resources),
1037 .resources = ab8500_poweronkey_db_resources,
1038 },
f0f05b1c
AM		 1039 {
1040 .name = "ab8500-pwm",
bad76991 1041 .of_compatible = "stericsson,ab8500-pwm",
f0f05b1c
AM		 1042 .id = 1,
1043 },
1044 {
1045 .name = "ab8500-pwm",
bad76991 1046 .of_compatible = "stericsson,ab8500-pwm",
f0f05b1c
AM		 1047 .id = 2,
1048 },
1049 {
1050 .name = "ab8500-pwm",
bad76991 1051 .of_compatible = "stericsson,ab8500-pwm",
f0f05b1c
AM		 1052 .id = 3,
1053 },
bad76991
LJ		 1054 {
1055 .name = "ab8500-leds",
1056 .of_compatible = "stericsson,ab8500-leds",
1057 },
77686517 1058 {
e098aded 1059 .name = "ab8500-denc",
bad76991 1060 .of_compatible = "stericsson,ab8500-denc",
e098aded
MW		 1061 },
1062 {
151621a7
HZ		 1063 .name = "abx500-temp",
1064 .of_compatible = "stericsson,abx500-temp",
e098aded
MW		 1065 .num_resources = ARRAY_SIZE(ab8500_temp_resources),
1066 .resources = ab8500_temp_resources,
77686517 1067 },
62579266
RV		 1068};
1069
a9e9ce4c 1070static struct mfd_cell ab8500_bm_devs[] = {
6ef9418c
RA		 1071 {
1072 .name = "ab8500-charger",
4aef72db 1073 .of_compatible = "stericsson,ab8500-charger",
6ef9418c
RA		 1074 .num_resources = ARRAY_SIZE(ab8500_charger_resources),
1075 .resources = ab8500_charger_resources,
4aef72db
R		 1076 .platform_data = &ab8500_bm_data,
1077 .pdata_size = sizeof(ab8500_bm_data),
6ef9418c
RA		 1078 },
1079 {
1080 .name = "ab8500-btemp",
bd9e8ab2 1081 .of_compatible = "stericsson,ab8500-btemp",
6ef9418c
RA		 1082 .num_resources = ARRAY_SIZE(ab8500_btemp_resources),
1083 .resources = ab8500_btemp_resources,
bd9e8ab2
R		 1084 .platform_data = &ab8500_bm_data,
1085 .pdata_size = sizeof(ab8500_bm_data),
6ef9418c
RA		 1086 },
1087 {
1088 .name = "ab8500-fg",
e0f1abeb 1089 .of_compatible = "stericsson,ab8500-fg",
6ef9418c
RA		 1090 .num_resources = ARRAY_SIZE(ab8500_fg_resources),
1091 .resources = ab8500_fg_resources,
e0f1abeb
R		 1092 .platform_data = &ab8500_bm_data,
1093 .pdata_size = sizeof(ab8500_bm_data),
6ef9418c
RA		 1094 },
1095 {
1096 .name = "ab8500-chargalg",
a12810ab 1097 .of_compatible = "stericsson,ab8500-chargalg",
6ef9418c
RA		 1098 .num_resources = ARRAY_SIZE(ab8500_chargalg_resources),
1099 .resources = ab8500_chargalg_resources,
a12810ab
R		 1100 .platform_data = &ab8500_bm_data,
1101 .pdata_size = sizeof(ab8500_bm_data),
6ef9418c
RA		 1102 },
1103};
1104
a9e9ce4c 1105static struct mfd_cell ab8500_devs[] = {
d6255529 1106 {
7d56a46e 1107 .name = "pinctrl-ab8500",
bad76991 1108 .of_compatible = "stericsson,ab8500-gpio",
d6255529
LW		 1109 },
1110 {
1111 .name = "ab8500-usb",
bad76991 1112 .of_compatible = "stericsson,ab8500-usb",
d6255529
LW		 1113 .num_resources = ARRAY_SIZE(ab8500_usb_resources),
1114 .resources = ab8500_usb_resources,
1115 },
44f72e53
VS		 1116 {
1117 .name = "ab8500-codec",
81a21cdd 1118 .of_compatible = "stericsson,ab8500-codec",
44f72e53 1119 },
d6255529
LW		 1120};
1121
a9e9ce4c 1122static struct mfd_cell ab9540_devs[] = {
d6255529 1123 {
e64d905e
LJ		 1124 .name = "pinctrl-ab9540",
1125 .of_compatible = "stericsson,ab9540-gpio",
d6255529
LW		 1126 },
1127 {
1128 .name = "ab9540-usb",
1129 .num_resources = ARRAY_SIZE(ab8500_usb_resources),
1130 .resources = ab8500_usb_resources,
1131 },
44f72e53
VS		 1132 {
1133 .name = "ab9540-codec",
1134 },
1135};
1136
1137/* Device list common to ab9540 and ab8505 */
a9e9ce4c 1138static struct mfd_cell ab9540_ab8505_devs[] = {
44f72e53
VS		 1139 {
1140 .name = "ab-iddet",
1141 .num_resources = ARRAY_SIZE(ab8505_iddet_resources),
1142 .resources = ab8505_iddet_resources,
1143 },
d6255529
LW		 1144};
1145
cca69b67
MW		 1146static ssize_t show_chip_id(struct device *dev,
1147 struct device_attribute *attr, char *buf)
1148{
1149 struct ab8500 *ab8500;
1150
1151 ab8500 = dev_get_drvdata(dev);
1152 return sprintf(buf, "%#x\n", ab8500 ? ab8500->chip_id : -EINVAL);
1153}
1154
e5c238c3
MW		 1155/*
1156 * ab8500 has switched off due to (SWITCH_OFF_STATUS):
1157 * 0x01 Swoff bit programming
1158 * 0x02 Thermal protection activation
1159 * 0x04 Vbat lower then BattOk falling threshold
1160 * 0x08 Watchdog expired
1161 * 0x10 Non presence of 32kHz clock
1162 * 0x20 Battery level lower than power on reset threshold
1163 * 0x40 Power on key 1 pressed longer than 10 seconds
1164 * 0x80 DB8500 thermal shutdown
1165 */
1166static ssize_t show_switch_off_status(struct device *dev,
1167 struct device_attribute *attr, char *buf)
1168{
1169 int ret;
1170 u8 value;
1171 struct ab8500 *ab8500;
1172
1173 ab8500 = dev_get_drvdata(dev);
1174 ret = get_register_interruptible(ab8500, AB8500_RTC,
1175 AB8500_SWITCH_OFF_STATUS, &value);
1176 if (ret < 0)
1177 return ret;
1178 return sprintf(buf, "%#x\n", value);
1179}
1180
f04a9d8a
RK		 1181/* use mask and set to override the register turn_on_stat value */
1182void ab8500_override_turn_on_stat(u8 mask, u8 set)
1183{
1184 spin_lock(&on_stat_lock);
1185 turn_on_stat_mask = mask;
1186 turn_on_stat_set = set;
1187 spin_unlock(&on_stat_lock);
1188}
1189
b4a31037
AL		 1190/*
1191 * ab8500 has turned on due to (TURN_ON_STATUS):
1192 * 0x01 PORnVbat
1193 * 0x02 PonKey1dbF
1194 * 0x04 PonKey2dbF
1195 * 0x08 RTCAlarm
1196 * 0x10 MainChDet
1197 * 0x20 VbusDet
1198 * 0x40 UsbIDDetect
1199 * 0x80 Reserved
1200 */
1201static ssize_t show_turn_on_status(struct device *dev,
1202 struct device_attribute *attr, char *buf)
1203{
1204 int ret;
1205 u8 value;
1206 struct ab8500 *ab8500;
1207
1208 ab8500 = dev_get_drvdata(dev);
1209 ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK,
1210 AB8500_TURN_ON_STATUS, &value);
1211 if (ret < 0)
1212 return ret;
f04a9d8a
RK		 1213
1214 /*
1215 * In L9540, turn_on_status register is not updated correctly if
1216 * the device is rebooted with AC/USB charger connected. Due to
1217 * this, the device boots android instead of entering into charge
1218 * only mode. Read the AC/USB status register to detect the charger
1219 * presence and update the turn on status manually.
1220 */
1221 if (is_ab9540(ab8500)) {
1222 spin_lock(&on_stat_lock);
1223 value = (value & turn_on_stat_mask) | turn_on_stat_set;
1224 spin_unlock(&on_stat_lock);
1225 }
1226
b4a31037
AL		 1227 return sprintf(buf, "%#x\n", value);
1228}
1229
d6255529
LW		 1230static ssize_t show_ab9540_dbbrstn(struct device *dev,
1231 struct device_attribute *attr, char *buf)
1232{
1233 struct ab8500 *ab8500;
1234 int ret;
1235 u8 value;
1236
1237 ab8500 = dev_get_drvdata(dev);
1238
1239 ret = get_register_interruptible(ab8500, AB8500_REGU_CTRL2,
1240 AB9540_MODEM_CTRL2_REG, &value);
1241 if (ret < 0)
1242 return ret;
1243
1244 return sprintf(buf, "%d\n",
1245 (value & AB9540_MODEM_CTRL2_SWDBBRSTN_BIT) ? 1 : 0);
1246}
1247
1248static ssize_t store_ab9540_dbbrstn(struct device *dev,
1249 struct device_attribute *attr, const char *buf, size_t count)
1250{
1251 struct ab8500 *ab8500;
1252 int ret = count;
1253 int err;
1254 u8 bitvalues;
1255
1256 ab8500 = dev_get_drvdata(dev);
1257
1258 if (count > 0) {
1259 switch (buf[0]) {
1260 case '0':
1261 bitvalues = 0;
1262 break;
1263 case '1':
1264 bitvalues = AB9540_MODEM_CTRL2_SWDBBRSTN_BIT;
1265 break;
1266 default:
1267 goto exit;
1268 }
1269
1270 err = mask_and_set_register_interruptible(ab8500,
1271 AB8500_REGU_CTRL2, AB9540_MODEM_CTRL2_REG,
1272 AB9540_MODEM_CTRL2_SWDBBRSTN_BIT, bitvalues);
1273 if (err)
1274 dev_info(ab8500->dev,
1275 "Failed to set DBBRSTN %c, err %#x\n",
1276 buf[0], err);
1277 }
1278
1279exit:
1280 return ret;
1281}
1282
cca69b67 1283static DEVICE_ATTR(chip_id, S_IRUGO, show_chip_id, NULL);
e5c238c3 1284static DEVICE_ATTR(switch_off_status, S_IRUGO, show_switch_off_status, NULL);
b4a31037 1285static DEVICE_ATTR(turn_on_status, S_IRUGO, show_turn_on_status, NULL);
d6255529
LW		 1286static DEVICE_ATTR(dbbrstn, S_IRUGO | S_IWUSR,
1287 show_ab9540_dbbrstn, store_ab9540_dbbrstn);
cca69b67
MW		 1288
1289static struct attribute *ab8500_sysfs_entries[] = {
1290 &dev_attr_chip_id.attr,
e5c238c3 1291 &dev_attr_switch_off_status.attr,
b4a31037 1292 &dev_attr_turn_on_status.attr,
cca69b67
MW		 1293 NULL,
1294};
1295
d6255529
LW		 1296static struct attribute *ab9540_sysfs_entries[] = {
1297 &dev_attr_chip_id.attr,
1298 &dev_attr_switch_off_status.attr,
1299 &dev_attr_turn_on_status.attr,
1300 &dev_attr_dbbrstn.attr,
1301 NULL,
1302};
1303
cca69b67
MW		 1304static struct attribute_group ab8500_attr_group = {
1305 .attrs = ab8500_sysfs_entries,
1306};
1307
d6255529
LW		 1308static struct attribute_group ab9540_attr_group = {
1309 .attrs = ab9540_sysfs_entries,
1310};
1311
f791be49 1312static int ab8500_probe(struct platform_device *pdev)
62579266 1313{
b04c530c
JA		 1314 static char *switch_off_status[] = {
1315 "Swoff bit programming",
1316 "Thermal protection activation",
1317 "Vbat lower then BattOk falling threshold",
1318 "Watchdog expired",
1319 "Non presence of 32kHz clock",
1320 "Battery level lower than power on reset threshold",
1321 "Power on key 1 pressed longer than 10 seconds",
1322 "DB8500 thermal shutdown"};
d28f1db8
LJ		 1323 struct ab8500_platform_data *plat = dev_get_platdata(&pdev->dev);
1324 const struct platform_device_id *platid = platform_get_device_id(pdev);
6bc4a568
LJ		 1325 enum ab8500_version version = AB8500_VERSION_UNDEFINED;
1326 struct device_node *np = pdev->dev.of_node;
d28f1db8
LJ		 1327 struct ab8500 *ab8500;
1328 struct resource *resource;
62579266
RV		 1329 int ret;
1330 int i;
47c16975 1331 u8 value;
62579266 1332
8c4203cb 1333 ab8500 = devm_kzalloc(&pdev->dev, sizeof *ab8500, GFP_KERNEL);
d28f1db8
LJ		 1334 if (!ab8500)
1335 return -ENOMEM;
1336
62579266
RV		 1337 if (plat)
1338 ab8500->irq_base = plat->irq_base;
1339
d28f1db8
LJ		 1340 ab8500->dev = &pdev->dev;
1341
1342 resource = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
8c4203cb
LJ		 1343 if (!resource)
1344 return -ENODEV;
d28f1db8
LJ		 1345
1346 ab8500->irq = resource->start;
1347
822672a7
LJ		 1348 ab8500->read = ab8500_prcmu_read;
1349 ab8500->write = ab8500_prcmu_write;
1350 ab8500->write_masked = ab8500_prcmu_write_masked;
d28f1db8 1351
62579266
RV		 1352 mutex_init(&ab8500->lock);
1353 mutex_init(&ab8500->irq_lock);
112a80d2 1354 atomic_set(&ab8500->transfer_ongoing, 0);
62579266 1355
d28f1db8
LJ		 1356 platform_set_drvdata(pdev, ab8500);
1357
6bc4a568
LJ		 1358 if (platid)
1359 version = platid->driver_data;
6bc4a568 1360
0f620837
LW		 1361 if (version != AB8500_VERSION_UNDEFINED)
1362 ab8500->version = version;
1363 else {
1364 ret = get_register_interruptible(ab8500, AB8500_MISC,
1365 AB8500_IC_NAME_REG, &value);
1366 if (ret < 0)
8c4203cb 1367 return ret;
0f620837
LW		 1368
1369 ab8500->version = value;
1370 }
1371
47c16975
MW		 1372 ret = get_register_interruptible(ab8500, AB8500_MISC,
1373 AB8500_REV_REG, &value);
62579266 1374 if (ret < 0)
8c4203cb 1375 return ret;
62579266 1376
47c16975 1377 ab8500->chip_id = value;
62579266 1378
0f620837
LW		 1379 dev_info(ab8500->dev, "detected chip, %s rev. %1x.%1x\n",
1380 ab8500_version_str[ab8500->version],
1381 ab8500->chip_id >> 4,
1382 ab8500->chip_id & 0x0F);
1383
d6255529 1384 /* Configure AB8500 or AB9540 IRQ */
a982362c 1385 if (is_ab9540(ab8500) || is_ab8505(ab8500)) {
d6255529
LW		 1386 ab8500->mask_size = AB9540_NUM_IRQ_REGS;
1387 ab8500->irq_reg_offset = ab9540_irq_regoffset;
1388 } else {
1389 ab8500->mask_size = AB8500_NUM_IRQ_REGS;
1390 ab8500->irq_reg_offset = ab8500_irq_regoffset;
1391 }
8c4203cb 1392 ab8500->mask = devm_kzalloc(&pdev->dev, ab8500->mask_size, GFP_KERNEL);
2ced445e
LW		 1393 if (!ab8500->mask)
1394 return -ENOMEM;
8c4203cb
LJ		 1395 ab8500->oldmask = devm_kzalloc(&pdev->dev, ab8500->mask_size, GFP_KERNEL);
1396 if (!ab8500->oldmask)
1397 return -ENOMEM;
1398
e5c238c3
MW		 1399 /*
1400 * ab8500 has switched off due to (SWITCH_OFF_STATUS):
1401 * 0x01 Swoff bit programming
1402 * 0x02 Thermal protection activation
1403 * 0x04 Vbat lower then BattOk falling threshold
1404 * 0x08 Watchdog expired
1405 * 0x10 Non presence of 32kHz clock
1406 * 0x20 Battery level lower than power on reset threshold
1407 * 0x40 Power on key 1 pressed longer than 10 seconds
1408 * 0x80 DB8500 thermal shutdown
1409 */
1410
1411 ret = get_register_interruptible(ab8500, AB8500_RTC,
1412 AB8500_SWITCH_OFF_STATUS, &value);
1413 if (ret < 0)
1414 return ret;
b04c530c
JA		 1415 dev_info(ab8500->dev, "switch off cause(s) (%#x): ", value);
1416
1417 if (value) {
1418 for (i = 0; i < ARRAY_SIZE(switch_off_status); i++) {
1419 if (value & 1)
1420 printk(KERN_CONT " \"%s\"",
1421 switch_off_status[i]);
1422 value = value >> 1;
1423
1424 }
1425 printk(KERN_CONT "\n");
1426 } else {
1427 printk(KERN_CONT " None\n");
1428 }
e5c238c3 1429
62579266
RV		 1430 if (plat && plat->init)
1431 plat->init(ab8500);
f04a9d8a
RK		 1432 if (is_ab9540(ab8500)) {
1433 ret = get_register_interruptible(ab8500, AB8500_CHARGER,
1434 AB8500_CH_USBCH_STAT1_REG, &value);
1435 if (ret < 0)
1436 return ret;
1437 if ((value & VBUS_DET_DBNC1) && (value & VBUS_DET_DBNC100))
1438 ab8500_override_turn_on_stat(~AB8500_POW_KEY_1_ON,
1439 AB8500_VBUS_DET);
1440 }
62579266
RV		 1441
1442 /* Clear and mask all interrupts */
2ced445e 1443 for (i = 0; i < ab8500->mask_size; i++) {
0f620837
LW		 1444 /*
1445 * Interrupt register 12 doesn't exist prior to AB8500 version
1446 * 2.0
1447 */
1448 if (ab8500->irq_reg_offset[i] == 11 &&
1449 is_ab8500_1p1_or_earlier(ab8500))
92d50a41 1450 continue;
62579266 1451
47c16975 1452 get_register_interruptible(ab8500, AB8500_INTERRUPT,
2ced445e 1453 AB8500_IT_LATCH1_REG + ab8500->irq_reg_offset[i],
92d50a41 1454 &value);
47c16975 1455 set_register_interruptible(ab8500, AB8500_INTERRUPT,
2ced445e 1456 AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i], 0xff);
62579266
RV		 1457 }
1458
47c16975
MW		 1459 ret = abx500_register_ops(ab8500->dev, &ab8500_ops);
1460 if (ret)
8c4203cb 1461 return ret;
47c16975 1462
2ced445e 1463 for (i = 0; i < ab8500->mask_size; i++)
62579266
RV		 1464 ab8500->mask[i] = ab8500->oldmask[i] = 0xff;
1465
06e589ef
LJ		 1466 ret = ab8500_irq_init(ab8500, np);
1467 if (ret)
8c4203cb 1468 return ret;
62579266 1469
06e589ef
LJ		 1470 /* Activate this feature only in ab9540 */
1471 /* till tests are done on ab8500 1p2 or later*/
1472 if (is_ab9540(ab8500)) {
8c4203cb
LJ		 1473 ret = devm_request_threaded_irq(&pdev->dev, ab8500->irq, NULL,
1474 ab8500_hierarchical_irq,
1475 IRQF_ONESHOT | IRQF_NO_SUSPEND,
1476 "ab8500", ab8500);
06e589ef
LJ		 1477 }
1478 else {
8c4203cb
LJ		 1479 ret = devm_request_threaded_irq(&pdev->dev, ab8500->irq, NULL,
1480 ab8500_irq,
1481 IRQF_ONESHOT | IRQF_NO_SUSPEND,
1482 "ab8500", ab8500);
62579266 1483 if (ret)
8c4203cb 1484 return ret;
62579266
RV		 1485 }
1486
bad76991
LJ		 1487 ret = mfd_add_devices(ab8500->dev, 0, abx500_common_devs,
1488 ARRAY_SIZE(abx500_common_devs), NULL,
55692af5 1489 ab8500->irq_base, ab8500->domain);
bad76991 1490 if (ret)
8c4203cb 1491 return ret;
d6255529 1492
bad76991
LJ		 1493 if (is_ab9540(ab8500))
1494 ret = mfd_add_devices(ab8500->dev, 0, ab9540_devs,
1495 ARRAY_SIZE(ab9540_devs), NULL,
55692af5 1496 ab8500->irq_base, ab8500->domain);
bad76991
LJ		 1497 else
1498 ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
1499 ARRAY_SIZE(ab8500_devs), NULL,
55692af5 1500 ab8500->irq_base, ab8500->domain);
bad76991 1501 if (ret)
8c4203cb 1502 return ret;
44f72e53 1503
bad76991
LJ		 1504 if (is_ab9540(ab8500) || is_ab8505(ab8500))
1505 ret = mfd_add_devices(ab8500->dev, 0, ab9540_ab8505_devs,
1506 ARRAY_SIZE(ab9540_ab8505_devs), NULL,
55692af5 1507 ab8500->irq_base, ab8500->domain);
bad76991 1508 if (ret)
8c4203cb 1509 return ret;
62579266 1510
6ef9418c
RA		 1511 if (!no_bm) {
1512 /* Add battery management devices */
1513 ret = mfd_add_devices(ab8500->dev, 0, ab8500_bm_devs,
1514 ARRAY_SIZE(ab8500_bm_devs), NULL,
55692af5 1515 ab8500->irq_base, ab8500->domain);
6ef9418c
RA		 1516 if (ret)
1517 dev_err(ab8500->dev, "error adding bm devices\n");
1518 }
1519
d6255529
LW		 1520 if (is_ab9540(ab8500))
1521 ret = sysfs_create_group(&ab8500->dev->kobj,
1522 &ab9540_attr_group);
1523 else
1524 ret = sysfs_create_group(&ab8500->dev->kobj,
1525 &ab8500_attr_group);
cca69b67
MW		 1526 if (ret)
1527 dev_err(ab8500->dev, "error creating sysfs entries\n");
06e589ef
LJ		 1528
1529 return ret;
62579266
RV		 1530}
1531
4740f73f 1532static int ab8500_remove(struct platform_device *pdev)
62579266 1533{
d28f1db8
LJ		 1534 struct ab8500 *ab8500 = platform_get_drvdata(pdev);
1535
d6255529
LW		 1536 if (is_ab9540(ab8500))
1537 sysfs_remove_group(&ab8500->dev->kobj, &ab9540_attr_group);
1538 else
1539 sysfs_remove_group(&ab8500->dev->kobj, &ab8500_attr_group);
06e589ef 1540
62579266 1541 mfd_remove_devices(ab8500->dev);
62579266
RV		 1542
1543 return 0;
1544}
1545
d28f1db8
LJ		 1546static const struct platform_device_id ab8500_id[] = {
1547 { "ab8500-core", AB8500_VERSION_AB8500 },
1548 { "ab8505-i2c", AB8500_VERSION_AB8505 },
1549 { "ab9540-i2c", AB8500_VERSION_AB9540 },
1550 { "ab8540-i2c", AB8500_VERSION_AB8540 },
1551 { }
1552};
1553
1554static struct platform_driver ab8500_core_driver = {
1555 .driver = {
1556 .name = "ab8500-core",
1557 .owner = THIS_MODULE,
1558 },
1559 .probe = ab8500_probe,
84449216 1560 .remove = ab8500_remove,
d28f1db8
LJ		 1561 .id_table = ab8500_id,
1562};
1563
1564static int __init ab8500_core_init(void)
1565{
1566 return platform_driver_register(&ab8500_core_driver);
1567}
1568
1569static void __exit ab8500_core_exit(void)
1570{
1571 platform_driver_unregister(&ab8500_core_driver);
1572}
ba7cbc3e 1573core_initcall(ab8500_core_init);
d28f1db8
LJ		 1574module_exit(ab8500_core_exit);
1575
adceed62 1576MODULE_AUTHOR("Mattias Wallin, Srinidhi Kasagar, Rabin Vincent");
62579266
RV		 1577MODULE_DESCRIPTION("AB8500 MFD core");
1578MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)