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mfd: rtsx: Optimize card detect flow
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mfd / ab8500-core.c
CommitLineData
62579266
RV		 1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
6 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
adceed62 7 * Author: Mattias Wallin <mattias.wallin@stericsson.com>
62579266
RV		 8 */
9
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/init.h>
13#include <linux/irq.h>
06e589ef 14#include <linux/irqdomain.h>
62579266
RV		 15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/mfd/core.h>
47c16975 20#include <linux/mfd/abx500.h>
ee66e653 21#include <linux/mfd/abx500/ab8500.h>
00441b5e 22#include <linux/mfd/abx500/ab8500-bm.h>
d28f1db8 23#include <linux/mfd/dbx500-prcmu.h>
549931f9 24#include <linux/regulator/ab8500.h>
6bc4a568
LJ		 25#include <linux/of.h>
26#include <linux/of_device.h>
62579266
RV		 27
28/*
29 * Interrupt register offsets
30 * Bank : 0x0E
31 */
47c16975
MW		 32#define AB8500_IT_SOURCE1_REG 0x00
33#define AB8500_IT_SOURCE2_REG 0x01
34#define AB8500_IT_SOURCE3_REG 0x02
35#define AB8500_IT_SOURCE4_REG 0x03
36#define AB8500_IT_SOURCE5_REG 0x04
37#define AB8500_IT_SOURCE6_REG 0x05
38#define AB8500_IT_SOURCE7_REG 0x06
39#define AB8500_IT_SOURCE8_REG 0x07
d6255529 40#define AB9540_IT_SOURCE13_REG 0x0C
47c16975
MW		 41#define AB8500_IT_SOURCE19_REG 0x12
42#define AB8500_IT_SOURCE20_REG 0x13
43#define AB8500_IT_SOURCE21_REG 0x14
44#define AB8500_IT_SOURCE22_REG 0x15
45#define AB8500_IT_SOURCE23_REG 0x16
46#define AB8500_IT_SOURCE24_REG 0x17
62579266
RV		 47
48/*
49 * latch registers
50 */
47c16975
MW		 51#define AB8500_IT_LATCH1_REG 0x20
52#define AB8500_IT_LATCH2_REG 0x21
53#define AB8500_IT_LATCH3_REG 0x22
54#define AB8500_IT_LATCH4_REG 0x23
55#define AB8500_IT_LATCH5_REG 0x24
56#define AB8500_IT_LATCH6_REG 0x25
57#define AB8500_IT_LATCH7_REG 0x26
58#define AB8500_IT_LATCH8_REG 0x27
59#define AB8500_IT_LATCH9_REG 0x28
60#define AB8500_IT_LATCH10_REG 0x29
92d50a41 61#define AB8500_IT_LATCH12_REG 0x2B
d6255529 62#define AB9540_IT_LATCH13_REG 0x2C
47c16975
MW		 63#define AB8500_IT_LATCH19_REG 0x32
64#define AB8500_IT_LATCH20_REG 0x33
65#define AB8500_IT_LATCH21_REG 0x34
66#define AB8500_IT_LATCH22_REG 0x35
67#define AB8500_IT_LATCH23_REG 0x36
68#define AB8500_IT_LATCH24_REG 0x37
62579266
RV		 69
70/*
71 * mask registers
72 */
73
47c16975
MW		 74#define AB8500_IT_MASK1_REG 0x40
75#define AB8500_IT_MASK2_REG 0x41
76#define AB8500_IT_MASK3_REG 0x42
77#define AB8500_IT_MASK4_REG 0x43
78#define AB8500_IT_MASK5_REG 0x44
79#define AB8500_IT_MASK6_REG 0x45
80#define AB8500_IT_MASK7_REG 0x46
81#define AB8500_IT_MASK8_REG 0x47
82#define AB8500_IT_MASK9_REG 0x48
83#define AB8500_IT_MASK10_REG 0x49
84#define AB8500_IT_MASK11_REG 0x4A
85#define AB8500_IT_MASK12_REG 0x4B
86#define AB8500_IT_MASK13_REG 0x4C
87#define AB8500_IT_MASK14_REG 0x4D
88#define AB8500_IT_MASK15_REG 0x4E
89#define AB8500_IT_MASK16_REG 0x4F
90#define AB8500_IT_MASK17_REG 0x50
91#define AB8500_IT_MASK18_REG 0x51
92#define AB8500_IT_MASK19_REG 0x52
93#define AB8500_IT_MASK20_REG 0x53
94#define AB8500_IT_MASK21_REG 0x54
95#define AB8500_IT_MASK22_REG 0x55
96#define AB8500_IT_MASK23_REG 0x56
97#define AB8500_IT_MASK24_REG 0x57
98
7ccfe9b1
MJ		 99/*
100 * latch hierarchy registers
101 */
102#define AB8500_IT_LATCHHIER1_REG 0x60
103#define AB8500_IT_LATCHHIER2_REG 0x61
104#define AB8500_IT_LATCHHIER3_REG 0x62
105
106#define AB8500_IT_LATCHHIER_NUM 3
107
47c16975 108#define AB8500_REV_REG 0x80
0f620837 109#define AB8500_IC_NAME_REG 0x82
e5c238c3 110#define AB8500_SWITCH_OFF_STATUS 0x00
62579266 111
b4a31037
AL		 112#define AB8500_TURN_ON_STATUS 0x00
113
6ef9418c
RA		 114static bool no_bm; /* No battery management */
115module_param(no_bm, bool, S_IRUGO);
116
d6255529
LW		 117#define AB9540_MODEM_CTRL2_REG 0x23
118#define AB9540_MODEM_CTRL2_SWDBBRSTN_BIT BIT(2)
119
62579266
RV		 120/*
121 * Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
2ced445e
LW		 122 * numbers are indexed into this array with (num / 8). The interupts are
123 * defined in linux/mfd/ab8500.h
62579266
RV		 124 *
125 * This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at
126 * offset 0.
127 */
2ced445e 128/* AB8500 support */
62579266 129static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = {
92d50a41 130 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21,
62579266
RV		 131};
132
d6255529
LW		 133/* AB9540 support */
134static const int ab9540_irq_regoffset[AB9540_NUM_IRQ_REGS] = {
135 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21, 12, 13, 24,
136};
137
0f620837
LW		 138static const char ab8500_version_str[][7] = {
139 [AB8500_VERSION_AB8500] = "AB8500",
140 [AB8500_VERSION_AB8505] = "AB8505",
141 [AB8500_VERSION_AB9540] = "AB9540",
142 [AB8500_VERSION_AB8540] = "AB8540",
143};
144
822672a7 145static int ab8500_prcmu_write(struct ab8500 *ab8500, u16 addr, u8 data)
d28f1db8
LJ		 146{
147 int ret;
148
149 ret = prcmu_abb_write((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1);
150 if (ret < 0)
151 dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
152 return ret;
153}
154
822672a7 155static int ab8500_prcmu_write_masked(struct ab8500 *ab8500, u16 addr, u8 mask,
d28f1db8
LJ		 156 u8 data)
157{
158 int ret;
159
160 ret = prcmu_abb_write_masked((u8)(addr >> 8), (u8)(addr & 0xFF), &data,
161 &mask, 1);
162 if (ret < 0)
163 dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
164 return ret;
165}
166
822672a7 167static int ab8500_prcmu_read(struct ab8500 *ab8500, u16 addr)
d28f1db8
LJ		 168{
169 int ret;
170 u8 data;
171
172 ret = prcmu_abb_read((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1);
173 if (ret < 0) {
174 dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
175 return ret;
176 }
177 return (int)data;
178}
179
47c16975
MW		 180static int ab8500_get_chip_id(struct device *dev)
181{
6bce7bf1
MW		 182 struct ab8500 *ab8500;
183
184 if (!dev)
185 return -EINVAL;
186 ab8500 = dev_get_drvdata(dev->parent);
187 return ab8500 ? (int)ab8500->chip_id : -EINVAL;
47c16975
MW		 188}
189
190static int set_register_interruptible(struct ab8500 *ab8500, u8 bank,
191 u8 reg, u8 data)
62579266
RV		 192{
193 int ret;
47c16975
MW		 194 /*
195 * Put the u8 bank and u8 register together into a an u16.
196 * The bank on higher 8 bits and register in lower 8 bits.
197 * */
198 u16 addr = ((u16)bank) << 8 | reg;
62579266
RV		 199
200 dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data);
201
392cbd1e 202 mutex_lock(&ab8500->lock);
47c16975 203
62579266
RV		 204 ret = ab8500->write(ab8500, addr, data);
205 if (ret < 0)
206 dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
207 addr, ret);
47c16975 208 mutex_unlock(&ab8500->lock);
62579266
RV		 209
210 return ret;
211}
212
47c16975
MW		 213static int ab8500_set_register(struct device *dev, u8 bank,
214 u8 reg, u8 value)
62579266 215{
112a80d2 216 int ret;
47c16975 217 struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
62579266 218
112a80d2
JA		 219 atomic_inc(&ab8500->transfer_ongoing);
220 ret = set_register_interruptible(ab8500, bank, reg, value);
221 atomic_dec(&ab8500->transfer_ongoing);
222 return ret;
62579266 223}
62579266 224
47c16975
MW		 225static int get_register_interruptible(struct ab8500 *ab8500, u8 bank,
226 u8 reg, u8 *value)
62579266
RV		 227{
228 int ret;
47c16975
MW		 229 /* put the u8 bank and u8 reg together into a an u16.
230 * bank on higher 8 bits and reg in lower */
231 u16 addr = ((u16)bank) << 8 | reg;
232
392cbd1e 233 mutex_lock(&ab8500->lock);
62579266
RV		 234
235 ret = ab8500->read(ab8500, addr);
236 if (ret < 0)
237 dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
238 addr, ret);
47c16975
MW		 239 else
240 *value = ret;
62579266 241
47c16975 242 mutex_unlock(&ab8500->lock);
62579266
RV		 243 dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret);
244
245 return ret;
246}
247
47c16975
MW		 248static int ab8500_get_register(struct device *dev, u8 bank,
249 u8 reg, u8 *value)
62579266 250{
112a80d2 251 int ret;
47c16975 252 struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
62579266 253
112a80d2
JA		 254 atomic_inc(&ab8500->transfer_ongoing);
255 ret = get_register_interruptible(ab8500, bank, reg, value);
256 atomic_dec(&ab8500->transfer_ongoing);
257 return ret;
62579266 258}
47c16975
MW		 259
260static int mask_and_set_register_interruptible(struct ab8500 *ab8500, u8 bank,
261 u8 reg, u8 bitmask, u8 bitvalues)
62579266
RV		 262{
263 int ret;
47c16975
MW		 264 /* put the u8 bank and u8 reg together into a an u16.
265 * bank on higher 8 bits and reg in lower */
266 u16 addr = ((u16)bank) << 8 | reg;
62579266 267
392cbd1e 268 mutex_lock(&ab8500->lock);
62579266 269
bc628fd1
MN		 270 if (ab8500->write_masked == NULL) {
271 u8 data;
62579266 272
bc628fd1
MN		 273 ret = ab8500->read(ab8500, addr);
274 if (ret < 0) {
275 dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
276 addr, ret);
277 goto out;
278 }
62579266 279
bc628fd1
MN		 280 data = (u8)ret;
281 data = (~bitmask & data) | (bitmask & bitvalues);
282
283 ret = ab8500->write(ab8500, addr, data);
284 if (ret < 0)
285 dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
286 addr, ret);
62579266 287
bc628fd1
MN		 288 dev_vdbg(ab8500->dev, "mask: addr %#x => data %#x\n", addr,
289 data);
290 goto out;
291 }
292 ret = ab8500->write_masked(ab8500, addr, bitmask, bitvalues);
293 if (ret < 0)
294 dev_err(ab8500->dev, "failed to modify reg %#x: %d\n", addr,
295 ret);
62579266
RV		 296out:
297 mutex_unlock(&ab8500->lock);
298 return ret;
299}
47c16975
MW		 300
301static int ab8500_mask_and_set_register(struct device *dev,
302 u8 bank, u8 reg, u8 bitmask, u8 bitvalues)
303{
112a80d2 304 int ret;
47c16975
MW		 305 struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
306
112a80d2
JA		 307 atomic_inc(&ab8500->transfer_ongoing);
308 ret= mask_and_set_register_interruptible(ab8500, bank, reg,
309 bitmask, bitvalues);
310 atomic_dec(&ab8500->transfer_ongoing);
311 return ret;
47c16975
MW		 312}
313
314static struct abx500_ops ab8500_ops = {
315 .get_chip_id = ab8500_get_chip_id,
316 .get_register = ab8500_get_register,
317 .set_register = ab8500_set_register,
318 .get_register_page = NULL,
319 .set_register_page = NULL,
320 .mask_and_set_register = ab8500_mask_and_set_register,
321 .event_registers_startup_state_get = NULL,
322 .startup_irq_enabled = NULL,
323};
62579266 324
9505a0a0 325static void ab8500_irq_lock(struct irq_data *data)
62579266 326{
9505a0a0 327 struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
62579266
RV		 328
329 mutex_lock(&ab8500->irq_lock);
112a80d2 330 atomic_inc(&ab8500->transfer_ongoing);
62579266
RV		 331}
332
9505a0a0 333static void ab8500_irq_sync_unlock(struct irq_data *data)
62579266 334{
9505a0a0 335 struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
62579266
RV		 336 int i;
337
2ced445e 338 for (i = 0; i < ab8500->mask_size; i++) {
62579266
RV		 339 u8 old = ab8500->oldmask[i];
340 u8 new = ab8500->mask[i];
341 int reg;
342
343 if (new == old)
344 continue;
345
0f620837
LW		 346 /*
347 * Interrupt register 12 doesn't exist prior to AB8500 version
348 * 2.0
349 */
350 if (ab8500->irq_reg_offset[i] == 11 &&
351 is_ab8500_1p1_or_earlier(ab8500))
92d50a41
MW		 352 continue;
353
62579266
RV		 354 ab8500->oldmask[i] = new;
355
2ced445e 356 reg = AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i];
47c16975 357 set_register_interruptible(ab8500, AB8500_INTERRUPT, reg, new);
62579266 358 }
112a80d2 359 atomic_dec(&ab8500->transfer_ongoing);
62579266
RV		 360 mutex_unlock(&ab8500->irq_lock);
361}
362
9505a0a0 363static void ab8500_irq_mask(struct irq_data *data)
62579266 364{
9505a0a0 365 struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
06e589ef 366 int offset = data->hwirq;
62579266
RV		 367 int index = offset / 8;
368 int mask = 1 << (offset % 8);
369
370 ab8500->mask[index] |= mask;
371}
372
9505a0a0 373static void ab8500_irq_unmask(struct irq_data *data)
62579266 374{
9505a0a0 375 struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
06e589ef 376 int offset = data->hwirq;
62579266
RV		 377 int index = offset / 8;
378 int mask = 1 << (offset % 8);
379
380 ab8500->mask[index] &= ~mask;
381}
382
383static struct irq_chip ab8500_irq_chip = {
384 .name = "ab8500",
9505a0a0
MB		 385 .irq_bus_lock = ab8500_irq_lock,
386 .irq_bus_sync_unlock = ab8500_irq_sync_unlock,
387 .irq_mask = ab8500_irq_mask,
e6f9306e 388 .irq_disable = ab8500_irq_mask,
9505a0a0 389 .irq_unmask = ab8500_irq_unmask,
62579266
RV		 390};
391
7ccfe9b1
MJ		 392static int ab8500_handle_hierarchical_line(struct ab8500 *ab8500,
393 int latch_offset, u8 latch_val)
394{
395 int int_bit = __ffs(latch_val);
396 int line, i;
397
398 do {
399 int_bit = __ffs(latch_val);
400
401 for (i = 0; i < ab8500->mask_size; i++)
402 if (ab8500->irq_reg_offset[i] == latch_offset)
403 break;
404
405 if (i >= ab8500->mask_size) {
406 dev_err(ab8500->dev, "Register offset 0x%2x not declared\n",
407 latch_offset);
408 return -ENXIO;
409 }
410
411 line = (i << 3) + int_bit;
412 latch_val &= ~(1 << int_bit);
413
414 handle_nested_irq(ab8500->irq_base + line);
415 } while (latch_val);
416
417 return 0;
418}
419
420static int ab8500_handle_hierarchical_latch(struct ab8500 *ab8500,
421 int hier_offset, u8 hier_val)
422{
423 int latch_bit, status;
424 u8 latch_offset, latch_val;
425
426 do {
427 latch_bit = __ffs(hier_val);
428 latch_offset = (hier_offset << 3) + latch_bit;
429
430 /* Fix inconsistent ITFromLatch25 bit mapping... */
431 if (unlikely(latch_offset == 17))
432 latch_offset = 24;
433
434 status = get_register_interruptible(ab8500,
435 AB8500_INTERRUPT,
436 AB8500_IT_LATCH1_REG + latch_offset,
437 &latch_val);
438 if (status < 0 || latch_val == 0)
439 goto discard;
440
441 status = ab8500_handle_hierarchical_line(ab8500,
442 latch_offset, latch_val);
443 if (status < 0)
444 return status;
445discard:
446 hier_val &= ~(1 << latch_bit);
447 } while (hier_val);
448
449 return 0;
450}
451
452static irqreturn_t ab8500_hierarchical_irq(int irq, void *dev)
453{
454 struct ab8500 *ab8500 = dev;
455 u8 i;
456
457 dev_vdbg(ab8500->dev, "interrupt\n");
458
459 /* Hierarchical interrupt version */
460 for (i = 0; i < AB8500_IT_LATCHHIER_NUM; i++) {
461 int status;
462 u8 hier_val;
463
464 status = get_register_interruptible(ab8500, AB8500_INTERRUPT,
465 AB8500_IT_LATCHHIER1_REG + i, &hier_val);
466 if (status < 0 || hier_val == 0)
467 continue;
468
469 status = ab8500_handle_hierarchical_latch(ab8500, i, hier_val);
470 if (status < 0)
471 break;
472 }
473 return IRQ_HANDLED;
474}
475
80633f05
LJ		 476/**
477 * ab8500_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
478 *
479 * @ab8500: ab8500_irq controller to operate on.
480 * @irq: index of the interrupt requested in the chip IRQs
481 *
482 * Useful for drivers to request their own IRQs.
483 */
484static int ab8500_irq_get_virq(struct ab8500 *ab8500, int irq)
485{
486 if (!ab8500)
487 return -EINVAL;
488
489 return irq_create_mapping(ab8500->domain, irq);
490}
491
62579266
RV		 492static irqreturn_t ab8500_irq(int irq, void *dev)
493{
494 struct ab8500 *ab8500 = dev;
495 int i;
496
497 dev_vdbg(ab8500->dev, "interrupt\n");
498
112a80d2
JA		 499 atomic_inc(&ab8500->transfer_ongoing);
500
2ced445e
LW		 501 for (i = 0; i < ab8500->mask_size; i++) {
502 int regoffset = ab8500->irq_reg_offset[i];
62579266 503 int status;
47c16975 504 u8 value;
62579266 505
0f620837
LW		 506 /*
507 * Interrupt register 12 doesn't exist prior to AB8500 version
508 * 2.0
509 */
510 if (regoffset == 11 && is_ab8500_1p1_or_earlier(ab8500))
92d50a41
MW		 511 continue;
512
47c16975
MW		 513 status = get_register_interruptible(ab8500, AB8500_INTERRUPT,
514 AB8500_IT_LATCH1_REG + regoffset, &value);
515 if (status < 0 || value == 0)
62579266
RV		 516 continue;
517
518 do {
88aec4f7 519 int bit = __ffs(value);
62579266 520 int line = i * 8 + bit;
0a37fc56 521 int virq = ab8500_irq_get_virq(ab8500, line);
62579266 522
0a37fc56 523 handle_nested_irq(virq);
47c16975 524 value &= ~(1 << bit);
112a80d2 525
47c16975 526 } while (value);
62579266 527 }
112a80d2 528 atomic_dec(&ab8500->transfer_ongoing);
62579266
RV		 529 return IRQ_HANDLED;
530}
531
06e589ef
LJ		 532static int ab8500_irq_map(struct irq_domain *d, unsigned int virq,
533 irq_hw_number_t hwirq)
534{
535 struct ab8500 *ab8500 = d->host_data;
536
537 if (!ab8500)
538 return -EINVAL;
539
540 irq_set_chip_data(virq, ab8500);
541 irq_set_chip_and_handler(virq, &ab8500_irq_chip,
542 handle_simple_irq);
543 irq_set_nested_thread(virq, 1);
62579266 544#ifdef CONFIG_ARM
06e589ef 545 set_irq_flags(virq, IRQF_VALID);
62579266 546#else
06e589ef 547 irq_set_noprobe(virq);
62579266 548#endif
62579266
RV		 549
550 return 0;
551}
552
06e589ef
LJ		 553static struct irq_domain_ops ab8500_irq_ops = {
554 .map = ab8500_irq_map,
555 .xlate = irq_domain_xlate_twocell,
556};
557
558static int ab8500_irq_init(struct ab8500 *ab8500, struct device_node *np)
62579266 559{
2ced445e
LW		 560 int num_irqs;
561
d6255529
LW		 562 if (is_ab9540(ab8500))
563 num_irqs = AB9540_NR_IRQS;
a982362c
BJ		 564 else if (is_ab8505(ab8500))
565 num_irqs = AB8505_NR_IRQS;
d6255529
LW		 566 else
567 num_irqs = AB8500_NR_IRQS;
62579266 568
f1d11f39
LW		 569 /* If ->irq_base is zero this will give a linear mapping */
570 ab8500->domain = irq_domain_add_simple(NULL,
571 num_irqs, ab8500->irq_base,
572 &ab8500_irq_ops, ab8500);
06e589ef
LJ		 573
574 if (!ab8500->domain) {
575 dev_err(ab8500->dev, "Failed to create irqdomain\n");
576 return -ENOSYS;
577 }
578
579 return 0;
62579266
RV		 580}
581
112a80d2
JA		 582int ab8500_suspend(struct ab8500 *ab8500)
583{
584 if (atomic_read(&ab8500->transfer_ongoing))
585 return -EINVAL;
586 else
587 return 0;
588}
589
a9e9ce4c 590static struct resource ab8500_gpadc_resources[] = {
62579266
RV		 591 {
592 .name = "HW_CONV_END",
593 .start = AB8500_INT_GP_HW_ADC_CONV_END,
594 .end = AB8500_INT_GP_HW_ADC_CONV_END,
595 .flags = IORESOURCE_IRQ,
596 },
597 {
598 .name = "SW_CONV_END",
599 .start = AB8500_INT_GP_SW_ADC_CONV_END,
600 .end = AB8500_INT_GP_SW_ADC_CONV_END,
601 .flags = IORESOURCE_IRQ,
602 },
603};
604
a9e9ce4c 605static struct resource ab8500_rtc_resources[] = {
62579266
RV		 606 {
607 .name = "60S",
608 .start = AB8500_INT_RTC_60S,
609 .end = AB8500_INT_RTC_60S,
610 .flags = IORESOURCE_IRQ,
611 },
612 {
613 .name = "ALARM",
614 .start = AB8500_INT_RTC_ALARM,
615 .end = AB8500_INT_RTC_ALARM,
616 .flags = IORESOURCE_IRQ,
617 },
618};
619
a9e9ce4c 620static struct resource ab8500_poweronkey_db_resources[] = {
77686517
SI		 621 {
622 .name = "ONKEY_DBF",
623 .start = AB8500_INT_PON_KEY1DB_F,
624 .end = AB8500_INT_PON_KEY1DB_F,
625 .flags = IORESOURCE_IRQ,
626 },
627 {
628 .name = "ONKEY_DBR",
629 .start = AB8500_INT_PON_KEY1DB_R,
630 .end = AB8500_INT_PON_KEY1DB_R,
631 .flags = IORESOURCE_IRQ,
632 },
633};
634
a9e9ce4c 635static struct resource ab8500_av_acc_detect_resources[] = {
e098aded 636 {
6af75ecd
LW		 637 .name = "ACC_DETECT_1DB_F",
638 .start = AB8500_INT_ACC_DETECT_1DB_F,
639 .end = AB8500_INT_ACC_DETECT_1DB_F,
640 .flags = IORESOURCE_IRQ,
e098aded
MW		 641 },
642 {
6af75ecd
LW		 643 .name = "ACC_DETECT_1DB_R",
644 .start = AB8500_INT_ACC_DETECT_1DB_R,
645 .end = AB8500_INT_ACC_DETECT_1DB_R,
646 .flags = IORESOURCE_IRQ,
647 },
648 {
649 .name = "ACC_DETECT_21DB_F",
650 .start = AB8500_INT_ACC_DETECT_21DB_F,
651 .end = AB8500_INT_ACC_DETECT_21DB_F,
652 .flags = IORESOURCE_IRQ,
653 },
654 {
655 .name = "ACC_DETECT_21DB_R",
656 .start = AB8500_INT_ACC_DETECT_21DB_R,
657 .end = AB8500_INT_ACC_DETECT_21DB_R,
658 .flags = IORESOURCE_IRQ,
659 },
660 {
661 .name = "ACC_DETECT_22DB_F",
662 .start = AB8500_INT_ACC_DETECT_22DB_F,
663 .end = AB8500_INT_ACC_DETECT_22DB_F,
664 .flags = IORESOURCE_IRQ,
e098aded 665 },
6af75ecd
LW		 666 {
667 .name = "ACC_DETECT_22DB_R",
668 .start = AB8500_INT_ACC_DETECT_22DB_R,
669 .end = AB8500_INT_ACC_DETECT_22DB_R,
670 .flags = IORESOURCE_IRQ,
671 },
672};
673
a9e9ce4c 674static struct resource ab8500_charger_resources[] = {
e098aded
MW		 675 {
676 .name = "MAIN_CH_UNPLUG_DET",
677 .start = AB8500_INT_MAIN_CH_UNPLUG_DET,
678 .end = AB8500_INT_MAIN_CH_UNPLUG_DET,
679 .flags = IORESOURCE_IRQ,
680 },
681 {
682 .name = "MAIN_CHARGE_PLUG_DET",
683 .start = AB8500_INT_MAIN_CH_PLUG_DET,
684 .end = AB8500_INT_MAIN_CH_PLUG_DET,
685 .flags = IORESOURCE_IRQ,
686 },
e098aded
MW		 687 {
688 .name = "VBUS_DET_R",
689 .start = AB8500_INT_VBUS_DET_R,
690 .end = AB8500_INT_VBUS_DET_R,
691 .flags = IORESOURCE_IRQ,
692 },
693 {
6af75ecd
LW		 694 .name = "VBUS_DET_F",
695 .start = AB8500_INT_VBUS_DET_F,
696 .end = AB8500_INT_VBUS_DET_F,
e098aded
MW		 697 .flags = IORESOURCE_IRQ,
698 },
699 {
6af75ecd
LW		 700 .name = "USB_LINK_STATUS",
701 .start = AB8500_INT_USB_LINK_STATUS,
702 .end = AB8500_INT_USB_LINK_STATUS,
703 .flags = IORESOURCE_IRQ,
704 },
e098aded
MW		 705 {
706 .name = "VBUS_OVV",
707 .start = AB8500_INT_VBUS_OVV,
708 .end = AB8500_INT_VBUS_OVV,
709 .flags = IORESOURCE_IRQ,
710 },
711 {
6af75ecd
LW		 712 .name = "USB_CH_TH_PROT_R",
713 .start = AB8500_INT_USB_CH_TH_PROT_R,
714 .end = AB8500_INT_USB_CH_TH_PROT_R,
e098aded
MW		 715 .flags = IORESOURCE_IRQ,
716 },
717 {
6af75ecd
LW		 718 .name = "USB_CH_TH_PROT_F",
719 .start = AB8500_INT_USB_CH_TH_PROT_F,
720 .end = AB8500_INT_USB_CH_TH_PROT_F,
e098aded
MW		 721 .flags = IORESOURCE_IRQ,
722 },
723 {
6af75ecd
LW		 724 .name = "MAIN_EXT_CH_NOT_OK",
725 .start = AB8500_INT_MAIN_EXT_CH_NOT_OK,
726 .end = AB8500_INT_MAIN_EXT_CH_NOT_OK,
727 .flags = IORESOURCE_IRQ,
728 },
729 {
730 .name = "MAIN_CH_TH_PROT_R",
731 .start = AB8500_INT_MAIN_CH_TH_PROT_R,
732 .end = AB8500_INT_MAIN_CH_TH_PROT_R,
733 .flags = IORESOURCE_IRQ,
734 },
735 {
736 .name = "MAIN_CH_TH_PROT_F",
737 .start = AB8500_INT_MAIN_CH_TH_PROT_F,
738 .end = AB8500_INT_MAIN_CH_TH_PROT_F,
739 .flags = IORESOURCE_IRQ,
740 },
741 {
742 .name = "USB_CHARGER_NOT_OKR",
a982362c
BJ		 743 .start = AB8500_INT_USB_CHARGER_NOT_OKR,
744 .end = AB8500_INT_USB_CHARGER_NOT_OKR,
6af75ecd
LW		 745 .flags = IORESOURCE_IRQ,
746 },
747 {
748 .name = "CH_WD_EXP",
749 .start = AB8500_INT_CH_WD_EXP,
750 .end = AB8500_INT_CH_WD_EXP,
751 .flags = IORESOURCE_IRQ,
752 },
753};
754
a9e9ce4c 755static struct resource ab8500_btemp_resources[] = {
6af75ecd
LW		 756 {
757 .name = "BAT_CTRL_INDB",
758 .start = AB8500_INT_BAT_CTRL_INDB,
759 .end = AB8500_INT_BAT_CTRL_INDB,
e098aded
MW		 760 .flags = IORESOURCE_IRQ,
761 },
762 {
763 .name = "BTEMP_LOW",
764 .start = AB8500_INT_BTEMP_LOW,
765 .end = AB8500_INT_BTEMP_LOW,
766 .flags = IORESOURCE_IRQ,
767 },
768 {
769 .name = "BTEMP_HIGH",
770 .start = AB8500_INT_BTEMP_HIGH,
771 .end = AB8500_INT_BTEMP_HIGH,
772 .flags = IORESOURCE_IRQ,
773 },
774 {
6af75ecd
LW		 775 .name = "BTEMP_LOW_MEDIUM",
776 .start = AB8500_INT_BTEMP_LOW_MEDIUM,
777 .end = AB8500_INT_BTEMP_LOW_MEDIUM,
e098aded
MW		 778 .flags = IORESOURCE_IRQ,
779 },
780 {
6af75ecd
LW		 781 .name = "BTEMP_MEDIUM_HIGH",
782 .start = AB8500_INT_BTEMP_MEDIUM_HIGH,
783 .end = AB8500_INT_BTEMP_MEDIUM_HIGH,
e098aded
MW		 784 .flags = IORESOURCE_IRQ,
785 },
6af75ecd
LW		 786};
787
a9e9ce4c 788static struct resource ab8500_fg_resources[] = {
e098aded 789 {
6af75ecd
LW		 790 .name = "NCONV_ACCU",
791 .start = AB8500_INT_CCN_CONV_ACC,
792 .end = AB8500_INT_CCN_CONV_ACC,
e098aded
MW		 793 .flags = IORESOURCE_IRQ,
794 },
795 {
6af75ecd
LW		 796 .name = "BATT_OVV",
797 .start = AB8500_INT_BATT_OVV,
798 .end = AB8500_INT_BATT_OVV,
e098aded
MW		 799 .flags = IORESOURCE_IRQ,
800 },
801 {
6af75ecd
LW		 802 .name = "LOW_BAT_F",
803 .start = AB8500_INT_LOW_BAT_F,
804 .end = AB8500_INT_LOW_BAT_F,
805 .flags = IORESOURCE_IRQ,
806 },
807 {
808 .name = "LOW_BAT_R",
809 .start = AB8500_INT_LOW_BAT_R,
810 .end = AB8500_INT_LOW_BAT_R,
811 .flags = IORESOURCE_IRQ,
812 },
813 {
814 .name = "CC_INT_CALIB",
815 .start = AB8500_INT_CC_INT_CALIB,
816 .end = AB8500_INT_CC_INT_CALIB,
e098aded
MW		 817 .flags = IORESOURCE_IRQ,
818 },
a982362c
BJ		 819 {
820 .name = "CCEOC",
821 .start = AB8500_INT_CCEOC,
822 .end = AB8500_INT_CCEOC,
823 .flags = IORESOURCE_IRQ,
824 },
e098aded
MW		 825};
826
a9e9ce4c 827static struct resource ab8500_chargalg_resources[] = {};
6af75ecd 828
df720647 829#ifdef CONFIG_DEBUG_FS
a9e9ce4c 830static struct resource ab8500_debug_resources[] = {
e098aded
MW		 831 {
832 .name = "IRQ_FIRST",
833 .start = AB8500_INT_MAIN_EXT_CH_NOT_OK,
834 .end = AB8500_INT_MAIN_EXT_CH_NOT_OK,
835 .flags = IORESOURCE_IRQ,
836 },
837 {
838 .name = "IRQ_LAST",
a982362c
BJ		 839 .start = AB8500_INT_XTAL32K_KO,
840 .end = AB8500_INT_XTAL32K_KO,
e098aded
MW		 841 .flags = IORESOURCE_IRQ,
842 },
843};
df720647 844#endif
e098aded 845
a9e9ce4c 846static struct resource ab8500_usb_resources[] = {
e098aded
MW		 847 {
848 .name = "ID_WAKEUP_R",
849 .start = AB8500_INT_ID_WAKEUP_R,
850 .end = AB8500_INT_ID_WAKEUP_R,
851 .flags = IORESOURCE_IRQ,
852 },
853 {
854 .name = "ID_WAKEUP_F",
855 .start = AB8500_INT_ID_WAKEUP_F,
856 .end = AB8500_INT_ID_WAKEUP_F,
857 .flags = IORESOURCE_IRQ,
858 },
859 {
860 .name = "VBUS_DET_F",
861 .start = AB8500_INT_VBUS_DET_F,
862 .end = AB8500_INT_VBUS_DET_F,
863 .flags = IORESOURCE_IRQ,
864 },
865 {
866 .name = "VBUS_DET_R",
867 .start = AB8500_INT_VBUS_DET_R,
868 .end = AB8500_INT_VBUS_DET_R,
869 .flags = IORESOURCE_IRQ,
870 },
92d50a41
MW		 871 {
872 .name = "USB_LINK_STATUS",
873 .start = AB8500_INT_USB_LINK_STATUS,
874 .end = AB8500_INT_USB_LINK_STATUS,
875 .flags = IORESOURCE_IRQ,
876 },
6af75ecd
LW		 877 {
878 .name = "USB_ADP_PROBE_PLUG",
879 .start = AB8500_INT_ADP_PROBE_PLUG,
880 .end = AB8500_INT_ADP_PROBE_PLUG,
881 .flags = IORESOURCE_IRQ,
882 },
883 {
884 .name = "USB_ADP_PROBE_UNPLUG",
885 .start = AB8500_INT_ADP_PROBE_UNPLUG,
886 .end = AB8500_INT_ADP_PROBE_UNPLUG,
887 .flags = IORESOURCE_IRQ,
888 },
e098aded
MW		 889};
890
a9e9ce4c 891static struct resource ab8505_iddet_resources[] = {
44f72e53
VS		 892 {
893 .name = "KeyDeglitch",
894 .start = AB8505_INT_KEYDEGLITCH,
895 .end = AB8505_INT_KEYDEGLITCH,
896 .flags = IORESOURCE_IRQ,
897 },
898 {
899 .name = "KP",
900 .start = AB8505_INT_KP,
901 .end = AB8505_INT_KP,
902 .flags = IORESOURCE_IRQ,
903 },
904 {
905 .name = "IKP",
906 .start = AB8505_INT_IKP,
907 .end = AB8505_INT_IKP,
908 .flags = IORESOURCE_IRQ,
909 },
910 {
911 .name = "IKR",
912 .start = AB8505_INT_IKR,
913 .end = AB8505_INT_IKR,
914 .flags = IORESOURCE_IRQ,
915 },
916 {
917 .name = "KeyStuck",
918 .start = AB8505_INT_KEYSTUCK,
919 .end = AB8505_INT_KEYSTUCK,
920 .flags = IORESOURCE_IRQ,
921 },
922};
923
a9e9ce4c 924static struct resource ab8500_temp_resources[] = {
e098aded
MW		 925 {
926 .name = "AB8500_TEMP_WARM",
927 .start = AB8500_INT_TEMP_WARM,
928 .end = AB8500_INT_TEMP_WARM,
929 .flags = IORESOURCE_IRQ,
930 },
931};
932
a9e9ce4c 933static struct mfd_cell abx500_common_devs[] = {
5814fc35
MW		 934#ifdef CONFIG_DEBUG_FS
935 {
936 .name = "ab8500-debug",
bad76991 937 .of_compatible = "stericsson,ab8500-debug",
e098aded
MW		 938 .num_resources = ARRAY_SIZE(ab8500_debug_resources),
939 .resources = ab8500_debug_resources,
5814fc35
MW		 940 },
941#endif
e098aded
MW		 942 {
943 .name = "ab8500-sysctrl",
bad76991 944 .of_compatible = "stericsson,ab8500-sysctrl",
e098aded
MW		 945 },
946 {
947 .name = "ab8500-regulator",
bad76991 948 .of_compatible = "stericsson,ab8500-regulator",
e098aded 949 },
916a871c
UH		 950 {
951 .name = "abx500-clk",
952 .of_compatible = "stericsson,abx500-clk",
953 },
62579266
RV		 954 {
955 .name = "ab8500-gpadc",
bad76991 956 .of_compatible = "stericsson,ab8500-gpadc",
62579266
RV		 957 .num_resources = ARRAY_SIZE(ab8500_gpadc_resources),
958 .resources = ab8500_gpadc_resources,
959 },
960 {
961 .name = "ab8500-rtc",
bad76991 962 .of_compatible = "stericsson,ab8500-rtc",
62579266
RV		 963 .num_resources = ARRAY_SIZE(ab8500_rtc_resources),
964 .resources = ab8500_rtc_resources,
965 },
6af75ecd
LW		 966 {
967 .name = "ab8500-acc-det",
bad76991 968 .of_compatible = "stericsson,ab8500-acc-det",
6af75ecd
LW		 969 .num_resources = ARRAY_SIZE(ab8500_av_acc_detect_resources),
970 .resources = ab8500_av_acc_detect_resources,
971 },
e098aded
MW		 972 {
973 .name = "ab8500-poweron-key",
bad76991 974 .of_compatible = "stericsson,ab8500-poweron-key",
e098aded
MW		 975 .num_resources = ARRAY_SIZE(ab8500_poweronkey_db_resources),
976 .resources = ab8500_poweronkey_db_resources,
977 },
f0f05b1c
AM		 978 {
979 .name = "ab8500-pwm",
bad76991 980 .of_compatible = "stericsson,ab8500-pwm",
f0f05b1c
AM		 981 .id = 1,
982 },
983 {
984 .name = "ab8500-pwm",
bad76991 985 .of_compatible = "stericsson,ab8500-pwm",
f0f05b1c
AM		 986 .id = 2,
987 },
988 {
989 .name = "ab8500-pwm",
bad76991 990 .of_compatible = "stericsson,ab8500-pwm",
f0f05b1c
AM		 991 .id = 3,
992 },
bad76991
LJ		 993 {
994 .name = "ab8500-leds",
995 .of_compatible = "stericsson,ab8500-leds",
996 },
77686517 997 {
e098aded 998 .name = "ab8500-denc",
bad76991 999 .of_compatible = "stericsson,ab8500-denc",
e098aded
MW		 1000 },
1001 {
1002 .name = "ab8500-temp",
bad76991 1003 .of_compatible = "stericsson,ab8500-temp",
e098aded
MW		 1004 .num_resources = ARRAY_SIZE(ab8500_temp_resources),
1005 .resources = ab8500_temp_resources,
77686517 1006 },
62579266
RV		 1007};
1008
a9e9ce4c 1009static struct mfd_cell ab8500_bm_devs[] = {
6ef9418c
RA		 1010 {
1011 .name = "ab8500-charger",
4aef72db 1012 .of_compatible = "stericsson,ab8500-charger",
6ef9418c
RA		 1013 .num_resources = ARRAY_SIZE(ab8500_charger_resources),
1014 .resources = ab8500_charger_resources,
4aef72db
R		 1015#ifndef CONFIG_OF
1016 .platform_data = &ab8500_bm_data,
1017 .pdata_size = sizeof(ab8500_bm_data),
1018#endif
6ef9418c
RA		 1019 },
1020 {
1021 .name = "ab8500-btemp",
bd9e8ab2 1022 .of_compatible = "stericsson,ab8500-btemp",
6ef9418c
RA		 1023 .num_resources = ARRAY_SIZE(ab8500_btemp_resources),
1024 .resources = ab8500_btemp_resources,
bd9e8ab2
R		 1025#ifndef CONFIG_OF
1026 .platform_data = &ab8500_bm_data,
1027 .pdata_size = sizeof(ab8500_bm_data),
1028#endif
6ef9418c
RA		 1029 },
1030 {
1031 .name = "ab8500-fg",
e0f1abeb 1032 .of_compatible = "stericsson,ab8500-fg",
6ef9418c
RA		 1033 .num_resources = ARRAY_SIZE(ab8500_fg_resources),
1034 .resources = ab8500_fg_resources,
e0f1abeb
R		 1035#ifndef CONFIG_OF
1036 .platform_data = &ab8500_bm_data,
1037 .pdata_size = sizeof(ab8500_bm_data),
1038#endif
6ef9418c
RA		 1039 },
1040 {
1041 .name = "ab8500-chargalg",
a12810ab 1042 .of_compatible = "stericsson,ab8500-chargalg",
6ef9418c
RA		 1043 .num_resources = ARRAY_SIZE(ab8500_chargalg_resources),
1044 .resources = ab8500_chargalg_resources,
a12810ab
R		 1045#ifndef CONFIG_OF
1046 .platform_data = &ab8500_bm_data,
1047 .pdata_size = sizeof(ab8500_bm_data),
1048#endif
6ef9418c
RA		 1049 },
1050};
1051
a9e9ce4c 1052static struct mfd_cell ab8500_devs[] = {
d6255529
LW		 1053 {
1054 .name = "ab8500-gpio",
bad76991 1055 .of_compatible = "stericsson,ab8500-gpio",
d6255529
LW		 1056 },
1057 {
1058 .name = "ab8500-usb",
bad76991 1059 .of_compatible = "stericsson,ab8500-usb",
d6255529
LW		 1060 .num_resources = ARRAY_SIZE(ab8500_usb_resources),
1061 .resources = ab8500_usb_resources,
1062 },
44f72e53
VS		 1063 {
1064 .name = "ab8500-codec",
81a21cdd 1065 .of_compatible = "stericsson,ab8500-codec",
44f72e53 1066 },
d6255529
LW		 1067};
1068
a9e9ce4c 1069static struct mfd_cell ab9540_devs[] = {
d6255529
LW		 1070 {
1071 .name = "ab8500-gpio",
d6255529
LW		 1072 },
1073 {
1074 .name = "ab9540-usb",
1075 .num_resources = ARRAY_SIZE(ab8500_usb_resources),
1076 .resources = ab8500_usb_resources,
1077 },
44f72e53
VS		 1078 {
1079 .name = "ab9540-codec",
1080 },
1081};
1082
1083/* Device list common to ab9540 and ab8505 */
a9e9ce4c 1084static struct mfd_cell ab9540_ab8505_devs[] = {
44f72e53
VS		 1085 {
1086 .name = "ab-iddet",
1087 .num_resources = ARRAY_SIZE(ab8505_iddet_resources),
1088 .resources = ab8505_iddet_resources,
1089 },
d6255529
LW		 1090};
1091
cca69b67
MW		 1092static ssize_t show_chip_id(struct device *dev,
1093 struct device_attribute *attr, char *buf)
1094{
1095 struct ab8500 *ab8500;
1096
1097 ab8500 = dev_get_drvdata(dev);
1098 return sprintf(buf, "%#x\n", ab8500 ? ab8500->chip_id : -EINVAL);
1099}
1100
e5c238c3
MW		 1101/*
1102 * ab8500 has switched off due to (SWITCH_OFF_STATUS):
1103 * 0x01 Swoff bit programming
1104 * 0x02 Thermal protection activation
1105 * 0x04 Vbat lower then BattOk falling threshold
1106 * 0x08 Watchdog expired
1107 * 0x10 Non presence of 32kHz clock
1108 * 0x20 Battery level lower than power on reset threshold
1109 * 0x40 Power on key 1 pressed longer than 10 seconds
1110 * 0x80 DB8500 thermal shutdown
1111 */
1112static ssize_t show_switch_off_status(struct device *dev,
1113 struct device_attribute *attr, char *buf)
1114{
1115 int ret;
1116 u8 value;
1117 struct ab8500 *ab8500;
1118
1119 ab8500 = dev_get_drvdata(dev);
1120 ret = get_register_interruptible(ab8500, AB8500_RTC,
1121 AB8500_SWITCH_OFF_STATUS, &value);
1122 if (ret < 0)
1123 return ret;
1124 return sprintf(buf, "%#x\n", value);
1125}
1126
b4a31037
AL		 1127/*
1128 * ab8500 has turned on due to (TURN_ON_STATUS):
1129 * 0x01 PORnVbat
1130 * 0x02 PonKey1dbF
1131 * 0x04 PonKey2dbF
1132 * 0x08 RTCAlarm
1133 * 0x10 MainChDet
1134 * 0x20 VbusDet
1135 * 0x40 UsbIDDetect
1136 * 0x80 Reserved
1137 */
1138static ssize_t show_turn_on_status(struct device *dev,
1139 struct device_attribute *attr, char *buf)
1140{
1141 int ret;
1142 u8 value;
1143 struct ab8500 *ab8500;
1144
1145 ab8500 = dev_get_drvdata(dev);
1146 ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK,
1147 AB8500_TURN_ON_STATUS, &value);
1148 if (ret < 0)
1149 return ret;
1150 return sprintf(buf, "%#x\n", value);
1151}
1152
d6255529
LW		 1153static ssize_t show_ab9540_dbbrstn(struct device *dev,
1154 struct device_attribute *attr, char *buf)
1155{
1156 struct ab8500 *ab8500;
1157 int ret;
1158 u8 value;
1159
1160 ab8500 = dev_get_drvdata(dev);
1161
1162 ret = get_register_interruptible(ab8500, AB8500_REGU_CTRL2,
1163 AB9540_MODEM_CTRL2_REG, &value);
1164 if (ret < 0)
1165 return ret;
1166
1167 return sprintf(buf, "%d\n",
1168 (value & AB9540_MODEM_CTRL2_SWDBBRSTN_BIT) ? 1 : 0);
1169}
1170
1171static ssize_t store_ab9540_dbbrstn(struct device *dev,
1172 struct device_attribute *attr, const char *buf, size_t count)
1173{
1174 struct ab8500 *ab8500;
1175 int ret = count;
1176 int err;
1177 u8 bitvalues;
1178
1179 ab8500 = dev_get_drvdata(dev);
1180
1181 if (count > 0) {
1182 switch (buf[0]) {
1183 case '0':
1184 bitvalues = 0;
1185 break;
1186 case '1':
1187 bitvalues = AB9540_MODEM_CTRL2_SWDBBRSTN_BIT;
1188 break;
1189 default:
1190 goto exit;
1191 }
1192
1193 err = mask_and_set_register_interruptible(ab8500,
1194 AB8500_REGU_CTRL2, AB9540_MODEM_CTRL2_REG,
1195 AB9540_MODEM_CTRL2_SWDBBRSTN_BIT, bitvalues);
1196 if (err)
1197 dev_info(ab8500->dev,
1198 "Failed to set DBBRSTN %c, err %#x\n",
1199 buf[0], err);
1200 }
1201
1202exit:
1203 return ret;
1204}
1205
cca69b67 1206static DEVICE_ATTR(chip_id, S_IRUGO, show_chip_id, NULL);
e5c238c3 1207static DEVICE_ATTR(switch_off_status, S_IRUGO, show_switch_off_status, NULL);
b4a31037 1208static DEVICE_ATTR(turn_on_status, S_IRUGO, show_turn_on_status, NULL);
d6255529
LW		 1209static DEVICE_ATTR(dbbrstn, S_IRUGO | S_IWUSR,
1210 show_ab9540_dbbrstn, store_ab9540_dbbrstn);
cca69b67
MW		 1211
1212static struct attribute *ab8500_sysfs_entries[] = {
1213 &dev_attr_chip_id.attr,
e5c238c3 1214 &dev_attr_switch_off_status.attr,
b4a31037 1215 &dev_attr_turn_on_status.attr,
cca69b67
MW		 1216 NULL,
1217};
1218
d6255529
LW		 1219static struct attribute *ab9540_sysfs_entries[] = {
1220 &dev_attr_chip_id.attr,
1221 &dev_attr_switch_off_status.attr,
1222 &dev_attr_turn_on_status.attr,
1223 &dev_attr_dbbrstn.attr,
1224 NULL,
1225};
1226
cca69b67
MW		 1227static struct attribute_group ab8500_attr_group = {
1228 .attrs = ab8500_sysfs_entries,
1229};
1230
d6255529
LW		 1231static struct attribute_group ab9540_attr_group = {
1232 .attrs = ab9540_sysfs_entries,
1233};
1234
f791be49 1235static int ab8500_probe(struct platform_device *pdev)
62579266 1236{
b04c530c
JA		 1237 static char *switch_off_status[] = {
1238 "Swoff bit programming",
1239 "Thermal protection activation",
1240 "Vbat lower then BattOk falling threshold",
1241 "Watchdog expired",
1242 "Non presence of 32kHz clock",
1243 "Battery level lower than power on reset threshold",
1244 "Power on key 1 pressed longer than 10 seconds",
1245 "DB8500 thermal shutdown"};
d28f1db8
LJ		 1246 struct ab8500_platform_data *plat = dev_get_platdata(&pdev->dev);
1247 const struct platform_device_id *platid = platform_get_device_id(pdev);
6bc4a568
LJ		 1248 enum ab8500_version version = AB8500_VERSION_UNDEFINED;
1249 struct device_node *np = pdev->dev.of_node;
d28f1db8
LJ		 1250 struct ab8500 *ab8500;
1251 struct resource *resource;
62579266
RV		 1252 int ret;
1253 int i;
47c16975 1254 u8 value;
62579266 1255
8c4203cb 1256 ab8500 = devm_kzalloc(&pdev->dev, sizeof *ab8500, GFP_KERNEL);
d28f1db8
LJ		 1257 if (!ab8500)
1258 return -ENOMEM;
1259
62579266
RV		 1260 if (plat)
1261 ab8500->irq_base = plat->irq_base;
1262
d28f1db8
LJ		 1263 ab8500->dev = &pdev->dev;
1264
1265 resource = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
8c4203cb
LJ		 1266 if (!resource)
1267 return -ENODEV;
d28f1db8
LJ		 1268
1269 ab8500->irq = resource->start;
1270
822672a7
LJ		 1271 ab8500->read = ab8500_prcmu_read;
1272 ab8500->write = ab8500_prcmu_write;
1273 ab8500->write_masked = ab8500_prcmu_write_masked;
d28f1db8 1274
62579266
RV		 1275 mutex_init(&ab8500->lock);
1276 mutex_init(&ab8500->irq_lock);
112a80d2 1277 atomic_set(&ab8500->transfer_ongoing, 0);
62579266 1278
d28f1db8
LJ		 1279 platform_set_drvdata(pdev, ab8500);
1280
6bc4a568
LJ		 1281 if (platid)
1282 version = platid->driver_data;
6bc4a568 1283
0f620837
LW		 1284 if (version != AB8500_VERSION_UNDEFINED)
1285 ab8500->version = version;
1286 else {
1287 ret = get_register_interruptible(ab8500, AB8500_MISC,
1288 AB8500_IC_NAME_REG, &value);
1289 if (ret < 0)
8c4203cb 1290 return ret;
0f620837
LW		 1291
1292 ab8500->version = value;
1293 }
1294
47c16975
MW		 1295 ret = get_register_interruptible(ab8500, AB8500_MISC,
1296 AB8500_REV_REG, &value);
62579266 1297 if (ret < 0)
8c4203cb 1298 return ret;
62579266 1299
47c16975 1300 ab8500->chip_id = value;
62579266 1301
0f620837
LW		 1302 dev_info(ab8500->dev, "detected chip, %s rev. %1x.%1x\n",
1303 ab8500_version_str[ab8500->version],
1304 ab8500->chip_id >> 4,
1305 ab8500->chip_id & 0x0F);
1306
d6255529 1307 /* Configure AB8500 or AB9540 IRQ */
a982362c 1308 if (is_ab9540(ab8500) || is_ab8505(ab8500)) {
d6255529
LW		 1309 ab8500->mask_size = AB9540_NUM_IRQ_REGS;
1310 ab8500->irq_reg_offset = ab9540_irq_regoffset;
1311 } else {
1312 ab8500->mask_size = AB8500_NUM_IRQ_REGS;
1313 ab8500->irq_reg_offset = ab8500_irq_regoffset;
1314 }
8c4203cb 1315 ab8500->mask = devm_kzalloc(&pdev->dev, ab8500->mask_size, GFP_KERNEL);
2ced445e
LW		 1316 if (!ab8500->mask)
1317 return -ENOMEM;
8c4203cb
LJ		 1318 ab8500->oldmask = devm_kzalloc(&pdev->dev, ab8500->mask_size, GFP_KERNEL);
1319 if (!ab8500->oldmask)
1320 return -ENOMEM;
1321
e5c238c3
MW		 1322 /*
1323 * ab8500 has switched off due to (SWITCH_OFF_STATUS):
1324 * 0x01 Swoff bit programming
1325 * 0x02 Thermal protection activation
1326 * 0x04 Vbat lower then BattOk falling threshold
1327 * 0x08 Watchdog expired
1328 * 0x10 Non presence of 32kHz clock
1329 * 0x20 Battery level lower than power on reset threshold
1330 * 0x40 Power on key 1 pressed longer than 10 seconds
1331 * 0x80 DB8500 thermal shutdown
1332 */
1333
1334 ret = get_register_interruptible(ab8500, AB8500_RTC,
1335 AB8500_SWITCH_OFF_STATUS, &value);
1336 if (ret < 0)
1337 return ret;
b04c530c
JA		 1338 dev_info(ab8500->dev, "switch off cause(s) (%#x): ", value);
1339
1340 if (value) {
1341 for (i = 0; i < ARRAY_SIZE(switch_off_status); i++) {
1342 if (value & 1)
1343 printk(KERN_CONT " \"%s\"",
1344 switch_off_status[i]);
1345 value = value >> 1;
1346
1347 }
1348 printk(KERN_CONT "\n");
1349 } else {
1350 printk(KERN_CONT " None\n");
1351 }
e5c238c3 1352
62579266
RV		 1353 if (plat && plat->init)
1354 plat->init(ab8500);
1355
1356 /* Clear and mask all interrupts */
2ced445e 1357 for (i = 0; i < ab8500->mask_size; i++) {
0f620837
LW		 1358 /*
1359 * Interrupt register 12 doesn't exist prior to AB8500 version
1360 * 2.0
1361 */
1362 if (ab8500->irq_reg_offset[i] == 11 &&
1363 is_ab8500_1p1_or_earlier(ab8500))
92d50a41 1364 continue;
62579266 1365
47c16975 1366 get_register_interruptible(ab8500, AB8500_INTERRUPT,
2ced445e 1367 AB8500_IT_LATCH1_REG + ab8500->irq_reg_offset[i],
92d50a41 1368 &value);
47c16975 1369 set_register_interruptible(ab8500, AB8500_INTERRUPT,
2ced445e 1370 AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i], 0xff);
62579266
RV		 1371 }
1372
47c16975
MW		 1373 ret = abx500_register_ops(ab8500->dev, &ab8500_ops);
1374 if (ret)
8c4203cb 1375 return ret;
47c16975 1376
2ced445e 1377 for (i = 0; i < ab8500->mask_size; i++)
62579266
RV		 1378 ab8500->mask[i] = ab8500->oldmask[i] = 0xff;
1379
06e589ef
LJ		 1380 ret = ab8500_irq_init(ab8500, np);
1381 if (ret)
8c4203cb 1382 return ret;
62579266 1383
06e589ef
LJ		 1384 /* Activate this feature only in ab9540 */
1385 /* till tests are done on ab8500 1p2 or later*/
1386 if (is_ab9540(ab8500)) {
8c4203cb
LJ		 1387 ret = devm_request_threaded_irq(&pdev->dev, ab8500->irq, NULL,
1388 ab8500_hierarchical_irq,
1389 IRQF_ONESHOT | IRQF_NO_SUSPEND,
1390 "ab8500", ab8500);
06e589ef
LJ		 1391 }
1392 else {
8c4203cb
LJ		 1393 ret = devm_request_threaded_irq(&pdev->dev, ab8500->irq, NULL,
1394 ab8500_irq,
1395 IRQF_ONESHOT | IRQF_NO_SUSPEND,
1396 "ab8500", ab8500);
62579266 1397 if (ret)
8c4203cb 1398 return ret;
62579266
RV		 1399 }
1400
bad76991
LJ		 1401 ret = mfd_add_devices(ab8500->dev, 0, abx500_common_devs,
1402 ARRAY_SIZE(abx500_common_devs), NULL,
55692af5 1403 ab8500->irq_base, ab8500->domain);
bad76991 1404 if (ret)
8c4203cb 1405 return ret;
d6255529 1406
bad76991
LJ		 1407 if (is_ab9540(ab8500))
1408 ret = mfd_add_devices(ab8500->dev, 0, ab9540_devs,
1409 ARRAY_SIZE(ab9540_devs), NULL,
55692af5 1410 ab8500->irq_base, ab8500->domain);
bad76991
LJ		 1411 else
1412 ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
1413 ARRAY_SIZE(ab8500_devs), NULL,
55692af5 1414 ab8500->irq_base, ab8500->domain);
bad76991 1415 if (ret)
8c4203cb 1416 return ret;
44f72e53 1417
bad76991
LJ		 1418 if (is_ab9540(ab8500) || is_ab8505(ab8500))
1419 ret = mfd_add_devices(ab8500->dev, 0, ab9540_ab8505_devs,
1420 ARRAY_SIZE(ab9540_ab8505_devs), NULL,
55692af5 1421 ab8500->irq_base, ab8500->domain);
bad76991 1422 if (ret)
8c4203cb 1423 return ret;
62579266 1424
6ef9418c
RA		 1425 if (!no_bm) {
1426 /* Add battery management devices */
1427 ret = mfd_add_devices(ab8500->dev, 0, ab8500_bm_devs,
1428 ARRAY_SIZE(ab8500_bm_devs), NULL,
55692af5 1429 ab8500->irq_base, ab8500->domain);
6ef9418c
RA		 1430 if (ret)
1431 dev_err(ab8500->dev, "error adding bm devices\n");
1432 }
1433
d6255529
LW		 1434 if (is_ab9540(ab8500))
1435 ret = sysfs_create_group(&ab8500->dev->kobj,
1436 &ab9540_attr_group);
1437 else
1438 ret = sysfs_create_group(&ab8500->dev->kobj,
1439 &ab8500_attr_group);
cca69b67
MW		 1440 if (ret)
1441 dev_err(ab8500->dev, "error creating sysfs entries\n");
06e589ef
LJ		 1442
1443 return ret;
62579266
RV		 1444}
1445
4740f73f 1446static int ab8500_remove(struct platform_device *pdev)
62579266 1447{
d28f1db8
LJ		 1448 struct ab8500 *ab8500 = platform_get_drvdata(pdev);
1449
d6255529
LW		 1450 if (is_ab9540(ab8500))
1451 sysfs_remove_group(&ab8500->dev->kobj, &ab9540_attr_group);
1452 else
1453 sysfs_remove_group(&ab8500->dev->kobj, &ab8500_attr_group);
06e589ef 1454
62579266 1455 mfd_remove_devices(ab8500->dev);
62579266
RV		 1456
1457 return 0;
1458}
1459
d28f1db8
LJ		 1460static const struct platform_device_id ab8500_id[] = {
1461 { "ab8500-core", AB8500_VERSION_AB8500 },
1462 { "ab8505-i2c", AB8500_VERSION_AB8505 },
1463 { "ab9540-i2c", AB8500_VERSION_AB9540 },
1464 { "ab8540-i2c", AB8500_VERSION_AB8540 },
1465 { }
1466};
1467
1468static struct platform_driver ab8500_core_driver = {
1469 .driver = {
1470 .name = "ab8500-core",
1471 .owner = THIS_MODULE,
1472 },
1473 .probe = ab8500_probe,
84449216 1474 .remove = ab8500_remove,
d28f1db8
LJ		 1475 .id_table = ab8500_id,
1476};
1477
1478static int __init ab8500_core_init(void)
1479{
1480 return platform_driver_register(&ab8500_core_driver);
1481}
1482
1483static void __exit ab8500_core_exit(void)
1484{
1485 platform_driver_unregister(&ab8500_core_driver);
1486}
ba7cbc3e 1487core_initcall(ab8500_core_init);
d28f1db8
LJ		 1488module_exit(ab8500_core_exit);
1489
adceed62 1490MODULE_AUTHOR("Mattias Wallin, Srinidhi Kasagar, Rabin Vincent");
62579266
RV		 1491MODULE_DESCRIPTION("AB8500 MFD core");
1492MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)