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Fix common misspellings
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / dvb / ngene / ngene-core.c
CommitLineData
dae52d00
MB		 1/*
2 * ngene.c: nGene PCIe bridge driver
3 *
4 * Copyright (C) 2005-2007 Micronas
5 *
6 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
7 * Modifications for new nGene firmware,
8 * support for EEPROM-copying,
9 * support for new dual DVB-S2 card prototype
10 *
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 only, as published by the Free Software Foundation.
15 *
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
26 * 02110-1301, USA
27 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
28 */
29
30#include <linux/module.h>
31#include <linux/init.h>
32#include <linux/delay.h>
dae52d00 33#include <linux/poll.h>
684688d8 34#include <linux/io.h>
dae52d00
MB		 35#include <asm/div64.h>
36#include <linux/pci.h>
dae52d00 37#include <linux/timer.h>
dae52d00
MB		 38#include <linux/byteorder/generic.h>
39#include <linux/firmware.h>
6fd2d0f9 40#include <linux/vmalloc.h>
dae52d00
MB		 41
42#include "ngene.h"
43
cf1b12f2
MB		 44static int one_adapter = 1;
45module_param(one_adapter, int, 0444);
46MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
47
1b7c41ef
RM		 48static int shutdown_workaround;
49module_param(shutdown_workaround, int, 0644);
e549bedf 50MODULE_PARM_DESC(shutdown_workaround, "Activate workaround for shutdown problem with some chipsets.");
1b7c41ef 51
dae52d00
MB		 52static int debug;
53module_param(debug, int, 0444);
54MODULE_PARM_DESC(debug, "Print debugging information.");
55
83f3c715
OE		 56DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
57
dae52d00
MB		 58#define dprintk if (debug) printk
59
dae52d00
MB		 60#define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr)))
61#define ngwritel(dat, adr) writel((dat), (char *)(dev->iomem + (adr)))
62#define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr)))
63#define ngreadl(adr) readl(dev->iomem + (adr))
64#define ngreadb(adr) readb(dev->iomem + (adr))
65#define ngcpyto(adr, src, count) memcpy_toio((char *) \
66 (dev->iomem + (adr)), (src), (count))
67#define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \
68 (dev->iomem + (adr)), (count))
69
dae52d00
MB		 70/****************************************************************************/
71/* nGene interrupt handler **************************************************/
72/****************************************************************************/
73
74static void event_tasklet(unsigned long data)
75{
76 struct ngene *dev = (struct ngene *)data;
77
78 while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
79 struct EVENT_BUFFER Event =
80 dev->EventQueue[dev->EventQueueReadIndex];
81 dev->EventQueueReadIndex =
82 (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
83
84 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
85 dev->TxEventNotify(dev, Event.TimeStamp);
86 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
87 dev->RxEventNotify(dev, Event.TimeStamp,
88 Event.RXCharacter);
89 }
90}
91
92static void demux_tasklet(unsigned long data)
93{
94 struct ngene_channel *chan = (struct ngene_channel *)data;
95 struct SBufferHeader *Cur = chan->nextBuffer;
96
97 spin_lock_irq(&chan->state_lock);
98
99 while (Cur->ngeneBuffer.SR.Flags & 0x80) {
100 if (chan->mode & NGENE_IO_TSOUT) {
101 u32 Flags = chan->DataFormatFlags;
102 if (Cur->ngeneBuffer.SR.Flags & 0x20)
103 Flags |= BEF_OVERFLOW;
104 if (chan->pBufferExchange) {
105 if (!chan->pBufferExchange(chan,
106 Cur->Buffer1,
107 chan->Capture1Length,
108 Cur->ngeneBuffer.SR.
109 Clock, Flags)) {
110 /*
111 We didn't get data
112 Clear in service flag to make sure we
113 get called on next interrupt again.
114 leave fill/empty (0x80) flag alone
115 to avoid hardware running out of
116 buffers during startup, we hold only
117 in run state ( the source may be late
118 delivering data )
119 */
120
121 if (chan->HWState == HWSTATE_RUN) {
122 Cur->ngeneBuffer.SR.Flags &=
123 ~0x40;
124 break;
25985edc 125 /* Stop processing stream */
dae52d00
MB		 126 }
127 } else {
128 /* We got a valid buffer,
129 so switch to run state */
130 chan->HWState = HWSTATE_RUN;
131 }
132 } else {
133 printk(KERN_ERR DEVICE_NAME ": OOPS\n");
134 if (chan->HWState == HWSTATE_RUN) {
135 Cur->ngeneBuffer.SR.Flags &= ~0x40;
25985edc 136 break; /* Stop processing stream */
dae52d00
MB		 137 }
138 }
139 if (chan->AudioDTOUpdated) {
140 printk(KERN_INFO DEVICE_NAME
141 ": Update AudioDTO = %d\n",
142 chan->AudioDTOValue);
143 Cur->ngeneBuffer.SR.DTOUpdate =
144 chan->AudioDTOValue;
145 chan->AudioDTOUpdated = 0;
146 }
147 } else {
148 if (chan->HWState == HWSTATE_RUN) {
ac9725d2 149 u32 Flags = chan->DataFormatFlags;
eb05d155
OE		 150 IBufferExchange *exch1 = chan->pBufferExchange;
151 IBufferExchange *exch2 = chan->pBufferExchange2;
dae52d00
MB		 152 if (Cur->ngeneBuffer.SR.Flags & 0x01)
153 Flags |= BEF_EVEN_FIELD;
154 if (Cur->ngeneBuffer.SR.Flags & 0x20)
155 Flags |= BEF_OVERFLOW;
eb05d155
OE		 156 spin_unlock_irq(&chan->state_lock);
157 if (exch1)
158 exch1(chan, Cur->Buffer1,
159 chan->Capture1Length,
160 Cur->ngeneBuffer.SR.Clock,
161 Flags);
162 if (exch2)
163 exch2(chan, Cur->Buffer2,
164 chan->Capture2Length,
165 Cur->ngeneBuffer.SR.Clock,
166 Flags);
167 spin_lock_irq(&chan->state_lock);
dae52d00
MB		 168 } else if (chan->HWState != HWSTATE_STOP)
169 chan->HWState = HWSTATE_RUN;
170 }
171 Cur->ngeneBuffer.SR.Flags = 0x00;
172 Cur = Cur->Next;
173 }
174 chan->nextBuffer = Cur;
175
176 spin_unlock_irq(&chan->state_lock);
177}
178
179static irqreturn_t irq_handler(int irq, void *dev_id)
180{
181 struct ngene *dev = (struct ngene *)dev_id;
182 u32 icounts = 0;
183 irqreturn_t rc = IRQ_NONE;
184 u32 i = MAX_STREAM;
185 u8 *tmpCmdDoneByte;
186
187 if (dev->BootFirmware) {
188 icounts = ngreadl(NGENE_INT_COUNTS);
189 if (icounts != dev->icounts) {
190 ngwritel(0, FORCE_NMI);
191 dev->cmd_done = 1;
192 wake_up(&dev->cmd_wq);
193 dev->icounts = icounts;
194 rc = IRQ_HANDLED;
195 }
196 return rc;
197 }
198
199 ngwritel(0, FORCE_NMI);
200
201 spin_lock(&dev->cmd_lock);
202 tmpCmdDoneByte = dev->CmdDoneByte;
203 if (tmpCmdDoneByte &&
204 (*tmpCmdDoneByte ||
205 (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
206 dev->CmdDoneByte = NULL;
207 dev->cmd_done = 1;
208 wake_up(&dev->cmd_wq);
209 rc = IRQ_HANDLED;
210 }
211 spin_unlock(&dev->cmd_lock);
212
213 if (dev->EventBuffer->EventStatus & 0x80) {
214 u8 nextWriteIndex =
215 (dev->EventQueueWriteIndex + 1) &
216 (EVENT_QUEUE_SIZE - 1);
217 if (nextWriteIndex != dev->EventQueueReadIndex) {
218 dev->EventQueue[dev->EventQueueWriteIndex] =
219 *(dev->EventBuffer);
220 dev->EventQueueWriteIndex = nextWriteIndex;
221 } else {
222 printk(KERN_ERR DEVICE_NAME ": event overflow\n");
223 dev->EventQueueOverflowCount += 1;
224 dev->EventQueueOverflowFlag = 1;
225 }
226 dev->EventBuffer->EventStatus &= ~0x80;
227 tasklet_schedule(&dev->event_tasklet);
228 rc = IRQ_HANDLED;
229 }
230
231 while (i > 0) {
232 i--;
233 spin_lock(&dev->channel[i].state_lock);
234 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
235 if (dev->channel[i].nextBuffer) {
236 if ((dev->channel[i].nextBuffer->
237 ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
238 dev->channel[i].nextBuffer->
239 ngeneBuffer.SR.Flags |= 0x40;
240 tasklet_schedule(
241 &dev->channel[i].demux_tasklet);
242 rc = IRQ_HANDLED;
243 }
244 }
245 spin_unlock(&dev->channel[i].state_lock);
246 }
247
ace30f74
OE		 248 /* Request might have been processed by a previous call. */
249 return IRQ_HANDLED;
dae52d00
MB		 250}
251
252/****************************************************************************/
253/* nGene command interface **************************************************/
254/****************************************************************************/
255
b1ec9532
OE		 256static void dump_command_io(struct ngene *dev)
257{
258 u8 buf[8], *b;
259
260 ngcpyfrom(buf, HOST_TO_NGENE, 8);
261 printk(KERN_ERR "host_to_ngene (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
684688d8
OE		 262 HOST_TO_NGENE, buf[0], buf[1], buf[2], buf[3],
263 buf[4], buf[5], buf[6], buf[7]);
b1ec9532
OE		 264
265 ngcpyfrom(buf, NGENE_TO_HOST, 8);
266 printk(KERN_ERR "ngene_to_host (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
684688d8
OE		 267 NGENE_TO_HOST, buf[0], buf[1], buf[2], buf[3],
268 buf[4], buf[5], buf[6], buf[7]);
b1ec9532
OE		 269
270 b = dev->hosttongene;
271 printk(KERN_ERR "dev->hosttongene (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
272 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
273
274 b = dev->ngenetohost;
275 printk(KERN_ERR "dev->ngenetohost (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
276 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
277}
278
dae52d00
MB		 279static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
280{
281 int ret;
282 u8 *tmpCmdDoneByte;
283
284 dev->cmd_done = 0;
285
286 if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
287 dev->BootFirmware = 1;
288 dev->icounts = ngreadl(NGENE_INT_COUNTS);
289 ngwritel(0, NGENE_COMMAND);
290 ngwritel(0, NGENE_COMMAND_HI);
291 ngwritel(0, NGENE_STATUS);
292 ngwritel(0, NGENE_STATUS_HI);
293 ngwritel(0, NGENE_EVENT);
294 ngwritel(0, NGENE_EVENT_HI);
295 } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
296 u64 fwio = dev->PAFWInterfaceBuffer;
297
298 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
299 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
300 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
301 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
302 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
303 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
304 }
305
306 memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
307
308 if (dev->BootFirmware)
309 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
310
311 spin_lock_irq(&dev->cmd_lock);
312 tmpCmdDoneByte = dev->ngenetohost + com->out_len;
313 if (!com->out_len)
314 tmpCmdDoneByte++;
315 *tmpCmdDoneByte = 0;
316 dev->ngenetohost[0] = 0;
317 dev->ngenetohost[1] = 0;
318 dev->CmdDoneByte = tmpCmdDoneByte;
319 spin_unlock_irq(&dev->cmd_lock);
320
321 /* Notify 8051. */
322 ngwritel(1, FORCE_INT);
323
324 ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
325 if (!ret) {
326 /*ngwritel(0, FORCE_NMI);*/
327
328 printk(KERN_ERR DEVICE_NAME
329 ": Command timeout cmd=%02x prev=%02x\n",
330 com->cmd.hdr.Opcode, dev->prev_cmd);
b1ec9532 331 dump_command_io(dev);
dae52d00
MB		 332 return -1;
333 }
334 if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
335 dev->BootFirmware = 0;
336
337 dev->prev_cmd = com->cmd.hdr.Opcode;
dae52d00
MB		 338
339 if (!com->out_len)
340 return 0;
341
342 memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
343
344 return 0;
345}
346
cb1c0f8e 347int ngene_command(struct ngene *dev, struct ngene_command *com)
dae52d00
MB		 348{
349 int result;
350
351 down(&dev->cmd_mutex);
352 result = ngene_command_mutex(dev, com);
353 up(&dev->cmd_mutex);
354 return result;
355}
356
dae52d00 357
dae52d00
MB		 358static int ngene_command_load_firmware(struct ngene *dev,
359 u8 *ngene_fw, u32 size)
360{
361#define FIRSTCHUNK (1024)
362 u32 cleft;
363 struct ngene_command com;
364
365 com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
366 com.cmd.hdr.Length = 0;
367 com.in_len = 0;
368 com.out_len = 0;
369
370 ngene_command(dev, &com);
371
372 cleft = (size + 3) & ~3;
373 if (cleft > FIRSTCHUNK) {
374 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
375 cleft - FIRSTCHUNK);
376 cleft = FIRSTCHUNK;
377 }
dae52d00
MB		 378 ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
379
380 memset(&com, 0, sizeof(struct ngene_command));
381 com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
382 com.cmd.hdr.Length = 4;
383 com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
384 com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
385 com.in_len = 4;
386 com.out_len = 0;
387
388 return ngene_command(dev, &com);
389}
390
dae52d00
MB		 391
392static int ngene_command_config_buf(struct ngene *dev, u8 config)
393{
394 struct ngene_command com;
395
396 com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
397 com.cmd.hdr.Length = 1;
398 com.cmd.ConfigureBuffers.config = config;
399 com.in_len = 1;
400 com.out_len = 0;
401
402 if (ngene_command(dev, &com) < 0)
403 return -EIO;
404 return 0;
405}
406
407static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
408{
409 struct ngene_command com;
410
411 com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
412 com.cmd.hdr.Length = 6;
413 memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
414 com.in_len = 6;
415 com.out_len = 0;
416
417 if (ngene_command(dev, &com) < 0)
418 return -EIO;
419
420 return 0;
421}
422
cb1c0f8e 423int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
dae52d00
MB		 424{
425 struct ngene_command com;
426
427 com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
428 com.cmd.hdr.Length = 1;
429 com.cmd.SetGpioPin.select = select | (level << 7);
430 com.in_len = 1;
431 com.out_len = 0;
432
433 return ngene_command(dev, &com);
434}
435
dae52d00
MB		 436
437/*
438 02000640 is sample on rising edge.
439 02000740 is sample on falling edge.
440 02000040 is ignore "valid" signal
441
442 0: FD_CTL1 Bit 7,6 must be 0,1
443 7 disable(fw controlled)
444 6 0-AUX,1-TS
445 5 0-par,1-ser
446 4 0-lsb/1-msb
447 3,2 reserved
448 1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
449 1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
450 2: FD_STA is read-only. 0-sync
451 3: FD_INSYNC is number of 47s to trigger "in sync".
452 4: FD_OUTSYNC is number of 47s to trigger "out of sync".
453 5: FD_MAXBYTE1 is low-order of bytes per packet.
454 6: FD_MAXBYTE2 is high-order of bytes per packet.
455 7: Top byte is unused.
456*/
457
458/****************************************************************************/
459
0abf2629 460static u8 TSFeatureDecoderSetup[8 * 5] = {
dae52d00
MB		 461 0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
462 0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
463 0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
464 0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
0abf2629 465 0x40, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* LGDT3303 */
dae52d00
MB		 466};
467
468/* Set NGENE I2S Config to 16 bit packed */
469static u8 I2SConfiguration[] = {
470 0x00, 0x10, 0x00, 0x00,
471 0x80, 0x10, 0x00, 0x00,
472};
473
474static u8 SPDIFConfiguration[10] = {
475 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
476};
477
478/* Set NGENE I2S Config to transport stream compatible mode */
479
ac9725d2 480static u8 TS_I2SConfiguration[4] = { 0x3E, 0x18, 0x00, 0x00 };
dae52d00 481
0f0b270f 482static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x04, 0x00, 0x00 };
dae52d00
MB		 483
484static u8 ITUDecoderSetup[4][16] = {
485 {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */
486 0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
487 {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
488 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
489 {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00, /* HDTV 1080i50 */
490 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
491 {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, /* HDTV 1080i60 */
492 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
493};
494
495/*
496 * 50 48 60 gleich
497 * 27p50 9f 00 22 80 42 69 18 ...
498 * 27p60 93 00 22 80 82 69 1c ...
499 */
500
501/* Maxbyte to 1144 (for raw data) */
502static u8 ITUFeatureDecoderSetup[8] = {
503 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
504};
505
1899e97c 506void FillTSBuffer(void *Buffer, int Length, u32 Flags)
dae52d00
MB		 507{
508 u32 *ptr = Buffer;
509
fd9be0dc 510 memset(Buffer, 0xff, Length);
dae52d00
MB		 511 while (Length > 0) {
512 if (Flags & DF_SWAP32)
513 *ptr = 0x471FFF10;
514 else
515 *ptr = 0x10FF1F47;
516 ptr += (188 / 4);
517 Length -= 188;
518 }
519}
520
dae52d00
MB		 521
522static void flush_buffers(struct ngene_channel *chan)
523{
524 u8 val;
525
526 do {
527 msleep(1);
528 spin_lock_irq(&chan->state_lock);
529 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
530 spin_unlock_irq(&chan->state_lock);
531 } while (val);
532}
533
534static void clear_buffers(struct ngene_channel *chan)
535{
536 struct SBufferHeader *Cur = chan->nextBuffer;
537
538 do {
539 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
540 if (chan->mode & NGENE_IO_TSOUT)
541 FillTSBuffer(Cur->Buffer1,
542 chan->Capture1Length,
543 chan->DataFormatFlags);
544 Cur = Cur->Next;
545 } while (Cur != chan->nextBuffer);
546
547 if (chan->mode & NGENE_IO_TSOUT) {
548 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
549 chan->AudioDTOValue;
550 chan->AudioDTOUpdated = 0;
551
552 Cur = chan->TSIdleBuffer.Head;
553
554 do {
555 memset(&Cur->ngeneBuffer.SR, 0,
556 sizeof(Cur->ngeneBuffer.SR));
557 FillTSBuffer(Cur->Buffer1,
558 chan->Capture1Length,
559 chan->DataFormatFlags);
560 Cur = Cur->Next;
561 } while (Cur != chan->TSIdleBuffer.Head);
562 }
563}
564
9fdd7976
OE		 565static int ngene_command_stream_control(struct ngene *dev, u8 stream,
566 u8 control, u8 mode, u8 flags)
dae52d00
MB		 567{
568 struct ngene_channel *chan = &dev->channel[stream];
569 struct ngene_command com;
570 u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
571 u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
572 u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
573 u16 BsSDO = 0x9B00;
574
51ff9ef1 575 down(&dev->stream_mutex);
dae52d00
MB		 576 memset(&com, 0, sizeof(com));
577 com.cmd.hdr.Opcode = CMD_CONTROL;
578 com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
579 com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
580 if (chan->mode & NGENE_IO_TSOUT)
581 com.cmd.StreamControl.Stream |= 0x07;
582 com.cmd.StreamControl.Control = control |
583 (flags & SFLAG_ORDER_LUMA_CHROMA);
584 com.cmd.StreamControl.Mode = mode;
585 com.in_len = sizeof(struct FW_STREAM_CONTROL);
586 com.out_len = 0;
587
44cdd064
OE		 588 dprintk(KERN_INFO DEVICE_NAME
589 ": Stream=%02x, Control=%02x, Mode=%02x\n",
590 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
591 com.cmd.StreamControl.Mode);
592
dae52d00
MB		 593 chan->Mode = mode;
594
595 if (!(control & 0x80)) {
596 spin_lock_irq(&chan->state_lock);
597 if (chan->State == KSSTATE_RUN) {
598 chan->State = KSSTATE_ACQUIRE;
599 chan->HWState = HWSTATE_STOP;
600 spin_unlock_irq(&chan->state_lock);
601 if (ngene_command(dev, &com) < 0) {
602 up(&dev->stream_mutex);
603 return -1;
604 }
605 /* clear_buffers(chan); */
606 flush_buffers(chan);
607 up(&dev->stream_mutex);
608 return 0;
609 }
610 spin_unlock_irq(&chan->state_lock);
611 up(&dev->stream_mutex);
612 return 0;
613 }
614
615 if (mode & SMODE_AUDIO_CAPTURE) {
616 com.cmd.StreamControl.CaptureBlockCount =
617 chan->Capture1Length / AUDIO_BLOCK_SIZE;
618 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
619 } else if (mode & SMODE_TRANSPORT_STREAM) {
620 com.cmd.StreamControl.CaptureBlockCount =
621 chan->Capture1Length / TS_BLOCK_SIZE;
622 com.cmd.StreamControl.MaxLinesPerField =
623 chan->Capture1Length / TS_BLOCK_SIZE;
624 com.cmd.StreamControl.Buffer_Address =
625 chan->TSRingBuffer.PAHead;
626 if (chan->mode & NGENE_IO_TSOUT) {
627 com.cmd.StreamControl.BytesPerVBILine =
628 chan->Capture1Length / TS_BLOCK_SIZE;
629 com.cmd.StreamControl.Stream |= 0x07;
630 }
631 } else {
632 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
633 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
634 com.cmd.StreamControl.MinLinesPerField = 100;
635 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
636
637 if (mode & SMODE_VBI_CAPTURE) {
638 com.cmd.StreamControl.MaxVBILinesPerField =
639 chan->nVBILines;
640 com.cmd.StreamControl.MinVBILinesPerField = 0;
641 com.cmd.StreamControl.BytesPerVBILine =
642 chan->nBytesPerVBILine;
643 }
644 if (flags & SFLAG_COLORBAR)
645 com.cmd.StreamControl.Stream |= 0x04;
646 }
647
648 spin_lock_irq(&chan->state_lock);
649 if (mode & SMODE_AUDIO_CAPTURE) {
650 chan->nextBuffer = chan->RingBuffer.Head;
651 if (mode & SMODE_AUDIO_SPDIF) {
652 com.cmd.StreamControl.SetupDataLen =
653 sizeof(SPDIFConfiguration);
654 com.cmd.StreamControl.SetupDataAddr = BsSPI;
655 memcpy(com.cmd.StreamControl.SetupData,
656 SPDIFConfiguration, sizeof(SPDIFConfiguration));
657 } else {
658 com.cmd.StreamControl.SetupDataLen = 4;
659 com.cmd.StreamControl.SetupDataAddr = BsSDI;
660 memcpy(com.cmd.StreamControl.SetupData,
661 I2SConfiguration +
662 4 * dev->card_info->i2s[stream], 4);
663 }
664 } else if (mode & SMODE_TRANSPORT_STREAM) {
665 chan->nextBuffer = chan->TSRingBuffer.Head;
666 if (stream >= STREAM_AUDIOIN1) {
667 if (chan->mode & NGENE_IO_TSOUT) {
668 com.cmd.StreamControl.SetupDataLen =
669 sizeof(TS_I2SOutConfiguration);
670 com.cmd.StreamControl.SetupDataAddr = BsSDO;
671 memcpy(com.cmd.StreamControl.SetupData,
672 TS_I2SOutConfiguration,
673 sizeof(TS_I2SOutConfiguration));
674 } else {
675 com.cmd.StreamControl.SetupDataLen =
676 sizeof(TS_I2SConfiguration);
677 com.cmd.StreamControl.SetupDataAddr = BsSDI;
678 memcpy(com.cmd.StreamControl.SetupData,
679 TS_I2SConfiguration,
680 sizeof(TS_I2SConfiguration));
681 }
682 } else {
683 com.cmd.StreamControl.SetupDataLen = 8;
684 com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
685 memcpy(com.cmd.StreamControl.SetupData,
686 TSFeatureDecoderSetup +
687 8 * dev->card_info->tsf[stream], 8);
688 }
689 } else {
690 chan->nextBuffer = chan->RingBuffer.Head;
691 com.cmd.StreamControl.SetupDataLen =
692 16 + sizeof(ITUFeatureDecoderSetup);
693 com.cmd.StreamControl.SetupDataAddr = BsUVI;
694 memcpy(com.cmd.StreamControl.SetupData,
695 ITUDecoderSetup[chan->itumode], 16);
696 memcpy(com.cmd.StreamControl.SetupData + 16,
697 ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
698 }
699 clear_buffers(chan);
700 chan->State = KSSTATE_RUN;
701 if (mode & SMODE_TRANSPORT_STREAM)
702 chan->HWState = HWSTATE_RUN;
703 else
704 chan->HWState = HWSTATE_STARTUP;
705 spin_unlock_irq(&chan->state_lock);
706
707 if (ngene_command(dev, &com) < 0) {
708 up(&dev->stream_mutex);
709 return -1;
710 }
711 up(&dev->stream_mutex);
712 return 0;
713}
714
1899e97c 715void set_transfer(struct ngene_channel *chan, int state)
dae52d00
MB		 716{
717 u8 control = 0, mode = 0, flags = 0;
718 struct ngene *dev = chan->dev;
719 int ret;
720
dae52d00
MB		 721 /*
722 printk(KERN_INFO DEVICE_NAME ": st %d\n", state);
723 msleep(100);
724 */
725
726 if (state) {
727 if (chan->running) {
728 printk(KERN_INFO DEVICE_NAME ": already running\n");
729 return;
730 }
731 } else {
732 if (!chan->running) {
733 printk(KERN_INFO DEVICE_NAME ": already stopped\n");
734 return;
735 }
736 }
737
738 if (dev->card_info->switch_ctrl)
739 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
740
741 if (state) {
742 spin_lock_irq(&chan->state_lock);
743
744 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
745 ngreadl(0x9310)); */
126cd4bc 746 dvb_ringbuffer_flush(&dev->tsout_rbuf);
dae52d00
MB		 747 control = 0x80;
748 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
749 chan->Capture1Length = 512 * 188;
750 mode = SMODE_TRANSPORT_STREAM;
751 }
752 if (chan->mode & NGENE_IO_TSOUT) {
753 chan->pBufferExchange = tsout_exchange;
754 /* 0x66666666 = 50MHz *2^33 /250MHz */
0f0b270f
RM		 755 chan->AudioDTOValue = 0x80000000;
756 chan->AudioDTOUpdated = 1;
dae52d00
MB		 757 }
758 if (chan->mode & NGENE_IO_TSIN)
759 chan->pBufferExchange = tsin_exchange;
dae52d00
MB		 760 spin_unlock_irq(&chan->state_lock);
761 } else
762 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
763 ngreadl(0x9310)); */
764
765 ret = ngene_command_stream_control(dev, chan->number,
766 control, mode, flags);
767 if (!ret)
768 chan->running = state;
769 else
770 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n",
771 state);
772 if (!state) {
773 spin_lock_irq(&chan->state_lock);
7b1fc72c 774 chan->pBufferExchange = NULL;
126cd4bc 775 dvb_ringbuffer_flush(&dev->tsout_rbuf);
dae52d00
MB		 776 spin_unlock_irq(&chan->state_lock);
777 }
778}
779
dae52d00
MB		 780
781/****************************************************************************/
782/* nGene hardware init and release functions ********************************/
783/****************************************************************************/
784
9fdd7976 785static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
dae52d00
MB		 786{
787 struct SBufferHeader *Cur = rb->Head;
788 u32 j;
789
790 if (!Cur)
791 return;
792
793 for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
794 if (Cur->Buffer1)
795 pci_free_consistent(dev->pci_dev,
796 rb->Buffer1Length,
797 Cur->Buffer1,
798 Cur->scList1->Address);
799
800 if (Cur->Buffer2)
801 pci_free_consistent(dev->pci_dev,
802 rb->Buffer2Length,
803 Cur->Buffer2,
804 Cur->scList2->Address);
805 }
806
807 if (rb->SCListMem)
808 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
809 rb->SCListMem, rb->PASCListMem);
810
811 pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
812}
813
9fdd7976 814static void free_idlebuffer(struct ngene *dev,
dae52d00
MB		 815 struct SRingBufferDescriptor *rb,
816 struct SRingBufferDescriptor *tb)
817{
818 int j;
819 struct SBufferHeader *Cur = tb->Head;
820
821 if (!rb->Head)
822 return;
823 free_ringbuffer(dev, rb);
824 for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
7b1fc72c
MN		 825 Cur->Buffer2 = NULL;
826 Cur->scList2 = NULL;
dae52d00
MB		 827 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
828 Cur->ngeneBuffer.Number_of_entries_2 = 0;
829 }
830}
831
9fdd7976 832static void free_common_buffers(struct ngene *dev)
dae52d00
MB		 833{
834 u32 i;
835 struct ngene_channel *chan;
836
837 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
838 chan = &dev->channel[i];
839 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
840 free_ringbuffer(dev, &chan->RingBuffer);
841 free_ringbuffer(dev, &chan->TSRingBuffer);
842 }
843
844 if (dev->OverflowBuffer)
845 pci_free_consistent(dev->pci_dev,
846 OVERFLOW_BUFFER_SIZE,
847 dev->OverflowBuffer, dev->PAOverflowBuffer);
848
849 if (dev->FWInterfaceBuffer)
850 pci_free_consistent(dev->pci_dev,
851 4096,
852 dev->FWInterfaceBuffer,
853 dev->PAFWInterfaceBuffer);
854}
855
856/****************************************************************************/
857/* Ring buffer handling *****************************************************/
858/****************************************************************************/
859
9fdd7976 860static int create_ring_buffer(struct pci_dev *pci_dev,
dae52d00
MB		 861 struct SRingBufferDescriptor *descr, u32 NumBuffers)
862{
863 dma_addr_t tmp;
864 struct SBufferHeader *Head;
865 u32 i;
866 u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
867 u64 PARingBufferHead;
868 u64 PARingBufferCur;
869 u64 PARingBufferNext;
870 struct SBufferHeader *Cur, *Next;
871
7b1fc72c 872 descr->Head = NULL;
dae52d00
MB		 873 descr->MemSize = 0;
874 descr->PAHead = 0;
875 descr->NumBuffers = 0;
876
877 if (MemSize < 4096)
878 MemSize = 4096;
879
880 Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
881 PARingBufferHead = tmp;
882
883 if (!Head)
884 return -ENOMEM;
885
886 memset(Head, 0, MemSize);
887
888 PARingBufferCur = PARingBufferHead;
889 Cur = Head;
890
891 for (i = 0; i < NumBuffers - 1; i++) {
892 Next = (struct SBufferHeader *)
893 (((u8 *) Cur) + SIZEOF_SBufferHeader);
894 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
895 Cur->Next = Next;
896 Cur->ngeneBuffer.Next = PARingBufferNext;
897 Cur = Next;
898 PARingBufferCur = PARingBufferNext;
899 }
900 /* Last Buffer points back to first one */
901 Cur->Next = Head;
902 Cur->ngeneBuffer.Next = PARingBufferHead;
903
904 descr->Head = Head;
905 descr->MemSize = MemSize;
906 descr->PAHead = PARingBufferHead;
907 descr->NumBuffers = NumBuffers;
908
909 return 0;
910}
911
912static int AllocateRingBuffers(struct pci_dev *pci_dev,
913 dma_addr_t of,
914 struct SRingBufferDescriptor *pRingBuffer,
915 u32 Buffer1Length, u32 Buffer2Length)
916{
917 dma_addr_t tmp;
918 u32 i, j;
919 int status = 0;
920 u32 SCListMemSize = pRingBuffer->NumBuffers
921 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
922 NUM_SCATTER_GATHER_ENTRIES)
923 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
924
925 u64 PASCListMem;
684688d8 926 struct HW_SCATTER_GATHER_ELEMENT *SCListEntry;
dae52d00
MB		 927 u64 PASCListEntry;
928 struct SBufferHeader *Cur;
929 void *SCListMem;
930
931 if (SCListMemSize < 4096)
932 SCListMemSize = 4096;
933
934 SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
935
936 PASCListMem = tmp;
937 if (SCListMem == NULL)
938 return -ENOMEM;
939
940 memset(SCListMem, 0, SCListMemSize);
941
942 pRingBuffer->SCListMem = SCListMem;
943 pRingBuffer->PASCListMem = PASCListMem;
944 pRingBuffer->SCListMemSize = SCListMemSize;
945 pRingBuffer->Buffer1Length = Buffer1Length;
946 pRingBuffer->Buffer2Length = Buffer2Length;
947
684688d8 948 SCListEntry = SCListMem;
dae52d00
MB		 949 PASCListEntry = PASCListMem;
950 Cur = pRingBuffer->Head;
951
952 for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
953 u64 PABuffer;
954
955 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
956 &tmp);
957 PABuffer = tmp;
958
959 if (Buffer == NULL)
960 return -ENOMEM;
961
962 Cur->Buffer1 = Buffer;
963
964 SCListEntry->Address = PABuffer;
965 SCListEntry->Length = Buffer1Length;
966
967 Cur->scList1 = SCListEntry;
968 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
969 Cur->ngeneBuffer.Number_of_entries_1 =
970 NUM_SCATTER_GATHER_ENTRIES;
971
972 SCListEntry += 1;
973 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
974
975#if NUM_SCATTER_GATHER_ENTRIES > 1
976 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
977 SCListEntry->Address = of;
978 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
979 SCListEntry += 1;
980 PASCListEntry +=
981 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
982 }
983#endif
984
985 if (!Buffer2Length)
986 continue;
987
988 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
989 PABuffer = tmp;
990
991 if (Buffer == NULL)
992 return -ENOMEM;
993
994 Cur->Buffer2 = Buffer;
995
996 SCListEntry->Address = PABuffer;
997 SCListEntry->Length = Buffer2Length;
998
999 Cur->scList2 = SCListEntry;
1000 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
1001 Cur->ngeneBuffer.Number_of_entries_2 =
1002 NUM_SCATTER_GATHER_ENTRIES;
1003
1004 SCListEntry += 1;
1005 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1006
1007#if NUM_SCATTER_GATHER_ENTRIES > 1
1008 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
1009 SCListEntry->Address = of;
1010 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1011 SCListEntry += 1;
1012 PASCListEntry +=
1013 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1014 }
1015#endif
1016
1017 }
1018
1019 return status;
1020}
1021
1022static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
1023 struct SRingBufferDescriptor *pRingBuffer)
1024{
1025 int status = 0;
1026
1027 /* Copy pointer to scatter gather list in TSRingbuffer
1028 structure for buffer 2
1029 Load number of buffer
1030 */
1031 u32 n = pRingBuffer->NumBuffers;
1032
1033 /* Point to first buffer entry */
1034 struct SBufferHeader *Cur = pRingBuffer->Head;
1035 int i;
1036 /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
1037 for (i = 0; i < n; i++) {
1038 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
1039 Cur->scList2 = pIdleBuffer->Head->scList1;
1040 Cur->ngeneBuffer.Address_of_first_entry_2 =
1041 pIdleBuffer->Head->ngeneBuffer.
1042 Address_of_first_entry_1;
1043 Cur->ngeneBuffer.Number_of_entries_2 =
1044 pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
1045 Cur = Cur->Next;
1046 }
1047 return status;
1048}
1049
1050static u32 RingBufferSizes[MAX_STREAM] = {
1051 RING_SIZE_VIDEO,
1052 RING_SIZE_VIDEO,
1053 RING_SIZE_AUDIO,
1054 RING_SIZE_AUDIO,
1055 RING_SIZE_AUDIO,
1056};
1057
1058static u32 Buffer1Sizes[MAX_STREAM] = {
1059 MAX_VIDEO_BUFFER_SIZE,
1060 MAX_VIDEO_BUFFER_SIZE,
1061 MAX_AUDIO_BUFFER_SIZE,
1062 MAX_AUDIO_BUFFER_SIZE,
1063 MAX_AUDIO_BUFFER_SIZE
1064};
1065
1066static u32 Buffer2Sizes[MAX_STREAM] = {
1067 MAX_VBI_BUFFER_SIZE,
1068 MAX_VBI_BUFFER_SIZE,
1069 0,
1070 0,
1071 0
1072};
1073
dae52d00
MB		 1074
1075static int AllocCommonBuffers(struct ngene *dev)
1076{
1077 int status = 0, i;
1078
1079 dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
1080 &dev->PAFWInterfaceBuffer);
1081 if (!dev->FWInterfaceBuffer)
1082 return -ENOMEM;
1083 dev->hosttongene = dev->FWInterfaceBuffer;
1084 dev->ngenetohost = dev->FWInterfaceBuffer + 256;
1085 dev->EventBuffer = dev->FWInterfaceBuffer + 512;
1086
1087 dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev,
1088 OVERFLOW_BUFFER_SIZE,
1089 &dev->PAOverflowBuffer);
1090 if (!dev->OverflowBuffer)
1091 return -ENOMEM;
1092 memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE);
1093
1094 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1095 int type = dev->card_info->io_type[i];
1096
1097 dev->channel[i].State = KSSTATE_STOP;
1098
1099 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
1100 status = create_ring_buffer(dev->pci_dev,
1101 &dev->channel[i].RingBuffer,
1102 RingBufferSizes[i]);
1103 if (status < 0)
1104 break;
1105
1106 if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
1107 status = AllocateRingBuffers(dev->pci_dev,
1108 dev->
1109 PAOverflowBuffer,
1110 &dev->channel[i].
1111 RingBuffer,
1112 Buffer1Sizes[i],
1113 Buffer2Sizes[i]);
1114 if (status < 0)
1115 break;
1116 } else if (type & NGENE_IO_HDTV) {
1117 status = AllocateRingBuffers(dev->pci_dev,
1118 dev->
1119 PAOverflowBuffer,
1120 &dev->channel[i].
1121 RingBuffer,
1122 MAX_HDTV_BUFFER_SIZE,
1123 0);
1124 if (status < 0)
1125 break;
1126 }
1127 }
1128
1129 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1130
1131 status = create_ring_buffer(dev->pci_dev,
1132 &dev->channel[i].
1133 TSRingBuffer, RING_SIZE_TS);
1134 if (status < 0)
1135 break;
1136
1137 status = AllocateRingBuffers(dev->pci_dev,
1138 dev->PAOverflowBuffer,
1139 &dev->channel[i].
1140 TSRingBuffer,
1141 MAX_TS_BUFFER_SIZE, 0);
1142 if (status)
1143 break;
1144 }
1145
1146 if (type & NGENE_IO_TSOUT) {
1147 status = create_ring_buffer(dev->pci_dev,
1148 &dev->channel[i].
1149 TSIdleBuffer, 1);
1150 if (status < 0)
1151 break;
1152 status = AllocateRingBuffers(dev->pci_dev,
1153 dev->PAOverflowBuffer,
1154 &dev->channel[i].
1155 TSIdleBuffer,
1156 MAX_TS_BUFFER_SIZE, 0);
1157 if (status)
1158 break;
1159 FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
1160 &dev->channel[i].TSRingBuffer);
1161 }
1162 }
1163 return status;
1164}
1165
1166static void ngene_release_buffers(struct ngene *dev)
1167{
1168 if (dev->iomem)
1169 iounmap(dev->iomem);
1170 free_common_buffers(dev);
1171 vfree(dev->tsout_buf);
0f0b270f 1172 vfree(dev->tsin_buf);
dae52d00
MB		 1173 vfree(dev->ain_buf);
1174 vfree(dev->vin_buf);
1175 vfree(dev);
1176}
1177
1178static int ngene_get_buffers(struct ngene *dev)
1179{
1180 if (AllocCommonBuffers(dev))
1181 return -ENOMEM;
1182 if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
1183 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
1184 if (!dev->tsout_buf)
1185 return -ENOMEM;
1186 dvb_ringbuffer_init(&dev->tsout_rbuf,
1187 dev->tsout_buf, TSOUT_BUF_SIZE);
1188 }
0f0b270f
RM		 1189 if (dev->card_info->io_type[2]&NGENE_IO_TSIN) {
1190 dev->tsin_buf = vmalloc(TSIN_BUF_SIZE);
1191 if (!dev->tsin_buf)
1192 return -ENOMEM;
1193 dvb_ringbuffer_init(&dev->tsin_rbuf,
1194 dev->tsin_buf, TSIN_BUF_SIZE);
1195 }
dae52d00
MB		 1196 if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1197 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1198 if (!dev->ain_buf)
1199 return -ENOMEM;
1200 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
1201 }
1202 if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
1203 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
1204 if (!dev->vin_buf)
1205 return -ENOMEM;
1206 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
1207 }
1208 dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
1209 pci_resource_len(dev->pci_dev, 0));
1210 if (!dev->iomem)
1211 return -ENOMEM;
1212
1213 return 0;
1214}
1215
1216static void ngene_init(struct ngene *dev)
1217{
1218 int i;
1219
1220 tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
1221
1222 memset_io(dev->iomem + 0xc000, 0x00, 0x220);
1223 memset_io(dev->iomem + 0xc400, 0x00, 0x100);
1224
1225 for (i = 0; i < MAX_STREAM; i++) {
1226 dev->channel[i].dev = dev;
1227 dev->channel[i].number = i;
1228 }
1229
1230 dev->fw_interface_version = 0;
1231
1232 ngwritel(0, NGENE_INT_ENABLE);
1233
1234 dev->icounts = ngreadl(NGENE_INT_COUNTS);
1235
1236 dev->device_version = ngreadl(DEV_VER) & 0x0f;
1237 printk(KERN_INFO DEVICE_NAME ": Device version %d\n",
1238 dev->device_version);
1239}
1240
1241static int ngene_load_firm(struct ngene *dev)
1242{
1243 u32 size;
1244 const struct firmware *fw = NULL;
1245 u8 *ngene_fw;
1246 char *fw_name;
1247 int err, version;
1248
1249 version = dev->card_info->fw_version;
1250
1251 switch (version) {
1252 default:
1253 case 15:
1254 version = 15;
0027ebb7 1255 size = 23466;
dae52d00 1256 fw_name = "ngene_15.fw";
5a2a1848 1257 dev->cmd_timeout_workaround = true;
dae52d00
MB		 1258 break;
1259 case 16:
0027ebb7 1260 size = 23498;
dae52d00 1261 fw_name = "ngene_16.fw";
5a2a1848 1262 dev->cmd_timeout_workaround = true;
dae52d00
MB		 1263 break;
1264 case 17:
0027ebb7 1265 size = 24446;
dae52d00 1266 fw_name = "ngene_17.fw";
5a2a1848 1267 dev->cmd_timeout_workaround = true;
dae52d00 1268 break;
09961aae
OE		 1269 case 18:
1270 size = 0;
1271 fw_name = "ngene_18.fw";
1272 break;
dae52d00 1273 }
dae52d00 1274
dae52d00
MB		 1275 if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
1276 printk(KERN_ERR DEVICE_NAME
0027ebb7 1277 ": Could not load firmware file %s.\n", fw_name);
dae52d00
MB		 1278 printk(KERN_INFO DEVICE_NAME
1279 ": Copy %s to your hotplug directory!\n", fw_name);
1280 return -1;
1281 }
09961aae
OE		 1282 if (size == 0)
1283 size = fw->size;
0027ebb7
OE		 1284 if (size != fw->size) {
1285 printk(KERN_ERR DEVICE_NAME
1286 ": Firmware %s has invalid size!", fw_name);
1287 err = -1;
1288 } else {
1289 printk(KERN_INFO DEVICE_NAME
1290 ": Loading firmware file %s.\n", fw_name);
1291 ngene_fw = (u8 *) fw->data;
1292 err = ngene_command_load_firmware(dev, ngene_fw, size);
1293 }
1294
dae52d00 1295 release_firmware(fw);
0027ebb7 1296
dae52d00
MB		 1297 return err;
1298}
1299
1300static void ngene_stop(struct ngene *dev)
1301{
1302 down(&dev->cmd_mutex);
1303 i2c_del_adapter(&(dev->channel[0].i2c_adapter));
1304 i2c_del_adapter(&(dev->channel[1].i2c_adapter));
1305 ngwritel(0, NGENE_INT_ENABLE);
1306 ngwritel(0, NGENE_COMMAND);
1307 ngwritel(0, NGENE_COMMAND_HI);
1308 ngwritel(0, NGENE_STATUS);
1309 ngwritel(0, NGENE_STATUS_HI);
1310 ngwritel(0, NGENE_EVENT);
1311 ngwritel(0, NGENE_EVENT_HI);
1312 free_irq(dev->pci_dev->irq, dev);
478b3a42 1313#ifdef CONFIG_PCI_MSI
43874181
OE		 1314 if (dev->msi_enabled)
1315 pci_disable_msi(dev->pci_dev);
478b3a42 1316#endif
dae52d00
MB		 1317}
1318
0f0b270f
RM		 1319static int ngene_buffer_config(struct ngene *dev)
1320{
1321 int stat;
1322
1323 if (dev->card_info->fw_version >= 17) {
1324 u8 tsin12_config[6] = { 0x60, 0x60, 0x00, 0x00, 0x00, 0x00 };
1325 u8 tsin1234_config[6] = { 0x30, 0x30, 0x00, 0x30, 0x30, 0x00 };
1326 u8 tsio1235_config[6] = { 0x30, 0x30, 0x00, 0x28, 0x00, 0x38 };
1327 u8 *bconf = tsin12_config;
1328
1329 if (dev->card_info->io_type[2]&NGENE_IO_TSIN &&
1330 dev->card_info->io_type[3]&NGENE_IO_TSIN) {
1331 bconf = tsin1234_config;
1332 if (dev->card_info->io_type[4]&NGENE_IO_TSOUT &&
1333 dev->ci.en)
1334 bconf = tsio1235_config;
1335 }
1336 stat = ngene_command_config_free_buf(dev, bconf);
1337 } else {
1338 int bconf = BUFFER_CONFIG_4422;
1339
1340 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1341 bconf = BUFFER_CONFIG_3333;
1342 stat = ngene_command_config_buf(dev, bconf);
1343 }
1344 return stat;
1345}
1346
1347
dae52d00
MB		 1348static int ngene_start(struct ngene *dev)
1349{
1350 int stat;
1351 int i;
1352
1353 pci_set_master(dev->pci_dev);
1354 ngene_init(dev);
1355
1356 stat = request_irq(dev->pci_dev->irq, irq_handler,
1357 IRQF_SHARED, "nGene",
1358 (void *)dev);
1359 if (stat < 0)
1360 return stat;
1361
1362 init_waitqueue_head(&dev->cmd_wq);
1363 init_waitqueue_head(&dev->tx_wq);
1364 init_waitqueue_head(&dev->rx_wq);
1365 sema_init(&dev->cmd_mutex, 1);
1366 sema_init(&dev->stream_mutex, 1);
1367 sema_init(&dev->pll_mutex, 1);
1368 sema_init(&dev->i2c_switch_mutex, 1);
1369 spin_lock_init(&dev->cmd_lock);
1370 for (i = 0; i < MAX_STREAM; i++)
1371 spin_lock_init(&dev->channel[i].state_lock);
1372 ngwritel(1, TIMESTAMPS);
1373
1374 ngwritel(1, NGENE_INT_ENABLE);
1375
1376 stat = ngene_load_firm(dev);
1377 if (stat < 0)
1378 goto fail;
1379
43874181
OE		 1380#ifdef CONFIG_PCI_MSI
1381 /* enable MSI if kernel and card support it */
478b3a42 1382 if (pci_msi_enabled() && dev->card_info->msi_supported) {
4f77b86c
HV		 1383 unsigned long flags;
1384
43874181
OE		 1385 ngwritel(0, NGENE_INT_ENABLE);
1386 free_irq(dev->pci_dev->irq, dev);
1387 stat = pci_enable_msi(dev->pci_dev);
1388 if (stat) {
1389 printk(KERN_INFO DEVICE_NAME
1390 ": MSI not available\n");
1391 flags = IRQF_SHARED;
1392 } else {
1393 flags = 0;
1394 dev->msi_enabled = true;
1395 }
1396 stat = request_irq(dev->pci_dev->irq, irq_handler,
1397 flags, "nGene", dev);
1398 if (stat < 0)
1399 goto fail2;
1400 ngwritel(1, NGENE_INT_ENABLE);
1401 }
1402#endif
1403
dae52d00
MB		 1404 stat = ngene_i2c_init(dev, 0);
1405 if (stat < 0)
1406 goto fail;
1407
1408 stat = ngene_i2c_init(dev, 1);
1409 if (stat < 0)
1410 goto fail;
1411
43874181
OE		 1412 if (!stat)
1413 return stat;
1414
1415 /* otherwise error: fall through */
dae52d00
MB		 1416fail:
1417 ngwritel(0, NGENE_INT_ENABLE);
1418 free_irq(dev->pci_dev->irq, dev);
478b3a42 1419#ifdef CONFIG_PCI_MSI
43874181
OE		 1420fail2:
1421 if (dev->msi_enabled)
1422 pci_disable_msi(dev->pci_dev);
478b3a42 1423#endif
dae52d00
MB		 1424 return stat;
1425}
1426
83f3c715
OE		 1427/****************************************************************************/
1428/****************************************************************************/
1429/****************************************************************************/
1430
1431static void release_channel(struct ngene_channel *chan)
dae52d00
MB		 1432{
1433 struct dvb_demux *dvbdemux = &chan->demux;
1434 struct ngene *dev = chan->dev;
dae52d00 1435
3d0cef2c 1436 if (chan->running)
b1ec9532 1437 set_transfer(chan, 0);
b1ec9532 1438
dae52d00
MB		 1439 tasklet_kill(&chan->demux_tasklet);
1440
3d0cef2c
OE		 1441 if (chan->ci_dev) {
1442 dvb_unregister_device(chan->ci_dev);
1443 chan->ci_dev = NULL;
1444 }
0f0b270f 1445
3d0cef2c
OE		 1446 if (chan->fe) {
1447 dvb_unregister_frontend(chan->fe);
1448 dvb_frontend_detach(chan->fe);
1449 chan->fe = NULL;
1450 }
1451
1452 if (chan->has_demux) {
cce33c34 1453 dvb_net_release(&chan->dvbnet);
dae52d00
MB		 1454 dvbdemux->dmx.close(&dvbdemux->dmx);
1455 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1456 &chan->hw_frontend);
1457 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1458 &chan->mem_frontend);
1459 dvb_dmxdev_release(&chan->dmxdev);
1460 dvb_dmx_release(&chan->demux);
3d0cef2c
OE		 1461 chan->has_demux = false;
1462 }
cf1b12f2 1463
3d0cef2c
OE		 1464 if (chan->has_adapter) {
1465 dvb_unregister_adapter(&dev->adapter[chan->number]);
1466 chan->has_adapter = false;
dae52d00 1467 }
dae52d00
MB		 1468}
1469
1470static int init_channel(struct ngene_channel *chan)
1471{
1472 int ret = 0, nr = chan->number;
948a1195 1473 struct dvb_adapter *adapter = NULL;
dae52d00
MB		 1474 struct dvb_demux *dvbdemux = &chan->demux;
1475 struct ngene *dev = chan->dev;
1476 struct ngene_info *ni = dev->card_info;
1477 int io = ni->io_type[nr];
1478
1479 tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
1480 chan->users = 0;
1481 chan->type = io;
1482 chan->mode = chan->type; /* for now only one mode */
1483
3d0cef2c
OE		 1484 if (io & NGENE_IO_TSIN) {
1485 chan->fe = NULL;
1486 if (ni->demod_attach[nr]) {
1487 ret = ni->demod_attach[nr](chan);
1488 if (ret < 0)
1489 goto err;
1490 }
1491 if (chan->fe && ni->tuner_attach[nr]) {
1492 ret = ni->tuner_attach[nr](chan);
1493 if (ret < 0)
1494 goto err;
1495 }
1496 }
1497
1498 if (!dev->ci.en && (io & NGENE_IO_TSOUT))
1499 return 0;
1500
dae52d00
MB		 1501 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1502 if (nr >= STREAM_AUDIOIN1)
1503 chan->DataFormatFlags = DF_SWAP32;
0f0b270f 1504
fdafc96c 1505 if (nr == 0 || !one_adapter || dev->first_adapter == NULL) {
cf1b12f2
MB		 1506 adapter = &dev->adapter[nr];
1507 ret = dvb_register_adapter(adapter, "nGene",
1508 THIS_MODULE,
1509 &chan->dev->pci_dev->dev,
1510 adapter_nr);
1511 if (ret < 0)
3d0cef2c 1512 goto err;
fdafc96c
DH		 1513 if (dev->first_adapter == NULL)
1514 dev->first_adapter = adapter;
3d0cef2c
OE		 1515 chan->has_adapter = true;
1516 } else
fdafc96c 1517 adapter = dev->first_adapter;
3d0cef2c
OE		 1518 }
1519
1520 if (dev->ci.en && (io & NGENE_IO_TSOUT)) {
1521 dvb_ca_en50221_init(adapter, dev->ci.en, 0, 1);
1522 set_transfer(chan, 1);
1523 set_transfer(&chan->dev->channel[2], 1);
1524 dvb_register_device(adapter, &chan->ci_dev,
1525 &ngene_dvbdev_ci, (void *) chan,
1526 DVB_DEVICE_SEC);
1527 if (!chan->ci_dev)
1528 goto err;
1529 }
cf1b12f2 1530
3d0cef2c
OE		 1531 if (chan->fe) {
1532 if (dvb_register_frontend(adapter, chan->fe) < 0)
1533 goto err;
1534 chan->has_demux = true;
1535 }
1536
1537 if (chan->has_demux) {
dae52d00
MB		 1538 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1539 ngene_start_feed,
1540 ngene_stop_feed, chan);
1541 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1542 &chan->hw_frontend,
1543 &chan->mem_frontend, adapter);
cce33c34 1544 ret = dvb_net_init(adapter, &chan->dvbnet, &chan->demux.dmx);
dae52d00
MB		 1545 }
1546
dae52d00 1547 return ret;
8a484719 1548
3d0cef2c 1549err:
8a484719
OE		 1550 if (chan->fe) {
1551 dvb_frontend_detach(chan->fe);
1552 chan->fe = NULL;
1553 }
3d0cef2c 1554 release_channel(chan);
8a484719 1555 return 0;
dae52d00
MB		 1556}
1557
1558static int init_channels(struct ngene *dev)
1559{
1560 int i, j;
1561
1562 for (i = 0; i < MAX_STREAM; i++) {
fdafc96c 1563 dev->channel[i].number = i;
dae52d00 1564 if (init_channel(&dev->channel[i]) < 0) {
cf1b12f2 1565 for (j = i - 1; j >= 0; j--)
dae52d00
MB		 1566 release_channel(&dev->channel[j]);
1567 return -1;
1568 }
1569 }
1570 return 0;
1571}
1572
0f0b270f
RM		 1573static void cxd_attach(struct ngene *dev)
1574{
1575 struct ngene_ci *ci = &dev->ci;
1576
1577 ci->en = cxd2099_attach(0x40, dev, &dev->channel[0].i2c_adapter);
1578 ci->dev = dev;
1579 return;
1580}
1581
1582static void cxd_detach(struct ngene *dev)
1583{
1584 struct ngene_ci *ci = &dev->ci;
1585
1586 dvb_ca_en50221_release(ci->en);
1587 kfree(ci->en);
1588 ci->en = 0;
1589}
1590
1b7c41ef
RM		 1591/***********************************/
1592/* workaround for shutdown failure */
1593/***********************************/
1594
1595static void ngene_unlink(struct ngene *dev)
1596{
1597 struct ngene_command com;
1598
1599 com.cmd.hdr.Opcode = CMD_MEM_WRITE;
1600 com.cmd.hdr.Length = 3;
1601 com.cmd.MemoryWrite.address = 0x910c;
1602 com.cmd.MemoryWrite.data = 0xff;
1603 com.in_len = 3;
1604 com.out_len = 1;
1605
1606 down(&dev->cmd_mutex);
1607 ngwritel(0, NGENE_INT_ENABLE);
1608 ngene_command_mutex(dev, &com);
1609 up(&dev->cmd_mutex);
1610}
1611
1612void ngene_shutdown(struct pci_dev *pdev)
1613{
1614 struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev);
1615
1616 if (!dev || !shutdown_workaround)
1617 return;
1618
1619 printk(KERN_INFO DEVICE_NAME ": shutdown workaround...\n");
1620 ngene_unlink(dev);
1621 pci_disable_device(pdev);
1622}
1623
dae52d00
MB		 1624/****************************************************************************/
1625/* device probe/remove calls ************************************************/
1626/****************************************************************************/
1627
cbddcba6 1628void __devexit ngene_remove(struct pci_dev *pdev)
dae52d00 1629{
ecfc95eb 1630 struct ngene *dev = pci_get_drvdata(pdev);
dae52d00
MB		 1631 int i;
1632
1633 tasklet_kill(&dev->event_tasklet);
cf1b12f2 1634 for (i = MAX_STREAM - 1; i >= 0; i--)
dae52d00 1635 release_channel(&dev->channel[i]);
0f0b270f
RM		 1636 if (dev->ci.en)
1637 cxd_detach(dev);
dae52d00
MB		 1638 ngene_stop(dev);
1639 ngene_release_buffers(dev);
7b1fc72c 1640 pci_set_drvdata(pdev, NULL);
dae52d00
MB		 1641 pci_disable_device(pdev);
1642}
1643
cbddcba6
DH		 1644int __devinit ngene_probe(struct pci_dev *pci_dev,
1645 const struct pci_device_id *id)
dae52d00
MB		 1646{
1647 struct ngene *dev;
1648 int stat = 0;
1649
1650 if (pci_enable_device(pci_dev) < 0)
1651 return -ENODEV;
1652
101b25b5 1653 dev = vzalloc(sizeof(struct ngene));
dc35c9ae
RP		 1654 if (dev == NULL) {
1655 stat = -ENOMEM;
1656 goto fail0;
1657 }
dae52d00
MB		 1658
1659 dev->pci_dev = pci_dev;
1660 dev->card_info = (struct ngene_info *)id->driver_data;
1661 printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name);
1662
1663 pci_set_drvdata(pci_dev, dev);
1664
1665 /* Alloc buffers and start nGene */
1666 stat = ngene_get_buffers(dev);
1667 if (stat < 0)
1668 goto fail1;
1669 stat = ngene_start(dev);
1670 if (stat < 0)
1671 goto fail1;
1672
0f0b270f
RM		 1673 cxd_attach(dev);
1674
1675 stat = ngene_buffer_config(dev);
1676 if (stat < 0)
1677 goto fail1;
1678
1679
dae52d00 1680 dev->i2c_current_bus = -1;
dae52d00
MB		 1681
1682 /* Register DVB adapters and devices for both channels */
dae52d00
MB		 1683 if (init_channels(dev) < 0)
1684 goto fail2;
1685
1686 return 0;
1687
1688fail2:
1689 ngene_stop(dev);
1690fail1:
1691 ngene_release_buffers(dev);
dc35c9ae
RP		 1692fail0:
1693 pci_disable_device(pci_dev);
7b1fc72c 1694 pci_set_drvdata(pci_dev, NULL);
dae52d00
MB		 1695 return stat;
1696}
kernel source for telekom puls (alcatel/mediatek)