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V4L/DVB: ngene: Change severity of some diagnostic messages
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / dvb / ngene / ngene-core.c
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dae52d00
MB		 1/*
2 * ngene.c: nGene PCIe bridge driver
3 *
4 * Copyright (C) 2005-2007 Micronas
5 *
6 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
7 * Modifications for new nGene firmware,
8 * support for EEPROM-copying,
9 * support for new dual DVB-S2 card prototype
10 *
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 only, as published by the Free Software Foundation.
15 *
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
26 * 02110-1301, USA
27 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
28 */
29
30#include <linux/module.h>
31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
34#include <linux/poll.h>
35#include <asm/io.h>
36#include <asm/div64.h>
37#include <linux/pci.h>
38#include <linux/pci_ids.h>
39#include <linux/smp_lock.h>
40#include <linux/timer.h>
41#include <linux/version.h>
42#include <linux/byteorder/generic.h>
43#include <linux/firmware.h>
44
45#include "ngene.h"
46
8bba2607
MB		 47#include "stv6110x.h"
48#include "stv090x.h"
49#include "lnbh24.h"
50
dae52d00
MB		 51#ifdef NGENE_COMMAND_API
52#include "ngene-ioctls.h"
53#endif
54
dae52d00
MB		 55static int copy_eeprom;
56module_param(copy_eeprom, int, 0444);
57MODULE_PARM_DESC(copy_eeprom, "Copy eeprom.");
58
dae52d00
MB		 59static int debug;
60module_param(debug, int, 0444);
61MODULE_PARM_DESC(debug, "Print debugging information.");
62
83f3c715
OE		 63DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
64
dae52d00
MB		 65#define dprintk if (debug) printk
66
67#define DEVICE_NAME "ngene"
68
69#define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr)))
70#define ngwritel(dat, adr) writel((dat), (char *)(dev->iomem + (adr)))
71#define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr)))
72#define ngreadl(adr) readl(dev->iomem + (adr))
73#define ngreadb(adr) readb(dev->iomem + (adr))
74#define ngcpyto(adr, src, count) memcpy_toio((char *) \
75 (dev->iomem + (adr)), (src), (count))
76#define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \
77 (dev->iomem + (adr)), (count))
78
79/****************************************************************************/
80/* Functions with missing kernel exports ************************************/
81/****************************************************************************/
82
83/* yeah, let's throw out all exports which are not used in kernel ... */
84
85void my_dvb_ringbuffer_flush(struct dvb_ringbuffer *rbuf)
86{
87 rbuf->pread = rbuf->pwrite;
88 rbuf->error = 0;
89}
90
91/****************************************************************************/
92/* nGene interrupt handler **************************************************/
93/****************************************************************************/
94
95static void event_tasklet(unsigned long data)
96{
97 struct ngene *dev = (struct ngene *)data;
98
99 while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
100 struct EVENT_BUFFER Event =
101 dev->EventQueue[dev->EventQueueReadIndex];
102 dev->EventQueueReadIndex =
103 (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
104
105 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
106 dev->TxEventNotify(dev, Event.TimeStamp);
107 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
108 dev->RxEventNotify(dev, Event.TimeStamp,
109 Event.RXCharacter);
110 }
111}
112
113static void demux_tasklet(unsigned long data)
114{
115 struct ngene_channel *chan = (struct ngene_channel *)data;
116 struct SBufferHeader *Cur = chan->nextBuffer;
117
118 spin_lock_irq(&chan->state_lock);
119
120 while (Cur->ngeneBuffer.SR.Flags & 0x80) {
121 if (chan->mode & NGENE_IO_TSOUT) {
122 u32 Flags = chan->DataFormatFlags;
123 if (Cur->ngeneBuffer.SR.Flags & 0x20)
124 Flags |= BEF_OVERFLOW;
125 if (chan->pBufferExchange) {
126 if (!chan->pBufferExchange(chan,
127 Cur->Buffer1,
128 chan->Capture1Length,
129 Cur->ngeneBuffer.SR.
130 Clock, Flags)) {
131 /*
132 We didn't get data
133 Clear in service flag to make sure we
134 get called on next interrupt again.
135 leave fill/empty (0x80) flag alone
136 to avoid hardware running out of
137 buffers during startup, we hold only
138 in run state ( the source may be late
139 delivering data )
140 */
141
142 if (chan->HWState == HWSTATE_RUN) {
143 Cur->ngeneBuffer.SR.Flags &=
144 ~0x40;
145 break;
146 /* Stop proccessing stream */
147 }
148 } else {
149 /* We got a valid buffer,
150 so switch to run state */
151 chan->HWState = HWSTATE_RUN;
152 }
153 } else {
154 printk(KERN_ERR DEVICE_NAME ": OOPS\n");
155 if (chan->HWState == HWSTATE_RUN) {
156 Cur->ngeneBuffer.SR.Flags &= ~0x40;
157 break; /* Stop proccessing stream */
158 }
159 }
160 if (chan->AudioDTOUpdated) {
161 printk(KERN_INFO DEVICE_NAME
162 ": Update AudioDTO = %d\n",
163 chan->AudioDTOValue);
164 Cur->ngeneBuffer.SR.DTOUpdate =
165 chan->AudioDTOValue;
166 chan->AudioDTOUpdated = 0;
167 }
168 } else {
169 if (chan->HWState == HWSTATE_RUN) {
170 u32 Flags = 0;
171 if (Cur->ngeneBuffer.SR.Flags & 0x01)
172 Flags |= BEF_EVEN_FIELD;
173 if (Cur->ngeneBuffer.SR.Flags & 0x20)
174 Flags |= BEF_OVERFLOW;
175 if (chan->pBufferExchange)
176 chan->pBufferExchange(chan,
177 Cur->Buffer1,
178 chan->
179 Capture1Length,
180 Cur->ngeneBuffer.
181 SR.Clock, Flags);
182 if (chan->pBufferExchange2)
183 chan->pBufferExchange2(chan,
184 Cur->Buffer2,
185 chan->
186 Capture2Length,
187 Cur->ngeneBuffer.
188 SR.Clock, Flags);
189 } else if (chan->HWState != HWSTATE_STOP)
190 chan->HWState = HWSTATE_RUN;
191 }
192 Cur->ngeneBuffer.SR.Flags = 0x00;
193 Cur = Cur->Next;
194 }
195 chan->nextBuffer = Cur;
196
197 spin_unlock_irq(&chan->state_lock);
198}
199
200static irqreturn_t irq_handler(int irq, void *dev_id)
201{
202 struct ngene *dev = (struct ngene *)dev_id;
203 u32 icounts = 0;
204 irqreturn_t rc = IRQ_NONE;
205 u32 i = MAX_STREAM;
206 u8 *tmpCmdDoneByte;
207
208 if (dev->BootFirmware) {
209 icounts = ngreadl(NGENE_INT_COUNTS);
210 if (icounts != dev->icounts) {
211 ngwritel(0, FORCE_NMI);
212 dev->cmd_done = 1;
213 wake_up(&dev->cmd_wq);
214 dev->icounts = icounts;
215 rc = IRQ_HANDLED;
216 }
217 return rc;
218 }
219
220 ngwritel(0, FORCE_NMI);
221
222 spin_lock(&dev->cmd_lock);
223 tmpCmdDoneByte = dev->CmdDoneByte;
224 if (tmpCmdDoneByte &&
225 (*tmpCmdDoneByte ||
226 (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
227 dev->CmdDoneByte = NULL;
228 dev->cmd_done = 1;
229 wake_up(&dev->cmd_wq);
230 rc = IRQ_HANDLED;
231 }
232 spin_unlock(&dev->cmd_lock);
233
234 if (dev->EventBuffer->EventStatus & 0x80) {
235 u8 nextWriteIndex =
236 (dev->EventQueueWriteIndex + 1) &
237 (EVENT_QUEUE_SIZE - 1);
238 if (nextWriteIndex != dev->EventQueueReadIndex) {
239 dev->EventQueue[dev->EventQueueWriteIndex] =
240 *(dev->EventBuffer);
241 dev->EventQueueWriteIndex = nextWriteIndex;
242 } else {
243 printk(KERN_ERR DEVICE_NAME ": event overflow\n");
244 dev->EventQueueOverflowCount += 1;
245 dev->EventQueueOverflowFlag = 1;
246 }
247 dev->EventBuffer->EventStatus &= ~0x80;
248 tasklet_schedule(&dev->event_tasklet);
249 rc = IRQ_HANDLED;
250 }
251
252 while (i > 0) {
253 i--;
254 spin_lock(&dev->channel[i].state_lock);
255 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
256 if (dev->channel[i].nextBuffer) {
257 if ((dev->channel[i].nextBuffer->
258 ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
259 dev->channel[i].nextBuffer->
260 ngeneBuffer.SR.Flags |= 0x40;
261 tasklet_schedule(
262 &dev->channel[i].demux_tasklet);
263 rc = IRQ_HANDLED;
264 }
265 }
266 spin_unlock(&dev->channel[i].state_lock);
267 }
268
269 return rc;
270}
271
272/****************************************************************************/
273/* nGene command interface **************************************************/
274/****************************************************************************/
275
276static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
277{
278 int ret;
279 u8 *tmpCmdDoneByte;
280
281 dev->cmd_done = 0;
282
283 if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
284 dev->BootFirmware = 1;
285 dev->icounts = ngreadl(NGENE_INT_COUNTS);
286 ngwritel(0, NGENE_COMMAND);
287 ngwritel(0, NGENE_COMMAND_HI);
288 ngwritel(0, NGENE_STATUS);
289 ngwritel(0, NGENE_STATUS_HI);
290 ngwritel(0, NGENE_EVENT);
291 ngwritel(0, NGENE_EVENT_HI);
292 } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
293 u64 fwio = dev->PAFWInterfaceBuffer;
294
295 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
296 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
297 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
298 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
299 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
300 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
301 }
302
303 memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
304
305 if (dev->BootFirmware)
306 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
307
308 spin_lock_irq(&dev->cmd_lock);
309 tmpCmdDoneByte = dev->ngenetohost + com->out_len;
310 if (!com->out_len)
311 tmpCmdDoneByte++;
312 *tmpCmdDoneByte = 0;
313 dev->ngenetohost[0] = 0;
314 dev->ngenetohost[1] = 0;
315 dev->CmdDoneByte = tmpCmdDoneByte;
316 spin_unlock_irq(&dev->cmd_lock);
317
318 /* Notify 8051. */
319 ngwritel(1, FORCE_INT);
320
321 ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
322 if (!ret) {
323 /*ngwritel(0, FORCE_NMI);*/
324
325 printk(KERN_ERR DEVICE_NAME
326 ": Command timeout cmd=%02x prev=%02x\n",
327 com->cmd.hdr.Opcode, dev->prev_cmd);
328 return -1;
329 }
330 if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
331 dev->BootFirmware = 0;
332
333 dev->prev_cmd = com->cmd.hdr.Opcode;
dae52d00
MB		 334
335 if (!com->out_len)
336 return 0;
337
338 memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
339
340 return 0;
341}
342
343static int ngene_command(struct ngene *dev, struct ngene_command *com)
344{
345 int result;
346
347 down(&dev->cmd_mutex);
348 result = ngene_command_mutex(dev, com);
349 up(&dev->cmd_mutex);
350 return result;
351}
352
353int ngene_command_nop(struct ngene *dev)
354{
355 struct ngene_command com;
356
357 com.cmd.hdr.Opcode = CMD_NOP;
358 com.cmd.hdr.Length = 0;
359 com.in_len = 0;
360 com.out_len = 0;
361
362 return ngene_command(dev, &com);
363}
364
365int ngene_command_i2c_read(struct ngene *dev, u8 adr,
366 u8 *out, u8 outlen, u8 *in, u8 inlen, int flag)
367{
368 struct ngene_command com;
369
370 com.cmd.hdr.Opcode = CMD_I2C_READ;
371 com.cmd.hdr.Length = outlen + 3;
372 com.cmd.I2CRead.Device = adr << 1;
373 memcpy(com.cmd.I2CRead.Data, out, outlen);
374 com.cmd.I2CRead.Data[outlen] = inlen;
375 com.cmd.I2CRead.Data[outlen + 1] = 0;
376 com.in_len = outlen + 3;
377 com.out_len = inlen + 1;
378
379 if (ngene_command(dev, &com) < 0)
380 return -EIO;
381
382 if ((com.cmd.raw8[0] >> 1) != adr)
383 return -EIO;
384
385 if (flag)
386 memcpy(in, com.cmd.raw8, inlen + 1);
387 else
388 memcpy(in, com.cmd.raw8 + 1, inlen);
389 return 0;
390}
391
392int ngene_command_i2c_write(struct ngene *dev, u8 adr, u8 *out, u8 outlen)
393{
394 struct ngene_command com;
395
396
397 com.cmd.hdr.Opcode = CMD_I2C_WRITE;
398 com.cmd.hdr.Length = outlen + 1;
399 com.cmd.I2CRead.Device = adr << 1;
400 memcpy(com.cmd.I2CRead.Data, out, outlen);
401 com.in_len = outlen + 1;
402 com.out_len = 1;
403
404 if (ngene_command(dev, &com) < 0)
405 return -EIO;
406
407 if (com.cmd.raw8[0] == 1)
408 return -EIO;
409
410 return 0;
411}
412
413static int ngene_command_load_firmware(struct ngene *dev,
414 u8 *ngene_fw, u32 size)
415{
416#define FIRSTCHUNK (1024)
417 u32 cleft;
418 struct ngene_command com;
419
420 com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
421 com.cmd.hdr.Length = 0;
422 com.in_len = 0;
423 com.out_len = 0;
424
425 ngene_command(dev, &com);
426
427 cleft = (size + 3) & ~3;
428 if (cleft > FIRSTCHUNK) {
429 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
430 cleft - FIRSTCHUNK);
431 cleft = FIRSTCHUNK;
432 }
dae52d00
MB		 433 ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
434
435 memset(&com, 0, sizeof(struct ngene_command));
436 com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
437 com.cmd.hdr.Length = 4;
438 com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
439 com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
440 com.in_len = 4;
441 com.out_len = 0;
442
443 return ngene_command(dev, &com);
444}
445
446int ngene_command_imem_read(struct ngene *dev, u8 adr, u8 *data, int type)
447{
448 struct ngene_command com;
449
450 com.cmd.hdr.Opcode = type ? CMD_SFR_READ : CMD_IRAM_READ;
451 com.cmd.hdr.Length = 1;
452 com.cmd.SfrIramRead.address = adr;
453 com.in_len = 1;
454 com.out_len = 2;
455
456 if (ngene_command(dev, &com) < 0)
457 return -EIO;
458
459 *data = com.cmd.raw8[1];
460 return 0;
461}
462
463int ngene_command_imem_write(struct ngene *dev, u8 adr, u8 data, int type)
464{
465 struct ngene_command com;
466
467 com.cmd.hdr.Opcode = type ? CMD_SFR_WRITE : CMD_IRAM_WRITE;
468 com.cmd.hdr.Length = 2;
469 com.cmd.SfrIramWrite.address = adr;
470 com.cmd.SfrIramWrite.data = data;
471 com.in_len = 2;
472 com.out_len = 1;
473
474 if (ngene_command(dev, &com) < 0)
475 return -EIO;
476
477 return 0;
478}
479
480static int ngene_command_config_uart(struct ngene *dev, u8 config,
481 tx_cb_t *tx_cb, rx_cb_t *rx_cb)
482{
483 struct ngene_command com;
484
485 com.cmd.hdr.Opcode = CMD_CONFIGURE_UART;
486 com.cmd.hdr.Length = sizeof(struct FW_CONFIGURE_UART) - 2;
487 com.cmd.ConfigureUart.UartControl = config;
488 com.in_len = sizeof(struct FW_CONFIGURE_UART);
489 com.out_len = 0;
490
491 if (ngene_command(dev, &com) < 0)
492 return -EIO;
493
494 dev->TxEventNotify = tx_cb;
495 dev->RxEventNotify = rx_cb;
496
497 dprintk(KERN_DEBUG DEVICE_NAME ": Set UART config %02x.\n", config);
498
499 return 0;
500}
501
502static void tx_cb(struct ngene *dev, u32 ts)
503{
504 dev->tx_busy = 0;
505 wake_up_interruptible(&dev->tx_wq);
506}
507
508static void rx_cb(struct ngene *dev, u32 ts, u8 c)
509{
510 int rp = dev->uart_rp;
511 int nwp, wp = dev->uart_wp;
512
513 /* dprintk(KERN_DEBUG DEVICE_NAME ": %c\n", c); */
514 nwp = (wp + 1) % (UART_RBUF_LEN);
515 if (nwp == rp)
516 return;
517 dev->uart_rbuf[wp] = c;
518 dev->uart_wp = nwp;
519 wake_up_interruptible(&dev->rx_wq);
520}
521
522static int ngene_command_config_buf(struct ngene *dev, u8 config)
523{
524 struct ngene_command com;
525
526 com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
527 com.cmd.hdr.Length = 1;
528 com.cmd.ConfigureBuffers.config = config;
529 com.in_len = 1;
530 com.out_len = 0;
531
532 if (ngene_command(dev, &com) < 0)
533 return -EIO;
534 return 0;
535}
536
537static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
538{
539 struct ngene_command com;
540
541 com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
542 com.cmd.hdr.Length = 6;
543 memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
544 com.in_len = 6;
545 com.out_len = 0;
546
547 if (ngene_command(dev, &com) < 0)
548 return -EIO;
549
550 return 0;
551}
552
553static int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
554{
555 struct ngene_command com;
556
557 com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
558 com.cmd.hdr.Length = 1;
559 com.cmd.SetGpioPin.select = select | (level << 7);
560 com.in_len = 1;
561 com.out_len = 0;
562
563 return ngene_command(dev, &com);
564}
565
566/* The reset is only wired to GPIO4 on MicRacer Revision 1.10 !
567 Also better set bootdelay to 1 in nvram or less. */
568static void ngene_reset_decypher(struct ngene *dev)
569{
570 printk(KERN_INFO DEVICE_NAME ": Resetting Decypher.\n");
571 ngene_command_gpio_set(dev, 4, 0);
572 msleep(1);
573 ngene_command_gpio_set(dev, 4, 1);
574 msleep(2000);
575}
576
577/*
578 02000640 is sample on rising edge.
579 02000740 is sample on falling edge.
580 02000040 is ignore "valid" signal
581
582 0: FD_CTL1 Bit 7,6 must be 0,1
583 7 disable(fw controlled)
584 6 0-AUX,1-TS
585 5 0-par,1-ser
586 4 0-lsb/1-msb
587 3,2 reserved
588 1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
589 1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
590 2: FD_STA is read-only. 0-sync
591 3: FD_INSYNC is number of 47s to trigger "in sync".
592 4: FD_OUTSYNC is number of 47s to trigger "out of sync".
593 5: FD_MAXBYTE1 is low-order of bytes per packet.
594 6: FD_MAXBYTE2 is high-order of bytes per packet.
595 7: Top byte is unused.
596*/
597
598/****************************************************************************/
599
600static u8 TSFeatureDecoderSetup[8 * 4] = {
601 0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
602 0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
603 0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
604 0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
605};
606
607/* Set NGENE I2S Config to 16 bit packed */
608static u8 I2SConfiguration[] = {
609 0x00, 0x10, 0x00, 0x00,
610 0x80, 0x10, 0x00, 0x00,
611};
612
613static u8 SPDIFConfiguration[10] = {
614 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
615};
616
617/* Set NGENE I2S Config to transport stream compatible mode */
618
619static u8 TS_I2SConfiguration[4] = { 0x3E, 0x1A, 0x00, 0x00 }; /*3e 18 00 00 ?*/
620
621static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x20, 0x00, 0x00 };
622
623static u8 ITUDecoderSetup[4][16] = {
624 {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */
625 0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
626 {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
627 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
628 {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00, /* HDTV 1080i50 */
629 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
630 {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, /* HDTV 1080i60 */
631 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
632};
633
634/*
635 * 50 48 60 gleich
636 * 27p50 9f 00 22 80 42 69 18 ...
637 * 27p60 93 00 22 80 82 69 1c ...
638 */
639
640/* Maxbyte to 1144 (for raw data) */
641static u8 ITUFeatureDecoderSetup[8] = {
642 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
643};
644
645static void FillTSBuffer(void *Buffer, int Length, u32 Flags)
646{
647 u32 *ptr = Buffer;
648
649 memset(Buffer, Length, 0xff);
650 while (Length > 0) {
651 if (Flags & DF_SWAP32)
652 *ptr = 0x471FFF10;
653 else
654 *ptr = 0x10FF1F47;
655 ptr += (188 / 4);
656 Length -= 188;
657 }
658}
659
dae52d00
MB		 660
661static void flush_buffers(struct ngene_channel *chan)
662{
663 u8 val;
664
665 do {
666 msleep(1);
667 spin_lock_irq(&chan->state_lock);
668 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
669 spin_unlock_irq(&chan->state_lock);
670 } while (val);
671}
672
673static void clear_buffers(struct ngene_channel *chan)
674{
675 struct SBufferHeader *Cur = chan->nextBuffer;
676
677 do {
678 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
679 if (chan->mode & NGENE_IO_TSOUT)
680 FillTSBuffer(Cur->Buffer1,
681 chan->Capture1Length,
682 chan->DataFormatFlags);
683 Cur = Cur->Next;
684 } while (Cur != chan->nextBuffer);
685
686 if (chan->mode & NGENE_IO_TSOUT) {
687 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
688 chan->AudioDTOValue;
689 chan->AudioDTOUpdated = 0;
690
691 Cur = chan->TSIdleBuffer.Head;
692
693 do {
694 memset(&Cur->ngeneBuffer.SR, 0,
695 sizeof(Cur->ngeneBuffer.SR));
696 FillTSBuffer(Cur->Buffer1,
697 chan->Capture1Length,
698 chan->DataFormatFlags);
699 Cur = Cur->Next;
700 } while (Cur != chan->TSIdleBuffer.Head);
701 }
702}
703
704int ngene_command_stream_control(struct ngene *dev, u8 stream, u8 control,
705 u8 mode, u8 flags)
706{
707 struct ngene_channel *chan = &dev->channel[stream];
708 struct ngene_command com;
709 u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
710 u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
711 u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
712 u16 BsSDO = 0x9B00;
713
714 /* down(&dev->stream_mutex); */
715 while (down_trylock(&dev->stream_mutex)) {
716 printk(KERN_INFO DEVICE_NAME ": SC locked\n");
717 msleep(1);
718 }
719 memset(&com, 0, sizeof(com));
720 com.cmd.hdr.Opcode = CMD_CONTROL;
721 com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
722 com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
723 if (chan->mode & NGENE_IO_TSOUT)
724 com.cmd.StreamControl.Stream |= 0x07;
725 com.cmd.StreamControl.Control = control |
726 (flags & SFLAG_ORDER_LUMA_CHROMA);
727 com.cmd.StreamControl.Mode = mode;
728 com.in_len = sizeof(struct FW_STREAM_CONTROL);
729 com.out_len = 0;
730
44cdd064
OE		 731 dprintk(KERN_INFO DEVICE_NAME
732 ": Stream=%02x, Control=%02x, Mode=%02x\n",
733 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
734 com.cmd.StreamControl.Mode);
735
dae52d00
MB		 736 chan->Mode = mode;
737
738 if (!(control & 0x80)) {
739 spin_lock_irq(&chan->state_lock);
740 if (chan->State == KSSTATE_RUN) {
741 chan->State = KSSTATE_ACQUIRE;
742 chan->HWState = HWSTATE_STOP;
743 spin_unlock_irq(&chan->state_lock);
744 if (ngene_command(dev, &com) < 0) {
745 up(&dev->stream_mutex);
746 return -1;
747 }
748 /* clear_buffers(chan); */
749 flush_buffers(chan);
750 up(&dev->stream_mutex);
751 return 0;
752 }
753 spin_unlock_irq(&chan->state_lock);
754 up(&dev->stream_mutex);
755 return 0;
756 }
757
758 if (mode & SMODE_AUDIO_CAPTURE) {
759 com.cmd.StreamControl.CaptureBlockCount =
760 chan->Capture1Length / AUDIO_BLOCK_SIZE;
761 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
762 } else if (mode & SMODE_TRANSPORT_STREAM) {
763 com.cmd.StreamControl.CaptureBlockCount =
764 chan->Capture1Length / TS_BLOCK_SIZE;
765 com.cmd.StreamControl.MaxLinesPerField =
766 chan->Capture1Length / TS_BLOCK_SIZE;
767 com.cmd.StreamControl.Buffer_Address =
768 chan->TSRingBuffer.PAHead;
769 if (chan->mode & NGENE_IO_TSOUT) {
770 com.cmd.StreamControl.BytesPerVBILine =
771 chan->Capture1Length / TS_BLOCK_SIZE;
772 com.cmd.StreamControl.Stream |= 0x07;
773 }
774 } else {
775 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
776 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
777 com.cmd.StreamControl.MinLinesPerField = 100;
778 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
779
780 if (mode & SMODE_VBI_CAPTURE) {
781 com.cmd.StreamControl.MaxVBILinesPerField =
782 chan->nVBILines;
783 com.cmd.StreamControl.MinVBILinesPerField = 0;
784 com.cmd.StreamControl.BytesPerVBILine =
785 chan->nBytesPerVBILine;
786 }
787 if (flags & SFLAG_COLORBAR)
788 com.cmd.StreamControl.Stream |= 0x04;
789 }
790
791 spin_lock_irq(&chan->state_lock);
792 if (mode & SMODE_AUDIO_CAPTURE) {
793 chan->nextBuffer = chan->RingBuffer.Head;
794 if (mode & SMODE_AUDIO_SPDIF) {
795 com.cmd.StreamControl.SetupDataLen =
796 sizeof(SPDIFConfiguration);
797 com.cmd.StreamControl.SetupDataAddr = BsSPI;
798 memcpy(com.cmd.StreamControl.SetupData,
799 SPDIFConfiguration, sizeof(SPDIFConfiguration));
800 } else {
801 com.cmd.StreamControl.SetupDataLen = 4;
802 com.cmd.StreamControl.SetupDataAddr = BsSDI;
803 memcpy(com.cmd.StreamControl.SetupData,
804 I2SConfiguration +
805 4 * dev->card_info->i2s[stream], 4);
806 }
807 } else if (mode & SMODE_TRANSPORT_STREAM) {
808 chan->nextBuffer = chan->TSRingBuffer.Head;
809 if (stream >= STREAM_AUDIOIN1) {
810 if (chan->mode & NGENE_IO_TSOUT) {
811 com.cmd.StreamControl.SetupDataLen =
812 sizeof(TS_I2SOutConfiguration);
813 com.cmd.StreamControl.SetupDataAddr = BsSDO;
814 memcpy(com.cmd.StreamControl.SetupData,
815 TS_I2SOutConfiguration,
816 sizeof(TS_I2SOutConfiguration));
817 } else {
818 com.cmd.StreamControl.SetupDataLen =
819 sizeof(TS_I2SConfiguration);
820 com.cmd.StreamControl.SetupDataAddr = BsSDI;
821 memcpy(com.cmd.StreamControl.SetupData,
822 TS_I2SConfiguration,
823 sizeof(TS_I2SConfiguration));
824 }
825 } else {
826 com.cmd.StreamControl.SetupDataLen = 8;
827 com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
828 memcpy(com.cmd.StreamControl.SetupData,
829 TSFeatureDecoderSetup +
830 8 * dev->card_info->tsf[stream], 8);
831 }
832 } else {
833 chan->nextBuffer = chan->RingBuffer.Head;
834 com.cmd.StreamControl.SetupDataLen =
835 16 + sizeof(ITUFeatureDecoderSetup);
836 com.cmd.StreamControl.SetupDataAddr = BsUVI;
837 memcpy(com.cmd.StreamControl.SetupData,
838 ITUDecoderSetup[chan->itumode], 16);
839 memcpy(com.cmd.StreamControl.SetupData + 16,
840 ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
841 }
842 clear_buffers(chan);
843 chan->State = KSSTATE_RUN;
844 if (mode & SMODE_TRANSPORT_STREAM)
845 chan->HWState = HWSTATE_RUN;
846 else
847 chan->HWState = HWSTATE_STARTUP;
848 spin_unlock_irq(&chan->state_lock);
849
850 if (ngene_command(dev, &com) < 0) {
851 up(&dev->stream_mutex);
852 return -1;
853 }
854 up(&dev->stream_mutex);
855 return 0;
856}
857
858int ngene_stream_control(struct ngene *dev, u8 stream, u8 control, u8 mode,
859 u16 lines, u16 bpl, u16 vblines, u16 vbibpl)
860{
861 if (!(mode & SMODE_TRANSPORT_STREAM))
862 return -EINVAL;
863
864 if (lines * bpl > MAX_VIDEO_BUFFER_SIZE)
865 return -EINVAL;
866
867 if ((mode & SMODE_TRANSPORT_STREAM) && (((bpl * lines) & 0xff) != 0))
868 return -EINVAL;
869
870 if ((mode & SMODE_VIDEO_CAPTURE) && (bpl & 7) != 0)
871 return -EINVAL;
872
873 return ngene_command_stream_control(dev, stream, control, mode, 0);
874}
875
876/****************************************************************************/
877/* I2C **********************************************************************/
878/****************************************************************************/
879
880static void ngene_i2c_set_bus(struct ngene *dev, int bus)
881{
882 if (!(dev->card_info->i2c_access & 2))
883 return;
884 if (dev->i2c_current_bus == bus)
885 return;
886
887 switch (bus) {
888 case 0:
889 ngene_command_gpio_set(dev, 3, 0);
890 ngene_command_gpio_set(dev, 2, 1);
891 break;
892
893 case 1:
894 ngene_command_gpio_set(dev, 2, 0);
895 ngene_command_gpio_set(dev, 3, 1);
896 break;
897 }
898 dev->i2c_current_bus = bus;
899}
900
901static int ngene_i2c_master_xfer(struct i2c_adapter *adapter,
902 struct i2c_msg msg[], int num)
903{
904 struct ngene_channel *chan =
905 (struct ngene_channel *)i2c_get_adapdata(adapter);
906 struct ngene *dev = chan->dev;
907
908 down(&dev->i2c_switch_mutex);
909 ngene_i2c_set_bus(dev, chan->number);
910
911 if (num == 2 && msg[1].flags & I2C_M_RD && !(msg[0].flags & I2C_M_RD))
912 if (!ngene_command_i2c_read(dev, msg[0].addr,
913 msg[0].buf, msg[0].len,
914 msg[1].buf, msg[1].len, 0))
915 goto done;
916
917 if (num == 1 && !(msg[0].flags & I2C_M_RD))
918 if (!ngene_command_i2c_write(dev, msg[0].addr,
919 msg[0].buf, msg[0].len))
920 goto done;
921 if (num == 1 && (msg[0].flags & I2C_M_RD))
922 if (!ngene_command_i2c_read(dev, msg[0].addr, 0, 0,
923 msg[0].buf, msg[0].len, 0))
924 goto done;
925
926 up(&dev->i2c_switch_mutex);
927 return -EIO;
928
929done:
930 up(&dev->i2c_switch_mutex);
931 return num;
932}
933
934
dae52d00
MB		 935
936static u32 ngene_i2c_functionality(struct i2c_adapter *adap)
937{
938 return I2C_FUNC_SMBUS_EMUL;
939}
940
941struct i2c_algorithm ngene_i2c_algo = {
942 .master_xfer = ngene_i2c_master_xfer,
943 .functionality = ngene_i2c_functionality,
944};
945
dae52d00
MB		 946static int ngene_i2c_init(struct ngene *dev, int dev_nr)
947{
948 struct i2c_adapter *adap = &(dev->channel[dev_nr].i2c_adapter);
949
950 i2c_set_adapdata(adap, &(dev->channel[dev_nr]));
951#ifdef I2C_ADAP_CLASS_TV_DIGITAL
952 adap->class = I2C_ADAP_CLASS_TV_DIGITAL | I2C_CLASS_TV_ANALOG;
953#else
954 adap->class = I2C_CLASS_TV_ANALOG;
955#endif
956
957 strcpy(adap->name, "nGene");
958
959 adap->id = I2C_HW_SAA7146;
dae52d00
MB		 960 adap->algo = &ngene_i2c_algo;
961 adap->algo_data = (void *)&(dev->channel[dev_nr]);
962
963 mutex_init(&adap->bus_lock);
964 return i2c_add_adapter(adap);
965}
966
967int i2c_write(struct i2c_adapter *adapter, u8 adr, u8 data)
968{
969 u8 m[1] = {data};
970 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 1};
971
972 if (i2c_transfer(adapter, &msg, 1) != 1) {
973 printk(KERN_ERR DEVICE_NAME
974 ": Failed to write to I2C adr %02x!\n", adr);
975 return -1;
976 }
977 return 0;
978}
979
dae52d00
MB		 980
981static int i2c_write_read(struct i2c_adapter *adapter,
982 u8 adr, u8 *w, u8 wlen, u8 *r, u8 rlen)
983{
984 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
985 .buf = w, .len = wlen},
986 {.addr = adr, .flags = I2C_M_RD,
987 .buf = r, .len = rlen} };
988
989 if (i2c_transfer(adapter, msgs, 2) != 2) {
990 printk(KERN_ERR DEVICE_NAME ": error in i2c_write_read\n");
991 return -1;
992 }
993 return 0;
994}
995
996static int test_dec_i2c(struct i2c_adapter *adapter, int reg)
997{
998 u8 data[256] = { reg, 0x00, 0x93, 0x78, 0x43, 0x45 };
999 u8 data2[256];
1000 int i;
1001
1002 memset(data2, 0, 256);
1003 i2c_write_read(adapter, 0x66, data, 2, data2, 4);
1004 for (i = 0; i < 4; i++)
1005 printk("%02x ", data2[i]);
1006 printk("\n");
1007
1008 return 0;
1009}
1010
1011
1012/****************************************************************************/
1013/* EEPROM TAGS **************************************************************/
1014/****************************************************************************/
1015
1016#define MICNG_EE_START 0x0100
1017#define MICNG_EE_END 0x0FF0
1018
1019#define MICNG_EETAG_END0 0x0000
1020#define MICNG_EETAG_END1 0xFFFF
1021
1022/* 0x0001 - 0x000F reserved for housekeeping */
1023/* 0xFFFF - 0xFFFE reserved for housekeeping */
1024
1025/* Micronas assigned tags
1026 EEProm tags for hardware support */
1027
1028#define MICNG_EETAG_DRXD1_OSCDEVIATION 0x1000 /* 2 Bytes data */
1029#define MICNG_EETAG_DRXD2_OSCDEVIATION 0x1001 /* 2 Bytes data */
1030
1031#define MICNG_EETAG_MT2060_1_1STIF 0x1100 /* 2 Bytes data */
1032#define MICNG_EETAG_MT2060_2_1STIF 0x1101 /* 2 Bytes data */
1033
1034/* Tag range for OEMs */
1035
1036#define MICNG_EETAG_OEM_FIRST 0xC000
1037#define MICNG_EETAG_OEM_LAST 0xFFEF
1038
1039static int i2c_write_eeprom(struct i2c_adapter *adapter,
1040 u8 adr, u16 reg, u8 data)
1041{
1042 u8 m[3] = {(reg >> 8), (reg & 0xff), data};
1043 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m,
1044 .len = sizeof(m)};
1045
1046 if (i2c_transfer(adapter, &msg, 1) != 1) {
44cdd064 1047 dprintk(KERN_ERR DEVICE_NAME ": Error writing EEPROM!\n");
dae52d00
MB		 1048 return -EIO;
1049 }
1050 return 0;
1051}
1052
1053static int i2c_read_eeprom(struct i2c_adapter *adapter,
1054 u8 adr, u16 reg, u8 *data, int len)
1055{
1056 u8 msg[2] = {(reg >> 8), (reg & 0xff)};
1057 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
1058 .buf = msg, .len = 2 },
1059 {.addr = adr, .flags = I2C_M_RD,
1060 .buf = data, .len = len} };
1061
1062 if (i2c_transfer(adapter, msgs, 2) != 2) {
44cdd064 1063 dprintk(KERN_ERR DEVICE_NAME ": Error reading EEPROM\n");
dae52d00
MB		 1064 return -EIO;
1065 }
1066 return 0;
1067}
1068
dae52d00
MB		 1069
1070static int i2c_dump_eeprom(struct i2c_adapter *adapter, u8 adr)
1071{
1072 u8 buf[64];
1073 int i;
1074
1075 if (i2c_read_eeprom(adapter, adr, 0x0000, buf, sizeof(buf))) {
1076 printk(KERN_ERR DEVICE_NAME ": No EEPROM?\n");
1077 return -1;
1078 }
1079 for (i = 0; i < sizeof(buf); i++) {
1080 if (!(i & 15))
1081 printk("\n");
1082 printk("%02x ", buf[i]);
1083 }
1084 printk("\n");
1085
1086 return 0;
1087}
1088
1089static int i2c_copy_eeprom(struct i2c_adapter *adapter, u8 adr, u8 adr2)
1090{
1091 u8 buf[64];
1092 int i;
1093
1094 if (i2c_read_eeprom(adapter, adr, 0x0000, buf, sizeof(buf))) {
1095 printk(KERN_ERR DEVICE_NAME ": No EEPROM?\n");
1096 return -1;
1097 }
1098 buf[36] = 0xc3;
1099 buf[39] = 0xab;
1100 for (i = 0; i < sizeof(buf); i++) {
1101 i2c_write_eeprom(adapter, adr2, i, buf[i]);
1102 msleep(10);
1103 }
1104 return 0;
1105}
1106
1107
1108/****************************************************************************/
1109/* COMMAND API interface ****************************************************/
1110/****************************************************************************/
1111
1112#ifdef NGENE_COMMAND_API
1113
1114static int command_do_ioctl(struct inode *inode, struct file *file,
1115 unsigned int cmd, void *parg)
1116{
1117 struct dvb_device *dvbdev = file->private_data;
1118 struct ngene_channel *chan = dvbdev->priv;
1119 struct ngene *dev = chan->dev;
1120 int err = 0;
1121
1122 switch (cmd) {
1123 case IOCTL_MIC_NO_OP:
1124 err = ngene_command_nop(dev);
1125 break;
1126
1127 case IOCTL_MIC_DOWNLOAD_FIRMWARE:
1128 break;
1129
1130 case IOCTL_MIC_I2C_READ:
1131 {
1132 MIC_I2C_READ *msg = parg;
1133
1134 err = ngene_command_i2c_read(dev, msg->I2CAddress >> 1,
1135 msg->OutData, msg->OutLength,
1136 msg->OutData, msg->InLength, 1);
1137 break;
1138 }
1139
1140 case IOCTL_MIC_I2C_WRITE:
1141 {
1142 MIC_I2C_WRITE *msg = parg;
1143
1144 err = ngene_command_i2c_write(dev, msg->I2CAddress >> 1,
1145 msg->Data, msg->Length);
1146 break;
1147 }
1148
1149 case IOCTL_MIC_TEST_GETMEM:
1150 {
1151 MIC_MEM *m = parg;
1152
1153 if (m->Length > 64 * 1024 || m->Start + m->Length > 64 * 1024)
1154 return -EINVAL;
1155
1156 /* WARNING, only use this on x86,
1157 other archs may not swallow this */
1158 err = copy_to_user(m->Data, dev->iomem + m->Start, m->Length);
1159 break;
1160 }
1161
1162 case IOCTL_MIC_TEST_SETMEM:
1163 {
1164 MIC_MEM *m = parg;
1165
1166 if (m->Length > 64 * 1024 || m->Start + m->Length > 64 * 1024)
1167 return -EINVAL;
1168
1169 err = copy_from_user(dev->iomem + m->Start, m->Data, m->Length);
1170 break;
1171 }
1172
1173 case IOCTL_MIC_SFR_READ:
1174 {
1175 MIC_IMEM *m = parg;
1176
1177 err = ngene_command_imem_read(dev, m->Address, &m->Data, 1);
1178 break;
1179 }
1180
1181 case IOCTL_MIC_SFR_WRITE:
1182 {
1183 MIC_IMEM *m = parg;
1184
1185 err = ngene_command_imem_write(dev, m->Address, m->Data, 1);
1186 break;
1187 }
1188
1189 case IOCTL_MIC_IRAM_READ:
1190 {
1191 MIC_IMEM *m = parg;
1192
1193 err = ngene_command_imem_read(dev, m->Address, &m->Data, 0);
1194 break;
1195 }
1196
1197 case IOCTL_MIC_IRAM_WRITE:
1198 {
1199 MIC_IMEM *m = parg;
1200
1201 err = ngene_command_imem_write(dev, m->Address, m->Data, 0);
1202 break;
1203 }
1204
1205 case IOCTL_MIC_STREAM_CONTROL:
1206 {
1207 MIC_STREAM_CONTROL *m = parg;
1208
1209 err = ngene_stream_control(dev, m->Stream, m->Control, m->Mode,
1210 m->nLines, m->nBytesPerLine,
1211 m->nVBILines, m->nBytesPerVBILine);
1212 break;
1213 }
1214
1215 default:
1216 err = -EINVAL;
1217 break;
1218 }
1219 return err;
1220}
1221
1222static int command_ioctl(struct inode *inode, struct file *file,
1223 unsigned int cmd, unsigned long arg)
1224{
1225 void *parg = (void *)arg, *pbuf = NULL;
1226 char buf[64];
1227 int res = -EFAULT;
1228
1229 if (_IOC_DIR(cmd) & _IOC_WRITE) {
1230 parg = buf;
1231 if (_IOC_SIZE(cmd) > sizeof(buf)) {
1232 pbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL);
1233 if (!pbuf)
1234 return -ENOMEM;
1235 parg = pbuf;
1236 }
1237 if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd)))
1238 goto error;
1239 }
1240 res = command_do_ioctl(inode, file, cmd, parg);
1241 if (res < 0)
1242 goto error;
1243 if (_IOC_DIR(cmd) & _IOC_READ)
1244 if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd)))
1245 res = -EFAULT;
1246error:
1247 kfree(pbuf);
1248 return res;
1249}
1250
1251struct page *ngene_nopage(struct vm_area_struct *vma,
1252 unsigned long address, int *type)
1253{
1254 return 0;
1255}
1256
1257static int ngene_mmap(struct file *file, struct vm_area_struct *vma)
1258{
1259 struct dvb_device *dvbdev = file->private_data;
1260 struct ngene_channel *chan = dvbdev->priv;
1261 struct ngene *dev = chan->dev;
1262
1263 unsigned long size = vma->vm_end - vma->vm_start;
1264 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
1265 unsigned long padr = pci_resource_start(dev->pci_dev, 0) + off;
1266 unsigned long psize = pci_resource_len(dev->pci_dev, 0) - off;
1267
1268 if (size > psize)
1269 return -EINVAL;
1270
1271 if (io_remap_pfn_range(vma, vma->vm_start, padr >> PAGE_SHIFT, size,
1272 vma->vm_page_prot))
1273 return -EAGAIN;
1274 return 0;
1275}
1276
1277static int write_uart(struct ngene *dev, u8 *data, int len)
1278{
1279 struct ngene_command com;
1280
1281 com.cmd.hdr.Opcode = CMD_WRITE_UART;
1282 com.cmd.hdr.Length = len;
1283 memcpy(com.cmd.WriteUart.Data, data, len);
1284 com.cmd.WriteUart.Data[len] = 0;
1285 com.cmd.WriteUart.Data[len + 1] = 0;
1286 com.in_len = len;
1287 com.out_len = 0;
1288
1289 if (ngene_command(dev, &com) < 0)
1290 return -EIO;
1291
1292 return 0;
1293}
1294
1295static int send_cli(struct ngene *dev, char *cmd)
1296{
1297 /* printk(KERN_INFO DEVICE_NAME ": %s", cmd); */
1298 return write_uart(dev, cmd, strlen(cmd));
1299}
1300
1301static int send_cli_val(struct ngene *dev, char *cmd, u32 val)
1302{
1303 char s[32];
1304
1305 snprintf(s, 32, "%s %d\n", cmd, val);
1306 /* printk(KERN_INFO DEVICE_NAME ": %s", s); */
1307 return write_uart(dev, s, strlen(s));
1308}
1309
1310static int ngene_command_write_uart_user(struct ngene *dev,
1311 const u8 *data, int len)
1312{
1313 struct ngene_command com;
1314
1315 dev->tx_busy = 1;
1316 com.cmd.hdr.Opcode = CMD_WRITE_UART;
1317 com.cmd.hdr.Length = len;
1318
1319 if (copy_from_user(com.cmd.WriteUart.Data, data, len))
1320 return -EFAULT;
1321 com.in_len = len;
1322 com.out_len = 0;
1323
1324 if (ngene_command(dev, &com) < 0)
1325 return -EIO;
1326
1327 return 0;
1328}
1329
1330static ssize_t uart_write(struct file *file, const char *buf,
1331 size_t count, loff_t *ppos)
1332{
1333 struct dvb_device *dvbdev = file->private_data;
1334 struct ngene_channel *chan = dvbdev->priv;
1335 struct ngene *dev = chan->dev;
1336 int len, ret = 0;
1337 size_t left = count;
1338
1339 while (left) {
1340 len = left;
1341 if (len > 250)
1342 len = 250;
1343 ret = wait_event_interruptible(dev->tx_wq, dev->tx_busy == 0);
1344 if (ret < 0)
1345 return ret;
1346 ngene_command_write_uart_user(dev, buf, len);
1347 left -= len;
1348 buf += len;
1349 }
1350 return count;
1351}
1352
1353static ssize_t ts_write(struct file *file, const char *buf,
1354 size_t count, loff_t *ppos)
1355{
1356 struct dvb_device *dvbdev = file->private_data;
1357 struct ngene_channel *chan = dvbdev->priv;
1358 struct ngene *dev = chan->dev;
1359
1360 if (wait_event_interruptible(dev->tsout_rbuf.queue,
1361 dvb_ringbuffer_free
1362 (&dev->tsout_rbuf) >= count) < 0)
1363 return 0;
1364
1365 dvb_ringbuffer_write(&dev->tsout_rbuf, buf, count);
1366
1367 return count;
1368}
1369
1370static ssize_t uart_read(struct file *file, char *buf,
1371 size_t count, loff_t *ppos)
1372{
1373 struct dvb_device *dvbdev = file->private_data;
1374 struct ngene_channel *chan = dvbdev->priv;
1375 struct ngene *dev = chan->dev;
1376 int left;
1377 int wp, rp, avail, len;
1378
1379 if (!dev->uart_rbuf)
1380 return -EINVAL;
1381 if (count > 128)
1382 count = 128;
1383 left = count;
1384 while (left) {
1385 if (wait_event_interruptible(dev->rx_wq,
1386 dev->uart_wp != dev->uart_rp) < 0)
1387 return -EAGAIN;
1388 wp = dev->uart_wp;
1389 rp = dev->uart_rp;
1390 avail = (wp - rp);
1391
1392 if (avail < 0)
1393 avail += UART_RBUF_LEN;
1394 if (avail > left)
1395 avail = left;
1396 if (wp < rp) {
1397 len = UART_RBUF_LEN - rp;
1398 if (len > avail)
1399 len = avail;
1400 if (copy_to_user(buf, dev->uart_rbuf + rp, len))
1401 return -EFAULT;
1402 if (len < avail)
1403 if (copy_to_user(buf + len, dev->uart_rbuf,
1404 avail - len))
1405 return -EFAULT;
1406 } else {
1407 if (copy_to_user(buf, dev->uart_rbuf + rp, avail))
1408 return -EFAULT;
1409 }
1410 dev->uart_rp = (rp + avail) % UART_RBUF_LEN;
1411 left -= avail;
1412 buf += avail;
1413 }
1414 return count;
1415}
1416
1417static const struct file_operations command_fops = {
1418 .owner = THIS_MODULE,
1419 .read = uart_read,
1420 .write = ts_write,
1421 .ioctl = command_ioctl,
1422 .open = dvb_generic_open,
1423 .release = dvb_generic_release,
1424 .poll = 0,
1425 .mmap = ngene_mmap,
1426};
1427
1428static struct dvb_device dvbdev_command = {
1429 .priv = 0,
1430 .readers = -1,
1431 .writers = -1,
1432 .users = -1,
1433 .fops = &command_fops,
1434};
1435
1436#endif
1437
1438/****************************************************************************/
1439/* DVB functions and API interface ******************************************/
1440/****************************************************************************/
1441
1442static void swap_buffer(u32 *p, u32 len)
1443{
1444 while (len) {
1445 *p = swab32(*p);
1446 p++;
1447 len -= 4;
1448 }
1449}
1450
dae52d00
MB		 1451
1452static void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
1453{
1454 struct ngene_channel *chan = priv;
1455
1456
1457 dvb_dmx_swfilter(&chan->demux, buf, len);
1458 return 0;
1459}
1460
1461u8 fill_ts[188] = { 0x47, 0x1f, 0xff, 0x10 };
1462
1463static void *tsout_exchange(void *priv, void *buf, u32 len,
1464 u32 clock, u32 flags)
1465{
1466 struct ngene_channel *chan = priv;
1467 struct ngene *dev = chan->dev;
1468 u32 alen;
1469
1470 alen = dvb_ringbuffer_avail(&dev->tsout_rbuf);
1471 alen -= alen % 188;
1472
1473 if (alen < len)
1474 FillTSBuffer(buf + alen, len - alen, flags);
1475 else
1476 alen = len;
1477 dvb_ringbuffer_read(&dev->tsout_rbuf, buf, alen);
1478 if (flags & DF_SWAP32)
1479 swap_buffer((u32 *)buf, alen);
1480 wake_up_interruptible(&dev->tsout_rbuf.queue);
1481 return buf;
1482}
1483
dae52d00
MB		 1484
1485static void set_transfer(struct ngene_channel *chan, int state)
1486{
1487 u8 control = 0, mode = 0, flags = 0;
1488 struct ngene *dev = chan->dev;
1489 int ret;
1490
1491 /*
1492 if (chan->running)
1493 return;
1494 */
1495
1496 /*
1497 printk(KERN_INFO DEVICE_NAME ": st %d\n", state);
1498 msleep(100);
1499 */
1500
1501 if (state) {
1502 if (chan->running) {
1503 printk(KERN_INFO DEVICE_NAME ": already running\n");
1504 return;
1505 }
1506 } else {
1507 if (!chan->running) {
1508 printk(KERN_INFO DEVICE_NAME ": already stopped\n");
1509 return;
1510 }
1511 }
1512
1513 if (dev->card_info->switch_ctrl)
1514 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
1515
1516 if (state) {
1517 spin_lock_irq(&chan->state_lock);
1518
1519 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
1520 ngreadl(0x9310)); */
1521 my_dvb_ringbuffer_flush(&dev->tsout_rbuf);
1522 control = 0x80;
1523 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1524 chan->Capture1Length = 512 * 188;
1525 mode = SMODE_TRANSPORT_STREAM;
1526 }
1527 if (chan->mode & NGENE_IO_TSOUT) {
1528 chan->pBufferExchange = tsout_exchange;
1529 /* 0x66666666 = 50MHz *2^33 /250MHz */
1530 chan->AudioDTOValue = 0x66666666;
1531 /* set_dto(chan, 38810700+1000); */
1532 /* set_dto(chan, 19392658); */
1533 }
1534 if (chan->mode & NGENE_IO_TSIN)
1535 chan->pBufferExchange = tsin_exchange;
1536 /* ngwritel(0, 0x9310); */
1537 spin_unlock_irq(&chan->state_lock);
1538 } else
1539 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
1540 ngreadl(0x9310)); */
1541
1542 ret = ngene_command_stream_control(dev, chan->number,
1543 control, mode, flags);
1544 if (!ret)
1545 chan->running = state;
1546 else
1547 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n",
1548 state);
1549 if (!state) {
1550 spin_lock_irq(&chan->state_lock);
1551 chan->pBufferExchange = 0;
1552 my_dvb_ringbuffer_flush(&dev->tsout_rbuf);
1553 spin_unlock_irq(&chan->state_lock);
1554 }
1555}
1556
1557static int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed)
1558{
1559 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
1560 struct ngene_channel *chan = dvbdmx->priv;
83f3c715 1561#ifdef NGENE_COMMAND_API
dae52d00
MB		 1562 struct ngene *dev = chan->dev;
1563
1564 if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) {
1565 switch (dvbdmxfeed->pes_type) {
1566 case DMX_TS_PES_VIDEO:
1567 send_cli_val(dev, "vpid", dvbdmxfeed->pid);
1568 send_cli(dev, "res 1080i50\n");
1569 /* send_cli(dev, "vdec mpeg2\n"); */
1570 break;
1571
1572 case DMX_TS_PES_AUDIO:
1573 send_cli_val(dev, "apid", dvbdmxfeed->pid);
1574 send_cli(dev, "start\n");
1575 break;
1576
1577 case DMX_TS_PES_PCR:
1578 send_cli_val(dev, "pcrpid", dvbdmxfeed->pid);
1579 break;
1580
1581 default:
1582 break;
1583 }
1584
1585 }
83f3c715 1586#endif
dae52d00
MB		 1587
1588 if (chan->users == 0) {
1589 set_transfer(chan, 1);
1590 /* msleep(10); */
1591 }
1592
1593 return ++chan->users;
1594}
1595
1596static int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
1597{
1598 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
1599 struct ngene_channel *chan = dvbdmx->priv;
83f3c715 1600#ifdef NGENE_COMMAND_API
dae52d00
MB		 1601 struct ngene *dev = chan->dev;
1602
1603 if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) {
1604 switch (dvbdmxfeed->pes_type) {
1605 case DMX_TS_PES_VIDEO:
1606 send_cli(dev, "stop\n");
1607 break;
1608
1609 case DMX_TS_PES_AUDIO:
1610 break;
1611
1612 case DMX_TS_PES_PCR:
1613 break;
1614
1615 default:
1616 break;
1617 }
1618
1619 }
83f3c715 1620#endif
dae52d00
MB		 1621
1622 if (--chan->users)
1623 return chan->users;
1624
1625 set_transfer(chan, 0);
1626
1627 return 0;
1628}
1629
dae52d00 1630
dae52d00
MB		 1631
1632static int write_to_decoder(struct dvb_demux_feed *feed,
1633 const u8 *buf, size_t len)
1634{
1635 struct dvb_demux *dvbdmx = feed->demux;
1636 struct ngene_channel *chan = dvbdmx->priv;
1637 struct ngene *dev = chan->dev;
1638
1639 if (wait_event_interruptible(dev->tsout_rbuf.queue,
1640 dvb_ringbuffer_free
1641 (&dev->tsout_rbuf) >= len) < 0)
1642 return 0;
1643
1644 dvb_ringbuffer_write(&dev->tsout_rbuf, buf, len);
1645
1646 return len;
1647}
1648
1649static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
1650 int (*start_feed)(struct dvb_demux_feed *),
1651 int (*stop_feed)(struct dvb_demux_feed *),
1652 void *priv)
1653{
1654 dvbdemux->priv = priv;
1655
1656 dvbdemux->filternum = 256;
1657 dvbdemux->feednum = 256;
1658 dvbdemux->start_feed = start_feed;
1659 dvbdemux->stop_feed = stop_feed;
1660 dvbdemux->write_to_decoder = 0;
1661 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
1662 DMX_SECTION_FILTERING |
1663 DMX_MEMORY_BASED_FILTERING);
1664 return dvb_dmx_init(dvbdemux);
1665}
1666
1667static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
1668 struct dvb_demux *dvbdemux,
1669 struct dmx_frontend *hw_frontend,
1670 struct dmx_frontend *mem_frontend,
1671 struct dvb_adapter *dvb_adapter)
1672{
1673 int ret;
1674
1675 dmxdev->filternum = 256;
1676 dmxdev->demux = &dvbdemux->dmx;
1677 dmxdev->capabilities = 0;
1678 ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
1679 if (ret < 0)
1680 return ret;
1681
1682 hw_frontend->source = DMX_FRONTEND_0;
1683 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
1684 mem_frontend->source = DMX_MEMORY_FE;
1685 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
1686 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
1687}
1688
1689/****************************************************************************/
1690/* Decypher firmware loading ************************************************/
1691/****************************************************************************/
1692
1693#define DECYPHER_FW "decypher.fw"
1694
1695static int dec_ts_send(struct ngene *dev, u8 *buf, u32 len)
1696{
1697 while (dvb_ringbuffer_free(&dev->tsout_rbuf) < len)
1698 msleep(1);
1699
1700
1701 dvb_ringbuffer_write(&dev->tsout_rbuf, buf, len);
1702
1703 return len;
1704}
1705
1706u8 dec_fw_fill_ts[188] = { 0x47, 0x09, 0x0e, 0x10, 0xff, 0xff, 0x00, 0x00 };
1707
1708int dec_fw_send(struct ngene *dev, u8 *fw, u32 size)
1709{
1710 struct ngene_channel *chan = &dev->channel[4];
1711 u32 len = 180, cc = 0;
1712 u8 buf[8] = { 0x47, 0x09, 0x0e, 0x10, 0x00, 0x00, 0x00, 0x00 };
1713
1714 set_transfer(chan, 1);
1715 msleep(100);
1716 while (size) {
1717 len = 180;
1718 if (len > size)
1719 len = size;
1720 buf[3] = 0x10 | (cc & 0x0f);
1721 buf[4] = (cc >> 8);
1722 buf[5] = cc & 0xff;
1723 buf[6] = len;
1724
1725 dec_ts_send(dev, buf, 8);
1726 dec_ts_send(dev, fw, len);
1727 if (len < 180)
1728 dec_ts_send(dev, dec_fw_fill_ts + len + 8, 180 - len);
1729 cc++;
1730 size -= len;
1731 fw += len;
1732 }
1733 for (len = 0; len < 512; len++)
1734 dec_ts_send(dev, dec_fw_fill_ts, 188);
1735 while (dvb_ringbuffer_avail(&dev->tsout_rbuf))
1736 msleep(10);
1737 msleep(100);
1738 set_transfer(chan, 0);
1739 return 0;
1740}
1741
1742int dec_fw_boot(struct ngene *dev)
1743{
1744 u32 size;
1745 const struct firmware *fw = NULL;
1746 u8 *dec_fw;
dae52d00
MB		 1747
1748 if (request_firmware(&fw, DECYPHER_FW, &dev->pci_dev->dev) < 0) {
1749 printk(KERN_ERR DEVICE_NAME
1750 ": %s not found. Check hotplug directory.\n",
1751 DECYPHER_FW);
1752 return -1;
1753 }
1754 printk(KERN_INFO DEVICE_NAME ": Booting decypher firmware file %s\n",
1755 DECYPHER_FW);
1756
1757 size = fw->size;
83f3c715 1758 dec_fw = (u8 *)fw->data;
dae52d00
MB		 1759 dec_fw_send(dev, dec_fw, size);
1760 release_firmware(fw);
1761 return 0;
1762}
1763
1764/****************************************************************************/
1765/* nGene hardware init and release functions ********************************/
1766/****************************************************************************/
1767
1768void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
1769{
1770 struct SBufferHeader *Cur = rb->Head;
1771 u32 j;
1772
1773 if (!Cur)
1774 return;
1775
1776 for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
1777 if (Cur->Buffer1)
1778 pci_free_consistent(dev->pci_dev,
1779 rb->Buffer1Length,
1780 Cur->Buffer1,
1781 Cur->scList1->Address);
1782
1783 if (Cur->Buffer2)
1784 pci_free_consistent(dev->pci_dev,
1785 rb->Buffer2Length,
1786 Cur->Buffer2,
1787 Cur->scList2->Address);
1788 }
1789
1790 if (rb->SCListMem)
1791 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
1792 rb->SCListMem, rb->PASCListMem);
1793
1794 pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
1795}
1796
1797void free_idlebuffer(struct ngene *dev,
1798 struct SRingBufferDescriptor *rb,
1799 struct SRingBufferDescriptor *tb)
1800{
1801 int j;
1802 struct SBufferHeader *Cur = tb->Head;
1803
1804 if (!rb->Head)
1805 return;
1806 free_ringbuffer(dev, rb);
1807 for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
1808 Cur->Buffer2 = 0;
1809 Cur->scList2 = 0;
1810 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
1811 Cur->ngeneBuffer.Number_of_entries_2 = 0;
1812 }
1813}
1814
1815void free_common_buffers(struct ngene *dev)
1816{
1817 u32 i;
1818 struct ngene_channel *chan;
1819
1820 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1821 chan = &dev->channel[i];
1822 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
1823 free_ringbuffer(dev, &chan->RingBuffer);
1824 free_ringbuffer(dev, &chan->TSRingBuffer);
1825 }
1826
1827 if (dev->OverflowBuffer)
1828 pci_free_consistent(dev->pci_dev,
1829 OVERFLOW_BUFFER_SIZE,
1830 dev->OverflowBuffer, dev->PAOverflowBuffer);
1831
1832 if (dev->FWInterfaceBuffer)
1833 pci_free_consistent(dev->pci_dev,
1834 4096,
1835 dev->FWInterfaceBuffer,
1836 dev->PAFWInterfaceBuffer);
1837}
1838
1839/****************************************************************************/
1840/* Ring buffer handling *****************************************************/
1841/****************************************************************************/
1842
1843int create_ring_buffer(struct pci_dev *pci_dev,
1844 struct SRingBufferDescriptor *descr, u32 NumBuffers)
1845{
1846 dma_addr_t tmp;
1847 struct SBufferHeader *Head;
1848 u32 i;
1849 u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
1850 u64 PARingBufferHead;
1851 u64 PARingBufferCur;
1852 u64 PARingBufferNext;
1853 struct SBufferHeader *Cur, *Next;
1854
1855 descr->Head = 0;
1856 descr->MemSize = 0;
1857 descr->PAHead = 0;
1858 descr->NumBuffers = 0;
1859
1860 if (MemSize < 4096)
1861 MemSize = 4096;
1862
1863 Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
1864 PARingBufferHead = tmp;
1865
1866 if (!Head)
1867 return -ENOMEM;
1868
1869 memset(Head, 0, MemSize);
1870
1871 PARingBufferCur = PARingBufferHead;
1872 Cur = Head;
1873
1874 for (i = 0; i < NumBuffers - 1; i++) {
1875 Next = (struct SBufferHeader *)
1876 (((u8 *) Cur) + SIZEOF_SBufferHeader);
1877 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
1878 Cur->Next = Next;
1879 Cur->ngeneBuffer.Next = PARingBufferNext;
1880 Cur = Next;
1881 PARingBufferCur = PARingBufferNext;
1882 }
1883 /* Last Buffer points back to first one */
1884 Cur->Next = Head;
1885 Cur->ngeneBuffer.Next = PARingBufferHead;
1886
1887 descr->Head = Head;
1888 descr->MemSize = MemSize;
1889 descr->PAHead = PARingBufferHead;
1890 descr->NumBuffers = NumBuffers;
1891
1892 return 0;
1893}
1894
1895static int AllocateRingBuffers(struct pci_dev *pci_dev,
1896 dma_addr_t of,
1897 struct SRingBufferDescriptor *pRingBuffer,
1898 u32 Buffer1Length, u32 Buffer2Length)
1899{
1900 dma_addr_t tmp;
1901 u32 i, j;
1902 int status = 0;
1903 u32 SCListMemSize = pRingBuffer->NumBuffers
1904 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
1905 NUM_SCATTER_GATHER_ENTRIES)
1906 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1907
1908 u64 PASCListMem;
1909 PHW_SCATTER_GATHER_ELEMENT SCListEntry;
1910 u64 PASCListEntry;
1911 struct SBufferHeader *Cur;
1912 void *SCListMem;
1913
1914 if (SCListMemSize < 4096)
1915 SCListMemSize = 4096;
1916
1917 SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
1918
1919 PASCListMem = tmp;
1920 if (SCListMem == NULL)
1921 return -ENOMEM;
1922
1923 memset(SCListMem, 0, SCListMemSize);
1924
1925 pRingBuffer->SCListMem = SCListMem;
1926 pRingBuffer->PASCListMem = PASCListMem;
1927 pRingBuffer->SCListMemSize = SCListMemSize;
1928 pRingBuffer->Buffer1Length = Buffer1Length;
1929 pRingBuffer->Buffer2Length = Buffer2Length;
1930
1931 SCListEntry = (PHW_SCATTER_GATHER_ELEMENT) SCListMem;
1932 PASCListEntry = PASCListMem;
1933 Cur = pRingBuffer->Head;
1934
1935 for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
1936 u64 PABuffer;
1937
1938 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
1939 &tmp);
1940 PABuffer = tmp;
1941
1942 if (Buffer == NULL)
1943 return -ENOMEM;
1944
1945 Cur->Buffer1 = Buffer;
1946
1947 SCListEntry->Address = PABuffer;
1948 SCListEntry->Length = Buffer1Length;
1949
1950 Cur->scList1 = SCListEntry;
1951 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
1952 Cur->ngeneBuffer.Number_of_entries_1 =
1953 NUM_SCATTER_GATHER_ENTRIES;
1954
1955 SCListEntry += 1;
1956 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1957
1958#if NUM_SCATTER_GATHER_ENTRIES > 1
1959 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
1960 SCListEntry->Address = of;
1961 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1962 SCListEntry += 1;
1963 PASCListEntry +=
1964 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1965 }
1966#endif
1967
1968 if (!Buffer2Length)
1969 continue;
1970
1971 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
1972 PABuffer = tmp;
1973
1974 if (Buffer == NULL)
1975 return -ENOMEM;
1976
1977 Cur->Buffer2 = Buffer;
1978
1979 SCListEntry->Address = PABuffer;
1980 SCListEntry->Length = Buffer2Length;
1981
1982 Cur->scList2 = SCListEntry;
1983 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
1984 Cur->ngeneBuffer.Number_of_entries_2 =
1985 NUM_SCATTER_GATHER_ENTRIES;
1986
1987 SCListEntry += 1;
1988 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1989
1990#if NUM_SCATTER_GATHER_ENTRIES > 1
1991 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
1992 SCListEntry->Address = of;
1993 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1994 SCListEntry += 1;
1995 PASCListEntry +=
1996 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1997 }
1998#endif
1999
2000 }
2001
2002 return status;
2003}
2004
2005static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
2006 struct SRingBufferDescriptor *pRingBuffer)
2007{
2008 int status = 0;
2009
2010 /* Copy pointer to scatter gather list in TSRingbuffer
2011 structure for buffer 2
2012 Load number of buffer
2013 */
2014 u32 n = pRingBuffer->NumBuffers;
2015
2016 /* Point to first buffer entry */
2017 struct SBufferHeader *Cur = pRingBuffer->Head;
2018 int i;
2019 /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
2020 for (i = 0; i < n; i++) {
2021 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
2022 Cur->scList2 = pIdleBuffer->Head->scList1;
2023 Cur->ngeneBuffer.Address_of_first_entry_2 =
2024 pIdleBuffer->Head->ngeneBuffer.
2025 Address_of_first_entry_1;
2026 Cur->ngeneBuffer.Number_of_entries_2 =
2027 pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
2028 Cur = Cur->Next;
2029 }
2030 return status;
2031}
2032
2033static u32 RingBufferSizes[MAX_STREAM] = {
2034 RING_SIZE_VIDEO,
2035 RING_SIZE_VIDEO,
2036 RING_SIZE_AUDIO,
2037 RING_SIZE_AUDIO,
2038 RING_SIZE_AUDIO,
2039};
2040
2041static u32 Buffer1Sizes[MAX_STREAM] = {
2042 MAX_VIDEO_BUFFER_SIZE,
2043 MAX_VIDEO_BUFFER_SIZE,
2044 MAX_AUDIO_BUFFER_SIZE,
2045 MAX_AUDIO_BUFFER_SIZE,
2046 MAX_AUDIO_BUFFER_SIZE
2047};
2048
2049static u32 Buffer2Sizes[MAX_STREAM] = {
2050 MAX_VBI_BUFFER_SIZE,
2051 MAX_VBI_BUFFER_SIZE,
2052 0,
2053 0,
2054 0
2055};
2056
dae52d00
MB		 2057
2058static int AllocCommonBuffers(struct ngene *dev)
2059{
2060 int status = 0, i;
2061
2062 dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
2063 &dev->PAFWInterfaceBuffer);
2064 if (!dev->FWInterfaceBuffer)
2065 return -ENOMEM;
2066 dev->hosttongene = dev->FWInterfaceBuffer;
2067 dev->ngenetohost = dev->FWInterfaceBuffer + 256;
2068 dev->EventBuffer = dev->FWInterfaceBuffer + 512;
2069
2070 dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev,
2071 OVERFLOW_BUFFER_SIZE,
2072 &dev->PAOverflowBuffer);
2073 if (!dev->OverflowBuffer)
2074 return -ENOMEM;
2075 memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE);
2076
2077 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
2078 int type = dev->card_info->io_type[i];
2079
2080 dev->channel[i].State = KSSTATE_STOP;
2081
2082 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
2083 status = create_ring_buffer(dev->pci_dev,
2084 &dev->channel[i].RingBuffer,
2085 RingBufferSizes[i]);
2086 if (status < 0)
2087 break;
2088
2089 if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
2090 status = AllocateRingBuffers(dev->pci_dev,
2091 dev->
2092 PAOverflowBuffer,
2093 &dev->channel[i].
2094 RingBuffer,
2095 Buffer1Sizes[i],
2096 Buffer2Sizes[i]);
2097 if (status < 0)
2098 break;
2099 } else if (type & NGENE_IO_HDTV) {
2100 status = AllocateRingBuffers(dev->pci_dev,
2101 dev->
2102 PAOverflowBuffer,
2103 &dev->channel[i].
2104 RingBuffer,
2105 MAX_HDTV_BUFFER_SIZE,
2106 0);
2107 if (status < 0)
2108 break;
2109 }
2110 }
2111
2112 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
2113
2114 status = create_ring_buffer(dev->pci_dev,
2115 &dev->channel[i].
2116 TSRingBuffer, RING_SIZE_TS);
2117 if (status < 0)
2118 break;
2119
2120 status = AllocateRingBuffers(dev->pci_dev,
2121 dev->PAOverflowBuffer,
2122 &dev->channel[i].
2123 TSRingBuffer,
2124 MAX_TS_BUFFER_SIZE, 0);
2125 if (status)
2126 break;
2127 }
2128
2129 if (type & NGENE_IO_TSOUT) {
2130 status = create_ring_buffer(dev->pci_dev,
2131 &dev->channel[i].
2132 TSIdleBuffer, 1);
2133 if (status < 0)
2134 break;
2135 status = AllocateRingBuffers(dev->pci_dev,
2136 dev->PAOverflowBuffer,
2137 &dev->channel[i].
2138 TSIdleBuffer,
2139 MAX_TS_BUFFER_SIZE, 0);
2140 if (status)
2141 break;
2142 FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
2143 &dev->channel[i].TSRingBuffer);
2144 }
2145 }
2146 return status;
2147}
2148
2149static void ngene_release_buffers(struct ngene *dev)
2150{
2151 if (dev->iomem)
2152 iounmap(dev->iomem);
2153 free_common_buffers(dev);
2154 vfree(dev->tsout_buf);
2155 vfree(dev->ain_buf);
2156 vfree(dev->vin_buf);
2157 vfree(dev);
2158}
2159
2160static int ngene_get_buffers(struct ngene *dev)
2161{
2162 if (AllocCommonBuffers(dev))
2163 return -ENOMEM;
2164 if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
2165 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
2166 if (!dev->tsout_buf)
2167 return -ENOMEM;
2168 dvb_ringbuffer_init(&dev->tsout_rbuf,
2169 dev->tsout_buf, TSOUT_BUF_SIZE);
2170 }
2171 if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
2172 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
2173 if (!dev->ain_buf)
2174 return -ENOMEM;
2175 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
2176 }
2177 if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
2178 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
2179 if (!dev->vin_buf)
2180 return -ENOMEM;
2181 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
2182 }
2183 dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
2184 pci_resource_len(dev->pci_dev, 0));
2185 if (!dev->iomem)
2186 return -ENOMEM;
2187
2188 return 0;
2189}
2190
2191static void ngene_init(struct ngene *dev)
2192{
2193 int i;
2194
2195 tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
2196
2197 memset_io(dev->iomem + 0xc000, 0x00, 0x220);
2198 memset_io(dev->iomem + 0xc400, 0x00, 0x100);
2199
2200 for (i = 0; i < MAX_STREAM; i++) {
2201 dev->channel[i].dev = dev;
2202 dev->channel[i].number = i;
2203 }
2204
2205 dev->fw_interface_version = 0;
2206
2207 ngwritel(0, NGENE_INT_ENABLE);
2208
2209 dev->icounts = ngreadl(NGENE_INT_COUNTS);
2210
2211 dev->device_version = ngreadl(DEV_VER) & 0x0f;
2212 printk(KERN_INFO DEVICE_NAME ": Device version %d\n",
2213 dev->device_version);
2214}
2215
2216static int ngene_load_firm(struct ngene *dev)
2217{
2218 u32 size;
2219 const struct firmware *fw = NULL;
2220 u8 *ngene_fw;
2221 char *fw_name;
2222 int err, version;
2223
2224 version = dev->card_info->fw_version;
2225
2226 switch (version) {
2227 default:
2228 case 15:
2229 version = 15;
0027ebb7 2230 size = 23466;
dae52d00
MB		 2231 fw_name = "ngene_15.fw";
2232 break;
2233 case 16:
0027ebb7 2234 size = 23498;
dae52d00
MB		 2235 fw_name = "ngene_16.fw";
2236 break;
2237 case 17:
0027ebb7 2238 size = 24446;
dae52d00
MB		 2239 fw_name = "ngene_17.fw";
2240 break;
2241 }
dae52d00 2242
dae52d00
MB		 2243 if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
2244 printk(KERN_ERR DEVICE_NAME
0027ebb7 2245 ": Could not load firmware file %s.\n", fw_name);
dae52d00
MB		 2246 printk(KERN_INFO DEVICE_NAME
2247 ": Copy %s to your hotplug directory!\n", fw_name);
2248 return -1;
2249 }
0027ebb7
OE		 2250 if (size != fw->size) {
2251 printk(KERN_ERR DEVICE_NAME
2252 ": Firmware %s has invalid size!", fw_name);
2253 err = -1;
2254 } else {
2255 printk(KERN_INFO DEVICE_NAME
2256 ": Loading firmware file %s.\n", fw_name);
2257 ngene_fw = (u8 *) fw->data;
2258 err = ngene_command_load_firmware(dev, ngene_fw, size);
2259 }
2260
dae52d00 2261 release_firmware(fw);
0027ebb7 2262
dae52d00
MB		 2263 return err;
2264}
2265
2266static void ngene_stop(struct ngene *dev)
2267{
2268 down(&dev->cmd_mutex);
2269 i2c_del_adapter(&(dev->channel[0].i2c_adapter));
2270 i2c_del_adapter(&(dev->channel[1].i2c_adapter));
2271 ngwritel(0, NGENE_INT_ENABLE);
2272 ngwritel(0, NGENE_COMMAND);
2273 ngwritel(0, NGENE_COMMAND_HI);
2274 ngwritel(0, NGENE_STATUS);
2275 ngwritel(0, NGENE_STATUS_HI);
2276 ngwritel(0, NGENE_EVENT);
2277 ngwritel(0, NGENE_EVENT_HI);
2278 free_irq(dev->pci_dev->irq, dev);
2279}
2280
2281static int ngene_start(struct ngene *dev)
2282{
2283 int stat;
2284 int i;
2285
2286 pci_set_master(dev->pci_dev);
2287 ngene_init(dev);
2288
2289 stat = request_irq(dev->pci_dev->irq, irq_handler,
2290 IRQF_SHARED, "nGene",
2291 (void *)dev);
2292 if (stat < 0)
2293 return stat;
2294
2295 init_waitqueue_head(&dev->cmd_wq);
2296 init_waitqueue_head(&dev->tx_wq);
2297 init_waitqueue_head(&dev->rx_wq);
2298 sema_init(&dev->cmd_mutex, 1);
2299 sema_init(&dev->stream_mutex, 1);
2300 sema_init(&dev->pll_mutex, 1);
2301 sema_init(&dev->i2c_switch_mutex, 1);
2302 spin_lock_init(&dev->cmd_lock);
2303 for (i = 0; i < MAX_STREAM; i++)
2304 spin_lock_init(&dev->channel[i].state_lock);
2305 ngwritel(1, TIMESTAMPS);
2306
2307 ngwritel(1, NGENE_INT_ENABLE);
2308
2309 stat = ngene_load_firm(dev);
2310 if (stat < 0)
2311 goto fail;
2312
2313 stat = ngene_i2c_init(dev, 0);
2314 if (stat < 0)
2315 goto fail;
2316
2317 stat = ngene_i2c_init(dev, 1);
2318 if (stat < 0)
2319 goto fail;
2320
2321 if (dev->card_info->fw_version == 17) {
2322 u8 hdtv_config[6] =
2323 {6144 / 64, 0, 0, 2048 / 64, 2048 / 64, 2048 / 64};
2324 u8 tsin4_config[6] =
2325 {3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0};
dae52d00
MB		 2326 u8 default_config[6] =
2327 {4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0};
2328 u8 *bconf = default_config;
2329
2330 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
2331 bconf = tsin4_config;
2332 if (dev->card_info->io_type[0] == NGENE_IO_HDTV) {
2333 bconf = hdtv_config;
2334 ngene_reset_decypher(dev);
2335 }
44cdd064 2336 dprintk(KERN_DEBUG DEVICE_NAME ": FW 17 buffer config\n");
dae52d00
MB		 2337 stat = ngene_command_config_free_buf(dev, bconf);
2338 } else {
2339 int bconf = BUFFER_CONFIG_4422;
2340
2341 if (dev->card_info->io_type[0] == NGENE_IO_HDTV) {
2342 bconf = BUFFER_CONFIG_8022;
2343 ngene_reset_decypher(dev);
2344 }
2345 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
2346 bconf = BUFFER_CONFIG_3333;
2347 stat = ngene_command_config_buf(dev, bconf);
2348 }
2349
2350 if (dev->card_info->io_type[0] == NGENE_IO_HDTV) {
2351 ngene_command_config_uart(dev, 0xc1, tx_cb, rx_cb);
2352 test_dec_i2c(&dev->channel[0].i2c_adapter, 0);
2353 test_dec_i2c(&dev->channel[0].i2c_adapter, 1);
2354 }
2355
2356 return stat;
2357fail:
2358 ngwritel(0, NGENE_INT_ENABLE);
2359 free_irq(dev->pci_dev->irq, dev);
2360 return stat;
2361}
2362
83f3c715
OE		 2363
2364
dae52d00 2365/****************************************************************************/
83f3c715 2366/* Switch control (I2C gates, etc.) *****************************************/
dae52d00
MB		 2367/****************************************************************************/
2368
dae52d00 2369
83f3c715
OE		 2370/****************************************************************************/
2371/* Demod/tuner attachment ***************************************************/
2372/****************************************************************************/
dae52d00 2373
8bba2607
MB		 2374static int tuner_attach_stv6110(struct ngene_channel *chan)
2375{
2376 struct stv090x_config *feconf = (struct stv090x_config *)
2377 chan->dev->card_info->fe_config[chan->number];
2378 struct stv6110x_config *tunerconf = (struct stv6110x_config *)
2379 chan->dev->card_info->tuner_config[chan->number];
2380 struct stv6110x_devctl *ctl;
2381
2382 ctl = dvb_attach(stv6110x_attach, chan->fe, tunerconf,
2383 &chan->i2c_adapter);
2384 if (ctl == NULL) {
2385 printk(KERN_ERR DEVICE_NAME ": No STV6110X found!\n");
2386 return -ENODEV;
2387 }
2388
2389 feconf->tuner_init = ctl->tuner_init;
2390 feconf->tuner_set_mode = ctl->tuner_set_mode;
2391 feconf->tuner_set_frequency = ctl->tuner_set_frequency;
2392 feconf->tuner_get_frequency = ctl->tuner_get_frequency;
2393 feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
2394 feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
2395 feconf->tuner_set_bbgain = ctl->tuner_set_bbgain;
2396 feconf->tuner_get_bbgain = ctl->tuner_get_bbgain;
2397 feconf->tuner_set_refclk = ctl->tuner_set_refclk;
2398 feconf->tuner_get_status = ctl->tuner_get_status;
2399
2400 return 0;
2401}
2402
2403
2404static int demod_attach_stv0900(struct ngene_channel *chan)
2405{
2406 struct stv090x_config *feconf = (struct stv090x_config *)
2407 chan->dev->card_info->fe_config[chan->number];
2408
2409 chan->fe = dvb_attach(stv090x_attach,
2410 feconf,
2411 &chan->i2c_adapter,
2412 chan->number == 0 ? STV090x_DEMODULATOR_0 :
2413 STV090x_DEMODULATOR_1);
2414 if (chan->fe == NULL) {
2415 printk(KERN_ERR DEVICE_NAME ": No STV0900 found!\n");
2416 return -ENODEV;
2417 }
2418
2419 if (!dvb_attach(lnbh24_attach, chan->fe, &chan->i2c_adapter, 0,
2420 0, chan->dev->card_info->lnb[chan->number])) {
2421 printk(KERN_ERR DEVICE_NAME ": No LNBH24 found!\n");
2422 dvb_frontend_detach(chan->fe);
2423 return -ENODEV;
2424 }
2425
2426 return 0;
2427}
dae52d00 2428
83f3c715
OE		 2429/****************************************************************************/
2430/****************************************************************************/
2431/****************************************************************************/
2432
2433static void release_channel(struct ngene_channel *chan)
dae52d00
MB		 2434{
2435 struct dvb_demux *dvbdemux = &chan->demux;
2436 struct ngene *dev = chan->dev;
2437 struct ngene_info *ni = dev->card_info;
2438 int io = ni->io_type[chan->number];
2439
2440 tasklet_kill(&chan->demux_tasklet);
2441
2442 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
2443#ifdef NGENE_COMMAND_API
2444 if (chan->command_dev)
2445 dvb_unregister_device(chan->command_dev);
2446#endif
dae52d00
MB		 2447 if (chan->fe) {
2448 dvb_unregister_frontend(chan->fe);
dc35c9ae 2449 dvb_frontend_detach(chan->fe);
dae52d00
MB		 2450 chan->fe = 0;
2451 }
2452 dvbdemux->dmx.close(&dvbdemux->dmx);
2453 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
2454 &chan->hw_frontend);
2455 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
2456 &chan->mem_frontend);
2457 dvb_dmxdev_release(&chan->dmxdev);
2458 dvb_dmx_release(&chan->demux);
2459#ifndef ONE_ADAPTER
2460 dvb_unregister_adapter(&chan->dvb_adapter);
2461#endif
2462 }
2463
dae52d00
MB		 2464}
2465
2466static int init_channel(struct ngene_channel *chan)
2467{
2468 int ret = 0, nr = chan->number;
2469 struct dvb_adapter *adapter = 0;
2470 struct dvb_demux *dvbdemux = &chan->demux;
2471 struct ngene *dev = chan->dev;
2472 struct ngene_info *ni = dev->card_info;
2473 int io = ni->io_type[nr];
2474
2475 tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
2476 chan->users = 0;
2477 chan->type = io;
2478 chan->mode = chan->type; /* for now only one mode */
2479
2480 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
2481 if (nr >= STREAM_AUDIOIN1)
2482 chan->DataFormatFlags = DF_SWAP32;
2483
2484 if (io & NGENE_IO_TSOUT)
2485 dec_fw_boot(dev);
2486
2487#ifdef ONE_ADAPTER
2488 adapter = &chan->dev->dvb_adapter;
2489#else
2490 ret = dvb_register_adapter(&chan->dvb_adapter, "nGene",
2491 THIS_MODULE,
6ed36e66
MB		 2492 &chan->dev->pci_dev->dev,
2493 adapter_nr);
dae52d00
MB		 2494 if (ret < 0)
2495 return ret;
2496 adapter = &chan->dvb_adapter;
2497#endif
2498 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
2499 ngene_start_feed,
2500 ngene_stop_feed, chan);
2501 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
2502 &chan->hw_frontend,
2503 &chan->mem_frontend, adapter);
2504 if (io & NGENE_IO_TSOUT) {
2505 dvbdemux->write_to_decoder = write_to_decoder;
dae52d00
MB		 2506 }
2507#ifdef NGENE_COMMAND_API
2508 dvb_register_device(adapter, &chan->command_dev,
2509 &dvbdev_command, (void *)chan,
2510 DVB_DEVICE_SEC);
2511#endif
2512 }
2513
2514 if (io & NGENE_IO_TSIN) {
2515 chan->fe = NULL;
2516 if (ni->demod_attach[nr])
2517 ni->demod_attach[nr](chan);
2518 if (chan->fe) {
2519 if (dvb_register_frontend(adapter, chan->fe) < 0) {
2520 if (chan->fe->ops.release)
2521 chan->fe->ops.release(chan->fe);
2522 chan->fe = NULL;
2523 }
2524 }
2525 if (chan->fe && ni->tuner_attach[nr])
2526 if (ni->tuner_attach[nr] (chan) < 0) {
2527 printk(KERN_ERR DEVICE_NAME
2528 ": Tuner attach failed on channel %d!\n",
2529 nr);
2530 }
2531 }
2532
dae52d00
MB		 2533 return ret;
2534}
2535
2536static int init_channels(struct ngene *dev)
2537{
2538 int i, j;
2539
2540 for (i = 0; i < MAX_STREAM; i++) {
2541 if (init_channel(&dev->channel[i]) < 0) {
2542 for (j = 0; j < i; j++)
2543 release_channel(&dev->channel[j]);
2544 return -1;
2545 }
2546 }
2547 return 0;
2548}
2549
2550/****************************************************************************/
2551/* device probe/remove calls ************************************************/
2552/****************************************************************************/
2553
2554static void __devexit ngene_remove(struct pci_dev *pdev)
2555{
2556 struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev);
2557 int i;
2558
2559 tasklet_kill(&dev->event_tasklet);
2560 for (i = 0; i < MAX_STREAM; i++)
2561 release_channel(&dev->channel[i]);
2562#ifdef ONE_ADAPTER
2563 dvb_unregister_adapter(&dev->dvb_adapter);
2564#endif
2565 ngene_stop(dev);
2566 ngene_release_buffers(dev);
2567 pci_set_drvdata(pdev, 0);
2568 pci_disable_device(pdev);
2569}
2570
2571static int __devinit ngene_probe(struct pci_dev *pci_dev,
2572 const struct pci_device_id *id)
2573{
2574 struct ngene *dev;
2575 int stat = 0;
2576
2577 if (pci_enable_device(pci_dev) < 0)
2578 return -ENODEV;
2579
2580 dev = vmalloc(sizeof(struct ngene));
dc35c9ae
RP		 2581 if (dev == NULL) {
2582 stat = -ENOMEM;
2583 goto fail0;
2584 }
dae52d00
MB		 2585 memset(dev, 0, sizeof(struct ngene));
2586
2587 dev->pci_dev = pci_dev;
2588 dev->card_info = (struct ngene_info *)id->driver_data;
2589 printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name);
2590
2591 pci_set_drvdata(pci_dev, dev);
2592
2593 /* Alloc buffers and start nGene */
2594 stat = ngene_get_buffers(dev);
2595 if (stat < 0)
2596 goto fail1;
2597 stat = ngene_start(dev);
2598 if (stat < 0)
2599 goto fail1;
2600
2601 dev->i2c_current_bus = -1;
dae52d00
MB		 2602 /* Disable analog TV decoder chips if present */
2603 if (copy_eeprom) {
2604 i2c_copy_eeprom(&dev->channel[0].i2c_adapter, 0x50, 0x52);
2605 i2c_dump_eeprom(&dev->channel[0].i2c_adapter, 0x52);
2606 }
2607 /*i2c_check_eeprom(&dev->i2c_adapter);*/
2608
2609 /* Register DVB adapters and devices for both channels */
2610#ifdef ONE_ADAPTER
2611 if (dvb_register_adapter(&dev->dvb_adapter, "nGene", THIS_MODULE,
2612 &dev->pci_dev->dev, adapter_nr) < 0)
2613 goto fail2;
2614#endif
2615 if (init_channels(dev) < 0)
2616 goto fail2;
2617
2618 return 0;
2619
2620fail2:
2621 ngene_stop(dev);
2622fail1:
2623 ngene_release_buffers(dev);
dc35c9ae
RP		 2624fail0:
2625 pci_disable_device(pci_dev);
dae52d00
MB		 2626 pci_set_drvdata(pci_dev, 0);
2627 return stat;
2628}
2629
2630/****************************************************************************/
2631/* Card configs *************************************************************/
2632/****************************************************************************/
2633
8bba2607
MB		 2634static struct stv090x_config fe_mps2 = {
2635 .device = STV0900,
2636 .demod_mode = STV090x_DUAL,
2637 .clk_mode = STV090x_CLK_EXT,
2638
2639 .xtal = 27000000,
2640 .address = 0x68,
2641// .ref_clk = 27000000,
2642
2643 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
2644 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
2645
2646 .repeater_level = STV090x_RPTLEVEL_16,
2647
2648 .diseqc_envelope_mode = true,
2649
2650 .tuner_init = NULL,
2651 .tuner_set_mode = NULL,
2652 .tuner_set_frequency = NULL,
2653 .tuner_get_frequency = NULL,
2654 .tuner_set_bandwidth = NULL,
2655 .tuner_get_bandwidth = NULL,
2656 .tuner_set_bbgain = NULL,
2657 .tuner_get_bbgain = NULL,
2658 .tuner_set_refclk = NULL,
2659 .tuner_get_status = NULL,
2660};
2661
2662static struct stv6110x_config tuner_mps2_0 = {
2663 .addr = 0x60,
2664 .refclk = 27000000,
2665};
2666
2667static struct stv6110x_config tuner_mps2_1 = {
2668 .addr = 0x63,
2669 .refclk = 27000000,
2670};
2671
2672static struct ngene_info ngene_info_mps2 = {
2673 .type = NGENE_SIDEWINDER,
2674 .name = "Media-Pointer MP-S2/CineS2 DVB-S2 Twin Tuner",
2675 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN},
2676 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900},
2677 .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110},
2678 .fe_config = {&fe_mps2, &fe_mps2},
2679 .tuner_config = {&tuner_mps2_0, &tuner_mps2_1},
2680 .lnb = {0x0b, 0x08},
2681 .tsf = {3, 3},
2682 .fw_version = 17,
2683};
2684
2685/****************************************************************************/
2686
dae52d00
MB		 2687
2688
2689/****************************************************************************/
2690/****************************************************************************/
2691/****************************************************************************/
2692
2693#define NGENE_ID(_subvend, _subdev, _driverdata) { \
2694 .vendor = NGENE_VID, .device = NGENE_PID, \
2695 .subvendor = _subvend, .subdevice = _subdev, \
2696 .driver_data = (unsigned long) &_driverdata }
2697
2698/****************************************************************************/
2699
2700static const struct pci_device_id ngene_id_tbl[] __devinitdata = {
8bba2607
MB		 2701 NGENE_ID(0x18c3, 0xabc3, ngene_info_mps2),
2702 NGENE_ID(0x18c3, 0xabc4, ngene_info_mps2),
2703 NGENE_ID(0x18c3, 0xdb01, ngene_info_mps2),
dae52d00
MB		 2704 {0}
2705};
8bba2607 2706MODULE_DEVICE_TABLE(pci, ngene_id_tbl);
dae52d00
MB		 2707
2708/****************************************************************************/
2709/* Init/Exit ****************************************************************/
2710/****************************************************************************/
2711
2712static pci_ers_result_t ngene_error_detected(struct pci_dev *dev,
2713 enum pci_channel_state state)
2714{
2715 printk(KERN_ERR DEVICE_NAME ": PCI error\n");
2716 if (state == pci_channel_io_perm_failure)
2717 return PCI_ERS_RESULT_DISCONNECT;
2718 if (state == pci_channel_io_frozen)
2719 return PCI_ERS_RESULT_NEED_RESET;
2720 return PCI_ERS_RESULT_CAN_RECOVER;
2721}
2722
2723static pci_ers_result_t ngene_link_reset(struct pci_dev *dev)
2724{
2725 printk(KERN_INFO DEVICE_NAME ": link reset\n");
2726 return 0;
2727}
2728
2729static pci_ers_result_t ngene_slot_reset(struct pci_dev *dev)
2730{
2731 printk(KERN_INFO DEVICE_NAME ": slot reset\n");
2732 return 0;
2733}
2734
2735static void ngene_resume(struct pci_dev *dev)
2736{
2737 printk(KERN_INFO DEVICE_NAME ": resume\n");
2738}
2739
2740static struct pci_error_handlers ngene_errors = {
2741 .error_detected = ngene_error_detected,
2742 .link_reset = ngene_link_reset,
2743 .slot_reset = ngene_slot_reset,
2744 .resume = ngene_resume,
2745};
2746
2747static struct pci_driver ngene_pci_driver = {
2748 .name = "ngene",
2749 .id_table = ngene_id_tbl,
2750 .probe = ngene_probe,
dc35c9ae 2751 .remove = __devexit_p(ngene_remove),
dae52d00
MB		 2752 .err_handler = &ngene_errors,
2753};
2754
2755static __init int module_init_ngene(void)
2756{
2757 printk(KERN_INFO
2758 "nGene PCIE bridge driver, Copyright (C) 2005-2007 Micronas\n");
2759 return pci_register_driver(&ngene_pci_driver);
2760}
2761
2762static __exit void module_exit_ngene(void)
2763{
2764 pci_unregister_driver(&ngene_pci_driver);
2765}
2766
2767module_init(module_init_ngene);
2768module_exit(module_exit_ngene);
2769
2770MODULE_DESCRIPTION("nGene");
2771MODULE_AUTHOR("Micronas, Ralph Metzler, Manfred Voelkel");
2772MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)