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V4L/DVB: em28xx: add Dikom DK300 hybrid USB tuner
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / dvb / ngene / ngene-core.c
CommitLineData
dae52d00
MB		 1/*
2 * ngene.c: nGene PCIe bridge driver
3 *
4 * Copyright (C) 2005-2007 Micronas
5 *
6 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
7 * Modifications for new nGene firmware,
8 * support for EEPROM-copying,
9 * support for new dual DVB-S2 card prototype
10 *
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 only, as published by the Free Software Foundation.
15 *
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
26 * 02110-1301, USA
27 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
28 */
29
30#include <linux/module.h>
31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
34#include <linux/poll.h>
684688d8 35#include <linux/io.h>
dae52d00
MB		 36#include <asm/div64.h>
37#include <linux/pci.h>
38#include <linux/pci_ids.h>
39#include <linux/smp_lock.h>
40#include <linux/timer.h>
41#include <linux/version.h>
42#include <linux/byteorder/generic.h>
43#include <linux/firmware.h>
6fd2d0f9 44#include <linux/vmalloc.h>
dae52d00
MB		 45
46#include "ngene.h"
47
8bba2607
MB		 48#include "stv6110x.h"
49#include "stv090x.h"
50#include "lnbh24.h"
51
cf1b12f2
MB		 52static int one_adapter = 1;
53module_param(one_adapter, int, 0444);
54MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
55
dae52d00 56
dae52d00
MB		 57static int debug;
58module_param(debug, int, 0444);
59MODULE_PARM_DESC(debug, "Print debugging information.");
60
83f3c715
OE		 61DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
62
b1ec9532
OE		 63#define COMMAND_TIMEOUT_WORKAROUND
64
dae52d00
MB		 65#define dprintk if (debug) printk
66
67#define DEVICE_NAME "ngene"
68
69#define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr)))
70#define ngwritel(dat, adr) writel((dat), (char *)(dev->iomem + (adr)))
71#define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr)))
72#define ngreadl(adr) readl(dev->iomem + (adr))
73#define ngreadb(adr) readb(dev->iomem + (adr))
74#define ngcpyto(adr, src, count) memcpy_toio((char *) \
75 (dev->iomem + (adr)), (src), (count))
76#define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \
77 (dev->iomem + (adr)), (count))
78
dae52d00
MB		 79/****************************************************************************/
80/* nGene interrupt handler **************************************************/
81/****************************************************************************/
82
83static void event_tasklet(unsigned long data)
84{
85 struct ngene *dev = (struct ngene *)data;
86
87 while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
88 struct EVENT_BUFFER Event =
89 dev->EventQueue[dev->EventQueueReadIndex];
90 dev->EventQueueReadIndex =
91 (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
92
93 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
94 dev->TxEventNotify(dev, Event.TimeStamp);
95 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
96 dev->RxEventNotify(dev, Event.TimeStamp,
97 Event.RXCharacter);
98 }
99}
100
101static void demux_tasklet(unsigned long data)
102{
103 struct ngene_channel *chan = (struct ngene_channel *)data;
104 struct SBufferHeader *Cur = chan->nextBuffer;
105
106 spin_lock_irq(&chan->state_lock);
107
108 while (Cur->ngeneBuffer.SR.Flags & 0x80) {
109 if (chan->mode & NGENE_IO_TSOUT) {
110 u32 Flags = chan->DataFormatFlags;
111 if (Cur->ngeneBuffer.SR.Flags & 0x20)
112 Flags |= BEF_OVERFLOW;
113 if (chan->pBufferExchange) {
114 if (!chan->pBufferExchange(chan,
115 Cur->Buffer1,
116 chan->Capture1Length,
117 Cur->ngeneBuffer.SR.
118 Clock, Flags)) {
119 /*
120 We didn't get data
121 Clear in service flag to make sure we
122 get called on next interrupt again.
123 leave fill/empty (0x80) flag alone
124 to avoid hardware running out of
125 buffers during startup, we hold only
126 in run state ( the source may be late
127 delivering data )
128 */
129
130 if (chan->HWState == HWSTATE_RUN) {
131 Cur->ngeneBuffer.SR.Flags &=
132 ~0x40;
133 break;
134 /* Stop proccessing stream */
135 }
136 } else {
137 /* We got a valid buffer,
138 so switch to run state */
139 chan->HWState = HWSTATE_RUN;
140 }
141 } else {
142 printk(KERN_ERR DEVICE_NAME ": OOPS\n");
143 if (chan->HWState == HWSTATE_RUN) {
144 Cur->ngeneBuffer.SR.Flags &= ~0x40;
145 break; /* Stop proccessing stream */
146 }
147 }
148 if (chan->AudioDTOUpdated) {
149 printk(KERN_INFO DEVICE_NAME
150 ": Update AudioDTO = %d\n",
151 chan->AudioDTOValue);
152 Cur->ngeneBuffer.SR.DTOUpdate =
153 chan->AudioDTOValue;
154 chan->AudioDTOUpdated = 0;
155 }
156 } else {
157 if (chan->HWState == HWSTATE_RUN) {
158 u32 Flags = 0;
159 if (Cur->ngeneBuffer.SR.Flags & 0x01)
160 Flags |= BEF_EVEN_FIELD;
161 if (Cur->ngeneBuffer.SR.Flags & 0x20)
162 Flags |= BEF_OVERFLOW;
163 if (chan->pBufferExchange)
164 chan->pBufferExchange(chan,
165 Cur->Buffer1,
166 chan->
167 Capture1Length,
168 Cur->ngeneBuffer.
169 SR.Clock, Flags);
170 if (chan->pBufferExchange2)
171 chan->pBufferExchange2(chan,
172 Cur->Buffer2,
173 chan->
174 Capture2Length,
175 Cur->ngeneBuffer.
176 SR.Clock, Flags);
177 } else if (chan->HWState != HWSTATE_STOP)
178 chan->HWState = HWSTATE_RUN;
179 }
180 Cur->ngeneBuffer.SR.Flags = 0x00;
181 Cur = Cur->Next;
182 }
183 chan->nextBuffer = Cur;
184
185 spin_unlock_irq(&chan->state_lock);
186}
187
188static irqreturn_t irq_handler(int irq, void *dev_id)
189{
190 struct ngene *dev = (struct ngene *)dev_id;
191 u32 icounts = 0;
192 irqreturn_t rc = IRQ_NONE;
193 u32 i = MAX_STREAM;
194 u8 *tmpCmdDoneByte;
195
196 if (dev->BootFirmware) {
197 icounts = ngreadl(NGENE_INT_COUNTS);
198 if (icounts != dev->icounts) {
199 ngwritel(0, FORCE_NMI);
200 dev->cmd_done = 1;
201 wake_up(&dev->cmd_wq);
202 dev->icounts = icounts;
203 rc = IRQ_HANDLED;
204 }
205 return rc;
206 }
207
208 ngwritel(0, FORCE_NMI);
209
210 spin_lock(&dev->cmd_lock);
211 tmpCmdDoneByte = dev->CmdDoneByte;
212 if (tmpCmdDoneByte &&
213 (*tmpCmdDoneByte ||
214 (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
215 dev->CmdDoneByte = NULL;
216 dev->cmd_done = 1;
217 wake_up(&dev->cmd_wq);
218 rc = IRQ_HANDLED;
219 }
220 spin_unlock(&dev->cmd_lock);
221
222 if (dev->EventBuffer->EventStatus & 0x80) {
223 u8 nextWriteIndex =
224 (dev->EventQueueWriteIndex + 1) &
225 (EVENT_QUEUE_SIZE - 1);
226 if (nextWriteIndex != dev->EventQueueReadIndex) {
227 dev->EventQueue[dev->EventQueueWriteIndex] =
228 *(dev->EventBuffer);
229 dev->EventQueueWriteIndex = nextWriteIndex;
230 } else {
231 printk(KERN_ERR DEVICE_NAME ": event overflow\n");
232 dev->EventQueueOverflowCount += 1;
233 dev->EventQueueOverflowFlag = 1;
234 }
235 dev->EventBuffer->EventStatus &= ~0x80;
236 tasklet_schedule(&dev->event_tasklet);
237 rc = IRQ_HANDLED;
238 }
239
240 while (i > 0) {
241 i--;
242 spin_lock(&dev->channel[i].state_lock);
243 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
244 if (dev->channel[i].nextBuffer) {
245 if ((dev->channel[i].nextBuffer->
246 ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
247 dev->channel[i].nextBuffer->
248 ngeneBuffer.SR.Flags |= 0x40;
249 tasklet_schedule(
250 &dev->channel[i].demux_tasklet);
251 rc = IRQ_HANDLED;
252 }
253 }
254 spin_unlock(&dev->channel[i].state_lock);
255 }
256
ace30f74
OE		 257 /* Request might have been processed by a previous call. */
258 return IRQ_HANDLED;
dae52d00
MB		 259}
260
261/****************************************************************************/
262/* nGene command interface **************************************************/
263/****************************************************************************/
264
b1ec9532
OE		 265static void dump_command_io(struct ngene *dev)
266{
267 u8 buf[8], *b;
268
269 ngcpyfrom(buf, HOST_TO_NGENE, 8);
270 printk(KERN_ERR "host_to_ngene (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
684688d8
OE		 271 HOST_TO_NGENE, buf[0], buf[1], buf[2], buf[3],
272 buf[4], buf[5], buf[6], buf[7]);
b1ec9532
OE		 273
274 ngcpyfrom(buf, NGENE_TO_HOST, 8);
275 printk(KERN_ERR "ngene_to_host (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
684688d8
OE		 276 NGENE_TO_HOST, buf[0], buf[1], buf[2], buf[3],
277 buf[4], buf[5], buf[6], buf[7]);
b1ec9532
OE		 278
279 b = dev->hosttongene;
280 printk(KERN_ERR "dev->hosttongene (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
281 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
282
283 b = dev->ngenetohost;
284 printk(KERN_ERR "dev->ngenetohost (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
285 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
286}
287
dae52d00
MB		 288static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
289{
290 int ret;
291 u8 *tmpCmdDoneByte;
292
293 dev->cmd_done = 0;
294
295 if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
296 dev->BootFirmware = 1;
297 dev->icounts = ngreadl(NGENE_INT_COUNTS);
298 ngwritel(0, NGENE_COMMAND);
299 ngwritel(0, NGENE_COMMAND_HI);
300 ngwritel(0, NGENE_STATUS);
301 ngwritel(0, NGENE_STATUS_HI);
302 ngwritel(0, NGENE_EVENT);
303 ngwritel(0, NGENE_EVENT_HI);
304 } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
305 u64 fwio = dev->PAFWInterfaceBuffer;
306
307 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
308 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
309 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
310 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
311 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
312 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
313 }
314
315 memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
316
317 if (dev->BootFirmware)
318 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
319
320 spin_lock_irq(&dev->cmd_lock);
321 tmpCmdDoneByte = dev->ngenetohost + com->out_len;
322 if (!com->out_len)
323 tmpCmdDoneByte++;
324 *tmpCmdDoneByte = 0;
325 dev->ngenetohost[0] = 0;
326 dev->ngenetohost[1] = 0;
327 dev->CmdDoneByte = tmpCmdDoneByte;
328 spin_unlock_irq(&dev->cmd_lock);
329
330 /* Notify 8051. */
331 ngwritel(1, FORCE_INT);
332
333 ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
334 if (!ret) {
335 /*ngwritel(0, FORCE_NMI);*/
336
337 printk(KERN_ERR DEVICE_NAME
338 ": Command timeout cmd=%02x prev=%02x\n",
339 com->cmd.hdr.Opcode, dev->prev_cmd);
b1ec9532 340 dump_command_io(dev);
dae52d00
MB		 341 return -1;
342 }
343 if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
344 dev->BootFirmware = 0;
345
346 dev->prev_cmd = com->cmd.hdr.Opcode;
dae52d00
MB		 347
348 if (!com->out_len)
349 return 0;
350
351 memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
352
353 return 0;
354}
355
356static int ngene_command(struct ngene *dev, struct ngene_command *com)
357{
358 int result;
359
360 down(&dev->cmd_mutex);
361 result = ngene_command_mutex(dev, com);
362 up(&dev->cmd_mutex);
363 return result;
364}
365
dae52d00 366
9fdd7976 367static int ngene_command_i2c_read(struct ngene *dev, u8 adr,
dae52d00
MB		 368 u8 *out, u8 outlen, u8 *in, u8 inlen, int flag)
369{
370 struct ngene_command com;
371
372 com.cmd.hdr.Opcode = CMD_I2C_READ;
373 com.cmd.hdr.Length = outlen + 3;
374 com.cmd.I2CRead.Device = adr << 1;
375 memcpy(com.cmd.I2CRead.Data, out, outlen);
376 com.cmd.I2CRead.Data[outlen] = inlen;
377 com.cmd.I2CRead.Data[outlen + 1] = 0;
378 com.in_len = outlen + 3;
379 com.out_len = inlen + 1;
380
381 if (ngene_command(dev, &com) < 0)
382 return -EIO;
383
384 if ((com.cmd.raw8[0] >> 1) != adr)
385 return -EIO;
386
387 if (flag)
388 memcpy(in, com.cmd.raw8, inlen + 1);
389 else
390 memcpy(in, com.cmd.raw8 + 1, inlen);
391 return 0;
392}
393
9fdd7976
OE		 394static int ngene_command_i2c_write(struct ngene *dev, u8 adr,
395 u8 *out, u8 outlen)
dae52d00
MB		 396{
397 struct ngene_command com;
398
399
400 com.cmd.hdr.Opcode = CMD_I2C_WRITE;
401 com.cmd.hdr.Length = outlen + 1;
402 com.cmd.I2CRead.Device = adr << 1;
403 memcpy(com.cmd.I2CRead.Data, out, outlen);
404 com.in_len = outlen + 1;
405 com.out_len = 1;
406
407 if (ngene_command(dev, &com) < 0)
408 return -EIO;
409
410 if (com.cmd.raw8[0] == 1)
411 return -EIO;
412
413 return 0;
414}
415
416static int ngene_command_load_firmware(struct ngene *dev,
417 u8 *ngene_fw, u32 size)
418{
419#define FIRSTCHUNK (1024)
420 u32 cleft;
421 struct ngene_command com;
422
423 com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
424 com.cmd.hdr.Length = 0;
425 com.in_len = 0;
426 com.out_len = 0;
427
428 ngene_command(dev, &com);
429
430 cleft = (size + 3) & ~3;
431 if (cleft > FIRSTCHUNK) {
432 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
433 cleft - FIRSTCHUNK);
434 cleft = FIRSTCHUNK;
435 }
dae52d00
MB		 436 ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
437
438 memset(&com, 0, sizeof(struct ngene_command));
439 com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
440 com.cmd.hdr.Length = 4;
441 com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
442 com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
443 com.in_len = 4;
444 com.out_len = 0;
445
446 return ngene_command(dev, &com);
447}
448
dae52d00
MB		 449
450static int ngene_command_config_buf(struct ngene *dev, u8 config)
451{
452 struct ngene_command com;
453
454 com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
455 com.cmd.hdr.Length = 1;
456 com.cmd.ConfigureBuffers.config = config;
457 com.in_len = 1;
458 com.out_len = 0;
459
460 if (ngene_command(dev, &com) < 0)
461 return -EIO;
462 return 0;
463}
464
465static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
466{
467 struct ngene_command com;
468
469 com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
470 com.cmd.hdr.Length = 6;
471 memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
472 com.in_len = 6;
473 com.out_len = 0;
474
475 if (ngene_command(dev, &com) < 0)
476 return -EIO;
477
478 return 0;
479}
480
481static int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
482{
483 struct ngene_command com;
484
485 com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
486 com.cmd.hdr.Length = 1;
487 com.cmd.SetGpioPin.select = select | (level << 7);
488 com.in_len = 1;
489 com.out_len = 0;
490
491 return ngene_command(dev, &com);
492}
493
dae52d00
MB		 494
495/*
496 02000640 is sample on rising edge.
497 02000740 is sample on falling edge.
498 02000040 is ignore "valid" signal
499
500 0: FD_CTL1 Bit 7,6 must be 0,1
501 7 disable(fw controlled)
502 6 0-AUX,1-TS
503 5 0-par,1-ser
504 4 0-lsb/1-msb
505 3,2 reserved
506 1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
507 1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
508 2: FD_STA is read-only. 0-sync
509 3: FD_INSYNC is number of 47s to trigger "in sync".
510 4: FD_OUTSYNC is number of 47s to trigger "out of sync".
511 5: FD_MAXBYTE1 is low-order of bytes per packet.
512 6: FD_MAXBYTE2 is high-order of bytes per packet.
513 7: Top byte is unused.
514*/
515
516/****************************************************************************/
517
518static u8 TSFeatureDecoderSetup[8 * 4] = {
519 0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
520 0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
521 0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
522 0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
523};
524
525/* Set NGENE I2S Config to 16 bit packed */
526static u8 I2SConfiguration[] = {
527 0x00, 0x10, 0x00, 0x00,
528 0x80, 0x10, 0x00, 0x00,
529};
530
531static u8 SPDIFConfiguration[10] = {
532 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
533};
534
535/* Set NGENE I2S Config to transport stream compatible mode */
536
537static u8 TS_I2SConfiguration[4] = { 0x3E, 0x1A, 0x00, 0x00 }; /*3e 18 00 00 ?*/
538
539static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x20, 0x00, 0x00 };
540
541static u8 ITUDecoderSetup[4][16] = {
542 {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */
543 0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
544 {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
545 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
546 {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00, /* HDTV 1080i50 */
547 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
548 {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, /* HDTV 1080i60 */
549 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
550};
551
552/*
553 * 50 48 60 gleich
554 * 27p50 9f 00 22 80 42 69 18 ...
555 * 27p60 93 00 22 80 82 69 1c ...
556 */
557
558/* Maxbyte to 1144 (for raw data) */
559static u8 ITUFeatureDecoderSetup[8] = {
560 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
561};
562
563static void FillTSBuffer(void *Buffer, int Length, u32 Flags)
564{
565 u32 *ptr = Buffer;
566
567 memset(Buffer, Length, 0xff);
568 while (Length > 0) {
569 if (Flags & DF_SWAP32)
570 *ptr = 0x471FFF10;
571 else
572 *ptr = 0x10FF1F47;
573 ptr += (188 / 4);
574 Length -= 188;
575 }
576}
577
dae52d00
MB		 578
579static void flush_buffers(struct ngene_channel *chan)
580{
581 u8 val;
582
583 do {
584 msleep(1);
585 spin_lock_irq(&chan->state_lock);
586 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
587 spin_unlock_irq(&chan->state_lock);
588 } while (val);
589}
590
591static void clear_buffers(struct ngene_channel *chan)
592{
593 struct SBufferHeader *Cur = chan->nextBuffer;
594
595 do {
596 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
597 if (chan->mode & NGENE_IO_TSOUT)
598 FillTSBuffer(Cur->Buffer1,
599 chan->Capture1Length,
600 chan->DataFormatFlags);
601 Cur = Cur->Next;
602 } while (Cur != chan->nextBuffer);
603
604 if (chan->mode & NGENE_IO_TSOUT) {
605 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
606 chan->AudioDTOValue;
607 chan->AudioDTOUpdated = 0;
608
609 Cur = chan->TSIdleBuffer.Head;
610
611 do {
612 memset(&Cur->ngeneBuffer.SR, 0,
613 sizeof(Cur->ngeneBuffer.SR));
614 FillTSBuffer(Cur->Buffer1,
615 chan->Capture1Length,
616 chan->DataFormatFlags);
617 Cur = Cur->Next;
618 } while (Cur != chan->TSIdleBuffer.Head);
619 }
620}
621
9fdd7976
OE		 622static int ngene_command_stream_control(struct ngene *dev, u8 stream,
623 u8 control, u8 mode, u8 flags)
dae52d00
MB		 624{
625 struct ngene_channel *chan = &dev->channel[stream];
626 struct ngene_command com;
627 u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
628 u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
629 u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
630 u16 BsSDO = 0x9B00;
631
632 /* down(&dev->stream_mutex); */
633 while (down_trylock(&dev->stream_mutex)) {
634 printk(KERN_INFO DEVICE_NAME ": SC locked\n");
635 msleep(1);
636 }
637 memset(&com, 0, sizeof(com));
638 com.cmd.hdr.Opcode = CMD_CONTROL;
639 com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
640 com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
641 if (chan->mode & NGENE_IO_TSOUT)
642 com.cmd.StreamControl.Stream |= 0x07;
643 com.cmd.StreamControl.Control = control |
644 (flags & SFLAG_ORDER_LUMA_CHROMA);
645 com.cmd.StreamControl.Mode = mode;
646 com.in_len = sizeof(struct FW_STREAM_CONTROL);
647 com.out_len = 0;
648
44cdd064
OE		 649 dprintk(KERN_INFO DEVICE_NAME
650 ": Stream=%02x, Control=%02x, Mode=%02x\n",
651 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
652 com.cmd.StreamControl.Mode);
653
dae52d00
MB		 654 chan->Mode = mode;
655
656 if (!(control & 0x80)) {
657 spin_lock_irq(&chan->state_lock);
658 if (chan->State == KSSTATE_RUN) {
659 chan->State = KSSTATE_ACQUIRE;
660 chan->HWState = HWSTATE_STOP;
661 spin_unlock_irq(&chan->state_lock);
662 if (ngene_command(dev, &com) < 0) {
663 up(&dev->stream_mutex);
664 return -1;
665 }
666 /* clear_buffers(chan); */
667 flush_buffers(chan);
668 up(&dev->stream_mutex);
669 return 0;
670 }
671 spin_unlock_irq(&chan->state_lock);
672 up(&dev->stream_mutex);
673 return 0;
674 }
675
676 if (mode & SMODE_AUDIO_CAPTURE) {
677 com.cmd.StreamControl.CaptureBlockCount =
678 chan->Capture1Length / AUDIO_BLOCK_SIZE;
679 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
680 } else if (mode & SMODE_TRANSPORT_STREAM) {
681 com.cmd.StreamControl.CaptureBlockCount =
682 chan->Capture1Length / TS_BLOCK_SIZE;
683 com.cmd.StreamControl.MaxLinesPerField =
684 chan->Capture1Length / TS_BLOCK_SIZE;
685 com.cmd.StreamControl.Buffer_Address =
686 chan->TSRingBuffer.PAHead;
687 if (chan->mode & NGENE_IO_TSOUT) {
688 com.cmd.StreamControl.BytesPerVBILine =
689 chan->Capture1Length / TS_BLOCK_SIZE;
690 com.cmd.StreamControl.Stream |= 0x07;
691 }
692 } else {
693 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
694 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
695 com.cmd.StreamControl.MinLinesPerField = 100;
696 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
697
698 if (mode & SMODE_VBI_CAPTURE) {
699 com.cmd.StreamControl.MaxVBILinesPerField =
700 chan->nVBILines;
701 com.cmd.StreamControl.MinVBILinesPerField = 0;
702 com.cmd.StreamControl.BytesPerVBILine =
703 chan->nBytesPerVBILine;
704 }
705 if (flags & SFLAG_COLORBAR)
706 com.cmd.StreamControl.Stream |= 0x04;
707 }
708
709 spin_lock_irq(&chan->state_lock);
710 if (mode & SMODE_AUDIO_CAPTURE) {
711 chan->nextBuffer = chan->RingBuffer.Head;
712 if (mode & SMODE_AUDIO_SPDIF) {
713 com.cmd.StreamControl.SetupDataLen =
714 sizeof(SPDIFConfiguration);
715 com.cmd.StreamControl.SetupDataAddr = BsSPI;
716 memcpy(com.cmd.StreamControl.SetupData,
717 SPDIFConfiguration, sizeof(SPDIFConfiguration));
718 } else {
719 com.cmd.StreamControl.SetupDataLen = 4;
720 com.cmd.StreamControl.SetupDataAddr = BsSDI;
721 memcpy(com.cmd.StreamControl.SetupData,
722 I2SConfiguration +
723 4 * dev->card_info->i2s[stream], 4);
724 }
725 } else if (mode & SMODE_TRANSPORT_STREAM) {
726 chan->nextBuffer = chan->TSRingBuffer.Head;
727 if (stream >= STREAM_AUDIOIN1) {
728 if (chan->mode & NGENE_IO_TSOUT) {
729 com.cmd.StreamControl.SetupDataLen =
730 sizeof(TS_I2SOutConfiguration);
731 com.cmd.StreamControl.SetupDataAddr = BsSDO;
732 memcpy(com.cmd.StreamControl.SetupData,
733 TS_I2SOutConfiguration,
734 sizeof(TS_I2SOutConfiguration));
735 } else {
736 com.cmd.StreamControl.SetupDataLen =
737 sizeof(TS_I2SConfiguration);
738 com.cmd.StreamControl.SetupDataAddr = BsSDI;
739 memcpy(com.cmd.StreamControl.SetupData,
740 TS_I2SConfiguration,
741 sizeof(TS_I2SConfiguration));
742 }
743 } else {
744 com.cmd.StreamControl.SetupDataLen = 8;
745 com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
746 memcpy(com.cmd.StreamControl.SetupData,
747 TSFeatureDecoderSetup +
748 8 * dev->card_info->tsf[stream], 8);
749 }
750 } else {
751 chan->nextBuffer = chan->RingBuffer.Head;
752 com.cmd.StreamControl.SetupDataLen =
753 16 + sizeof(ITUFeatureDecoderSetup);
754 com.cmd.StreamControl.SetupDataAddr = BsUVI;
755 memcpy(com.cmd.StreamControl.SetupData,
756 ITUDecoderSetup[chan->itumode], 16);
757 memcpy(com.cmd.StreamControl.SetupData + 16,
758 ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
759 }
760 clear_buffers(chan);
761 chan->State = KSSTATE_RUN;
762 if (mode & SMODE_TRANSPORT_STREAM)
763 chan->HWState = HWSTATE_RUN;
764 else
765 chan->HWState = HWSTATE_STARTUP;
766 spin_unlock_irq(&chan->state_lock);
767
768 if (ngene_command(dev, &com) < 0) {
769 up(&dev->stream_mutex);
770 return -1;
771 }
772 up(&dev->stream_mutex);
773 return 0;
774}
775
dae52d00
MB		 776
777/****************************************************************************/
778/* I2C **********************************************************************/
779/****************************************************************************/
780
781static void ngene_i2c_set_bus(struct ngene *dev, int bus)
782{
783 if (!(dev->card_info->i2c_access & 2))
784 return;
785 if (dev->i2c_current_bus == bus)
786 return;
787
788 switch (bus) {
789 case 0:
790 ngene_command_gpio_set(dev, 3, 0);
791 ngene_command_gpio_set(dev, 2, 1);
792 break;
793
794 case 1:
795 ngene_command_gpio_set(dev, 2, 0);
796 ngene_command_gpio_set(dev, 3, 1);
797 break;
798 }
799 dev->i2c_current_bus = bus;
800}
801
802static int ngene_i2c_master_xfer(struct i2c_adapter *adapter,
803 struct i2c_msg msg[], int num)
804{
805 struct ngene_channel *chan =
806 (struct ngene_channel *)i2c_get_adapdata(adapter);
807 struct ngene *dev = chan->dev;
808
809 down(&dev->i2c_switch_mutex);
810 ngene_i2c_set_bus(dev, chan->number);
811
812 if (num == 2 && msg[1].flags & I2C_M_RD && !(msg[0].flags & I2C_M_RD))
813 if (!ngene_command_i2c_read(dev, msg[0].addr,
814 msg[0].buf, msg[0].len,
815 msg[1].buf, msg[1].len, 0))
816 goto done;
817
818 if (num == 1 && !(msg[0].flags & I2C_M_RD))
819 if (!ngene_command_i2c_write(dev, msg[0].addr,
820 msg[0].buf, msg[0].len))
821 goto done;
822 if (num == 1 && (msg[0].flags & I2C_M_RD))
823 if (!ngene_command_i2c_read(dev, msg[0].addr, 0, 0,
824 msg[0].buf, msg[0].len, 0))
825 goto done;
826
827 up(&dev->i2c_switch_mutex);
828 return -EIO;
829
830done:
831 up(&dev->i2c_switch_mutex);
832 return num;
833}
834
835
dae52d00
MB		 836static u32 ngene_i2c_functionality(struct i2c_adapter *adap)
837{
838 return I2C_FUNC_SMBUS_EMUL;
839}
840
9fdd7976 841static struct i2c_algorithm ngene_i2c_algo = {
dae52d00
MB		 842 .master_xfer = ngene_i2c_master_xfer,
843 .functionality = ngene_i2c_functionality,
844};
845
dae52d00
MB		 846static int ngene_i2c_init(struct ngene *dev, int dev_nr)
847{
848 struct i2c_adapter *adap = &(dev->channel[dev_nr].i2c_adapter);
849
850 i2c_set_adapdata(adap, &(dev->channel[dev_nr]));
6525e67c 851 adap->class = I2C_CLASS_TV_DIGITAL | I2C_CLASS_TV_ANALOG;
dae52d00
MB		 852
853 strcpy(adap->name, "nGene");
854
dae52d00
MB		 855 adap->algo = &ngene_i2c_algo;
856 adap->algo_data = (void *)&(dev->channel[dev_nr]);
c58b5ecd 857 adap->dev.parent = &dev->pci_dev->dev;
dae52d00 858
dae52d00
MB		 859 return i2c_add_adapter(adap);
860}
861
dae52d00
MB		 862
863/****************************************************************************/
864/* DVB functions and API interface ******************************************/
865/****************************************************************************/
866
867static void swap_buffer(u32 *p, u32 len)
868{
869 while (len) {
870 *p = swab32(*p);
871 p++;
872 len -= 4;
873 }
874}
875
dae52d00
MB		 876
877static void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
878{
879 struct ngene_channel *chan = priv;
880
881
b1ec9532
OE		 882#ifdef COMMAND_TIMEOUT_WORKAROUND
883 if (chan->users > 0)
884#endif
885 dvb_dmx_swfilter(&chan->demux, buf, len);
dae52d00
MB		 886 return 0;
887}
888
889u8 fill_ts[188] = { 0x47, 0x1f, 0xff, 0x10 };
890
891static void *tsout_exchange(void *priv, void *buf, u32 len,
892 u32 clock, u32 flags)
893{
894 struct ngene_channel *chan = priv;
895 struct ngene *dev = chan->dev;
896 u32 alen;
897
898 alen = dvb_ringbuffer_avail(&dev->tsout_rbuf);
899 alen -= alen % 188;
900
901 if (alen < len)
902 FillTSBuffer(buf + alen, len - alen, flags);
903 else
904 alen = len;
905 dvb_ringbuffer_read(&dev->tsout_rbuf, buf, alen);
906 if (flags & DF_SWAP32)
907 swap_buffer((u32 *)buf, alen);
908 wake_up_interruptible(&dev->tsout_rbuf.queue);
909 return buf;
910}
911
dae52d00
MB		 912
913static void set_transfer(struct ngene_channel *chan, int state)
914{
915 u8 control = 0, mode = 0, flags = 0;
916 struct ngene *dev = chan->dev;
917 int ret;
918
dae52d00
MB		 919 /*
920 printk(KERN_INFO DEVICE_NAME ": st %d\n", state);
921 msleep(100);
922 */
923
924 if (state) {
925 if (chan->running) {
926 printk(KERN_INFO DEVICE_NAME ": already running\n");
927 return;
928 }
929 } else {
930 if (!chan->running) {
931 printk(KERN_INFO DEVICE_NAME ": already stopped\n");
932 return;
933 }
934 }
935
936 if (dev->card_info->switch_ctrl)
937 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
938
939 if (state) {
940 spin_lock_irq(&chan->state_lock);
941
942 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
943 ngreadl(0x9310)); */
126cd4bc 944 dvb_ringbuffer_flush(&dev->tsout_rbuf);
dae52d00
MB		 945 control = 0x80;
946 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
947 chan->Capture1Length = 512 * 188;
948 mode = SMODE_TRANSPORT_STREAM;
949 }
950 if (chan->mode & NGENE_IO_TSOUT) {
951 chan->pBufferExchange = tsout_exchange;
952 /* 0x66666666 = 50MHz *2^33 /250MHz */
953 chan->AudioDTOValue = 0x66666666;
954 /* set_dto(chan, 38810700+1000); */
955 /* set_dto(chan, 19392658); */
956 }
957 if (chan->mode & NGENE_IO_TSIN)
958 chan->pBufferExchange = tsin_exchange;
959 /* ngwritel(0, 0x9310); */
960 spin_unlock_irq(&chan->state_lock);
961 } else
962 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
963 ngreadl(0x9310)); */
964
965 ret = ngene_command_stream_control(dev, chan->number,
966 control, mode, flags);
967 if (!ret)
968 chan->running = state;
969 else
970 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n",
971 state);
972 if (!state) {
973 spin_lock_irq(&chan->state_lock);
974 chan->pBufferExchange = 0;
126cd4bc 975 dvb_ringbuffer_flush(&dev->tsout_rbuf);
dae52d00
MB		 976 spin_unlock_irq(&chan->state_lock);
977 }
978}
979
980static int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed)
981{
982 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
983 struct ngene_channel *chan = dvbdmx->priv;
dae52d00
MB		 984
985 if (chan->users == 0) {
b1ec9532
OE		 986#ifdef COMMAND_TIMEOUT_WORKAROUND
987 if (!chan->running)
988#endif
989 set_transfer(chan, 1);
dae52d00
MB		 990 /* msleep(10); */
991 }
992
993 return ++chan->users;
994}
995
996static int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
997{
998 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
999 struct ngene_channel *chan = dvbdmx->priv;
dae52d00
MB		 1000
1001 if (--chan->users)
1002 return chan->users;
1003
b1ec9532 1004#ifndef COMMAND_TIMEOUT_WORKAROUND
dae52d00 1005 set_transfer(chan, 0);
b1ec9532 1006#endif
dae52d00
MB		 1007
1008 return 0;
1009}
1010
dae52d00 1011
dae52d00 1012
dae52d00
MB		 1013static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
1014 int (*start_feed)(struct dvb_demux_feed *),
1015 int (*stop_feed)(struct dvb_demux_feed *),
1016 void *priv)
1017{
1018 dvbdemux->priv = priv;
1019
1020 dvbdemux->filternum = 256;
1021 dvbdemux->feednum = 256;
1022 dvbdemux->start_feed = start_feed;
1023 dvbdemux->stop_feed = stop_feed;
1024 dvbdemux->write_to_decoder = 0;
1025 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
1026 DMX_SECTION_FILTERING |
1027 DMX_MEMORY_BASED_FILTERING);
1028 return dvb_dmx_init(dvbdemux);
1029}
1030
1031static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
1032 struct dvb_demux *dvbdemux,
1033 struct dmx_frontend *hw_frontend,
1034 struct dmx_frontend *mem_frontend,
1035 struct dvb_adapter *dvb_adapter)
1036{
1037 int ret;
1038
1039 dmxdev->filternum = 256;
1040 dmxdev->demux = &dvbdemux->dmx;
1041 dmxdev->capabilities = 0;
1042 ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
1043 if (ret < 0)
1044 return ret;
1045
1046 hw_frontend->source = DMX_FRONTEND_0;
1047 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
1048 mem_frontend->source = DMX_MEMORY_FE;
1049 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
1050 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
1051}
1052
dae52d00
MB		 1053
1054/****************************************************************************/
1055/* nGene hardware init and release functions ********************************/
1056/****************************************************************************/
1057
9fdd7976 1058static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
dae52d00
MB		 1059{
1060 struct SBufferHeader *Cur = rb->Head;
1061 u32 j;
1062
1063 if (!Cur)
1064 return;
1065
1066 for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
1067 if (Cur->Buffer1)
1068 pci_free_consistent(dev->pci_dev,
1069 rb->Buffer1Length,
1070 Cur->Buffer1,
1071 Cur->scList1->Address);
1072
1073 if (Cur->Buffer2)
1074 pci_free_consistent(dev->pci_dev,
1075 rb->Buffer2Length,
1076 Cur->Buffer2,
1077 Cur->scList2->Address);
1078 }
1079
1080 if (rb->SCListMem)
1081 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
1082 rb->SCListMem, rb->PASCListMem);
1083
1084 pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
1085}
1086
9fdd7976 1087static void free_idlebuffer(struct ngene *dev,
dae52d00
MB		 1088 struct SRingBufferDescriptor *rb,
1089 struct SRingBufferDescriptor *tb)
1090{
1091 int j;
1092 struct SBufferHeader *Cur = tb->Head;
1093
1094 if (!rb->Head)
1095 return;
1096 free_ringbuffer(dev, rb);
1097 for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
1098 Cur->Buffer2 = 0;
1099 Cur->scList2 = 0;
1100 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
1101 Cur->ngeneBuffer.Number_of_entries_2 = 0;
1102 }
1103}
1104
9fdd7976 1105static void free_common_buffers(struct ngene *dev)
dae52d00
MB		 1106{
1107 u32 i;
1108 struct ngene_channel *chan;
1109
1110 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1111 chan = &dev->channel[i];
1112 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
1113 free_ringbuffer(dev, &chan->RingBuffer);
1114 free_ringbuffer(dev, &chan->TSRingBuffer);
1115 }
1116
1117 if (dev->OverflowBuffer)
1118 pci_free_consistent(dev->pci_dev,
1119 OVERFLOW_BUFFER_SIZE,
1120 dev->OverflowBuffer, dev->PAOverflowBuffer);
1121
1122 if (dev->FWInterfaceBuffer)
1123 pci_free_consistent(dev->pci_dev,
1124 4096,
1125 dev->FWInterfaceBuffer,
1126 dev->PAFWInterfaceBuffer);
1127}
1128
1129/****************************************************************************/
1130/* Ring buffer handling *****************************************************/
1131/****************************************************************************/
1132
9fdd7976 1133static int create_ring_buffer(struct pci_dev *pci_dev,
dae52d00
MB		 1134 struct SRingBufferDescriptor *descr, u32 NumBuffers)
1135{
1136 dma_addr_t tmp;
1137 struct SBufferHeader *Head;
1138 u32 i;
1139 u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
1140 u64 PARingBufferHead;
1141 u64 PARingBufferCur;
1142 u64 PARingBufferNext;
1143 struct SBufferHeader *Cur, *Next;
1144
1145 descr->Head = 0;
1146 descr->MemSize = 0;
1147 descr->PAHead = 0;
1148 descr->NumBuffers = 0;
1149
1150 if (MemSize < 4096)
1151 MemSize = 4096;
1152
1153 Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
1154 PARingBufferHead = tmp;
1155
1156 if (!Head)
1157 return -ENOMEM;
1158
1159 memset(Head, 0, MemSize);
1160
1161 PARingBufferCur = PARingBufferHead;
1162 Cur = Head;
1163
1164 for (i = 0; i < NumBuffers - 1; i++) {
1165 Next = (struct SBufferHeader *)
1166 (((u8 *) Cur) + SIZEOF_SBufferHeader);
1167 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
1168 Cur->Next = Next;
1169 Cur->ngeneBuffer.Next = PARingBufferNext;
1170 Cur = Next;
1171 PARingBufferCur = PARingBufferNext;
1172 }
1173 /* Last Buffer points back to first one */
1174 Cur->Next = Head;
1175 Cur->ngeneBuffer.Next = PARingBufferHead;
1176
1177 descr->Head = Head;
1178 descr->MemSize = MemSize;
1179 descr->PAHead = PARingBufferHead;
1180 descr->NumBuffers = NumBuffers;
1181
1182 return 0;
1183}
1184
1185static int AllocateRingBuffers(struct pci_dev *pci_dev,
1186 dma_addr_t of,
1187 struct SRingBufferDescriptor *pRingBuffer,
1188 u32 Buffer1Length, u32 Buffer2Length)
1189{
1190 dma_addr_t tmp;
1191 u32 i, j;
1192 int status = 0;
1193 u32 SCListMemSize = pRingBuffer->NumBuffers
1194 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
1195 NUM_SCATTER_GATHER_ENTRIES)
1196 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1197
1198 u64 PASCListMem;
684688d8 1199 struct HW_SCATTER_GATHER_ELEMENT *SCListEntry;
dae52d00
MB		 1200 u64 PASCListEntry;
1201 struct SBufferHeader *Cur;
1202 void *SCListMem;
1203
1204 if (SCListMemSize < 4096)
1205 SCListMemSize = 4096;
1206
1207 SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
1208
1209 PASCListMem = tmp;
1210 if (SCListMem == NULL)
1211 return -ENOMEM;
1212
1213 memset(SCListMem, 0, SCListMemSize);
1214
1215 pRingBuffer->SCListMem = SCListMem;
1216 pRingBuffer->PASCListMem = PASCListMem;
1217 pRingBuffer->SCListMemSize = SCListMemSize;
1218 pRingBuffer->Buffer1Length = Buffer1Length;
1219 pRingBuffer->Buffer2Length = Buffer2Length;
1220
684688d8 1221 SCListEntry = SCListMem;
dae52d00
MB		 1222 PASCListEntry = PASCListMem;
1223 Cur = pRingBuffer->Head;
1224
1225 for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
1226 u64 PABuffer;
1227
1228 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
1229 &tmp);
1230 PABuffer = tmp;
1231
1232 if (Buffer == NULL)
1233 return -ENOMEM;
1234
1235 Cur->Buffer1 = Buffer;
1236
1237 SCListEntry->Address = PABuffer;
1238 SCListEntry->Length = Buffer1Length;
1239
1240 Cur->scList1 = SCListEntry;
1241 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
1242 Cur->ngeneBuffer.Number_of_entries_1 =
1243 NUM_SCATTER_GATHER_ENTRIES;
1244
1245 SCListEntry += 1;
1246 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1247
1248#if NUM_SCATTER_GATHER_ENTRIES > 1
1249 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
1250 SCListEntry->Address = of;
1251 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1252 SCListEntry += 1;
1253 PASCListEntry +=
1254 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1255 }
1256#endif
1257
1258 if (!Buffer2Length)
1259 continue;
1260
1261 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
1262 PABuffer = tmp;
1263
1264 if (Buffer == NULL)
1265 return -ENOMEM;
1266
1267 Cur->Buffer2 = Buffer;
1268
1269 SCListEntry->Address = PABuffer;
1270 SCListEntry->Length = Buffer2Length;
1271
1272 Cur->scList2 = SCListEntry;
1273 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
1274 Cur->ngeneBuffer.Number_of_entries_2 =
1275 NUM_SCATTER_GATHER_ENTRIES;
1276
1277 SCListEntry += 1;
1278 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1279
1280#if NUM_SCATTER_GATHER_ENTRIES > 1
1281 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
1282 SCListEntry->Address = of;
1283 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1284 SCListEntry += 1;
1285 PASCListEntry +=
1286 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1287 }
1288#endif
1289
1290 }
1291
1292 return status;
1293}
1294
1295static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
1296 struct SRingBufferDescriptor *pRingBuffer)
1297{
1298 int status = 0;
1299
1300 /* Copy pointer to scatter gather list in TSRingbuffer
1301 structure for buffer 2
1302 Load number of buffer
1303 */
1304 u32 n = pRingBuffer->NumBuffers;
1305
1306 /* Point to first buffer entry */
1307 struct SBufferHeader *Cur = pRingBuffer->Head;
1308 int i;
1309 /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
1310 for (i = 0; i < n; i++) {
1311 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
1312 Cur->scList2 = pIdleBuffer->Head->scList1;
1313 Cur->ngeneBuffer.Address_of_first_entry_2 =
1314 pIdleBuffer->Head->ngeneBuffer.
1315 Address_of_first_entry_1;
1316 Cur->ngeneBuffer.Number_of_entries_2 =
1317 pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
1318 Cur = Cur->Next;
1319 }
1320 return status;
1321}
1322
1323static u32 RingBufferSizes[MAX_STREAM] = {
1324 RING_SIZE_VIDEO,
1325 RING_SIZE_VIDEO,
1326 RING_SIZE_AUDIO,
1327 RING_SIZE_AUDIO,
1328 RING_SIZE_AUDIO,
1329};
1330
1331static u32 Buffer1Sizes[MAX_STREAM] = {
1332 MAX_VIDEO_BUFFER_SIZE,
1333 MAX_VIDEO_BUFFER_SIZE,
1334 MAX_AUDIO_BUFFER_SIZE,
1335 MAX_AUDIO_BUFFER_SIZE,
1336 MAX_AUDIO_BUFFER_SIZE
1337};
1338
1339static u32 Buffer2Sizes[MAX_STREAM] = {
1340 MAX_VBI_BUFFER_SIZE,
1341 MAX_VBI_BUFFER_SIZE,
1342 0,
1343 0,
1344 0
1345};
1346
dae52d00
MB		 1347
1348static int AllocCommonBuffers(struct ngene *dev)
1349{
1350 int status = 0, i;
1351
1352 dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
1353 &dev->PAFWInterfaceBuffer);
1354 if (!dev->FWInterfaceBuffer)
1355 return -ENOMEM;
1356 dev->hosttongene = dev->FWInterfaceBuffer;
1357 dev->ngenetohost = dev->FWInterfaceBuffer + 256;
1358 dev->EventBuffer = dev->FWInterfaceBuffer + 512;
1359
1360 dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev,
1361 OVERFLOW_BUFFER_SIZE,
1362 &dev->PAOverflowBuffer);
1363 if (!dev->OverflowBuffer)
1364 return -ENOMEM;
1365 memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE);
1366
1367 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1368 int type = dev->card_info->io_type[i];
1369
1370 dev->channel[i].State = KSSTATE_STOP;
1371
1372 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
1373 status = create_ring_buffer(dev->pci_dev,
1374 &dev->channel[i].RingBuffer,
1375 RingBufferSizes[i]);
1376 if (status < 0)
1377 break;
1378
1379 if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
1380 status = AllocateRingBuffers(dev->pci_dev,
1381 dev->
1382 PAOverflowBuffer,
1383 &dev->channel[i].
1384 RingBuffer,
1385 Buffer1Sizes[i],
1386 Buffer2Sizes[i]);
1387 if (status < 0)
1388 break;
1389 } else if (type & NGENE_IO_HDTV) {
1390 status = AllocateRingBuffers(dev->pci_dev,
1391 dev->
1392 PAOverflowBuffer,
1393 &dev->channel[i].
1394 RingBuffer,
1395 MAX_HDTV_BUFFER_SIZE,
1396 0);
1397 if (status < 0)
1398 break;
1399 }
1400 }
1401
1402 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1403
1404 status = create_ring_buffer(dev->pci_dev,
1405 &dev->channel[i].
1406 TSRingBuffer, RING_SIZE_TS);
1407 if (status < 0)
1408 break;
1409
1410 status = AllocateRingBuffers(dev->pci_dev,
1411 dev->PAOverflowBuffer,
1412 &dev->channel[i].
1413 TSRingBuffer,
1414 MAX_TS_BUFFER_SIZE, 0);
1415 if (status)
1416 break;
1417 }
1418
1419 if (type & NGENE_IO_TSOUT) {
1420 status = create_ring_buffer(dev->pci_dev,
1421 &dev->channel[i].
1422 TSIdleBuffer, 1);
1423 if (status < 0)
1424 break;
1425 status = AllocateRingBuffers(dev->pci_dev,
1426 dev->PAOverflowBuffer,
1427 &dev->channel[i].
1428 TSIdleBuffer,
1429 MAX_TS_BUFFER_SIZE, 0);
1430 if (status)
1431 break;
1432 FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
1433 &dev->channel[i].TSRingBuffer);
1434 }
1435 }
1436 return status;
1437}
1438
1439static void ngene_release_buffers(struct ngene *dev)
1440{
1441 if (dev->iomem)
1442 iounmap(dev->iomem);
1443 free_common_buffers(dev);
1444 vfree(dev->tsout_buf);
1445 vfree(dev->ain_buf);
1446 vfree(dev->vin_buf);
1447 vfree(dev);
1448}
1449
1450static int ngene_get_buffers(struct ngene *dev)
1451{
1452 if (AllocCommonBuffers(dev))
1453 return -ENOMEM;
1454 if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
1455 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
1456 if (!dev->tsout_buf)
1457 return -ENOMEM;
1458 dvb_ringbuffer_init(&dev->tsout_rbuf,
1459 dev->tsout_buf, TSOUT_BUF_SIZE);
1460 }
1461 if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1462 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1463 if (!dev->ain_buf)
1464 return -ENOMEM;
1465 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
1466 }
1467 if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
1468 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
1469 if (!dev->vin_buf)
1470 return -ENOMEM;
1471 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
1472 }
1473 dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
1474 pci_resource_len(dev->pci_dev, 0));
1475 if (!dev->iomem)
1476 return -ENOMEM;
1477
1478 return 0;
1479}
1480
1481static void ngene_init(struct ngene *dev)
1482{
1483 int i;
1484
1485 tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
1486
1487 memset_io(dev->iomem + 0xc000, 0x00, 0x220);
1488 memset_io(dev->iomem + 0xc400, 0x00, 0x100);
1489
1490 for (i = 0; i < MAX_STREAM; i++) {
1491 dev->channel[i].dev = dev;
1492 dev->channel[i].number = i;
1493 }
1494
1495 dev->fw_interface_version = 0;
1496
1497 ngwritel(0, NGENE_INT_ENABLE);
1498
1499 dev->icounts = ngreadl(NGENE_INT_COUNTS);
1500
1501 dev->device_version = ngreadl(DEV_VER) & 0x0f;
1502 printk(KERN_INFO DEVICE_NAME ": Device version %d\n",
1503 dev->device_version);
1504}
1505
1506static int ngene_load_firm(struct ngene *dev)
1507{
1508 u32 size;
1509 const struct firmware *fw = NULL;
1510 u8 *ngene_fw;
1511 char *fw_name;
1512 int err, version;
1513
1514 version = dev->card_info->fw_version;
1515
1516 switch (version) {
1517 default:
1518 case 15:
1519 version = 15;
0027ebb7 1520 size = 23466;
dae52d00
MB		 1521 fw_name = "ngene_15.fw";
1522 break;
1523 case 16:
0027ebb7 1524 size = 23498;
dae52d00
MB		 1525 fw_name = "ngene_16.fw";
1526 break;
1527 case 17:
0027ebb7 1528 size = 24446;
dae52d00
MB		 1529 fw_name = "ngene_17.fw";
1530 break;
1531 }
dae52d00 1532
dae52d00
MB		 1533 if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
1534 printk(KERN_ERR DEVICE_NAME
0027ebb7 1535 ": Could not load firmware file %s.\n", fw_name);
dae52d00
MB		 1536 printk(KERN_INFO DEVICE_NAME
1537 ": Copy %s to your hotplug directory!\n", fw_name);
1538 return -1;
1539 }
0027ebb7
OE		 1540 if (size != fw->size) {
1541 printk(KERN_ERR DEVICE_NAME
1542 ": Firmware %s has invalid size!", fw_name);
1543 err = -1;
1544 } else {
1545 printk(KERN_INFO DEVICE_NAME
1546 ": Loading firmware file %s.\n", fw_name);
1547 ngene_fw = (u8 *) fw->data;
1548 err = ngene_command_load_firmware(dev, ngene_fw, size);
1549 }
1550
dae52d00 1551 release_firmware(fw);
0027ebb7 1552
dae52d00
MB		 1553 return err;
1554}
1555
1556static void ngene_stop(struct ngene *dev)
1557{
1558 down(&dev->cmd_mutex);
1559 i2c_del_adapter(&(dev->channel[0].i2c_adapter));
1560 i2c_del_adapter(&(dev->channel[1].i2c_adapter));
1561 ngwritel(0, NGENE_INT_ENABLE);
1562 ngwritel(0, NGENE_COMMAND);
1563 ngwritel(0, NGENE_COMMAND_HI);
1564 ngwritel(0, NGENE_STATUS);
1565 ngwritel(0, NGENE_STATUS_HI);
1566 ngwritel(0, NGENE_EVENT);
1567 ngwritel(0, NGENE_EVENT_HI);
1568 free_irq(dev->pci_dev->irq, dev);
1569}
1570
1571static int ngene_start(struct ngene *dev)
1572{
1573 int stat;
1574 int i;
1575
1576 pci_set_master(dev->pci_dev);
1577 ngene_init(dev);
1578
1579 stat = request_irq(dev->pci_dev->irq, irq_handler,
1580 IRQF_SHARED, "nGene",
1581 (void *)dev);
1582 if (stat < 0)
1583 return stat;
1584
1585 init_waitqueue_head(&dev->cmd_wq);
1586 init_waitqueue_head(&dev->tx_wq);
1587 init_waitqueue_head(&dev->rx_wq);
1588 sema_init(&dev->cmd_mutex, 1);
1589 sema_init(&dev->stream_mutex, 1);
1590 sema_init(&dev->pll_mutex, 1);
1591 sema_init(&dev->i2c_switch_mutex, 1);
1592 spin_lock_init(&dev->cmd_lock);
1593 for (i = 0; i < MAX_STREAM; i++)
1594 spin_lock_init(&dev->channel[i].state_lock);
1595 ngwritel(1, TIMESTAMPS);
1596
1597 ngwritel(1, NGENE_INT_ENABLE);
1598
1599 stat = ngene_load_firm(dev);
1600 if (stat < 0)
1601 goto fail;
1602
1603 stat = ngene_i2c_init(dev, 0);
1604 if (stat < 0)
1605 goto fail;
1606
1607 stat = ngene_i2c_init(dev, 1);
1608 if (stat < 0)
1609 goto fail;
1610
1611 if (dev->card_info->fw_version == 17) {
684688d8
OE		 1612 u8 tsin4_config[6] = {
1613 3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0};
1614 u8 default_config[6] = {
1615 4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0};
dae52d00
MB		 1616 u8 *bconf = default_config;
1617
1618 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1619 bconf = tsin4_config;
44cdd064 1620 dprintk(KERN_DEBUG DEVICE_NAME ": FW 17 buffer config\n");
dae52d00
MB		 1621 stat = ngene_command_config_free_buf(dev, bconf);
1622 } else {
1623 int bconf = BUFFER_CONFIG_4422;
dae52d00
MB		 1624 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1625 bconf = BUFFER_CONFIG_3333;
1626 stat = ngene_command_config_buf(dev, bconf);
1627 }
dae52d00
MB		 1628 return stat;
1629fail:
1630 ngwritel(0, NGENE_INT_ENABLE);
1631 free_irq(dev->pci_dev->irq, dev);
1632 return stat;
1633}
1634
83f3c715
OE		 1635
1636
dae52d00 1637/****************************************************************************/
83f3c715 1638/* Switch control (I2C gates, etc.) *****************************************/
dae52d00
MB		 1639/****************************************************************************/
1640
dae52d00 1641
83f3c715
OE		 1642/****************************************************************************/
1643/* Demod/tuner attachment ***************************************************/
1644/****************************************************************************/
dae52d00 1645
8bba2607
MB		 1646static int tuner_attach_stv6110(struct ngene_channel *chan)
1647{
1648 struct stv090x_config *feconf = (struct stv090x_config *)
1649 chan->dev->card_info->fe_config[chan->number];
1650 struct stv6110x_config *tunerconf = (struct stv6110x_config *)
1651 chan->dev->card_info->tuner_config[chan->number];
1652 struct stv6110x_devctl *ctl;
1653
1654 ctl = dvb_attach(stv6110x_attach, chan->fe, tunerconf,
1655 &chan->i2c_adapter);
1656 if (ctl == NULL) {
1657 printk(KERN_ERR DEVICE_NAME ": No STV6110X found!\n");
1658 return -ENODEV;
1659 }
1660
1661 feconf->tuner_init = ctl->tuner_init;
1662 feconf->tuner_set_mode = ctl->tuner_set_mode;
1663 feconf->tuner_set_frequency = ctl->tuner_set_frequency;
1664 feconf->tuner_get_frequency = ctl->tuner_get_frequency;
1665 feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
1666 feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
1667 feconf->tuner_set_bbgain = ctl->tuner_set_bbgain;
1668 feconf->tuner_get_bbgain = ctl->tuner_get_bbgain;
1669 feconf->tuner_set_refclk = ctl->tuner_set_refclk;
1670 feconf->tuner_get_status = ctl->tuner_get_status;
1671
1672 return 0;
1673}
1674
1675
1676static int demod_attach_stv0900(struct ngene_channel *chan)
1677{
1678 struct stv090x_config *feconf = (struct stv090x_config *)
1679 chan->dev->card_info->fe_config[chan->number];
1680
1681 chan->fe = dvb_attach(stv090x_attach,
1682 feconf,
1683 &chan->i2c_adapter,
1684 chan->number == 0 ? STV090x_DEMODULATOR_0 :
1685 STV090x_DEMODULATOR_1);
1686 if (chan->fe == NULL) {
1687 printk(KERN_ERR DEVICE_NAME ": No STV0900 found!\n");
1688 return -ENODEV;
1689 }
1690
1691 if (!dvb_attach(lnbh24_attach, chan->fe, &chan->i2c_adapter, 0,
1692 0, chan->dev->card_info->lnb[chan->number])) {
1693 printk(KERN_ERR DEVICE_NAME ": No LNBH24 found!\n");
1694 dvb_frontend_detach(chan->fe);
1695 return -ENODEV;
1696 }
1697
1698 return 0;
1699}
dae52d00 1700
83f3c715
OE		 1701/****************************************************************************/
1702/****************************************************************************/
1703/****************************************************************************/
1704
1705static void release_channel(struct ngene_channel *chan)
dae52d00
MB		 1706{
1707 struct dvb_demux *dvbdemux = &chan->demux;
1708 struct ngene *dev = chan->dev;
1709 struct ngene_info *ni = dev->card_info;
1710 int io = ni->io_type[chan->number];
1711
b1ec9532
OE		 1712#ifdef COMMAND_TIMEOUT_WORKAROUND
1713 if (chan->running)
1714 set_transfer(chan, 0);
1715#endif
1716
dae52d00
MB		 1717 tasklet_kill(&chan->demux_tasklet);
1718
1719 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
dae52d00
MB		 1720 if (chan->fe) {
1721 dvb_unregister_frontend(chan->fe);
dc35c9ae 1722 dvb_frontend_detach(chan->fe);
dae52d00
MB		 1723 chan->fe = 0;
1724 }
1725 dvbdemux->dmx.close(&dvbdemux->dmx);
1726 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1727 &chan->hw_frontend);
1728 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1729 &chan->mem_frontend);
1730 dvb_dmxdev_release(&chan->dmxdev);
1731 dvb_dmx_release(&chan->demux);
cf1b12f2
MB		 1732
1733 if (chan->number == 0 || !one_adapter)
1734 dvb_unregister_adapter(&dev->adapter[chan->number]);
dae52d00 1735 }
dae52d00
MB		 1736}
1737
1738static int init_channel(struct ngene_channel *chan)
1739{
1740 int ret = 0, nr = chan->number;
948a1195 1741 struct dvb_adapter *adapter = NULL;
dae52d00
MB		 1742 struct dvb_demux *dvbdemux = &chan->demux;
1743 struct ngene *dev = chan->dev;
1744 struct ngene_info *ni = dev->card_info;
1745 int io = ni->io_type[nr];
1746
1747 tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
1748 chan->users = 0;
1749 chan->type = io;
1750 chan->mode = chan->type; /* for now only one mode */
1751
1752 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1753 if (nr >= STREAM_AUDIOIN1)
1754 chan->DataFormatFlags = DF_SWAP32;
cf1b12f2
MB		 1755 if (nr == 0 || !one_adapter) {
1756 adapter = &dev->adapter[nr];
1757 ret = dvb_register_adapter(adapter, "nGene",
1758 THIS_MODULE,
1759 &chan->dev->pci_dev->dev,
1760 adapter_nr);
1761 if (ret < 0)
1762 return ret;
1763 } else {
1764 adapter = &dev->adapter[0];
1765 }
1766
dae52d00
MB		 1767 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1768 ngene_start_feed,
1769 ngene_stop_feed, chan);
1770 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1771 &chan->hw_frontend,
1772 &chan->mem_frontend, adapter);
dae52d00
MB		 1773 }
1774
1775 if (io & NGENE_IO_TSIN) {
1776 chan->fe = NULL;
1777 if (ni->demod_attach[nr])
1778 ni->demod_attach[nr](chan);
1779 if (chan->fe) {
1780 if (dvb_register_frontend(adapter, chan->fe) < 0) {
1781 if (chan->fe->ops.release)
1782 chan->fe->ops.release(chan->fe);
1783 chan->fe = NULL;
1784 }
1785 }
1786 if (chan->fe && ni->tuner_attach[nr])
1787 if (ni->tuner_attach[nr] (chan) < 0) {
1788 printk(KERN_ERR DEVICE_NAME
1789 ": Tuner attach failed on channel %d!\n",
1790 nr);
1791 }
1792 }
dae52d00
MB		 1793 return ret;
1794}
1795
1796static int init_channels(struct ngene *dev)
1797{
1798 int i, j;
1799
1800 for (i = 0; i < MAX_STREAM; i++) {
1801 if (init_channel(&dev->channel[i]) < 0) {
cf1b12f2 1802 for (j = i - 1; j >= 0; j--)
dae52d00
MB		 1803 release_channel(&dev->channel[j]);
1804 return -1;
1805 }
1806 }
1807 return 0;
1808}
1809
1810/****************************************************************************/
1811/* device probe/remove calls ************************************************/
1812/****************************************************************************/
1813
1814static void __devexit ngene_remove(struct pci_dev *pdev)
1815{
1816 struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev);
1817 int i;
1818
1819 tasklet_kill(&dev->event_tasklet);
cf1b12f2 1820 for (i = MAX_STREAM - 1; i >= 0; i--)
dae52d00 1821 release_channel(&dev->channel[i]);
dae52d00
MB		 1822 ngene_stop(dev);
1823 ngene_release_buffers(dev);
1824 pci_set_drvdata(pdev, 0);
1825 pci_disable_device(pdev);
1826}
1827
1828static int __devinit ngene_probe(struct pci_dev *pci_dev,
1829 const struct pci_device_id *id)
1830{
1831 struct ngene *dev;
1832 int stat = 0;
1833
1834 if (pci_enable_device(pci_dev) < 0)
1835 return -ENODEV;
1836
1837 dev = vmalloc(sizeof(struct ngene));
dc35c9ae
RP		 1838 if (dev == NULL) {
1839 stat = -ENOMEM;
1840 goto fail0;
1841 }
dae52d00
MB		 1842 memset(dev, 0, sizeof(struct ngene));
1843
1844 dev->pci_dev = pci_dev;
1845 dev->card_info = (struct ngene_info *)id->driver_data;
1846 printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name);
1847
1848 pci_set_drvdata(pci_dev, dev);
1849
1850 /* Alloc buffers and start nGene */
1851 stat = ngene_get_buffers(dev);
1852 if (stat < 0)
1853 goto fail1;
1854 stat = ngene_start(dev);
1855 if (stat < 0)
1856 goto fail1;
1857
1858 dev->i2c_current_bus = -1;
dae52d00
MB		 1859
1860 /* Register DVB adapters and devices for both channels */
dae52d00
MB		 1861 if (init_channels(dev) < 0)
1862 goto fail2;
1863
1864 return 0;
1865
1866fail2:
1867 ngene_stop(dev);
1868fail1:
1869 ngene_release_buffers(dev);
dc35c9ae
RP		 1870fail0:
1871 pci_disable_device(pci_dev);
dae52d00
MB		 1872 pci_set_drvdata(pci_dev, 0);
1873 return stat;
1874}
1875
1876/****************************************************************************/
1877/* Card configs *************************************************************/
1878/****************************************************************************/
1879
e890e7c0 1880static struct stv090x_config fe_cineS2 = {
8bba2607
MB		 1881 .device = STV0900,
1882 .demod_mode = STV090x_DUAL,
1883 .clk_mode = STV090x_CLK_EXT,
1884
1885 .xtal = 27000000,
1886 .address = 0x68,
8bba2607
MB		 1887
1888 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
1889 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
1890
1891 .repeater_level = STV090x_RPTLEVEL_16,
1892
589816c6
OE		 1893 .adc1_range = STV090x_ADC_1Vpp,
1894 .adc2_range = STV090x_ADC_1Vpp,
1895
8bba2607 1896 .diseqc_envelope_mode = true,
8bba2607
MB		 1897};
1898
e890e7c0 1899static struct stv6110x_config tuner_cineS2_0 = {
8bba2607
MB		 1900 .addr = 0x60,
1901 .refclk = 27000000,
83e74554 1902 .clk_div = 1,
8bba2607
MB		 1903};
1904
e890e7c0 1905static struct stv6110x_config tuner_cineS2_1 = {
8bba2607
MB		 1906 .addr = 0x63,
1907 .refclk = 27000000,
83e74554 1908 .clk_div = 1,
8bba2607
MB		 1909};
1910
e890e7c0 1911static struct ngene_info ngene_info_cineS2 = {
8bba2607 1912 .type = NGENE_SIDEWINDER,
e890e7c0 1913 .name = "Linux4Media cineS2 DVB-S2 Twin Tuner",
8bba2607
MB		 1914 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN},
1915 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900},
1916 .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110},
e890e7c0
OE		 1917 .fe_config = {&fe_cineS2, &fe_cineS2},
1918 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1},
8bba2607
MB		 1919 .lnb = {0x0b, 0x08},
1920 .tsf = {3, 3},
b1ec9532 1921 .fw_version = 15,
8bba2607
MB		 1922};
1923
edad22a7
MB		 1924static struct ngene_info ngene_info_satixs2 = {
1925 .type = NGENE_SIDEWINDER,
1926 .name = "Mystique SaTiX-S2 Dual",
1927 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN},
1928 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900},
1929 .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110},
e890e7c0
OE		 1930 .fe_config = {&fe_cineS2, &fe_cineS2},
1931 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1},
edad22a7
MB		 1932 .lnb = {0x0b, 0x08},
1933 .tsf = {3, 3},
b1ec9532 1934 .fw_version = 15,
edad22a7
MB		 1935};
1936
8bba2607
MB		 1937/****************************************************************************/
1938
dae52d00
MB		 1939
1940
1941/****************************************************************************/
edad22a7 1942/* PCI Subsystem ID *********************************************************/
dae52d00
MB		 1943/****************************************************************************/
1944
1945#define NGENE_ID(_subvend, _subdev, _driverdata) { \
1946 .vendor = NGENE_VID, .device = NGENE_PID, \
1947 .subvendor = _subvend, .subdevice = _subdev, \
1948 .driver_data = (unsigned long) &_driverdata }
1949
1950/****************************************************************************/
1951
1952static const struct pci_device_id ngene_id_tbl[] __devinitdata = {
e890e7c0
OE		 1953 NGENE_ID(0x18c3, 0xabc3, ngene_info_cineS2),
1954 NGENE_ID(0x18c3, 0xabc4, ngene_info_cineS2),
edad22a7 1955 NGENE_ID(0x18c3, 0xdb01, ngene_info_satixs2),
dae52d00
MB		 1956 {0}
1957};
8bba2607 1958MODULE_DEVICE_TABLE(pci, ngene_id_tbl);
dae52d00
MB		 1959
1960/****************************************************************************/
1961/* Init/Exit ****************************************************************/
1962/****************************************************************************/
1963
1964static pci_ers_result_t ngene_error_detected(struct pci_dev *dev,
1965 enum pci_channel_state state)
1966{
1967 printk(KERN_ERR DEVICE_NAME ": PCI error\n");
1968 if (state == pci_channel_io_perm_failure)
1969 return PCI_ERS_RESULT_DISCONNECT;
1970 if (state == pci_channel_io_frozen)
1971 return PCI_ERS_RESULT_NEED_RESET;
1972 return PCI_ERS_RESULT_CAN_RECOVER;
1973}
1974
1975static pci_ers_result_t ngene_link_reset(struct pci_dev *dev)
1976{
1977 printk(KERN_INFO DEVICE_NAME ": link reset\n");
1978 return 0;
1979}
1980
1981static pci_ers_result_t ngene_slot_reset(struct pci_dev *dev)
1982{
1983 printk(KERN_INFO DEVICE_NAME ": slot reset\n");
1984 return 0;
1985}
1986
1987static void ngene_resume(struct pci_dev *dev)
1988{
1989 printk(KERN_INFO DEVICE_NAME ": resume\n");
1990}
1991
1992static struct pci_error_handlers ngene_errors = {
1993 .error_detected = ngene_error_detected,
1994 .link_reset = ngene_link_reset,
1995 .slot_reset = ngene_slot_reset,
1996 .resume = ngene_resume,
1997};
1998
1999static struct pci_driver ngene_pci_driver = {
2000 .name = "ngene",
2001 .id_table = ngene_id_tbl,
2002 .probe = ngene_probe,
dc35c9ae 2003 .remove = __devexit_p(ngene_remove),
dae52d00
MB		 2004 .err_handler = &ngene_errors,
2005};
2006
2007static __init int module_init_ngene(void)
2008{
2009 printk(KERN_INFO
2010 "nGene PCIE bridge driver, Copyright (C) 2005-2007 Micronas\n");
2011 return pci_register_driver(&ngene_pci_driver);
2012}
2013
2014static __exit void module_exit_ngene(void)
2015{
2016 pci_unregister_driver(&ngene_pci_driver);
2017}
2018
2019module_init(module_init_ngene);
2020module_exit(module_exit_ngene);
2021
2022MODULE_DESCRIPTION("nGene");
2023MODULE_AUTHOR("Micronas, Ralph Metzler, Manfred Voelkel");
2024MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)