Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
8 | * | |
9 | * Authors: | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * Yaniv Kamay <yaniv@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include "kvm.h" | |
e7d5d76c | 19 | #include "x86_emulate.h" |
85f455f7 | 20 | #include "irq.h" |
6aa8b732 | 21 | #include "vmx.h" |
e495606d AK |
22 | #include "segment_descriptor.h" |
23 | ||
6aa8b732 | 24 | #include <linux/module.h> |
9d8f549d | 25 | #include <linux/kernel.h> |
6aa8b732 AK |
26 | #include <linux/mm.h> |
27 | #include <linux/highmem.h> | |
07031e14 | 28 | #include <linux/profile.h> |
e8edc6e0 | 29 | #include <linux/sched.h> |
e495606d | 30 | |
6aa8b732 | 31 | #include <asm/io.h> |
3b3be0d1 | 32 | #include <asm/desc.h> |
6aa8b732 | 33 | |
6aa8b732 AK |
34 | MODULE_AUTHOR("Qumranet"); |
35 | MODULE_LICENSE("GPL"); | |
36 | ||
a2fa3e9f GH |
37 | struct vmcs { |
38 | u32 revision_id; | |
39 | u32 abort; | |
40 | char data[0]; | |
41 | }; | |
42 | ||
43 | struct vcpu_vmx { | |
fb3f0f51 | 44 | struct kvm_vcpu vcpu; |
a2fa3e9f GH |
45 | int launched; |
46 | struct kvm_msr_entry *guest_msrs; | |
47 | struct kvm_msr_entry *host_msrs; | |
48 | int nmsrs; | |
49 | int save_nmsrs; | |
50 | int msr_offset_efer; | |
51 | #ifdef CONFIG_X86_64 | |
52 | int msr_offset_kernel_gs_base; | |
53 | #endif | |
54 | struct vmcs *vmcs; | |
55 | struct { | |
56 | int loaded; | |
57 | u16 fs_sel, gs_sel, ldt_sel; | |
152d3f2f LV |
58 | int gs_ldt_reload_needed; |
59 | int fs_reload_needed; | |
a2fa3e9f GH |
60 | }host_state; |
61 | ||
62 | }; | |
63 | ||
64 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) | |
65 | { | |
fb3f0f51 | 66 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
67 | } |
68 | ||
75880a01 AK |
69 | static int init_rmode_tss(struct kvm *kvm); |
70 | ||
6aa8b732 AK |
71 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
72 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
73 | ||
fdef3ad1 HQ |
74 | static struct page *vmx_io_bitmap_a; |
75 | static struct page *vmx_io_bitmap_b; | |
76 | ||
2cc51560 | 77 | #define EFER_SAVE_RESTORE_BITS ((u64)EFER_SCE) |
6aa8b732 | 78 | |
1c3d14fe | 79 | static struct vmcs_config { |
6aa8b732 AK |
80 | int size; |
81 | int order; | |
82 | u32 revision_id; | |
1c3d14fe YS |
83 | u32 pin_based_exec_ctrl; |
84 | u32 cpu_based_exec_ctrl; | |
85 | u32 vmexit_ctrl; | |
86 | u32 vmentry_ctrl; | |
87 | } vmcs_config; | |
6aa8b732 AK |
88 | |
89 | #define VMX_SEGMENT_FIELD(seg) \ | |
90 | [VCPU_SREG_##seg] = { \ | |
91 | .selector = GUEST_##seg##_SELECTOR, \ | |
92 | .base = GUEST_##seg##_BASE, \ | |
93 | .limit = GUEST_##seg##_LIMIT, \ | |
94 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
95 | } | |
96 | ||
97 | static struct kvm_vmx_segment_field { | |
98 | unsigned selector; | |
99 | unsigned base; | |
100 | unsigned limit; | |
101 | unsigned ar_bytes; | |
102 | } kvm_vmx_segment_fields[] = { | |
103 | VMX_SEGMENT_FIELD(CS), | |
104 | VMX_SEGMENT_FIELD(DS), | |
105 | VMX_SEGMENT_FIELD(ES), | |
106 | VMX_SEGMENT_FIELD(FS), | |
107 | VMX_SEGMENT_FIELD(GS), | |
108 | VMX_SEGMENT_FIELD(SS), | |
109 | VMX_SEGMENT_FIELD(TR), | |
110 | VMX_SEGMENT_FIELD(LDTR), | |
111 | }; | |
112 | ||
4d56c8a7 AK |
113 | /* |
114 | * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it | |
115 | * away by decrementing the array size. | |
116 | */ | |
6aa8b732 | 117 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 118 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
119 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE, |
120 | #endif | |
121 | MSR_EFER, MSR_K6_STAR, | |
122 | }; | |
9d8f549d | 123 | #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) |
6aa8b732 | 124 | |
a2fa3e9f GH |
125 | static void load_msrs(struct kvm_msr_entry *e, int n) |
126 | { | |
127 | int i; | |
128 | ||
129 | for (i = 0; i < n; ++i) | |
130 | wrmsrl(e[i].index, e[i].data); | |
131 | } | |
132 | ||
133 | static void save_msrs(struct kvm_msr_entry *e, int n) | |
134 | { | |
135 | int i; | |
136 | ||
137 | for (i = 0; i < n; ++i) | |
138 | rdmsrl(e[i].index, e[i].data); | |
139 | } | |
140 | ||
141 | static inline u64 msr_efer_save_restore_bits(struct kvm_msr_entry msr) | |
2cc51560 ED |
142 | { |
143 | return (u64)msr.data & EFER_SAVE_RESTORE_BITS; | |
144 | } | |
145 | ||
8b9cf98c | 146 | static inline int msr_efer_need_save_restore(struct vcpu_vmx *vmx) |
2cc51560 | 147 | { |
a2fa3e9f GH |
148 | int efer_offset = vmx->msr_offset_efer; |
149 | return msr_efer_save_restore_bits(vmx->host_msrs[efer_offset]) != | |
150 | msr_efer_save_restore_bits(vmx->guest_msrs[efer_offset]); | |
2cc51560 ED |
151 | } |
152 | ||
6aa8b732 AK |
153 | static inline int is_page_fault(u32 intr_info) |
154 | { | |
155 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
156 | INTR_INFO_VALID_MASK)) == | |
157 | (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); | |
158 | } | |
159 | ||
2ab455cc AL |
160 | static inline int is_no_device(u32 intr_info) |
161 | { | |
162 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
163 | INTR_INFO_VALID_MASK)) == | |
164 | (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); | |
165 | } | |
166 | ||
6aa8b732 AK |
167 | static inline int is_external_interrupt(u32 intr_info) |
168 | { | |
169 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
170 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
171 | } | |
172 | ||
8b9cf98c | 173 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
174 | { |
175 | int i; | |
176 | ||
a2fa3e9f GH |
177 | for (i = 0; i < vmx->nmsrs; ++i) |
178 | if (vmx->guest_msrs[i].index == msr) | |
a75beee6 ED |
179 | return i; |
180 | return -1; | |
181 | } | |
182 | ||
8b9cf98c | 183 | static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
184 | { |
185 | int i; | |
186 | ||
8b9cf98c | 187 | i = __find_msr_index(vmx, msr); |
a75beee6 | 188 | if (i >= 0) |
a2fa3e9f | 189 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 190 | return NULL; |
7725f0ba AK |
191 | } |
192 | ||
6aa8b732 AK |
193 | static void vmcs_clear(struct vmcs *vmcs) |
194 | { | |
195 | u64 phys_addr = __pa(vmcs); | |
196 | u8 error; | |
197 | ||
198 | asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0" | |
199 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) | |
200 | : "cc", "memory"); | |
201 | if (error) | |
202 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
203 | vmcs, phys_addr); | |
204 | } | |
205 | ||
206 | static void __vcpu_clear(void *arg) | |
207 | { | |
8b9cf98c | 208 | struct vcpu_vmx *vmx = arg; |
d3b2c338 | 209 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 210 | |
8b9cf98c | 211 | if (vmx->vcpu.cpu == cpu) |
a2fa3e9f GH |
212 | vmcs_clear(vmx->vmcs); |
213 | if (per_cpu(current_vmcs, cpu) == vmx->vmcs) | |
6aa8b732 | 214 | per_cpu(current_vmcs, cpu) = NULL; |
8b9cf98c | 215 | rdtscll(vmx->vcpu.host_tsc); |
6aa8b732 AK |
216 | } |
217 | ||
8b9cf98c | 218 | static void vcpu_clear(struct vcpu_vmx *vmx) |
8d0be2b3 | 219 | { |
8b9cf98c RR |
220 | if (vmx->vcpu.cpu != raw_smp_processor_id() && vmx->vcpu.cpu != -1) |
221 | smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, | |
222 | vmx, 0, 1); | |
8d0be2b3 | 223 | else |
8b9cf98c RR |
224 | __vcpu_clear(vmx); |
225 | vmx->launched = 0; | |
8d0be2b3 AK |
226 | } |
227 | ||
6aa8b732 AK |
228 | static unsigned long vmcs_readl(unsigned long field) |
229 | { | |
230 | unsigned long value; | |
231 | ||
232 | asm volatile (ASM_VMX_VMREAD_RDX_RAX | |
233 | : "=a"(value) : "d"(field) : "cc"); | |
234 | return value; | |
235 | } | |
236 | ||
237 | static u16 vmcs_read16(unsigned long field) | |
238 | { | |
239 | return vmcs_readl(field); | |
240 | } | |
241 | ||
242 | static u32 vmcs_read32(unsigned long field) | |
243 | { | |
244 | return vmcs_readl(field); | |
245 | } | |
246 | ||
247 | static u64 vmcs_read64(unsigned long field) | |
248 | { | |
05b3e0c2 | 249 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
250 | return vmcs_readl(field); |
251 | #else | |
252 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
253 | #endif | |
254 | } | |
255 | ||
e52de1b8 AK |
256 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
257 | { | |
258 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
259 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
260 | dump_stack(); | |
261 | } | |
262 | ||
6aa8b732 AK |
263 | static void vmcs_writel(unsigned long field, unsigned long value) |
264 | { | |
265 | u8 error; | |
266 | ||
267 | asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0" | |
268 | : "=q"(error) : "a"(value), "d"(field) : "cc" ); | |
e52de1b8 AK |
269 | if (unlikely(error)) |
270 | vmwrite_error(field, value); | |
6aa8b732 AK |
271 | } |
272 | ||
273 | static void vmcs_write16(unsigned long field, u16 value) | |
274 | { | |
275 | vmcs_writel(field, value); | |
276 | } | |
277 | ||
278 | static void vmcs_write32(unsigned long field, u32 value) | |
279 | { | |
280 | vmcs_writel(field, value); | |
281 | } | |
282 | ||
283 | static void vmcs_write64(unsigned long field, u64 value) | |
284 | { | |
05b3e0c2 | 285 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
286 | vmcs_writel(field, value); |
287 | #else | |
288 | vmcs_writel(field, value); | |
289 | asm volatile (""); | |
290 | vmcs_writel(field+1, value >> 32); | |
291 | #endif | |
292 | } | |
293 | ||
2ab455cc AL |
294 | static void vmcs_clear_bits(unsigned long field, u32 mask) |
295 | { | |
296 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
297 | } | |
298 | ||
299 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
300 | { | |
301 | vmcs_writel(field, vmcs_readl(field) | mask); | |
302 | } | |
303 | ||
abd3f2d6 AK |
304 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
305 | { | |
306 | u32 eb; | |
307 | ||
308 | eb = 1u << PF_VECTOR; | |
309 | if (!vcpu->fpu_active) | |
310 | eb |= 1u << NM_VECTOR; | |
311 | if (vcpu->guest_debug.enabled) | |
312 | eb |= 1u << 1; | |
313 | if (vcpu->rmode.active) | |
314 | eb = ~0; | |
315 | vmcs_write32(EXCEPTION_BITMAP, eb); | |
316 | } | |
317 | ||
33ed6329 AK |
318 | static void reload_tss(void) |
319 | { | |
320 | #ifndef CONFIG_X86_64 | |
321 | ||
322 | /* | |
323 | * VT restores TR but not its size. Useless. | |
324 | */ | |
325 | struct descriptor_table gdt; | |
326 | struct segment_descriptor *descs; | |
327 | ||
328 | get_gdt(&gdt); | |
329 | descs = (void *)gdt.base; | |
330 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ | |
331 | load_TR_desc(); | |
332 | #endif | |
333 | } | |
334 | ||
8b9cf98c | 335 | static void load_transition_efer(struct vcpu_vmx *vmx) |
2cc51560 ED |
336 | { |
337 | u64 trans_efer; | |
a2fa3e9f | 338 | int efer_offset = vmx->msr_offset_efer; |
2cc51560 | 339 | |
a2fa3e9f | 340 | trans_efer = vmx->host_msrs[efer_offset].data; |
2cc51560 | 341 | trans_efer &= ~EFER_SAVE_RESTORE_BITS; |
a2fa3e9f | 342 | trans_efer |= msr_efer_save_restore_bits(vmx->guest_msrs[efer_offset]); |
2cc51560 | 343 | wrmsrl(MSR_EFER, trans_efer); |
8b9cf98c | 344 | vmx->vcpu.stat.efer_reload++; |
2cc51560 ED |
345 | } |
346 | ||
8b9cf98c | 347 | static void vmx_save_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 348 | { |
a2fa3e9f | 349 | if (vmx->host_state.loaded) |
33ed6329 AK |
350 | return; |
351 | ||
a2fa3e9f | 352 | vmx->host_state.loaded = 1; |
33ed6329 AK |
353 | /* |
354 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
355 | * allow segment selectors with cpl > 0 or ti == 1. | |
356 | */ | |
a2fa3e9f | 357 | vmx->host_state.ldt_sel = read_ldt(); |
152d3f2f | 358 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
a2fa3e9f | 359 | vmx->host_state.fs_sel = read_fs(); |
152d3f2f | 360 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 361 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
362 | vmx->host_state.fs_reload_needed = 0; |
363 | } else { | |
33ed6329 | 364 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 365 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 366 | } |
a2fa3e9f GH |
367 | vmx->host_state.gs_sel = read_gs(); |
368 | if (!(vmx->host_state.gs_sel & 7)) | |
369 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
370 | else { |
371 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 372 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
373 | } |
374 | ||
375 | #ifdef CONFIG_X86_64 | |
376 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
377 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
378 | #else | |
a2fa3e9f GH |
379 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
380 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 381 | #endif |
707c0874 AK |
382 | |
383 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 384 | if (is_long_mode(&vmx->vcpu)) { |
a2fa3e9f GH |
385 | save_msrs(vmx->host_msrs + |
386 | vmx->msr_offset_kernel_gs_base, 1); | |
707c0874 AK |
387 | } |
388 | #endif | |
a2fa3e9f | 389 | load_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
8b9cf98c RR |
390 | if (msr_efer_need_save_restore(vmx)) |
391 | load_transition_efer(vmx); | |
33ed6329 AK |
392 | } |
393 | ||
8b9cf98c | 394 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 395 | { |
15ad7146 | 396 | unsigned long flags; |
33ed6329 | 397 | |
a2fa3e9f | 398 | if (!vmx->host_state.loaded) |
33ed6329 AK |
399 | return; |
400 | ||
a2fa3e9f | 401 | vmx->host_state.loaded = 0; |
152d3f2f | 402 | if (vmx->host_state.fs_reload_needed) |
a2fa3e9f | 403 | load_fs(vmx->host_state.fs_sel); |
152d3f2f LV |
404 | if (vmx->host_state.gs_ldt_reload_needed) { |
405 | load_ldt(vmx->host_state.ldt_sel); | |
33ed6329 AK |
406 | /* |
407 | * If we have to reload gs, we must take care to | |
408 | * preserve our gs base. | |
409 | */ | |
15ad7146 | 410 | local_irq_save(flags); |
a2fa3e9f | 411 | load_gs(vmx->host_state.gs_sel); |
33ed6329 AK |
412 | #ifdef CONFIG_X86_64 |
413 | wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE)); | |
414 | #endif | |
15ad7146 | 415 | local_irq_restore(flags); |
33ed6329 | 416 | } |
152d3f2f | 417 | reload_tss(); |
a2fa3e9f GH |
418 | save_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
419 | load_msrs(vmx->host_msrs, vmx->save_nmsrs); | |
8b9cf98c | 420 | if (msr_efer_need_save_restore(vmx)) |
a2fa3e9f | 421 | load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1); |
33ed6329 AK |
422 | } |
423 | ||
6aa8b732 AK |
424 | /* |
425 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
426 | * vcpu mutex is already taken. | |
427 | */ | |
15ad7146 | 428 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 429 | { |
a2fa3e9f GH |
430 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
431 | u64 phys_addr = __pa(vmx->vmcs); | |
7700270e | 432 | u64 tsc_this, delta; |
6aa8b732 | 433 | |
8d0be2b3 | 434 | if (vcpu->cpu != cpu) |
8b9cf98c | 435 | vcpu_clear(vmx); |
6aa8b732 | 436 | |
a2fa3e9f | 437 | if (per_cpu(current_vmcs, cpu) != vmx->vmcs) { |
6aa8b732 AK |
438 | u8 error; |
439 | ||
a2fa3e9f | 440 | per_cpu(current_vmcs, cpu) = vmx->vmcs; |
6aa8b732 AK |
441 | asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0" |
442 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) | |
443 | : "cc"); | |
444 | if (error) | |
445 | printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n", | |
a2fa3e9f | 446 | vmx->vmcs, phys_addr); |
6aa8b732 AK |
447 | } |
448 | ||
449 | if (vcpu->cpu != cpu) { | |
450 | struct descriptor_table dt; | |
451 | unsigned long sysenter_esp; | |
452 | ||
453 | vcpu->cpu = cpu; | |
454 | /* | |
455 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
456 | * processors. | |
457 | */ | |
458 | vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */ | |
459 | get_gdt(&dt); | |
460 | vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */ | |
461 | ||
462 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
463 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
7700270e AK |
464 | |
465 | /* | |
466 | * Make sure the time stamp counter is monotonous. | |
467 | */ | |
468 | rdtscll(tsc_this); | |
469 | delta = vcpu->host_tsc - tsc_this; | |
470 | vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta); | |
6aa8b732 | 471 | } |
6aa8b732 AK |
472 | } |
473 | ||
474 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
475 | { | |
8b9cf98c | 476 | vmx_load_host_state(to_vmx(vcpu)); |
7702fd1f | 477 | kvm_put_guest_fpu(vcpu); |
6aa8b732 AK |
478 | } |
479 | ||
5fd86fcf AK |
480 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
481 | { | |
482 | if (vcpu->fpu_active) | |
483 | return; | |
484 | vcpu->fpu_active = 1; | |
707d92fa RR |
485 | vmcs_clear_bits(GUEST_CR0, X86_CR0_TS); |
486 | if (vcpu->cr0 & X86_CR0_TS) | |
487 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); | |
5fd86fcf AK |
488 | update_exception_bitmap(vcpu); |
489 | } | |
490 | ||
491 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) | |
492 | { | |
493 | if (!vcpu->fpu_active) | |
494 | return; | |
495 | vcpu->fpu_active = 0; | |
707d92fa | 496 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf AK |
497 | update_exception_bitmap(vcpu); |
498 | } | |
499 | ||
774c47f1 AK |
500 | static void vmx_vcpu_decache(struct kvm_vcpu *vcpu) |
501 | { | |
8b9cf98c | 502 | vcpu_clear(to_vmx(vcpu)); |
774c47f1 AK |
503 | } |
504 | ||
6aa8b732 AK |
505 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
506 | { | |
507 | return vmcs_readl(GUEST_RFLAGS); | |
508 | } | |
509 | ||
510 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
511 | { | |
512 | vmcs_writel(GUEST_RFLAGS, rflags); | |
513 | } | |
514 | ||
515 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
516 | { | |
517 | unsigned long rip; | |
518 | u32 interruptibility; | |
519 | ||
520 | rip = vmcs_readl(GUEST_RIP); | |
521 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
522 | vmcs_writel(GUEST_RIP, rip); | |
523 | ||
524 | /* | |
525 | * We emulated an instruction, so temporary interrupt blocking | |
526 | * should be removed, if set. | |
527 | */ | |
528 | interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
529 | if (interruptibility & 3) | |
530 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
531 | interruptibility & ~3); | |
c1150d8c | 532 | vcpu->interrupt_window_open = 1; |
6aa8b732 AK |
533 | } |
534 | ||
535 | static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code) | |
536 | { | |
537 | printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n", | |
538 | vmcs_readl(GUEST_RIP)); | |
539 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); | |
540 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
541 | GP_VECTOR | | |
542 | INTR_TYPE_EXCEPTION | | |
543 | INTR_INFO_DELIEVER_CODE_MASK | | |
544 | INTR_INFO_VALID_MASK); | |
545 | } | |
546 | ||
a75beee6 ED |
547 | /* |
548 | * Swap MSR entry in host/guest MSR entry array. | |
549 | */ | |
54e11fa1 | 550 | #ifdef CONFIG_X86_64 |
8b9cf98c | 551 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 552 | { |
a2fa3e9f GH |
553 | struct kvm_msr_entry tmp; |
554 | ||
555 | tmp = vmx->guest_msrs[to]; | |
556 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
557 | vmx->guest_msrs[from] = tmp; | |
558 | tmp = vmx->host_msrs[to]; | |
559 | vmx->host_msrs[to] = vmx->host_msrs[from]; | |
560 | vmx->host_msrs[from] = tmp; | |
a75beee6 | 561 | } |
54e11fa1 | 562 | #endif |
a75beee6 | 563 | |
e38aea3e AK |
564 | /* |
565 | * Set up the vmcs to automatically save and restore system | |
566 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
567 | * mode, as fiddling with msrs is very expensive. | |
568 | */ | |
8b9cf98c | 569 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 570 | { |
2cc51560 | 571 | int save_nmsrs; |
e38aea3e | 572 | |
a75beee6 ED |
573 | save_nmsrs = 0; |
574 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 575 | if (is_long_mode(&vmx->vcpu)) { |
2cc51560 ED |
576 | int index; |
577 | ||
8b9cf98c | 578 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 579 | if (index >= 0) |
8b9cf98c RR |
580 | move_msr_up(vmx, index, save_nmsrs++); |
581 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 582 | if (index >= 0) |
8b9cf98c RR |
583 | move_msr_up(vmx, index, save_nmsrs++); |
584 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 585 | if (index >= 0) |
8b9cf98c RR |
586 | move_msr_up(vmx, index, save_nmsrs++); |
587 | index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE); | |
a75beee6 | 588 | if (index >= 0) |
8b9cf98c | 589 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
590 | /* |
591 | * MSR_K6_STAR is only needed on long mode guests, and only | |
592 | * if efer.sce is enabled. | |
593 | */ | |
8b9cf98c RR |
594 | index = __find_msr_index(vmx, MSR_K6_STAR); |
595 | if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE)) | |
596 | move_msr_up(vmx, index, save_nmsrs++); | |
a75beee6 ED |
597 | } |
598 | #endif | |
a2fa3e9f | 599 | vmx->save_nmsrs = save_nmsrs; |
e38aea3e | 600 | |
4d56c8a7 | 601 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 602 | vmx->msr_offset_kernel_gs_base = |
8b9cf98c | 603 | __find_msr_index(vmx, MSR_KERNEL_GS_BASE); |
4d56c8a7 | 604 | #endif |
8b9cf98c | 605 | vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER); |
e38aea3e AK |
606 | } |
607 | ||
6aa8b732 AK |
608 | /* |
609 | * reads and returns guest's timestamp counter "register" | |
610 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
611 | */ | |
612 | static u64 guest_read_tsc(void) | |
613 | { | |
614 | u64 host_tsc, tsc_offset; | |
615 | ||
616 | rdtscll(host_tsc); | |
617 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
618 | return host_tsc + tsc_offset; | |
619 | } | |
620 | ||
621 | /* | |
622 | * writes 'guest_tsc' into guest's timestamp counter "register" | |
623 | * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc | |
624 | */ | |
625 | static void guest_write_tsc(u64 guest_tsc) | |
626 | { | |
627 | u64 host_tsc; | |
628 | ||
629 | rdtscll(host_tsc); | |
630 | vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc); | |
631 | } | |
632 | ||
6aa8b732 AK |
633 | /* |
634 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
635 | * Returns 0 on success, non-0 otherwise. | |
636 | * Assumes vcpu_load() was already called. | |
637 | */ | |
638 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
639 | { | |
640 | u64 data; | |
a2fa3e9f | 641 | struct kvm_msr_entry *msr; |
6aa8b732 AK |
642 | |
643 | if (!pdata) { | |
644 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
645 | return -EINVAL; | |
646 | } | |
647 | ||
648 | switch (msr_index) { | |
05b3e0c2 | 649 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
650 | case MSR_FS_BASE: |
651 | data = vmcs_readl(GUEST_FS_BASE); | |
652 | break; | |
653 | case MSR_GS_BASE: | |
654 | data = vmcs_readl(GUEST_GS_BASE); | |
655 | break; | |
656 | case MSR_EFER: | |
3bab1f5d | 657 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
658 | #endif |
659 | case MSR_IA32_TIME_STAMP_COUNTER: | |
660 | data = guest_read_tsc(); | |
661 | break; | |
662 | case MSR_IA32_SYSENTER_CS: | |
663 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
664 | break; | |
665 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 666 | data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
667 | break; |
668 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 669 | data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 670 | break; |
6aa8b732 | 671 | default: |
8b9cf98c | 672 | msr = find_msr_entry(to_vmx(vcpu), msr_index); |
3bab1f5d AK |
673 | if (msr) { |
674 | data = msr->data; | |
675 | break; | |
6aa8b732 | 676 | } |
3bab1f5d | 677 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
678 | } |
679 | ||
680 | *pdata = data; | |
681 | return 0; | |
682 | } | |
683 | ||
684 | /* | |
685 | * Writes msr value into into the appropriate "register". | |
686 | * Returns 0 on success, non-0 otherwise. | |
687 | * Assumes vcpu_load() was already called. | |
688 | */ | |
689 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
690 | { | |
a2fa3e9f GH |
691 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
692 | struct kvm_msr_entry *msr; | |
2cc51560 ED |
693 | int ret = 0; |
694 | ||
6aa8b732 | 695 | switch (msr_index) { |
05b3e0c2 | 696 | #ifdef CONFIG_X86_64 |
3bab1f5d | 697 | case MSR_EFER: |
2cc51560 | 698 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
a2fa3e9f | 699 | if (vmx->host_state.loaded) |
8b9cf98c | 700 | load_transition_efer(vmx); |
2cc51560 | 701 | break; |
6aa8b732 AK |
702 | case MSR_FS_BASE: |
703 | vmcs_writel(GUEST_FS_BASE, data); | |
704 | break; | |
705 | case MSR_GS_BASE: | |
706 | vmcs_writel(GUEST_GS_BASE, data); | |
707 | break; | |
708 | #endif | |
709 | case MSR_IA32_SYSENTER_CS: | |
710 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
711 | break; | |
712 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 713 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
714 | break; |
715 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 716 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 717 | break; |
d27d4aca | 718 | case MSR_IA32_TIME_STAMP_COUNTER: |
6aa8b732 AK |
719 | guest_write_tsc(data); |
720 | break; | |
6aa8b732 | 721 | default: |
8b9cf98c | 722 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d AK |
723 | if (msr) { |
724 | msr->data = data; | |
a2fa3e9f GH |
725 | if (vmx->host_state.loaded) |
726 | load_msrs(vmx->guest_msrs, vmx->save_nmsrs); | |
3bab1f5d | 727 | break; |
6aa8b732 | 728 | } |
2cc51560 | 729 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
6aa8b732 AK |
730 | } |
731 | ||
2cc51560 | 732 | return ret; |
6aa8b732 AK |
733 | } |
734 | ||
735 | /* | |
736 | * Sync the rsp and rip registers into the vcpu structure. This allows | |
737 | * registers to be accessed by indexing vcpu->regs. | |
738 | */ | |
739 | static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu) | |
740 | { | |
741 | vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
742 | vcpu->rip = vmcs_readl(GUEST_RIP); | |
743 | } | |
744 | ||
745 | /* | |
746 | * Syncs rsp and rip back into the vmcs. Should be called after possible | |
747 | * modification. | |
748 | */ | |
749 | static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu) | |
750 | { | |
751 | vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]); | |
752 | vmcs_writel(GUEST_RIP, vcpu->rip); | |
753 | } | |
754 | ||
755 | static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
756 | { | |
757 | unsigned long dr7 = 0x400; | |
6aa8b732 AK |
758 | int old_singlestep; |
759 | ||
6aa8b732 AK |
760 | old_singlestep = vcpu->guest_debug.singlestep; |
761 | ||
762 | vcpu->guest_debug.enabled = dbg->enabled; | |
763 | if (vcpu->guest_debug.enabled) { | |
764 | int i; | |
765 | ||
766 | dr7 |= 0x200; /* exact */ | |
767 | for (i = 0; i < 4; ++i) { | |
768 | if (!dbg->breakpoints[i].enabled) | |
769 | continue; | |
770 | vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address; | |
771 | dr7 |= 2 << (i*2); /* global enable */ | |
772 | dr7 |= 0 << (i*4+16); /* execution breakpoint */ | |
773 | } | |
774 | ||
6aa8b732 | 775 | vcpu->guest_debug.singlestep = dbg->singlestep; |
abd3f2d6 | 776 | } else |
6aa8b732 | 777 | vcpu->guest_debug.singlestep = 0; |
6aa8b732 AK |
778 | |
779 | if (old_singlestep && !vcpu->guest_debug.singlestep) { | |
780 | unsigned long flags; | |
781 | ||
782 | flags = vmcs_readl(GUEST_RFLAGS); | |
783 | flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
784 | vmcs_writel(GUEST_RFLAGS, flags); | |
785 | } | |
786 | ||
abd3f2d6 | 787 | update_exception_bitmap(vcpu); |
6aa8b732 AK |
788 | vmcs_writel(GUEST_DR7, dr7); |
789 | ||
790 | return 0; | |
791 | } | |
792 | ||
793 | static __init int cpu_has_kvm_support(void) | |
794 | { | |
795 | unsigned long ecx = cpuid_ecx(1); | |
796 | return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */ | |
797 | } | |
798 | ||
799 | static __init int vmx_disabled_by_bios(void) | |
800 | { | |
801 | u64 msr; | |
802 | ||
803 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
62b3ffb8 YS |
804 | return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED | |
805 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
806 | == MSR_IA32_FEATURE_CONTROL_LOCKED; | |
807 | /* locked but not enabled */ | |
6aa8b732 AK |
808 | } |
809 | ||
774c47f1 | 810 | static void hardware_enable(void *garbage) |
6aa8b732 AK |
811 | { |
812 | int cpu = raw_smp_processor_id(); | |
813 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
814 | u64 old; | |
815 | ||
816 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); | |
62b3ffb8 YS |
817 | if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED | |
818 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
819 | != (MSR_IA32_FEATURE_CONTROL_LOCKED | | |
820 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
6aa8b732 | 821 | /* enable and lock */ |
62b3ffb8 YS |
822 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | |
823 | MSR_IA32_FEATURE_CONTROL_LOCKED | | |
824 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED); | |
66aee91a | 825 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
6aa8b732 AK |
826 | asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr) |
827 | : "memory", "cc"); | |
828 | } | |
829 | ||
830 | static void hardware_disable(void *garbage) | |
831 | { | |
832 | asm volatile (ASM_VMX_VMXOFF : : : "cc"); | |
833 | } | |
834 | ||
1c3d14fe YS |
835 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
836 | u32 msr, u32* result) | |
837 | { | |
838 | u32 vmx_msr_low, vmx_msr_high; | |
839 | u32 ctl = ctl_min | ctl_opt; | |
840 | ||
841 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
842 | ||
843 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
844 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
845 | ||
846 | /* Ensure minimum (required) set of control bits are supported. */ | |
847 | if (ctl_min & ~ctl) | |
002c7f7c | 848 | return -EIO; |
1c3d14fe YS |
849 | |
850 | *result = ctl; | |
851 | return 0; | |
852 | } | |
853 | ||
002c7f7c | 854 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
855 | { |
856 | u32 vmx_msr_low, vmx_msr_high; | |
1c3d14fe YS |
857 | u32 min, opt; |
858 | u32 _pin_based_exec_control = 0; | |
859 | u32 _cpu_based_exec_control = 0; | |
860 | u32 _vmexit_control = 0; | |
861 | u32 _vmentry_control = 0; | |
862 | ||
863 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; | |
864 | opt = 0; | |
865 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, | |
866 | &_pin_based_exec_control) < 0) | |
002c7f7c | 867 | return -EIO; |
1c3d14fe YS |
868 | |
869 | min = CPU_BASED_HLT_EXITING | | |
870 | #ifdef CONFIG_X86_64 | |
871 | CPU_BASED_CR8_LOAD_EXITING | | |
872 | CPU_BASED_CR8_STORE_EXITING | | |
873 | #endif | |
874 | CPU_BASED_USE_IO_BITMAPS | | |
875 | CPU_BASED_MOV_DR_EXITING | | |
876 | CPU_BASED_USE_TSC_OFFSETING; | |
877 | opt = 0; | |
878 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, | |
879 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 880 | return -EIO; |
1c3d14fe YS |
881 | |
882 | min = 0; | |
883 | #ifdef CONFIG_X86_64 | |
884 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
885 | #endif | |
886 | opt = 0; | |
887 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, | |
888 | &_vmexit_control) < 0) | |
002c7f7c | 889 | return -EIO; |
1c3d14fe YS |
890 | |
891 | min = opt = 0; | |
892 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, | |
893 | &_vmentry_control) < 0) | |
002c7f7c | 894 | return -EIO; |
6aa8b732 | 895 | |
c68876fd | 896 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
897 | |
898 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
899 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 900 | return -EIO; |
1c3d14fe YS |
901 | |
902 | #ifdef CONFIG_X86_64 | |
903 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
904 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 905 | return -EIO; |
1c3d14fe YS |
906 | #endif |
907 | ||
908 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
909 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 910 | return -EIO; |
1c3d14fe | 911 | |
002c7f7c YS |
912 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
913 | vmcs_conf->order = get_order(vmcs_config.size); | |
914 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 915 | |
002c7f7c YS |
916 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
917 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
918 | vmcs_conf->vmexit_ctrl = _vmexit_control; | |
919 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe YS |
920 | |
921 | return 0; | |
c68876fd | 922 | } |
6aa8b732 AK |
923 | |
924 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
925 | { | |
926 | int node = cpu_to_node(cpu); | |
927 | struct page *pages; | |
928 | struct vmcs *vmcs; | |
929 | ||
1c3d14fe | 930 | pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
931 | if (!pages) |
932 | return NULL; | |
933 | vmcs = page_address(pages); | |
1c3d14fe YS |
934 | memset(vmcs, 0, vmcs_config.size); |
935 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
936 | return vmcs; |
937 | } | |
938 | ||
939 | static struct vmcs *alloc_vmcs(void) | |
940 | { | |
d3b2c338 | 941 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
942 | } |
943 | ||
944 | static void free_vmcs(struct vmcs *vmcs) | |
945 | { | |
1c3d14fe | 946 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
947 | } |
948 | ||
39959588 | 949 | static void free_kvm_area(void) |
6aa8b732 AK |
950 | { |
951 | int cpu; | |
952 | ||
953 | for_each_online_cpu(cpu) | |
954 | free_vmcs(per_cpu(vmxarea, cpu)); | |
955 | } | |
956 | ||
6aa8b732 AK |
957 | static __init int alloc_kvm_area(void) |
958 | { | |
959 | int cpu; | |
960 | ||
961 | for_each_online_cpu(cpu) { | |
962 | struct vmcs *vmcs; | |
963 | ||
964 | vmcs = alloc_vmcs_cpu(cpu); | |
965 | if (!vmcs) { | |
966 | free_kvm_area(); | |
967 | return -ENOMEM; | |
968 | } | |
969 | ||
970 | per_cpu(vmxarea, cpu) = vmcs; | |
971 | } | |
972 | return 0; | |
973 | } | |
974 | ||
975 | static __init int hardware_setup(void) | |
976 | { | |
002c7f7c YS |
977 | if (setup_vmcs_config(&vmcs_config) < 0) |
978 | return -EIO; | |
6aa8b732 AK |
979 | return alloc_kvm_area(); |
980 | } | |
981 | ||
982 | static __exit void hardware_unsetup(void) | |
983 | { | |
984 | free_kvm_area(); | |
985 | } | |
986 | ||
6aa8b732 AK |
987 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) |
988 | { | |
989 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
990 | ||
6af11b9e | 991 | if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { |
6aa8b732 AK |
992 | vmcs_write16(sf->selector, save->selector); |
993 | vmcs_writel(sf->base, save->base); | |
994 | vmcs_write32(sf->limit, save->limit); | |
995 | vmcs_write32(sf->ar_bytes, save->ar); | |
996 | } else { | |
997 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
998 | << AR_DPL_SHIFT; | |
999 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
1000 | } | |
1001 | } | |
1002 | ||
1003 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
1004 | { | |
1005 | unsigned long flags; | |
1006 | ||
1007 | vcpu->rmode.active = 0; | |
1008 | ||
1009 | vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base); | |
1010 | vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit); | |
1011 | vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar); | |
1012 | ||
1013 | flags = vmcs_readl(GUEST_RFLAGS); | |
1014 | flags &= ~(IOPL_MASK | X86_EFLAGS_VM); | |
1015 | flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT); | |
1016 | vmcs_writel(GUEST_RFLAGS, flags); | |
1017 | ||
66aee91a RR |
1018 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
1019 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
1020 | |
1021 | update_exception_bitmap(vcpu); | |
1022 | ||
1023 | fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es); | |
1024 | fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds); | |
1025 | fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs); | |
1026 | fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs); | |
1027 | ||
1028 | vmcs_write16(GUEST_SS_SELECTOR, 0); | |
1029 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
1030 | ||
1031 | vmcs_write16(GUEST_CS_SELECTOR, | |
1032 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
1033 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1034 | } | |
1035 | ||
33f5fa16 | 1036 | static gva_t rmode_tss_base(struct kvm* kvm) |
6aa8b732 AK |
1037 | { |
1038 | gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3; | |
1039 | return base_gfn << PAGE_SHIFT; | |
1040 | } | |
1041 | ||
1042 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
1043 | { | |
1044 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1045 | ||
1046 | save->selector = vmcs_read16(sf->selector); | |
1047 | save->base = vmcs_readl(sf->base); | |
1048 | save->limit = vmcs_read32(sf->limit); | |
1049 | save->ar = vmcs_read32(sf->ar_bytes); | |
1050 | vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4); | |
1051 | vmcs_write32(sf->limit, 0xffff); | |
1052 | vmcs_write32(sf->ar_bytes, 0xf3); | |
1053 | } | |
1054 | ||
1055 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
1056 | { | |
1057 | unsigned long flags; | |
1058 | ||
1059 | vcpu->rmode.active = 1; | |
1060 | ||
1061 | vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE); | |
1062 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); | |
1063 | ||
1064 | vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); | |
1065 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); | |
1066 | ||
1067 | vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
1068 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
1069 | ||
1070 | flags = vmcs_readl(GUEST_RFLAGS); | |
1071 | vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT; | |
1072 | ||
1073 | flags |= IOPL_MASK | X86_EFLAGS_VM; | |
1074 | ||
1075 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 1076 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
1077 | update_exception_bitmap(vcpu); |
1078 | ||
1079 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); | |
1080 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
1081 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
1082 | ||
1083 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
abacf8df | 1084 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
8cb5b033 AK |
1085 | if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) |
1086 | vmcs_writel(GUEST_CS_BASE, 0xf0000); | |
6aa8b732 AK |
1087 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
1088 | ||
1089 | fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es); | |
1090 | fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds); | |
1091 | fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs); | |
1092 | fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs); | |
75880a01 AK |
1093 | |
1094 | init_rmode_tss(vcpu->kvm); | |
6aa8b732 AK |
1095 | } |
1096 | ||
05b3e0c2 | 1097 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1098 | |
1099 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
1100 | { | |
1101 | u32 guest_tr_ar; | |
1102 | ||
1103 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
1104 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
1105 | printk(KERN_DEBUG "%s: tss fixup for long mode. \n", | |
1106 | __FUNCTION__); | |
1107 | vmcs_write32(GUEST_TR_AR_BYTES, | |
1108 | (guest_tr_ar & ~AR_TYPE_MASK) | |
1109 | | AR_TYPE_BUSY_64_TSS); | |
1110 | } | |
1111 | ||
1112 | vcpu->shadow_efer |= EFER_LMA; | |
1113 | ||
8b9cf98c | 1114 | find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1115 | vmcs_write32(VM_ENTRY_CONTROLS, |
1116 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1117 | | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1118 | } |
1119 | ||
1120 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
1121 | { | |
1122 | vcpu->shadow_efer &= ~EFER_LMA; | |
1123 | ||
1124 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1125 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1126 | & ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1127 | } |
1128 | ||
1129 | #endif | |
1130 | ||
25c4c276 | 1131 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 1132 | { |
399badf3 AK |
1133 | vcpu->cr4 &= KVM_GUEST_CR4_MASK; |
1134 | vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK; | |
1135 | } | |
1136 | ||
6aa8b732 AK |
1137 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1138 | { | |
5fd86fcf AK |
1139 | vmx_fpu_deactivate(vcpu); |
1140 | ||
707d92fa | 1141 | if (vcpu->rmode.active && (cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1142 | enter_pmode(vcpu); |
1143 | ||
707d92fa | 1144 | if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1145 | enter_rmode(vcpu); |
1146 | ||
05b3e0c2 | 1147 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1148 | if (vcpu->shadow_efer & EFER_LME) { |
707d92fa | 1149 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 1150 | enter_lmode(vcpu); |
707d92fa | 1151 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
1152 | exit_lmode(vcpu); |
1153 | } | |
1154 | #endif | |
1155 | ||
1156 | vmcs_writel(CR0_READ_SHADOW, cr0); | |
1157 | vmcs_writel(GUEST_CR0, | |
1158 | (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON); | |
1159 | vcpu->cr0 = cr0; | |
5fd86fcf | 1160 | |
707d92fa | 1161 | if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE)) |
5fd86fcf | 1162 | vmx_fpu_activate(vcpu); |
6aa8b732 AK |
1163 | } |
1164 | ||
6aa8b732 AK |
1165 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
1166 | { | |
1167 | vmcs_writel(GUEST_CR3, cr3); | |
707d92fa | 1168 | if (vcpu->cr0 & X86_CR0_PE) |
5fd86fcf | 1169 | vmx_fpu_deactivate(vcpu); |
6aa8b732 AK |
1170 | } |
1171 | ||
1172 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1173 | { | |
1174 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
1175 | vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ? | |
1176 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON)); | |
1177 | vcpu->cr4 = cr4; | |
1178 | } | |
1179 | ||
05b3e0c2 | 1180 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1181 | |
1182 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1183 | { | |
8b9cf98c RR |
1184 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1185 | struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); | |
6aa8b732 AK |
1186 | |
1187 | vcpu->shadow_efer = efer; | |
1188 | if (efer & EFER_LMA) { | |
1189 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1190 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
1e4e6e00 | 1191 | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1192 | msr->data = efer; |
1193 | ||
1194 | } else { | |
1195 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1196 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
1e4e6e00 | 1197 | ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1198 | |
1199 | msr->data = efer & ~EFER_LME; | |
1200 | } | |
8b9cf98c | 1201 | setup_msrs(vmx); |
6aa8b732 AK |
1202 | } |
1203 | ||
1204 | #endif | |
1205 | ||
1206 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1207 | { | |
1208 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1209 | ||
1210 | return vmcs_readl(sf->base); | |
1211 | } | |
1212 | ||
1213 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
1214 | struct kvm_segment *var, int seg) | |
1215 | { | |
1216 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1217 | u32 ar; | |
1218 | ||
1219 | var->base = vmcs_readl(sf->base); | |
1220 | var->limit = vmcs_read32(sf->limit); | |
1221 | var->selector = vmcs_read16(sf->selector); | |
1222 | ar = vmcs_read32(sf->ar_bytes); | |
1223 | if (ar & AR_UNUSABLE_MASK) | |
1224 | ar = 0; | |
1225 | var->type = ar & 15; | |
1226 | var->s = (ar >> 4) & 1; | |
1227 | var->dpl = (ar >> 5) & 3; | |
1228 | var->present = (ar >> 7) & 1; | |
1229 | var->avl = (ar >> 12) & 1; | |
1230 | var->l = (ar >> 13) & 1; | |
1231 | var->db = (ar >> 14) & 1; | |
1232 | var->g = (ar >> 15) & 1; | |
1233 | var->unusable = (ar >> 16) & 1; | |
1234 | } | |
1235 | ||
653e3108 | 1236 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 1237 | { |
6aa8b732 AK |
1238 | u32 ar; |
1239 | ||
653e3108 | 1240 | if (var->unusable) |
6aa8b732 AK |
1241 | ar = 1 << 16; |
1242 | else { | |
1243 | ar = var->type & 15; | |
1244 | ar |= (var->s & 1) << 4; | |
1245 | ar |= (var->dpl & 3) << 5; | |
1246 | ar |= (var->present & 1) << 7; | |
1247 | ar |= (var->avl & 1) << 12; | |
1248 | ar |= (var->l & 1) << 13; | |
1249 | ar |= (var->db & 1) << 14; | |
1250 | ar |= (var->g & 1) << 15; | |
1251 | } | |
f7fbf1fd UL |
1252 | if (ar == 0) /* a 0 value means unusable */ |
1253 | ar = AR_UNUSABLE_MASK; | |
653e3108 AK |
1254 | |
1255 | return ar; | |
1256 | } | |
1257 | ||
1258 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
1259 | struct kvm_segment *var, int seg) | |
1260 | { | |
1261 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1262 | u32 ar; | |
1263 | ||
1264 | if (vcpu->rmode.active && seg == VCPU_SREG_TR) { | |
1265 | vcpu->rmode.tr.selector = var->selector; | |
1266 | vcpu->rmode.tr.base = var->base; | |
1267 | vcpu->rmode.tr.limit = var->limit; | |
1268 | vcpu->rmode.tr.ar = vmx_segment_access_rights(var); | |
1269 | return; | |
1270 | } | |
1271 | vmcs_writel(sf->base, var->base); | |
1272 | vmcs_write32(sf->limit, var->limit); | |
1273 | vmcs_write16(sf->selector, var->selector); | |
1274 | if (vcpu->rmode.active && var->s) { | |
1275 | /* | |
1276 | * Hack real-mode segments into vm86 compatibility. | |
1277 | */ | |
1278 | if (var->base == 0xffff0000 && var->selector == 0xf000) | |
1279 | vmcs_writel(sf->base, 0xf0000); | |
1280 | ar = 0xf3; | |
1281 | } else | |
1282 | ar = vmx_segment_access_rights(var); | |
6aa8b732 AK |
1283 | vmcs_write32(sf->ar_bytes, ar); |
1284 | } | |
1285 | ||
6aa8b732 AK |
1286 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
1287 | { | |
1288 | u32 ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
1289 | ||
1290 | *db = (ar >> 14) & 1; | |
1291 | *l = (ar >> 13) & 1; | |
1292 | } | |
1293 | ||
1294 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1295 | { | |
1296 | dt->limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
1297 | dt->base = vmcs_readl(GUEST_IDTR_BASE); | |
1298 | } | |
1299 | ||
1300 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1301 | { | |
1302 | vmcs_write32(GUEST_IDTR_LIMIT, dt->limit); | |
1303 | vmcs_writel(GUEST_IDTR_BASE, dt->base); | |
1304 | } | |
1305 | ||
1306 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1307 | { | |
1308 | dt->limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
1309 | dt->base = vmcs_readl(GUEST_GDTR_BASE); | |
1310 | } | |
1311 | ||
1312 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1313 | { | |
1314 | vmcs_write32(GUEST_GDTR_LIMIT, dt->limit); | |
1315 | vmcs_writel(GUEST_GDTR_BASE, dt->base); | |
1316 | } | |
1317 | ||
1318 | static int init_rmode_tss(struct kvm* kvm) | |
1319 | { | |
1320 | struct page *p1, *p2, *p3; | |
1321 | gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT; | |
1322 | char *page; | |
1323 | ||
954bbbc2 AK |
1324 | p1 = gfn_to_page(kvm, fn++); |
1325 | p2 = gfn_to_page(kvm, fn++); | |
1326 | p3 = gfn_to_page(kvm, fn); | |
6aa8b732 AK |
1327 | |
1328 | if (!p1 || !p2 || !p3) { | |
1329 | kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__); | |
1330 | return 0; | |
1331 | } | |
1332 | ||
1333 | page = kmap_atomic(p1, KM_USER0); | |
a3870c47 | 1334 | clear_page(page); |
6aa8b732 AK |
1335 | *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
1336 | kunmap_atomic(page, KM_USER0); | |
1337 | ||
1338 | page = kmap_atomic(p2, KM_USER0); | |
a3870c47 | 1339 | clear_page(page); |
6aa8b732 AK |
1340 | kunmap_atomic(page, KM_USER0); |
1341 | ||
1342 | page = kmap_atomic(p3, KM_USER0); | |
a3870c47 | 1343 | clear_page(page); |
6aa8b732 AK |
1344 | *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0; |
1345 | kunmap_atomic(page, KM_USER0); | |
1346 | ||
1347 | return 1; | |
1348 | } | |
1349 | ||
6aa8b732 AK |
1350 | static void seg_setup(int seg) |
1351 | { | |
1352 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1353 | ||
1354 | vmcs_write16(sf->selector, 0); | |
1355 | vmcs_writel(sf->base, 0); | |
1356 | vmcs_write32(sf->limit, 0xffff); | |
1357 | vmcs_write32(sf->ar_bytes, 0x93); | |
1358 | } | |
1359 | ||
1360 | /* | |
1361 | * Sets up the vmcs for emulated real mode. | |
1362 | */ | |
8b9cf98c | 1363 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 AK |
1364 | { |
1365 | u32 host_sysenter_cs; | |
1366 | u32 junk; | |
1367 | unsigned long a; | |
1368 | struct descriptor_table dt; | |
1369 | int i; | |
1370 | int ret = 0; | |
cd2276a7 | 1371 | unsigned long kvm_vmx_return; |
6aa8b732 | 1372 | |
8b9cf98c | 1373 | if (!init_rmode_tss(vmx->vcpu.kvm)) { |
6aa8b732 AK |
1374 | ret = -ENOMEM; |
1375 | goto out; | |
1376 | } | |
1377 | ||
8b9cf98c RR |
1378 | vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
1379 | vmx->vcpu.cr8 = 0; | |
1380 | vmx->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; | |
1381 | if (vmx->vcpu.vcpu_id == 0) | |
1382 | vmx->vcpu.apic_base |= MSR_IA32_APICBASE_BSP; | |
6aa8b732 | 1383 | |
8b9cf98c | 1384 | fx_init(&vmx->vcpu); |
6aa8b732 AK |
1385 | |
1386 | /* | |
1387 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
1388 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
1389 | */ | |
1390 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); | |
1391 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
1392 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); | |
1393 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1394 | ||
1395 | seg_setup(VCPU_SREG_DS); | |
1396 | seg_setup(VCPU_SREG_ES); | |
1397 | seg_setup(VCPU_SREG_FS); | |
1398 | seg_setup(VCPU_SREG_GS); | |
1399 | seg_setup(VCPU_SREG_SS); | |
1400 | ||
1401 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
1402 | vmcs_writel(GUEST_TR_BASE, 0); | |
1403 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
1404 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
1405 | ||
1406 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
1407 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
1408 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
1409 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
1410 | ||
1411 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
1412 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
1413 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
1414 | ||
1415 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
1416 | vmcs_writel(GUEST_RIP, 0xfff0); | |
1417 | vmcs_writel(GUEST_RSP, 0); | |
1418 | ||
6aa8b732 AK |
1419 | //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 |
1420 | vmcs_writel(GUEST_DR7, 0x400); | |
1421 | ||
1422 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
1423 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
1424 | ||
1425 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
1426 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
1427 | ||
1428 | vmcs_write32(GUEST_ACTIVITY_STATE, 0); | |
1429 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); | |
1430 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
1431 | ||
1432 | /* I/O */ | |
fdef3ad1 HQ |
1433 | vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a)); |
1434 | vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b)); | |
6aa8b732 AK |
1435 | |
1436 | guest_write_tsc(0); | |
1437 | ||
1438 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ | |
1439 | ||
1440 | /* Special registers */ | |
1441 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
1442 | ||
1443 | /* Control */ | |
1c3d14fe YS |
1444 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, |
1445 | vmcs_config.pin_based_exec_ctrl); | |
1446 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
1447 | vmcs_config.cpu_based_exec_ctrl); | |
6aa8b732 | 1448 | |
6aa8b732 AK |
1449 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); |
1450 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
1451 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ | |
1452 | ||
1453 | vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */ | |
1454 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ | |
1455 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
1456 | ||
1457 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
1458 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1459 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1460 | vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */ | |
1461 | vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */ | |
1462 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
05b3e0c2 | 1463 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1464 | rdmsrl(MSR_FS_BASE, a); |
1465 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
1466 | rdmsrl(MSR_GS_BASE, a); | |
1467 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
1468 | #else | |
1469 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
1470 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
1471 | #endif | |
1472 | ||
1473 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
1474 | ||
1475 | get_idt(&dt); | |
1476 | vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */ | |
1477 | ||
cd2276a7 AK |
1478 | asm ("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return)); |
1479 | vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */ | |
2cc51560 ED |
1480 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
1481 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
1482 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); | |
6aa8b732 AK |
1483 | |
1484 | rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); | |
1485 | vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); | |
1486 | rdmsrl(MSR_IA32_SYSENTER_ESP, a); | |
1487 | vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */ | |
1488 | rdmsrl(MSR_IA32_SYSENTER_EIP, a); | |
1489 | vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */ | |
1490 | ||
6aa8b732 AK |
1491 | for (i = 0; i < NR_VMX_MSR; ++i) { |
1492 | u32 index = vmx_msr_index[i]; | |
1493 | u32 data_low, data_high; | |
1494 | u64 data; | |
a2fa3e9f | 1495 | int j = vmx->nmsrs; |
6aa8b732 AK |
1496 | |
1497 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
1498 | continue; | |
432bd6cb AK |
1499 | if (wrmsr_safe(index, data_low, data_high) < 0) |
1500 | continue; | |
6aa8b732 | 1501 | data = data_low | ((u64)data_high << 32); |
a2fa3e9f GH |
1502 | vmx->host_msrs[j].index = index; |
1503 | vmx->host_msrs[j].reserved = 0; | |
1504 | vmx->host_msrs[j].data = data; | |
1505 | vmx->guest_msrs[j] = vmx->host_msrs[j]; | |
1506 | ++vmx->nmsrs; | |
6aa8b732 | 1507 | } |
6aa8b732 | 1508 | |
8b9cf98c | 1509 | setup_msrs(vmx); |
e38aea3e | 1510 | |
1c3d14fe | 1511 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
6aa8b732 AK |
1512 | |
1513 | /* 22.2.1, 20.8.1 */ | |
1c3d14fe YS |
1514 | vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl); |
1515 | ||
6aa8b732 AK |
1516 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
1517 | ||
3b99ab24 | 1518 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1519 | vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0); |
1520 | vmcs_writel(TPR_THRESHOLD, 0); | |
3b99ab24 | 1521 | #endif |
6aa8b732 | 1522 | |
25c4c276 | 1523 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
6aa8b732 AK |
1524 | vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK); |
1525 | ||
8b9cf98c RR |
1526 | vmx->vcpu.cr0 = 0x60000010; |
1527 | vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); // enter rmode | |
1528 | vmx_set_cr4(&vmx->vcpu, 0); | |
05b3e0c2 | 1529 | #ifdef CONFIG_X86_64 |
8b9cf98c | 1530 | vmx_set_efer(&vmx->vcpu, 0); |
6aa8b732 | 1531 | #endif |
8b9cf98c RR |
1532 | vmx_fpu_activate(&vmx->vcpu); |
1533 | update_exception_bitmap(&vmx->vcpu); | |
6aa8b732 AK |
1534 | |
1535 | return 0; | |
1536 | ||
6aa8b732 AK |
1537 | out: |
1538 | return ret; | |
1539 | } | |
1540 | ||
1541 | static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq) | |
1542 | { | |
1543 | u16 ent[2]; | |
1544 | u16 cs; | |
1545 | u16 ip; | |
1546 | unsigned long flags; | |
1547 | unsigned long ss_base = vmcs_readl(GUEST_SS_BASE); | |
1548 | u16 sp = vmcs_readl(GUEST_RSP); | |
1549 | u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
1550 | ||
3964994b | 1551 | if (sp > ss_limit || sp < 6 ) { |
6aa8b732 AK |
1552 | vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n", |
1553 | __FUNCTION__, | |
1554 | vmcs_readl(GUEST_RSP), | |
1555 | vmcs_readl(GUEST_SS_BASE), | |
1556 | vmcs_read32(GUEST_SS_LIMIT)); | |
1557 | return; | |
1558 | } | |
1559 | ||
e7d5d76c LV |
1560 | if (emulator_read_std(irq * sizeof(ent), &ent, sizeof(ent), vcpu) != |
1561 | X86EMUL_CONTINUE) { | |
6aa8b732 AK |
1562 | vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__); |
1563 | return; | |
1564 | } | |
1565 | ||
1566 | flags = vmcs_readl(GUEST_RFLAGS); | |
1567 | cs = vmcs_readl(GUEST_CS_BASE) >> 4; | |
1568 | ip = vmcs_readl(GUEST_RIP); | |
1569 | ||
1570 | ||
e7d5d76c LV |
1571 | if (emulator_write_emulated(ss_base + sp - 2, &flags, 2, vcpu) != X86EMUL_CONTINUE || |
1572 | emulator_write_emulated(ss_base + sp - 4, &cs, 2, vcpu) != X86EMUL_CONTINUE || | |
1573 | emulator_write_emulated(ss_base + sp - 6, &ip, 2, vcpu) != X86EMUL_CONTINUE) { | |
6aa8b732 AK |
1574 | vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__); |
1575 | return; | |
1576 | } | |
1577 | ||
1578 | vmcs_writel(GUEST_RFLAGS, flags & | |
1579 | ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF)); | |
1580 | vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ; | |
1581 | vmcs_writel(GUEST_CS_BASE, ent[1] << 4); | |
1582 | vmcs_writel(GUEST_RIP, ent[0]); | |
1583 | vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6)); | |
1584 | } | |
1585 | ||
85f455f7 ED |
1586 | static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq) |
1587 | { | |
1588 | if (vcpu->rmode.active) { | |
1589 | inject_rmode_irq(vcpu, irq); | |
1590 | return; | |
1591 | } | |
1592 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
1593 | irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1594 | } | |
1595 | ||
6aa8b732 AK |
1596 | static void kvm_do_inject_irq(struct kvm_vcpu *vcpu) |
1597 | { | |
1598 | int word_index = __ffs(vcpu->irq_summary); | |
1599 | int bit_index = __ffs(vcpu->irq_pending[word_index]); | |
1600 | int irq = word_index * BITS_PER_LONG + bit_index; | |
1601 | ||
1602 | clear_bit(bit_index, &vcpu->irq_pending[word_index]); | |
1603 | if (!vcpu->irq_pending[word_index]) | |
1604 | clear_bit(word_index, &vcpu->irq_summary); | |
85f455f7 | 1605 | vmx_inject_irq(vcpu, irq); |
6aa8b732 AK |
1606 | } |
1607 | ||
c1150d8c DL |
1608 | |
1609 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, | |
1610 | struct kvm_run *kvm_run) | |
6aa8b732 | 1611 | { |
c1150d8c DL |
1612 | u32 cpu_based_vm_exec_control; |
1613 | ||
1614 | vcpu->interrupt_window_open = | |
1615 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
1616 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0); | |
1617 | ||
1618 | if (vcpu->interrupt_window_open && | |
1619 | vcpu->irq_summary && | |
1620 | !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK)) | |
6aa8b732 | 1621 | /* |
c1150d8c | 1622 | * If interrupts enabled, and not blocked by sti or mov ss. Good. |
6aa8b732 AK |
1623 | */ |
1624 | kvm_do_inject_irq(vcpu); | |
c1150d8c DL |
1625 | |
1626 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
1627 | if (!vcpu->interrupt_window_open && | |
1628 | (vcpu->irq_summary || kvm_run->request_interrupt_window)) | |
6aa8b732 AK |
1629 | /* |
1630 | * Interrupts blocked. Wait for unblock. | |
1631 | */ | |
c1150d8c DL |
1632 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; |
1633 | else | |
1634 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
1635 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
6aa8b732 AK |
1636 | } |
1637 | ||
1638 | static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu) | |
1639 | { | |
1640 | struct kvm_guest_debug *dbg = &vcpu->guest_debug; | |
1641 | ||
1642 | set_debugreg(dbg->bp[0], 0); | |
1643 | set_debugreg(dbg->bp[1], 1); | |
1644 | set_debugreg(dbg->bp[2], 2); | |
1645 | set_debugreg(dbg->bp[3], 3); | |
1646 | ||
1647 | if (dbg->singlestep) { | |
1648 | unsigned long flags; | |
1649 | ||
1650 | flags = vmcs_readl(GUEST_RFLAGS); | |
1651 | flags |= X86_EFLAGS_TF | X86_EFLAGS_RF; | |
1652 | vmcs_writel(GUEST_RFLAGS, flags); | |
1653 | } | |
1654 | } | |
1655 | ||
1656 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
1657 | int vec, u32 err_code) | |
1658 | { | |
1659 | if (!vcpu->rmode.active) | |
1660 | return 0; | |
1661 | ||
b3f37707 NK |
1662 | /* |
1663 | * Instruction with address size override prefix opcode 0x67 | |
1664 | * Cause the #SS fault with 0 error code in VM86 mode. | |
1665 | */ | |
1666 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) | |
6aa8b732 AK |
1667 | if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE) |
1668 | return 1; | |
1669 | return 0; | |
1670 | } | |
1671 | ||
1672 | static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1673 | { | |
1674 | u32 intr_info, error_code; | |
1675 | unsigned long cr2, rip; | |
1676 | u32 vect_info; | |
1677 | enum emulation_result er; | |
e2dec939 | 1678 | int r; |
6aa8b732 AK |
1679 | |
1680 | vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
1681 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
1682 | ||
1683 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
1684 | !is_page_fault(intr_info)) { | |
1685 | printk(KERN_ERR "%s: unexpected, vectoring info 0x%x " | |
1686 | "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info); | |
1687 | } | |
1688 | ||
85f455f7 | 1689 | if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) { |
6aa8b732 AK |
1690 | int irq = vect_info & VECTORING_INFO_VECTOR_MASK; |
1691 | set_bit(irq, vcpu->irq_pending); | |
1692 | set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary); | |
1693 | } | |
1694 | ||
1695 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */ | |
1696 | asm ("int $2"); | |
1697 | return 1; | |
1698 | } | |
2ab455cc AL |
1699 | |
1700 | if (is_no_device(intr_info)) { | |
5fd86fcf | 1701 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
1702 | return 1; |
1703 | } | |
1704 | ||
6aa8b732 AK |
1705 | error_code = 0; |
1706 | rip = vmcs_readl(GUEST_RIP); | |
1707 | if (intr_info & INTR_INFO_DELIEVER_CODE_MASK) | |
1708 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
1709 | if (is_page_fault(intr_info)) { | |
1710 | cr2 = vmcs_readl(EXIT_QUALIFICATION); | |
1711 | ||
11ec2804 | 1712 | mutex_lock(&vcpu->kvm->lock); |
e2dec939 AK |
1713 | r = kvm_mmu_page_fault(vcpu, cr2, error_code); |
1714 | if (r < 0) { | |
11ec2804 | 1715 | mutex_unlock(&vcpu->kvm->lock); |
e2dec939 AK |
1716 | return r; |
1717 | } | |
1718 | if (!r) { | |
11ec2804 | 1719 | mutex_unlock(&vcpu->kvm->lock); |
6aa8b732 AK |
1720 | return 1; |
1721 | } | |
1722 | ||
1723 | er = emulate_instruction(vcpu, kvm_run, cr2, error_code); | |
11ec2804 | 1724 | mutex_unlock(&vcpu->kvm->lock); |
6aa8b732 AK |
1725 | |
1726 | switch (er) { | |
1727 | case EMULATE_DONE: | |
1728 | return 1; | |
1729 | case EMULATE_DO_MMIO: | |
1165f5fe | 1730 | ++vcpu->stat.mmio_exits; |
6aa8b732 AK |
1731 | return 0; |
1732 | case EMULATE_FAIL: | |
1733 | vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__); | |
1734 | break; | |
1735 | default: | |
1736 | BUG(); | |
1737 | } | |
1738 | } | |
1739 | ||
1740 | if (vcpu->rmode.active && | |
1741 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, | |
72d6e5a0 AK |
1742 | error_code)) { |
1743 | if (vcpu->halt_request) { | |
1744 | vcpu->halt_request = 0; | |
1745 | return kvm_emulate_halt(vcpu); | |
1746 | } | |
6aa8b732 | 1747 | return 1; |
72d6e5a0 | 1748 | } |
6aa8b732 AK |
1749 | |
1750 | if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) { | |
1751 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
1752 | return 0; | |
1753 | } | |
1754 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; | |
1755 | kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK; | |
1756 | kvm_run->ex.error_code = error_code; | |
1757 | return 0; | |
1758 | } | |
1759 | ||
1760 | static int handle_external_interrupt(struct kvm_vcpu *vcpu, | |
1761 | struct kvm_run *kvm_run) | |
1762 | { | |
1165f5fe | 1763 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
1764 | return 1; |
1765 | } | |
1766 | ||
988ad74f AK |
1767 | static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1768 | { | |
1769 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1770 | return 0; | |
1771 | } | |
6aa8b732 | 1772 | |
6aa8b732 AK |
1773 | static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1774 | { | |
1775 | u64 exit_qualification; | |
039576c0 AK |
1776 | int size, down, in, string, rep; |
1777 | unsigned port; | |
6aa8b732 | 1778 | |
1165f5fe | 1779 | ++vcpu->stat.io_exits; |
6aa8b732 | 1780 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); |
039576c0 | 1781 | string = (exit_qualification & 16) != 0; |
e70669ab LV |
1782 | |
1783 | if (string) { | |
1784 | if (emulate_instruction(vcpu, kvm_run, 0, 0) == EMULATE_DO_MMIO) | |
1785 | return 0; | |
1786 | return 1; | |
1787 | } | |
1788 | ||
1789 | size = (exit_qualification & 7) + 1; | |
1790 | in = (exit_qualification & 8) != 0; | |
039576c0 | 1791 | down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0; |
039576c0 AK |
1792 | rep = (exit_qualification & 32) != 0; |
1793 | port = exit_qualification >> 16; | |
e70669ab | 1794 | |
3090dd73 | 1795 | return kvm_emulate_pio(vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
1796 | } |
1797 | ||
102d8325 IM |
1798 | static void |
1799 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1800 | { | |
1801 | /* | |
1802 | * Patch in the VMCALL instruction: | |
1803 | */ | |
1804 | hypercall[0] = 0x0f; | |
1805 | hypercall[1] = 0x01; | |
1806 | hypercall[2] = 0xc1; | |
1807 | hypercall[3] = 0xc3; | |
1808 | } | |
1809 | ||
6aa8b732 AK |
1810 | static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1811 | { | |
1812 | u64 exit_qualification; | |
1813 | int cr; | |
1814 | int reg; | |
1815 | ||
1816 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
1817 | cr = exit_qualification & 15; | |
1818 | reg = (exit_qualification >> 8) & 15; | |
1819 | switch ((exit_qualification >> 4) & 3) { | |
1820 | case 0: /* mov to cr */ | |
1821 | switch (cr) { | |
1822 | case 0: | |
1823 | vcpu_load_rsp_rip(vcpu); | |
1824 | set_cr0(vcpu, vcpu->regs[reg]); | |
1825 | skip_emulated_instruction(vcpu); | |
1826 | return 1; | |
1827 | case 3: | |
1828 | vcpu_load_rsp_rip(vcpu); | |
1829 | set_cr3(vcpu, vcpu->regs[reg]); | |
1830 | skip_emulated_instruction(vcpu); | |
1831 | return 1; | |
1832 | case 4: | |
1833 | vcpu_load_rsp_rip(vcpu); | |
1834 | set_cr4(vcpu, vcpu->regs[reg]); | |
1835 | skip_emulated_instruction(vcpu); | |
1836 | return 1; | |
1837 | case 8: | |
1838 | vcpu_load_rsp_rip(vcpu); | |
1839 | set_cr8(vcpu, vcpu->regs[reg]); | |
1840 | skip_emulated_instruction(vcpu); | |
253abdee YS |
1841 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
1842 | return 0; | |
6aa8b732 AK |
1843 | }; |
1844 | break; | |
25c4c276 AL |
1845 | case 2: /* clts */ |
1846 | vcpu_load_rsp_rip(vcpu); | |
5fd86fcf | 1847 | vmx_fpu_deactivate(vcpu); |
707d92fa | 1848 | vcpu->cr0 &= ~X86_CR0_TS; |
2ab455cc | 1849 | vmcs_writel(CR0_READ_SHADOW, vcpu->cr0); |
5fd86fcf | 1850 | vmx_fpu_activate(vcpu); |
25c4c276 AL |
1851 | skip_emulated_instruction(vcpu); |
1852 | return 1; | |
6aa8b732 AK |
1853 | case 1: /*mov from cr*/ |
1854 | switch (cr) { | |
1855 | case 3: | |
1856 | vcpu_load_rsp_rip(vcpu); | |
1857 | vcpu->regs[reg] = vcpu->cr3; | |
1858 | vcpu_put_rsp_rip(vcpu); | |
1859 | skip_emulated_instruction(vcpu); | |
1860 | return 1; | |
1861 | case 8: | |
6aa8b732 AK |
1862 | vcpu_load_rsp_rip(vcpu); |
1863 | vcpu->regs[reg] = vcpu->cr8; | |
1864 | vcpu_put_rsp_rip(vcpu); | |
1865 | skip_emulated_instruction(vcpu); | |
1866 | return 1; | |
1867 | } | |
1868 | break; | |
1869 | case 3: /* lmsw */ | |
1870 | lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f); | |
1871 | ||
1872 | skip_emulated_instruction(vcpu); | |
1873 | return 1; | |
1874 | default: | |
1875 | break; | |
1876 | } | |
1877 | kvm_run->exit_reason = 0; | |
f0242478 | 1878 | pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
1879 | (int)(exit_qualification >> 4) & 3, cr); |
1880 | return 0; | |
1881 | } | |
1882 | ||
1883 | static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1884 | { | |
1885 | u64 exit_qualification; | |
1886 | unsigned long val; | |
1887 | int dr, reg; | |
1888 | ||
1889 | /* | |
1890 | * FIXME: this code assumes the host is debugging the guest. | |
1891 | * need to deal with guest debugging itself too. | |
1892 | */ | |
1893 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
1894 | dr = exit_qualification & 7; | |
1895 | reg = (exit_qualification >> 8) & 15; | |
1896 | vcpu_load_rsp_rip(vcpu); | |
1897 | if (exit_qualification & 16) { | |
1898 | /* mov from dr */ | |
1899 | switch (dr) { | |
1900 | case 6: | |
1901 | val = 0xffff0ff0; | |
1902 | break; | |
1903 | case 7: | |
1904 | val = 0x400; | |
1905 | break; | |
1906 | default: | |
1907 | val = 0; | |
1908 | } | |
1909 | vcpu->regs[reg] = val; | |
1910 | } else { | |
1911 | /* mov to dr */ | |
1912 | } | |
1913 | vcpu_put_rsp_rip(vcpu); | |
1914 | skip_emulated_instruction(vcpu); | |
1915 | return 1; | |
1916 | } | |
1917 | ||
1918 | static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1919 | { | |
06465c5a AK |
1920 | kvm_emulate_cpuid(vcpu); |
1921 | return 1; | |
6aa8b732 AK |
1922 | } |
1923 | ||
1924 | static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1925 | { | |
1926 | u32 ecx = vcpu->regs[VCPU_REGS_RCX]; | |
1927 | u64 data; | |
1928 | ||
1929 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
1930 | vmx_inject_gp(vcpu, 0); | |
1931 | return 1; | |
1932 | } | |
1933 | ||
1934 | /* FIXME: handling of bits 32:63 of rax, rdx */ | |
1935 | vcpu->regs[VCPU_REGS_RAX] = data & -1u; | |
1936 | vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
1937 | skip_emulated_instruction(vcpu); | |
1938 | return 1; | |
1939 | } | |
1940 | ||
1941 | static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1942 | { | |
1943 | u32 ecx = vcpu->regs[VCPU_REGS_RCX]; | |
1944 | u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u) | |
1945 | | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32); | |
1946 | ||
1947 | if (vmx_set_msr(vcpu, ecx, data) != 0) { | |
1948 | vmx_inject_gp(vcpu, 0); | |
1949 | return 1; | |
1950 | } | |
1951 | ||
1952 | skip_emulated_instruction(vcpu); | |
1953 | return 1; | |
1954 | } | |
1955 | ||
c1150d8c DL |
1956 | static void post_kvm_run_save(struct kvm_vcpu *vcpu, |
1957 | struct kvm_run *kvm_run) | |
1958 | { | |
1959 | kvm_run->if_flag = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) != 0; | |
1960 | kvm_run->cr8 = vcpu->cr8; | |
1961 | kvm_run->apic_base = vcpu->apic_base; | |
1962 | kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open && | |
1963 | vcpu->irq_summary == 0); | |
1964 | } | |
1965 | ||
6aa8b732 AK |
1966 | static int handle_interrupt_window(struct kvm_vcpu *vcpu, |
1967 | struct kvm_run *kvm_run) | |
1968 | { | |
85f455f7 ED |
1969 | u32 cpu_based_vm_exec_control; |
1970 | ||
1971 | /* clear pending irq */ | |
1972 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
1973 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
1974 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
c1150d8c DL |
1975 | /* |
1976 | * If the user space waits to inject interrupts, exit as soon as | |
1977 | * possible | |
1978 | */ | |
1979 | if (kvm_run->request_interrupt_window && | |
022a9308 | 1980 | !vcpu->irq_summary) { |
c1150d8c | 1981 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1165f5fe | 1982 | ++vcpu->stat.irq_window_exits; |
c1150d8c DL |
1983 | return 0; |
1984 | } | |
6aa8b732 AK |
1985 | return 1; |
1986 | } | |
1987 | ||
1988 | static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1989 | { | |
1990 | skip_emulated_instruction(vcpu); | |
d3bef15f | 1991 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
1992 | } |
1993 | ||
c21415e8 IM |
1994 | static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1995 | { | |
510043da | 1996 | skip_emulated_instruction(vcpu); |
270fd9b9 | 1997 | return kvm_hypercall(vcpu, kvm_run); |
c21415e8 IM |
1998 | } |
1999 | ||
6aa8b732 AK |
2000 | /* |
2001 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
2002 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
2003 | * to be done to userspace and return 0. | |
2004 | */ | |
2005 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu, | |
2006 | struct kvm_run *kvm_run) = { | |
2007 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, | |
2008 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 2009 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
6aa8b732 | 2010 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
2011 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
2012 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
2013 | [EXIT_REASON_CPUID] = handle_cpuid, | |
2014 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
2015 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
2016 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
2017 | [EXIT_REASON_HLT] = handle_halt, | |
c21415e8 | 2018 | [EXIT_REASON_VMCALL] = handle_vmcall, |
6aa8b732 AK |
2019 | }; |
2020 | ||
2021 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 2022 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 AK |
2023 | |
2024 | /* | |
2025 | * The guest has exited. See if we can fix it or if we need userspace | |
2026 | * assistance. | |
2027 | */ | |
2028 | static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | |
2029 | { | |
2030 | u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
2031 | u32 exit_reason = vmcs_read32(VM_EXIT_REASON); | |
2032 | ||
2033 | if ( (vectoring_info & VECTORING_INFO_VALID_MASK) && | |
2034 | exit_reason != EXIT_REASON_EXCEPTION_NMI ) | |
2035 | printk(KERN_WARNING "%s: unexpected, valid vectoring info and " | |
2036 | "exit reason is 0x%x\n", __FUNCTION__, exit_reason); | |
6aa8b732 AK |
2037 | if (exit_reason < kvm_vmx_max_exit_handlers |
2038 | && kvm_vmx_exit_handlers[exit_reason]) | |
2039 | return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run); | |
2040 | else { | |
2041 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
2042 | kvm_run->hw.hardware_exit_reason = exit_reason; | |
2043 | } | |
2044 | return 0; | |
2045 | } | |
2046 | ||
c1150d8c DL |
2047 | /* |
2048 | * Check if userspace requested an interrupt window, and that the | |
2049 | * interrupt window is open. | |
2050 | * | |
2051 | * No need to exit to userspace if we already have an interrupt queued. | |
2052 | */ | |
2053 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu, | |
2054 | struct kvm_run *kvm_run) | |
2055 | { | |
2056 | return (!vcpu->irq_summary && | |
2057 | kvm_run->request_interrupt_window && | |
2058 | vcpu->interrupt_window_open && | |
2059 | (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF)); | |
2060 | } | |
2061 | ||
d9e368d6 AK |
2062 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
2063 | { | |
d9e368d6 AK |
2064 | } |
2065 | ||
85f455f7 ED |
2066 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
2067 | { | |
2068 | u32 cpu_based_vm_exec_control; | |
2069 | ||
2070 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2071 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
2072 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2073 | } | |
2074 | ||
2075 | static void vmx_intr_assist(struct kvm_vcpu *vcpu) | |
2076 | { | |
2077 | u32 idtv_info_field, intr_info_field; | |
2078 | int has_ext_irq, interrupt_window_open; | |
2079 | ||
2080 | has_ext_irq = kvm_cpu_has_interrupt(vcpu); | |
2081 | intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD); | |
2082 | idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
2083 | if (intr_info_field & INTR_INFO_VALID_MASK) { | |
2084 | if (idtv_info_field & INTR_INFO_VALID_MASK) { | |
2085 | /* TODO: fault when IDT_Vectoring */ | |
2086 | printk(KERN_ERR "Fault when IDT_Vectoring\n"); | |
2087 | } | |
2088 | if (has_ext_irq) | |
2089 | enable_irq_window(vcpu); | |
2090 | return; | |
2091 | } | |
2092 | if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) { | |
2093 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field); | |
2094 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2095 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
2096 | ||
2097 | if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK)) | |
2098 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
2099 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
2100 | if (unlikely(has_ext_irq)) | |
2101 | enable_irq_window(vcpu); | |
2102 | return; | |
2103 | } | |
2104 | if (!has_ext_irq) | |
2105 | return; | |
2106 | interrupt_window_open = | |
2107 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
2108 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0); | |
2109 | if (interrupt_window_open) | |
2110 | vmx_inject_irq(vcpu, kvm_cpu_get_interrupt(vcpu)); | |
2111 | else | |
2112 | enable_irq_window(vcpu); | |
2113 | } | |
2114 | ||
6aa8b732 AK |
2115 | static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2116 | { | |
a2fa3e9f | 2117 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 2118 | u8 fail; |
e2dec939 | 2119 | int r; |
6aa8b732 | 2120 | |
e6adf283 | 2121 | preempted: |
6aa8b732 AK |
2122 | if (vcpu->guest_debug.enabled) |
2123 | kvm_guest_debug_pre(vcpu); | |
2124 | ||
e6adf283 | 2125 | again: |
9ae0448f SL |
2126 | r = kvm_mmu_reload(vcpu); |
2127 | if (unlikely(r)) | |
2128 | goto out; | |
2129 | ||
15ad7146 AK |
2130 | preempt_disable(); |
2131 | ||
8b9cf98c | 2132 | vmx_save_host_state(vmx); |
e6adf283 AK |
2133 | kvm_load_guest_fpu(vcpu); |
2134 | ||
2135 | /* | |
2136 | * Loading guest fpu may have cleared host cr0.ts | |
2137 | */ | |
2138 | vmcs_writel(HOST_CR0, read_cr0()); | |
2139 | ||
d9e368d6 AK |
2140 | local_irq_disable(); |
2141 | ||
7e66f350 AK |
2142 | if (signal_pending(current)) { |
2143 | local_irq_enable(); | |
2144 | preempt_enable(); | |
2145 | r = -EINTR; | |
2146 | kvm_run->exit_reason = KVM_EXIT_INTR; | |
2147 | ++vcpu->stat.signal_exits; | |
2148 | goto out; | |
2149 | } | |
2150 | ||
85f455f7 ED |
2151 | if (irqchip_in_kernel(vcpu->kvm)) |
2152 | vmx_intr_assist(vcpu); | |
2153 | else if (!vcpu->mmio_read_completed) | |
7e66f350 AK |
2154 | do_interrupt_requests(vcpu, kvm_run); |
2155 | ||
d9e368d6 AK |
2156 | vcpu->guest_mode = 1; |
2157 | if (vcpu->requests) | |
2158 | if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests)) | |
2159 | vmx_flush_tlb(vcpu); | |
2160 | ||
6aa8b732 AK |
2161 | asm ( |
2162 | /* Store host registers */ | |
05b3e0c2 | 2163 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2164 | "push %%rax; push %%rbx; push %%rdx;" |
2165 | "push %%rsi; push %%rdi; push %%rbp;" | |
2166 | "push %%r8; push %%r9; push %%r10; push %%r11;" | |
2167 | "push %%r12; push %%r13; push %%r14; push %%r15;" | |
2168 | "push %%rcx \n\t" | |
2169 | ASM_VMX_VMWRITE_RSP_RDX "\n\t" | |
2170 | #else | |
2171 | "pusha; push %%ecx \n\t" | |
2172 | ASM_VMX_VMWRITE_RSP_RDX "\n\t" | |
2173 | #endif | |
2174 | /* Check if vmlaunch of vmresume is needed */ | |
2175 | "cmp $0, %1 \n\t" | |
2176 | /* Load guest registers. Don't clobber flags. */ | |
05b3e0c2 | 2177 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2178 | "mov %c[cr2](%3), %%rax \n\t" |
2179 | "mov %%rax, %%cr2 \n\t" | |
2180 | "mov %c[rax](%3), %%rax \n\t" | |
2181 | "mov %c[rbx](%3), %%rbx \n\t" | |
2182 | "mov %c[rdx](%3), %%rdx \n\t" | |
2183 | "mov %c[rsi](%3), %%rsi \n\t" | |
2184 | "mov %c[rdi](%3), %%rdi \n\t" | |
2185 | "mov %c[rbp](%3), %%rbp \n\t" | |
2186 | "mov %c[r8](%3), %%r8 \n\t" | |
2187 | "mov %c[r9](%3), %%r9 \n\t" | |
2188 | "mov %c[r10](%3), %%r10 \n\t" | |
2189 | "mov %c[r11](%3), %%r11 \n\t" | |
2190 | "mov %c[r12](%3), %%r12 \n\t" | |
2191 | "mov %c[r13](%3), %%r13 \n\t" | |
2192 | "mov %c[r14](%3), %%r14 \n\t" | |
2193 | "mov %c[r15](%3), %%r15 \n\t" | |
2194 | "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */ | |
2195 | #else | |
2196 | "mov %c[cr2](%3), %%eax \n\t" | |
2197 | "mov %%eax, %%cr2 \n\t" | |
2198 | "mov %c[rax](%3), %%eax \n\t" | |
2199 | "mov %c[rbx](%3), %%ebx \n\t" | |
2200 | "mov %c[rdx](%3), %%edx \n\t" | |
2201 | "mov %c[rsi](%3), %%esi \n\t" | |
2202 | "mov %c[rdi](%3), %%edi \n\t" | |
2203 | "mov %c[rbp](%3), %%ebp \n\t" | |
2204 | "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */ | |
2205 | #endif | |
2206 | /* Enter guest mode */ | |
cd2276a7 | 2207 | "jne .Llaunched \n\t" |
6aa8b732 | 2208 | ASM_VMX_VMLAUNCH "\n\t" |
cd2276a7 AK |
2209 | "jmp .Lkvm_vmx_return \n\t" |
2210 | ".Llaunched: " ASM_VMX_VMRESUME "\n\t" | |
2211 | ".Lkvm_vmx_return: " | |
6aa8b732 | 2212 | /* Save guest registers, load host registers, keep flags */ |
05b3e0c2 | 2213 | #ifdef CONFIG_X86_64 |
96958231 | 2214 | "xchg %3, (%%rsp) \n\t" |
6aa8b732 AK |
2215 | "mov %%rax, %c[rax](%3) \n\t" |
2216 | "mov %%rbx, %c[rbx](%3) \n\t" | |
96958231 | 2217 | "pushq (%%rsp); popq %c[rcx](%3) \n\t" |
6aa8b732 AK |
2218 | "mov %%rdx, %c[rdx](%3) \n\t" |
2219 | "mov %%rsi, %c[rsi](%3) \n\t" | |
2220 | "mov %%rdi, %c[rdi](%3) \n\t" | |
2221 | "mov %%rbp, %c[rbp](%3) \n\t" | |
2222 | "mov %%r8, %c[r8](%3) \n\t" | |
2223 | "mov %%r9, %c[r9](%3) \n\t" | |
2224 | "mov %%r10, %c[r10](%3) \n\t" | |
2225 | "mov %%r11, %c[r11](%3) \n\t" | |
2226 | "mov %%r12, %c[r12](%3) \n\t" | |
2227 | "mov %%r13, %c[r13](%3) \n\t" | |
2228 | "mov %%r14, %c[r14](%3) \n\t" | |
2229 | "mov %%r15, %c[r15](%3) \n\t" | |
2230 | "mov %%cr2, %%rax \n\t" | |
2231 | "mov %%rax, %c[cr2](%3) \n\t" | |
96958231 | 2232 | "mov (%%rsp), %3 \n\t" |
6aa8b732 AK |
2233 | |
2234 | "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;" | |
2235 | "pop %%r11; pop %%r10; pop %%r9; pop %%r8;" | |
2236 | "pop %%rbp; pop %%rdi; pop %%rsi;" | |
2237 | "pop %%rdx; pop %%rbx; pop %%rax \n\t" | |
2238 | #else | |
96958231 | 2239 | "xchg %3, (%%esp) \n\t" |
6aa8b732 AK |
2240 | "mov %%eax, %c[rax](%3) \n\t" |
2241 | "mov %%ebx, %c[rbx](%3) \n\t" | |
96958231 | 2242 | "pushl (%%esp); popl %c[rcx](%3) \n\t" |
6aa8b732 AK |
2243 | "mov %%edx, %c[rdx](%3) \n\t" |
2244 | "mov %%esi, %c[rsi](%3) \n\t" | |
2245 | "mov %%edi, %c[rdi](%3) \n\t" | |
2246 | "mov %%ebp, %c[rbp](%3) \n\t" | |
2247 | "mov %%cr2, %%eax \n\t" | |
2248 | "mov %%eax, %c[cr2](%3) \n\t" | |
96958231 | 2249 | "mov (%%esp), %3 \n\t" |
6aa8b732 AK |
2250 | |
2251 | "pop %%ecx; popa \n\t" | |
2252 | #endif | |
2253 | "setbe %0 \n\t" | |
e0015489 | 2254 | : "=q" (fail) |
a2fa3e9f | 2255 | : "r"(vmx->launched), "d"((unsigned long)HOST_RSP), |
6aa8b732 AK |
2256 | "c"(vcpu), |
2257 | [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])), | |
2258 | [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])), | |
2259 | [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])), | |
2260 | [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])), | |
2261 | [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])), | |
2262 | [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])), | |
2263 | [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 2264 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2265 | [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])), |
2266 | [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])), | |
2267 | [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])), | |
2268 | [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])), | |
2269 | [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])), | |
2270 | [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])), | |
2271 | [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])), | |
2272 | [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])), | |
2273 | #endif | |
2274 | [cr2]"i"(offsetof(struct kvm_vcpu, cr2)) | |
2275 | : "cc", "memory" ); | |
2276 | ||
d9e368d6 AK |
2277 | vcpu->guest_mode = 0; |
2278 | local_irq_enable(); | |
2279 | ||
1165f5fe | 2280 | ++vcpu->stat.exits; |
6aa8b732 | 2281 | |
c1150d8c | 2282 | vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0; |
6aa8b732 | 2283 | |
6aa8b732 | 2284 | asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
15ad7146 AK |
2285 | vmx->launched = 1; |
2286 | ||
2287 | preempt_enable(); | |
6aa8b732 | 2288 | |
05e0c8c3 | 2289 | if (unlikely(fail)) { |
8eb7d334 AK |
2290 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
2291 | kvm_run->fail_entry.hardware_entry_failure_reason | |
2292 | = vmcs_read32(VM_INSTRUCTION_ERROR); | |
e2dec939 | 2293 | r = 0; |
05e0c8c3 AK |
2294 | goto out; |
2295 | } | |
2296 | /* | |
2297 | * Profile KVM exit RIPs: | |
2298 | */ | |
2299 | if (unlikely(prof_on == KVM_PROFILING)) | |
2300 | profile_hit(KVM_PROFILING, (void *)vmcs_readl(GUEST_RIP)); | |
2301 | ||
05e0c8c3 AK |
2302 | r = kvm_handle_exit(kvm_run, vcpu); |
2303 | if (r > 0) { | |
05e0c8c3 AK |
2304 | if (dm_request_for_irq_injection(vcpu, kvm_run)) { |
2305 | r = -EINTR; | |
2306 | kvm_run->exit_reason = KVM_EXIT_INTR; | |
2307 | ++vcpu->stat.request_irq_exits; | |
2308 | goto out; | |
2309 | } | |
2310 | if (!need_resched()) { | |
2311 | ++vcpu->stat.light_exits; | |
2312 | goto again; | |
6aa8b732 AK |
2313 | } |
2314 | } | |
c1150d8c | 2315 | |
e6adf283 | 2316 | out: |
e6adf283 AK |
2317 | if (r > 0) { |
2318 | kvm_resched(vcpu); | |
2319 | goto preempted; | |
2320 | } | |
2321 | ||
c1150d8c | 2322 | post_kvm_run_save(vcpu, kvm_run); |
e2dec939 | 2323 | return r; |
6aa8b732 AK |
2324 | } |
2325 | ||
6aa8b732 AK |
2326 | static void vmx_inject_page_fault(struct kvm_vcpu *vcpu, |
2327 | unsigned long addr, | |
2328 | u32 err_code) | |
2329 | { | |
2330 | u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
2331 | ||
1165f5fe | 2332 | ++vcpu->stat.pf_guest; |
6aa8b732 AK |
2333 | |
2334 | if (is_page_fault(vect_info)) { | |
2335 | printk(KERN_DEBUG "inject_page_fault: " | |
2336 | "double fault 0x%lx @ 0x%lx\n", | |
2337 | addr, vmcs_readl(GUEST_RIP)); | |
2338 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0); | |
2339 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2340 | DF_VECTOR | | |
2341 | INTR_TYPE_EXCEPTION | | |
2342 | INTR_INFO_DELIEVER_CODE_MASK | | |
2343 | INTR_INFO_VALID_MASK); | |
2344 | return; | |
2345 | } | |
2346 | vcpu->cr2 = addr; | |
2347 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code); | |
2348 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2349 | PF_VECTOR | | |
2350 | INTR_TYPE_EXCEPTION | | |
2351 | INTR_INFO_DELIEVER_CODE_MASK | | |
2352 | INTR_INFO_VALID_MASK); | |
2353 | ||
2354 | } | |
2355 | ||
2356 | static void vmx_free_vmcs(struct kvm_vcpu *vcpu) | |
2357 | { | |
a2fa3e9f GH |
2358 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2359 | ||
2360 | if (vmx->vmcs) { | |
8b9cf98c | 2361 | on_each_cpu(__vcpu_clear, vmx, 0, 1); |
a2fa3e9f GH |
2362 | free_vmcs(vmx->vmcs); |
2363 | vmx->vmcs = NULL; | |
6aa8b732 AK |
2364 | } |
2365 | } | |
2366 | ||
2367 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) | |
2368 | { | |
fb3f0f51 RR |
2369 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2370 | ||
6aa8b732 | 2371 | vmx_free_vmcs(vcpu); |
fb3f0f51 RR |
2372 | kfree(vmx->host_msrs); |
2373 | kfree(vmx->guest_msrs); | |
2374 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 2375 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
2376 | } |
2377 | ||
fb3f0f51 | 2378 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 2379 | { |
fb3f0f51 | 2380 | int err; |
c16f862d | 2381 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 2382 | int cpu; |
6aa8b732 | 2383 | |
a2fa3e9f | 2384 | if (!vmx) |
fb3f0f51 RR |
2385 | return ERR_PTR(-ENOMEM); |
2386 | ||
2387 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); | |
2388 | if (err) | |
2389 | goto free_vcpu; | |
965b58a5 | 2390 | |
a2fa3e9f | 2391 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
fb3f0f51 RR |
2392 | if (!vmx->guest_msrs) { |
2393 | err = -ENOMEM; | |
2394 | goto uninit_vcpu; | |
2395 | } | |
965b58a5 | 2396 | |
a2fa3e9f GH |
2397 | vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
2398 | if (!vmx->host_msrs) | |
fb3f0f51 | 2399 | goto free_guest_msrs; |
965b58a5 | 2400 | |
a2fa3e9f GH |
2401 | vmx->vmcs = alloc_vmcs(); |
2402 | if (!vmx->vmcs) | |
fb3f0f51 | 2403 | goto free_msrs; |
a2fa3e9f GH |
2404 | |
2405 | vmcs_clear(vmx->vmcs); | |
2406 | ||
15ad7146 AK |
2407 | cpu = get_cpu(); |
2408 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
8b9cf98c | 2409 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 2410 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 2411 | put_cpu(); |
fb3f0f51 RR |
2412 | if (err) |
2413 | goto free_vmcs; | |
2414 | ||
2415 | return &vmx->vcpu; | |
2416 | ||
2417 | free_vmcs: | |
2418 | free_vmcs(vmx->vmcs); | |
2419 | free_msrs: | |
2420 | kfree(vmx->host_msrs); | |
2421 | free_guest_msrs: | |
2422 | kfree(vmx->guest_msrs); | |
2423 | uninit_vcpu: | |
2424 | kvm_vcpu_uninit(&vmx->vcpu); | |
2425 | free_vcpu: | |
a4770347 | 2426 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 2427 | return ERR_PTR(err); |
6aa8b732 AK |
2428 | } |
2429 | ||
002c7f7c YS |
2430 | static void __init vmx_check_processor_compat(void *rtn) |
2431 | { | |
2432 | struct vmcs_config vmcs_conf; | |
2433 | ||
2434 | *(int *)rtn = 0; | |
2435 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
2436 | *(int *)rtn = -EIO; | |
2437 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
2438 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
2439 | smp_processor_id()); | |
2440 | *(int *)rtn = -EIO; | |
2441 | } | |
2442 | } | |
2443 | ||
6aa8b732 AK |
2444 | static struct kvm_arch_ops vmx_arch_ops = { |
2445 | .cpu_has_kvm_support = cpu_has_kvm_support, | |
2446 | .disabled_by_bios = vmx_disabled_by_bios, | |
2447 | .hardware_setup = hardware_setup, | |
2448 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 2449 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
2450 | .hardware_enable = hardware_enable, |
2451 | .hardware_disable = hardware_disable, | |
2452 | ||
2453 | .vcpu_create = vmx_create_vcpu, | |
2454 | .vcpu_free = vmx_free_vcpu, | |
2455 | ||
2456 | .vcpu_load = vmx_vcpu_load, | |
2457 | .vcpu_put = vmx_vcpu_put, | |
774c47f1 | 2458 | .vcpu_decache = vmx_vcpu_decache, |
6aa8b732 AK |
2459 | |
2460 | .set_guest_debug = set_guest_debug, | |
2461 | .get_msr = vmx_get_msr, | |
2462 | .set_msr = vmx_set_msr, | |
2463 | .get_segment_base = vmx_get_segment_base, | |
2464 | .get_segment = vmx_get_segment, | |
2465 | .set_segment = vmx_set_segment, | |
6aa8b732 | 2466 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
25c4c276 | 2467 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 2468 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
2469 | .set_cr3 = vmx_set_cr3, |
2470 | .set_cr4 = vmx_set_cr4, | |
05b3e0c2 | 2471 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2472 | .set_efer = vmx_set_efer, |
2473 | #endif | |
2474 | .get_idt = vmx_get_idt, | |
2475 | .set_idt = vmx_set_idt, | |
2476 | .get_gdt = vmx_get_gdt, | |
2477 | .set_gdt = vmx_set_gdt, | |
2478 | .cache_regs = vcpu_load_rsp_rip, | |
2479 | .decache_regs = vcpu_put_rsp_rip, | |
2480 | .get_rflags = vmx_get_rflags, | |
2481 | .set_rflags = vmx_set_rflags, | |
2482 | ||
2483 | .tlb_flush = vmx_flush_tlb, | |
2484 | .inject_page_fault = vmx_inject_page_fault, | |
2485 | ||
2486 | .inject_gp = vmx_inject_gp, | |
2487 | ||
2488 | .run = vmx_vcpu_run, | |
2489 | .skip_emulated_instruction = skip_emulated_instruction, | |
102d8325 | 2490 | .patch_hypercall = vmx_patch_hypercall, |
6aa8b732 AK |
2491 | }; |
2492 | ||
2493 | static int __init vmx_init(void) | |
2494 | { | |
fdef3ad1 HQ |
2495 | void *iova; |
2496 | int r; | |
2497 | ||
2498 | vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
2499 | if (!vmx_io_bitmap_a) | |
2500 | return -ENOMEM; | |
2501 | ||
2502 | vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
2503 | if (!vmx_io_bitmap_b) { | |
2504 | r = -ENOMEM; | |
2505 | goto out; | |
2506 | } | |
2507 | ||
2508 | /* | |
2509 | * Allow direct access to the PC debug port (it is often used for I/O | |
2510 | * delays, but the vmexits simply slow things down). | |
2511 | */ | |
2512 | iova = kmap(vmx_io_bitmap_a); | |
2513 | memset(iova, 0xff, PAGE_SIZE); | |
2514 | clear_bit(0x80, iova); | |
cd0536d7 | 2515 | kunmap(vmx_io_bitmap_a); |
fdef3ad1 HQ |
2516 | |
2517 | iova = kmap(vmx_io_bitmap_b); | |
2518 | memset(iova, 0xff, PAGE_SIZE); | |
cd0536d7 | 2519 | kunmap(vmx_io_bitmap_b); |
fdef3ad1 | 2520 | |
c16f862d | 2521 | r = kvm_init_arch(&vmx_arch_ops, sizeof(struct vcpu_vmx), THIS_MODULE); |
fdef3ad1 HQ |
2522 | if (r) |
2523 | goto out1; | |
2524 | ||
2525 | return 0; | |
2526 | ||
2527 | out1: | |
2528 | __free_page(vmx_io_bitmap_b); | |
2529 | out: | |
2530 | __free_page(vmx_io_bitmap_a); | |
2531 | return r; | |
6aa8b732 AK |
2532 | } |
2533 | ||
2534 | static void __exit vmx_exit(void) | |
2535 | { | |
fdef3ad1 HQ |
2536 | __free_page(vmx_io_bitmap_b); |
2537 | __free_page(vmx_io_bitmap_a); | |
2538 | ||
6aa8b732 AK |
2539 | kvm_exit_arch(); |
2540 | } | |
2541 | ||
2542 | module_init(vmx_init) | |
2543 | module_exit(vmx_exit) |