[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / s390 / include / asm / processor.h

/*
 *  S390 version
 *    Copyright IBM Corp. 1999
 *    Author(s): Hartmut Penner (hp@de.ibm.com),
 *               Martin Schwidefsky (schwidefsky@de.ibm.com)
 *
 *  Derived from "include/asm-i386/processor.h"
 *    Copyright (C) 1994, Linus Torvalds
 */

#ifndef __ASM_S390_PROCESSOR_H
#define __ASM_S390_PROCESSOR_H

#include <linux/linkage.h>
#include <linux/irqflags.h>
#include <asm/cpu.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include <asm/setup.h>

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })

static inline void get_cpu_id(struct cpuid *ptr)
{
	asm volatile("stidp %0" : "=Q" (*ptr));
}

extern void s390_adjust_jiffies(void);
extern const struct seq_operations cpuinfo_op;
extern int sysctl_ieee_emulation_warnings;

/*
 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
 */
#ifndef CONFIG_64BIT

#define TASK_SIZE		(1UL << 31)
#define TASK_UNMAPPED_BASE	(1UL << 30)

#else /* CONFIG_64BIT */

#define TASK_SIZE_OF(tsk)	((tsk)->mm->context.asce_limit)
#define TASK_UNMAPPED_BASE	(test_thread_flag(TIF_31BIT) ? \
					(1UL << 30) : (1UL << 41))
#define TASK_SIZE		TASK_SIZE_OF(current)

#endif /* CONFIG_64BIT */

#ifndef CONFIG_64BIT
#define STACK_TOP		(1UL << 31)
#define STACK_TOP_MAX		(1UL << 31)
#else /* CONFIG_64BIT */
#define STACK_TOP		(1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
#define STACK_TOP_MAX		(1UL << 42)
#endif /* CONFIG_64BIT */

#define HAVE_ARCH_PICK_MMAP_LAYOUT

typedef struct {
        __u32 ar4;
} mm_segment_t;

/*
 * Thread structure
 */
struct thread_struct {
	s390_fp_regs fp_regs;
	unsigned int  acrs[NUM_ACRS];
        unsigned long ksp;              /* kernel stack pointer             */
	mm_segment_t mm_segment;
	unsigned long gmap_addr;	/* address of last gmap fault. */
	struct per_regs per_user;	/* User specified PER registers */
	struct per_event per_event;	/* Cause of the last PER trap */
        /* pfault_wait is used to block the process on a pfault event */
	unsigned long pfault_wait;
	struct list_head list;
};

typedef struct thread_struct thread_struct;

/*
 * Stack layout of a C stack frame.
 */
#ifndef __PACK_STACK
struct stack_frame {
	unsigned long back_chain;
	unsigned long empty1[5];
	unsigned long gprs[10];
	unsigned int  empty2[8];
};
#else
struct stack_frame {
	unsigned long empty1[5];
	unsigned int  empty2[8];
	unsigned long gprs[10];
	unsigned long back_chain;
};
#endif

#define ARCH_MIN_TASKALIGN	8

#define INIT_THREAD {							\
	.ksp = sizeof(init_stack) + (unsigned long) &init_stack,	\
}

/*
 * Do necessary setup to start up a new thread.
 */
#define start_thread(regs, new_psw, new_stackp) do {			\
	regs->psw.mask	= psw_user_bits | PSW_MASK_EA | PSW_MASK_BA;	\
	regs->psw.addr	= new_psw | PSW_ADDR_AMODE;			\
	regs->gprs[15]	= new_stackp;					\
} while (0)

#define start_thread31(regs, new_psw, new_stackp) do {			\
	regs->psw.mask	= psw_user_bits | PSW_MASK_BA;			\
	regs->psw.addr	= new_psw | PSW_ADDR_AMODE;			\
	regs->gprs[15]	= new_stackp;					\
	crst_table_downgrade(current->mm, 1UL << 31);			\
} while (0)

/* Forward declaration, a strange C thing */
struct task_struct;
struct mm_struct;
struct seq_file;

/* Free all resources held by a thread. */
extern void release_thread(struct task_struct *);
extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);

/*
 * Return saved PC of a blocked thread.
 */
extern unsigned long thread_saved_pc(struct task_struct *t);

extern void show_code(struct pt_regs *regs);

unsigned long get_wchan(struct task_struct *p);
#define task_pt_regs(tsk) ((struct pt_regs *) \
        (task_stack_page(tsk) + THREAD_SIZE) - 1)
#define KSTK_EIP(tsk)	(task_pt_regs(tsk)->psw.addr)
#define KSTK_ESP(tsk)	(task_pt_regs(tsk)->gprs[15])

static inline unsigned short stap(void)
{
	unsigned short cpu_address;

	asm volatile("stap %0" : "=m" (cpu_address));
	return cpu_address;
}

/*
 * Give up the time slice of the virtual PU.
 */
static inline void cpu_relax(void)
{
	if (MACHINE_HAS_DIAG44)
		asm volatile("diag 0,0,68");
	barrier();
}

static inline void psw_set_key(unsigned int key)
{
	asm volatile("spka 0(%0)" : : "d" (key));
}

/*
 * Set PSW to specified value.
 */
static inline void __load_psw(psw_t psw)
{
#ifndef CONFIG_64BIT
	asm volatile("lpsw  %0" : : "Q" (psw) : "cc");
#else
	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
#endif
}

/*
 * Set PSW mask to specified value, while leaving the
 * PSW addr pointing to the next instruction.
 */
static inline void __load_psw_mask (unsigned long mask)
{
	unsigned long addr;
	psw_t psw;

	psw.mask = mask;

#ifndef CONFIG_64BIT
	asm volatile(
		"	basr	%0,0\n"
		"0:	ahi	%0,1f-0b\n"
		"	st	%0,%O1+4(%R1)\n"
		"	lpsw	%1\n"
		"1:"
		: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
#else /* CONFIG_64BIT */
	asm volatile(
		"	larl	%0,1f\n"
		"	stg	%0,%O1+8(%R1)\n"
		"	lpswe	%1\n"
		"1:"
		: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
#endif /* CONFIG_64BIT */
}

/*
 * Rewind PSW instruction address by specified number of bytes.
 */
static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
{
#ifndef CONFIG_64BIT
	if (psw.addr & PSW_ADDR_AMODE)
		/* 31 bit mode */
		return (psw.addr - ilc) | PSW_ADDR_AMODE;
	/* 24 bit mode */
	return (psw.addr - ilc) & ((1UL << 24) - 1);
#else
	unsigned long mask;

	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
	       (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
					  (1UL << 24) - 1;
	return (psw.addr - ilc) & mask;
#endif
}
 
/*
 * Function to drop a processor into disabled wait state
 */
static inline void __noreturn disabled_wait(unsigned long code)
{
        unsigned long ctl_buf;
        psw_t dw_psw;

	dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
        dw_psw.addr = code;
        /* 
         * Store status and then load disabled wait psw,
         * the processor is dead afterwards
         */
#ifndef CONFIG_64BIT
	asm volatile(
		"	stctl	0,0,0(%2)\n"
		"	ni	0(%2),0xef\n"	/* switch off protection */
		"	lctl	0,0,0(%2)\n"
		"	stpt	0xd8\n"		/* store timer */
		"	stckc	0xe0\n"		/* store clock comparator */
		"	stpx	0x108\n"	/* store prefix register */
		"	stam	0,15,0x120\n"	/* store access registers */
		"	std	0,0x160\n"	/* store f0 */
		"	std	2,0x168\n"	/* store f2 */
		"	std	4,0x170\n"	/* store f4 */
		"	std	6,0x178\n"	/* store f6 */
		"	stm	0,15,0x180\n"	/* store general registers */
		"	stctl	0,15,0x1c0\n"	/* store control registers */
		"	oi	0x1c0,0x10\n"	/* fake protection bit */
		"	lpsw	0(%1)"
		: "=m" (ctl_buf)
		: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
#else /* CONFIG_64BIT */
	asm volatile(
		"	stctg	0,0,0(%2)\n"
		"	ni	4(%2),0xef\n"	/* switch off protection */
		"	lctlg	0,0,0(%2)\n"
		"	lghi	1,0x1000\n"
		"	stpt	0x328(1)\n"	/* store timer */
		"	stckc	0x330(1)\n"	/* store clock comparator */
		"	stpx	0x318(1)\n"	/* store prefix register */
		"	stam	0,15,0x340(1)\n"/* store access registers */
		"	stfpc	0x31c(1)\n"	/* store fpu control */
		"	std	0,0x200(1)\n"	/* store f0 */
		"	std	1,0x208(1)\n"	/* store f1 */
		"	std	2,0x210(1)\n"	/* store f2 */
		"	std	3,0x218(1)\n"	/* store f3 */
		"	std	4,0x220(1)\n"	/* store f4 */
		"	std	5,0x228(1)\n"	/* store f5 */
		"	std	6,0x230(1)\n"	/* store f6 */
		"	std	7,0x238(1)\n"	/* store f7 */
		"	std	8,0x240(1)\n"	/* store f8 */
		"	std	9,0x248(1)\n"	/* store f9 */
		"	std	10,0x250(1)\n"	/* store f10 */
		"	std	11,0x258(1)\n"	/* store f11 */
		"	std	12,0x260(1)\n"	/* store f12 */
		"	std	13,0x268(1)\n"	/* store f13 */
		"	std	14,0x270(1)\n"	/* store f14 */
		"	std	15,0x278(1)\n"	/* store f15 */
		"	stmg	0,15,0x280(1)\n"/* store general registers */
		"	stctg	0,15,0x380(1)\n"/* store control registers */
		"	oi	0x384(1),0x10\n"/* fake protection bit */
		"	lpswe	0(%1)"
		: "=m" (ctl_buf)
		: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
#endif /* CONFIG_64BIT */
	while (1);
}

/*
 * Use to set psw mask except for the first byte which
 * won't be changed by this function.
 */
static inline void
__set_psw_mask(unsigned long mask)
{
	__load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
}

#define local_mcck_enable() \
	__set_psw_mask(psw_kernel_bits | PSW_MASK_DAT | PSW_MASK_MCHECK)
#define local_mcck_disable() \
	__set_psw_mask(psw_kernel_bits | PSW_MASK_DAT)

/*
 * Basic Machine Check/Program Check Handler.
 */

extern void s390_base_mcck_handler(void);
extern void s390_base_pgm_handler(void);
extern void s390_base_ext_handler(void);

extern void (*s390_base_mcck_handler_fn)(void);
extern void (*s390_base_pgm_handler_fn)(void);
extern void (*s390_base_ext_handler_fn)(void);

#define ARCH_LOW_ADDRESS_LIMIT	0x7fffffffUL

/*
 * Helper macro for exception table entries
 */
#ifndef CONFIG_64BIT
#define EX_TABLE(_fault,_target)			\
	".section __ex_table,\"a\"\n"			\
	"	.align 4\n"				\
	"	.long  " #_fault "," #_target "\n"	\
	".previous\n"
#else
#define EX_TABLE(_fault,_target)			\
	".section __ex_table,\"a\"\n"			\
	"	.align 8\n"				\
	"	.quad  " #_fault "," #_target "\n"	\
	".previous\n"
#endif

extern int memcpy_real(void *, void *, size_t);
extern void memcpy_absolute(void *, void *, size_t);

#define mem_assign_absolute(dest, val) {			\
	__typeof__(dest) __tmp = (val);				\
								\
	BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));		\
	memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));	\
}

#endif                                 /* __ASM_S390_PROCESSOR_H           */
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* S390 version
a53c8fab	3	* Copyright IBM Corp. 1999
1da177e4 LT	4	* Author(s): Hartmut Penner (hp@de.ibm.com),
	5	* Martin Schwidefsky (schwidefsky@de.ibm.com)
	6	*
	7	* Derived from "include/asm-i386/processor.h"
	8	* Copyright (C) 1994, Linus Torvalds
	9	*/
	10
	11	#ifndef __ASM_S390_PROCESSOR_H
	12	#define __ASM_S390_PROCESSOR_H
	13
edd53787	14	#include <linux/linkage.h>
a0616cde	15	#include <linux/irqflags.h>
e86a6ed6	16	#include <asm/cpu.h>
25097bf1	17	#include <asm/page.h>
1da177e4	18	#include <asm/ptrace.h>
25097bf1	19	#include <asm/setup.h>
1da177e4	20
1da177e4 LT	21	/*
	22	* Default implementation of macro that returns current
	23	* instruction pointer ("program counter").
	24	*/
94c12cc7	25	#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
1da177e4	26
e86a6ed6	27	static inline void get_cpu_id(struct cpuid *ptr)
72960a02	28	{
987bcdac	29	asm volatile("stidp %0" : "=Q" (*ptr));
72960a02 MH	30	}
72960a02 MH	31
31ee4b2f	32	extern void s390_adjust_jiffies(void);
638ad34a MS	33	extern const struct seq_operations cpuinfo_op;
638ad34a MS	34	extern int sysctl_ieee_emulation_warnings;
1da177e4	35
1da177e4	36	/*
f481bfaf	37	* User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
1da177e4	38	*/
f4815ac6	39	#ifndef CONFIG_64BIT
1da177e4	40
5a216a20 MS	41	#define TASK_SIZE (1UL << 31)
5a216a20 MS	42	#define TASK_UNMAPPED_BASE (1UL << 30)
1da177e4	43
f4815ac6	44	#else /* CONFIG_64BIT */
1da177e4	45
f481bfaf	46	#define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit)
5a216a20 MS	47	#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
	48	(1UL << 30) : (1UL << 41))
	49	#define TASK_SIZE TASK_SIZE_OF(current)
1da177e4	50
f4815ac6	51	#endif /* CONFIG_64BIT */
1da177e4	52
f4815ac6	53	#ifndef CONFIG_64BIT
5a216a20	54	#define STACK_TOP (1UL << 31)
6252d702	55	#define STACK_TOP_MAX (1UL << 31)
f4815ac6	56	#else /* CONFIG_64BIT */
6252d702 MS	57	#define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
6252d702 MS	58	#define STACK_TOP_MAX (1UL << 42)
f4815ac6	59	#endif /* CONFIG_64BIT */
922a70d3	60
1da177e4 LT	61	#define HAVE_ARCH_PICK_MMAP_LAYOUT
	62
	63	typedef struct {
	64	__u32 ar4;
	65	} mm_segment_t;
	66
	67	/*
	68	* Thread structure
	69	*/
	70	struct thread_struct {
	71	s390_fp_regs fp_regs;
	72	unsigned int acrs[NUM_ACRS];
	73	unsigned long ksp; /* kernel stack pointer */
1da177e4	74	mm_segment_t mm_segment;
e5992f2e	75	unsigned long gmap_addr; /* address of last gmap fault. */
5e9a2692 MS	76	struct per_regs per_user; /* User specified PER registers */
5e9a2692 MS	77	struct per_event per_event; /* Cause of the last PER trap */
1da177e4 LT	78	/* pfault_wait is used to block the process on a pfault event */
1da177e4 LT	79	unsigned long pfault_wait;
f2db2e6c	80	struct list_head list;
1da177e4 LT	81	};
	82
	83	typedef struct thread_struct thread_struct;
	84
	85	/*
	86	* Stack layout of a C stack frame.
	87	*/
	88	#ifndef __PACK_STACK
	89	struct stack_frame {
	90	unsigned long back_chain;
	91	unsigned long empty1[5];
	92	unsigned long gprs[10];
	93	unsigned int empty2[8];
	94	};
	95	#else
	96	struct stack_frame {
	97	unsigned long empty1[5];
	98	unsigned int empty2[8];
	99	unsigned long gprs[10];
	100	unsigned long back_chain;
	101	};
	102	#endif
	103
	104	#define ARCH_MIN_TASKALIGN 8
	105
6f3fa3f0 MS	106	#define INIT_THREAD { \
	107	.ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
	108	}
1da177e4 LT	109
	110	/*
	111	* Do necessary setup to start up a new thread.
	112	*/
b50511e4 MS	113	#define start_thread(regs, new_psw, new_stackp) do { \
	114	regs->psw.mask = psw_user_bits \| PSW_MASK_EA \| PSW_MASK_BA; \
	115	regs->psw.addr = new_psw \| PSW_ADDR_AMODE; \
	116	regs->gprs[15] = new_stackp; \
63506c41 MS	117	} while (0)
63506c41 MS	118
b50511e4 MS	119	#define start_thread31(regs, new_psw, new_stackp) do { \
	120	regs->psw.mask = psw_user_bits \| PSW_MASK_BA; \
	121	regs->psw.addr = new_psw \| PSW_ADDR_AMODE; \
	122	regs->gprs[15] = new_stackp; \
	123	crst_table_downgrade(current->mm, 1UL << 31); \
1da177e4 LT	124	} while (0)
1da177e4 LT	125
1da177e4 LT	126	/* Forward declaration, a strange C thing */
	127	struct task_struct;
	128	struct mm_struct;
df5f8314	129	struct seq_file;
1da177e4 LT	130
	131	/* Free all resources held by a thread. */
	132	extern void release_thread(struct task_struct *);
	133	extern int kernel_thread(int (fn)(void ), void * arg, unsigned long flags);
	134
1da177e4 LT	135	/*
	136	* Return saved PC of a blocked thread.
	137	*/
	138	extern unsigned long thread_saved_pc(struct task_struct *t);
	139
bb11e3bd	140	extern void show_code(struct pt_regs *regs);
1da177e4 LT	141
1da177e4 LT	142	unsigned long get_wchan(struct task_struct *p);
c7584fb6	143	#define task_pt_regs(tsk) ((struct pt_regs *) \
30af7120	144	(task_stack_page(tsk) + THREAD_SIZE) - 1)
c7584fb6 AV	145	#define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
c7584fb6 AV	146	#define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
1da177e4	147
a0616cde DH	148	static inline unsigned short stap(void)
	149	{
	150	unsigned short cpu_address;
	151
	152	asm volatile("stap %0" : "=m" (cpu_address));
	153	return cpu_address;
	154	}
	155
1da177e4 LT	156	/*
	157	* Give up the time slice of the virtual PU.
	158	*/
abdba61a HC	159	static inline void cpu_relax(void)
	160	{
	161	if (MACHINE_HAS_DIAG44)
c48e0913 HC	162	asm volatile("diag 0,0,68");
c48e0913 HC	163	barrier();
abdba61a	164	}
1da177e4	165
dc74d7f9 HC	166	static inline void psw_set_key(unsigned int key)
	167	{
	168	asm volatile("spka 0(%0)" : : "d" (key));
	169	}
	170
77fa2245 HC	171	/*
	172	* Set PSW to specified value.
	173	*/
	174	static inline void __load_psw(psw_t psw)
	175	{
f4815ac6	176	#ifndef CONFIG_64BIT
987bcdac	177	asm volatile("lpsw %0" : : "Q" (psw) : "cc");
77fa2245	178	#else
987bcdac	179	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
77fa2245 HC	180	#endif
	181	}
	182
1da177e4 LT	183	/*
	184	* Set PSW mask to specified value, while leaving the
	185	* PSW addr pointing to the next instruction.
	186	*/
1da177e4 LT	187	static inline void __load_psw_mask (unsigned long mask)
	188	{
	189	unsigned long addr;
1da177e4	190	psw_t psw;
77fa2245	191
1da177e4 LT	192	psw.mask = mask;
1da177e4 LT	193
f4815ac6	194	#ifndef CONFIG_64BIT
94c12cc7 MS	195	asm volatile(
	196	" basr %0,0\n"
	197	"0: ahi %0,1f-0b\n"
987bcdac MS	198	" st %0,%O1+4(%R1)\n"
987bcdac MS	199	" lpsw %1\n"
1da177e4	200	"1:"
987bcdac	201	: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
f4815ac6	202	#else /* CONFIG_64BIT */
94c12cc7 MS	203	asm volatile(
94c12cc7 MS	204	" larl %0,1f\n"
987bcdac MS	205	" stg %0,%O1+8(%R1)\n"
987bcdac MS	206	" lpswe %1\n"
1da177e4	207	"1:"
987bcdac	208	: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
f4815ac6	209	#endif /* CONFIG_64BIT */
1da177e4	210	}
ccf45caf MS	211
	212	/*
	213	* Rewind PSW instruction address by specified number of bytes.
	214	*/
	215	static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
	216	{
f4815ac6	217	#ifndef CONFIG_64BIT
ccf45caf MS	218	if (psw.addr & PSW_ADDR_AMODE)
	219	/* 31 bit mode */
	220	return (psw.addr - ilc) \| PSW_ADDR_AMODE;
	221	/* 24 bit mode */
	222	return (psw.addr - ilc) & ((1UL << 24) - 1);
	223	#else
	224	unsigned long mask;
	225
	226	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
	227	(psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
	228	(1UL << 24) - 1;
	229	return (psw.addr - ilc) & mask;
	230	#endif
	231	}
1da177e4	232
1da177e4 LT	233	/*
	234	* Function to drop a processor into disabled wait state
	235	*/
ff2d8b19	236	static inline void __noreturn disabled_wait(unsigned long code)
1da177e4	237	{
1da177e4	238	unsigned long ctl_buf;
77fa2245	239	psw_t dw_psw;
1da177e4	240
b50511e4	241	dw_psw.mask = PSW_MASK_BASE \| PSW_MASK_WAIT \| PSW_MASK_BA \| PSW_MASK_EA;
77fa2245	242	dw_psw.addr = code;
1da177e4 LT	243	/*
	244	* Store status and then load disabled wait psw,
	245	* the processor is dead afterwards
	246	*/
f4815ac6	247	#ifndef CONFIG_64BIT
94c12cc7 MS	248	asm volatile(
	249	" stctl 0,0,0(%2)\n"
	250	" ni 0(%2),0xef\n" /* switch off protection */
	251	" lctl 0,0,0(%2)\n"
	252	" stpt 0xd8\n" /* store timer */
	253	" stckc 0xe0\n" /* store clock comparator */
	254	" stpx 0x108\n" /* store prefix register */
	255	" stam 0,15,0x120\n" /* store access registers */
	256	" std 0,0x160\n" /* store f0 */
	257	" std 2,0x168\n" /* store f2 */
	258	" std 4,0x170\n" /* store f4 */
	259	" std 6,0x178\n" /* store f6 */
	260	" stm 0,15,0x180\n" /* store general registers */
	261	" stctl 0,15,0x1c0\n" /* store control registers */
	262	" oi 0x1c0,0x10\n" /* fake protection bit */
	263	" lpsw 0(%1)"
	264	: "=m" (ctl_buf)
	265	: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
f4815ac6	266	#else /* CONFIG_64BIT */
94c12cc7 MS	267	asm volatile(
	268	" stctg 0,0,0(%2)\n"
	269	" ni 4(%2),0xef\n" /* switch off protection */
	270	" lctlg 0,0,0(%2)\n"
	271	" lghi 1,0x1000\n"
	272	" stpt 0x328(1)\n" /* store timer */
	273	" stckc 0x330(1)\n" /* store clock comparator */
	274	" stpx 0x318(1)\n" /* store prefix register */
	275	" stam 0,15,0x340(1)\n"/* store access registers */
	276	" stfpc 0x31c(1)\n" /* store fpu control */
	277	" std 0,0x200(1)\n" /* store f0 */
	278	" std 1,0x208(1)\n" /* store f1 */
	279	" std 2,0x210(1)\n" /* store f2 */
	280	" std 3,0x218(1)\n" /* store f3 */
	281	" std 4,0x220(1)\n" /* store f4 */
	282	" std 5,0x228(1)\n" /* store f5 */
	283	" std 6,0x230(1)\n" /* store f6 */
	284	" std 7,0x238(1)\n" /* store f7 */
	285	" std 8,0x240(1)\n" /* store f8 */
	286	" std 9,0x248(1)\n" /* store f9 */
	287	" std 10,0x250(1)\n" /* store f10 */
	288	" std 11,0x258(1)\n" /* store f11 */
	289	" std 12,0x260(1)\n" /* store f12 */
	290	" std 13,0x268(1)\n" /* store f13 */
	291	" std 14,0x270(1)\n" /* store f14 */
	292	" std 15,0x278(1)\n" /* store f15 */
	293	" stmg 0,15,0x280(1)\n"/* store general registers */
	294	" stctg 0,15,0x380(1)\n"/* store control registers */
	295	" oi 0x384(1),0x10\n"/* fake protection bit */
	296	" lpswe 0(%1)"
	297	: "=m" (ctl_buf)
bdd42b28	298	: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
f4815ac6	299	#endif /* CONFIG_64BIT */
edd53787	300	while (1);
1da177e4 LT	301	}
1da177e4 LT	302
a0616cde DH	303	/*
	304	* Use to set psw mask except for the first byte which
	305	* won't be changed by this function.
	306	*/
	307	static inline void
	308	__set_psw_mask(unsigned long mask)
	309	{
	310	__load_psw_mask(mask \| (arch_local_save_flags() & ~(-1UL >> 8)));
	311	}
	312
	313	#define local_mcck_enable() \
	314	__set_psw_mask(psw_kernel_bits \| PSW_MASK_DAT \| PSW_MASK_MCHECK)
	315	#define local_mcck_disable() \
	316	__set_psw_mask(psw_kernel_bits \| PSW_MASK_DAT)
	317
ab14de6c HC	318	/*
	319	* Basic Machine Check/Program Check Handler.
	320	*/
	321
	322	extern void s390_base_mcck_handler(void);
	323	extern void s390_base_pgm_handler(void);
	324	extern void s390_base_ext_handler(void);
	325
	326	extern void (*s390_base_mcck_handler_fn)(void);
	327	extern void (*s390_base_pgm_handler_fn)(void);
	328	extern void (*s390_base_ext_handler_fn)(void);
	329
dfd54cbc HC	330	#define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
dfd54cbc HC	331
de1a3f1c MS	332	/*
	333	* Helper macro for exception table entries
	334	*/
f4815ac6	335	#ifndef CONFIG_64BIT
de1a3f1c MS	336	#define EX_TABLE(_fault,_target) \
	337	".section __ex_table,\"a\"\n" \
	338	" .align 4\n" \
	339	" .long " #_fault "," #_target "\n" \
	340	".previous\n"
	341	#else
	342	#define EX_TABLE(_fault,_target) \
	343	".section __ex_table,\"a\"\n" \
	344	" .align 8\n" \
	345	" .quad " #_fault "," #_target "\n" \
	346	".previous\n"
	347	#endif
	348
fbe76568 HC	349	extern int memcpy_real(void , void , size_t);
	350	extern void memcpy_absolute(void , void , size_t);
	351
	352	#define mem_assign_absolute(dest, val) { \
	353	__typeof__(dest) __tmp = (val); \
	354	\
	355	BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \
	356	memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \
	357	}
	358
1da177e4	359	#endif /* __ASM_S390_PROCESSOR_H */