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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/spi/spi.h> | |
28 | #include <linux/workqueue.h> | |
e0c9905e | 29 | #include <linux/delay.h> |
2f1a74e5 | 30 | #include <linux/clk.h> |
e0c9905e SS |
31 | |
32 | #include <asm/io.h> | |
33 | #include <asm/irq.h> | |
e0c9905e | 34 | #include <asm/delay.h> |
e0c9905e | 35 | |
dcea83ad | 36 | #include <mach/dma.h> |
a09e64fb RK |
37 | #include <mach/regs-ssp.h> |
38 | #include <mach/ssp.h> | |
39 | #include <mach/pxa2xx_spi.h> | |
e0c9905e SS |
40 | |
41 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 42 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 43 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 44 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e SS |
45 | |
46 | #define MAX_BUSES 3 | |
47 | ||
f1f640a9 VS |
48 | #define RX_THRESH_DFLT 8 |
49 | #define TX_THRESH_DFLT 8 | |
50 | #define TIMOUT_DFLT 1000 | |
51 | ||
7e964455 NF |
52 | #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR) |
53 | #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK) | |
20b918dc | 54 | #define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0) |
7e964455 | 55 | #define MAX_DMA_LEN 8191 |
e0c9905e | 56 | |
b97c74bd NF |
57 | /* |
58 | * for testing SSCR1 changes that require SSP restart, basically | |
59 | * everything except the service and interrupt enables, the pxa270 developer | |
60 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
61 | * list, but the PXA255 dev man says all bits without really meaning the | |
62 | * service and interrupt enables | |
63 | */ | |
64 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 65 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
66 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
67 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
68 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
69 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 70 | |
e0c9905e | 71 | #define DEFINE_SSP_REG(reg, off) \ |
cf43369d DB |
72 | static inline u32 read_##reg(void const __iomem *p) \ |
73 | { return __raw_readl(p + (off)); } \ | |
74 | \ | |
75 | static inline void write_##reg(u32 v, void __iomem *p) \ | |
76 | { __raw_writel(v, p + (off)); } | |
e0c9905e SS |
77 | |
78 | DEFINE_SSP_REG(SSCR0, 0x00) | |
79 | DEFINE_SSP_REG(SSCR1, 0x04) | |
80 | DEFINE_SSP_REG(SSSR, 0x08) | |
81 | DEFINE_SSP_REG(SSITR, 0x0c) | |
82 | DEFINE_SSP_REG(SSDR, 0x10) | |
83 | DEFINE_SSP_REG(SSTO, 0x28) | |
84 | DEFINE_SSP_REG(SSPSP, 0x2c) | |
85 | ||
86 | #define START_STATE ((void*)0) | |
87 | #define RUNNING_STATE ((void*)1) | |
88 | #define DONE_STATE ((void*)2) | |
89 | #define ERROR_STATE ((void*)-1) | |
90 | ||
91 | #define QUEUE_RUNNING 0 | |
92 | #define QUEUE_STOPPED 1 | |
93 | ||
94 | struct driver_data { | |
95 | /* Driver model hookup */ | |
96 | struct platform_device *pdev; | |
97 | ||
2f1a74e5 | 98 | /* SSP Info */ |
99 | struct ssp_device *ssp; | |
100 | ||
e0c9905e SS |
101 | /* SPI framework hookup */ |
102 | enum pxa_ssp_type ssp_type; | |
103 | struct spi_master *master; | |
104 | ||
105 | /* PXA hookup */ | |
106 | struct pxa2xx_spi_master *master_info; | |
107 | ||
108 | /* DMA setup stuff */ | |
109 | int rx_channel; | |
110 | int tx_channel; | |
111 | u32 *null_dma_buf; | |
112 | ||
113 | /* SSP register addresses */ | |
cf43369d | 114 | void __iomem *ioaddr; |
e0c9905e SS |
115 | u32 ssdr_physical; |
116 | ||
117 | /* SSP masks*/ | |
118 | u32 dma_cr1; | |
119 | u32 int_cr1; | |
120 | u32 clear_sr; | |
121 | u32 mask_sr; | |
122 | ||
123 | /* Driver message queue */ | |
124 | struct workqueue_struct *workqueue; | |
125 | struct work_struct pump_messages; | |
126 | spinlock_t lock; | |
127 | struct list_head queue; | |
128 | int busy; | |
129 | int run; | |
130 | ||
131 | /* Message Transfer pump */ | |
132 | struct tasklet_struct pump_transfers; | |
133 | ||
134 | /* Current message transfer state info */ | |
135 | struct spi_message* cur_msg; | |
136 | struct spi_transfer* cur_transfer; | |
137 | struct chip_data *cur_chip; | |
138 | size_t len; | |
139 | void *tx; | |
140 | void *tx_end; | |
141 | void *rx; | |
142 | void *rx_end; | |
143 | int dma_mapped; | |
144 | dma_addr_t rx_dma; | |
145 | dma_addr_t tx_dma; | |
146 | size_t rx_map_len; | |
147 | size_t tx_map_len; | |
9708c121 SS |
148 | u8 n_bytes; |
149 | u32 dma_width; | |
8d94cc50 SS |
150 | int (*write)(struct driver_data *drv_data); |
151 | int (*read)(struct driver_data *drv_data); | |
e0c9905e SS |
152 | irqreturn_t (*transfer_handler)(struct driver_data *drv_data); |
153 | void (*cs_control)(u32 command); | |
154 | }; | |
155 | ||
156 | struct chip_data { | |
157 | u32 cr0; | |
158 | u32 cr1; | |
e0c9905e SS |
159 | u32 psp; |
160 | u32 timeout; | |
161 | u8 n_bytes; | |
162 | u32 dma_width; | |
163 | u32 dma_burst_size; | |
164 | u32 threshold; | |
165 | u32 dma_threshold; | |
166 | u8 enable_dma; | |
9708c121 SS |
167 | u8 bits_per_word; |
168 | u32 speed_hz; | |
8d94cc50 SS |
169 | int (*write)(struct driver_data *drv_data); |
170 | int (*read)(struct driver_data *drv_data); | |
e0c9905e SS |
171 | void (*cs_control)(u32 command); |
172 | }; | |
173 | ||
6d5aefb8 | 174 | static void pump_messages(struct work_struct *work); |
e0c9905e SS |
175 | |
176 | static int flush(struct driver_data *drv_data) | |
177 | { | |
178 | unsigned long limit = loops_per_jiffy << 1; | |
179 | ||
cf43369d | 180 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
181 | |
182 | do { | |
183 | while (read_SSSR(reg) & SSSR_RNE) { | |
184 | read_SSDR(reg); | |
185 | } | |
186 | } while ((read_SSSR(reg) & SSSR_BSY) && limit--); | |
187 | write_SSSR(SSSR_ROR, reg); | |
188 | ||
189 | return limit; | |
190 | } | |
191 | ||
e0c9905e SS |
192 | static void null_cs_control(u32 command) |
193 | { | |
194 | } | |
195 | ||
8d94cc50 | 196 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 197 | { |
cf43369d | 198 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 199 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 200 | |
8d94cc50 SS |
201 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
202 | || (drv_data->tx == drv_data->tx_end)) | |
203 | return 0; | |
204 | ||
205 | write_SSDR(0, reg); | |
206 | drv_data->tx += n_bytes; | |
207 | ||
208 | return 1; | |
e0c9905e SS |
209 | } |
210 | ||
8d94cc50 | 211 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 212 | { |
cf43369d | 213 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 214 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e SS |
215 | |
216 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 217 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
218 | read_SSDR(reg); |
219 | drv_data->rx += n_bytes; | |
220 | } | |
8d94cc50 SS |
221 | |
222 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
223 | } |
224 | ||
8d94cc50 | 225 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 226 | { |
cf43369d | 227 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 228 | |
8d94cc50 SS |
229 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
230 | || (drv_data->tx == drv_data->tx_end)) | |
231 | return 0; | |
232 | ||
233 | write_SSDR(*(u8 *)(drv_data->tx), reg); | |
234 | ++drv_data->tx; | |
235 | ||
236 | return 1; | |
e0c9905e SS |
237 | } |
238 | ||
8d94cc50 | 239 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 240 | { |
cf43369d | 241 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
242 | |
243 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 244 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
245 | *(u8 *)(drv_data->rx) = read_SSDR(reg); |
246 | ++drv_data->rx; | |
247 | } | |
8d94cc50 SS |
248 | |
249 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
250 | } |
251 | ||
8d94cc50 | 252 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 253 | { |
cf43369d | 254 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 255 | |
8d94cc50 SS |
256 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
257 | || (drv_data->tx == drv_data->tx_end)) | |
258 | return 0; | |
259 | ||
260 | write_SSDR(*(u16 *)(drv_data->tx), reg); | |
261 | drv_data->tx += 2; | |
262 | ||
263 | return 1; | |
e0c9905e SS |
264 | } |
265 | ||
8d94cc50 | 266 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 267 | { |
cf43369d | 268 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
269 | |
270 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 271 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
272 | *(u16 *)(drv_data->rx) = read_SSDR(reg); |
273 | drv_data->rx += 2; | |
274 | } | |
8d94cc50 SS |
275 | |
276 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 277 | } |
8d94cc50 SS |
278 | |
279 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 280 | { |
cf43369d | 281 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 282 | |
8d94cc50 SS |
283 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
284 | || (drv_data->tx == drv_data->tx_end)) | |
285 | return 0; | |
286 | ||
287 | write_SSDR(*(u32 *)(drv_data->tx), reg); | |
288 | drv_data->tx += 4; | |
289 | ||
290 | return 1; | |
e0c9905e SS |
291 | } |
292 | ||
8d94cc50 | 293 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 294 | { |
cf43369d | 295 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
296 | |
297 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 298 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
299 | *(u32 *)(drv_data->rx) = read_SSDR(reg); |
300 | drv_data->rx += 4; | |
301 | } | |
8d94cc50 SS |
302 | |
303 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
304 | } |
305 | ||
306 | static void *next_transfer(struct driver_data *drv_data) | |
307 | { | |
308 | struct spi_message *msg = drv_data->cur_msg; | |
309 | struct spi_transfer *trans = drv_data->cur_transfer; | |
310 | ||
311 | /* Move to next transfer */ | |
312 | if (trans->transfer_list.next != &msg->transfers) { | |
313 | drv_data->cur_transfer = | |
314 | list_entry(trans->transfer_list.next, | |
315 | struct spi_transfer, | |
316 | transfer_list); | |
317 | return RUNNING_STATE; | |
318 | } else | |
319 | return DONE_STATE; | |
320 | } | |
321 | ||
322 | static int map_dma_buffers(struct driver_data *drv_data) | |
323 | { | |
324 | struct spi_message *msg = drv_data->cur_msg; | |
325 | struct device *dev = &msg->spi->dev; | |
326 | ||
327 | if (!drv_data->cur_chip->enable_dma) | |
328 | return 0; | |
329 | ||
330 | if (msg->is_dma_mapped) | |
331 | return drv_data->rx_dma && drv_data->tx_dma; | |
332 | ||
333 | if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx)) | |
334 | return 0; | |
335 | ||
336 | /* Modify setup if rx buffer is null */ | |
337 | if (drv_data->rx == NULL) { | |
338 | *drv_data->null_dma_buf = 0; | |
339 | drv_data->rx = drv_data->null_dma_buf; | |
340 | drv_data->rx_map_len = 4; | |
341 | } else | |
342 | drv_data->rx_map_len = drv_data->len; | |
343 | ||
344 | ||
345 | /* Modify setup if tx buffer is null */ | |
346 | if (drv_data->tx == NULL) { | |
347 | *drv_data->null_dma_buf = 0; | |
348 | drv_data->tx = drv_data->null_dma_buf; | |
349 | drv_data->tx_map_len = 4; | |
350 | } else | |
351 | drv_data->tx_map_len = drv_data->len; | |
352 | ||
393df744 NF |
353 | /* Stream map the tx buffer. Always do DMA_TO_DEVICE first |
354 | * so we flush the cache *before* invalidating it, in case | |
355 | * the tx and rx buffers overlap. | |
356 | */ | |
e0c9905e | 357 | drv_data->tx_dma = dma_map_single(dev, drv_data->tx, |
393df744 NF |
358 | drv_data->tx_map_len, DMA_TO_DEVICE); |
359 | if (dma_mapping_error(dev, drv_data->tx_dma)) | |
360 | return 0; | |
e0c9905e | 361 | |
393df744 NF |
362 | /* Stream map the rx buffer */ |
363 | drv_data->rx_dma = dma_map_single(dev, drv_data->rx, | |
e0c9905e | 364 | drv_data->rx_map_len, DMA_FROM_DEVICE); |
393df744 NF |
365 | if (dma_mapping_error(dev, drv_data->rx_dma)) { |
366 | dma_unmap_single(dev, drv_data->tx_dma, | |
367 | drv_data->tx_map_len, DMA_TO_DEVICE); | |
e0c9905e SS |
368 | return 0; |
369 | } | |
370 | ||
371 | return 1; | |
372 | } | |
373 | ||
374 | static void unmap_dma_buffers(struct driver_data *drv_data) | |
375 | { | |
376 | struct device *dev; | |
377 | ||
378 | if (!drv_data->dma_mapped) | |
379 | return; | |
380 | ||
381 | if (!drv_data->cur_msg->is_dma_mapped) { | |
382 | dev = &drv_data->cur_msg->spi->dev; | |
383 | dma_unmap_single(dev, drv_data->rx_dma, | |
384 | drv_data->rx_map_len, DMA_FROM_DEVICE); | |
385 | dma_unmap_single(dev, drv_data->tx_dma, | |
386 | drv_data->tx_map_len, DMA_TO_DEVICE); | |
387 | } | |
388 | ||
389 | drv_data->dma_mapped = 0; | |
390 | } | |
391 | ||
392 | /* caller already set message->status; dma and pio irqs are blocked */ | |
5daa3ba0 | 393 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
394 | { |
395 | struct spi_transfer* last_transfer; | |
5daa3ba0 SS |
396 | unsigned long flags; |
397 | struct spi_message *msg; | |
e0c9905e | 398 | |
5daa3ba0 SS |
399 | spin_lock_irqsave(&drv_data->lock, flags); |
400 | msg = drv_data->cur_msg; | |
401 | drv_data->cur_msg = NULL; | |
402 | drv_data->cur_transfer = NULL; | |
403 | drv_data->cur_chip = NULL; | |
404 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
405 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
406 | ||
407 | last_transfer = list_entry(msg->transfers.prev, | |
e0c9905e SS |
408 | struct spi_transfer, |
409 | transfer_list); | |
410 | ||
8423597d NF |
411 | /* Delay if requested before any change in chip select */ |
412 | if (last_transfer->delay_usecs) | |
413 | udelay(last_transfer->delay_usecs); | |
414 | ||
415 | /* Drop chip select UNLESS cs_change is true or we are returning | |
416 | * a message with an error, or next message is for another chip | |
417 | */ | |
e0c9905e SS |
418 | if (!last_transfer->cs_change) |
419 | drv_data->cs_control(PXA2XX_CS_DEASSERT); | |
8423597d NF |
420 | else { |
421 | struct spi_message *next_msg; | |
422 | ||
423 | /* Holding of cs was hinted, but we need to make sure | |
424 | * the next message is for the same chip. Don't waste | |
425 | * time with the following tests unless this was hinted. | |
426 | * | |
427 | * We cannot postpone this until pump_messages, because | |
428 | * after calling msg->complete (below) the driver that | |
429 | * sent the current message could be unloaded, which | |
430 | * could invalidate the cs_control() callback... | |
431 | */ | |
432 | ||
433 | /* get a pointer to the next message, if any */ | |
434 | spin_lock_irqsave(&drv_data->lock, flags); | |
435 | if (list_empty(&drv_data->queue)) | |
436 | next_msg = NULL; | |
437 | else | |
438 | next_msg = list_entry(drv_data->queue.next, | |
439 | struct spi_message, queue); | |
440 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
441 | ||
442 | /* see if the next and current messages point | |
443 | * to the same chip | |
444 | */ | |
445 | if (next_msg && next_msg->spi != msg->spi) | |
446 | next_msg = NULL; | |
447 | if (!next_msg || msg->state == ERROR_STATE) | |
448 | drv_data->cs_control(PXA2XX_CS_DEASSERT); | |
449 | } | |
e0c9905e | 450 | |
5daa3ba0 SS |
451 | msg->state = NULL; |
452 | if (msg->complete) | |
453 | msg->complete(msg->context); | |
e0c9905e SS |
454 | } |
455 | ||
cf43369d | 456 | static int wait_ssp_rx_stall(void const __iomem *ioaddr) |
e0c9905e SS |
457 | { |
458 | unsigned long limit = loops_per_jiffy << 1; | |
459 | ||
460 | while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--) | |
461 | cpu_relax(); | |
462 | ||
463 | return limit; | |
464 | } | |
465 | ||
466 | static int wait_dma_channel_stop(int channel) | |
467 | { | |
468 | unsigned long limit = loops_per_jiffy << 1; | |
469 | ||
470 | while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--) | |
471 | cpu_relax(); | |
472 | ||
473 | return limit; | |
474 | } | |
475 | ||
cf43369d | 476 | static void dma_error_stop(struct driver_data *drv_data, const char *msg) |
e0c9905e | 477 | { |
cf43369d | 478 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 479 | |
8d94cc50 SS |
480 | /* Stop and reset */ |
481 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
482 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
483 | write_SSSR(drv_data->clear_sr, reg); | |
484 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | |
485 | if (drv_data->ssp_type != PXA25x_SSP) | |
486 | write_SSTO(0, reg); | |
487 | flush(drv_data); | |
488 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
e0c9905e | 489 | |
8d94cc50 | 490 | unmap_dma_buffers(drv_data); |
e0c9905e | 491 | |
8d94cc50 | 492 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 493 | |
8d94cc50 SS |
494 | drv_data->cur_msg->state = ERROR_STATE; |
495 | tasklet_schedule(&drv_data->pump_transfers); | |
496 | } | |
497 | ||
498 | static void dma_transfer_complete(struct driver_data *drv_data) | |
499 | { | |
cf43369d | 500 | void __iomem *reg = drv_data->ioaddr; |
8d94cc50 SS |
501 | struct spi_message *msg = drv_data->cur_msg; |
502 | ||
503 | /* Clear and disable interrupts on SSP and DMA channels*/ | |
504 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | |
505 | write_SSSR(drv_data->clear_sr, reg); | |
506 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
507 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
508 | ||
509 | if (wait_dma_channel_stop(drv_data->rx_channel) == 0) | |
510 | dev_err(&drv_data->pdev->dev, | |
511 | "dma_handler: dma rx channel stop failed\n"); | |
512 | ||
513 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | |
514 | dev_err(&drv_data->pdev->dev, | |
515 | "dma_transfer: ssp rx stall failed\n"); | |
516 | ||
517 | unmap_dma_buffers(drv_data); | |
518 | ||
519 | /* update the buffer pointer for the amount completed in dma */ | |
520 | drv_data->rx += drv_data->len - | |
521 | (DCMD(drv_data->rx_channel) & DCMD_LENGTH); | |
522 | ||
523 | /* read trailing data from fifo, it does not matter how many | |
524 | * bytes are in the fifo just read until buffer is full | |
525 | * or fifo is empty, which ever occurs first */ | |
526 | drv_data->read(drv_data); | |
527 | ||
528 | /* return count of what was actually read */ | |
529 | msg->actual_length += drv_data->len - | |
530 | (drv_data->rx_end - drv_data->rx); | |
531 | ||
8423597d NF |
532 | /* Transfer delays and chip select release are |
533 | * handled in pump_transfers or giveback | |
534 | */ | |
8d94cc50 SS |
535 | |
536 | /* Move to next transfer */ | |
537 | msg->state = next_transfer(drv_data); | |
538 | ||
539 | /* Schedule transfer tasklet */ | |
540 | tasklet_schedule(&drv_data->pump_transfers); | |
541 | } | |
542 | ||
543 | static void dma_handler(int channel, void *data) | |
544 | { | |
545 | struct driver_data *drv_data = data; | |
546 | u32 irq_status = DCSR(channel) & DMA_INT_MASK; | |
547 | ||
548 | if (irq_status & DCSR_BUSERR) { | |
e0c9905e SS |
549 | |
550 | if (channel == drv_data->tx_channel) | |
8d94cc50 SS |
551 | dma_error_stop(drv_data, |
552 | "dma_handler: " | |
553 | "bad bus address on tx channel"); | |
e0c9905e | 554 | else |
8d94cc50 SS |
555 | dma_error_stop(drv_data, |
556 | "dma_handler: " | |
557 | "bad bus address on rx channel"); | |
558 | return; | |
e0c9905e SS |
559 | } |
560 | ||
561 | /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */ | |
8d94cc50 SS |
562 | if ((channel == drv_data->tx_channel) |
563 | && (irq_status & DCSR_ENDINTR) | |
564 | && (drv_data->ssp_type == PXA25x_SSP)) { | |
e0c9905e SS |
565 | |
566 | /* Wait for rx to stall */ | |
567 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | |
568 | dev_err(&drv_data->pdev->dev, | |
569 | "dma_handler: ssp rx stall failed\n"); | |
570 | ||
8d94cc50 SS |
571 | /* finish this transfer, start the next */ |
572 | dma_transfer_complete(drv_data); | |
e0c9905e SS |
573 | } |
574 | } | |
575 | ||
576 | static irqreturn_t dma_transfer(struct driver_data *drv_data) | |
577 | { | |
578 | u32 irq_status; | |
cf43369d | 579 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
580 | |
581 | irq_status = read_SSSR(reg) & drv_data->mask_sr; | |
582 | if (irq_status & SSSR_ROR) { | |
8d94cc50 | 583 | dma_error_stop(drv_data, "dma_transfer: fifo overrun"); |
e0c9905e SS |
584 | return IRQ_HANDLED; |
585 | } | |
586 | ||
587 | /* Check for false positive timeout */ | |
8d94cc50 SS |
588 | if ((irq_status & SSSR_TINT) |
589 | && (DCSR(drv_data->tx_channel) & DCSR_RUN)) { | |
e0c9905e SS |
590 | write_SSSR(SSSR_TINT, reg); |
591 | return IRQ_HANDLED; | |
592 | } | |
593 | ||
594 | if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) { | |
595 | ||
8d94cc50 SS |
596 | /* Clear and disable timeout interrupt, do the rest in |
597 | * dma_transfer_complete */ | |
e0c9905e SS |
598 | if (drv_data->ssp_type != PXA25x_SSP) |
599 | write_SSTO(0, reg); | |
e0c9905e | 600 | |
8d94cc50 SS |
601 | /* finish this transfer, start the next */ |
602 | dma_transfer_complete(drv_data); | |
e0c9905e SS |
603 | |
604 | return IRQ_HANDLED; | |
605 | } | |
606 | ||
607 | /* Opps problem detected */ | |
608 | return IRQ_NONE; | |
609 | } | |
610 | ||
8d94cc50 | 611 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 612 | { |
cf43369d | 613 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 614 | |
8d94cc50 SS |
615 | /* Stop and reset SSP */ |
616 | write_SSSR(drv_data->clear_sr, reg); | |
617 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
618 | if (drv_data->ssp_type != PXA25x_SSP) | |
619 | write_SSTO(0, reg); | |
620 | flush(drv_data); | |
621 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
e0c9905e | 622 | |
8d94cc50 | 623 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 624 | |
8d94cc50 SS |
625 | drv_data->cur_msg->state = ERROR_STATE; |
626 | tasklet_schedule(&drv_data->pump_transfers); | |
627 | } | |
5daa3ba0 | 628 | |
8d94cc50 SS |
629 | static void int_transfer_complete(struct driver_data *drv_data) |
630 | { | |
cf43369d | 631 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 632 | |
8d94cc50 SS |
633 | /* Stop SSP */ |
634 | write_SSSR(drv_data->clear_sr, reg); | |
635 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
636 | if (drv_data->ssp_type != PXA25x_SSP) | |
637 | write_SSTO(0, reg); | |
e0c9905e | 638 | |
8d94cc50 SS |
639 | /* Update total byte transfered return count actual bytes read */ |
640 | drv_data->cur_msg->actual_length += drv_data->len - | |
641 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 642 | |
8423597d NF |
643 | /* Transfer delays and chip select release are |
644 | * handled in pump_transfers or giveback | |
645 | */ | |
e0c9905e | 646 | |
8d94cc50 SS |
647 | /* Move to next transfer */ |
648 | drv_data->cur_msg->state = next_transfer(drv_data); | |
e0c9905e | 649 | |
8d94cc50 SS |
650 | /* Schedule transfer tasklet */ |
651 | tasklet_schedule(&drv_data->pump_transfers); | |
652 | } | |
e0c9905e | 653 | |
8d94cc50 SS |
654 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
655 | { | |
cf43369d | 656 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 657 | |
8d94cc50 SS |
658 | u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? |
659 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 660 | |
8d94cc50 | 661 | u32 irq_status = read_SSSR(reg) & irq_mask; |
e0c9905e | 662 | |
8d94cc50 SS |
663 | if (irq_status & SSSR_ROR) { |
664 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
665 | return IRQ_HANDLED; | |
666 | } | |
e0c9905e | 667 | |
8d94cc50 SS |
668 | if (irq_status & SSSR_TINT) { |
669 | write_SSSR(SSSR_TINT, reg); | |
670 | if (drv_data->read(drv_data)) { | |
671 | int_transfer_complete(drv_data); | |
672 | return IRQ_HANDLED; | |
673 | } | |
674 | } | |
e0c9905e | 675 | |
8d94cc50 SS |
676 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
677 | do { | |
678 | if (drv_data->read(drv_data)) { | |
679 | int_transfer_complete(drv_data); | |
680 | return IRQ_HANDLED; | |
681 | } | |
682 | } while (drv_data->write(drv_data)); | |
e0c9905e | 683 | |
8d94cc50 SS |
684 | if (drv_data->read(drv_data)) { |
685 | int_transfer_complete(drv_data); | |
686 | return IRQ_HANDLED; | |
687 | } | |
e0c9905e | 688 | |
8d94cc50 SS |
689 | if (drv_data->tx == drv_data->tx_end) { |
690 | write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg); | |
691 | /* PXA25x_SSP has no timeout, read trailing bytes */ | |
692 | if (drv_data->ssp_type == PXA25x_SSP) { | |
693 | if (!wait_ssp_rx_stall(reg)) | |
694 | { | |
695 | int_error_stop(drv_data, "interrupt_transfer: " | |
696 | "rx stall failed"); | |
697 | return IRQ_HANDLED; | |
698 | } | |
699 | if (!drv_data->read(drv_data)) | |
700 | { | |
701 | int_error_stop(drv_data, | |
702 | "interrupt_transfer: " | |
703 | "trailing byte read failed"); | |
704 | return IRQ_HANDLED; | |
705 | } | |
706 | int_transfer_complete(drv_data); | |
e0c9905e | 707 | } |
e0c9905e SS |
708 | } |
709 | ||
5daa3ba0 SS |
710 | /* We did something */ |
711 | return IRQ_HANDLED; | |
e0c9905e SS |
712 | } |
713 | ||
7d12e780 | 714 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 715 | { |
c7bec5ab | 716 | struct driver_data *drv_data = dev_id; |
cf43369d | 717 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
718 | |
719 | if (!drv_data->cur_msg) { | |
5daa3ba0 SS |
720 | |
721 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
722 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
723 | if (drv_data->ssp_type != PXA25x_SSP) | |
724 | write_SSTO(0, reg); | |
725 | write_SSSR(drv_data->clear_sr, reg); | |
726 | ||
e0c9905e | 727 | dev_err(&drv_data->pdev->dev, "bad message state " |
8d94cc50 | 728 | "in interrupt handler\n"); |
5daa3ba0 | 729 | |
e0c9905e SS |
730 | /* Never fail */ |
731 | return IRQ_HANDLED; | |
732 | } | |
733 | ||
734 | return drv_data->transfer_handler(drv_data); | |
735 | } | |
736 | ||
cf43369d DB |
737 | static int set_dma_burst_and_threshold(struct chip_data *chip, |
738 | struct spi_device *spi, | |
8d94cc50 SS |
739 | u8 bits_per_word, u32 *burst_code, |
740 | u32 *threshold) | |
741 | { | |
742 | struct pxa2xx_spi_chip *chip_info = | |
743 | (struct pxa2xx_spi_chip *)spi->controller_data; | |
744 | int bytes_per_word; | |
745 | int burst_bytes; | |
746 | int thresh_words; | |
747 | int req_burst_size; | |
748 | int retval = 0; | |
749 | ||
750 | /* Set the threshold (in registers) to equal the same amount of data | |
751 | * as represented by burst size (in bytes). The computation below | |
752 | * is (burst_size rounded up to nearest 8 byte, word or long word) | |
753 | * divided by (bytes/register); the tx threshold is the inverse of | |
754 | * the rx, so that there will always be enough data in the rx fifo | |
755 | * to satisfy a burst, and there will always be enough space in the | |
756 | * tx fifo to accept a burst (a tx burst will overwrite the fifo if | |
757 | * there is not enough space), there must always remain enough empty | |
758 | * space in the rx fifo for any data loaded to the tx fifo. | |
759 | * Whenever burst_size (in bytes) equals bits/word, the fifo threshold | |
760 | * will be 8, or half the fifo; | |
761 | * The threshold can only be set to 2, 4 or 8, but not 16, because | |
762 | * to burst 16 to the tx fifo, the fifo would have to be empty; | |
763 | * however, the minimum fifo trigger level is 1, and the tx will | |
764 | * request service when the fifo is at this level, with only 15 spaces. | |
765 | */ | |
766 | ||
767 | /* find bytes/word */ | |
768 | if (bits_per_word <= 8) | |
769 | bytes_per_word = 1; | |
770 | else if (bits_per_word <= 16) | |
771 | bytes_per_word = 2; | |
772 | else | |
773 | bytes_per_word = 4; | |
774 | ||
775 | /* use struct pxa2xx_spi_chip->dma_burst_size if available */ | |
776 | if (chip_info) | |
777 | req_burst_size = chip_info->dma_burst_size; | |
778 | else { | |
779 | switch (chip->dma_burst_size) { | |
780 | default: | |
781 | /* if the default burst size is not set, | |
782 | * do it now */ | |
783 | chip->dma_burst_size = DCMD_BURST8; | |
784 | case DCMD_BURST8: | |
785 | req_burst_size = 8; | |
786 | break; | |
787 | case DCMD_BURST16: | |
788 | req_burst_size = 16; | |
789 | break; | |
790 | case DCMD_BURST32: | |
791 | req_burst_size = 32; | |
792 | break; | |
793 | } | |
794 | } | |
795 | if (req_burst_size <= 8) { | |
796 | *burst_code = DCMD_BURST8; | |
797 | burst_bytes = 8; | |
798 | } else if (req_burst_size <= 16) { | |
799 | if (bytes_per_word == 1) { | |
800 | /* don't burst more than 1/2 the fifo */ | |
801 | *burst_code = DCMD_BURST8; | |
802 | burst_bytes = 8; | |
803 | retval = 1; | |
804 | } else { | |
805 | *burst_code = DCMD_BURST16; | |
806 | burst_bytes = 16; | |
807 | } | |
808 | } else { | |
809 | if (bytes_per_word == 1) { | |
810 | /* don't burst more than 1/2 the fifo */ | |
811 | *burst_code = DCMD_BURST8; | |
812 | burst_bytes = 8; | |
813 | retval = 1; | |
814 | } else if (bytes_per_word == 2) { | |
815 | /* don't burst more than 1/2 the fifo */ | |
816 | *burst_code = DCMD_BURST16; | |
817 | burst_bytes = 16; | |
818 | retval = 1; | |
819 | } else { | |
820 | *burst_code = DCMD_BURST32; | |
821 | burst_bytes = 32; | |
822 | } | |
823 | } | |
824 | ||
825 | thresh_words = burst_bytes / bytes_per_word; | |
826 | ||
827 | /* thresh_words will be between 2 and 8 */ | |
828 | *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT) | |
829 | | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT); | |
830 | ||
831 | return retval; | |
832 | } | |
833 | ||
2f1a74e5 | 834 | static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate) |
835 | { | |
836 | unsigned long ssp_clk = clk_get_rate(ssp->clk); | |
837 | ||
838 | if (ssp->type == PXA25x_SSP) | |
839 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; | |
840 | else | |
841 | return ((ssp_clk / rate - 1) & 0xfff) << 8; | |
842 | } | |
843 | ||
e0c9905e SS |
844 | static void pump_transfers(unsigned long data) |
845 | { | |
846 | struct driver_data *drv_data = (struct driver_data *)data; | |
847 | struct spi_message *message = NULL; | |
848 | struct spi_transfer *transfer = NULL; | |
849 | struct spi_transfer *previous = NULL; | |
850 | struct chip_data *chip = NULL; | |
2f1a74e5 | 851 | struct ssp_device *ssp = drv_data->ssp; |
cf43369d | 852 | void __iomem *reg = drv_data->ioaddr; |
9708c121 SS |
853 | u32 clk_div = 0; |
854 | u8 bits = 0; | |
855 | u32 speed = 0; | |
856 | u32 cr0; | |
8d94cc50 SS |
857 | u32 cr1; |
858 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
859 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
e0c9905e SS |
860 | |
861 | /* Get current state information */ | |
862 | message = drv_data->cur_msg; | |
863 | transfer = drv_data->cur_transfer; | |
864 | chip = drv_data->cur_chip; | |
865 | ||
866 | /* Handle for abort */ | |
867 | if (message->state == ERROR_STATE) { | |
868 | message->status = -EIO; | |
5daa3ba0 | 869 | giveback(drv_data); |
e0c9905e SS |
870 | return; |
871 | } | |
872 | ||
873 | /* Handle end of message */ | |
874 | if (message->state == DONE_STATE) { | |
875 | message->status = 0; | |
5daa3ba0 | 876 | giveback(drv_data); |
e0c9905e SS |
877 | return; |
878 | } | |
879 | ||
8423597d | 880 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
881 | if (message->state == RUNNING_STATE) { |
882 | previous = list_entry(transfer->transfer_list.prev, | |
883 | struct spi_transfer, | |
884 | transfer_list); | |
885 | if (previous->delay_usecs) | |
886 | udelay(previous->delay_usecs); | |
8423597d NF |
887 | |
888 | /* Drop chip select only if cs_change is requested */ | |
889 | if (previous->cs_change) | |
890 | drv_data->cs_control(PXA2XX_CS_DEASSERT); | |
e0c9905e SS |
891 | } |
892 | ||
7e964455 NF |
893 | /* Check for transfers that need multiple DMA segments */ |
894 | if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { | |
895 | ||
896 | /* reject already-mapped transfers; PIO won't always work */ | |
897 | if (message->is_dma_mapped | |
898 | || transfer->rx_dma || transfer->tx_dma) { | |
899 | dev_err(&drv_data->pdev->dev, | |
900 | "pump_transfers: mapped transfer length " | |
20b918dc | 901 | "of %u is greater than %d\n", |
7e964455 NF |
902 | transfer->len, MAX_DMA_LEN); |
903 | message->status = -EINVAL; | |
904 | giveback(drv_data); | |
905 | return; | |
906 | } | |
907 | ||
908 | /* warn ... we force this to PIO mode */ | |
909 | if (printk_ratelimit()) | |
910 | dev_warn(&message->spi->dev, "pump_transfers: " | |
911 | "DMA disabled for transfer length %ld " | |
912 | "greater than %d\n", | |
913 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
914 | } |
915 | ||
e0c9905e SS |
916 | /* Setup the transfer state based on the type of transfer */ |
917 | if (flush(drv_data) == 0) { | |
918 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); | |
919 | message->status = -EIO; | |
5daa3ba0 | 920 | giveback(drv_data); |
e0c9905e SS |
921 | return; |
922 | } | |
9708c121 SS |
923 | drv_data->n_bytes = chip->n_bytes; |
924 | drv_data->dma_width = chip->dma_width; | |
e0c9905e SS |
925 | drv_data->cs_control = chip->cs_control; |
926 | drv_data->tx = (void *)transfer->tx_buf; | |
927 | drv_data->tx_end = drv_data->tx + transfer->len; | |
928 | drv_data->rx = transfer->rx_buf; | |
929 | drv_data->rx_end = drv_data->rx + transfer->len; | |
930 | drv_data->rx_dma = transfer->rx_dma; | |
931 | drv_data->tx_dma = transfer->tx_dma; | |
8d94cc50 | 932 | drv_data->len = transfer->len & DCMD_LENGTH; |
e0c9905e SS |
933 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
934 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
935 | |
936 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 937 | cr0 = chip->cr0; |
9708c121 SS |
938 | if (transfer->speed_hz || transfer->bits_per_word) { |
939 | ||
9708c121 SS |
940 | bits = chip->bits_per_word; |
941 | speed = chip->speed_hz; | |
942 | ||
943 | if (transfer->speed_hz) | |
944 | speed = transfer->speed_hz; | |
945 | ||
946 | if (transfer->bits_per_word) | |
947 | bits = transfer->bits_per_word; | |
948 | ||
2f1a74e5 | 949 | clk_div = ssp_get_clk_div(ssp, speed); |
9708c121 SS |
950 | |
951 | if (bits <= 8) { | |
952 | drv_data->n_bytes = 1; | |
953 | drv_data->dma_width = DCMD_WIDTH1; | |
954 | drv_data->read = drv_data->read != null_reader ? | |
955 | u8_reader : null_reader; | |
956 | drv_data->write = drv_data->write != null_writer ? | |
957 | u8_writer : null_writer; | |
958 | } else if (bits <= 16) { | |
959 | drv_data->n_bytes = 2; | |
960 | drv_data->dma_width = DCMD_WIDTH2; | |
961 | drv_data->read = drv_data->read != null_reader ? | |
962 | u16_reader : null_reader; | |
963 | drv_data->write = drv_data->write != null_writer ? | |
964 | u16_writer : null_writer; | |
965 | } else if (bits <= 32) { | |
966 | drv_data->n_bytes = 4; | |
967 | drv_data->dma_width = DCMD_WIDTH4; | |
968 | drv_data->read = drv_data->read != null_reader ? | |
969 | u32_reader : null_reader; | |
970 | drv_data->write = drv_data->write != null_writer ? | |
971 | u32_writer : null_writer; | |
972 | } | |
8d94cc50 SS |
973 | /* if bits/word is changed in dma mode, then must check the |
974 | * thresholds and burst also */ | |
975 | if (chip->enable_dma) { | |
976 | if (set_dma_burst_and_threshold(chip, message->spi, | |
977 | bits, &dma_burst, | |
978 | &dma_thresh)) | |
979 | if (printk_ratelimit()) | |
980 | dev_warn(&message->spi->dev, | |
7e964455 | 981 | "pump_transfers: " |
8d94cc50 SS |
982 | "DMA burst size reduced to " |
983 | "match bits_per_word\n"); | |
984 | } | |
9708c121 SS |
985 | |
986 | cr0 = clk_div | |
987 | | SSCR0_Motorola | |
5daa3ba0 | 988 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) |
9708c121 SS |
989 | | SSCR0_SSE |
990 | | (bits > 16 ? SSCR0_EDSS : 0); | |
9708c121 SS |
991 | } |
992 | ||
e0c9905e SS |
993 | message->state = RUNNING_STATE; |
994 | ||
7e964455 NF |
995 | /* Try to map dma buffer and do a dma transfer if successful, but |
996 | * only if the length is non-zero and less than MAX_DMA_LEN. | |
997 | * | |
998 | * Zero-length non-descriptor DMA is illegal on PXA2xx; force use | |
999 | * of PIO instead. Care is needed above because the transfer may | |
1000 | * have have been passed with buffers that are already dma mapped. | |
1001 | * A zero-length transfer in PIO mode will not try to write/read | |
1002 | * to/from the buffers | |
1003 | * | |
1004 | * REVISIT large transfers are exactly where we most want to be | |
1005 | * using DMA. If this happens much, split those transfers into | |
1006 | * multiple DMA segments rather than forcing PIO. | |
1007 | */ | |
1008 | drv_data->dma_mapped = 0; | |
1009 | if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN) | |
1010 | drv_data->dma_mapped = map_dma_buffers(drv_data); | |
1011 | if (drv_data->dma_mapped) { | |
e0c9905e SS |
1012 | |
1013 | /* Ensure we have the correct interrupt handler */ | |
1014 | drv_data->transfer_handler = dma_transfer; | |
1015 | ||
1016 | /* Setup rx DMA Channel */ | |
1017 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
1018 | DSADR(drv_data->rx_channel) = drv_data->ssdr_physical; | |
1019 | DTADR(drv_data->rx_channel) = drv_data->rx_dma; | |
1020 | if (drv_data->rx == drv_data->null_dma_buf) | |
1021 | /* No target address increment */ | |
1022 | DCMD(drv_data->rx_channel) = DCMD_FLOWSRC | |
9708c121 | 1023 | | drv_data->dma_width |
8d94cc50 | 1024 | | dma_burst |
e0c9905e SS |
1025 | | drv_data->len; |
1026 | else | |
1027 | DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR | |
1028 | | DCMD_FLOWSRC | |
9708c121 | 1029 | | drv_data->dma_width |
8d94cc50 | 1030 | | dma_burst |
e0c9905e SS |
1031 | | drv_data->len; |
1032 | ||
1033 | /* Setup tx DMA Channel */ | |
1034 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
1035 | DSADR(drv_data->tx_channel) = drv_data->tx_dma; | |
1036 | DTADR(drv_data->tx_channel) = drv_data->ssdr_physical; | |
1037 | if (drv_data->tx == drv_data->null_dma_buf) | |
1038 | /* No source address increment */ | |
1039 | DCMD(drv_data->tx_channel) = DCMD_FLOWTRG | |
9708c121 | 1040 | | drv_data->dma_width |
8d94cc50 | 1041 | | dma_burst |
e0c9905e SS |
1042 | | drv_data->len; |
1043 | else | |
1044 | DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR | |
1045 | | DCMD_FLOWTRG | |
9708c121 | 1046 | | drv_data->dma_width |
8d94cc50 | 1047 | | dma_burst |
e0c9905e SS |
1048 | | drv_data->len; |
1049 | ||
1050 | /* Enable dma end irqs on SSP to detect end of transfer */ | |
1051 | if (drv_data->ssp_type == PXA25x_SSP) | |
1052 | DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN; | |
1053 | ||
8d94cc50 SS |
1054 | /* Clear status and start DMA engine */ |
1055 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
e0c9905e SS |
1056 | write_SSSR(drv_data->clear_sr, reg); |
1057 | DCSR(drv_data->rx_channel) |= DCSR_RUN; | |
1058 | DCSR(drv_data->tx_channel) |= DCSR_RUN; | |
e0c9905e SS |
1059 | } else { |
1060 | /* Ensure we have the correct interrupt handler */ | |
1061 | drv_data->transfer_handler = interrupt_transfer; | |
1062 | ||
8d94cc50 SS |
1063 | /* Clear status */ |
1064 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
e0c9905e | 1065 | write_SSSR(drv_data->clear_sr, reg); |
8d94cc50 SS |
1066 | } |
1067 | ||
1068 | /* see if we need to reload the config registers */ | |
1069 | if ((read_SSCR0(reg) != cr0) | |
1070 | || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != | |
1071 | (cr1 & SSCR1_CHANGE_MASK)) { | |
1072 | ||
b97c74bd | 1073 | /* stop the SSP, and update the other bits */ |
8d94cc50 | 1074 | write_SSCR0(cr0 & ~SSCR0_SSE, reg); |
e0c9905e SS |
1075 | if (drv_data->ssp_type != PXA25x_SSP) |
1076 | write_SSTO(chip->timeout, reg); | |
b97c74bd NF |
1077 | /* first set CR1 without interrupt and service enables */ |
1078 | write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); | |
1079 | /* restart the SSP */ | |
8d94cc50 | 1080 | write_SSCR0(cr0, reg); |
b97c74bd | 1081 | |
8d94cc50 SS |
1082 | } else { |
1083 | if (drv_data->ssp_type != PXA25x_SSP) | |
1084 | write_SSTO(chip->timeout, reg); | |
e0c9905e | 1085 | } |
b97c74bd NF |
1086 | |
1087 | /* FIXME, need to handle cs polarity, | |
1088 | * this driver uses struct pxa2xx_spi_chip.cs_control to | |
1089 | * specify a CS handling function, and it ignores most | |
1090 | * struct spi_device.mode[s], including SPI_CS_HIGH */ | |
1091 | drv_data->cs_control(PXA2XX_CS_ASSERT); | |
1092 | ||
1093 | /* after chip select, release the data by enabling service | |
1094 | * requests and interrupts, without changing any mode bits */ | |
1095 | write_SSCR1(cr1, reg); | |
e0c9905e SS |
1096 | } |
1097 | ||
6d5aefb8 | 1098 | static void pump_messages(struct work_struct *work) |
e0c9905e | 1099 | { |
6d5aefb8 DH |
1100 | struct driver_data *drv_data = |
1101 | container_of(work, struct driver_data, pump_messages); | |
e0c9905e SS |
1102 | unsigned long flags; |
1103 | ||
1104 | /* Lock queue and check for queue work */ | |
1105 | spin_lock_irqsave(&drv_data->lock, flags); | |
1106 | if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { | |
1107 | drv_data->busy = 0; | |
1108 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1109 | return; | |
1110 | } | |
1111 | ||
1112 | /* Make sure we are not already running a message */ | |
1113 | if (drv_data->cur_msg) { | |
1114 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1115 | return; | |
1116 | } | |
1117 | ||
1118 | /* Extract head of queue */ | |
1119 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
1120 | struct spi_message, queue); | |
1121 | list_del_init(&drv_data->cur_msg->queue); | |
e0c9905e SS |
1122 | |
1123 | /* Initial message state*/ | |
1124 | drv_data->cur_msg->state = START_STATE; | |
1125 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
1126 | struct spi_transfer, | |
1127 | transfer_list); | |
1128 | ||
8d94cc50 SS |
1129 | /* prepare to setup the SSP, in pump_transfers, using the per |
1130 | * chip configuration */ | |
e0c9905e | 1131 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
1132 | |
1133 | /* Mark as busy and launch transfers */ | |
1134 | tasklet_schedule(&drv_data->pump_transfers); | |
5daa3ba0 SS |
1135 | |
1136 | drv_data->busy = 1; | |
1137 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
e0c9905e SS |
1138 | } |
1139 | ||
1140 | static int transfer(struct spi_device *spi, struct spi_message *msg) | |
1141 | { | |
1142 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
1143 | unsigned long flags; | |
1144 | ||
1145 | spin_lock_irqsave(&drv_data->lock, flags); | |
1146 | ||
1147 | if (drv_data->run == QUEUE_STOPPED) { | |
1148 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1149 | return -ESHUTDOWN; | |
1150 | } | |
1151 | ||
1152 | msg->actual_length = 0; | |
1153 | msg->status = -EINPROGRESS; | |
1154 | msg->state = START_STATE; | |
1155 | ||
1156 | list_add_tail(&msg->queue, &drv_data->queue); | |
1157 | ||
1158 | if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) | |
1159 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1160 | ||
1161 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1162 | ||
1163 | return 0; | |
1164 | } | |
1165 | ||
dccd573b DB |
1166 | /* the spi->mode bits understood by this driver: */ |
1167 | #define MODEBITS (SPI_CPOL | SPI_CPHA) | |
1168 | ||
e0c9905e SS |
1169 | static int setup(struct spi_device *spi) |
1170 | { | |
1171 | struct pxa2xx_spi_chip *chip_info = NULL; | |
1172 | struct chip_data *chip; | |
1173 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
2f1a74e5 | 1174 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e | 1175 | unsigned int clk_div; |
f1f640a9 VS |
1176 | uint tx_thres = TX_THRESH_DFLT; |
1177 | uint rx_thres = RX_THRESH_DFLT; | |
e0c9905e SS |
1178 | |
1179 | if (!spi->bits_per_word) | |
1180 | spi->bits_per_word = 8; | |
1181 | ||
1182 | if (drv_data->ssp_type != PXA25x_SSP | |
8d94cc50 SS |
1183 | && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { |
1184 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
1185 | "b/w not 4-32 for type non-PXA25x_SSP\n", | |
1186 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 1187 | return -EINVAL; |
8d94cc50 SS |
1188 | } |
1189 | else if (drv_data->ssp_type == PXA25x_SSP | |
1190 | && (spi->bits_per_word < 4 | |
1191 | || spi->bits_per_word > 16)) { | |
1192 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
1193 | "b/w not 4-16 for type PXA25x_SSP\n", | |
1194 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 1195 | return -EINVAL; |
8d94cc50 | 1196 | } |
e0c9905e | 1197 | |
dccd573b DB |
1198 | if (spi->mode & ~MODEBITS) { |
1199 | dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", | |
1200 | spi->mode & ~MODEBITS); | |
1201 | return -EINVAL; | |
1202 | } | |
1203 | ||
8d94cc50 | 1204 | /* Only alloc on first setup */ |
e0c9905e | 1205 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1206 | if (!chip) { |
e0c9905e | 1207 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
8d94cc50 SS |
1208 | if (!chip) { |
1209 | dev_err(&spi->dev, | |
1210 | "failed setup: can't allocate chip data\n"); | |
e0c9905e | 1211 | return -ENOMEM; |
8d94cc50 | 1212 | } |
e0c9905e SS |
1213 | |
1214 | chip->cs_control = null_cs_control; | |
1215 | chip->enable_dma = 0; | |
f1f640a9 | 1216 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
1217 | chip->dma_burst_size = drv_data->master_info->enable_dma ? |
1218 | DCMD_BURST8 : 0; | |
e0c9905e SS |
1219 | } |
1220 | ||
8d94cc50 SS |
1221 | /* protocol drivers may change the chip settings, so... |
1222 | * if chip_info exists, use it */ | |
1223 | chip_info = spi->controller_data; | |
1224 | ||
e0c9905e | 1225 | /* chip_info isn't always needed */ |
8d94cc50 | 1226 | chip->cr1 = 0; |
e0c9905e SS |
1227 | if (chip_info) { |
1228 | if (chip_info->cs_control) | |
1229 | chip->cs_control = chip_info->cs_control; | |
f1f640a9 VS |
1230 | if (chip_info->timeout) |
1231 | chip->timeout = chip_info->timeout; | |
1232 | if (chip_info->tx_threshold) | |
1233 | tx_thres = chip_info->tx_threshold; | |
1234 | if (chip_info->rx_threshold) | |
1235 | rx_thres = chip_info->rx_threshold; | |
1236 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 1237 | chip->dma_threshold = 0; |
e0c9905e SS |
1238 | if (chip_info->enable_loopback) |
1239 | chip->cr1 = SSCR1_LBM; | |
1240 | } | |
1241 | ||
f1f640a9 VS |
1242 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | |
1243 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
1244 | ||
8d94cc50 SS |
1245 | /* set dma burst and threshold outside of chip_info path so that if |
1246 | * chip_info goes away after setting chip->enable_dma, the | |
1247 | * burst and threshold can still respond to changes in bits_per_word */ | |
1248 | if (chip->enable_dma) { | |
1249 | /* set up legal burst and threshold for dma */ | |
1250 | if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word, | |
1251 | &chip->dma_burst_size, | |
1252 | &chip->dma_threshold)) { | |
1253 | dev_warn(&spi->dev, "in setup: DMA burst size reduced " | |
1254 | "to match bits_per_word\n"); | |
1255 | } | |
1256 | } | |
1257 | ||
2f1a74e5 | 1258 | clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz); |
9708c121 | 1259 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e SS |
1260 | |
1261 | chip->cr0 = clk_div | |
1262 | | SSCR0_Motorola | |
5daa3ba0 SS |
1263 | | SSCR0_DataSize(spi->bits_per_word > 16 ? |
1264 | spi->bits_per_word - 16 : spi->bits_per_word) | |
e0c9905e SS |
1265 | | SSCR0_SSE |
1266 | | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); | |
7f6ee1ad JC |
1267 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1268 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1269 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e SS |
1270 | |
1271 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ | |
1272 | if (drv_data->ssp_type != PXA25x_SSP) | |
f1f640a9 | 1273 | dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d, %s\n", |
e0c9905e | 1274 | spi->bits_per_word, |
2f1a74e5 | 1275 | clk_get_rate(ssp->clk) |
e0c9905e | 1276 | / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), |
f1f640a9 VS |
1277 | spi->mode & 0x3, |
1278 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e | 1279 | else |
f1f640a9 | 1280 | dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d, %s\n", |
e0c9905e | 1281 | spi->bits_per_word, |
f1f640a9 | 1282 | clk_get_rate(ssp->clk) / 2 |
e0c9905e | 1283 | / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), |
f1f640a9 VS |
1284 | spi->mode & 0x3, |
1285 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e SS |
1286 | |
1287 | if (spi->bits_per_word <= 8) { | |
1288 | chip->n_bytes = 1; | |
1289 | chip->dma_width = DCMD_WIDTH1; | |
1290 | chip->read = u8_reader; | |
1291 | chip->write = u8_writer; | |
1292 | } else if (spi->bits_per_word <= 16) { | |
1293 | chip->n_bytes = 2; | |
1294 | chip->dma_width = DCMD_WIDTH2; | |
1295 | chip->read = u16_reader; | |
1296 | chip->write = u16_writer; | |
1297 | } else if (spi->bits_per_word <= 32) { | |
1298 | chip->cr0 |= SSCR0_EDSS; | |
1299 | chip->n_bytes = 4; | |
1300 | chip->dma_width = DCMD_WIDTH4; | |
1301 | chip->read = u32_reader; | |
1302 | chip->write = u32_writer; | |
1303 | } else { | |
1304 | dev_err(&spi->dev, "invalid wordsize\n"); | |
e0c9905e SS |
1305 | return -ENODEV; |
1306 | } | |
9708c121 | 1307 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1308 | |
1309 | spi_set_ctldata(spi, chip); | |
1310 | ||
1311 | return 0; | |
1312 | } | |
1313 | ||
0ffa0285 | 1314 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1315 | { |
0ffa0285 | 1316 | struct chip_data *chip = spi_get_ctldata(spi); |
e0c9905e SS |
1317 | |
1318 | kfree(chip); | |
1319 | } | |
1320 | ||
d1e44d9c | 1321 | static int __init init_queue(struct driver_data *drv_data) |
e0c9905e SS |
1322 | { |
1323 | INIT_LIST_HEAD(&drv_data->queue); | |
1324 | spin_lock_init(&drv_data->lock); | |
1325 | ||
1326 | drv_data->run = QUEUE_STOPPED; | |
1327 | drv_data->busy = 0; | |
1328 | ||
1329 | tasklet_init(&drv_data->pump_transfers, | |
1330 | pump_transfers, (unsigned long)drv_data); | |
1331 | ||
6d5aefb8 | 1332 | INIT_WORK(&drv_data->pump_messages, pump_messages); |
e0c9905e | 1333 | drv_data->workqueue = create_singlethread_workqueue( |
6c7377ab | 1334 | dev_name(drv_data->master->dev.parent)); |
e0c9905e SS |
1335 | if (drv_data->workqueue == NULL) |
1336 | return -EBUSY; | |
1337 | ||
1338 | return 0; | |
1339 | } | |
1340 | ||
1341 | static int start_queue(struct driver_data *drv_data) | |
1342 | { | |
1343 | unsigned long flags; | |
1344 | ||
1345 | spin_lock_irqsave(&drv_data->lock, flags); | |
1346 | ||
1347 | if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { | |
1348 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1349 | return -EBUSY; | |
1350 | } | |
1351 | ||
1352 | drv_data->run = QUEUE_RUNNING; | |
1353 | drv_data->cur_msg = NULL; | |
1354 | drv_data->cur_transfer = NULL; | |
1355 | drv_data->cur_chip = NULL; | |
1356 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1357 | ||
1358 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1359 | ||
1360 | return 0; | |
1361 | } | |
1362 | ||
1363 | static int stop_queue(struct driver_data *drv_data) | |
1364 | { | |
1365 | unsigned long flags; | |
1366 | unsigned limit = 500; | |
1367 | int status = 0; | |
1368 | ||
1369 | spin_lock_irqsave(&drv_data->lock, flags); | |
1370 | ||
1371 | /* This is a bit lame, but is optimized for the common execution path. | |
1372 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1373 | * execution path (pump_messages) would be required to call wake_up or | |
1374 | * friends on every SPI message. Do this instead */ | |
1375 | drv_data->run = QUEUE_STOPPED; | |
1376 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { | |
1377 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1378 | msleep(10); | |
1379 | spin_lock_irqsave(&drv_data->lock, flags); | |
1380 | } | |
1381 | ||
1382 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1383 | status = -EBUSY; | |
1384 | ||
1385 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1386 | ||
1387 | return status; | |
1388 | } | |
1389 | ||
1390 | static int destroy_queue(struct driver_data *drv_data) | |
1391 | { | |
1392 | int status; | |
1393 | ||
1394 | status = stop_queue(drv_data); | |
8d94cc50 SS |
1395 | /* we are unloading the module or failing to load (only two calls |
1396 | * to this routine), and neither call can handle a return value. | |
1397 | * However, destroy_workqueue calls flush_workqueue, and that will | |
1398 | * block until all work is done. If the reason that stop_queue | |
1399 | * timed out is that the work will never finish, then it does no | |
1400 | * good to call destroy_workqueue, so return anyway. */ | |
e0c9905e SS |
1401 | if (status != 0) |
1402 | return status; | |
1403 | ||
1404 | destroy_workqueue(drv_data->workqueue); | |
1405 | ||
1406 | return 0; | |
1407 | } | |
1408 | ||
d1e44d9c | 1409 | static int __init pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1410 | { |
1411 | struct device *dev = &pdev->dev; | |
1412 | struct pxa2xx_spi_master *platform_info; | |
1413 | struct spi_master *master; | |
65a00a20 | 1414 | struct driver_data *drv_data; |
2f1a74e5 | 1415 | struct ssp_device *ssp; |
65a00a20 | 1416 | int status; |
e0c9905e SS |
1417 | |
1418 | platform_info = dev->platform_data; | |
1419 | ||
2f1a74e5 | 1420 | ssp = ssp_request(pdev->id, pdev->name); |
1421 | if (ssp == NULL) { | |
1422 | dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id); | |
e0c9905e SS |
1423 | return -ENODEV; |
1424 | } | |
1425 | ||
1426 | /* Allocate master with space for drv_data and null dma buffer */ | |
1427 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1428 | if (!master) { | |
65a00a20 | 1429 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
2f1a74e5 | 1430 | ssp_free(ssp); |
e0c9905e SS |
1431 | return -ENOMEM; |
1432 | } | |
1433 | drv_data = spi_master_get_devdata(master); | |
1434 | drv_data->master = master; | |
1435 | drv_data->master_info = platform_info; | |
1436 | drv_data->pdev = pdev; | |
2f1a74e5 | 1437 | drv_data->ssp = ssp; |
e0c9905e SS |
1438 | |
1439 | master->bus_num = pdev->id; | |
1440 | master->num_chipselect = platform_info->num_chipselect; | |
1441 | master->cleanup = cleanup; | |
1442 | master->setup = setup; | |
1443 | master->transfer = transfer; | |
1444 | ||
2f1a74e5 | 1445 | drv_data->ssp_type = ssp->type; |
e0c9905e SS |
1446 | drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data + |
1447 | sizeof(struct driver_data)), 8); | |
1448 | ||
2f1a74e5 | 1449 | drv_data->ioaddr = ssp->mmio_base; |
1450 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
1451 | if (ssp->type == PXA25x_SSP) { | |
e0c9905e SS |
1452 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1453 | drv_data->dma_cr1 = 0; | |
1454 | drv_data->clear_sr = SSSR_ROR; | |
1455 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1456 | } else { | |
1457 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; | |
1458 | drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE; | |
1459 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; | |
1460 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1461 | } | |
1462 | ||
6c7377ab | 1463 | status = request_irq(ssp->irq, ssp_int, 0, dev_name(dev), drv_data); |
e0c9905e | 1464 | if (status < 0) { |
65a00a20 | 1465 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1466 | goto out_error_master_alloc; |
1467 | } | |
1468 | ||
1469 | /* Setup DMA if requested */ | |
1470 | drv_data->tx_channel = -1; | |
1471 | drv_data->rx_channel = -1; | |
1472 | if (platform_info->enable_dma) { | |
1473 | ||
1474 | /* Get two DMA channels (rx and tx) */ | |
1475 | drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx", | |
1476 | DMA_PRIO_HIGH, | |
1477 | dma_handler, | |
1478 | drv_data); | |
1479 | if (drv_data->rx_channel < 0) { | |
1480 | dev_err(dev, "problem (%d) requesting rx channel\n", | |
1481 | drv_data->rx_channel); | |
1482 | status = -ENODEV; | |
1483 | goto out_error_irq_alloc; | |
1484 | } | |
1485 | drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx", | |
1486 | DMA_PRIO_MEDIUM, | |
1487 | dma_handler, | |
1488 | drv_data); | |
1489 | if (drv_data->tx_channel < 0) { | |
1490 | dev_err(dev, "problem (%d) requesting tx channel\n", | |
1491 | drv_data->tx_channel); | |
1492 | status = -ENODEV; | |
1493 | goto out_error_dma_alloc; | |
1494 | } | |
1495 | ||
2f1a74e5 | 1496 | DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel; |
1497 | DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel; | |
e0c9905e SS |
1498 | } |
1499 | ||
1500 | /* Enable SOC clock */ | |
2f1a74e5 | 1501 | clk_enable(ssp->clk); |
e0c9905e SS |
1502 | |
1503 | /* Load default SSP configuration */ | |
1504 | write_SSCR0(0, drv_data->ioaddr); | |
f1f640a9 VS |
1505 | write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | |
1506 | SSCR1_TxTresh(TX_THRESH_DFLT), | |
1507 | drv_data->ioaddr); | |
e0c9905e SS |
1508 | write_SSCR0(SSCR0_SerClkDiv(2) |
1509 | | SSCR0_Motorola | |
1510 | | SSCR0_DataSize(8), | |
1511 | drv_data->ioaddr); | |
1512 | if (drv_data->ssp_type != PXA25x_SSP) | |
1513 | write_SSTO(0, drv_data->ioaddr); | |
1514 | write_SSPSP(0, drv_data->ioaddr); | |
1515 | ||
1516 | /* Initial and start queue */ | |
1517 | status = init_queue(drv_data); | |
1518 | if (status != 0) { | |
1519 | dev_err(&pdev->dev, "problem initializing queue\n"); | |
1520 | goto out_error_clock_enabled; | |
1521 | } | |
1522 | status = start_queue(drv_data); | |
1523 | if (status != 0) { | |
1524 | dev_err(&pdev->dev, "problem starting queue\n"); | |
1525 | goto out_error_clock_enabled; | |
1526 | } | |
1527 | ||
1528 | /* Register with the SPI framework */ | |
1529 | platform_set_drvdata(pdev, drv_data); | |
1530 | status = spi_register_master(master); | |
1531 | if (status != 0) { | |
1532 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
1533 | goto out_error_queue_alloc; | |
1534 | } | |
1535 | ||
1536 | return status; | |
1537 | ||
1538 | out_error_queue_alloc: | |
1539 | destroy_queue(drv_data); | |
1540 | ||
1541 | out_error_clock_enabled: | |
2f1a74e5 | 1542 | clk_disable(ssp->clk); |
e0c9905e SS |
1543 | |
1544 | out_error_dma_alloc: | |
1545 | if (drv_data->tx_channel != -1) | |
1546 | pxa_free_dma(drv_data->tx_channel); | |
1547 | if (drv_data->rx_channel != -1) | |
1548 | pxa_free_dma(drv_data->rx_channel); | |
1549 | ||
1550 | out_error_irq_alloc: | |
2f1a74e5 | 1551 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1552 | |
1553 | out_error_master_alloc: | |
1554 | spi_master_put(master); | |
2f1a74e5 | 1555 | ssp_free(ssp); |
e0c9905e SS |
1556 | return status; |
1557 | } | |
1558 | ||
1559 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1560 | { | |
1561 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1562 | struct ssp_device *ssp; |
e0c9905e SS |
1563 | int status = 0; |
1564 | ||
1565 | if (!drv_data) | |
1566 | return 0; | |
51e911e2 | 1567 | ssp = drv_data->ssp; |
e0c9905e SS |
1568 | |
1569 | /* Remove the queue */ | |
1570 | status = destroy_queue(drv_data); | |
1571 | if (status != 0) | |
8d94cc50 SS |
1572 | /* the kernel does not check the return status of this |
1573 | * this routine (mod->exit, within the kernel). Therefore | |
1574 | * nothing is gained by returning from here, the module is | |
1575 | * going away regardless, and we should not leave any more | |
1576 | * resources allocated than necessary. We cannot free the | |
1577 | * message memory in drv_data->queue, but we can release the | |
1578 | * resources below. I think the kernel should honor -EBUSY | |
1579 | * returns but... */ | |
1580 | dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not " | |
1581 | "complete, message memory not freed\n"); | |
e0c9905e SS |
1582 | |
1583 | /* Disable the SSP at the peripheral and SOC level */ | |
1584 | write_SSCR0(0, drv_data->ioaddr); | |
2f1a74e5 | 1585 | clk_disable(ssp->clk); |
e0c9905e SS |
1586 | |
1587 | /* Release DMA */ | |
1588 | if (drv_data->master_info->enable_dma) { | |
2f1a74e5 | 1589 | DRCMR(ssp->drcmr_rx) = 0; |
1590 | DRCMR(ssp->drcmr_tx) = 0; | |
e0c9905e SS |
1591 | pxa_free_dma(drv_data->tx_channel); |
1592 | pxa_free_dma(drv_data->rx_channel); | |
1593 | } | |
1594 | ||
1595 | /* Release IRQ */ | |
2f1a74e5 | 1596 | free_irq(ssp->irq, drv_data); |
1597 | ||
1598 | /* Release SSP */ | |
1599 | ssp_free(ssp); | |
e0c9905e SS |
1600 | |
1601 | /* Disconnect from the SPI framework */ | |
1602 | spi_unregister_master(drv_data->master); | |
1603 | ||
1604 | /* Prevent double remove */ | |
1605 | platform_set_drvdata(pdev, NULL); | |
1606 | ||
1607 | return 0; | |
1608 | } | |
1609 | ||
1610 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1611 | { | |
1612 | int status = 0; | |
1613 | ||
1614 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1615 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1616 | } | |
1617 | ||
1618 | #ifdef CONFIG_PM | |
e0c9905e SS |
1619 | |
1620 | static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state) | |
1621 | { | |
1622 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
2f1a74e5 | 1623 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1624 | int status = 0; |
1625 | ||
e0c9905e SS |
1626 | status = stop_queue(drv_data); |
1627 | if (status != 0) | |
1628 | return status; | |
1629 | write_SSCR0(0, drv_data->ioaddr); | |
2f1a74e5 | 1630 | clk_disable(ssp->clk); |
e0c9905e SS |
1631 | |
1632 | return 0; | |
1633 | } | |
1634 | ||
1635 | static int pxa2xx_spi_resume(struct platform_device *pdev) | |
1636 | { | |
1637 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
2f1a74e5 | 1638 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1639 | int status = 0; |
1640 | ||
1641 | /* Enable the SSP clock */ | |
0cf942d7 | 1642 | clk_enable(ssp->clk); |
e0c9905e SS |
1643 | |
1644 | /* Start the queue running */ | |
1645 | status = start_queue(drv_data); | |
1646 | if (status != 0) { | |
1647 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1648 | return status; | |
1649 | } | |
1650 | ||
1651 | return 0; | |
1652 | } | |
1653 | #else | |
1654 | #define pxa2xx_spi_suspend NULL | |
1655 | #define pxa2xx_spi_resume NULL | |
1656 | #endif /* CONFIG_PM */ | |
1657 | ||
1658 | static struct platform_driver driver = { | |
1659 | .driver = { | |
1660 | .name = "pxa2xx-spi", | |
e0c9905e SS |
1661 | .owner = THIS_MODULE, |
1662 | }, | |
d1e44d9c | 1663 | .remove = pxa2xx_spi_remove, |
e0c9905e SS |
1664 | .shutdown = pxa2xx_spi_shutdown, |
1665 | .suspend = pxa2xx_spi_suspend, | |
1666 | .resume = pxa2xx_spi_resume, | |
1667 | }; | |
1668 | ||
1669 | static int __init pxa2xx_spi_init(void) | |
1670 | { | |
d1e44d9c | 1671 | return platform_driver_probe(&driver, pxa2xx_spi_probe); |
e0c9905e SS |
1672 | } |
1673 | module_init(pxa2xx_spi_init); | |
1674 | ||
1675 | static void __exit pxa2xx_spi_exit(void) | |
1676 | { | |
1677 | platform_driver_unregister(&driver); | |
1678 | } | |
1679 | module_exit(pxa2xx_spi_exit); |