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eventfd/kaio integration fix
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / pxa2xx_spi.c
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e0c9905e
SS		 1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/device.h>
22#include <linux/ioport.h>
23#include <linux/errno.h>
24#include <linux/interrupt.h>
25#include <linux/platform_device.h>
26#include <linux/dma-mapping.h>
27#include <linux/spi/spi.h>
28#include <linux/workqueue.h>
e0c9905e 29#include <linux/delay.h>
2f1a74e5 30#include <linux/clk.h>
e0c9905e
SS		 31
32#include <asm/io.h>
33#include <asm/irq.h>
34#include <asm/hardware.h>
35#include <asm/delay.h>
36#include <asm/dma.h>
37
38#include <asm/arch/hardware.h>
39#include <asm/arch/pxa-regs.h>
0aea1fd5 40#include <asm/arch/regs-ssp.h>
2f1a74e5 41#include <asm/arch/ssp.h>
e0c9905e
SS		 42#include <asm/arch/pxa2xx_spi.h>
43
44MODULE_AUTHOR("Stephen Street");
037cdafe 45MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
e0c9905e
SS		 46MODULE_LICENSE("GPL");
47
48#define MAX_BUSES 3
49
50#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
51#define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
52#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
53
b97c74bd
NF		 54/*
55 * for testing SSCR1 changes that require SSP restart, basically
56 * everything except the service and interrupt enables, the pxa270 developer
57 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
58 * list, but the PXA255 dev man says all bits without really meaning the
59 * service and interrupt enables
60 */
61#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
8d94cc50 62 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
b97c74bd
NF		 63 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
64 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
65 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
66 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
8d94cc50 67
e0c9905e
SS		 68#define DEFINE_SSP_REG(reg, off) \
69static inline u32 read_##reg(void *p) { return __raw_readl(p + (off)); } \
70static inline void write_##reg(u32 v, void *p) { __raw_writel(v, p + (off)); }
71
72DEFINE_SSP_REG(SSCR0, 0x00)
73DEFINE_SSP_REG(SSCR1, 0x04)
74DEFINE_SSP_REG(SSSR, 0x08)
75DEFINE_SSP_REG(SSITR, 0x0c)
76DEFINE_SSP_REG(SSDR, 0x10)
77DEFINE_SSP_REG(SSTO, 0x28)
78DEFINE_SSP_REG(SSPSP, 0x2c)
79
80#define START_STATE ((void*)0)
81#define RUNNING_STATE ((void*)1)
82#define DONE_STATE ((void*)2)
83#define ERROR_STATE ((void*)-1)
84
85#define QUEUE_RUNNING 0
86#define QUEUE_STOPPED 1
87
88struct driver_data {
89 /* Driver model hookup */
90 struct platform_device *pdev;
91
2f1a74e5 92 /* SSP Info */
93 struct ssp_device *ssp;
94
e0c9905e
SS		 95 /* SPI framework hookup */
96 enum pxa_ssp_type ssp_type;
97 struct spi_master *master;
98
99 /* PXA hookup */
100 struct pxa2xx_spi_master *master_info;
101
102 /* DMA setup stuff */
103 int rx_channel;
104 int tx_channel;
105 u32 *null_dma_buf;
106
107 /* SSP register addresses */
108 void *ioaddr;
109 u32 ssdr_physical;
110
111 /* SSP masks*/
112 u32 dma_cr1;
113 u32 int_cr1;
114 u32 clear_sr;
115 u32 mask_sr;
116
117 /* Driver message queue */
118 struct workqueue_struct *workqueue;
119 struct work_struct pump_messages;
120 spinlock_t lock;
121 struct list_head queue;
122 int busy;
123 int run;
124
125 /* Message Transfer pump */
126 struct tasklet_struct pump_transfers;
127
128 /* Current message transfer state info */
129 struct spi_message* cur_msg;
130 struct spi_transfer* cur_transfer;
131 struct chip_data *cur_chip;
132 size_t len;
133 void *tx;
134 void *tx_end;
135 void *rx;
136 void *rx_end;
137 int dma_mapped;
138 dma_addr_t rx_dma;
139 dma_addr_t tx_dma;
140 size_t rx_map_len;
141 size_t tx_map_len;
9708c121
SS		 142 u8 n_bytes;
143 u32 dma_width;
e0c9905e 144 int cs_change;
8d94cc50
SS		 145 int (*write)(struct driver_data *drv_data);
146 int (*read)(struct driver_data *drv_data);
e0c9905e
SS		 147 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
148 void (*cs_control)(u32 command);
149};
150
151struct chip_data {
152 u32 cr0;
153 u32 cr1;
e0c9905e
SS		 154 u32 psp;
155 u32 timeout;
156 u8 n_bytes;
157 u32 dma_width;
158 u32 dma_burst_size;
159 u32 threshold;
160 u32 dma_threshold;
161 u8 enable_dma;
9708c121
SS		 162 u8 bits_per_word;
163 u32 speed_hz;
8d94cc50
SS		 164 int (*write)(struct driver_data *drv_data);
165 int (*read)(struct driver_data *drv_data);
e0c9905e
SS		 166 void (*cs_control)(u32 command);
167};
168
6d5aefb8 169static void pump_messages(struct work_struct *work);
e0c9905e
SS		 170
171static int flush(struct driver_data *drv_data)
172{
173 unsigned long limit = loops_per_jiffy << 1;
174
175 void *reg = drv_data->ioaddr;
176
177 do {
178 while (read_SSSR(reg) & SSSR_RNE) {
179 read_SSDR(reg);
180 }
181 } while ((read_SSSR(reg) & SSSR_BSY) && limit--);
182 write_SSSR(SSSR_ROR, reg);
183
184 return limit;
185}
186
e0c9905e
SS		 187static void null_cs_control(u32 command)
188{
189}
190
8d94cc50 191static int null_writer(struct driver_data *drv_data)
e0c9905e
SS		 192{
193 void *reg = drv_data->ioaddr;
9708c121 194 u8 n_bytes = drv_data->n_bytes;
e0c9905e 195
8d94cc50
SS		 196 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
197 || (drv_data->tx == drv_data->tx_end))
198 return 0;
199
200 write_SSDR(0, reg);
201 drv_data->tx += n_bytes;
202
203 return 1;
e0c9905e
SS		 204}
205
8d94cc50 206static int null_reader(struct driver_data *drv_data)
e0c9905e
SS		 207{
208 void *reg = drv_data->ioaddr;
9708c121 209 u8 n_bytes = drv_data->n_bytes;
e0c9905e
SS		 210
211 while ((read_SSSR(reg) & SSSR_RNE)
8d94cc50 212 && (drv_data->rx < drv_data->rx_end)) {
e0c9905e
SS		 213 read_SSDR(reg);
214 drv_data->rx += n_bytes;
215 }
8d94cc50
SS		 216
217 return drv_data->rx == drv_data->rx_end;
e0c9905e
SS		 218}
219
8d94cc50 220static int u8_writer(struct driver_data *drv_data)
e0c9905e
SS		 221{
222 void *reg = drv_data->ioaddr;
223
8d94cc50
SS		 224 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
225 || (drv_data->tx == drv_data->tx_end))
226 return 0;
227
228 write_SSDR(*(u8 *)(drv_data->tx), reg);
229 ++drv_data->tx;
230
231 return 1;
e0c9905e
SS		 232}
233
8d94cc50 234static int u8_reader(struct driver_data *drv_data)
e0c9905e
SS		 235{
236 void *reg = drv_data->ioaddr;
237
238 while ((read_SSSR(reg) & SSSR_RNE)
8d94cc50 239 && (drv_data->rx < drv_data->rx_end)) {
e0c9905e
SS		 240 *(u8 *)(drv_data->rx) = read_SSDR(reg);
241 ++drv_data->rx;
242 }
8d94cc50
SS		 243
244 return drv_data->rx == drv_data->rx_end;
e0c9905e
SS		 245}
246
8d94cc50 247static int u16_writer(struct driver_data *drv_data)
e0c9905e
SS		 248{
249 void *reg = drv_data->ioaddr;
250
8d94cc50
SS		 251 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
252 || (drv_data->tx == drv_data->tx_end))
253 return 0;
254
255 write_SSDR(*(u16 *)(drv_data->tx), reg);
256 drv_data->tx += 2;
257
258 return 1;
e0c9905e
SS		 259}
260
8d94cc50 261static int u16_reader(struct driver_data *drv_data)
e0c9905e
SS		 262{
263 void *reg = drv_data->ioaddr;
264
265 while ((read_SSSR(reg) & SSSR_RNE)
8d94cc50 266 && (drv_data->rx < drv_data->rx_end)) {
e0c9905e
SS		 267 *(u16 *)(drv_data->rx) = read_SSDR(reg);
268 drv_data->rx += 2;
269 }
8d94cc50
SS		 270
271 return drv_data->rx == drv_data->rx_end;
e0c9905e 272}
8d94cc50
SS		 273
274static int u32_writer(struct driver_data *drv_data)
e0c9905e
SS		 275{
276 void *reg = drv_data->ioaddr;
277
8d94cc50
SS		 278 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
279 || (drv_data->tx == drv_data->tx_end))
280 return 0;
281
282 write_SSDR(*(u32 *)(drv_data->tx), reg);
283 drv_data->tx += 4;
284
285 return 1;
e0c9905e
SS		 286}
287
8d94cc50 288static int u32_reader(struct driver_data *drv_data)
e0c9905e
SS		 289{
290 void *reg = drv_data->ioaddr;
291
292 while ((read_SSSR(reg) & SSSR_RNE)
8d94cc50 293 && (drv_data->rx < drv_data->rx_end)) {
e0c9905e
SS		 294 *(u32 *)(drv_data->rx) = read_SSDR(reg);
295 drv_data->rx += 4;
296 }
8d94cc50
SS		 297
298 return drv_data->rx == drv_data->rx_end;
e0c9905e
SS		 299}
300
301static void *next_transfer(struct driver_data *drv_data)
302{
303 struct spi_message *msg = drv_data->cur_msg;
304 struct spi_transfer *trans = drv_data->cur_transfer;
305
306 /* Move to next transfer */
307 if (trans->transfer_list.next != &msg->transfers) {
308 drv_data->cur_transfer =
309 list_entry(trans->transfer_list.next,
310 struct spi_transfer,
311 transfer_list);
312 return RUNNING_STATE;
313 } else
314 return DONE_STATE;
315}
316
317static int map_dma_buffers(struct driver_data *drv_data)
318{
319 struct spi_message *msg = drv_data->cur_msg;
320 struct device *dev = &msg->spi->dev;
321
322 if (!drv_data->cur_chip->enable_dma)
323 return 0;
324
325 if (msg->is_dma_mapped)
326 return drv_data->rx_dma && drv_data->tx_dma;
327
328 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
329 return 0;
330
331 /* Modify setup if rx buffer is null */
332 if (drv_data->rx == NULL) {
333 *drv_data->null_dma_buf = 0;
334 drv_data->rx = drv_data->null_dma_buf;
335 drv_data->rx_map_len = 4;
336 } else
337 drv_data->rx_map_len = drv_data->len;
338
339
340 /* Modify setup if tx buffer is null */
341 if (drv_data->tx == NULL) {
342 *drv_data->null_dma_buf = 0;
343 drv_data->tx = drv_data->null_dma_buf;
344 drv_data->tx_map_len = 4;
345 } else
346 drv_data->tx_map_len = drv_data->len;
347
348 /* Stream map the rx buffer */
349 drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
350 drv_data->rx_map_len,
351 DMA_FROM_DEVICE);
352 if (dma_mapping_error(drv_data->rx_dma))
353 return 0;
354
355 /* Stream map the tx buffer */
356 drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
357 drv_data->tx_map_len,
358 DMA_TO_DEVICE);
359
360 if (dma_mapping_error(drv_data->tx_dma)) {
361 dma_unmap_single(dev, drv_data->rx_dma,
362 drv_data->rx_map_len, DMA_FROM_DEVICE);
363 return 0;
364 }
365
366 return 1;
367}
368
369static void unmap_dma_buffers(struct driver_data *drv_data)
370{
371 struct device *dev;
372
373 if (!drv_data->dma_mapped)
374 return;
375
376 if (!drv_data->cur_msg->is_dma_mapped) {
377 dev = &drv_data->cur_msg->spi->dev;
378 dma_unmap_single(dev, drv_data->rx_dma,
379 drv_data->rx_map_len, DMA_FROM_DEVICE);
380 dma_unmap_single(dev, drv_data->tx_dma,
381 drv_data->tx_map_len, DMA_TO_DEVICE);
382 }
383
384 drv_data->dma_mapped = 0;
385}
386
387/* caller already set message->status; dma and pio irqs are blocked */
5daa3ba0 388static void giveback(struct driver_data *drv_data)
e0c9905e
SS		 389{
390 struct spi_transfer* last_transfer;
5daa3ba0
SS		 391 unsigned long flags;
392 struct spi_message *msg;
e0c9905e 393
5daa3ba0
SS		 394 spin_lock_irqsave(&drv_data->lock, flags);
395 msg = drv_data->cur_msg;
396 drv_data->cur_msg = NULL;
397 drv_data->cur_transfer = NULL;
398 drv_data->cur_chip = NULL;
399 queue_work(drv_data->workqueue, &drv_data->pump_messages);
400 spin_unlock_irqrestore(&drv_data->lock, flags);
401
402 last_transfer = list_entry(msg->transfers.prev,
e0c9905e
SS		 403 struct spi_transfer,
404 transfer_list);
405
406 if (!last_transfer->cs_change)
407 drv_data->cs_control(PXA2XX_CS_DEASSERT);
408
5daa3ba0
SS		 409 msg->state = NULL;
410 if (msg->complete)
411 msg->complete(msg->context);
e0c9905e
SS		 412}
413
414static int wait_ssp_rx_stall(void *ioaddr)
415{
416 unsigned long limit = loops_per_jiffy << 1;
417
418 while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--)
419 cpu_relax();
420
421 return limit;
422}
423
424static int wait_dma_channel_stop(int channel)
425{
426 unsigned long limit = loops_per_jiffy << 1;
427
428 while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--)
429 cpu_relax();
430
431 return limit;
432}
433
8d94cc50 434void dma_error_stop(struct driver_data *drv_data, const char *msg)
e0c9905e 435{
e0c9905e 436 void *reg = drv_data->ioaddr;
e0c9905e 437
8d94cc50
SS		 438 /* Stop and reset */
439 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
440 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
441 write_SSSR(drv_data->clear_sr, reg);
442 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
443 if (drv_data->ssp_type != PXA25x_SSP)
444 write_SSTO(0, reg);
445 flush(drv_data);
446 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
e0c9905e 447
8d94cc50 448 unmap_dma_buffers(drv_data);
e0c9905e 449
8d94cc50 450 dev_err(&drv_data->pdev->dev, "%s\n", msg);
e0c9905e 451
8d94cc50
SS		 452 drv_data->cur_msg->state = ERROR_STATE;
453 tasklet_schedule(&drv_data->pump_transfers);
454}
455
456static void dma_transfer_complete(struct driver_data *drv_data)
457{
458 void *reg = drv_data->ioaddr;
459 struct spi_message *msg = drv_data->cur_msg;
460
461 /* Clear and disable interrupts on SSP and DMA channels*/
462 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
463 write_SSSR(drv_data->clear_sr, reg);
464 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
465 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
466
467 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
468 dev_err(&drv_data->pdev->dev,
469 "dma_handler: dma rx channel stop failed\n");
470
471 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
472 dev_err(&drv_data->pdev->dev,
473 "dma_transfer: ssp rx stall failed\n");
474
475 unmap_dma_buffers(drv_data);
476
477 /* update the buffer pointer for the amount completed in dma */
478 drv_data->rx += drv_data->len -
479 (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
480
481 /* read trailing data from fifo, it does not matter how many
482 * bytes are in the fifo just read until buffer is full
483 * or fifo is empty, which ever occurs first */
484 drv_data->read(drv_data);
485
486 /* return count of what was actually read */
487 msg->actual_length += drv_data->len -
488 (drv_data->rx_end - drv_data->rx);
489
490 /* Release chip select if requested, transfer delays are
491 * handled in pump_transfers */
492 if (drv_data->cs_change)
493 drv_data->cs_control(PXA2XX_CS_DEASSERT);
494
495 /* Move to next transfer */
496 msg->state = next_transfer(drv_data);
497
498 /* Schedule transfer tasklet */
499 tasklet_schedule(&drv_data->pump_transfers);
500}
501
502static void dma_handler(int channel, void *data)
503{
504 struct driver_data *drv_data = data;
505 u32 irq_status = DCSR(channel) & DMA_INT_MASK;
506
507 if (irq_status & DCSR_BUSERR) {
e0c9905e
SS		 508
509 if (channel == drv_data->tx_channel)
8d94cc50
SS		 510 dma_error_stop(drv_data,
511 "dma_handler: "
512 "bad bus address on tx channel");
e0c9905e 513 else
8d94cc50
SS		 514 dma_error_stop(drv_data,
515 "dma_handler: "
516 "bad bus address on rx channel");
517 return;
e0c9905e
SS		 518 }
519
520 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
8d94cc50
SS		 521 if ((channel == drv_data->tx_channel)
522 && (irq_status & DCSR_ENDINTR)
523 && (drv_data->ssp_type == PXA25x_SSP)) {
e0c9905e
SS		 524
525 /* Wait for rx to stall */
526 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
527 dev_err(&drv_data->pdev->dev,
528 "dma_handler: ssp rx stall failed\n");
529
8d94cc50
SS		 530 /* finish this transfer, start the next */
531 dma_transfer_complete(drv_data);
e0c9905e
SS		 532 }
533}
534
535static irqreturn_t dma_transfer(struct driver_data *drv_data)
536{
537 u32 irq_status;
e0c9905e
SS		 538 void *reg = drv_data->ioaddr;
539
540 irq_status = read_SSSR(reg) & drv_data->mask_sr;
541 if (irq_status & SSSR_ROR) {
8d94cc50 542 dma_error_stop(drv_data, "dma_transfer: fifo overrun");
e0c9905e
SS		 543 return IRQ_HANDLED;
544 }
545
546 /* Check for false positive timeout */
8d94cc50
SS		 547 if ((irq_status & SSSR_TINT)
548 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
e0c9905e
SS		 549 write_SSSR(SSSR_TINT, reg);
550 return IRQ_HANDLED;
551 }
552
553 if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
554
8d94cc50
SS		 555 /* Clear and disable timeout interrupt, do the rest in
556 * dma_transfer_complete */
e0c9905e
SS		 557 if (drv_data->ssp_type != PXA25x_SSP)
558 write_SSTO(0, reg);
e0c9905e 559
8d94cc50
SS		 560 /* finish this transfer, start the next */
561 dma_transfer_complete(drv_data);
e0c9905e
SS		 562
563 return IRQ_HANDLED;
564 }
565
566 /* Opps problem detected */
567 return IRQ_NONE;
568}
569
8d94cc50 570static void int_error_stop(struct driver_data *drv_data, const char* msg)
e0c9905e 571{
e0c9905e 572 void *reg = drv_data->ioaddr;
e0c9905e 573
8d94cc50
SS		 574 /* Stop and reset SSP */
575 write_SSSR(drv_data->clear_sr, reg);
576 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
577 if (drv_data->ssp_type != PXA25x_SSP)
578 write_SSTO(0, reg);
579 flush(drv_data);
580 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
e0c9905e 581
8d94cc50 582 dev_err(&drv_data->pdev->dev, "%s\n", msg);
e0c9905e 583
8d94cc50
SS		 584 drv_data->cur_msg->state = ERROR_STATE;
585 tasklet_schedule(&drv_data->pump_transfers);
586}
5daa3ba0 587
8d94cc50
SS		 588static void int_transfer_complete(struct driver_data *drv_data)
589{
590 void *reg = drv_data->ioaddr;
e0c9905e 591
8d94cc50
SS		 592 /* Stop SSP */
593 write_SSSR(drv_data->clear_sr, reg);
594 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
595 if (drv_data->ssp_type != PXA25x_SSP)
596 write_SSTO(0, reg);
e0c9905e 597
8d94cc50
SS		 598 /* Update total byte transfered return count actual bytes read */
599 drv_data->cur_msg->actual_length += drv_data->len -
600 (drv_data->rx_end - drv_data->rx);
e0c9905e 601
8d94cc50
SS		 602 /* Release chip select if requested, transfer delays are
603 * handled in pump_transfers */
604 if (drv_data->cs_change)
605 drv_data->cs_control(PXA2XX_CS_DEASSERT);
e0c9905e 606
8d94cc50
SS		 607 /* Move to next transfer */
608 drv_data->cur_msg->state = next_transfer(drv_data);
e0c9905e 609
8d94cc50
SS		 610 /* Schedule transfer tasklet */
611 tasklet_schedule(&drv_data->pump_transfers);
612}
e0c9905e 613
8d94cc50
SS		 614static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
615{
616 void *reg = drv_data->ioaddr;
e0c9905e 617
8d94cc50
SS		 618 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
619 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
e0c9905e 620
8d94cc50 621 u32 irq_status = read_SSSR(reg) & irq_mask;
e0c9905e 622
8d94cc50
SS		 623 if (irq_status & SSSR_ROR) {
624 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
625 return IRQ_HANDLED;
626 }
e0c9905e 627
8d94cc50
SS		 628 if (irq_status & SSSR_TINT) {
629 write_SSSR(SSSR_TINT, reg);
630 if (drv_data->read(drv_data)) {
631 int_transfer_complete(drv_data);
632 return IRQ_HANDLED;
633 }
634 }
e0c9905e 635
8d94cc50
SS		 636 /* Drain rx fifo, Fill tx fifo and prevent overruns */
637 do {
638 if (drv_data->read(drv_data)) {
639 int_transfer_complete(drv_data);
640 return IRQ_HANDLED;
641 }
642 } while (drv_data->write(drv_data));
e0c9905e 643
8d94cc50
SS		 644 if (drv_data->read(drv_data)) {
645 int_transfer_complete(drv_data);
646 return IRQ_HANDLED;
647 }
e0c9905e 648
8d94cc50
SS		 649 if (drv_data->tx == drv_data->tx_end) {
650 write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
651 /* PXA25x_SSP has no timeout, read trailing bytes */
652 if (drv_data->ssp_type == PXA25x_SSP) {
653 if (!wait_ssp_rx_stall(reg))
654 {
655 int_error_stop(drv_data, "interrupt_transfer: "
656 "rx stall failed");
657 return IRQ_HANDLED;
658 }
659 if (!drv_data->read(drv_data))
660 {
661 int_error_stop(drv_data,
662 "interrupt_transfer: "
663 "trailing byte read failed");
664 return IRQ_HANDLED;
665 }
666 int_transfer_complete(drv_data);
e0c9905e 667 }
e0c9905e
SS		 668 }
669
5daa3ba0
SS		 670 /* We did something */
671 return IRQ_HANDLED;
e0c9905e
SS		 672}
673
7d12e780 674static irqreturn_t ssp_int(int irq, void *dev_id)
e0c9905e 675{
c7bec5ab 676 struct driver_data *drv_data = dev_id;
5daa3ba0 677 void *reg = drv_data->ioaddr;
e0c9905e
SS		 678
679 if (!drv_data->cur_msg) {
5daa3ba0
SS		 680
681 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
682 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
683 if (drv_data->ssp_type != PXA25x_SSP)
684 write_SSTO(0, reg);
685 write_SSSR(drv_data->clear_sr, reg);
686
e0c9905e 687 dev_err(&drv_data->pdev->dev, "bad message state "
8d94cc50 688 "in interrupt handler\n");
5daa3ba0 689
e0c9905e
SS		 690 /* Never fail */
691 return IRQ_HANDLED;
692 }
693
694 return drv_data->transfer_handler(drv_data);
695}
696
8d94cc50
SS		 697int set_dma_burst_and_threshold(struct chip_data *chip, struct spi_device *spi,
698 u8 bits_per_word, u32 *burst_code,
699 u32 *threshold)
700{
701 struct pxa2xx_spi_chip *chip_info =
702 (struct pxa2xx_spi_chip *)spi->controller_data;
703 int bytes_per_word;
704 int burst_bytes;
705 int thresh_words;
706 int req_burst_size;
707 int retval = 0;
708
709 /* Set the threshold (in registers) to equal the same amount of data
710 * as represented by burst size (in bytes). The computation below
711 * is (burst_size rounded up to nearest 8 byte, word or long word)
712 * divided by (bytes/register); the tx threshold is the inverse of
713 * the rx, so that there will always be enough data in the rx fifo
714 * to satisfy a burst, and there will always be enough space in the
715 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
716 * there is not enough space), there must always remain enough empty
717 * space in the rx fifo for any data loaded to the tx fifo.
718 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
719 * will be 8, or half the fifo;
720 * The threshold can only be set to 2, 4 or 8, but not 16, because
721 * to burst 16 to the tx fifo, the fifo would have to be empty;
722 * however, the minimum fifo trigger level is 1, and the tx will
723 * request service when the fifo is at this level, with only 15 spaces.
724 */
725
726 /* find bytes/word */
727 if (bits_per_word <= 8)
728 bytes_per_word = 1;
729 else if (bits_per_word <= 16)
730 bytes_per_word = 2;
731 else
732 bytes_per_word = 4;
733
734 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
735 if (chip_info)
736 req_burst_size = chip_info->dma_burst_size;
737 else {
738 switch (chip->dma_burst_size) {
739 default:
740 /* if the default burst size is not set,
741 * do it now */
742 chip->dma_burst_size = DCMD_BURST8;
743 case DCMD_BURST8:
744 req_burst_size = 8;
745 break;
746 case DCMD_BURST16:
747 req_burst_size = 16;
748 break;
749 case DCMD_BURST32:
750 req_burst_size = 32;
751 break;
752 }
753 }
754 if (req_burst_size <= 8) {
755 *burst_code = DCMD_BURST8;
756 burst_bytes = 8;
757 } else if (req_burst_size <= 16) {
758 if (bytes_per_word == 1) {
759 /* don't burst more than 1/2 the fifo */
760 *burst_code = DCMD_BURST8;
761 burst_bytes = 8;
762 retval = 1;
763 } else {
764 *burst_code = DCMD_BURST16;
765 burst_bytes = 16;
766 }
767 } else {
768 if (bytes_per_word == 1) {
769 /* don't burst more than 1/2 the fifo */
770 *burst_code = DCMD_BURST8;
771 burst_bytes = 8;
772 retval = 1;
773 } else if (bytes_per_word == 2) {
774 /* don't burst more than 1/2 the fifo */
775 *burst_code = DCMD_BURST16;
776 burst_bytes = 16;
777 retval = 1;
778 } else {
779 *burst_code = DCMD_BURST32;
780 burst_bytes = 32;
781 }
782 }
783
784 thresh_words = burst_bytes / bytes_per_word;
785
786 /* thresh_words will be between 2 and 8 */
787 *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
788 | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
789
790 return retval;
791}
792
2f1a74e5 793static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
794{
795 unsigned long ssp_clk = clk_get_rate(ssp->clk);
796
797 if (ssp->type == PXA25x_SSP)
798 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
799 else
800 return ((ssp_clk / rate - 1) & 0xfff) << 8;
801}
802
e0c9905e
SS		 803static void pump_transfers(unsigned long data)
804{
805 struct driver_data *drv_data = (struct driver_data *)data;
806 struct spi_message *message = NULL;
807 struct spi_transfer *transfer = NULL;
808 struct spi_transfer *previous = NULL;
809 struct chip_data *chip = NULL;
2f1a74e5 810 struct ssp_device *ssp = drv_data->ssp;
e0c9905e 811 void *reg = drv_data->ioaddr;
9708c121
SS		 812 u32 clk_div = 0;
813 u8 bits = 0;
814 u32 speed = 0;
815 u32 cr0;
8d94cc50
SS		 816 u32 cr1;
817 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
818 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
e0c9905e
SS		 819
820 /* Get current state information */
821 message = drv_data->cur_msg;
822 transfer = drv_data->cur_transfer;
823 chip = drv_data->cur_chip;
824
825 /* Handle for abort */
826 if (message->state == ERROR_STATE) {
827 message->status = -EIO;
5daa3ba0 828 giveback(drv_data);
e0c9905e
SS		 829 return;
830 }
831
832 /* Handle end of message */
833 if (message->state == DONE_STATE) {
834 message->status = 0;
5daa3ba0 835 giveback(drv_data);
e0c9905e
SS		 836 return;
837 }
838
839 /* Delay if requested at end of transfer*/
840 if (message->state == RUNNING_STATE) {
841 previous = list_entry(transfer->transfer_list.prev,
842 struct spi_transfer,
843 transfer_list);
844 if (previous->delay_usecs)
845 udelay(previous->delay_usecs);
846 }
847
8d94cc50
SS		 848 /* Check transfer length */
849 if (transfer->len > 8191)
850 {
851 dev_warn(&drv_data->pdev->dev, "pump_transfers: transfer "
852 "length greater than 8191\n");
853 message->status = -EINVAL;
854 giveback(drv_data);
855 return;
856 }
857
e0c9905e
SS		 858 /* Setup the transfer state based on the type of transfer */
859 if (flush(drv_data) == 0) {
860 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
861 message->status = -EIO;
5daa3ba0 862 giveback(drv_data);
e0c9905e
SS		 863 return;
864 }
9708c121
SS		 865 drv_data->n_bytes = chip->n_bytes;
866 drv_data->dma_width = chip->dma_width;
e0c9905e
SS		 867 drv_data->cs_control = chip->cs_control;
868 drv_data->tx = (void *)transfer->tx_buf;
869 drv_data->tx_end = drv_data->tx + transfer->len;
870 drv_data->rx = transfer->rx_buf;
871 drv_data->rx_end = drv_data->rx + transfer->len;
872 drv_data->rx_dma = transfer->rx_dma;
873 drv_data->tx_dma = transfer->tx_dma;
8d94cc50 874 drv_data->len = transfer->len & DCMD_LENGTH;
e0c9905e
SS		 875 drv_data->write = drv_data->tx ? chip->write : null_writer;
876 drv_data->read = drv_data->rx ? chip->read : null_reader;
877 drv_data->cs_change = transfer->cs_change;
9708c121
SS		 878
879 /* Change speed and bit per word on a per transfer */
8d94cc50 880 cr0 = chip->cr0;
9708c121
SS		 881 if (transfer->speed_hz || transfer->bits_per_word) {
882
9708c121
SS		 883 bits = chip->bits_per_word;
884 speed = chip->speed_hz;
885
886 if (transfer->speed_hz)
887 speed = transfer->speed_hz;
888
889 if (transfer->bits_per_word)
890 bits = transfer->bits_per_word;
891
2f1a74e5 892 clk_div = ssp_get_clk_div(ssp, speed);
9708c121
SS		 893
894 if (bits <= 8) {
895 drv_data->n_bytes = 1;
896 drv_data->dma_width = DCMD_WIDTH1;
897 drv_data->read = drv_data->read != null_reader ?
898 u8_reader : null_reader;
899 drv_data->write = drv_data->write != null_writer ?
900 u8_writer : null_writer;
901 } else if (bits <= 16) {
902 drv_data->n_bytes = 2;
903 drv_data->dma_width = DCMD_WIDTH2;
904 drv_data->read = drv_data->read != null_reader ?
905 u16_reader : null_reader;
906 drv_data->write = drv_data->write != null_writer ?
907 u16_writer : null_writer;
908 } else if (bits <= 32) {
909 drv_data->n_bytes = 4;
910 drv_data->dma_width = DCMD_WIDTH4;
911 drv_data->read = drv_data->read != null_reader ?
912 u32_reader : null_reader;
913 drv_data->write = drv_data->write != null_writer ?
914 u32_writer : null_writer;
915 }
8d94cc50
SS		 916 /* if bits/word is changed in dma mode, then must check the
917 * thresholds and burst also */
918 if (chip->enable_dma) {
919 if (set_dma_burst_and_threshold(chip, message->spi,
920 bits, &dma_burst,
921 &dma_thresh))
922 if (printk_ratelimit())
923 dev_warn(&message->spi->dev,
924 "pump_transfer: "
925 "DMA burst size reduced to "
926 "match bits_per_word\n");
927 }
9708c121
SS		 928
929 cr0 = clk_div
930 | SSCR0_Motorola
5daa3ba0 931 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
9708c121
SS		 932 | SSCR0_SSE
933 | (bits > 16 ? SSCR0_EDSS : 0);
9708c121
SS		 934 }
935
e0c9905e
SS		 936 message->state = RUNNING_STATE;
937
938 /* Try to map dma buffer and do a dma transfer if successful */
939 if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) {
940
941 /* Ensure we have the correct interrupt handler */
942 drv_data->transfer_handler = dma_transfer;
943
944 /* Setup rx DMA Channel */
945 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
946 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
947 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
948 if (drv_data->rx == drv_data->null_dma_buf)
949 /* No target address increment */
950 DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
9708c121 951 | drv_data->dma_width
8d94cc50 952 | dma_burst
e0c9905e
SS		 953 | drv_data->len;
954 else
955 DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
956 | DCMD_FLOWSRC
9708c121 957 | drv_data->dma_width
8d94cc50 958 | dma_burst
e0c9905e
SS		 959 | drv_data->len;
960
961 /* Setup tx DMA Channel */
962 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
963 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
964 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
965 if (drv_data->tx == drv_data->null_dma_buf)
966 /* No source address increment */
967 DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
9708c121 968 | drv_data->dma_width
8d94cc50 969 | dma_burst
e0c9905e
SS		 970 | drv_data->len;
971 else
972 DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
973 | DCMD_FLOWTRG
9708c121 974 | drv_data->dma_width
8d94cc50 975 | dma_burst
e0c9905e
SS		 976 | drv_data->len;
977
978 /* Enable dma end irqs on SSP to detect end of transfer */
979 if (drv_data->ssp_type == PXA25x_SSP)
980 DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
981
8d94cc50
SS		 982 /* Clear status and start DMA engine */
983 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
e0c9905e
SS		 984 write_SSSR(drv_data->clear_sr, reg);
985 DCSR(drv_data->rx_channel) |= DCSR_RUN;
986 DCSR(drv_data->tx_channel) |= DCSR_RUN;
e0c9905e
SS		 987 } else {
988 /* Ensure we have the correct interrupt handler */
989 drv_data->transfer_handler = interrupt_transfer;
990
8d94cc50
SS		 991 /* Clear status */
992 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
e0c9905e 993 write_SSSR(drv_data->clear_sr, reg);
8d94cc50
SS		 994 }
995
996 /* see if we need to reload the config registers */
997 if ((read_SSCR0(reg) != cr0)
998 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
999 (cr1 & SSCR1_CHANGE_MASK)) {
1000
b97c74bd 1001 /* stop the SSP, and update the other bits */
8d94cc50 1002 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
e0c9905e
SS		 1003 if (drv_data->ssp_type != PXA25x_SSP)
1004 write_SSTO(chip->timeout, reg);
b97c74bd
NF		 1005 /* first set CR1 without interrupt and service enables */
1006 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
1007 /* restart the SSP */
8d94cc50 1008 write_SSCR0(cr0, reg);
b97c74bd 1009
8d94cc50
SS		 1010 } else {
1011 if (drv_data->ssp_type != PXA25x_SSP)
1012 write_SSTO(chip->timeout, reg);
e0c9905e 1013 }
b97c74bd
NF		 1014
1015 /* FIXME, need to handle cs polarity,
1016 * this driver uses struct pxa2xx_spi_chip.cs_control to
1017 * specify a CS handling function, and it ignores most
1018 * struct spi_device.mode[s], including SPI_CS_HIGH */
1019 drv_data->cs_control(PXA2XX_CS_ASSERT);
1020
1021 /* after chip select, release the data by enabling service
1022 * requests and interrupts, without changing any mode bits */
1023 write_SSCR1(cr1, reg);
e0c9905e
SS		 1024}
1025
6d5aefb8 1026static void pump_messages(struct work_struct *work)
e0c9905e 1027{
6d5aefb8
DH		 1028 struct driver_data *drv_data =
1029 container_of(work, struct driver_data, pump_messages);
e0c9905e
SS		 1030 unsigned long flags;
1031
1032 /* Lock queue and check for queue work */
1033 spin_lock_irqsave(&drv_data->lock, flags);
1034 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1035 drv_data->busy = 0;
1036 spin_unlock_irqrestore(&drv_data->lock, flags);
1037 return;
1038 }
1039
1040 /* Make sure we are not already running a message */
1041 if (drv_data->cur_msg) {
1042 spin_unlock_irqrestore(&drv_data->lock, flags);
1043 return;
1044 }
1045
1046 /* Extract head of queue */
1047 drv_data->cur_msg = list_entry(drv_data->queue.next,
1048 struct spi_message, queue);
1049 list_del_init(&drv_data->cur_msg->queue);
e0c9905e
SS		 1050
1051 /* Initial message state*/
1052 drv_data->cur_msg->state = START_STATE;
1053 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1054 struct spi_transfer,
1055 transfer_list);
1056
8d94cc50
SS		 1057 /* prepare to setup the SSP, in pump_transfers, using the per
1058 * chip configuration */
e0c9905e 1059 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
e0c9905e
SS		 1060
1061 /* Mark as busy and launch transfers */
1062 tasklet_schedule(&drv_data->pump_transfers);
5daa3ba0
SS		 1063
1064 drv_data->busy = 1;
1065 spin_unlock_irqrestore(&drv_data->lock, flags);
e0c9905e
SS		 1066}
1067
1068static int transfer(struct spi_device *spi, struct spi_message *msg)
1069{
1070 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1071 unsigned long flags;
1072
1073 spin_lock_irqsave(&drv_data->lock, flags);
1074
1075 if (drv_data->run == QUEUE_STOPPED) {
1076 spin_unlock_irqrestore(&drv_data->lock, flags);
1077 return -ESHUTDOWN;
1078 }
1079
1080 msg->actual_length = 0;
1081 msg->status = -EINPROGRESS;
1082 msg->state = START_STATE;
1083
1084 list_add_tail(&msg->queue, &drv_data->queue);
1085
1086 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1087 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1088
1089 spin_unlock_irqrestore(&drv_data->lock, flags);
1090
1091 return 0;
1092}
1093
dccd573b
DB		 1094/* the spi->mode bits understood by this driver: */
1095#define MODEBITS (SPI_CPOL | SPI_CPHA)
1096
e0c9905e
SS		 1097static int setup(struct spi_device *spi)
1098{
1099 struct pxa2xx_spi_chip *chip_info = NULL;
1100 struct chip_data *chip;
1101 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
2f1a74e5 1102 struct ssp_device *ssp = drv_data->ssp;
e0c9905e
SS		 1103 unsigned int clk_div;
1104
1105 if (!spi->bits_per_word)
1106 spi->bits_per_word = 8;
1107
1108 if (drv_data->ssp_type != PXA25x_SSP
8d94cc50
SS		 1109 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
1110 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1111 "b/w not 4-32 for type non-PXA25x_SSP\n",
1112 drv_data->ssp_type, spi->bits_per_word);
e0c9905e 1113 return -EINVAL;
8d94cc50
SS		 1114 }
1115 else if (drv_data->ssp_type == PXA25x_SSP
1116 && (spi->bits_per_word < 4
1117 || spi->bits_per_word > 16)) {
1118 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1119 "b/w not 4-16 for type PXA25x_SSP\n",
1120 drv_data->ssp_type, spi->bits_per_word);
e0c9905e 1121 return -EINVAL;
8d94cc50 1122 }
e0c9905e 1123
dccd573b
DB		 1124 if (spi->mode & ~MODEBITS) {
1125 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
1126 spi->mode & ~MODEBITS);
1127 return -EINVAL;
1128 }
1129
8d94cc50 1130 /* Only alloc on first setup */
e0c9905e 1131 chip = spi_get_ctldata(spi);
8d94cc50 1132 if (!chip) {
e0c9905e 1133 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
8d94cc50
SS		 1134 if (!chip) {
1135 dev_err(&spi->dev,
1136 "failed setup: can't allocate chip data\n");
e0c9905e 1137 return -ENOMEM;
8d94cc50 1138 }
e0c9905e
SS		 1139
1140 chip->cs_control = null_cs_control;
1141 chip->enable_dma = 0;
8d94cc50 1142 chip->timeout = 1000;
e0c9905e
SS		 1143 chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
1144 chip->dma_burst_size = drv_data->master_info->enable_dma ?
1145 DCMD_BURST8 : 0;
e0c9905e
SS		 1146 }
1147
8d94cc50
SS		 1148 /* protocol drivers may change the chip settings, so...
1149 * if chip_info exists, use it */
1150 chip_info = spi->controller_data;
1151
e0c9905e 1152 /* chip_info isn't always needed */
8d94cc50 1153 chip->cr1 = 0;
e0c9905e
SS		 1154 if (chip_info) {
1155 if (chip_info->cs_control)
1156 chip->cs_control = chip_info->cs_control;
1157
8d94cc50 1158 chip->timeout = chip_info->timeout;
e0c9905e 1159
8d94cc50
SS		 1160 chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) &
1161 SSCR1_RFT) |
1162 (SSCR1_TxTresh(chip_info->tx_threshold) &
1163 SSCR1_TFT);
e0c9905e
SS		 1164
1165 chip->enable_dma = chip_info->dma_burst_size != 0
1166 && drv_data->master_info->enable_dma;
1167 chip->dma_threshold = 0;
1168
e0c9905e
SS		 1169 if (chip_info->enable_loopback)
1170 chip->cr1 = SSCR1_LBM;
1171 }
1172
8d94cc50
SS		 1173 /* set dma burst and threshold outside of chip_info path so that if
1174 * chip_info goes away after setting chip->enable_dma, the
1175 * burst and threshold can still respond to changes in bits_per_word */
1176 if (chip->enable_dma) {
1177 /* set up legal burst and threshold for dma */
1178 if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
1179 &chip->dma_burst_size,
1180 &chip->dma_threshold)) {
1181 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
1182 "to match bits_per_word\n");
1183 }
1184 }
1185
2f1a74e5 1186 clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
9708c121 1187 chip->speed_hz = spi->max_speed_hz;
e0c9905e
SS		 1188
1189 chip->cr0 = clk_div
1190 | SSCR0_Motorola
5daa3ba0
SS		 1191 | SSCR0_DataSize(spi->bits_per_word > 16 ?
1192 spi->bits_per_word - 16 : spi->bits_per_word)
e0c9905e
SS		 1193 | SSCR0_SSE
1194 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
7f6ee1ad
JC		 1195 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1196 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1197 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
e0c9905e
SS		 1198
1199 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1200 if (drv_data->ssp_type != PXA25x_SSP)
2f1a74e5 1201 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
e0c9905e 1202 spi->bits_per_word,
2f1a74e5 1203 clk_get_rate(ssp->clk)
e0c9905e
SS		 1204 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1205 spi->mode & 0x3);
1206 else
2f1a74e5 1207 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
e0c9905e 1208 spi->bits_per_word,
2f1a74e5 1209 clk_get_rate(ssp->clk)
e0c9905e
SS		 1210 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1211 spi->mode & 0x3);
1212
1213 if (spi->bits_per_word <= 8) {
1214 chip->n_bytes = 1;
1215 chip->dma_width = DCMD_WIDTH1;
1216 chip->read = u8_reader;
1217 chip->write = u8_writer;
1218 } else if (spi->bits_per_word <= 16) {
1219 chip->n_bytes = 2;
1220 chip->dma_width = DCMD_WIDTH2;
1221 chip->read = u16_reader;
1222 chip->write = u16_writer;
1223 } else if (spi->bits_per_word <= 32) {
1224 chip->cr0 |= SSCR0_EDSS;
1225 chip->n_bytes = 4;
1226 chip->dma_width = DCMD_WIDTH4;
1227 chip->read = u32_reader;
1228 chip->write = u32_writer;
1229 } else {
1230 dev_err(&spi->dev, "invalid wordsize\n");
e0c9905e
SS		 1231 return -ENODEV;
1232 }
9708c121 1233 chip->bits_per_word = spi->bits_per_word;
e0c9905e
SS		 1234
1235 spi_set_ctldata(spi, chip);
1236
1237 return 0;
1238}
1239
0ffa0285 1240static void cleanup(struct spi_device *spi)
e0c9905e 1241{
0ffa0285 1242 struct chip_data *chip = spi_get_ctldata(spi);
e0c9905e
SS		 1243
1244 kfree(chip);
1245}
1246
d1e44d9c 1247static int __init init_queue(struct driver_data *drv_data)
e0c9905e
SS		 1248{
1249 INIT_LIST_HEAD(&drv_data->queue);
1250 spin_lock_init(&drv_data->lock);
1251
1252 drv_data->run = QUEUE_STOPPED;
1253 drv_data->busy = 0;
1254
1255 tasklet_init(&drv_data->pump_transfers,
1256 pump_transfers, (unsigned long)drv_data);
1257
6d5aefb8 1258 INIT_WORK(&drv_data->pump_messages, pump_messages);
e0c9905e 1259 drv_data->workqueue = create_singlethread_workqueue(
49dce689 1260 drv_data->master->dev.parent->bus_id);
e0c9905e
SS		 1261 if (drv_data->workqueue == NULL)
1262 return -EBUSY;
1263
1264 return 0;
1265}
1266
1267static int start_queue(struct driver_data *drv_data)
1268{
1269 unsigned long flags;
1270
1271 spin_lock_irqsave(&drv_data->lock, flags);
1272
1273 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1274 spin_unlock_irqrestore(&drv_data->lock, flags);
1275 return -EBUSY;
1276 }
1277
1278 drv_data->run = QUEUE_RUNNING;
1279 drv_data->cur_msg = NULL;
1280 drv_data->cur_transfer = NULL;
1281 drv_data->cur_chip = NULL;
1282 spin_unlock_irqrestore(&drv_data->lock, flags);
1283
1284 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1285
1286 return 0;
1287}
1288
1289static int stop_queue(struct driver_data *drv_data)
1290{
1291 unsigned long flags;
1292 unsigned limit = 500;
1293 int status = 0;
1294
1295 spin_lock_irqsave(&drv_data->lock, flags);
1296
1297 /* This is a bit lame, but is optimized for the common execution path.
1298 * A wait_queue on the drv_data->busy could be used, but then the common
1299 * execution path (pump_messages) would be required to call wake_up or
1300 * friends on every SPI message. Do this instead */
1301 drv_data->run = QUEUE_STOPPED;
1302 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1303 spin_unlock_irqrestore(&drv_data->lock, flags);
1304 msleep(10);
1305 spin_lock_irqsave(&drv_data->lock, flags);
1306 }
1307
1308 if (!list_empty(&drv_data->queue) || drv_data->busy)
1309 status = -EBUSY;
1310
1311 spin_unlock_irqrestore(&drv_data->lock, flags);
1312
1313 return status;
1314}
1315
1316static int destroy_queue(struct driver_data *drv_data)
1317{
1318 int status;
1319
1320 status = stop_queue(drv_data);
8d94cc50
SS		 1321 /* we are unloading the module or failing to load (only two calls
1322 * to this routine), and neither call can handle a return value.
1323 * However, destroy_workqueue calls flush_workqueue, and that will
1324 * block until all work is done. If the reason that stop_queue
1325 * timed out is that the work will never finish, then it does no
1326 * good to call destroy_workqueue, so return anyway. */
e0c9905e
SS		 1327 if (status != 0)
1328 return status;
1329
1330 destroy_workqueue(drv_data->workqueue);
1331
1332 return 0;
1333}
1334
d1e44d9c 1335static int __init pxa2xx_spi_probe(struct platform_device *pdev)
e0c9905e
SS		 1336{
1337 struct device *dev = &pdev->dev;
1338 struct pxa2xx_spi_master *platform_info;
1339 struct spi_master *master;
1340 struct driver_data *drv_data = 0;
2f1a74e5 1341 struct ssp_device *ssp;
e0c9905e
SS		 1342 int status = 0;
1343
1344 platform_info = dev->platform_data;
1345
2f1a74e5 1346 ssp = ssp_request(pdev->id, pdev->name);
1347 if (ssp == NULL) {
1348 dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
e0c9905e
SS		 1349 return -ENODEV;
1350 }
1351
1352 /* Allocate master with space for drv_data and null dma buffer */
1353 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1354 if (!master) {
1355 dev_err(&pdev->dev, "can not alloc spi_master\n");
2f1a74e5 1356 ssp_free(ssp);
e0c9905e
SS		 1357 return -ENOMEM;
1358 }
1359 drv_data = spi_master_get_devdata(master);
1360 drv_data->master = master;
1361 drv_data->master_info = platform_info;
1362 drv_data->pdev = pdev;
2f1a74e5 1363 drv_data->ssp = ssp;
e0c9905e
SS		 1364
1365 master->bus_num = pdev->id;
1366 master->num_chipselect = platform_info->num_chipselect;
1367 master->cleanup = cleanup;
1368 master->setup = setup;
1369 master->transfer = transfer;
1370
2f1a74e5 1371 drv_data->ssp_type = ssp->type;
e0c9905e
SS		 1372 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1373 sizeof(struct driver_data)), 8);
1374
2f1a74e5 1375 drv_data->ioaddr = ssp->mmio_base;
1376 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1377 if (ssp->type == PXA25x_SSP) {
e0c9905e
SS		 1378 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1379 drv_data->dma_cr1 = 0;
1380 drv_data->clear_sr = SSSR_ROR;
1381 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1382 } else {
1383 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1384 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1385 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1386 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1387 }
1388
2f1a74e5 1389 status = request_irq(ssp->irq, ssp_int, 0, dev->bus_id, drv_data);
e0c9905e
SS		 1390 if (status < 0) {
1391 dev_err(&pdev->dev, "can not get IRQ\n");
1392 goto out_error_master_alloc;
1393 }
1394
1395 /* Setup DMA if requested */
1396 drv_data->tx_channel = -1;
1397 drv_data->rx_channel = -1;
1398 if (platform_info->enable_dma) {
1399
1400 /* Get two DMA channels (rx and tx) */
1401 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1402 DMA_PRIO_HIGH,
1403 dma_handler,
1404 drv_data);
1405 if (drv_data->rx_channel < 0) {
1406 dev_err(dev, "problem (%d) requesting rx channel\n",
1407 drv_data->rx_channel);
1408 status = -ENODEV;
1409 goto out_error_irq_alloc;
1410 }
1411 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1412 DMA_PRIO_MEDIUM,
1413 dma_handler,
1414 drv_data);
1415 if (drv_data->tx_channel < 0) {
1416 dev_err(dev, "problem (%d) requesting tx channel\n",
1417 drv_data->tx_channel);
1418 status = -ENODEV;
1419 goto out_error_dma_alloc;
1420 }
1421
2f1a74e5 1422 DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
1423 DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
e0c9905e
SS		 1424 }
1425
1426 /* Enable SOC clock */
2f1a74e5 1427 clk_enable(ssp->clk);
e0c9905e
SS		 1428
1429 /* Load default SSP configuration */
1430 write_SSCR0(0, drv_data->ioaddr);
1431 write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr);
1432 write_SSCR0(SSCR0_SerClkDiv(2)
1433 | SSCR0_Motorola
1434 | SSCR0_DataSize(8),
1435 drv_data->ioaddr);
1436 if (drv_data->ssp_type != PXA25x_SSP)
1437 write_SSTO(0, drv_data->ioaddr);
1438 write_SSPSP(0, drv_data->ioaddr);
1439
1440 /* Initial and start queue */
1441 status = init_queue(drv_data);
1442 if (status != 0) {
1443 dev_err(&pdev->dev, "problem initializing queue\n");
1444 goto out_error_clock_enabled;
1445 }
1446 status = start_queue(drv_data);
1447 if (status != 0) {
1448 dev_err(&pdev->dev, "problem starting queue\n");
1449 goto out_error_clock_enabled;
1450 }
1451
1452 /* Register with the SPI framework */
1453 platform_set_drvdata(pdev, drv_data);
1454 status = spi_register_master(master);
1455 if (status != 0) {
1456 dev_err(&pdev->dev, "problem registering spi master\n");
1457 goto out_error_queue_alloc;
1458 }
1459
1460 return status;
1461
1462out_error_queue_alloc:
1463 destroy_queue(drv_data);
1464
1465out_error_clock_enabled:
2f1a74e5 1466 clk_disable(ssp->clk);
e0c9905e
SS		 1467
1468out_error_dma_alloc:
1469 if (drv_data->tx_channel != -1)
1470 pxa_free_dma(drv_data->tx_channel);
1471 if (drv_data->rx_channel != -1)
1472 pxa_free_dma(drv_data->rx_channel);
1473
1474out_error_irq_alloc:
2f1a74e5 1475 free_irq(ssp->irq, drv_data);
e0c9905e
SS		 1476
1477out_error_master_alloc:
1478 spi_master_put(master);
2f1a74e5 1479 ssp_free(ssp);
e0c9905e
SS		 1480 return status;
1481}
1482
1483static int pxa2xx_spi_remove(struct platform_device *pdev)
1484{
1485 struct driver_data *drv_data = platform_get_drvdata(pdev);
2f1a74e5 1486 struct ssp_device *ssp = drv_data->ssp;
e0c9905e
SS		 1487 int status = 0;
1488
1489 if (!drv_data)
1490 return 0;
1491
1492 /* Remove the queue */
1493 status = destroy_queue(drv_data);
1494 if (status != 0)
8d94cc50
SS		 1495 /* the kernel does not check the return status of this
1496 * this routine (mod->exit, within the kernel). Therefore
1497 * nothing is gained by returning from here, the module is
1498 * going away regardless, and we should not leave any more
1499 * resources allocated than necessary. We cannot free the
1500 * message memory in drv_data->queue, but we can release the
1501 * resources below. I think the kernel should honor -EBUSY
1502 * returns but... */
1503 dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
1504 "complete, message memory not freed\n");
e0c9905e
SS		 1505
1506 /* Disable the SSP at the peripheral and SOC level */
1507 write_SSCR0(0, drv_data->ioaddr);
2f1a74e5 1508 clk_disable(ssp->clk);
e0c9905e
SS		 1509
1510 /* Release DMA */
1511 if (drv_data->master_info->enable_dma) {
2f1a74e5 1512 DRCMR(ssp->drcmr_rx) = 0;
1513 DRCMR(ssp->drcmr_tx) = 0;
e0c9905e
SS		 1514 pxa_free_dma(drv_data->tx_channel);
1515 pxa_free_dma(drv_data->rx_channel);
1516 }
1517
1518 /* Release IRQ */
2f1a74e5 1519 free_irq(ssp->irq, drv_data);
1520
1521 /* Release SSP */
1522 ssp_free(ssp);
e0c9905e
SS		 1523
1524 /* Disconnect from the SPI framework */
1525 spi_unregister_master(drv_data->master);
1526
1527 /* Prevent double remove */
1528 platform_set_drvdata(pdev, NULL);
1529
1530 return 0;
1531}
1532
1533static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1534{
1535 int status = 0;
1536
1537 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1538 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1539}
1540
1541#ifdef CONFIG_PM
e0c9905e
SS		 1542
1543static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1544{
1545 struct driver_data *drv_data = platform_get_drvdata(pdev);
2f1a74e5 1546 struct ssp_device *ssp = drv_data->ssp;
e0c9905e
SS		 1547 int status = 0;
1548
e0c9905e
SS		 1549 status = stop_queue(drv_data);
1550 if (status != 0)
1551 return status;
1552 write_SSCR0(0, drv_data->ioaddr);
2f1a74e5 1553 clk_disable(ssp->clk);
e0c9905e
SS		 1554
1555 return 0;
1556}
1557
1558static int pxa2xx_spi_resume(struct platform_device *pdev)
1559{
1560 struct driver_data *drv_data = platform_get_drvdata(pdev);
2f1a74e5 1561 struct ssp_device *ssp = drv_data->ssp;
e0c9905e
SS		 1562 int status = 0;
1563
1564 /* Enable the SSP clock */
2f1a74e5 1565 clk_disable(ssp->clk);
e0c9905e
SS		 1566
1567 /* Start the queue running */
1568 status = start_queue(drv_data);
1569 if (status != 0) {
1570 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1571 return status;
1572 }
1573
1574 return 0;
1575}
1576#else
1577#define pxa2xx_spi_suspend NULL
1578#define pxa2xx_spi_resume NULL
1579#endif /* CONFIG_PM */
1580
1581static struct platform_driver driver = {
1582 .driver = {
1583 .name = "pxa2xx-spi",
1584 .bus = &platform_bus_type,
1585 .owner = THIS_MODULE,
1586 },
d1e44d9c 1587 .remove = pxa2xx_spi_remove,
e0c9905e
SS		 1588 .shutdown = pxa2xx_spi_shutdown,
1589 .suspend = pxa2xx_spi_suspend,
1590 .resume = pxa2xx_spi_resume,
1591};
1592
1593static int __init pxa2xx_spi_init(void)
1594{
d1e44d9c 1595 return platform_driver_probe(&driver, pxa2xx_spi_probe);
e0c9905e
SS		 1596}
1597module_init(pxa2xx_spi_init);
1598
1599static void __exit pxa2xx_spi_exit(void)
1600{
1601 platform_driver_unregister(&driver);
1602}
1603module_exit(pxa2xx_spi_exit);
kernel source for telekom puls (alcatel/mediatek)