projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] mv643xx_eth: Fix tx_timeout to only conditionally wake tx queue
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
cd28ab6a 26#include <linux/config.h>
793b883e 27#include <linux/crc32.h>
cd28ab6a
SH		 28#include <linux/kernel.h>
29#include <linux/version.h>
30#include <linux/module.h>
31#include <linux/netdevice.h>
d0bbccfa 32#include <linux/dma-mapping.h>
cd28ab6a
SH		 33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/in.h>
39#include <linux/delay.h>
91c86df5 40#include <linux/workqueue.h>
d1f13708 41#include <linux/if_vlan.h>
d70cd51a 42#include <linux/prefetch.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
8368f31c 54#define DRV_VERSION "1.1"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
62 */
63
13210ce5 64#define RX_LE_SIZE 512
cd28ab6a 65#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 66#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 67#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 68#define RX_SKB_ALIGN 8
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77#define ETH_JUMBO_MTU 9000
78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
82static const u32 default_msg =
793b883e
SH		 83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 86
793b883e 87static int debug = -1; /* defaults above */
cd28ab6a
SH		 88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
bdb5c58e
SH		 91static int copybreak __read_mostly = 256;
92module_param(copybreak, int, 0);
93MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
fb2690a9
SH		 95static int disable_msi = 0;
96module_param(disable_msi, int, 0);
97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
cd28ab6a 99static const struct pci_device_id sky2_id_table[] = {
793b883e 100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
cd28ab6a
SH		 102 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
103 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
104 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
cd28ab6a
SH		 117 { 0 }
118};
793b883e 119
cd28ab6a
SH		 120MODULE_DEVICE_TABLE(pci, sky2_id_table);
121
122/* Avoid conditionals by using array */
123static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
124static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
125
92f965e8
SH		 126/* This driver supports yukon2 chipset only */
127static const char *yukon2_name[] = {
128 "XL", /* 0xb3 */
129 "EC Ultra", /* 0xb4 */
130 "UNKNOWN", /* 0xb5 */
131 "EC", /* 0xb6 */
132 "FE", /* 0xb7 */
793b883e
SH		 133};
134
793b883e 135/* Access to external PHY */
ef743d33 136static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 137{
138 int i;
139
140 gma_write16(hw, port, GM_SMI_DATA, val);
141 gma_write16(hw, port, GM_SMI_CTRL,
142 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
143
144 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 145 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 146 return 0;
793b883e 147 udelay(1);
cd28ab6a 148 }
ef743d33 149
793b883e 150 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 151 return -ETIMEDOUT;
cd28ab6a
SH		 152}
153
ef743d33 154static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 155{
156 int i;
157
793b883e 158 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 159 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
160
161 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 162 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
163 *val = gma_read16(hw, port, GM_SMI_DATA);
164 return 0;
165 }
166
793b883e 167 udelay(1);
cd28ab6a
SH		 168 }
169
ef743d33
SH		 170 return -ETIMEDOUT;
171}
172
173static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
174{
175 u16 v;
176
177 if (__gm_phy_read(hw, port, reg, &v) != 0)
178 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
179 return v;
cd28ab6a
SH		 180}
181
5afa0a9c
SH		 182static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
183{
184 u16 power_control;
185 u32 reg1;
186 int vaux;
187 int ret = 0;
188
189 pr_debug("sky2_set_power_state %d\n", state);
190 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
191
56a645cc 192 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 193 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c
SH		 194 (power_control & PCI_PM_CAP_PME_D3cold);
195
56a645cc 196 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c
SH		 197
198 power_control |= PCI_PM_CTRL_PME_STATUS;
199 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
200
201 switch (state) {
202 case PCI_D0:
203 /* switch power to VCC (WA for VAUX problem) */
204 sky2_write8(hw, B0_POWER_CTRL,
205 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
206
207 /* disable Core Clock Division, */
208 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
209
210 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
211 /* enable bits are inverted */
212 sky2_write8(hw, B2_Y2_CLK_GATE,
213 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
214 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
215 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
216 else
217 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
218
219 /* Turn off phy power saving */
56a645cc 220 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c
SH		 221 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
222
d571b694 223 /* looks like this XL is back asswards .. */
5afa0a9c
SH		 224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
225 reg1 |= PCI_Y2_PHY1_COMA;
226 if (hw->ports > 1)
227 reg1 |= PCI_Y2_PHY2_COMA;
228 }
977bdf06
SH		 229
230 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
56a645cc
SH		 231 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
232 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 233 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 234 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
235 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 236 }
237
56a645cc 238 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
977bdf06 239
5afa0a9c
SH		 240 break;
241
242 case PCI_D3hot:
243 case PCI_D3cold:
244 /* Turn on phy power saving */
56a645cc 245 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c
SH		 246 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
247 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
248 else
249 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
56a645cc 250 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
5afa0a9c
SH		 251
252 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
253 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
254 else
255 /* enable bits are inverted */
256 sky2_write8(hw, B2_Y2_CLK_GATE,
257 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
258 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
259 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
260
261 /* switch power to VAUX */
262 if (vaux && state != PCI_D3cold)
263 sky2_write8(hw, B0_POWER_CTRL,
264 (PC_VAUX_ENA | PC_VCC_ENA |
265 PC_VAUX_ON | PC_VCC_OFF));
266 break;
267 default:
268 printk(KERN_ERR PFX "Unknown power state %d\n", state);
269 ret = -1;
270 }
271
56a645cc 272 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c
SH		 273 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
274 return ret;
275}
276
cd28ab6a
SH		 277static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
278{
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
283 /* disable PHY IRQs */
284 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 285
cd28ab6a
SH		 286 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
287 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
288 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
289 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
290
291 reg = gma_read16(hw, port, GM_RX_CTRL);
292 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
293 gma_write16(hw, port, GM_RX_CTRL, reg);
294}
295
296static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
297{
298 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 299 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 300
793b883e 301 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
cd28ab6a
SH		 302 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
303
304 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 305 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 306 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
307
308 if (hw->chip_id == CHIP_ID_YUKON_EC)
309 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
310 else
311 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
312
313 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
314 }
315
316 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
317 if (hw->copper) {
318 if (hw->chip_id == CHIP_ID_YUKON_FE) {
319 /* enable automatic crossover */
320 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
321 } else {
322 /* disable energy detect */
323 ctrl &= ~PHY_M_PC_EN_DET_MSK;
324
325 /* enable automatic crossover */
326 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
327
328 if (sky2->autoneg == AUTONEG_ENABLE &&
329 hw->chip_id == CHIP_ID_YUKON_XL) {
330 ctrl &= ~PHY_M_PC_DSC_MSK;
331 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
332 }
333 }
334 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
335 } else {
336 /* workaround for deviation #4.88 (CRC errors) */
337 /* disable Automatic Crossover */
338
339 ctrl &= ~PHY_M_PC_MDIX_MSK;
340 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
341
342 if (hw->chip_id == CHIP_ID_YUKON_XL) {
343 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
344 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
345 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
346 ctrl &= ~PHY_M_MAC_MD_MSK;
347 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
348 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
349
350 /* select page 1 to access Fiber registers */
351 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
352 }
cd28ab6a
SH		 353 }
354
355 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
356 if (sky2->autoneg == AUTONEG_DISABLE)
357 ctrl &= ~PHY_CT_ANE;
358 else
359 ctrl |= PHY_CT_ANE;
360
361 ctrl |= PHY_CT_RESET;
362 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
363
364 ctrl = 0;
365 ct1000 = 0;
366 adv = PHY_AN_CSMA;
367
368 if (sky2->autoneg == AUTONEG_ENABLE) {
369 if (hw->copper) {
370 if (sky2->advertising & ADVERTISED_1000baseT_Full)
371 ct1000 |= PHY_M_1000C_AFD;
372 if (sky2->advertising & ADVERTISED_1000baseT_Half)
373 ct1000 |= PHY_M_1000C_AHD;
374 if (sky2->advertising & ADVERTISED_100baseT_Full)
375 adv |= PHY_M_AN_100_FD;
376 if (sky2->advertising & ADVERTISED_100baseT_Half)
377 adv |= PHY_M_AN_100_HD;
378 if (sky2->advertising & ADVERTISED_10baseT_Full)
379 adv |= PHY_M_AN_10_FD;
380 if (sky2->advertising & ADVERTISED_10baseT_Half)
381 adv |= PHY_M_AN_10_HD;
793b883e 382 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 383 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
384
385 /* Set Flow-control capabilities */
386 if (sky2->tx_pause && sky2->rx_pause)
793b883e 387 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 388 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 389 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 390 else if (!sky2->rx_pause && sky2->tx_pause)
391 adv |= PHY_AN_PAUSE_ASYM; /* local */
392
393 /* Restart Auto-negotiation */
394 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
395 } else {
396 /* forced speed/duplex settings */
397 ct1000 = PHY_M_1000C_MSE;
398
399 if (sky2->duplex == DUPLEX_FULL)
400 ctrl |= PHY_CT_DUP_MD;
401
402 switch (sky2->speed) {
403 case SPEED_1000:
404 ctrl |= PHY_CT_SP1000;
405 break;
406 case SPEED_100:
407 ctrl |= PHY_CT_SP100;
408 break;
409 }
410
411 ctrl |= PHY_CT_RESET;
412 }
413
414 if (hw->chip_id != CHIP_ID_YUKON_FE)
415 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
416
417 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
418 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
419
420 /* Setup Phy LED's */
421 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
422 ledover = 0;
423
424 switch (hw->chip_id) {
425 case CHIP_ID_YUKON_FE:
426 /* on 88E3082 these bits are at 11..9 (shifted left) */
427 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
428
429 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
430
431 /* delete ACT LED control bits */
432 ctrl &= ~PHY_M_FELP_LED1_MSK;
433 /* change ACT LED control to blink mode */
434 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
435 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
436 break;
437
438 case CHIP_ID_YUKON_XL:
793b883e 439 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 440
441 /* select page 3 to access LED control register */
442 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
443
444 /* set LED Function Control register */
793b883e
SH		 445 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
446 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
447 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
448 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 449
450 /* set Polarity Control register */
451 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 452 (PHY_M_POLC_LS1_P_MIX(4) |
453 PHY_M_POLC_IS0_P_MIX(4) |
454 PHY_M_POLC_LOS_CTRL(2) |
455 PHY_M_POLC_INIT_CTRL(2) |
456 PHY_M_POLC_STA1_CTRL(2) |
457 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 458
459 /* restore page register */
793b883e 460 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 461 break;
462
463 default:
464 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
465 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
466 /* turn off the Rx LED (LED_RX) */
467 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
468 }
469
977bdf06
SH		 470 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
471 /* apply fixes in PHY AFE */
472 gm_phy_write(hw, port, 22, 255);
473 /* increase differential signal amplitude in 10BASE-T */
474 gm_phy_write(hw, port, 24, 0xaa99);
475 gm_phy_write(hw, port, 23, 0x2011);
cd28ab6a 476
977bdf06
SH		 477 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
478 gm_phy_write(hw, port, 24, 0xa204);
479 gm_phy_write(hw, port, 23, 0x2002);
480
481 /* set page register to 0 */
482 gm_phy_write(hw, port, 22, 0);
483 } else {
484 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 485
977bdf06
SH		 486 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
487 /* turn on 100 Mbps LED (LED_LINK100) */
488 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
489 }
cd28ab6a 490
977bdf06
SH		 491 if (ledover)
492 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
493
494 }
d571b694 495 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 496 if (sky2->autoneg == AUTONEG_ENABLE)
497 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
498 else
499 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
500}
501
1b537565
SH		 502/* Force a renegotiation */
503static void sky2_phy_reinit(struct sky2_port *sky2)
504{
e07b1aa8 505 spin_lock_bh(&sky2->phy_lock);
1b537565 506 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 507 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 508}
509
cd28ab6a
SH		 510static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
511{
512 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
513 u16 reg;
514 int i;
515 const u8 *addr = hw->dev[port]->dev_addr;
516
42eeea01
SH		 517 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
518 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 519
520 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
521
793b883e 522 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 523 /* WA DEV_472 -- looks like crossed wires on port 2 */
524 /* clear GMAC 1 Control reset */
525 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
526 do {
527 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
528 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
529 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
530 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
531 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
532 }
533
cd28ab6a
SH		 534 if (sky2->autoneg == AUTONEG_DISABLE) {
535 reg = gma_read16(hw, port, GM_GP_CTRL);
536 reg |= GM_GPCR_AU_ALL_DIS;
537 gma_write16(hw, port, GM_GP_CTRL, reg);
538 gma_read16(hw, port, GM_GP_CTRL);
539
cd28ab6a
SH		 540 switch (sky2->speed) {
541 case SPEED_1000:
6f4c56b2 542 reg &= ~GM_GPCR_SPEED_100;
cd28ab6a 543 reg |= GM_GPCR_SPEED_1000;
6f4c56b2 544 break;
cd28ab6a 545 case SPEED_100:
6f4c56b2 546 reg &= ~GM_GPCR_SPEED_1000;
cd28ab6a 547 reg |= GM_GPCR_SPEED_100;
6f4c56b2
SH		 548 break;
549 case SPEED_10:
550 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
551 break;
cd28ab6a
SH		 552 }
553
554 if (sky2->duplex == DUPLEX_FULL)
555 reg |= GM_GPCR_DUP_FULL;
556 } else
557 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
558
559 if (!sky2->tx_pause && !sky2->rx_pause) {
560 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 561 reg |=
562 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
563 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 564 /* disable Rx flow-control */
565 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
566 }
567
568 gma_write16(hw, port, GM_GP_CTRL, reg);
569
793b883e 570 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 571
e07b1aa8 572 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 573 sky2_phy_init(hw, port);
e07b1aa8 574 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 575
576 /* MIB clear */
577 reg = gma_read16(hw, port, GM_PHY_ADDR);
578 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
579
580 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
793b883e 581 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
cd28ab6a
SH		 582 gma_write16(hw, port, GM_PHY_ADDR, reg);
583
584 /* transmit control */
585 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
586
587 /* receive control reg: unicast + multicast + no FCS */
588 gma_write16(hw, port, GM_RX_CTRL,
793b883e 589 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 590
591 /* transmit flow control */
592 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
593
594 /* transmit parameter */
595 gma_write16(hw, port, GM_TX_PARAM,
596 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
597 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
598 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
599 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
600
601 /* serial mode register */
602 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 603 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 604
6b1a3aef 605 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 606 reg |= GM_SMOD_JUMBO_ENA;
607
608 gma_write16(hw, port, GM_SERIAL_MODE, reg);
609
cd28ab6a
SH		 610 /* virtual address for data */
611 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
612
793b883e
SH		 613 /* physical address: used for pause frames */
614 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
615
616 /* ignore counter overflows */
cd28ab6a
SH		 617 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
618 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
619 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
620
621 /* Configure Rx MAC FIFO */
622 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 623 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
624 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 625
d571b694 626 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 627 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 628
793b883e
SH		 629 /* Set threshold to 0xa (64 bytes)
630 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 631 */
632 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
633
634 /* Configure Tx MAC FIFO */
635 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
636 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 637
638 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
639 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
640 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
641 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
642 /* set Tx GMAC FIFO Almost Empty Threshold */
643 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
644 /* Disable Store & Forward mode for TX */
645 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
646 }
647 }
648
cd28ab6a
SH		 649}
650
1c28f6ba
SH		 651/* Assign Ram Buffer allocation.
652 * start and end are in units of 4k bytes
653 * ram registers are in units of 64bit words
654 */
655static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 656{
1c28f6ba 657 u32 start, end;
cd28ab6a 658
1c28f6ba
SH		 659 start = startk * 4096/8;
660 end = (endk * 4096/8) - 1;
793b883e 661
cd28ab6a
SH		 662 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
663 sky2_write32(hw, RB_ADDR(q, RB_START), start);
664 sky2_write32(hw, RB_ADDR(q, RB_END), end);
665 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
666 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
667
668 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 669 u32 space = (endk - startk) * 4096/8;
670 u32 tp = space - space/4;
793b883e 671
1c28f6ba
SH		 672 /* On receive queue's set the thresholds
673 * give receiver priority when > 3/4 full
674 * send pause when down to 2K
675 */
676 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
677 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 678
1c28f6ba
SH		 679 tp = space - 2048/8;
680 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
681 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 682 } else {
683 /* Enable store & forward on Tx queue's because
684 * Tx FIFO is only 1K on Yukon
685 */
686 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
687 }
688
689 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 690 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 691}
692
cd28ab6a 693/* Setup Bus Memory Interface */
af4ed7e6 694static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 695{
696 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
697 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
698 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 699 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 700}
701
cd28ab6a
SH		 702/* Setup prefetch unit registers. This is the interface between
703 * hardware and driver list elements
704 */
8cc048e3 705static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 706 u64 addr, u32 last)
707{
cd28ab6a
SH		 708 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
709 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
710 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
711 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
712 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
713 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 714
715 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 716}
717
793b883e
SH		 718static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
719{
720 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
721
722 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
723 return le;
724}
cd28ab6a 725
290d4de5
SH		 726/* Update chip's next pointer */
727static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 728{
762c2de2 729 wmb();
290d4de5 730 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
762c2de2 731 mmiowb();
cd28ab6a
SH		 732}
733
793b883e 734
cd28ab6a
SH		 735static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
736{
737 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
738 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
739 return le;
740}
741
a018e330
SH		 742/* Return high part of DMA address (could be 32 or 64 bit) */
743static inline u32 high32(dma_addr_t a)
744{
a036119f 745 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 746}
747
793b883e 748/* Build description to hardware about buffer */
28bd181a 749static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 750{
751 struct sky2_rx_le *le;
734d1868
SH		 752 u32 hi = high32(map);
753 u16 len = sky2->rx_bufsize;
cd28ab6a 754
793b883e 755 if (sky2->rx_addr64 != hi) {
cd28ab6a 756 le = sky2_next_rx(sky2);
793b883e 757 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 758 le->ctrl = 0;
759 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 760 sky2->rx_addr64 = high32(map + len);
cd28ab6a 761 }
793b883e 762
cd28ab6a 763 le = sky2_next_rx(sky2);
734d1868
SH		 764 le->addr = cpu_to_le32((u32) map);
765 le->length = cpu_to_le16(len);
cd28ab6a
SH		 766 le->ctrl = 0;
767 le->opcode = OP_PACKET | HW_OWNER;
768}
769
793b883e 770
cd28ab6a
SH		 771/* Tell chip where to start receive checksum.
772 * Actually has two checksums, but set both same to avoid possible byte
773 * order problems.
774 */
793b883e 775static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 776{
777 struct sky2_rx_le *le;
778
cd28ab6a 779 le = sky2_next_rx(sky2);
793b883e 780 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 781 le->ctrl = 0;
782 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 783
793b883e
SH		 784 sky2_write32(sky2->hw,
785 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
786 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 787
788}
789
6b1a3aef
SH		 790/*
791 * The RX Stop command will not work for Yukon-2 if the BMU does not
792 * reach the end of packet and since we can't make sure that we have
793 * incoming data, we must reset the BMU while it is not doing a DMA
794 * transfer. Since it is possible that the RX path is still active,
795 * the RX RAM buffer will be stopped first, so any possible incoming
796 * data will not trigger a DMA. After the RAM buffer is stopped, the
797 * BMU is polled until any DMA in progress is ended and only then it
798 * will be reset.
799 */
800static void sky2_rx_stop(struct sky2_port *sky2)
801{
802 struct sky2_hw *hw = sky2->hw;
803 unsigned rxq = rxqaddr[sky2->port];
804 int i;
805
806 /* disable the RAM Buffer receive queue */
807 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
808
809 for (i = 0; i < 0xffff; i++)
810 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
811 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
812 goto stopped;
813
814 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
815 sky2->netdev->name);
816stopped:
817 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
818
819 /* reset the Rx prefetch unit */
820 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
821}
793b883e 822
d571b694 823/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 824static void sky2_rx_clean(struct sky2_port *sky2)
825{
826 unsigned i;
827
828 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 829 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 830 struct ring_info *re = sky2->rx_ring + i;
831
832 if (re->skb) {
793b883e 833 pci_unmap_single(sky2->hw->pdev,
734d1868 834 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 835 PCI_DMA_FROMDEVICE);
836 kfree_skb(re->skb);
837 re->skb = NULL;
838 }
839 }
840}
841
ef743d33
SH		 842/* Basic MII support */
843static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
844{
845 struct mii_ioctl_data *data = if_mii(ifr);
846 struct sky2_port *sky2 = netdev_priv(dev);
847 struct sky2_hw *hw = sky2->hw;
848 int err = -EOPNOTSUPP;
849
850 if (!netif_running(dev))
851 return -ENODEV; /* Phy still in reset */
852
d89e1343 853 switch (cmd) {
ef743d33
SH		 854 case SIOCGMIIPHY:
855 data->phy_id = PHY_ADDR_MARV;
856
857 /* fallthru */
858 case SIOCGMIIREG: {
859 u16 val = 0;
91c86df5 860
e07b1aa8 861 spin_lock_bh(&sky2->phy_lock);
ef743d33 862 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 863 spin_unlock_bh(&sky2->phy_lock);
91c86df5 864
ef743d33
SH		 865 data->val_out = val;
866 break;
867 }
868
869 case SIOCSMIIREG:
870 if (!capable(CAP_NET_ADMIN))
871 return -EPERM;
872
e07b1aa8 873 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 874 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
875 data->val_in);
e07b1aa8 876 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 877 break;
878 }
879 return err;
880}
881
d1f13708
SH		 882#ifdef SKY2_VLAN_TAG_USED
883static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
884{
885 struct sky2_port *sky2 = netdev_priv(dev);
886 struct sky2_hw *hw = sky2->hw;
887 u16 port = sky2->port;
d1f13708 888
302d1252 889 spin_lock_bh(&sky2->tx_lock);
d1f13708
SH		 890
891 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
892 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
893 sky2->vlgrp = grp;
894
302d1252 895 spin_unlock_bh(&sky2->tx_lock);
d1f13708
SH		 896}
897
898static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
899{
900 struct sky2_port *sky2 = netdev_priv(dev);
901 struct sky2_hw *hw = sky2->hw;
902 u16 port = sky2->port;
d1f13708 903
302d1252 904 spin_lock_bh(&sky2->tx_lock);
d1f13708
SH		 905
906 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
907 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
908 if (sky2->vlgrp)
909 sky2->vlgrp->vlan_devices[vid] = NULL;
910
302d1252 911 spin_unlock_bh(&sky2->tx_lock);
d1f13708
SH		 912}
913#endif
914
82788c7a
SH		 915/*
916 * It appears the hardware has a bug in the FIFO logic that
917 * cause it to hang if the FIFO gets overrun and the receive buffer
918 * is not aligned. ALso alloc_skb() won't align properly if slab
919 * debugging is enabled.
920 */
921static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
922{
923 struct sk_buff *skb;
924
925 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
926 if (likely(skb)) {
927 unsigned long p = (unsigned long) skb->data;
928 skb_reserve(skb,
929 ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
930 }
931
932 return skb;
933}
934
cd28ab6a
SH		 935/*
936 * Allocate and setup receiver buffer pool.
937 * In case of 64 bit dma, there are 2X as many list elements
938 * available as ring entries
939 * and need to reserve one list element so we don't wrap around.
940 */
6b1a3aef 941static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 942{
6b1a3aef 943 struct sky2_hw *hw = sky2->hw;
6b1a3aef
SH		 944 unsigned rxq = rxqaddr[sky2->port];
945 int i;
cd28ab6a 946
6b1a3aef 947 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 948 sky2_qset(hw, rxq);
977bdf06
SH		 949
950 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
951 /* MAC Rx RAM Read is controlled by hardware */
952 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
953 }
954
6b1a3aef
SH		 955 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
956
957 rx_set_checksum(sky2);
793b883e 958 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 959 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 960
82788c7a 961 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
cd28ab6a
SH		 962 if (!re->skb)
963 goto nomem;
964
6b1a3aef 965 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 966 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
967 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 968 }
969
70f1be48
SH		 970 /* Truncate oversize frames */
971 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
972 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
973
6b1a3aef
SH		 974 /* Tell chip about available buffers */
975 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 976 return 0;
977nomem:
978 sky2_rx_clean(sky2);
979 return -ENOMEM;
980}
981
982/* Bring up network interface. */
983static int sky2_up(struct net_device *dev)
984{
985 struct sky2_port *sky2 = netdev_priv(dev);
986 struct sky2_hw *hw = sky2->hw;
987 unsigned port = sky2->port;
e07b1aa8 988 u32 ramsize, rxspace, imask;
cd28ab6a
SH		 989 int err = -ENOMEM;
990
991 if (netif_msg_ifup(sky2))
992 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
993
994 /* must be power of 2 */
995 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 996 TX_RING_SIZE *
997 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 998 &sky2->tx_le_map);
999 if (!sky2->tx_le)
1000 goto err_out;
1001
6cdbbdf3 1002 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1003 GFP_KERNEL);
1004 if (!sky2->tx_ring)
1005 goto err_out;
1006 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1007
1008 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1009 &sky2->rx_le_map);
1010 if (!sky2->rx_le)
1011 goto err_out;
1012 memset(sky2->rx_le, 0, RX_LE_BYTES);
1013
6cdbbdf3 1014 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 1015 GFP_KERNEL);
1016 if (!sky2->rx_ring)
1017 goto err_out;
1018
1019 sky2_mac_init(hw, port);
1020
1c28f6ba
SH		 1021 /* Determine available ram buffer space (in 4K blocks).
1022 * Note: not sure about the FE setting below yet
1023 */
1024 if (hw->chip_id == CHIP_ID_YUKON_FE)
1025 ramsize = 4;
1026 else
1027 ramsize = sky2_read8(hw, B2_E_0);
1028
1029 /* Give transmitter one third (rounded up) */
1030 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1031
cd28ab6a 1032 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1033 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1034
793b883e
SH		 1035 /* Make sure SyncQ is disabled */
1036 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1037 RB_RST_SET);
1038
af4ed7e6 1039 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1040
977bdf06
SH		 1041 /* Set almost empty threshold */
1042 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1043 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1044
6b1a3aef
SH		 1045 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1046 TX_RING_SIZE - 1);
cd28ab6a 1047
6b1a3aef 1048 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1049 if (err)
1050 goto err_out;
1051
cd28ab6a 1052 /* Enable interrupts from phy/mac for port */
e07b1aa8
SH		 1053 imask = sky2_read32(hw, B0_IMSK);
1054 imask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1055 sky2_write32(hw, B0_IMSK, imask);
1056
cd28ab6a
SH		 1057 return 0;
1058
1059err_out:
1b537565 1060 if (sky2->rx_le) {
cd28ab6a
SH		 1061 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1062 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1063 sky2->rx_le = NULL;
1064 }
1065 if (sky2->tx_le) {
cd28ab6a
SH		 1066 pci_free_consistent(hw->pdev,
1067 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1068 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1069 sky2->tx_le = NULL;
1070 }
1071 kfree(sky2->tx_ring);
1072 kfree(sky2->rx_ring);
cd28ab6a 1073
1b537565
SH		 1074 sky2->tx_ring = NULL;
1075 sky2->rx_ring = NULL;
cd28ab6a
SH		 1076 return err;
1077}
1078
793b883e
SH		 1079/* Modular subtraction in ring */
1080static inline int tx_dist(unsigned tail, unsigned head)
1081{
129372d0 1082 return (head - tail) % TX_RING_SIZE;
793b883e 1083}
cd28ab6a 1084
793b883e
SH		 1085/* Number of list elements available for next tx */
1086static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1087{
793b883e 1088 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1089}
1090
793b883e 1091/* Estimate of number of transmit list elements required */
28bd181a 1092static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1093{
793b883e
SH		 1094 unsigned count;
1095
1096 count = sizeof(dma_addr_t) / sizeof(u32);
1097 count += skb_shinfo(skb)->nr_frags * count;
1098
1099 if (skb_shinfo(skb)->tso_size)
1100 ++count;
1101
0e3ff6aa 1102 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1103 ++count;
1104
1105 return count;
cd28ab6a
SH		 1106}
1107
793b883e
SH		 1108/*
1109 * Put one packet in ring for transmit.
1110 * A single packet can generate multiple list elements, and
1111 * the number of ring elements will probably be less than the number
1112 * of list elements used.
f2e46561
SH		 1113 *
1114 * No BH disabling for tx_lock here (like tg3)
793b883e 1115 */
cd28ab6a
SH		 1116static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1117{
1118 struct sky2_port *sky2 = netdev_priv(dev);
1119 struct sky2_hw *hw = sky2->hw;
d1f13708 1120 struct sky2_tx_le *le = NULL;
6cdbbdf3 1121 struct tx_ring_info *re;
cd28ab6a 1122 unsigned i, len;
b19666d9 1123 int avail;
cd28ab6a
SH		 1124 dma_addr_t mapping;
1125 u32 addr64;
1126 u16 mss;
1127 u8 ctrl;
1128
302d1252
SH		 1129 /* No BH disabling for tx_lock here. We are running in BH disabled
1130 * context and TX reclaim runs via poll inside of a software
1131 * interrupt, and no related locks in IRQ processing.
1132 */
f2e46561 1133 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1134 return NETDEV_TX_LOCKED;
1135
793b883e 1136 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1137 /* There is a known but harmless race with lockless tx
1138 * and netif_stop_queue.
1139 */
1140 if (!netif_queue_stopped(dev)) {
1141 netif_stop_queue(dev);
3be92a70
SH		 1142 if (net_ratelimit())
1143 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1144 dev->name);
8c463ef7 1145 }
f2e46561 1146 spin_unlock(&sky2->tx_lock);
cd28ab6a 1147
cd28ab6a
SH		 1148 return NETDEV_TX_BUSY;
1149 }
1150
793b883e 1151 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1152 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1153 dev->name, sky2->tx_prod, skb->len);
1154
cd28ab6a
SH		 1155 len = skb_headlen(skb);
1156 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1157 addr64 = high32(mapping);
793b883e
SH		 1158
1159 re = sky2->tx_ring + sky2->tx_prod;
1160
a018e330
SH		 1161 /* Send high bits if changed or crosses boundary */
1162 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1163 le = get_tx_le(sky2);
1164 le->tx.addr = cpu_to_le32(addr64);
1165 le->ctrl = 0;
1166 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1167 sky2->tx_addr64 = high32(mapping + len);
793b883e 1168 }
cd28ab6a
SH		 1169
1170 /* Check for TCP Segmentation Offload */
1171 mss = skb_shinfo(skb)->tso_size;
793b883e 1172 if (mss != 0) {
cd28ab6a
SH		 1173 /* just drop the packet if non-linear expansion fails */
1174 if (skb_header_cloned(skb) &&
1175 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
15240072 1176 dev_kfree_skb(skb);
793b883e 1177 goto out_unlock;
cd28ab6a
SH		 1178 }
1179
1180 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1181 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1182 mss += ETH_HLEN;
793b883e 1183 }
cd28ab6a 1184
793b883e 1185 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1186 le = get_tx_le(sky2);
1187 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1188 le->tx.tso.rsvd = 0;
cd28ab6a 1189 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1190 le->ctrl = 0;
793b883e 1191 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1192 }
1193
cd28ab6a 1194 ctrl = 0;
d1f13708
SH		 1195#ifdef SKY2_VLAN_TAG_USED
1196 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1197 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1198 if (!le) {
1199 le = get_tx_le(sky2);
1200 le->tx.addr = 0;
1201 le->opcode = OP_VLAN|HW_OWNER;
1202 le->ctrl = 0;
1203 } else
1204 le->opcode |= OP_VLAN;
1205 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1206 ctrl |= INS_VLAN;
1207 }
1208#endif
1209
1210 /* Handle TCP checksum offload */
cd28ab6a 1211 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1212 u16 hdr = skb->h.raw - skb->data;
1213 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1214
1215 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1216 if (skb->nh.iph->protocol == IPPROTO_UDP)
1217 ctrl |= UDPTCP;
1218
1219 le = get_tx_le(sky2);
1220 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1221 le->tx.csum.offset = cpu_to_le16(offset);
1222 le->length = 0; /* initial checksum value */
cd28ab6a 1223 le->ctrl = 1; /* one packet */
793b883e 1224 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1225 }
1226
1227 le = get_tx_le(sky2);
1228 le->tx.addr = cpu_to_le32((u32) mapping);
1229 le->length = cpu_to_le16(len);
1230 le->ctrl = ctrl;
793b883e 1231 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1232
793b883e 1233 /* Record the transmit mapping info */
cd28ab6a 1234 re->skb = skb;
6cdbbdf3 1235 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1236
1237 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1238 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1239 struct tx_ring_info *fre;
cd28ab6a
SH		 1240
1241 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1242 frag->size, PCI_DMA_TODEVICE);
a036119f 1243 addr64 = high32(mapping);
793b883e
SH		 1244 if (addr64 != sky2->tx_addr64) {
1245 le = get_tx_le(sky2);
1246 le->tx.addr = cpu_to_le32(addr64);
1247 le->ctrl = 0;
1248 le->opcode = OP_ADDR64 | HW_OWNER;
1249 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1250 }
1251
1252 le = get_tx_le(sky2);
1253 le->tx.addr = cpu_to_le32((u32) mapping);
1254 le->length = cpu_to_le16(frag->size);
1255 le->ctrl = ctrl;
793b883e 1256 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1257
793b883e
SH		 1258 fre = sky2->tx_ring
1259 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
6cdbbdf3 1260 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1261 }
6cdbbdf3 1262
793b883e 1263 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1264 le->ctrl |= EOP;
1265
b19666d9
SH		 1266 avail = tx_avail(sky2);
1267 if (mss != 0 || avail < TX_MIN_PENDING) {
1268 le->ctrl |= FRC_STAT;
1269 if (avail <= MAX_SKB_TX_LE)
1270 netif_stop_queue(dev);
1271 }
1272
290d4de5 1273 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1274
793b883e 1275out_unlock:
f2e46561 1276 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1277
1278 dev->trans_start = jiffies;
1279 return NETDEV_TX_OK;
1280}
1281
cd28ab6a 1282/*
793b883e
SH		 1283 * Free ring elements from starting at tx_cons until "done"
1284 *
1285 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1286 * buffers; these are deferred until completion.
cd28ab6a 1287 */
d11c13e7 1288static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1289{
d11c13e7 1290 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1291 struct pci_dev *pdev = sky2->hw->pdev;
1292 u16 nxt, put;
793b883e 1293 unsigned i;
cd28ab6a 1294
0e3ff6aa 1295 BUG_ON(done >= TX_RING_SIZE);
2224795d 1296
d11c13e7 1297 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1298 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1299 dev->name, done);
cd28ab6a 1300
af2a58ac
SH		 1301 for (put = sky2->tx_cons; put != done; put = nxt) {
1302 struct tx_ring_info *re = sky2->tx_ring + put;
1303 struct sk_buff *skb = re->skb;
cd28ab6a 1304
d89e1343 1305 nxt = re->idx;
af2a58ac 1306 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1307 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1308
793b883e 1309 /* Check for partial status */
af2a58ac
SH		 1310 if (tx_dist(put, done) < tx_dist(put, nxt))
1311 break;
793b883e
SH		 1312
1313 skb = re->skb;
af2a58ac 1314 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1315 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1316
1317 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1318 struct tx_ring_info *fre;
af2a58ac
SH		 1319 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1320 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
d89e1343 1321 skb_shinfo(skb)->frags[i].size,
734d1868 1322 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1323 }
1324
15240072 1325 dev_kfree_skb(skb);
793b883e 1326 }
793b883e 1327
af2a58ac 1328 sky2->tx_cons = put;
8f24664d 1329 if (tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a 1330 netif_wake_queue(dev);
cd28ab6a
SH		 1331}
1332
1333/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1334static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1335{
302d1252 1336 spin_lock_bh(&sky2->tx_lock);
d11c13e7 1337 sky2_tx_complete(sky2, sky2->tx_prod);
302d1252 1338 spin_unlock_bh(&sky2->tx_lock);
cd28ab6a
SH		 1339}
1340
1341/* Network shutdown */
1342static int sky2_down(struct net_device *dev)
1343{
1344 struct sky2_port *sky2 = netdev_priv(dev);
1345 struct sky2_hw *hw = sky2->hw;
1346 unsigned port = sky2->port;
1347 u16 ctrl;
e07b1aa8 1348 u32 imask;
cd28ab6a 1349
1b537565
SH		 1350 /* Never really got started! */
1351 if (!sky2->tx_le)
1352 return 0;
1353
cd28ab6a
SH		 1354 if (netif_msg_ifdown(sky2))
1355 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1356
018d1c66 1357 /* Stop more packets from being queued */
cd28ab6a
SH		 1358 netif_stop_queue(dev);
1359
793b883e
SH		 1360 sky2_phy_reset(hw, port);
1361
cd28ab6a
SH		 1362 /* Stop transmitter */
1363 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1364 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1365
1366 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1367 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1368
1369 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1370 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1371 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1372
1373 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1374
1375 /* Workaround shared GMAC reset */
793b883e
SH		 1376 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1377 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1378 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1379
1380 /* Disable Force Sync bit and Enable Alloc bit */
1381 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1382 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1383
1384 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1385 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1386 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1387
1388 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1389 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1390 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1391
1392 /* Reset the Tx prefetch units */
1393 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1394 PREF_UNIT_RST_SET);
1395
1396 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1397
6b1a3aef 1398 sky2_rx_stop(sky2);
cd28ab6a
SH		 1399
1400 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1401 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1402
e07b1aa8
SH		 1403 /* Disable port IRQ */
1404 imask = sky2_read32(hw, B0_IMSK);
1405 imask &= ~(sky2->port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1406 sky2_write32(hw, B0_IMSK, imask);
1407
d571b694 1408 /* turn off LED's */
cd28ab6a
SH		 1409 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1410
018d1c66
SH		 1411 synchronize_irq(hw->pdev->irq);
1412
cd28ab6a
SH		 1413 sky2_tx_clean(sky2);
1414 sky2_rx_clean(sky2);
1415
1416 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1417 sky2->rx_le, sky2->rx_le_map);
1418 kfree(sky2->rx_ring);
1419
1420 pci_free_consistent(hw->pdev,
1421 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1422 sky2->tx_le, sky2->tx_le_map);
1423 kfree(sky2->tx_ring);
1424
1b537565
SH		 1425 sky2->tx_le = NULL;
1426 sky2->rx_le = NULL;
1427
1428 sky2->rx_ring = NULL;
1429 sky2->tx_ring = NULL;
1430
cd28ab6a
SH		 1431 return 0;
1432}
1433
1434static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1435{
793b883e
SH		 1436 if (!hw->copper)
1437 return SPEED_1000;
1438
cd28ab6a
SH		 1439 if (hw->chip_id == CHIP_ID_YUKON_FE)
1440 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1441
1442 switch (aux & PHY_M_PS_SPEED_MSK) {
1443 case PHY_M_PS_SPEED_1000:
1444 return SPEED_1000;
1445 case PHY_M_PS_SPEED_100:
1446 return SPEED_100;
1447 default:
1448 return SPEED_10;
1449 }
1450}
1451
1452static void sky2_link_up(struct sky2_port *sky2)
1453{
1454 struct sky2_hw *hw = sky2->hw;
1455 unsigned port = sky2->port;
1456 u16 reg;
1457
1458 /* Enable Transmit FIFO Underrun */
793b883e 1459 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1460
1461 reg = gma_read16(hw, port, GM_GP_CTRL);
6f4c56b2
SH		 1462 if (sky2->autoneg == AUTONEG_DISABLE) {
1463 reg |= GM_GPCR_AU_ALL_DIS;
1464
1465 /* Is write/read necessary? Copied from sky2_mac_init */
1466 gma_write16(hw, port, GM_GP_CTRL, reg);
1467 gma_read16(hw, port, GM_GP_CTRL);
1468
1469 switch (sky2->speed) {
1470 case SPEED_1000:
1471 reg &= ~GM_GPCR_SPEED_100;
1472 reg |= GM_GPCR_SPEED_1000;
1473 break;
1474 case SPEED_100:
1475 reg &= ~GM_GPCR_SPEED_1000;
1476 reg |= GM_GPCR_SPEED_100;
1477 break;
1478 case SPEED_10:
1479 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1480 break;
1481 }
1482 } else
1483 reg &= ~GM_GPCR_AU_ALL_DIS;
1484
cd28ab6a
SH		 1485 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1486 reg |= GM_GPCR_DUP_FULL;
1487
cd28ab6a
SH		 1488 /* enable Rx/Tx */
1489 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1490 gma_write16(hw, port, GM_GP_CTRL, reg);
1491 gma_read16(hw, port, GM_GP_CTRL);
1492
1493 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1494
1495 netif_carrier_on(sky2->netdev);
1496 netif_wake_queue(sky2->netdev);
1497
1498 /* Turn on link LED */
793b883e 1499 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1500 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1501
793b883e
SH		 1502 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1503 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1504
1505 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1506 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1507 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1508 SPEED_10 ? 7 : 0) |
1509 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1510 SPEED_100 ? 7 : 0) |
1511 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1512 SPEED_1000 ? 7 : 0));
1513 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1514 }
1515
cd28ab6a
SH		 1516 if (netif_msg_link(sky2))
1517 printk(KERN_INFO PFX
d571b694 1518 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1519 sky2->netdev->name, sky2->speed,
1520 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1521 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1522 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1523}
1524
1525static void sky2_link_down(struct sky2_port *sky2)
1526{
1527 struct sky2_hw *hw = sky2->hw;
1528 unsigned port = sky2->port;
1529 u16 reg;
1530
1531 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1532
1533 reg = gma_read16(hw, port, GM_GP_CTRL);
1534 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1535 gma_write16(hw, port, GM_GP_CTRL, reg);
1536 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1537
1538 if (sky2->rx_pause && !sky2->tx_pause) {
1539 /* restore Asymmetric Pause bit */
1540 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1541 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1542 | PHY_M_AN_ASP);
cd28ab6a
SH		 1543 }
1544
cd28ab6a
SH		 1545 netif_carrier_off(sky2->netdev);
1546 netif_stop_queue(sky2->netdev);
1547
1548 /* Turn on link LED */
1549 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1550
1551 if (netif_msg_link(sky2))
1552 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1553 sky2_phy_init(hw, port);
1554}
1555
793b883e
SH		 1556static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1557{
1558 struct sky2_hw *hw = sky2->hw;
1559 unsigned port = sky2->port;
1560 u16 lpa;
1561
1562 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1563
1564 if (lpa & PHY_M_AN_RF) {
1565 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1566 return -1;
1567 }
1568
1569 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1570 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1571 printk(KERN_ERR PFX "%s: master/slave fault",
1572 sky2->netdev->name);
1573 return -1;
1574 }
1575
1576 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1577 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1578 sky2->netdev->name);
1579 return -1;
1580 }
1581
1582 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1583
1584 sky2->speed = sky2_phy_speed(hw, aux);
1585
1586 /* Pause bits are offset (9..8) */
1587 if (hw->chip_id == CHIP_ID_YUKON_XL)
1588 aux >>= 6;
1589
1590 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1591 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1592
1593 if ((sky2->tx_pause || sky2->rx_pause)
1594 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1595 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1596 else
1597 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1598
1599 return 0;
1600}
cd28ab6a 1601
e07b1aa8
SH		 1602/* Interrupt from PHY */
1603static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1604{
e07b1aa8
SH		 1605 struct net_device *dev = hw->dev[port];
1606 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1607 u16 istatus, phystat;
1608
e07b1aa8
SH		 1609 spin_lock(&sky2->phy_lock);
1610 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1611 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1612
1613 if (!netif_running(dev))
1614 goto out;
cd28ab6a
SH		 1615
1616 if (netif_msg_intr(sky2))
1617 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1618 sky2->netdev->name, istatus, phystat);
1619
1620 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1621 if (sky2_autoneg_done(sky2, phystat) == 0)
1622 sky2_link_up(sky2);
1623 goto out;
1624 }
cd28ab6a 1625
793b883e
SH		 1626 if (istatus & PHY_M_IS_LSP_CHANGE)
1627 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1628
793b883e
SH		 1629 if (istatus & PHY_M_IS_DUP_CHANGE)
1630 sky2->duplex =
1631 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1632
793b883e
SH		 1633 if (istatus & PHY_M_IS_LST_CHANGE) {
1634 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1635 sky2_link_up(sky2);
793b883e
SH		 1636 else
1637 sky2_link_down(sky2);
cd28ab6a 1638 }
793b883e 1639out:
e07b1aa8 1640 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1641}
1642
302d1252
SH		 1643
1644/* Transmit timeout is only called if we are running, carries is up
1645 * and tx queue is full (stopped).
1646 */
cd28ab6a
SH		 1647static void sky2_tx_timeout(struct net_device *dev)
1648{
1649 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1650 struct sky2_hw *hw = sky2->hw;
1651 unsigned txq = txqaddr[sky2->port];
8f24664d 1652 u16 report, done;
cd28ab6a
SH		 1653
1654 if (netif_msg_timer(sky2))
1655 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1656
8f24664d
SH		 1657 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1658 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1659
8f24664d
SH		 1660 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1661 dev->name,
1662 sky2->tx_cons, sky2->tx_prod, report, done);
1663
1664 if (report != done) {
1665 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1666
1667 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1668 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1669 } else if (report != sky2->tx_cons) {
1670 printk(KERN_INFO PFX "status report lost?\n");
1671
1672 spin_lock_bh(&sky2->tx_lock);
1673 sky2_tx_complete(sky2, report);
1674 spin_unlock_bh(&sky2->tx_lock);
1675 } else {
1676 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1677
8f24664d
SH		 1678 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1679 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1680
1681 sky2_tx_clean(sky2);
1682
1683 sky2_qset(hw, txq);
1684 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1685 }
cd28ab6a
SH		 1686}
1687
734d1868
SH		 1688
1689#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
70f1be48
SH		 1690/* Want receive buffer size to be multiple of 64 bits
1691 * and incl room for vlan and truncation
1692 */
734d1868
SH		 1693static inline unsigned sky2_buf_size(int mtu)
1694{
70f1be48 1695 return roundup(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
734d1868
SH		 1696}
1697
cd28ab6a
SH		 1698static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1699{
6b1a3aef
SH		 1700 struct sky2_port *sky2 = netdev_priv(dev);
1701 struct sky2_hw *hw = sky2->hw;
1702 int err;
1703 u16 ctl, mode;
e07b1aa8 1704 u32 imask;
cd28ab6a
SH		 1705
1706 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1707 return -EINVAL;
1708
5a5b1ea0
SH		 1709 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1710 return -EINVAL;
1711
6b1a3aef
SH		 1712 if (!netif_running(dev)) {
1713 dev->mtu = new_mtu;
1714 return 0;
1715 }
1716
e07b1aa8 1717 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1718 sky2_write32(hw, B0_IMSK, 0);
1719
018d1c66
SH		 1720 dev->trans_start = jiffies; /* prevent tx timeout */
1721 netif_stop_queue(dev);
1722 netif_poll_disable(hw->dev[0]);
1723
e07b1aa8
SH		 1724 synchronize_irq(hw->pdev->irq);
1725
6b1a3aef
SH		 1726 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1727 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1728 sky2_rx_stop(sky2);
1729 sky2_rx_clean(sky2);
cd28ab6a
SH		 1730
1731 dev->mtu = new_mtu;
734d1868 1732 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef
SH		 1733 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1734 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1735
1736 if (dev->mtu > ETH_DATA_LEN)
1737 mode |= GM_SMOD_JUMBO_ENA;
1738
1739 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1740
6b1a3aef 1741 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1742
6b1a3aef 1743 err = sky2_rx_start(sky2);
e07b1aa8 1744 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1745
1b537565
SH		 1746 if (err)
1747 dev_close(dev);
1748 else {
1749 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1750
1751 netif_poll_enable(hw->dev[0]);
1752 netif_wake_queue(dev);
1753 }
1754
cd28ab6a
SH		 1755 return err;
1756}
1757
1758/*
1759 * Receive one packet.
1760 * For small packets or errors, just reuse existing skb.
d571b694 1761 * For larger packets, get new buffer.
cd28ab6a 1762 */
d11c13e7 1763static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1764 u16 length, u32 status)
1765{
cd28ab6a 1766 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1767 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1768
1769 if (unlikely(netif_msg_rx_status(sky2)))
1770 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1771 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1772
793b883e 1773 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1774 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1775
42eeea01 1776 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1777 goto error;
1778
42eeea01
SH		 1779 if (!(status & GMR_FS_RX_OK))
1780 goto resubmit;
1781
70f1be48 1782 if (length > sky2->netdev->mtu + ETH_HLEN)
6e15b712
SH		 1783 goto oversize;
1784
bdb5c58e 1785 if (length < copybreak) {
79e57d32
SH		 1786 skb = alloc_skb(length + 2, GFP_ATOMIC);
1787 if (!skb)
793b883e
SH		 1788 goto resubmit;
1789
79e57d32 1790 skb_reserve(skb, 2);
793b883e
SH		 1791 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1792 length, PCI_DMA_FROMDEVICE);
79e57d32 1793 memcpy(skb->data, re->skb->data, length);
d11c13e7
SH		 1794 skb->ip_summed = re->skb->ip_summed;
1795 skb->csum = re->skb->csum;
793b883e
SH		 1796 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1797 length, PCI_DMA_FROMDEVICE);
793b883e 1798 } else {
79e57d32
SH		 1799 struct sk_buff *nskb;
1800
82788c7a 1801 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1802 if (!nskb)
1803 goto resubmit;
cd28ab6a 1804
793b883e 1805 skb = re->skb;
79e57d32 1806 re->skb = nskb;
793b883e 1807 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1808 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1809 prefetch(skb->data);
cd28ab6a 1810
793b883e 1811 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1812 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1813 }
cd28ab6a 1814
79e57d32 1815 skb_put(skb, length);
793b883e 1816resubmit:
d11c13e7 1817 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1818 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1819
bea86103 1820 /* Tell receiver about new buffers. */
290d4de5 1821 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
bea86103 1822
cd28ab6a
SH		 1823 return skb;
1824
6e15b712
SH		 1825oversize:
1826 ++sky2->net_stats.rx_over_errors;
1827 goto resubmit;
1828
cd28ab6a 1829error:
6e15b712
SH		 1830 ++sky2->net_stats.rx_errors;
1831
3be92a70 1832 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a
SH		 1833 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1834 sky2->netdev->name, status, length);
793b883e
SH		 1835
1836 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1837 sky2->net_stats.rx_length_errors++;
1838 if (status & GMR_FS_FRAGMENT)
1839 sky2->net_stats.rx_frame_errors++;
1840 if (status & GMR_FS_CRC_ERR)
1841 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1842 if (status & GMR_FS_RX_FF_OV)
1843 sky2->net_stats.rx_fifo_errors++;
79e57d32 1844
793b883e 1845 goto resubmit;
cd28ab6a
SH		 1846}
1847
e07b1aa8
SH		 1848/* Transmit complete */
1849static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 1850{
e07b1aa8 1851 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 1852
e07b1aa8
SH		 1853 if (netif_running(dev)) {
1854 spin_lock(&sky2->tx_lock);
1855 sky2_tx_complete(sky2, last);
1856 spin_unlock(&sky2->tx_lock);
2224795d 1857 }
cd28ab6a
SH		 1858}
1859
e07b1aa8
SH		 1860/* Process status response ring */
1861static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 1862{
e07b1aa8 1863 int work_done = 0;
a8fd6266 1864
af2a58ac 1865 rmb();
bea86103 1866
e07b1aa8 1867 for(;;) {
13210ce5
SH		 1868 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1869 struct net_device *dev;
d11c13e7 1870 struct sky2_port *sky2;
cd28ab6a 1871 struct sk_buff *skb;
cd28ab6a
SH		 1872 u32 status;
1873 u16 length;
e07b1aa8
SH		 1874 u8 link, opcode;
1875
1876 opcode = le->opcode;
1877 if (!opcode)
1878 break;
1879 opcode &= ~HW_OWNER;
cd28ab6a 1880
bea86103 1881 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
e07b1aa8 1882 le->opcode = 0;
bea86103 1883
e07b1aa8
SH		 1884 link = le->link;
1885 BUG_ON(link >= 2);
1886 dev = hw->dev[link];
13210ce5
SH		 1887
1888 sky2 = netdev_priv(dev);
e07b1aa8
SH		 1889 length = le->length;
1890 status = le->status;
cd28ab6a 1891
e07b1aa8 1892 switch (opcode) {
cd28ab6a 1893 case OP_RXSTAT:
d11c13e7 1894 skb = sky2_receive(sky2, length, status);
d1f13708
SH		 1895 if (!skb)
1896 break;
13210ce5
SH		 1897
1898 skb->dev = dev;
1899 skb->protocol = eth_type_trans(skb, dev);
1900 dev->last_rx = jiffies;
1901
d1f13708
SH		 1902#ifdef SKY2_VLAN_TAG_USED
1903 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1904 vlan_hwaccel_receive_skb(skb,
1905 sky2->vlgrp,
1906 be16_to_cpu(sky2->rx_tag));
1907 } else
1908#endif
cd28ab6a 1909 netif_receive_skb(skb);
13210ce5
SH		 1910
1911 if (++work_done >= to_do)
1912 goto exit_loop;
cd28ab6a
SH		 1913 break;
1914
d1f13708
SH		 1915#ifdef SKY2_VLAN_TAG_USED
1916 case OP_RXVLAN:
1917 sky2->rx_tag = length;
1918 break;
1919
1920 case OP_RXCHKSVLAN:
1921 sky2->rx_tag = length;
1922 /* fall through */
1923#endif
cd28ab6a 1924 case OP_RXCHKS:
d11c13e7
SH		 1925 skb = sky2->rx_ring[sky2->rx_next].skb;
1926 skb->ip_summed = CHECKSUM_HW;
1927 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1928 break;
1929
1930 case OP_TXINDEXLE:
13b97b74 1931 /* TX index reports status for both ports */
e07b1aa8
SH		 1932 sky2_tx_done(hw->dev[0], status & 0xffff);
1933 if (hw->dev[1])
1934 sky2_tx_done(hw->dev[1],
1935 ((status >> 24) & 0xff)
1936 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 1937 break;
1938
cd28ab6a
SH		 1939 default:
1940 if (net_ratelimit())
793b883e 1941 printk(KERN_WARNING PFX
e07b1aa8 1942 "unknown status opcode 0x%x\n", opcode);
cd28ab6a
SH		 1943 break;
1944 }
13210ce5 1945 }
cd28ab6a 1946
13210ce5 1947exit_loop:
e07b1aa8 1948 return work_done;
cd28ab6a
SH		 1949}
1950
1951static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1952{
1953 struct net_device *dev = hw->dev[port];
1954
3be92a70
SH		 1955 if (net_ratelimit())
1956 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1957 dev->name, status);
cd28ab6a
SH		 1958
1959 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 1960 if (net_ratelimit())
1961 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1962 dev->name);
cd28ab6a
SH		 1963 /* Clear IRQ */
1964 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1965 }
1966
1967 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 1968 if (net_ratelimit())
1969 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1970 dev->name);
cd28ab6a
SH		 1971
1972 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1973 }
1974
1975 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 1976 if (net_ratelimit())
1977 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 1978 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1979 }
1980
1981 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 1982 if (net_ratelimit())
1983 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 1984 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1985 }
1986
1987 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 1988 if (net_ratelimit())
1989 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
1990 dev->name);
cd28ab6a
SH		 1991 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1992 }
1993}
1994
1995static void sky2_hw_intr(struct sky2_hw *hw)
1996{
1997 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1998
793b883e 1999 if (status & Y2_IS_TIST_OV)
cd28ab6a 2000 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2001
2002 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2003 u16 pci_err;
2004
56a645cc 2005 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2006 if (net_ratelimit())
2007 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2008 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2009
2010 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2011 sky2_pci_write16(hw, PCI_STATUS,
793b883e 2012 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2013 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2014 }
2015
2016 if (status & Y2_IS_PCI_EXP) {
d571b694 2017 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2018 u32 pex_err;
2019
56a645cc 2020 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2021
3be92a70
SH		 2022 if (net_ratelimit())
2023 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2024 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2025
2026 /* clear the interrupt */
2027 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2028 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
793b883e 2029 0xffffffffUL);
cd28ab6a
SH		 2030 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2031
2032 if (pex_err & PEX_FATAL_ERRORS) {
2033 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2034 hwmsk &= ~Y2_IS_PCI_EXP;
2035 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2036 }
2037 }
2038
2039 if (status & Y2_HWE_L1_MASK)
2040 sky2_hw_error(hw, 0, status);
2041 status >>= 8;
2042 if (status & Y2_HWE_L1_MASK)
2043 sky2_hw_error(hw, 1, status);
2044}
2045
2046static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2047{
2048 struct net_device *dev = hw->dev[port];
2049 struct sky2_port *sky2 = netdev_priv(dev);
2050 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2051
2052 if (netif_msg_intr(sky2))
2053 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2054 dev->name, status);
2055
2056 if (status & GM_IS_RX_FF_OR) {
2057 ++sky2->net_stats.rx_fifo_errors;
2058 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2059 }
2060
2061 if (status & GM_IS_TX_FF_UR) {
2062 ++sky2->net_stats.tx_fifo_errors;
2063 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2064 }
cd28ab6a
SH		 2065}
2066
d257924e
SH		 2067/* This should never happen it is a fatal situation */
2068static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2069 const char *rxtx, u32 mask)
2070{
2071 struct net_device *dev = hw->dev[port];
2072 struct sky2_port *sky2 = netdev_priv(dev);
2073 u32 imask;
2074
2075 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2076 dev ? dev->name : "<not registered>", rxtx);
2077
2078 imask = sky2_read32(hw, B0_IMSK);
2079 imask &= ~mask;
2080 sky2_write32(hw, B0_IMSK, imask);
2081
2082 if (dev) {
2083 spin_lock(&sky2->phy_lock);
2084 sky2_link_down(sky2);
2085 spin_unlock(&sky2->phy_lock);
2086 }
2087}
cd28ab6a 2088
e07b1aa8 2089static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2090{
e07b1aa8
SH		 2091 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2092 int work_limit = min(dev0->quota, *budget);
2093 int work_done = 0;
fb2690a9 2094 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2095
d257924e
SH		 2096 if (unlikely(status & ~Y2_IS_STAT_BMU)) {
2097 if (status & Y2_IS_HW_ERR)
2098 sky2_hw_intr(hw);
2099
2100 if (status & Y2_IS_IRQ_PHY1)
2101 sky2_phy_intr(hw, 0);
cd28ab6a 2102
d257924e
SH		 2103 if (status & Y2_IS_IRQ_PHY2)
2104 sky2_phy_intr(hw, 1);
cd28ab6a 2105
d257924e
SH		 2106 if (status & Y2_IS_IRQ_MAC1)
2107 sky2_mac_intr(hw, 0);
cd28ab6a 2108
d257924e
SH		 2109 if (status & Y2_IS_IRQ_MAC2)
2110 sky2_mac_intr(hw, 1);
cd28ab6a 2111
d257924e
SH		 2112 if (status & Y2_IS_CHK_RX1)
2113 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2114
2115 if (status & Y2_IS_CHK_RX2)
2116 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2117
2118 if (status & Y2_IS_CHK_TXA1)
2119 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2120
2121 if (status & Y2_IS_CHK_TXA2)
2122 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2123 }
cd28ab6a 2124
e07b1aa8
SH		 2125 if (status & Y2_IS_STAT_BMU) {
2126 work_done = sky2_status_intr(hw, work_limit);
2127 *budget -= work_done;
2128 dev0->quota -= work_done;
2129
2130 if (work_done >= work_limit)
2131 return 1;
2132
2133 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2134 }
2135
2136 netif_rx_complete(dev0);
2137
fb2690a9 2138 status = sky2_read32(hw, B0_Y2_SP_LISR);
e07b1aa8
SH		 2139 return 0;
2140}
2141
2142static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2143{
2144 struct sky2_hw *hw = dev_id;
2145 struct net_device *dev0 = hw->dev[0];
2146 u32 status;
2147
2148 /* Reading this mask interrupts as side effect */
2149 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2150 if (status == 0 || status == ~0)
2151 return IRQ_NONE;
793b883e 2152
e07b1aa8
SH		 2153 prefetch(&hw->st_le[hw->st_idx]);
2154 if (likely(__netif_rx_schedule_prep(dev0)))
2155 __netif_rx_schedule(dev0);
8f24664d
SH		 2156 else
2157 printk(KERN_DEBUG PFX "irq race detected\n");
793b883e 2158
cd28ab6a
SH		 2159 return IRQ_HANDLED;
2160}
2161
2162#ifdef CONFIG_NET_POLL_CONTROLLER
2163static void sky2_netpoll(struct net_device *dev)
2164{
2165 struct sky2_port *sky2 = netdev_priv(dev);
2166
793b883e 2167 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 2168}
2169#endif
2170
2171/* Chip internal frequency for clock calculations */
fb17358f 2172static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2173{
793b883e 2174 switch (hw->chip_id) {
cd28ab6a 2175 case CHIP_ID_YUKON_EC:
5a5b1ea0 2176 case CHIP_ID_YUKON_EC_U:
fb17358f 2177 return 125; /* 125 Mhz */
cd28ab6a 2178 case CHIP_ID_YUKON_FE:
fb17358f 2179 return 100; /* 100 Mhz */
793b883e 2180 default: /* YUKON_XL */
fb17358f 2181 return 156; /* 156 Mhz */
cd28ab6a
SH		 2182 }
2183}
2184
fb17358f 2185static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2186{
fb17358f 2187 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2188}
2189
fb17358f 2190static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2191{
fb17358f 2192 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2193}
2194
fb17358f 2195
cd28ab6a
SH		 2196static int sky2_reset(struct sky2_hw *hw)
2197{
cd28ab6a
SH		 2198 u16 status;
2199 u8 t8, pmd_type;
56a645cc 2200 int i;
cd28ab6a 2201
cd28ab6a 2202 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2203
cd28ab6a
SH		 2204 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2205 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2206 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2207 pci_name(hw->pdev), hw->chip_id);
2208 return -EOPNOTSUPP;
2209 }
2210
290d4de5
SH		 2211 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2212
2213 /* This rev is really old, and requires untested workarounds */
2214 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2215 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2216 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2217 hw->chip_id, hw->chip_rev);
2218 return -EOPNOTSUPP;
2219 }
2220
2221 /* This chip is new and not tested yet */
2222 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
2223 pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n",
2224 pci_name(hw->pdev));
2225 pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n");
2226 }
2227
cd28ab6a
SH		 2228 /* disable ASF */
2229 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2230 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2231 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2232 }
2233
2234 /* do a SW reset */
2235 sky2_write8(hw, B0_CTST, CS_RST_SET);
2236 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2237
2238 /* clear PCI errors, if any */
56a645cc 2239 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2240
cd28ab6a 2241 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2242 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2243
cd28ab6a
SH		 2244
2245 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2246
2247 /* clear any PEX errors */
d89e1343 2248 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
56a645cc
SH		 2249 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2250
cd28ab6a
SH		 2251
2252 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2253 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2254
2255 hw->ports = 1;
2256 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2257 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2258 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2259 ++hw->ports;
2260 }
cd28ab6a 2261
5afa0a9c 2262 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2263
2264 for (i = 0; i < hw->ports; i++) {
2265 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2266 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2267 }
2268
2269 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2270
793b883e
SH		 2271 /* Clear I2C IRQ noise */
2272 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2273
2274 /* turn off hardware timer (unused) */
2275 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2276 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2277
cd28ab6a
SH		 2278 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2279
69634ee7
SH		 2280 /* Turn off descriptor polling */
2281 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2282
2283 /* Turn off receive timestamp */
2284 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2285 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2286
2287 /* enable the Tx Arbiters */
2288 for (i = 0; i < hw->ports; i++)
2289 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2290
2291 /* Initialize ram interface */
2292 for (i = 0; i < hw->ports; i++) {
793b883e 2293 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2294
2295 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2296 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2297 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2298 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2299 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2300 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2301 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2302 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2303 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2304 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2305 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2306 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2307 }
2308
cd28ab6a
SH		 2309 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2310
cd28ab6a
SH		 2311 for (i = 0; i < hw->ports; i++)
2312 sky2_phy_reset(hw, i);
cd28ab6a 2313
cd28ab6a
SH		 2314 memset(hw->st_le, 0, STATUS_LE_BYTES);
2315 hw->st_idx = 0;
2316
2317 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2318 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2319
2320 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2321 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2322
2323 /* Set the list last index */
793b883e 2324 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2325
290d4de5
SH		 2326 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2327 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2328
290d4de5
SH		 2329 /* set Status-FIFO ISR watermark */
2330 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2331 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2332 else
2333 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2334
290d4de5 2335 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2336 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2337 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2338
793b883e 2339 /* enable status unit */
cd28ab6a
SH		 2340 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2341
2342 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2343 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2344 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2345
2346 return 0;
2347}
2348
28bd181a 2349static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a
SH		 2350{
2351 u32 modes;
2352 if (hw->copper) {
793b883e
SH		 2353 modes = SUPPORTED_10baseT_Half
2354 | SUPPORTED_10baseT_Full
2355 | SUPPORTED_100baseT_Half
2356 | SUPPORTED_100baseT_Full
2357 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2358
2359 if (hw->chip_id != CHIP_ID_YUKON_FE)
2360 modes |= SUPPORTED_1000baseT_Half
793b883e 2361 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2362 } else
2363 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2364 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2365 return modes;
2366}
2367
793b883e 2368static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2369{
2370 struct sky2_port *sky2 = netdev_priv(dev);
2371 struct sky2_hw *hw = sky2->hw;
2372
2373 ecmd->transceiver = XCVR_INTERNAL;
2374 ecmd->supported = sky2_supported_modes(hw);
2375 ecmd->phy_address = PHY_ADDR_MARV;
2376 if (hw->copper) {
2377 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2378 | SUPPORTED_10baseT_Full
2379 | SUPPORTED_100baseT_Half
2380 | SUPPORTED_100baseT_Full
2381 | SUPPORTED_1000baseT_Half
2382 | SUPPORTED_1000baseT_Full
2383 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2384 ecmd->port = PORT_TP;
2385 } else
2386 ecmd->port = PORT_FIBRE;
2387
2388 ecmd->advertising = sky2->advertising;
2389 ecmd->autoneg = sky2->autoneg;
2390 ecmd->speed = sky2->speed;
2391 ecmd->duplex = sky2->duplex;
2392 return 0;
2393}
2394
2395static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2396{
2397 struct sky2_port *sky2 = netdev_priv(dev);
2398 const struct sky2_hw *hw = sky2->hw;
2399 u32 supported = sky2_supported_modes(hw);
2400
2401 if (ecmd->autoneg == AUTONEG_ENABLE) {
2402 ecmd->advertising = supported;
2403 sky2->duplex = -1;
2404 sky2->speed = -1;
2405 } else {
2406 u32 setting;
2407
793b883e 2408 switch (ecmd->speed) {
cd28ab6a
SH		 2409 case SPEED_1000:
2410 if (ecmd->duplex == DUPLEX_FULL)
2411 setting = SUPPORTED_1000baseT_Full;
2412 else if (ecmd->duplex == DUPLEX_HALF)
2413 setting = SUPPORTED_1000baseT_Half;
2414 else
2415 return -EINVAL;
2416 break;
2417 case SPEED_100:
2418 if (ecmd->duplex == DUPLEX_FULL)
2419 setting = SUPPORTED_100baseT_Full;
2420 else if (ecmd->duplex == DUPLEX_HALF)
2421 setting = SUPPORTED_100baseT_Half;
2422 else
2423 return -EINVAL;
2424 break;
2425
2426 case SPEED_10:
2427 if (ecmd->duplex == DUPLEX_FULL)
2428 setting = SUPPORTED_10baseT_Full;
2429 else if (ecmd->duplex == DUPLEX_HALF)
2430 setting = SUPPORTED_10baseT_Half;
2431 else
2432 return -EINVAL;
2433 break;
2434 default:
2435 return -EINVAL;
2436 }
2437
2438 if ((setting & supported) == 0)
2439 return -EINVAL;
2440
2441 sky2->speed = ecmd->speed;
2442 sky2->duplex = ecmd->duplex;
2443 }
2444
2445 sky2->autoneg = ecmd->autoneg;
2446 sky2->advertising = ecmd->advertising;
2447
1b537565
SH		 2448 if (netif_running(dev))
2449 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2450
2451 return 0;
2452}
2453
2454static void sky2_get_drvinfo(struct net_device *dev,
2455 struct ethtool_drvinfo *info)
2456{
2457 struct sky2_port *sky2 = netdev_priv(dev);
2458
2459 strcpy(info->driver, DRV_NAME);
2460 strcpy(info->version, DRV_VERSION);
2461 strcpy(info->fw_version, "N/A");
2462 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2463}
2464
2465static const struct sky2_stat {
793b883e
SH		 2466 char name[ETH_GSTRING_LEN];
2467 u16 offset;
cd28ab6a
SH		 2468} sky2_stats[] = {
2469 { "tx_bytes", GM_TXO_OK_HI },
2470 { "rx_bytes", GM_RXO_OK_HI },
2471 { "tx_broadcast", GM_TXF_BC_OK },
2472 { "rx_broadcast", GM_RXF_BC_OK },
2473 { "tx_multicast", GM_TXF_MC_OK },
2474 { "rx_multicast", GM_RXF_MC_OK },
2475 { "tx_unicast", GM_TXF_UC_OK },
2476 { "rx_unicast", GM_RXF_UC_OK },
2477 { "tx_mac_pause", GM_TXF_MPAUSE },
2478 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2479 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2480 { "late_collision",GM_TXF_LAT_COL },
2481 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2482 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2483 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2484
d2604540 2485 { "rx_short", GM_RXF_SHT },
cd28ab6a 2486 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2487 { "rx_64_byte_packets", GM_RXF_64B },
2488 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2489 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2490 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2491 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2492 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2493 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2494 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2495 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2496 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2497 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2498
2499 { "tx_64_byte_packets", GM_TXF_64B },
2500 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2501 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2502 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2503 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2504 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2505 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2506 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2507};
2508
cd28ab6a
SH		 2509static u32 sky2_get_rx_csum(struct net_device *dev)
2510{
2511 struct sky2_port *sky2 = netdev_priv(dev);
2512
2513 return sky2->rx_csum;
2514}
2515
2516static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2517{
2518 struct sky2_port *sky2 = netdev_priv(dev);
2519
2520 sky2->rx_csum = data;
793b883e 2521
cd28ab6a
SH		 2522 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2523 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2524
2525 return 0;
2526}
2527
2528static u32 sky2_get_msglevel(struct net_device *netdev)
2529{
2530 struct sky2_port *sky2 = netdev_priv(netdev);
2531 return sky2->msg_enable;
2532}
2533
9a7ae0a9
SH		 2534static int sky2_nway_reset(struct net_device *dev)
2535{
2536 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2537
2538 if (sky2->autoneg != AUTONEG_ENABLE)
2539 return -EINVAL;
2540
1b537565 2541 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2542
2543 return 0;
2544}
2545
793b883e 2546static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2547{
2548 struct sky2_hw *hw = sky2->hw;
2549 unsigned port = sky2->port;
2550 int i;
2551
2552 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2553 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2554 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2555 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2556
793b883e 2557 for (i = 2; i < count; i++)
cd28ab6a
SH		 2558 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2559}
2560
cd28ab6a
SH		 2561static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2562{
2563 struct sky2_port *sky2 = netdev_priv(netdev);
2564 sky2->msg_enable = value;
2565}
2566
2567static int sky2_get_stats_count(struct net_device *dev)
2568{
2569 return ARRAY_SIZE(sky2_stats);
2570}
2571
2572static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2573 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2574{
2575 struct sky2_port *sky2 = netdev_priv(dev);
2576
793b883e 2577 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2578}
2579
793b883e 2580static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2581{
2582 int i;
2583
2584 switch (stringset) {
2585 case ETH_SS_STATS:
2586 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2587 memcpy(data + i * ETH_GSTRING_LEN,
2588 sky2_stats[i].name, ETH_GSTRING_LEN);
2589 break;
2590 }
2591}
2592
2593/* Use hardware MIB variables for critical path statistics and
2594 * transmit feedback not reported at interrupt.
2595 * Other errors are accounted for in interrupt handler.
2596 */
2597static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2598{
2599 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2600 u64 data[13];
cd28ab6a 2601
793b883e 2602 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2603
2604 sky2->net_stats.tx_bytes = data[0];
2605 sky2->net_stats.rx_bytes = data[1];
2606 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2607 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2608 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2609 sky2->net_stats.collisions = data[10];
2610 sky2->net_stats.tx_aborted_errors = data[12];
2611
2612 return &sky2->net_stats;
2613}
2614
2615static int sky2_set_mac_address(struct net_device *dev, void *p)
2616{
2617 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2618 struct sky2_hw *hw = sky2->hw;
2619 unsigned port = sky2->port;
2620 const struct sockaddr *addr = p;
cd28ab6a
SH		 2621
2622 if (!is_valid_ether_addr(addr->sa_data))
2623 return -EADDRNOTAVAIL;
2624
cd28ab6a 2625 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2626 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2627 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2628 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2629 dev->dev_addr, ETH_ALEN);
1b537565 2630
a8ab1ec0
SH		 2631 /* virtual address for data */
2632 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2633
2634 /* physical address: used for pause frames */
2635 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2636
2637 return 0;
cd28ab6a
SH		 2638}
2639
2640static void sky2_set_multicast(struct net_device *dev)
2641{
2642 struct sky2_port *sky2 = netdev_priv(dev);
2643 struct sky2_hw *hw = sky2->hw;
2644 unsigned port = sky2->port;
2645 struct dev_mc_list *list = dev->mc_list;
2646 u16 reg;
2647 u8 filter[8];
2648
2649 memset(filter, 0, sizeof(filter));
2650
2651 reg = gma_read16(hw, port, GM_RX_CTRL);
2652 reg |= GM_RXCR_UCF_ENA;
2653
d571b694 2654 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2655 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2656 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2657 memset(filter, 0xff, sizeof(filter));
793b883e 2658 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2659 reg &= ~GM_RXCR_MCF_ENA;
2660 else {
2661 int i;
2662 reg |= GM_RXCR_MCF_ENA;
2663
2664 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2665 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2666 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2667 }
2668 }
2669
cd28ab6a 2670 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2671 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2672 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2673 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2674 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2675 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2676 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2677 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2678
2679 gma_write16(hw, port, GM_RX_CTRL, reg);
2680}
2681
2682/* Can have one global because blinking is controlled by
2683 * ethtool and that is always under RTNL mutex
2684 */
91c86df5 2685static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2686{
793b883e
SH		 2687 u16 pg;
2688
793b883e
SH		 2689 switch (hw->chip_id) {
2690 case CHIP_ID_YUKON_XL:
2691 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2692 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2693 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2694 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2695 PHY_M_LEDC_INIT_CTRL(7) |
2696 PHY_M_LEDC_STA1_CTRL(7) |
2697 PHY_M_LEDC_STA0_CTRL(7))
2698 : 0);
2699
2700 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2701 break;
2702
2703 default:
2704 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2705 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2706 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2707 PHY_M_LED_MO_10(MO_LED_ON) |
2708 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2709 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2710 PHY_M_LED_MO_RX(MO_LED_ON)
2711 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2712 PHY_M_LED_MO_10(MO_LED_OFF) |
2713 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2714 PHY_M_LED_MO_1000(MO_LED_OFF) |
2715 PHY_M_LED_MO_RX(MO_LED_OFF));
2716
793b883e 2717 }
cd28ab6a
SH		 2718}
2719
2720/* blink LED's for finding board */
2721static int sky2_phys_id(struct net_device *dev, u32 data)
2722{
2723 struct sky2_port *sky2 = netdev_priv(dev);
2724 struct sky2_hw *hw = sky2->hw;
2725 unsigned port = sky2->port;
793b883e 2726 u16 ledctrl, ledover = 0;
cd28ab6a 2727 long ms;
91c86df5 2728 int interrupted;
cd28ab6a
SH		 2729 int onoff = 1;
2730
793b883e 2731 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2732 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2733 else
2734 ms = data * 1000;
2735
2736 /* save initial values */
e07b1aa8 2737 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2738 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2739 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2740 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2741 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2742 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2743 } else {
2744 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2745 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2746 }
cd28ab6a 2747
91c86df5
SH		 2748 interrupted = 0;
2749 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2750 sky2_led(hw, port, onoff);
2751 onoff = !onoff;
2752
e07b1aa8 2753 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2754 interrupted = msleep_interruptible(250);
e07b1aa8 2755 spin_lock_bh(&sky2->phy_lock);
91c86df5 2756
cd28ab6a
SH		 2757 ms -= 250;
2758 }
2759
2760 /* resume regularly scheduled programming */
793b883e
SH		 2761 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2762 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2763 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2764 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2765 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2766 } else {
2767 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2768 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2769 }
e07b1aa8 2770 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2771
2772 return 0;
2773}
2774
2775static void sky2_get_pauseparam(struct net_device *dev,
2776 struct ethtool_pauseparam *ecmd)
2777{
2778 struct sky2_port *sky2 = netdev_priv(dev);
2779
2780 ecmd->tx_pause = sky2->tx_pause;
2781 ecmd->rx_pause = sky2->rx_pause;
2782 ecmd->autoneg = sky2->autoneg;
2783}
2784
2785static int sky2_set_pauseparam(struct net_device *dev,
2786 struct ethtool_pauseparam *ecmd)
2787{
2788 struct sky2_port *sky2 = netdev_priv(dev);
2789 int err = 0;
2790
2791 sky2->autoneg = ecmd->autoneg;
2792 sky2->tx_pause = ecmd->tx_pause != 0;
2793 sky2->rx_pause = ecmd->rx_pause != 0;
2794
1b537565 2795 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2796
2797 return err;
2798}
2799
fb17358f
SH		 2800static int sky2_get_coalesce(struct net_device *dev,
2801 struct ethtool_coalesce *ecmd)
2802{
2803 struct sky2_port *sky2 = netdev_priv(dev);
2804 struct sky2_hw *hw = sky2->hw;
2805
2806 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2807 ecmd->tx_coalesce_usecs = 0;
2808 else {
2809 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2810 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2811 }
2812 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2813
2814 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2815 ecmd->rx_coalesce_usecs = 0;
2816 else {
2817 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2818 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2819 }
2820 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2821
2822 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2823 ecmd->rx_coalesce_usecs_irq = 0;
2824 else {
2825 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2826 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2827 }
2828
2829 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2830
2831 return 0;
2832}
2833
2834/* Note: this affect both ports */
2835static int sky2_set_coalesce(struct net_device *dev,
2836 struct ethtool_coalesce *ecmd)
2837{
2838 struct sky2_port *sky2 = netdev_priv(dev);
2839 struct sky2_hw *hw = sky2->hw;
77b3d6a2 2840 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 2841
77b3d6a2
SH		 2842 if (ecmd->tx_coalesce_usecs > tmax ||
2843 ecmd->rx_coalesce_usecs > tmax ||
2844 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 2845 return -EINVAL;
2846
ff81fbbe 2847 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 2848 return -EINVAL;
ff81fbbe 2849 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 2850 return -EINVAL;
ff81fbbe 2851 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 2852 return -EINVAL;
2853
2854 if (ecmd->tx_coalesce_usecs == 0)
2855 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2856 else {
2857 sky2_write32(hw, STAT_TX_TIMER_INI,
2858 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2859 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2860 }
2861 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2862
2863 if (ecmd->rx_coalesce_usecs == 0)
2864 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2865 else {
2866 sky2_write32(hw, STAT_LEV_TIMER_INI,
2867 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2868 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2869 }
2870 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2871
2872 if (ecmd->rx_coalesce_usecs_irq == 0)
2873 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2874 else {
d28d4870 2875 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 2876 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2877 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2878 }
2879 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2880 return 0;
2881}
2882
793b883e
SH		 2883static void sky2_get_ringparam(struct net_device *dev,
2884 struct ethtool_ringparam *ering)
2885{
2886 struct sky2_port *sky2 = netdev_priv(dev);
2887
2888 ering->rx_max_pending = RX_MAX_PENDING;
2889 ering->rx_mini_max_pending = 0;
2890 ering->rx_jumbo_max_pending = 0;
2891 ering->tx_max_pending = TX_RING_SIZE - 1;
2892
2893 ering->rx_pending = sky2->rx_pending;
2894 ering->rx_mini_pending = 0;
2895 ering->rx_jumbo_pending = 0;
2896 ering->tx_pending = sky2->tx_pending;
2897}
2898
2899static int sky2_set_ringparam(struct net_device *dev,
2900 struct ethtool_ringparam *ering)
2901{
2902 struct sky2_port *sky2 = netdev_priv(dev);
2903 int err = 0;
2904
2905 if (ering->rx_pending > RX_MAX_PENDING ||
2906 ering->rx_pending < 8 ||
2907 ering->tx_pending < MAX_SKB_TX_LE ||
2908 ering->tx_pending > TX_RING_SIZE - 1)
2909 return -EINVAL;
2910
2911 if (netif_running(dev))
2912 sky2_down(dev);
2913
2914 sky2->rx_pending = ering->rx_pending;
2915 sky2->tx_pending = ering->tx_pending;
2916
1b537565 2917 if (netif_running(dev)) {
793b883e 2918 err = sky2_up(dev);
1b537565
SH		 2919 if (err)
2920 dev_close(dev);
6ed995bb
SH		 2921 else
2922 sky2_set_multicast(dev);
1b537565 2923 }
793b883e
SH		 2924
2925 return err;
2926}
2927
793b883e
SH		 2928static int sky2_get_regs_len(struct net_device *dev)
2929{
6e4cbb34 2930 return 0x4000;
793b883e
SH		 2931}
2932
2933/*
2934 * Returns copy of control register region
6e4cbb34 2935 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 2936 */
2937static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2938 void *p)
2939{
2940 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2941 const void __iomem *io = sky2->hw->regs;
793b883e 2942
6e4cbb34 2943 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 2944 regs->version = 1;
6e4cbb34 2945 memset(p, 0, regs->len);
793b883e 2946
6e4cbb34
SH		 2947 memcpy_fromio(p, io, B3_RAM_ADDR);
2948
2949 memcpy_fromio(p + B3_RI_WTO_R1,
2950 io + B3_RI_WTO_R1,
2951 regs->len - B3_RI_WTO_R1);
793b883e 2952}
cd28ab6a
SH		 2953
2954static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 2955 .get_settings = sky2_get_settings,
2956 .set_settings = sky2_set_settings,
2957 .get_drvinfo = sky2_get_drvinfo,
2958 .get_msglevel = sky2_get_msglevel,
2959 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 2960 .nway_reset = sky2_nway_reset,
793b883e
SH		 2961 .get_regs_len = sky2_get_regs_len,
2962 .get_regs = sky2_get_regs,
2963 .get_link = ethtool_op_get_link,
2964 .get_sg = ethtool_op_get_sg,
2965 .set_sg = ethtool_op_set_sg,
2966 .get_tx_csum = ethtool_op_get_tx_csum,
2967 .set_tx_csum = ethtool_op_set_tx_csum,
2968 .get_tso = ethtool_op_get_tso,
2969 .set_tso = ethtool_op_set_tso,
2970 .get_rx_csum = sky2_get_rx_csum,
2971 .set_rx_csum = sky2_set_rx_csum,
2972 .get_strings = sky2_get_strings,
fb17358f
SH		 2973 .get_coalesce = sky2_get_coalesce,
2974 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 2975 .get_ringparam = sky2_get_ringparam,
2976 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 2977 .get_pauseparam = sky2_get_pauseparam,
2978 .set_pauseparam = sky2_set_pauseparam,
793b883e 2979 .phys_id = sky2_phys_id,
cd28ab6a
SH		 2980 .get_stats_count = sky2_get_stats_count,
2981 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 2982 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 2983};
2984
2985/* Initialize network device */
2986static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2987 unsigned port, int highmem)
2988{
2989 struct sky2_port *sky2;
2990 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2991
2992 if (!dev) {
2993 printk(KERN_ERR "sky2 etherdev alloc failed");
2994 return NULL;
2995 }
2996
2997 SET_MODULE_OWNER(dev);
2998 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 2999 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3000 dev->open = sky2_up;
3001 dev->stop = sky2_down;
ef743d33 3002 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3003 dev->hard_start_xmit = sky2_xmit_frame;
3004 dev->get_stats = sky2_get_stats;
3005 dev->set_multicast_list = sky2_set_multicast;
3006 dev->set_mac_address = sky2_set_mac_address;
3007 dev->change_mtu = sky2_change_mtu;
3008 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3009 dev->tx_timeout = sky2_tx_timeout;
3010 dev->watchdog_timeo = TX_WATCHDOG;
3011 if (port == 0)
3012 dev->poll = sky2_poll;
3013 dev->weight = NAPI_WEIGHT;
3014#ifdef CONFIG_NET_POLL_CONTROLLER
3015 dev->poll_controller = sky2_netpoll;
3016#endif
cd28ab6a
SH		 3017
3018 sky2 = netdev_priv(dev);
3019 sky2->netdev = dev;
3020 sky2->hw = hw;
3021 sky2->msg_enable = netif_msg_init(debug, default_msg);
3022
3023 spin_lock_init(&sky2->tx_lock);
3024 /* Auto speed and flow control */
3025 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3026 sky2->tx_pause = 1;
cd28ab6a
SH		 3027 sky2->rx_pause = 1;
3028 sky2->duplex = -1;
3029 sky2->speed = -1;
3030 sky2->advertising = sky2_supported_modes(hw);
75d070c5 3031
d89e1343 3032 /* Receive checksum disabled for Yukon XL
75d070c5
SH		 3033 * because of observed problems with incorrect
3034 * values when multiple packets are received in one interrupt
3035 */
3036 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3037
e07b1aa8 3038 spin_lock_init(&sky2->phy_lock);
793b883e 3039 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3040 sky2->rx_pending = RX_DEF_PENDING;
734d1868 3041 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 3042
3043 hw->dev[port] = dev;
3044
3045 sky2->port = port;
3046
5a5b1ea0
SH		 3047 dev->features |= NETIF_F_LLTX;
3048 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3049 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3050 if (highmem)
3051 dev->features |= NETIF_F_HIGHDMA;
793b883e 3052 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3053
d1f13708
SH		 3054#ifdef SKY2_VLAN_TAG_USED
3055 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3056 dev->vlan_rx_register = sky2_vlan_rx_register;
3057 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3058#endif
3059
cd28ab6a 3060 /* read the mac address */
793b883e 3061 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3062 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3063
3064 /* device is off until link detection */
3065 netif_carrier_off(dev);
3066 netif_stop_queue(dev);
3067
3068 return dev;
3069}
3070
28bd181a 3071static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3072{
3073 const struct sky2_port *sky2 = netdev_priv(dev);
3074
3075 if (netif_msg_probe(sky2))
3076 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3077 dev->name,
3078 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3079 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3080}
3081
fb2690a9
SH		 3082/* Handle software interrupt used during MSI test */
3083static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3084 struct pt_regs *regs)
3085{
3086 struct sky2_hw *hw = dev_id;
3087 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3088
3089 if (status == 0)
3090 return IRQ_NONE;
3091
3092 if (status & Y2_IS_IRQ_SW) {
3093 hw->msi_detected = 1;
3094 wake_up(&hw->msi_wait);
3095 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3096 }
3097 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3098
3099 return IRQ_HANDLED;
3100}
3101
3102/* Test interrupt path by forcing a a software IRQ */
3103static int __devinit sky2_test_msi(struct sky2_hw *hw)
3104{
3105 struct pci_dev *pdev = hw->pdev;
3106 int err;
3107
3108 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3109
3110 err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
3111 if (err) {
3112 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3113 pci_name(pdev), pdev->irq);
3114 return err;
3115 }
3116
3117 init_waitqueue_head (&hw->msi_wait);
3118
3119 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3120 wmb();
3121
3122 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3123
3124 if (!hw->msi_detected) {
3125 /* MSI test failed, go back to INTx mode */
3126 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3127 "switching to INTx mode. Please report this failure to "
3128 "the PCI maintainer and include system chipset information.\n",
3129 pci_name(pdev));
3130
3131 err = -EOPNOTSUPP;
3132 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3133 }
3134
3135 sky2_write32(hw, B0_IMSK, 0);
3136
3137 free_irq(pdev->irq, hw);
3138
3139 return err;
3140}
3141
cd28ab6a
SH		 3142static int __devinit sky2_probe(struct pci_dev *pdev,
3143 const struct pci_device_id *ent)
3144{
793b883e 3145 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3146 struct sky2_hw *hw;
5afa0a9c 3147 int err, pm_cap, using_dac = 0;
cd28ab6a 3148
793b883e
SH		 3149 err = pci_enable_device(pdev);
3150 if (err) {
cd28ab6a
SH		 3151 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3152 pci_name(pdev));
3153 goto err_out;
3154 }
3155
793b883e
SH		 3156 err = pci_request_regions(pdev, DRV_NAME);
3157 if (err) {
cd28ab6a
SH		 3158 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3159 pci_name(pdev));
793b883e 3160 goto err_out;
cd28ab6a
SH		 3161 }
3162
3163 pci_set_master(pdev);
3164
5afa0a9c
SH		 3165 /* Find power-management capability. */
3166 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3167 if (pm_cap == 0) {
3168 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3169 "aborting.\n");
3170 err = -EIO;
3171 goto err_out_free_regions;
3172 }
3173
d1f3d4dd
SH		 3174 if (sizeof(dma_addr_t) > sizeof(u32) &&
3175 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3176 using_dac = 1;
3177 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3178 if (err < 0) {
3179 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3180 "for consistent allocations\n", pci_name(pdev));
3181 goto err_out_free_regions;
3182 }
cd28ab6a 3183
d1f3d4dd 3184 } else {
cd28ab6a
SH		 3185 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3186 if (err) {
3187 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3188 pci_name(pdev));
3189 goto err_out_free_regions;
3190 }
3191 }
d1f3d4dd 3192
cd28ab6a 3193 err = -ENOMEM;
6aad85d6 3194 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3195 if (!hw) {
3196 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3197 pci_name(pdev));
3198 goto err_out_free_regions;
3199 }
3200
cd28ab6a 3201 hw->pdev = pdev;
cd28ab6a
SH		 3202
3203 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3204 if (!hw->regs) {
3205 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3206 pci_name(pdev));
3207 goto err_out_free_hw;
3208 }
5afa0a9c 3209 hw->pm_cap = pm_cap;
cd28ab6a 3210
56a645cc
SH		 3211#ifdef __BIG_ENDIAN
3212 /* byte swap descriptors in hardware */
3213 {
3214 u32 reg;
3215
3216 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3217 reg |= PCI_REV_DESC;
3218 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3219 }
3220#endif
3221
08c06d8a
SH		 3222 /* ring for status responses */
3223 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3224 &hw->st_dma);
3225 if (!hw->st_le)
3226 goto err_out_iounmap;
3227
cd28ab6a
SH		 3228 err = sky2_reset(hw);
3229 if (err)
793b883e 3230 goto err_out_iounmap;
cd28ab6a 3231
5f4f9dc1
SH		 3232 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3233 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
92f965e8 3234 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3235 hw->chip_id, hw->chip_rev);
cd28ab6a 3236
793b883e
SH		 3237 dev = sky2_init_netdev(hw, 0, using_dac);
3238 if (!dev)
cd28ab6a
SH		 3239 goto err_out_free_pci;
3240
793b883e
SH		 3241 err = register_netdev(dev);
3242 if (err) {
cd28ab6a
SH		 3243 printk(KERN_ERR PFX "%s: cannot register net device\n",
3244 pci_name(pdev));
3245 goto err_out_free_netdev;
3246 }
3247
3248 sky2_show_addr(dev);
3249
3250 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3251 if (register_netdev(dev1) == 0)
3252 sky2_show_addr(dev1);
3253 else {
3254 /* Failure to register second port need not be fatal */
793b883e
SH		 3255 printk(KERN_WARNING PFX
3256 "register of second port failed\n");
cd28ab6a
SH		 3257 hw->dev[1] = NULL;
3258 free_netdev(dev1);
3259 }
3260 }
3261
fb2690a9
SH		 3262 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3263 err = sky2_test_msi(hw);
3264 if (err == -EOPNOTSUPP)
3265 pci_disable_msi(pdev);
3266 else if (err)
3267 goto err_out_unregister;
3268 }
3269
3270 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
793b883e
SH		 3271 if (err) {
3272 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3273 pci_name(pdev), pdev->irq);
3274 goto err_out_unregister;
3275 }
3276
e07b1aa8 3277 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
793b883e
SH		 3278
3279 pci_set_drvdata(pdev, hw);
3280
cd28ab6a
SH		 3281 return 0;
3282
793b883e 3283err_out_unregister:
fb2690a9 3284 pci_disable_msi(pdev);
793b883e
SH		 3285 if (dev1) {
3286 unregister_netdev(dev1);
3287 free_netdev(dev1);
3288 }
3289 unregister_netdev(dev);
cd28ab6a
SH		 3290err_out_free_netdev:
3291 free_netdev(dev);
cd28ab6a 3292err_out_free_pci:
793b883e 3293 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3294 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3295err_out_iounmap:
3296 iounmap(hw->regs);
3297err_out_free_hw:
3298 kfree(hw);
3299err_out_free_regions:
3300 pci_release_regions(pdev);
cd28ab6a 3301 pci_disable_device(pdev);
cd28ab6a
SH		 3302err_out:
3303 return err;
3304}
3305
3306static void __devexit sky2_remove(struct pci_dev *pdev)
3307{
793b883e 3308 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3309 struct net_device *dev0, *dev1;
3310
793b883e 3311 if (!hw)
cd28ab6a
SH		 3312 return;
3313
cd28ab6a 3314 dev0 = hw->dev[0];
793b883e
SH		 3315 dev1 = hw->dev[1];
3316 if (dev1)
3317 unregister_netdev(dev1);
cd28ab6a
SH		 3318 unregister_netdev(dev0);
3319
793b883e 3320 sky2_write32(hw, B0_IMSK, 0);
5afa0a9c 3321 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3322 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3323 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3324 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3325
3326 free_irq(pdev->irq, hw);
fb2690a9 3327 pci_disable_msi(pdev);
793b883e 3328 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3329 pci_release_regions(pdev);
3330 pci_disable_device(pdev);
793b883e 3331
cd28ab6a
SH		 3332 if (dev1)
3333 free_netdev(dev1);
3334 free_netdev(dev0);
3335 iounmap(hw->regs);
3336 kfree(hw);
5afa0a9c 3337
cd28ab6a
SH		 3338 pci_set_drvdata(pdev, NULL);
3339}
3340
3341#ifdef CONFIG_PM
3342static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3343{
793b883e 3344 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3345 int i;
cd28ab6a
SH		 3346
3347 for (i = 0; i < 2; i++) {
3348 struct net_device *dev = hw->dev[i];
3349
3350 if (dev) {
5afa0a9c
SH		 3351 if (!netif_running(dev))
3352 continue;
3353
3354 sky2_down(dev);
cd28ab6a 3355 netif_device_detach(dev);
cd28ab6a
SH		 3356 }
3357 }
3358
5afa0a9c 3359 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
cd28ab6a
SH		 3360}
3361
3362static int sky2_resume(struct pci_dev *pdev)
3363{
793b883e 3364 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3365 int i, err;
cd28ab6a 3366
cd28ab6a
SH		 3367 pci_restore_state(pdev);
3368 pci_enable_wake(pdev, PCI_D0, 0);
08c06d8a
SH		 3369 err = sky2_set_power_state(hw, PCI_D0);
3370 if (err)
3371 goto out;
cd28ab6a 3372
08c06d8a
SH		 3373 err = sky2_reset(hw);
3374 if (err)
3375 goto out;
cd28ab6a
SH		 3376
3377 for (i = 0; i < 2; i++) {
3378 struct net_device *dev = hw->dev[i];
08c06d8a
SH		 3379 if (dev && netif_running(dev)) {
3380 netif_device_attach(dev);
3381 err = sky2_up(dev);
3382 if (err) {
3383 printk(KERN_ERR PFX "%s: could not up: %d\n",
3384 dev->name, err);
3385 dev_close(dev);
3386 break;
5afa0a9c 3387 }
cd28ab6a
SH		 3388 }
3389 }
08c06d8a
SH		 3390out:
3391 return err;
cd28ab6a
SH		 3392}
3393#endif
3394
3395static struct pci_driver sky2_driver = {
793b883e
SH		 3396 .name = DRV_NAME,
3397 .id_table = sky2_id_table,
3398 .probe = sky2_probe,
3399 .remove = __devexit_p(sky2_remove),
cd28ab6a 3400#ifdef CONFIG_PM
793b883e
SH		 3401 .suspend = sky2_suspend,
3402 .resume = sky2_resume,
cd28ab6a
SH		 3403#endif
3404};
3405
3406static int __init sky2_init_module(void)
3407{
50241c4c 3408 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3409}
3410
3411static void __exit sky2_cleanup_module(void)
3412{
3413 pci_unregister_driver(&sky2_driver);
3414}
3415
3416module_init(sky2_init_module);
3417module_exit(sky2_cleanup_module);
3418
3419MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3420MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3421MODULE_LICENSE("GPL");
5f4f9dc1 3422MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)