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sky2: check drop truncated packets
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
a73b629b 54#define DRV_VERSION "1.15"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
c59697e0 102static int idle_timeout = 100;
01bd7564 103module_param(idle_timeout, int, 0);
e561a83b 104MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 105
cd28ab6a 106static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
108 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 111 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 112 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 137 { 0 }
138};
793b883e 139
cd28ab6a
SH		 140MODULE_DEVICE_TABLE(pci, sky2_id_table);
141
142/* Avoid conditionals by using array */
143static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
144static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 145static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 146
92f965e8
SH		 147/* This driver supports yukon2 chipset only */
148static const char *yukon2_name[] = {
149 "XL", /* 0xb3 */
150 "EC Ultra", /* 0xb4 */
93745494 151 "Extreme", /* 0xb5 */
92f965e8
SH		 152 "EC", /* 0xb6 */
153 "FE", /* 0xb7 */
793b883e
SH		 154};
155
793b883e 156/* Access to external PHY */
ef743d33 157static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 158{
159 int i;
160
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164
165 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 166 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 167 return 0;
793b883e 168 udelay(1);
cd28ab6a 169 }
ef743d33 170
793b883e 171 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 172 return -ETIMEDOUT;
cd28ab6a
SH		 173}
174
ef743d33 175static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 176{
177 int i;
178
793b883e 179 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 180 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
181
182 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 183 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
184 *val = gma_read16(hw, port, GM_SMI_DATA);
185 return 0;
186 }
187
793b883e 188 udelay(1);
cd28ab6a
SH		 189 }
190
ef743d33
SH		 191 return -ETIMEDOUT;
192}
193
194static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
195{
196 u16 v;
197
198 if (__gm_phy_read(hw, port, reg, &v) != 0)
199 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
200 return v;
cd28ab6a
SH		 201}
202
5afa0a9c 203
ae306cca
SH		 204static void sky2_power_on(struct sky2_hw *hw)
205{
206 /* switch power to VCC (WA for VAUX problem) */
207 sky2_write8(hw, B0_POWER_CTRL,
208 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 209
ae306cca
SH		 210 /* disable Core Clock Division, */
211 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 212
ae306cca
SH		 213 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
214 /* enable bits are inverted */
215 sky2_write8(hw, B2_Y2_CLK_GATE,
216 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
217 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
218 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
219 else
220 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 221
93745494 222 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
fc99fe06 223 u32 reg;
5afa0a9c 224
fc99fe06
SH		 225 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
226 /* set all bits to 0 except bits 15..12 and 8 */
227 reg &= P_ASPM_CONTROL_MSK;
228 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
229
230 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
231 /* set all bits to 0 except bits 28 & 27 */
232 reg &= P_CTL_TIM_VMAIN_AV_MSK;
233 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
234
235 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 236
237 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
238 reg = sky2_read32(hw, B2_GP_IO);
239 reg |= GLB_GPIO_STAT_RACE_DIS;
240 sky2_write32(hw, B2_GP_IO, reg);
5afa0a9c 241 }
ae306cca 242}
5afa0a9c 243
ae306cca
SH		 244static void sky2_power_aux(struct sky2_hw *hw)
245{
246 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
247 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
248 else
249 /* enable bits are inverted */
250 sky2_write8(hw, B2_Y2_CLK_GATE,
251 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
252 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
253 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
254
255 /* switch power to VAUX */
256 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
257 sky2_write8(hw, B0_POWER_CTRL,
258 (PC_VAUX_ENA | PC_VCC_ENA |
259 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 260}
261
d3bcfbeb 262static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 263{
264 u16 reg;
265
266 /* disable all GMAC IRQ's */
267 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
268 /* disable PHY IRQs */
269 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 270
cd28ab6a
SH		 271 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
272 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
273 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
274 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
275
276 reg = gma_read16(hw, port, GM_RX_CTRL);
277 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
278 gma_write16(hw, port, GM_RX_CTRL, reg);
279}
280
16ad91e1
SH		 281/* flow control to advertise bits */
282static const u16 copper_fc_adv[] = {
283 [FC_NONE] = 0,
284 [FC_TX] = PHY_M_AN_ASP,
285 [FC_RX] = PHY_M_AN_PC,
286 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
287};
288
289/* flow control to advertise bits when using 1000BaseX */
290static const u16 fiber_fc_adv[] = {
291 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
292 [FC_TX] = PHY_M_P_ASYM_MD_X,
293 [FC_RX] = PHY_M_P_SYM_MD_X,
294 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
295};
296
297/* flow control to GMA disable bits */
298static const u16 gm_fc_disable[] = {
299 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
300 [FC_TX] = GM_GPCR_FC_RX_DIS,
301 [FC_RX] = GM_GPCR_FC_TX_DIS,
302 [FC_BOTH] = 0,
303};
304
305
cd28ab6a
SH		 306static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
307{
308 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 309 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 310
93745494
SH		 311 if (sky2->autoneg == AUTONEG_ENABLE
312 && !(hw->chip_id == CHIP_ID_YUKON_XL
313 || hw->chip_id == CHIP_ID_YUKON_EC_U
314 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 315 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
316
317 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 318 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 319 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
320
53419c68 321 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 322 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 323 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 324 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
325 else
53419c68
SH		 326 /* set master & slave downshift counter to 1x */
327 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 328
329 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
330 }
331
332 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 333 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 334 if (hw->chip_id == CHIP_ID_YUKON_FE) {
335 /* enable automatic crossover */
336 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
337 } else {
338 /* disable energy detect */
339 ctrl &= ~PHY_M_PC_EN_DET_MSK;
340
341 /* enable automatic crossover */
342 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
343
53419c68 344 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494
SH		 345 if (sky2->autoneg == AUTONEG_ENABLE
346 && (hw->chip_id == CHIP_ID_YUKON_XL
347 || hw->chip_id == CHIP_ID_YUKON_EC_U
348 || hw->chip_id == CHIP_ID_YUKON_EX)) {
53419c68 349 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 350 ctrl &= ~PHY_M_PC_DSC_MSK;
351 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
352 }
353 }
cd28ab6a
SH		 354 } else {
355 /* workaround for deviation #4.88 (CRC errors) */
356 /* disable Automatic Crossover */
357
358 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 359 }
cd28ab6a 360
b89165f2
SH		 361 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
362
363 /* special setup for PHY 88E1112 Fiber */
364 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
365 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 366
b89165f2
SH		 367 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
368 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
369 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
370 ctrl &= ~PHY_M_MAC_MD_MSK;
371 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
372 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
373
374 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 375 /* select page 1 to access Fiber registers */
376 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 377
378 /* for SFP-module set SIGDET polarity to low */
379 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
380 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 381 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 382 }
b89165f2
SH		 383
384 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 385 }
386
7800fddc 387 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 388 ct1000 = 0;
389 adv = PHY_AN_CSMA;
2eaba1a2 390 reg = 0;
cd28ab6a
SH		 391
392 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 393 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 394 if (sky2->advertising & ADVERTISED_1000baseT_Full)
395 ct1000 |= PHY_M_1000C_AFD;
396 if (sky2->advertising & ADVERTISED_1000baseT_Half)
397 ct1000 |= PHY_M_1000C_AHD;
398 if (sky2->advertising & ADVERTISED_100baseT_Full)
399 adv |= PHY_M_AN_100_FD;
400 if (sky2->advertising & ADVERTISED_100baseT_Half)
401 adv |= PHY_M_AN_100_HD;
402 if (sky2->advertising & ADVERTISED_10baseT_Full)
403 adv |= PHY_M_AN_10_FD;
404 if (sky2->advertising & ADVERTISED_10baseT_Half)
405 adv |= PHY_M_AN_10_HD;
709c6e7b 406
16ad91e1 407 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 408 } else { /* special defines for FIBER (88E1040S only) */
409 if (sky2->advertising & ADVERTISED_1000baseT_Full)
410 adv |= PHY_M_AN_1000X_AFD;
411 if (sky2->advertising & ADVERTISED_1000baseT_Half)
412 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 413
16ad91e1 414 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 415 }
cd28ab6a
SH		 416
417 /* Restart Auto-negotiation */
418 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
419 } else {
420 /* forced speed/duplex settings */
421 ct1000 = PHY_M_1000C_MSE;
422
2eaba1a2
SH		 423 /* Disable auto update for duplex flow control and speed */
424 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 425
426 switch (sky2->speed) {
427 case SPEED_1000:
428 ctrl |= PHY_CT_SP1000;
2eaba1a2 429 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 430 break;
431 case SPEED_100:
432 ctrl |= PHY_CT_SP100;
2eaba1a2 433 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 434 break;
435 }
436
2eaba1a2
SH		 437 if (sky2->duplex == DUPLEX_FULL) {
438 reg |= GM_GPCR_DUP_FULL;
439 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 440 } else if (sky2->speed < SPEED_1000)
441 sky2->flow_mode = FC_NONE;
2eaba1a2 442
2eaba1a2 443
16ad91e1 444 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 445
446 /* Forward pause packets to GMAC? */
16ad91e1 447 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 448 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
449 else
450 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 451 }
452
2eaba1a2
SH		 453 gma_write16(hw, port, GM_GP_CTRL, reg);
454
cd28ab6a
SH		 455 if (hw->chip_id != CHIP_ID_YUKON_FE)
456 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
457
458 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
459 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
460
461 /* Setup Phy LED's */
462 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
463 ledover = 0;
464
465 switch (hw->chip_id) {
466 case CHIP_ID_YUKON_FE:
467 /* on 88E3082 these bits are at 11..9 (shifted left) */
468 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
469
470 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
471
472 /* delete ACT LED control bits */
473 ctrl &= ~PHY_M_FELP_LED1_MSK;
474 /* change ACT LED control to blink mode */
475 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
476 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
477 break;
478
479 case CHIP_ID_YUKON_XL:
793b883e 480 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 481
482 /* select page 3 to access LED control register */
483 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
484
485 /* set LED Function Control register */
ed6d32c7
SH		 486 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
487 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
488 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
489 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
490 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 491
492 /* set Polarity Control register */
493 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 494 (PHY_M_POLC_LS1_P_MIX(4) |
495 PHY_M_POLC_IS0_P_MIX(4) |
496 PHY_M_POLC_LOS_CTRL(2) |
497 PHY_M_POLC_INIT_CTRL(2) |
498 PHY_M_POLC_STA1_CTRL(2) |
499 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 500
501 /* restore page register */
793b883e 502 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 503 break;
93745494 504
ed6d32c7 505 case CHIP_ID_YUKON_EC_U:
93745494 506 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 507 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
508
509 /* select page 3 to access LED control register */
510 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
511
512 /* set LED Function Control register */
513 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
514 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
515 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
516 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
517 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
518
519 /* set Blink Rate in LED Timer Control Register */
520 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
521 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
522 /* restore page register */
523 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
524 break;
cd28ab6a
SH		 525
526 default:
527 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
528 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
529 /* turn off the Rx LED (LED_RX) */
0efdf262 530 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 531 }
532
9467a8fc
SH		 533 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
534 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 535 /* apply fixes in PHY AFE */
ed6d32c7
SH		 536 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
537
977bdf06 538 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 539 gm_phy_write(hw, port, 0x18, 0xaa99);
540 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 541
977bdf06 542 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 543 gm_phy_write(hw, port, 0x18, 0xa204);
544 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 545
546 /* set page register to 0 */
9467a8fc 547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
93745494 548 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 549 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 550
977bdf06
SH		 551 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
552 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 553 ledover |= PHY_M_LED_MO_100;
977bdf06 554 }
cd28ab6a 555
977bdf06
SH		 556 if (ledover)
557 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
558
559 }
2eaba1a2 560
d571b694 561 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 562 if (sky2->autoneg == AUTONEG_ENABLE)
563 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
564 else
565 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
566}
567
d3bcfbeb
SH		 568static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
569{
570 u32 reg1;
571 static const u32 phy_power[]
572 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
573
574 /* looks like this XL is back asswards .. */
575 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
576 onoff = !onoff;
577
aed2cec4 578 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 579 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 580 if (onoff)
581 /* Turn off phy power saving */
582 reg1 &= ~phy_power[port];
583 else
584 reg1 |= phy_power[port];
585
586 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 587 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 588 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 589 udelay(100);
590}
591
1b537565
SH		 592/* Force a renegotiation */
593static void sky2_phy_reinit(struct sky2_port *sky2)
594{
e07b1aa8 595 spin_lock_bh(&sky2->phy_lock);
1b537565 596 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 597 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 598}
599
e3173832
SH		 600/* Put device in state to listen for Wake On Lan */
601static void sky2_wol_init(struct sky2_port *sky2)
602{
603 struct sky2_hw *hw = sky2->hw;
604 unsigned port = sky2->port;
605 enum flow_control save_mode;
606 u16 ctrl;
607 u32 reg1;
608
609 /* Bring hardware out of reset */
610 sky2_write16(hw, B0_CTST, CS_RST_CLR);
611 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
612
613 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
614 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
615
616 /* Force to 10/100
617 * sky2_reset will re-enable on resume
618 */
619 save_mode = sky2->flow_mode;
620 ctrl = sky2->advertising;
621
622 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
623 sky2->flow_mode = FC_NONE;
624 sky2_phy_power(hw, port, 1);
625 sky2_phy_reinit(sky2);
626
627 sky2->flow_mode = save_mode;
628 sky2->advertising = ctrl;
629
630 /* Set GMAC to no flow control and auto update for speed/duplex */
631 gma_write16(hw, port, GM_GP_CTRL,
632 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
633 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
634
635 /* Set WOL address */
636 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
637 sky2->netdev->dev_addr, ETH_ALEN);
638
639 /* Turn on appropriate WOL control bits */
640 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
641 ctrl = 0;
642 if (sky2->wol & WAKE_PHY)
643 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
644 else
645 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
646
647 if (sky2->wol & WAKE_MAGIC)
648 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
649 else
650 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
651
652 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
653 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
654
655 /* Turn on legacy PCI-Express PME mode */
656 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
657 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
658 reg1 |= PCI_Y2_PME_LEGACY;
659 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
660 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
661
662 /* block receiver */
663 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
664
665}
666
69161611
SH		 667static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
668{
669 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev != CHIP_REV_YU_EX_A0) {
670 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
671 TX_STFW_ENA |
672 (hw->dev[port]->mtu > ETH_DATA_LEN) ? TX_JUMBO_ENA : TX_JUMBO_DIS);
673 } else {
674 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
675 /* set Tx GMAC FIFO Almost Empty Threshold */
676 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
677 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
678
679 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
680 TX_JUMBO_ENA | TX_STFW_DIS);
681
682 /* Can't do offload because of lack of store/forward */
683 hw->dev[port]->features &= ~(NETIF_F_TSO | NETIF_F_SG
684 | NETIF_F_ALL_CSUM);
685 } else
686 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
687 TX_JUMBO_DIS | TX_STFW_ENA);
688 }
689}
690
cd28ab6a
SH		 691static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
692{
693 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
694 u16 reg;
695 int i;
696 const u8 *addr = hw->dev[port]->dev_addr;
697
42eeea01 698 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
b4ed372b 699 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 700
701 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
702
793b883e 703 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 704 /* WA DEV_472 -- looks like crossed wires on port 2 */
705 /* clear GMAC 1 Control reset */
706 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
707 do {
708 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
709 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
710 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
711 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
712 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
713 }
714
793b883e 715 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 716
2eaba1a2
SH		 717 /* Enable Transmit FIFO Underrun */
718 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
719
e07b1aa8 720 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 721 sky2_phy_init(hw, port);
e07b1aa8 722 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 723
724 /* MIB clear */
725 reg = gma_read16(hw, port, GM_PHY_ADDR);
726 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
727
43f2f104
SH		 728 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
729 gma_read16(hw, port, i);
cd28ab6a
SH		 730 gma_write16(hw, port, GM_PHY_ADDR, reg);
731
732 /* transmit control */
733 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
734
735 /* receive control reg: unicast + multicast + no FCS */
736 gma_write16(hw, port, GM_RX_CTRL,
793b883e 737 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 738
739 /* transmit flow control */
740 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
741
742 /* transmit parameter */
743 gma_write16(hw, port, GM_TX_PARAM,
744 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
745 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
746 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
747 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
748
749 /* serial mode register */
750 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 751 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 752
6b1a3aef 753 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 754 reg |= GM_SMOD_JUMBO_ENA;
755
756 gma_write16(hw, port, GM_SERIAL_MODE, reg);
757
cd28ab6a
SH		 758 /* virtual address for data */
759 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
760
793b883e
SH		 761 /* physical address: used for pause frames */
762 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
763
764 /* ignore counter overflows */
cd28ab6a
SH		 765 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
766 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
767 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
768
769 /* Configure Rx MAC FIFO */
770 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
69161611
SH		 771 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
772 if (hw->chip_id == CHIP_ID_YUKON_EX)
773 reg |= GMF_RX_OVER_ON;
774
775 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
cd28ab6a 776
d571b694 777 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 778 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 779
8df9a876
SH		 780 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
781 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 782
783 /* Configure Tx MAC FIFO */
784 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
785 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 786
93745494 787 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 788 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 789 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 790
69161611 791 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 792 }
793
cd28ab6a
SH		 794}
795
67712901
SH		 796/* Assign Ram Buffer allocation to queue */
797static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 798{
67712901
SH		 799 u32 end;
800
801 /* convert from K bytes to qwords used for hw register */
802 start *= 1024/8;
803 space *= 1024/8;
804 end = start + space - 1;
793b883e 805
cd28ab6a
SH		 806 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
807 sky2_write32(hw, RB_ADDR(q, RB_START), start);
808 sky2_write32(hw, RB_ADDR(q, RB_END), end);
809 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
810 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
811
812 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 813 u32 tp = space - space/4;
793b883e 814
1c28f6ba
SH		 815 /* On receive queue's set the thresholds
816 * give receiver priority when > 3/4 full
817 * send pause when down to 2K
818 */
819 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
820 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 821
1c28f6ba
SH		 822 tp = space - 2048/8;
823 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
824 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 825 } else {
826 /* Enable store & forward on Tx queue's because
827 * Tx FIFO is only 1K on Yukon
828 */
829 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
830 }
831
832 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 833 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 834}
835
cd28ab6a 836/* Setup Bus Memory Interface */
af4ed7e6 837static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 838{
839 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
840 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
841 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 842 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 843}
844
cd28ab6a
SH		 845/* Setup prefetch unit registers. This is the interface between
846 * hardware and driver list elements
847 */
8cc048e3 848static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 849 u64 addr, u32 last)
850{
cd28ab6a
SH		 851 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
852 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
853 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
854 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
855 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
856 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 857
858 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 859}
860
793b883e
SH		 861static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
862{
863 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
864
cb5d9547 865 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 866 le->ctrl = 0;
793b883e
SH		 867 return le;
868}
cd28ab6a 869
291ea614
SH		 870static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
871 struct sky2_tx_le *le)
872{
873 return sky2->tx_ring + (le - sky2->tx_le);
874}
875
290d4de5
SH		 876/* Update chip's next pointer */
877static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 878{
50432cb5 879 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 880 wmb();
50432cb5
SH		 881 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
882
883 /* Synchronize I/O on since next processor may write to tail */
884 mmiowb();
cd28ab6a
SH		 885}
886
793b883e 887
cd28ab6a
SH		 888static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
889{
890 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 891 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 892 le->ctrl = 0;
cd28ab6a
SH		 893 return le;
894}
895
a018e330
SH		 896/* Return high part of DMA address (could be 32 or 64 bit) */
897static inline u32 high32(dma_addr_t a)
898{
a036119f 899 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 900}
901
14d0263f
SH		 902/* Build description to hardware for one receive segment */
903static void sky2_rx_add(struct sky2_port *sky2, u8 op,
904 dma_addr_t map, unsigned len)
cd28ab6a
SH		 905{
906 struct sky2_rx_le *le;
734d1868 907 u32 hi = high32(map);
cd28ab6a 908
793b883e 909 if (sky2->rx_addr64 != hi) {
cd28ab6a 910 le = sky2_next_rx(sky2);
793b883e 911 le->addr = cpu_to_le32(hi);
cd28ab6a 912 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 913 sky2->rx_addr64 = high32(map + len);
cd28ab6a 914 }
793b883e 915
cd28ab6a 916 le = sky2_next_rx(sky2);
734d1868
SH		 917 le->addr = cpu_to_le32((u32) map);
918 le->length = cpu_to_le16(len);
14d0263f 919 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 920}
921
14d0263f
SH		 922/* Build description to hardware for one possibly fragmented skb */
923static void sky2_rx_submit(struct sky2_port *sky2,
924 const struct rx_ring_info *re)
925{
926 int i;
927
928 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
929
930 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
931 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
932}
933
934
935static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
936 unsigned size)
937{
938 struct sk_buff *skb = re->skb;
939 int i;
940
941 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
942 pci_unmap_len_set(re, data_size, size);
943
944 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
945 re->frag_addr[i] = pci_map_page(pdev,
946 skb_shinfo(skb)->frags[i].page,
947 skb_shinfo(skb)->frags[i].page_offset,
948 skb_shinfo(skb)->frags[i].size,
949 PCI_DMA_FROMDEVICE);
950}
951
952static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
953{
954 struct sk_buff *skb = re->skb;
955 int i;
956
957 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
958 PCI_DMA_FROMDEVICE);
959
960 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
961 pci_unmap_page(pdev, re->frag_addr[i],
962 skb_shinfo(skb)->frags[i].size,
963 PCI_DMA_FROMDEVICE);
964}
793b883e 965
cd28ab6a
SH		 966/* Tell chip where to start receive checksum.
967 * Actually has two checksums, but set both same to avoid possible byte
968 * order problems.
969 */
793b883e 970static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 971{
972 struct sky2_rx_le *le;
973
69161611
SH		 974 if (sky2->hw->chip_id != CHIP_ID_YUKON_EX) {
975 le = sky2_next_rx(sky2);
976 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
977 le->ctrl = 0;
978 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 979
69161611
SH		 980 sky2_write32(sky2->hw,
981 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
982 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
983 }
cd28ab6a
SH		 984
985}
986
6b1a3aef
SH		 987/*
988 * The RX Stop command will not work for Yukon-2 if the BMU does not
989 * reach the end of packet and since we can't make sure that we have
990 * incoming data, we must reset the BMU while it is not doing a DMA
991 * transfer. Since it is possible that the RX path is still active,
992 * the RX RAM buffer will be stopped first, so any possible incoming
993 * data will not trigger a DMA. After the RAM buffer is stopped, the
994 * BMU is polled until any DMA in progress is ended and only then it
995 * will be reset.
996 */
997static void sky2_rx_stop(struct sky2_port *sky2)
998{
999 struct sky2_hw *hw = sky2->hw;
1000 unsigned rxq = rxqaddr[sky2->port];
1001 int i;
1002
1003 /* disable the RAM Buffer receive queue */
1004 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1005
1006 for (i = 0; i < 0xffff; i++)
1007 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1008 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1009 goto stopped;
1010
1011 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1012 sky2->netdev->name);
1013stopped:
1014 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1015
1016 /* reset the Rx prefetch unit */
1017 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1018 mmiowb();
6b1a3aef 1019}
793b883e 1020
d571b694 1021/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1022static void sky2_rx_clean(struct sky2_port *sky2)
1023{
1024 unsigned i;
1025
1026 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1027 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1028 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1029
1030 if (re->skb) {
14d0263f 1031 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1032 kfree_skb(re->skb);
1033 re->skb = NULL;
1034 }
1035 }
1036}
1037
ef743d33
SH		 1038/* Basic MII support */
1039static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1040{
1041 struct mii_ioctl_data *data = if_mii(ifr);
1042 struct sky2_port *sky2 = netdev_priv(dev);
1043 struct sky2_hw *hw = sky2->hw;
1044 int err = -EOPNOTSUPP;
1045
1046 if (!netif_running(dev))
1047 return -ENODEV; /* Phy still in reset */
1048
d89e1343 1049 switch (cmd) {
ef743d33
SH		 1050 case SIOCGMIIPHY:
1051 data->phy_id = PHY_ADDR_MARV;
1052
1053 /* fallthru */
1054 case SIOCGMIIREG: {
1055 u16 val = 0;
91c86df5 1056
e07b1aa8 1057 spin_lock_bh(&sky2->phy_lock);
ef743d33 1058 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1059 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1060
ef743d33
SH		 1061 data->val_out = val;
1062 break;
1063 }
1064
1065 case SIOCSMIIREG:
1066 if (!capable(CAP_NET_ADMIN))
1067 return -EPERM;
1068
e07b1aa8 1069 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1070 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1071 data->val_in);
e07b1aa8 1072 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1073 break;
1074 }
1075 return err;
1076}
1077
d1f13708
SH		 1078#ifdef SKY2_VLAN_TAG_USED
1079static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1080{
1081 struct sky2_port *sky2 = netdev_priv(dev);
1082 struct sky2_hw *hw = sky2->hw;
1083 u16 port = sky2->port;
d1f13708 1084
2bb8c262 1085 netif_tx_lock_bh(dev);
3d4e66f5 1086 netif_poll_disable(sky2->hw->dev[0]);
d1f13708 1087
d1f13708 1088 sky2->vlgrp = grp;
3d4e66f5
SH		 1089 if (grp) {
1090 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1091 RX_VLAN_STRIP_ON);
1092 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1093 TX_VLAN_TAG_ON);
1094 } else {
1095 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1096 RX_VLAN_STRIP_OFF);
1097 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1098 TX_VLAN_TAG_OFF);
1099 }
d1f13708 1100
3d4e66f5 1101 netif_poll_enable(sky2->hw->dev[0]);
2bb8c262 1102 netif_tx_unlock_bh(dev);
d1f13708
SH		 1103}
1104#endif
1105
82788c7a 1106/*
14d0263f
SH		 1107 * Allocate an skb for receiving. If the MTU is large enough
1108 * make the skb non-linear with a fragment list of pages.
1109 *
82788c7a
SH		 1110 * It appears the hardware has a bug in the FIFO logic that
1111 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1112 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1113 * aligned except if slab debugging is enabled.
82788c7a 1114 */
14d0263f 1115static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1116{
1117 struct sk_buff *skb;
14d0263f
SH		 1118 unsigned long p;
1119 int i;
82788c7a 1120
14d0263f
SH		 1121 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1122 if (!skb)
1123 goto nomem;
1124
1125 p = (unsigned long) skb->data;
1126 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1127
1128 for (i = 0; i < sky2->rx_nfrags; i++) {
1129 struct page *page = alloc_page(GFP_ATOMIC);
1130
1131 if (!page)
1132 goto free_partial;
1133 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1134 }
1135
1136 return skb;
14d0263f
SH		 1137free_partial:
1138 kfree_skb(skb);
1139nomem:
1140 return NULL;
82788c7a
SH		 1141}
1142
55c9dd35
SH		 1143static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1144{
1145 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1146}
1147
cd28ab6a
SH		 1148/*
1149 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1150 * Normal case this ends up creating one list element for skb
1151 * in the receive ring. Worst case if using large MTU and each
1152 * allocation falls on a different 64 bit region, that results
1153 * in 6 list elements per ring entry.
1154 * One element is used for checksum enable/disable, and one
1155 * extra to avoid wrap.
cd28ab6a 1156 */
6b1a3aef 1157static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1158{
6b1a3aef 1159 struct sky2_hw *hw = sky2->hw;
14d0263f 1160 struct rx_ring_info *re;
6b1a3aef 1161 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1162 unsigned i, size, space, thresh;
cd28ab6a 1163
6b1a3aef 1164 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1165 sky2_qset(hw, rxq);
977bdf06 1166
c3905bc4
SH		 1167 /* On PCI express lowering the watermark gives better performance */
1168 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1169 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1170
1171 /* These chips have no ram buffer?
1172 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1173 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1174 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1175 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1176 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1177
6b1a3aef
SH		 1178 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1179
1180 rx_set_checksum(sky2);
14d0263f
SH		 1181
1182 /* Space needed for frame data + headers rounded up */
1183 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1184 + 8;
1185
1186 /* Stopping point for hardware truncation */
1187 thresh = (size - 8) / sizeof(u32);
1188
1189 /* Account for overhead of skb - to avoid order > 0 allocation */
1190 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1191 + sizeof(struct skb_shared_info);
1192
1193 sky2->rx_nfrags = space >> PAGE_SHIFT;
1194 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1195
1196 if (sky2->rx_nfrags != 0) {
1197 /* Compute residue after pages */
1198 space = sky2->rx_nfrags << PAGE_SHIFT;
1199
1200 if (space < size)
1201 size -= space;
1202 else
1203 size = 0;
1204
1205 /* Optimize to handle small packets and headers */
1206 if (size < copybreak)
1207 size = copybreak;
1208 if (size < ETH_HLEN)
1209 size = ETH_HLEN;
1210 }
1211 sky2->rx_data_size = size;
1212
1213 /* Fill Rx ring */
793b883e 1214 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1215 re = sky2->rx_ring + i;
cd28ab6a 1216
14d0263f 1217 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1218 if (!re->skb)
1219 goto nomem;
1220
14d0263f
SH		 1221 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1222 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1223 }
1224
a1433ac4
SH		 1225 /*
1226 * The receiver hangs if it receives frames larger than the
1227 * packet buffer. As a workaround, truncate oversize frames, but
1228 * the register is limited to 9 bits, so if you do frames > 2052
1229 * you better get the MTU right!
1230 */
a1433ac4
SH		 1231 if (thresh > 0x1ff)
1232 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1233 else {
1234 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1235 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1236 }
1237
6b1a3aef 1238 /* Tell chip about available buffers */
55c9dd35 1239 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1240 return 0;
1241nomem:
1242 sky2_rx_clean(sky2);
1243 return -ENOMEM;
1244}
1245
1246/* Bring up network interface. */
1247static int sky2_up(struct net_device *dev)
1248{
1249 struct sky2_port *sky2 = netdev_priv(dev);
1250 struct sky2_hw *hw = sky2->hw;
1251 unsigned port = sky2->port;
67712901 1252 u32 ramsize, imask;
ee7abb04 1253 int cap, err = -ENOMEM;
843a46f4 1254 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1255
ee7abb04
SH		 1256 /*
1257 * On dual port PCI-X card, there is an problem where status
1258 * can be received out of order due to split transactions
843a46f4 1259 */
ee7abb04
SH		 1260 if (otherdev && netif_running(otherdev) &&
1261 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1262 struct sky2_port *osky2 = netdev_priv(otherdev);
1263 u16 cmd;
1264
1265 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1266 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1267 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1268
1269 sky2->rx_csum = 0;
1270 osky2->rx_csum = 0;
1271 }
843a46f4 1272
cd28ab6a
SH		 1273 if (netif_msg_ifup(sky2))
1274 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1275
55d7b4e6
SH		 1276 netif_carrier_off(dev);
1277
cd28ab6a
SH		 1278 /* must be power of 2 */
1279 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1280 TX_RING_SIZE *
1281 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1282 &sky2->tx_le_map);
1283 if (!sky2->tx_le)
1284 goto err_out;
1285
6cdbbdf3 1286 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1287 GFP_KERNEL);
1288 if (!sky2->tx_ring)
1289 goto err_out;
1290 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1291
1292 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1293 &sky2->rx_le_map);
1294 if (!sky2->rx_le)
1295 goto err_out;
1296 memset(sky2->rx_le, 0, RX_LE_BYTES);
1297
291ea614 1298 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1299 GFP_KERNEL);
1300 if (!sky2->rx_ring)
1301 goto err_out;
1302
d3bcfbeb
SH		 1303 sky2_phy_power(hw, port, 1);
1304
cd28ab6a
SH		 1305 sky2_mac_init(hw, port);
1306
67712901
SH		 1307 /* Register is number of 4K blocks on internal RAM buffer. */
1308 ramsize = sky2_read8(hw, B2_E_0) * 4;
1309 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1310
67712901
SH		 1311 if (ramsize > 0) {
1312 u32 rxspace;
cd28ab6a 1313
67712901
SH		 1314 if (ramsize < 16)
1315 rxspace = ramsize / 2;
1316 else
1317 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1318
67712901
SH		 1319 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1320 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1321
1322 /* Make sure SyncQ is disabled */
1323 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1324 RB_RST_SET);
1325 }
793b883e 1326
af4ed7e6 1327 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1328
69161611
SH		 1329 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1330 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1331 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1332
977bdf06 1333 /* Set almost empty threshold */
c2716fb4
SH		 1334 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1335 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1336 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1337
6b1a3aef
SH		 1338 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1339 TX_RING_SIZE - 1);
cd28ab6a 1340
6b1a3aef 1341 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1342 if (err)
1343 goto err_out;
1344
cd28ab6a 1345 /* Enable interrupts from phy/mac for port */
e07b1aa8 1346 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1347 imask |= portirq_msk[port];
e07b1aa8
SH		 1348 sky2_write32(hw, B0_IMSK, imask);
1349
cd28ab6a
SH		 1350 return 0;
1351
1352err_out:
1b537565 1353 if (sky2->rx_le) {
cd28ab6a
SH		 1354 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1355 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1356 sky2->rx_le = NULL;
1357 }
1358 if (sky2->tx_le) {
cd28ab6a
SH		 1359 pci_free_consistent(hw->pdev,
1360 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1361 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1362 sky2->tx_le = NULL;
1363 }
1364 kfree(sky2->tx_ring);
1365 kfree(sky2->rx_ring);
cd28ab6a 1366
1b537565
SH		 1367 sky2->tx_ring = NULL;
1368 sky2->rx_ring = NULL;
cd28ab6a
SH		 1369 return err;
1370}
1371
793b883e
SH		 1372/* Modular subtraction in ring */
1373static inline int tx_dist(unsigned tail, unsigned head)
1374{
cb5d9547 1375 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1376}
cd28ab6a 1377
793b883e
SH		 1378/* Number of list elements available for next tx */
1379static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1380{
793b883e 1381 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1382}
1383
793b883e 1384/* Estimate of number of transmit list elements required */
28bd181a 1385static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1386{
793b883e
SH		 1387 unsigned count;
1388
1389 count = sizeof(dma_addr_t) / sizeof(u32);
1390 count += skb_shinfo(skb)->nr_frags * count;
1391
89114afd 1392 if (skb_is_gso(skb))
793b883e
SH		 1393 ++count;
1394
84fa7933 1395 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1396 ++count;
1397
1398 return count;
cd28ab6a
SH		 1399}
1400
793b883e
SH		 1401/*
1402 * Put one packet in ring for transmit.
1403 * A single packet can generate multiple list elements, and
1404 * the number of ring elements will probably be less than the number
1405 * of list elements used.
1406 */
cd28ab6a
SH		 1407static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1408{
1409 struct sky2_port *sky2 = netdev_priv(dev);
1410 struct sky2_hw *hw = sky2->hw;
d1f13708 1411 struct sky2_tx_le *le = NULL;
6cdbbdf3 1412 struct tx_ring_info *re;
cd28ab6a
SH		 1413 unsigned i, len;
1414 dma_addr_t mapping;
1415 u32 addr64;
1416 u16 mss;
1417 u8 ctrl;
1418
2bb8c262
SH		 1419 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1420 return NETDEV_TX_BUSY;
cd28ab6a 1421
793b883e 1422 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1423 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1424 dev->name, sky2->tx_prod, skb->len);
1425
cd28ab6a
SH		 1426 len = skb_headlen(skb);
1427 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1428 addr64 = high32(mapping);
793b883e 1429
a018e330
SH		 1430 /* Send high bits if changed or crosses boundary */
1431 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1432 le = get_tx_le(sky2);
f65b138c 1433 le->addr = cpu_to_le32(addr64);
793b883e 1434 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1435 sky2->tx_addr64 = high32(mapping + len);
793b883e 1436 }
cd28ab6a
SH		 1437
1438 /* Check for TCP Segmentation Offload */
7967168c 1439 mss = skb_shinfo(skb)->gso_size;
793b883e 1440 if (mss != 0) {
69161611
SH		 1441 if (hw->chip_id != CHIP_ID_YUKON_EX)
1442 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1443
1444 if (mss != sky2->tx_last_mss) {
1445 le = get_tx_le(sky2);
1446 le->addr = cpu_to_le32(mss);
1447 if (hw->chip_id == CHIP_ID_YUKON_EX)
1448 le->opcode = OP_MSS | HW_OWNER;
1449 else
1450 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1451 sky2->tx_last_mss = mss;
1452 }
cd28ab6a
SH		 1453 }
1454
cd28ab6a 1455 ctrl = 0;
d1f13708
SH		 1456#ifdef SKY2_VLAN_TAG_USED
1457 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1458 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1459 if (!le) {
1460 le = get_tx_le(sky2);
f65b138c 1461 le->addr = 0;
d1f13708 1462 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1463 } else
1464 le->opcode |= OP_VLAN;
1465 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1466 ctrl |= INS_VLAN;
1467 }
1468#endif
1469
1470 /* Handle TCP checksum offload */
84fa7933 1471 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611
SH		 1472 /* On Yukon EX (some versions) encoding change. */
1473 if (hw->chip_id == CHIP_ID_YUKON_EX
1474 && hw->chip_rev != CHIP_REV_YU_EX_B0)
1475 ctrl |= CALSUM; /* auto checksum */
1476 else {
1477 const unsigned offset = skb_transport_offset(skb);
1478 u32 tcpsum;
1479
1480 tcpsum = offset << 16; /* sum start */
1481 tcpsum |= offset + skb->csum_offset; /* sum write */
1482
1483 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1484 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1485 ctrl |= UDPTCP;
1486
1487 if (tcpsum != sky2->tx_tcpsum) {
1488 sky2->tx_tcpsum = tcpsum;
1489
1490 le = get_tx_le(sky2);
1491 le->addr = cpu_to_le32(tcpsum);
1492 le->length = 0; /* initial checksum value */
1493 le->ctrl = 1; /* one packet */
1494 le->opcode = OP_TCPLISW | HW_OWNER;
1495 }
1d179332 1496 }
cd28ab6a
SH		 1497 }
1498
1499 le = get_tx_le(sky2);
f65b138c 1500 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1501 le->length = cpu_to_le16(len);
1502 le->ctrl = ctrl;
793b883e 1503 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1504
291ea614 1505 re = tx_le_re(sky2, le);
cd28ab6a 1506 re->skb = skb;
6cdbbdf3 1507 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1508 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1509
1510 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1511 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1512
1513 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1514 frag->size, PCI_DMA_TODEVICE);
a036119f 1515 addr64 = high32(mapping);
793b883e
SH		 1516 if (addr64 != sky2->tx_addr64) {
1517 le = get_tx_le(sky2);
f65b138c 1518 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1519 le->ctrl = 0;
1520 le->opcode = OP_ADDR64 | HW_OWNER;
1521 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1522 }
1523
1524 le = get_tx_le(sky2);
f65b138c 1525 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1526 le->length = cpu_to_le16(frag->size);
1527 le->ctrl = ctrl;
793b883e 1528 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1529
291ea614
SH		 1530 re = tx_le_re(sky2, le);
1531 re->skb = skb;
1532 pci_unmap_addr_set(re, mapaddr, mapping);
1533 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1534 }
6cdbbdf3 1535
cd28ab6a
SH		 1536 le->ctrl |= EOP;
1537
97bda706
SH		 1538 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1539 netif_stop_queue(dev);
b19666d9 1540
290d4de5 1541 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1542
cd28ab6a
SH		 1543 dev->trans_start = jiffies;
1544 return NETDEV_TX_OK;
1545}
1546
cd28ab6a 1547/*
793b883e
SH		 1548 * Free ring elements from starting at tx_cons until "done"
1549 *
1550 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1551 * buffers so make sure not to free skb to early.
cd28ab6a 1552 */
d11c13e7 1553static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1554{
d11c13e7 1555 struct net_device *dev = sky2->netdev;
af2a58ac 1556 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1557 unsigned idx;
cd28ab6a 1558
0e3ff6aa 1559 BUG_ON(done >= TX_RING_SIZE);
2224795d 1560
291ea614
SH		 1561 for (idx = sky2->tx_cons; idx != done;
1562 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1563 struct sky2_tx_le *le = sky2->tx_le + idx;
1564 struct tx_ring_info *re = sky2->tx_ring + idx;
1565
1566 switch(le->opcode & ~HW_OWNER) {
1567 case OP_LARGESEND:
1568 case OP_PACKET:
1569 pci_unmap_single(pdev,
1570 pci_unmap_addr(re, mapaddr),
1571 pci_unmap_len(re, maplen),
1572 PCI_DMA_TODEVICE);
af2a58ac 1573 break;
291ea614
SH		 1574 case OP_BUFFER:
1575 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1576 pci_unmap_len(re, maplen),
734d1868 1577 PCI_DMA_TODEVICE);
291ea614
SH		 1578 break;
1579 }
1580
1581 if (le->ctrl & EOP) {
1582 if (unlikely(netif_msg_tx_done(sky2)))
1583 printk(KERN_DEBUG "%s: tx done %u\n",
1584 dev->name, idx);
3cf26753 1585
2bf56fe2 1586 sky2->net_stats.tx_packets++;
1587 sky2->net_stats.tx_bytes += re->skb->len;
1588
794b2bd2 1589 dev_kfree_skb_any(re->skb);
3cf26753 1590 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1591 }
793b883e 1592 }
793b883e 1593
291ea614 1594 sky2->tx_cons = idx;
50432cb5
SH		 1595 smp_mb();
1596
22e11703 1597 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1598 netif_wake_queue(dev);
cd28ab6a
SH		 1599}
1600
1601/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1602static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1603{
2bb8c262
SH		 1604 struct sky2_port *sky2 = netdev_priv(dev);
1605
1606 netif_tx_lock_bh(dev);
d11c13e7 1607 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1608 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1609}
1610
1611/* Network shutdown */
1612static int sky2_down(struct net_device *dev)
1613{
1614 struct sky2_port *sky2 = netdev_priv(dev);
1615 struct sky2_hw *hw = sky2->hw;
1616 unsigned port = sky2->port;
1617 u16 ctrl;
e07b1aa8 1618 u32 imask;
cd28ab6a 1619
1b537565
SH		 1620 /* Never really got started! */
1621 if (!sky2->tx_le)
1622 return 0;
1623
cd28ab6a
SH		 1624 if (netif_msg_ifdown(sky2))
1625 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1626
018d1c66 1627 /* Stop more packets from being queued */
cd28ab6a
SH		 1628 netif_stop_queue(dev);
1629
ebc646f6
SH		 1630 /* Disable port IRQ */
1631 imask = sky2_read32(hw, B0_IMSK);
1632 imask &= ~portirq_msk[port];
1633 sky2_write32(hw, B0_IMSK, imask);
1634
d3bcfbeb 1635 sky2_gmac_reset(hw, port);
793b883e 1636
cd28ab6a
SH		 1637 /* Stop transmitter */
1638 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1639 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1640
1641 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1642 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1643
1644 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1645 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1646 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1647
1648 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1649
1650 /* Workaround shared GMAC reset */
793b883e
SH		 1651 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1652 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1653 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1654
1655 /* Disable Force Sync bit and Enable Alloc bit */
1656 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1657 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1658
1659 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1660 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1661 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1662
1663 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1664 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1665 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1666
1667 /* Reset the Tx prefetch units */
1668 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1669 PREF_UNIT_RST_SET);
1670
1671 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1672
6b1a3aef 1673 sky2_rx_stop(sky2);
cd28ab6a
SH		 1674
1675 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1676 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1677
d3bcfbeb
SH		 1678 sky2_phy_power(hw, port, 0);
1679
55d7b4e6
SH		 1680 netif_carrier_off(dev);
1681
d571b694 1682 /* turn off LED's */
cd28ab6a
SH		 1683 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1684
018d1c66
SH		 1685 synchronize_irq(hw->pdev->irq);
1686
2bb8c262 1687 sky2_tx_clean(dev);
cd28ab6a
SH		 1688 sky2_rx_clean(sky2);
1689
1690 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1691 sky2->rx_le, sky2->rx_le_map);
1692 kfree(sky2->rx_ring);
1693
1694 pci_free_consistent(hw->pdev,
1695 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1696 sky2->tx_le, sky2->tx_le_map);
1697 kfree(sky2->tx_ring);
1698
1b537565
SH		 1699 sky2->tx_le = NULL;
1700 sky2->rx_le = NULL;
1701
1702 sky2->rx_ring = NULL;
1703 sky2->tx_ring = NULL;
1704
cd28ab6a
SH		 1705 return 0;
1706}
1707
1708static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1709{
b89165f2 1710 if (!sky2_is_copper(hw))
793b883e
SH		 1711 return SPEED_1000;
1712
cd28ab6a
SH		 1713 if (hw->chip_id == CHIP_ID_YUKON_FE)
1714 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1715
1716 switch (aux & PHY_M_PS_SPEED_MSK) {
1717 case PHY_M_PS_SPEED_1000:
1718 return SPEED_1000;
1719 case PHY_M_PS_SPEED_100:
1720 return SPEED_100;
1721 default:
1722 return SPEED_10;
1723 }
1724}
1725
1726static void sky2_link_up(struct sky2_port *sky2)
1727{
1728 struct sky2_hw *hw = sky2->hw;
1729 unsigned port = sky2->port;
1730 u16 reg;
16ad91e1
SH		 1731 static const char *fc_name[] = {
1732 [FC_NONE] = "none",
1733 [FC_TX] = "tx",
1734 [FC_RX] = "rx",
1735 [FC_BOTH] = "both",
1736 };
cd28ab6a 1737
cd28ab6a 1738 /* enable Rx/Tx */
2eaba1a2 1739 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1740 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1741 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1742
1743 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1744
1745 netif_carrier_on(sky2->netdev);
cd28ab6a
SH		 1746
1747 /* Turn on link LED */
793b883e 1748 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1749 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1750
93745494
SH		 1751 if (hw->chip_id == CHIP_ID_YUKON_XL
1752 || hw->chip_id == CHIP_ID_YUKON_EC_U
1753 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1754 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1755 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1756
1757 switch(sky2->speed) {
1758 case SPEED_10:
1759 led |= PHY_M_LEDC_INIT_CTRL(7);
1760 break;
1761
1762 case SPEED_100:
1763 led |= PHY_M_LEDC_STA1_CTRL(7);
1764 break;
1765
1766 case SPEED_1000:
1767 led |= PHY_M_LEDC_STA0_CTRL(7);
1768 break;
1769 }
793b883e
SH		 1770
1771 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1772 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1773 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1774 }
1775
cd28ab6a
SH		 1776 if (netif_msg_link(sky2))
1777 printk(KERN_INFO PFX
d571b694 1778 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1779 sky2->netdev->name, sky2->speed,
1780 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1781 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1782}
1783
1784static void sky2_link_down(struct sky2_port *sky2)
1785{
1786 struct sky2_hw *hw = sky2->hw;
1787 unsigned port = sky2->port;
1788 u16 reg;
1789
1790 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1791
1792 reg = gma_read16(hw, port, GM_GP_CTRL);
1793 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1794 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1795
cd28ab6a 1796 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1797
1798 /* Turn on link LED */
1799 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1800
1801 if (netif_msg_link(sky2))
1802 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1803
cd28ab6a
SH		 1804 sky2_phy_init(hw, port);
1805}
1806
16ad91e1
SH		 1807static enum flow_control sky2_flow(int rx, int tx)
1808{
1809 if (rx)
1810 return tx ? FC_BOTH : FC_RX;
1811 else
1812 return tx ? FC_TX : FC_NONE;
1813}
1814
793b883e
SH		 1815static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1816{
1817 struct sky2_hw *hw = sky2->hw;
1818 unsigned port = sky2->port;
da4c1ff4 1819 u16 advert, lpa;
793b883e 1820
da4c1ff4 1821 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1822 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1823 if (lpa & PHY_M_AN_RF) {
1824 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1825 return -1;
1826 }
1827
793b883e
SH		 1828 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1829 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1830 sky2->netdev->name);
1831 return -1;
1832 }
1833
793b883e 1834 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1835 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1836
da4c1ff4
SH		 1837 /* Since the pause result bits seem to in different positions on
1838 * different chips. look at registers.
1839 */
1840 if (!sky2_is_copper(hw)) {
1841 /* Shift for bits in fiber PHY */
1842 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1843 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1844
1845 if (advert & ADVERTISE_1000XPAUSE)
1846 advert |= ADVERTISE_PAUSE_CAP;
1847 if (advert & ADVERTISE_1000XPSE_ASYM)
1848 advert |= ADVERTISE_PAUSE_ASYM;
1849 if (lpa & LPA_1000XPAUSE)
1850 lpa |= LPA_PAUSE_CAP;
1851 if (lpa & LPA_1000XPAUSE_ASYM)
1852 lpa |= LPA_PAUSE_ASYM;
1853 }
793b883e 1854
da4c1ff4
SH		 1855 sky2->flow_status = FC_NONE;
1856 if (advert & ADVERTISE_PAUSE_CAP) {
1857 if (lpa & LPA_PAUSE_CAP)
1858 sky2->flow_status = FC_BOTH;
1859 else if (advert & ADVERTISE_PAUSE_ASYM)
1860 sky2->flow_status = FC_RX;
1861 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1862 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1863 sky2->flow_status = FC_TX;
1864 }
793b883e 1865
16ad91e1 1866 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1867 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1868 sky2->flow_status = FC_NONE;
2eaba1a2 1869
da4c1ff4 1870 if (sky2->flow_status & FC_TX)
793b883e
SH		 1871 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1872 else
1873 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1874
1875 return 0;
1876}
cd28ab6a 1877
e07b1aa8
SH		 1878/* Interrupt from PHY */
1879static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1880{
e07b1aa8
SH		 1881 struct net_device *dev = hw->dev[port];
1882 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1883 u16 istatus, phystat;
1884
ebc646f6
SH		 1885 if (!netif_running(dev))
1886 return;
1887
e07b1aa8
SH		 1888 spin_lock(&sky2->phy_lock);
1889 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1890 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1891
cd28ab6a
SH		 1892 if (netif_msg_intr(sky2))
1893 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1894 sky2->netdev->name, istatus, phystat);
1895
2eaba1a2 1896 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1897 if (sky2_autoneg_done(sky2, phystat) == 0)
1898 sky2_link_up(sky2);
1899 goto out;
1900 }
cd28ab6a 1901
793b883e
SH		 1902 if (istatus & PHY_M_IS_LSP_CHANGE)
1903 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1904
793b883e
SH		 1905 if (istatus & PHY_M_IS_DUP_CHANGE)
1906 sky2->duplex =
1907 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1908
793b883e
SH		 1909 if (istatus & PHY_M_IS_LST_CHANGE) {
1910 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1911 sky2_link_up(sky2);
793b883e
SH		 1912 else
1913 sky2_link_down(sky2);
cd28ab6a 1914 }
793b883e 1915out:
e07b1aa8 1916 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1917}
1918
62335ab0 1919/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1920 * and tx queue is full (stopped).
1921 */
cd28ab6a
SH		 1922static void sky2_tx_timeout(struct net_device *dev)
1923{
1924 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1925 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1926
1927 if (netif_msg_timer(sky2))
1928 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1929
8f24664d 1930 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1931 dev->name, sky2->tx_cons, sky2->tx_prod,
1932 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1933 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1934
81906791
SH		 1935 /* can't restart safely under softirq */
1936 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1937}
1938
1939static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1940{
6b1a3aef
SH		 1941 struct sky2_port *sky2 = netdev_priv(dev);
1942 struct sky2_hw *hw = sky2->hw;
b628ed98 1943 unsigned port = sky2->port;
6b1a3aef
SH		 1944 int err;
1945 u16 ctl, mode;
e07b1aa8 1946 u32 imask;
cd28ab6a
SH		 1947
1948 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1949 return -EINVAL;
1950
d2adf4f6
SH		 1951 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1952 return -EINVAL;
1953
6b1a3aef
SH		 1954 if (!netif_running(dev)) {
1955 dev->mtu = new_mtu;
1956 return 0;
1957 }
1958
e07b1aa8 1959 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1960 sky2_write32(hw, B0_IMSK, 0);
1961
018d1c66
SH		 1962 dev->trans_start = jiffies; /* prevent tx timeout */
1963 netif_stop_queue(dev);
1964 netif_poll_disable(hw->dev[0]);
1965
e07b1aa8
SH		 1966 synchronize_irq(hw->pdev->irq);
1967
69161611
SH		 1968 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
1969 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 1970
1971 ctl = gma_read16(hw, port, GM_GP_CTRL);
1972 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 1973 sky2_rx_stop(sky2);
1974 sky2_rx_clean(sky2);
cd28ab6a
SH		 1975
1976 dev->mtu = new_mtu;
14d0263f 1977
6b1a3aef
SH		 1978 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1979 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1980
1981 if (dev->mtu > ETH_DATA_LEN)
1982 mode |= GM_SMOD_JUMBO_ENA;
1983
b628ed98 1984 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 1985
b628ed98 1986 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1987
6b1a3aef 1988 err = sky2_rx_start(sky2);
e07b1aa8 1989 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1990
1b537565
SH		 1991 if (err)
1992 dev_close(dev);
1993 else {
b628ed98 1994 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 1995
1996 netif_poll_enable(hw->dev[0]);
1997 netif_wake_queue(dev);
1998 }
1999
cd28ab6a
SH		 2000 return err;
2001}
2002
14d0263f
SH		 2003/* For small just reuse existing skb for next receive */
2004static struct sk_buff *receive_copy(struct sky2_port *sky2,
2005 const struct rx_ring_info *re,
2006 unsigned length)
2007{
2008 struct sk_buff *skb;
2009
2010 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2011 if (likely(skb)) {
2012 skb_reserve(skb, 2);
2013 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2014 length, PCI_DMA_FROMDEVICE);
d626f62b 2015 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2016 skb->ip_summed = re->skb->ip_summed;
2017 skb->csum = re->skb->csum;
2018 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2019 length, PCI_DMA_FROMDEVICE);
2020 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2021 skb_put(skb, length);
14d0263f
SH		 2022 }
2023 return skb;
2024}
2025
2026/* Adjust length of skb with fragments to match received data */
2027static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2028 unsigned int length)
2029{
2030 int i, num_frags;
2031 unsigned int size;
2032
2033 /* put header into skb */
2034 size = min(length, hdr_space);
2035 skb->tail += size;
2036 skb->len += size;
2037 length -= size;
2038
2039 num_frags = skb_shinfo(skb)->nr_frags;
2040 for (i = 0; i < num_frags; i++) {
2041 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2042
2043 if (length == 0) {
2044 /* don't need this page */
2045 __free_page(frag->page);
2046 --skb_shinfo(skb)->nr_frags;
2047 } else {
2048 size = min(length, (unsigned) PAGE_SIZE);
2049
2050 frag->size = size;
2051 skb->data_len += size;
2052 skb->truesize += size;
2053 skb->len += size;
2054 length -= size;
2055 }
2056 }
2057}
2058
2059/* Normal packet - take skb from ring element and put in a new one */
2060static struct sk_buff *receive_new(struct sky2_port *sky2,
2061 struct rx_ring_info *re,
2062 unsigned int length)
2063{
2064 struct sk_buff *skb, *nskb;
2065 unsigned hdr_space = sky2->rx_data_size;
2066
2067 pr_debug(PFX "receive new length=%d\n", length);
2068
2069 /* Don't be tricky about reusing pages (yet) */
2070 nskb = sky2_rx_alloc(sky2);
2071 if (unlikely(!nskb))
2072 return NULL;
2073
2074 skb = re->skb;
2075 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2076
2077 prefetch(skb->data);
2078 re->skb = nskb;
2079 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2080
2081 if (skb_shinfo(skb)->nr_frags)
2082 skb_put_frags(skb, hdr_space, length);
2083 else
489b10c1 2084 skb_put(skb, length);
14d0263f
SH		 2085 return skb;
2086}
2087
cd28ab6a
SH		 2088/*
2089 * Receive one packet.
d571b694 2090 * For larger packets, get new buffer.
cd28ab6a 2091 */
497d7c86 2092static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2093 u16 length, u32 status)
2094{
497d7c86 2095 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2096 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2097 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2098
2099 if (unlikely(netif_msg_rx_status(sky2)))
2100 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2101 dev->name, sky2->rx_next, status, length);
cd28ab6a 2102
793b883e 2103 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2104 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2105
42eeea01 2106 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2107 goto error;
2108
42eeea01
SH		 2109 if (!(status & GMR_FS_RX_OK))
2110 goto resubmit;
2111
71749531
SH		 2112 if (status >> 16 != length)
2113 goto len_mismatch;
2114
14d0263f
SH		 2115 if (length < copybreak)
2116 skb = receive_copy(sky2, re, length);
2117 else
2118 skb = receive_new(sky2, re, length);
793b883e 2119resubmit:
14d0263f 2120 sky2_rx_submit(sky2, re);
79e57d32 2121
cd28ab6a
SH		 2122 return skb;
2123
71749531
SH		 2124len_mismatch:
2125 /* Truncation of overlength packets
2126 causes PHY length to not match MAC length */
2127 ++sky2->net_stats.rx_length_errors;
2128
cd28ab6a 2129error:
6e15b712 2130 ++sky2->net_stats.rx_errors;
b6d77734 2131 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2132 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2133 goto resubmit;
2134 }
6e15b712 2135
3be92a70 2136 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2137 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2138 dev->name, status, length);
793b883e
SH		 2139
2140 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2141 sky2->net_stats.rx_length_errors++;
2142 if (status & GMR_FS_FRAGMENT)
2143 sky2->net_stats.rx_frame_errors++;
2144 if (status & GMR_FS_CRC_ERR)
2145 sky2->net_stats.rx_crc_errors++;
79e57d32 2146
793b883e 2147 goto resubmit;
cd28ab6a
SH		 2148}
2149
e07b1aa8
SH		 2150/* Transmit complete */
2151static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2152{
e07b1aa8 2153 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2154
e07b1aa8 2155 if (netif_running(dev)) {
2bb8c262 2156 netif_tx_lock(dev);
e07b1aa8 2157 sky2_tx_complete(sky2, last);
2bb8c262 2158 netif_tx_unlock(dev);
2224795d 2159 }
cd28ab6a
SH		 2160}
2161
e07b1aa8
SH		 2162/* Process status response ring */
2163static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2164{
e07b1aa8 2165 int work_done = 0;
55c9dd35 2166 unsigned rx[2] = { 0, 0 };
e71ebd73 2167 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2168
af2a58ac 2169 rmb();
bea86103 2170
e71ebd73 2171 while (hw->st_idx != hwidx) {
55c9dd35 2172 struct sky2_port *sky2;
13210ce5 2173 struct sky2_status_le *le = hw->st_le + hw->st_idx;
69161611 2174 unsigned port = le->css & CSS_LINK_BIT;
13210ce5 2175 struct net_device *dev;
cd28ab6a 2176 struct sk_buff *skb;
cd28ab6a
SH		 2177 u32 status;
2178 u16 length;
2179
cb5d9547 2180 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2181
69161611 2182 dev = hw->dev[port];
13210ce5 2183 sky2 = netdev_priv(dev);
f65b138c
SH		 2184 length = le16_to_cpu(le->length);
2185 status = le32_to_cpu(le->status);
cd28ab6a 2186
e71ebd73 2187 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2188 case OP_RXSTAT:
55c9dd35 2189 ++rx[port];
497d7c86 2190 skb = sky2_receive(dev, length, status);
3225b919
SH		 2191 if (unlikely(!skb)) {
2192 sky2->net_stats.rx_dropped++;
55c9dd35 2193 break;
3225b919 2194 }
13210ce5 2195
69161611
SH		 2196 /* This chip reports checksum status differently */
2197 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2198 if (sky2->rx_csum &&
2199 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2200 (le->css & CSS_TCPUDPCSOK))
2201 skb->ip_summed = CHECKSUM_UNNECESSARY;
2202 else
2203 skb->ip_summed = CHECKSUM_NONE;
2204 }
2205
13210ce5 2206 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2207 sky2->net_stats.rx_packets++;
2208 sky2->net_stats.rx_bytes += skb->len;
13210ce5
SH		 2209 dev->last_rx = jiffies;
2210
d1f13708
SH		 2211#ifdef SKY2_VLAN_TAG_USED
2212 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2213 vlan_hwaccel_receive_skb(skb,
2214 sky2->vlgrp,
2215 be16_to_cpu(sky2->rx_tag));
2216 } else
2217#endif
cd28ab6a 2218 netif_receive_skb(skb);
13210ce5 2219
22e11703 2220 /* Stop after net poll weight */
13210ce5
SH		 2221 if (++work_done >= to_do)
2222 goto exit_loop;
cd28ab6a
SH		 2223 break;
2224
d1f13708
SH		 2225#ifdef SKY2_VLAN_TAG_USED
2226 case OP_RXVLAN:
2227 sky2->rx_tag = length;
2228 break;
2229
2230 case OP_RXCHKSVLAN:
2231 sky2->rx_tag = length;
2232 /* fall through */
2233#endif
cd28ab6a 2234 case OP_RXCHKS:
87418307
SH		 2235 if (!sky2->rx_csum)
2236 break;
2237
69161611
SH		 2238 if (hw->chip_id == CHIP_ID_YUKON_EX)
2239 break;
2240
87418307
SH		 2241 /* Both checksum counters are programmed to start at
2242 * the same offset, so unless there is a problem they
2243 * should match. This failure is an early indication that
2244 * hardware receive checksumming won't work.
2245 */
2246 if (likely(status >> 16 == (status & 0xffff))) {
2247 skb = sky2->rx_ring[sky2->rx_next].skb;
2248 skb->ip_summed = CHECKSUM_COMPLETE;
2249 skb->csum = status & 0xffff;
2250 } else {
2251 printk(KERN_NOTICE PFX "%s: hardware receive "
2252 "checksum problem (status = %#x)\n",
2253 dev->name, status);
2254 sky2->rx_csum = 0;
2255 sky2_write32(sky2->hw,
69161611 2256 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2257 BMU_DIS_RX_CHKSUM);
2258 }
cd28ab6a
SH		 2259 break;
2260
2261 case OP_TXINDEXLE:
13b97b74 2262 /* TX index reports status for both ports */
f55925d7
SH		 2263 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2264 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2265 if (hw->dev[1])
2266 sky2_tx_done(hw->dev[1],
2267 ((status >> 24) & 0xff)
2268 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2269 break;
2270
cd28ab6a
SH		 2271 default:
2272 if (net_ratelimit())
793b883e 2273 printk(KERN_WARNING PFX
e71ebd73 2274 "unknown status opcode 0x%x\n", le->opcode);
cd28ab6a 2275 }
13210ce5 2276 }
cd28ab6a 2277
fe2a24df
SH		 2278 /* Fully processed status ring so clear irq */
2279 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2280
13210ce5 2281exit_loop:
55c9dd35
SH		 2282 if (rx[0])
2283 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2284
55c9dd35
SH		 2285 if (rx[1])
2286 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2287
e07b1aa8 2288 return work_done;
cd28ab6a
SH		 2289}
2290
2291static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2292{
2293 struct net_device *dev = hw->dev[port];
2294
3be92a70
SH		 2295 if (net_ratelimit())
2296 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2297 dev->name, status);
cd28ab6a
SH		 2298
2299 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2300 if (net_ratelimit())
2301 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2302 dev->name);
cd28ab6a
SH		 2303 /* Clear IRQ */
2304 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2305 }
2306
2307 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2308 if (net_ratelimit())
2309 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2310 dev->name);
cd28ab6a
SH		 2311
2312 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2313 }
2314
2315 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2316 if (net_ratelimit())
2317 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2318 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2319 }
2320
2321 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2322 if (net_ratelimit())
2323 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2324 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2325 }
2326
2327 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2328 if (net_ratelimit())
2329 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2330 dev->name);
cd28ab6a
SH		 2331 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2332 }
2333}
2334
2335static void sky2_hw_intr(struct sky2_hw *hw)
2336{
2337 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2338
793b883e 2339 if (status & Y2_IS_TIST_OV)
cd28ab6a 2340 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2341
2342 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2343 u16 pci_err;
2344
56a645cc 2345 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2346 if (net_ratelimit())
b02a9258
SH		 2347 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2348 pci_err);
cd28ab6a
SH		 2349
2350 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2351 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2352 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2353 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2354 }
2355
2356 if (status & Y2_IS_PCI_EXP) {
d571b694 2357 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2358 u32 pex_err;
2359
7bd656d1 2360 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2361
3be92a70 2362 if (net_ratelimit())
b02a9258
SH		 2363 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2364 pex_err);
cd28ab6a
SH		 2365
2366 /* clear the interrupt */
2367 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2368 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2369 0xffffffffUL);
cd28ab6a
SH		 2370 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2371
7bd656d1 2372 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2373 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2374 hwmsk &= ~Y2_IS_PCI_EXP;
2375 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2376 }
2377 }
2378
2379 if (status & Y2_HWE_L1_MASK)
2380 sky2_hw_error(hw, 0, status);
2381 status >>= 8;
2382 if (status & Y2_HWE_L1_MASK)
2383 sky2_hw_error(hw, 1, status);
2384}
2385
2386static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2387{
2388 struct net_device *dev = hw->dev[port];
2389 struct sky2_port *sky2 = netdev_priv(dev);
2390 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2391
2392 if (netif_msg_intr(sky2))
2393 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2394 dev->name, status);
2395
a3caeada
SH		 2396 if (status & GM_IS_RX_CO_OV)
2397 gma_read16(hw, port, GM_RX_IRQ_SRC);
2398
2399 if (status & GM_IS_TX_CO_OV)
2400 gma_read16(hw, port, GM_TX_IRQ_SRC);
2401
cd28ab6a
SH		 2402 if (status & GM_IS_RX_FF_OR) {
2403 ++sky2->net_stats.rx_fifo_errors;
2404 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2405 }
2406
2407 if (status & GM_IS_TX_FF_UR) {
2408 ++sky2->net_stats.tx_fifo_errors;
2409 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2410 }
cd28ab6a
SH		 2411}
2412
40b01727
SH		 2413/* This should never happen it is a bug. */
2414static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2415 u16 q, unsigned ring_size)
d257924e
SH		 2416{
2417 struct net_device *dev = hw->dev[port];
2418 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2419 unsigned idx;
2420 const u64 *le = (q == Q_R1 || q == Q_R2)
2421 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2422
40b01727
SH		 2423 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2424 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2425 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2426 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2427
40b01727 2428 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2429}
cd28ab6a 2430
d27ed387
SH		 2431/* If idle then force a fake soft NAPI poll once a second
2432 * to work around cases where sharing an edge triggered interrupt.
2433 */
eb35cf60
SH		 2434static inline void sky2_idle_start(struct sky2_hw *hw)
2435{
2436 if (idle_timeout > 0)
2437 mod_timer(&hw->idle_timer,
2438 jiffies + msecs_to_jiffies(idle_timeout));
2439}
2440
d27ed387
SH		 2441static void sky2_idle(unsigned long arg)
2442{
01bd7564
SH		 2443 struct sky2_hw *hw = (struct sky2_hw *) arg;
2444 struct net_device *dev = hw->dev[0];
d27ed387 2445
d27ed387
SH		 2446 if (__netif_rx_schedule_prep(dev))
2447 __netif_rx_schedule(dev);
01bd7564
SH		 2448
2449 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2450}
2451
40b01727
SH		 2452/* Hardware/software error handling */
2453static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2454{
40b01727
SH		 2455 if (net_ratelimit())
2456 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2457
1e5f1283
SH		 2458 if (status & Y2_IS_HW_ERR)
2459 sky2_hw_intr(hw);
d257924e 2460
1e5f1283
SH		 2461 if (status & Y2_IS_IRQ_MAC1)
2462 sky2_mac_intr(hw, 0);
cd28ab6a 2463
1e5f1283
SH		 2464 if (status & Y2_IS_IRQ_MAC2)
2465 sky2_mac_intr(hw, 1);
cd28ab6a 2466
1e5f1283 2467 if (status & Y2_IS_CHK_RX1)
40b01727 2468 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2469
1e5f1283 2470 if (status & Y2_IS_CHK_RX2)
40b01727 2471 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2472
1e5f1283 2473 if (status & Y2_IS_CHK_TXA1)
40b01727 2474 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2475
1e5f1283 2476 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2477 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2478}
2479
2480static int sky2_poll(struct net_device *dev0, int *budget)
2481{
2482 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
5c11ce70 2483 int work_done;
40b01727
SH		 2484 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2485
2486 if (unlikely(status & Y2_IS_ERROR))
2487 sky2_err_intr(hw, status);
2488
2489 if (status & Y2_IS_IRQ_PHY1)
2490 sky2_phy_intr(hw, 0);
2491
2492 if (status & Y2_IS_IRQ_PHY2)
2493 sky2_phy_intr(hw, 1);
cd28ab6a 2494
5c11ce70
SH		 2495 work_done = sky2_status_intr(hw, min(dev0->quota, *budget));
2496 *budget -= work_done;
2497 dev0->quota -= work_done;
86fba634 2498
5c11ce70
SH		 2499 /* More work? */
2500 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
1e5f1283 2501 return 1;
5c11ce70
SH		 2502
2503 /* Bug/Errata workaround?
2504 * Need to kick the TX irq moderation timer.
2505 */
2506 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2507 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2508 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2509 }
5c11ce70
SH		 2510 netif_rx_complete(dev0);
2511
2512 sky2_read32(hw, B0_Y2_SP_LISR);
2513 return 0;
e07b1aa8
SH		 2514}
2515
7d12e780 2516static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2517{
2518 struct sky2_hw *hw = dev_id;
2519 struct net_device *dev0 = hw->dev[0];
2520 u32 status;
2521
2522 /* Reading this mask interrupts as side effect */
2523 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2524 if (status == 0 || status == ~0)
2525 return IRQ_NONE;
793b883e 2526
e07b1aa8
SH		 2527 prefetch(&hw->st_le[hw->st_idx]);
2528 if (likely(__netif_rx_schedule_prep(dev0)))
2529 __netif_rx_schedule(dev0);
793b883e 2530
cd28ab6a
SH		 2531 return IRQ_HANDLED;
2532}
2533
2534#ifdef CONFIG_NET_POLL_CONTROLLER
2535static void sky2_netpoll(struct net_device *dev)
2536{
2537 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2538 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2539
88d11360
SH		 2540 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2541 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2542}
2543#endif
2544
2545/* Chip internal frequency for clock calculations */
fb17358f 2546static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2547{
793b883e 2548 switch (hw->chip_id) {
cd28ab6a 2549 case CHIP_ID_YUKON_EC:
5a5b1ea0 2550 case CHIP_ID_YUKON_EC_U:
93745494 2551 case CHIP_ID_YUKON_EX:
fb17358f 2552 return 125; /* 125 Mhz */
cd28ab6a 2553 case CHIP_ID_YUKON_FE:
fb17358f 2554 return 100; /* 100 Mhz */
793b883e 2555 default: /* YUKON_XL */
fb17358f 2556 return 156; /* 156 Mhz */
cd28ab6a
SH		 2557 }
2558}
2559
fb17358f 2560static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2561{
fb17358f 2562 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2563}
2564
fb17358f 2565static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2566{
fb17358f 2567 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2568}
2569
fb17358f 2570
e3173832 2571static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2572{
b89165f2 2573 u8 t8;
cd28ab6a 2574
451af335
SH		 2575 /* Enable all clocks */
2576 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2577
cd28ab6a 2578 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2579
cd28ab6a
SH		 2580 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2581 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2582 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2583 hw->chip_id);
cd28ab6a
SH		 2584 return -EOPNOTSUPP;
2585 }
2586
290d4de5
SH		 2587 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2588
2589 /* This rev is really old, and requires untested workarounds */
2590 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2591 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2592 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2593 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2594 return -EOPNOTSUPP;
2595 }
2596
e3173832
SH		 2597 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2598 hw->ports = 1;
2599 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2600 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2601 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2602 ++hw->ports;
2603 }
2604
2605 return 0;
2606}
2607
2608static void sky2_reset(struct sky2_hw *hw)
2609{
2610 u16 status;
2611 int i;
2612
cd28ab6a 2613 /* disable ASF */
4f44d8ba
SH		 2614 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2615 status = sky2_read16(hw, HCU_CCSR);
2616 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2617 HCU_CCSR_UC_STATE_MSK);
2618 sky2_write16(hw, HCU_CCSR, status);
2619 } else
2620 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2621 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2622
2623 /* do a SW reset */
2624 sky2_write8(hw, B0_CTST, CS_RST_SET);
2625 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2626
2627 /* clear PCI errors, if any */
56a645cc 2628 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2629
cd28ab6a 2630 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2631 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2632
cd28ab6a
SH		 2633
2634 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2635
2636 /* clear any PEX errors */
7bd656d1
SH		 2637 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2638 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2639
cd28ab6a 2640
ae306cca 2641 sky2_power_on(hw);
cd28ab6a
SH		 2642
2643 for (i = 0; i < hw->ports; i++) {
2644 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2645 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2646
2647 if (hw->chip_id == CHIP_ID_YUKON_EX)
2648 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2649 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2650 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2651 }
2652
2653 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2654
793b883e
SH		 2655 /* Clear I2C IRQ noise */
2656 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2657
2658 /* turn off hardware timer (unused) */
2659 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2660 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2661
cd28ab6a
SH		 2662 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2663
69634ee7
SH		 2664 /* Turn off descriptor polling */
2665 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2666
2667 /* Turn off receive timestamp */
2668 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2669 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2670
2671 /* enable the Tx Arbiters */
2672 for (i = 0; i < hw->ports; i++)
2673 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2674
2675 /* Initialize ram interface */
2676 for (i = 0; i < hw->ports; i++) {
793b883e 2677 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2678
2679 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2680 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2681 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2682 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2683 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2684 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2685 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2686 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2687 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2688 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2689 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2690 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2691 }
2692
7bd656d1 2693 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2694
cd28ab6a 2695 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2696 sky2_gmac_reset(hw, i);
cd28ab6a 2697
cd28ab6a
SH		 2698 memset(hw->st_le, 0, STATUS_LE_BYTES);
2699 hw->st_idx = 0;
2700
2701 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2702 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2703
2704 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2705 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2706
2707 /* Set the list last index */
793b883e 2708 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2709
290d4de5
SH		 2710 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2711 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2712
290d4de5
SH		 2713 /* set Status-FIFO ISR watermark */
2714 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2715 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2716 else
2717 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2718
290d4de5 2719 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2720 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2721 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2722
793b883e 2723 /* enable status unit */
cd28ab6a
SH		 2724 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2725
2726 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2727 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2728 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2729}
2730
81906791
SH		 2731static void sky2_restart(struct work_struct *work)
2732{
2733 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2734 struct net_device *dev;
2735 int i, err;
2736
2737 dev_dbg(&hw->pdev->dev, "restarting\n");
2738
2739 del_timer_sync(&hw->idle_timer);
2740
2741 rtnl_lock();
2742 sky2_write32(hw, B0_IMSK, 0);
2743 sky2_read32(hw, B0_IMSK);
2744
2745 netif_poll_disable(hw->dev[0]);
2746
2747 for (i = 0; i < hw->ports; i++) {
2748 dev = hw->dev[i];
2749 if (netif_running(dev))
2750 sky2_down(dev);
2751 }
2752
2753 sky2_reset(hw);
2754 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2755 netif_poll_enable(hw->dev[0]);
2756
2757 for (i = 0; i < hw->ports; i++) {
2758 dev = hw->dev[i];
2759 if (netif_running(dev)) {
2760 err = sky2_up(dev);
2761 if (err) {
2762 printk(KERN_INFO PFX "%s: could not restart %d\n",
2763 dev->name, err);
2764 dev_close(dev);
2765 }
2766 }
2767 }
2768
2769 sky2_idle_start(hw);
2770
2771 rtnl_unlock();
2772}
2773
e3173832
SH		 2774static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2775{
2776 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2777}
2778
2779static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2780{
2781 const struct sky2_port *sky2 = netdev_priv(dev);
2782
2783 wol->supported = sky2_wol_supported(sky2->hw);
2784 wol->wolopts = sky2->wol;
2785}
2786
2787static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2788{
2789 struct sky2_port *sky2 = netdev_priv(dev);
2790 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2791
e3173832
SH		 2792 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2793 return -EOPNOTSUPP;
2794
2795 sky2->wol = wol->wolopts;
2796
69161611 2797 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
e3173832
SH		 2798 sky2_write32(hw, B0_CTST, sky2->wol
2799 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2800
2801 if (!netif_running(dev))
2802 sky2_wol_init(sky2);
cd28ab6a
SH		 2803 return 0;
2804}
2805
28bd181a 2806static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2807{
b89165f2
SH		 2808 if (sky2_is_copper(hw)) {
2809 u32 modes = SUPPORTED_10baseT_Half
2810 | SUPPORTED_10baseT_Full
2811 | SUPPORTED_100baseT_Half
2812 | SUPPORTED_100baseT_Full
2813 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2814
2815 if (hw->chip_id != CHIP_ID_YUKON_FE)
2816 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2817 | SUPPORTED_1000baseT_Full;
2818 return modes;
cd28ab6a 2819 } else
b89165f2
SH		 2820 return SUPPORTED_1000baseT_Half
2821 | SUPPORTED_1000baseT_Full
2822 | SUPPORTED_Autoneg
2823 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2824}
2825
793b883e 2826static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2827{
2828 struct sky2_port *sky2 = netdev_priv(dev);
2829 struct sky2_hw *hw = sky2->hw;
2830
2831 ecmd->transceiver = XCVR_INTERNAL;
2832 ecmd->supported = sky2_supported_modes(hw);
2833 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2834 if (sky2_is_copper(hw)) {
cd28ab6a 2835 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2836 | SUPPORTED_10baseT_Full
2837 | SUPPORTED_100baseT_Half
2838 | SUPPORTED_100baseT_Full
2839 | SUPPORTED_1000baseT_Half
2840 | SUPPORTED_1000baseT_Full
2841 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2842 ecmd->port = PORT_TP;
b89165f2
SH		 2843 ecmd->speed = sky2->speed;
2844 } else {
2845 ecmd->speed = SPEED_1000;
cd28ab6a 2846 ecmd->port = PORT_FIBRE;
b89165f2 2847 }
cd28ab6a
SH		 2848
2849 ecmd->advertising = sky2->advertising;
2850 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2851 ecmd->duplex = sky2->duplex;
2852 return 0;
2853}
2854
2855static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2856{
2857 struct sky2_port *sky2 = netdev_priv(dev);
2858 const struct sky2_hw *hw = sky2->hw;
2859 u32 supported = sky2_supported_modes(hw);
2860
2861 if (ecmd->autoneg == AUTONEG_ENABLE) {
2862 ecmd->advertising = supported;
2863 sky2->duplex = -1;
2864 sky2->speed = -1;
2865 } else {
2866 u32 setting;
2867
793b883e 2868 switch (ecmd->speed) {
cd28ab6a
SH		 2869 case SPEED_1000:
2870 if (ecmd->duplex == DUPLEX_FULL)
2871 setting = SUPPORTED_1000baseT_Full;
2872 else if (ecmd->duplex == DUPLEX_HALF)
2873 setting = SUPPORTED_1000baseT_Half;
2874 else
2875 return -EINVAL;
2876 break;
2877 case SPEED_100:
2878 if (ecmd->duplex == DUPLEX_FULL)
2879 setting = SUPPORTED_100baseT_Full;
2880 else if (ecmd->duplex == DUPLEX_HALF)
2881 setting = SUPPORTED_100baseT_Half;
2882 else
2883 return -EINVAL;
2884 break;
2885
2886 case SPEED_10:
2887 if (ecmd->duplex == DUPLEX_FULL)
2888 setting = SUPPORTED_10baseT_Full;
2889 else if (ecmd->duplex == DUPLEX_HALF)
2890 setting = SUPPORTED_10baseT_Half;
2891 else
2892 return -EINVAL;
2893 break;
2894 default:
2895 return -EINVAL;
2896 }
2897
2898 if ((setting & supported) == 0)
2899 return -EINVAL;
2900
2901 sky2->speed = ecmd->speed;
2902 sky2->duplex = ecmd->duplex;
2903 }
2904
2905 sky2->autoneg = ecmd->autoneg;
2906 sky2->advertising = ecmd->advertising;
2907
1b537565
SH		 2908 if (netif_running(dev))
2909 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2910
2911 return 0;
2912}
2913
2914static void sky2_get_drvinfo(struct net_device *dev,
2915 struct ethtool_drvinfo *info)
2916{
2917 struct sky2_port *sky2 = netdev_priv(dev);
2918
2919 strcpy(info->driver, DRV_NAME);
2920 strcpy(info->version, DRV_VERSION);
2921 strcpy(info->fw_version, "N/A");
2922 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2923}
2924
2925static const struct sky2_stat {
793b883e
SH		 2926 char name[ETH_GSTRING_LEN];
2927 u16 offset;
cd28ab6a
SH		 2928} sky2_stats[] = {
2929 { "tx_bytes", GM_TXO_OK_HI },
2930 { "rx_bytes", GM_RXO_OK_HI },
2931 { "tx_broadcast", GM_TXF_BC_OK },
2932 { "rx_broadcast", GM_RXF_BC_OK },
2933 { "tx_multicast", GM_TXF_MC_OK },
2934 { "rx_multicast", GM_RXF_MC_OK },
2935 { "tx_unicast", GM_TXF_UC_OK },
2936 { "rx_unicast", GM_RXF_UC_OK },
2937 { "tx_mac_pause", GM_TXF_MPAUSE },
2938 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2939 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2940 { "late_collision",GM_TXF_LAT_COL },
2941 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2942 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2943 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2944
d2604540 2945 { "rx_short", GM_RXF_SHT },
cd28ab6a 2946 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2947 { "rx_64_byte_packets", GM_RXF_64B },
2948 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2949 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2950 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2951 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2952 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2953 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2954 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2955 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2956 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2957 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2958
2959 { "tx_64_byte_packets", GM_TXF_64B },
2960 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2961 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2962 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2963 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2964 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2965 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2966 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2967};
2968
cd28ab6a
SH		 2969static u32 sky2_get_rx_csum(struct net_device *dev)
2970{
2971 struct sky2_port *sky2 = netdev_priv(dev);
2972
2973 return sky2->rx_csum;
2974}
2975
2976static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2977{
2978 struct sky2_port *sky2 = netdev_priv(dev);
2979
2980 sky2->rx_csum = data;
793b883e 2981
cd28ab6a
SH		 2982 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2983 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2984
2985 return 0;
2986}
2987
2988static u32 sky2_get_msglevel(struct net_device *netdev)
2989{
2990 struct sky2_port *sky2 = netdev_priv(netdev);
2991 return sky2->msg_enable;
2992}
2993
9a7ae0a9
SH		 2994static int sky2_nway_reset(struct net_device *dev)
2995{
2996 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2997
16ad91e1 2998 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2999 return -EINVAL;
3000
1b537565 3001 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 3002
3003 return 0;
3004}
3005
793b883e 3006static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3007{
3008 struct sky2_hw *hw = sky2->hw;
3009 unsigned port = sky2->port;
3010 int i;
3011
3012 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3013 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3014 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3015 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3016
793b883e 3017 for (i = 2; i < count; i++)
cd28ab6a
SH		 3018 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3019}
3020
cd28ab6a
SH		 3021static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3022{
3023 struct sky2_port *sky2 = netdev_priv(netdev);
3024 sky2->msg_enable = value;
3025}
3026
3027static int sky2_get_stats_count(struct net_device *dev)
3028{
3029 return ARRAY_SIZE(sky2_stats);
3030}
3031
3032static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3033 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3034{
3035 struct sky2_port *sky2 = netdev_priv(dev);
3036
793b883e 3037 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3038}
3039
793b883e 3040static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3041{
3042 int i;
3043
3044 switch (stringset) {
3045 case ETH_SS_STATS:
3046 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3047 memcpy(data + i * ETH_GSTRING_LEN,
3048 sky2_stats[i].name, ETH_GSTRING_LEN);
3049 break;
3050 }
3051}
3052
cd28ab6a
SH		 3053static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3054{
3055 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3056 return &sky2->net_stats;
3057}
3058
3059static int sky2_set_mac_address(struct net_device *dev, void *p)
3060{
3061 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3062 struct sky2_hw *hw = sky2->hw;
3063 unsigned port = sky2->port;
3064 const struct sockaddr *addr = p;
cd28ab6a
SH		 3065
3066 if (!is_valid_ether_addr(addr->sa_data))
3067 return -EADDRNOTAVAIL;
3068
cd28ab6a 3069 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3070 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3071 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3072 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3073 dev->dev_addr, ETH_ALEN);
1b537565 3074
a8ab1ec0
SH		 3075 /* virtual address for data */
3076 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3077
3078 /* physical address: used for pause frames */
3079 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3080
3081 return 0;
cd28ab6a
SH		 3082}
3083
a052b52f
SH		 3084static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3085{
3086 u32 bit;
3087
3088 bit = ether_crc(ETH_ALEN, addr) & 63;
3089 filter[bit >> 3] |= 1 << (bit & 7);
3090}
3091
cd28ab6a
SH		 3092static void sky2_set_multicast(struct net_device *dev)
3093{
3094 struct sky2_port *sky2 = netdev_priv(dev);
3095 struct sky2_hw *hw = sky2->hw;
3096 unsigned port = sky2->port;
3097 struct dev_mc_list *list = dev->mc_list;
3098 u16 reg;
3099 u8 filter[8];
a052b52f
SH		 3100 int rx_pause;
3101 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3102
a052b52f 3103 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3104 memset(filter, 0, sizeof(filter));
3105
3106 reg = gma_read16(hw, port, GM_RX_CTRL);
3107 reg |= GM_RXCR_UCF_ENA;
3108
d571b694 3109 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3110 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3111 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3112 memset(filter, 0xff, sizeof(filter));
a052b52f 3113 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3114 reg &= ~GM_RXCR_MCF_ENA;
3115 else {
3116 int i;
3117 reg |= GM_RXCR_MCF_ENA;
3118
a052b52f
SH		 3119 if (rx_pause)
3120 sky2_add_filter(filter, pause_mc_addr);
3121
3122 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3123 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3124 }
3125
cd28ab6a 3126 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3127 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3128 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3129 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3130 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3131 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3132 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3133 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3134
3135 gma_write16(hw, port, GM_RX_CTRL, reg);
3136}
3137
3138/* Can have one global because blinking is controlled by
3139 * ethtool and that is always under RTNL mutex
3140 */
91c86df5 3141static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3142{
793b883e
SH		 3143 u16 pg;
3144
793b883e
SH		 3145 switch (hw->chip_id) {
3146 case CHIP_ID_YUKON_XL:
3147 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3148 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3149 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3150 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3151 PHY_M_LEDC_INIT_CTRL(7) |
3152 PHY_M_LEDC_STA1_CTRL(7) |
3153 PHY_M_LEDC_STA0_CTRL(7))
3154 : 0);
3155
3156 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3157 break;
3158
3159 default:
3160 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3161 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3162 on ? PHY_M_LED_ALL : 0);
793b883e 3163 }
cd28ab6a
SH		 3164}
3165
3166/* blink LED's for finding board */
3167static int sky2_phys_id(struct net_device *dev, u32 data)
3168{
3169 struct sky2_port *sky2 = netdev_priv(dev);
3170 struct sky2_hw *hw = sky2->hw;
3171 unsigned port = sky2->port;
793b883e 3172 u16 ledctrl, ledover = 0;
cd28ab6a 3173 long ms;
91c86df5 3174 int interrupted;
cd28ab6a
SH		 3175 int onoff = 1;
3176
793b883e 3177 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3178 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3179 else
3180 ms = data * 1000;
3181
3182 /* save initial values */
e07b1aa8 3183 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3184 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3185 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3186 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3187 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3188 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3189 } else {
3190 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3191 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3192 }
cd28ab6a 3193
91c86df5
SH		 3194 interrupted = 0;
3195 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3196 sky2_led(hw, port, onoff);
3197 onoff = !onoff;
3198
e07b1aa8 3199 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3200 interrupted = msleep_interruptible(250);
e07b1aa8 3201 spin_lock_bh(&sky2->phy_lock);
91c86df5 3202
cd28ab6a
SH		 3203 ms -= 250;
3204 }
3205
3206 /* resume regularly scheduled programming */
793b883e
SH		 3207 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3208 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3209 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3210 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3211 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3212 } else {
3213 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3214 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3215 }
e07b1aa8 3216 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3217
3218 return 0;
3219}
3220
3221static void sky2_get_pauseparam(struct net_device *dev,
3222 struct ethtool_pauseparam *ecmd)
3223{
3224 struct sky2_port *sky2 = netdev_priv(dev);
3225
16ad91e1
SH		 3226 switch (sky2->flow_mode) {
3227 case FC_NONE:
3228 ecmd->tx_pause = ecmd->rx_pause = 0;
3229 break;
3230 case FC_TX:
3231 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3232 break;
3233 case FC_RX:
3234 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3235 break;
3236 case FC_BOTH:
3237 ecmd->tx_pause = ecmd->rx_pause = 1;
3238 }
3239
cd28ab6a
SH		 3240 ecmd->autoneg = sky2->autoneg;
3241}
3242
3243static int sky2_set_pauseparam(struct net_device *dev,
3244 struct ethtool_pauseparam *ecmd)
3245{
3246 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3247
3248 sky2->autoneg = ecmd->autoneg;
16ad91e1 3249 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3250
16ad91e1
SH		 3251 if (netif_running(dev))
3252 sky2_phy_reinit(sky2);
cd28ab6a 3253
2eaba1a2 3254 return 0;
cd28ab6a
SH		 3255}
3256
fb17358f
SH		 3257static int sky2_get_coalesce(struct net_device *dev,
3258 struct ethtool_coalesce *ecmd)
3259{
3260 struct sky2_port *sky2 = netdev_priv(dev);
3261 struct sky2_hw *hw = sky2->hw;
3262
3263 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3264 ecmd->tx_coalesce_usecs = 0;
3265 else {
3266 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3267 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3268 }
3269 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3270
3271 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3272 ecmd->rx_coalesce_usecs = 0;
3273 else {
3274 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3275 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3276 }
3277 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3278
3279 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3280 ecmd->rx_coalesce_usecs_irq = 0;
3281 else {
3282 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3283 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3284 }
3285
3286 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3287
3288 return 0;
3289}
3290
3291/* Note: this affect both ports */
3292static int sky2_set_coalesce(struct net_device *dev,
3293 struct ethtool_coalesce *ecmd)
3294{
3295 struct sky2_port *sky2 = netdev_priv(dev);
3296 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3297 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3298
77b3d6a2
SH		 3299 if (ecmd->tx_coalesce_usecs > tmax ||
3300 ecmd->rx_coalesce_usecs > tmax ||
3301 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3302 return -EINVAL;
3303
ff81fbbe 3304 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3305 return -EINVAL;
ff81fbbe 3306 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3307 return -EINVAL;
ff81fbbe 3308 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3309 return -EINVAL;
3310
3311 if (ecmd->tx_coalesce_usecs == 0)
3312 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3313 else {
3314 sky2_write32(hw, STAT_TX_TIMER_INI,
3315 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3316 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3317 }
3318 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3319
3320 if (ecmd->rx_coalesce_usecs == 0)
3321 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3322 else {
3323 sky2_write32(hw, STAT_LEV_TIMER_INI,
3324 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3325 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3326 }
3327 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3328
3329 if (ecmd->rx_coalesce_usecs_irq == 0)
3330 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3331 else {
d28d4870 3332 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3333 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3334 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3335 }
3336 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3337 return 0;
3338}
3339
793b883e
SH		 3340static void sky2_get_ringparam(struct net_device *dev,
3341 struct ethtool_ringparam *ering)
3342{
3343 struct sky2_port *sky2 = netdev_priv(dev);
3344
3345 ering->rx_max_pending = RX_MAX_PENDING;
3346 ering->rx_mini_max_pending = 0;
3347 ering->rx_jumbo_max_pending = 0;
3348 ering->tx_max_pending = TX_RING_SIZE - 1;
3349
3350 ering->rx_pending = sky2->rx_pending;
3351 ering->rx_mini_pending = 0;
3352 ering->rx_jumbo_pending = 0;
3353 ering->tx_pending = sky2->tx_pending;
3354}
3355
3356static int sky2_set_ringparam(struct net_device *dev,
3357 struct ethtool_ringparam *ering)
3358{
3359 struct sky2_port *sky2 = netdev_priv(dev);
3360 int err = 0;
3361
3362 if (ering->rx_pending > RX_MAX_PENDING ||
3363 ering->rx_pending < 8 ||
3364 ering->tx_pending < MAX_SKB_TX_LE ||
3365 ering->tx_pending > TX_RING_SIZE - 1)
3366 return -EINVAL;
3367
3368 if (netif_running(dev))
3369 sky2_down(dev);
3370
3371 sky2->rx_pending = ering->rx_pending;
3372 sky2->tx_pending = ering->tx_pending;
3373
1b537565 3374 if (netif_running(dev)) {
793b883e 3375 err = sky2_up(dev);
1b537565
SH		 3376 if (err)
3377 dev_close(dev);
6ed995bb
SH		 3378 else
3379 sky2_set_multicast(dev);
1b537565 3380 }
793b883e
SH		 3381
3382 return err;
3383}
3384
793b883e
SH		 3385static int sky2_get_regs_len(struct net_device *dev)
3386{
6e4cbb34 3387 return 0x4000;
793b883e
SH		 3388}
3389
3390/*
3391 * Returns copy of control register region
3ead5db7 3392 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3393 */
3394static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3395 void *p)
3396{
3397 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3398 const void __iomem *io = sky2->hw->regs;
793b883e
SH		 3399
3400 regs->version = 1;
6e4cbb34 3401 memset(p, 0, regs->len);
793b883e 3402
6e4cbb34
SH		 3403 memcpy_fromio(p, io, B3_RAM_ADDR);
3404
3ead5db7
SH		 3405 /* skip diagnostic ram region */
3406 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3407
3408 /* copy GMAC registers */
3409 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3410 if (sky2->hw->ports > 1)
3411 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3412
793b883e 3413}
cd28ab6a 3414
b628ed98
SH		 3415/* In order to do Jumbo packets on these chips, need to turn off the
3416 * transmit store/forward. Therefore checksum offload won't work.
3417 */
3418static int no_tx_offload(struct net_device *dev)
3419{
3420 const struct sky2_port *sky2 = netdev_priv(dev);
3421 const struct sky2_hw *hw = sky2->hw;
3422
69161611 3423 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3424}
3425
3426static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3427{
3428 if (data && no_tx_offload(dev))
3429 return -EINVAL;
3430
3431 return ethtool_op_set_tx_csum(dev, data);
3432}
3433
3434
3435static int sky2_set_tso(struct net_device *dev, u32 data)
3436{
3437 if (data && no_tx_offload(dev))
3438 return -EINVAL;
3439
3440 return ethtool_op_set_tso(dev, data);
3441}
3442
f4331a6d
SH		 3443static int sky2_get_eeprom_len(struct net_device *dev)
3444{
3445 struct sky2_port *sky2 = netdev_priv(dev);
3446 u16 reg2;
3447
3448 reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
3449 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3450}
3451
3452static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3453{
3454 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3455
3456 while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
3457 cpu_relax();
3458 return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3459}
3460
3461static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3462{
3463 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3464 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3465 do {
3466 cpu_relax();
3467 } while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
3468}
3469
3470static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3471 u8 *data)
3472{
3473 struct sky2_port *sky2 = netdev_priv(dev);
3474 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3475 int length = eeprom->len;
3476 u16 offset = eeprom->offset;
3477
3478 if (!cap)
3479 return -EINVAL;
3480
3481 eeprom->magic = SKY2_EEPROM_MAGIC;
3482
3483 while (length > 0) {
3484 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3485 int n = min_t(int, length, sizeof(val));
3486
3487 memcpy(data, &val, n);
3488 length -= n;
3489 data += n;
3490 offset += n;
3491 }
3492 return 0;
3493}
3494
3495static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3496 u8 *data)
3497{
3498 struct sky2_port *sky2 = netdev_priv(dev);
3499 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3500 int length = eeprom->len;
3501 u16 offset = eeprom->offset;
3502
3503 if (!cap)
3504 return -EINVAL;
3505
3506 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3507 return -EINVAL;
3508
3509 while (length > 0) {
3510 u32 val;
3511 int n = min_t(int, length, sizeof(val));
3512
3513 if (n < sizeof(val))
3514 val = sky2_vpd_read(sky2->hw, cap, offset);
3515 memcpy(&val, data, n);
3516
3517 sky2_vpd_write(sky2->hw, cap, offset, val);
3518
3519 length -= n;
3520 data += n;
3521 offset += n;
3522 }
3523 return 0;
3524}
3525
3526
7282d491 3527static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3528 .get_settings = sky2_get_settings,
3529 .set_settings = sky2_set_settings,
3530 .get_drvinfo = sky2_get_drvinfo,
3531 .get_wol = sky2_get_wol,
3532 .set_wol = sky2_set_wol,
3533 .get_msglevel = sky2_get_msglevel,
3534 .set_msglevel = sky2_set_msglevel,
3535 .nway_reset = sky2_nway_reset,
3536 .get_regs_len = sky2_get_regs_len,
3537 .get_regs = sky2_get_regs,
3538 .get_link = ethtool_op_get_link,
3539 .get_eeprom_len = sky2_get_eeprom_len,
3540 .get_eeprom = sky2_get_eeprom,
3541 .set_eeprom = sky2_set_eeprom,
3542 .get_sg = ethtool_op_get_sg,
3543 .set_sg = ethtool_op_set_sg,
3544 .get_tx_csum = ethtool_op_get_tx_csum,
3545 .set_tx_csum = sky2_set_tx_csum,
3546 .get_tso = ethtool_op_get_tso,
3547 .set_tso = sky2_set_tso,
3548 .get_rx_csum = sky2_get_rx_csum,
3549 .set_rx_csum = sky2_set_rx_csum,
3550 .get_strings = sky2_get_strings,
3551 .get_coalesce = sky2_get_coalesce,
3552 .set_coalesce = sky2_set_coalesce,
3553 .get_ringparam = sky2_get_ringparam,
3554 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3555 .get_pauseparam = sky2_get_pauseparam,
3556 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3557 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3558 .get_stats_count = sky2_get_stats_count,
3559 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3560 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3561};
3562
3cf26753
SH		 3563#ifdef CONFIG_SKY2_DEBUG
3564
3565static struct dentry *sky2_debug;
3566
3567static int sky2_debug_show(struct seq_file *seq, void *v)
3568{
3569 struct net_device *dev = seq->private;
3570 const struct sky2_port *sky2 = netdev_priv(dev);
3571 const struct sky2_hw *hw = sky2->hw;
3572 unsigned port = sky2->port;
3573 unsigned idx, last;
3574 int sop;
3575
3576 if (!netif_running(dev))
3577 return -ENETDOWN;
3578
3579 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3580 sky2_read32(hw, B0_ISRC),
3581 sky2_read32(hw, B0_IMSK),
3582 sky2_read32(hw, B0_Y2_SP_ICR));
3583
3584 netif_poll_disable(hw->dev[0]);
3585 last = sky2_read16(hw, STAT_PUT_IDX);
3586
3587 if (hw->st_idx == last)
3588 seq_puts(seq, "Status ring (empty)\n");
3589 else {
3590 seq_puts(seq, "Status ring\n");
3591 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3592 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3593 const struct sky2_status_le *le = hw->st_le + idx;
3594 seq_printf(seq, "[%d] %#x %d %#x\n",
3595 idx, le->opcode, le->length, le->status);
3596 }
3597 seq_puts(seq, "\n");
3598 }
3599
3600 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3601 sky2->tx_cons, sky2->tx_prod,
3602 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3603 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3604
3605 /* Dump contents of tx ring */
3606 sop = 1;
3607 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3608 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3609 const struct sky2_tx_le *le = sky2->tx_le + idx;
3610 u32 a = le32_to_cpu(le->addr);
3611
3612 if (sop)
3613 seq_printf(seq, "%u:", idx);
3614 sop = 0;
3615
3616 switch(le->opcode & ~HW_OWNER) {
3617 case OP_ADDR64:
3618 seq_printf(seq, " %#x:", a);
3619 break;
3620 case OP_LRGLEN:
3621 seq_printf(seq, " mtu=%d", a);
3622 break;
3623 case OP_VLAN:
3624 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3625 break;
3626 case OP_TCPLISW:
3627 seq_printf(seq, " csum=%#x", a);
3628 break;
3629 case OP_LARGESEND:
3630 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3631 break;
3632 case OP_PACKET:
3633 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3634 break;
3635 case OP_BUFFER:
3636 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3637 break;
3638 default:
3639 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3640 a, le16_to_cpu(le->length));
3641 }
3642
3643 if (le->ctrl & EOP) {
3644 seq_putc(seq, '\n');
3645 sop = 1;
3646 }
3647 }
3648
3649 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3650 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3651 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3652 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3653
3654 netif_poll_enable(hw->dev[0]);
3655 return 0;
3656}
3657
3658static int sky2_debug_open(struct inode *inode, struct file *file)
3659{
3660 return single_open(file, sky2_debug_show, inode->i_private);
3661}
3662
3663static const struct file_operations sky2_debug_fops = {
3664 .owner = THIS_MODULE,
3665 .open = sky2_debug_open,
3666 .read = seq_read,
3667 .llseek = seq_lseek,
3668 .release = single_release,
3669};
3670
3671/*
3672 * Use network device events to create/remove/rename
3673 * debugfs file entries
3674 */
3675static int sky2_device_event(struct notifier_block *unused,
3676 unsigned long event, void *ptr)
3677{
3678 struct net_device *dev = ptr;
3679
3680 if (dev->open == sky2_up) {
3681 struct sky2_port *sky2 = netdev_priv(dev);
3682
3683 switch(event) {
3684 case NETDEV_CHANGENAME:
3685 if (!netif_running(dev))
3686 break;
3687 /* fallthrough */
3688 case NETDEV_DOWN:
3689 case NETDEV_GOING_DOWN:
3690 if (sky2->debugfs) {
3691 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3692 dev->name);
3693 debugfs_remove(sky2->debugfs);
3694 sky2->debugfs = NULL;
3695 }
3696
3697 if (event != NETDEV_CHANGENAME)
3698 break;
3699 /* fallthrough for changename */
3700 case NETDEV_UP:
3701 if (sky2_debug) {
3702 struct dentry *d;
3703 d = debugfs_create_file(dev->name, S_IRUGO,
3704 sky2_debug, dev,
3705 &sky2_debug_fops);
3706 if (d == NULL || IS_ERR(d))
3707 printk(KERN_INFO PFX
3708 "%s: debugfs create failed\n",
3709 dev->name);
3710 else
3711 sky2->debugfs = d;
3712 }
3713 break;
3714 }
3715 }
3716
3717 return NOTIFY_DONE;
3718}
3719
3720static struct notifier_block sky2_notifier = {
3721 .notifier_call = sky2_device_event,
3722};
3723
3724
3725static __init void sky2_debug_init(void)
3726{
3727 struct dentry *ent;
3728
3729 ent = debugfs_create_dir("sky2", NULL);
3730 if (!ent || IS_ERR(ent))
3731 return;
3732
3733 sky2_debug = ent;
3734 register_netdevice_notifier(&sky2_notifier);
3735}
3736
3737static __exit void sky2_debug_cleanup(void)
3738{
3739 if (sky2_debug) {
3740 unregister_netdevice_notifier(&sky2_notifier);
3741 debugfs_remove(sky2_debug);
3742 sky2_debug = NULL;
3743 }
3744}
3745
3746#else
3747#define sky2_debug_init()
3748#define sky2_debug_cleanup()
3749#endif
3750
3751
cd28ab6a
SH		 3752/* Initialize network device */
3753static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3754 unsigned port,
3755 int highmem, int wol)
cd28ab6a
SH		 3756{
3757 struct sky2_port *sky2;
3758 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3759
3760 if (!dev) {
b02a9258 3761 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3762 return NULL;
3763 }
3764
3765 SET_MODULE_OWNER(dev);
3766 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3767 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3768 dev->open = sky2_up;
3769 dev->stop = sky2_down;
ef743d33 3770 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3771 dev->hard_start_xmit = sky2_xmit_frame;
3772 dev->get_stats = sky2_get_stats;
3773 dev->set_multicast_list = sky2_set_multicast;
3774 dev->set_mac_address = sky2_set_mac_address;
3775 dev->change_mtu = sky2_change_mtu;
3776 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3777 dev->tx_timeout = sky2_tx_timeout;
3778 dev->watchdog_timeo = TX_WATCHDOG;
3779 if (port == 0)
3780 dev->poll = sky2_poll;
3781 dev->weight = NAPI_WEIGHT;
3782#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3783 /* Network console (only works on port 0)
3784 * because netpoll makes assumptions about NAPI
3785 */
3786 if (port == 0)
3787 dev->poll_controller = sky2_netpoll;
cd28ab6a 3788#endif
cd28ab6a
SH		 3789
3790 sky2 = netdev_priv(dev);
3791 sky2->netdev = dev;
3792 sky2->hw = hw;
3793 sky2->msg_enable = netif_msg_init(debug, default_msg);
3794
cd28ab6a
SH		 3795 /* Auto speed and flow control */
3796 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3797 sky2->flow_mode = FC_BOTH;
3798
cd28ab6a
SH		 3799 sky2->duplex = -1;
3800 sky2->speed = -1;
3801 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3802 sky2->rx_csum = 1;
e3173832 3803 sky2->wol = wol;
75d070c5 3804
e07b1aa8 3805 spin_lock_init(&sky2->phy_lock);
793b883e 3806 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3807 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3808
3809 hw->dev[port] = dev;
3810
3811 sky2->port = port;
3812
4a50a876 3813 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3814 if (highmem)
3815 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3816
d1f13708
SH		 3817#ifdef SKY2_VLAN_TAG_USED
3818 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3819 dev->vlan_rx_register = sky2_vlan_rx_register;
d1f13708
SH		 3820#endif
3821
cd28ab6a 3822 /* read the mac address */
793b883e 3823 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3824 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 3825
cd28ab6a
SH		 3826 return dev;
3827}
3828
28bd181a 3829static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3830{
3831 const struct sky2_port *sky2 = netdev_priv(dev);
3832
3833 if (netif_msg_probe(sky2))
3834 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3835 dev->name,
3836 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3837 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3838}
3839
fb2690a9 3840/* Handle software interrupt used during MSI test */
7d12e780 3841static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3842{
3843 struct sky2_hw *hw = dev_id;
3844 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3845
3846 if (status == 0)
3847 return IRQ_NONE;
3848
3849 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3850 hw->msi = 1;
fb2690a9
SH		 3851 wake_up(&hw->msi_wait);
3852 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3853 }
3854 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3855
3856 return IRQ_HANDLED;
3857}
3858
3859/* Test interrupt path by forcing a a software IRQ */
3860static int __devinit sky2_test_msi(struct sky2_hw *hw)
3861{
3862 struct pci_dev *pdev = hw->pdev;
3863 int err;
3864
bb507fe1
SH		 3865 init_waitqueue_head (&hw->msi_wait);
3866
fb2690a9
SH		 3867 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3868
b0a20ded 3869 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3870 if (err) {
b02a9258 3871 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3872 return err;
3873 }
3874
fb2690a9 3875 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3876 sky2_read8(hw, B0_CTST);
fb2690a9 3877
b0a20ded 3878 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3879
b0a20ded 3880 if (!hw->msi) {
fb2690a9 3881 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3882 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3883 "switching to INTx mode.\n");
fb2690a9
SH		 3884
3885 err = -EOPNOTSUPP;
3886 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3887 }
3888
3889 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3890 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3891
3892 free_irq(pdev->irq, hw);
3893
3894 return err;
3895}
3896
e3173832
SH		 3897static int __devinit pci_wake_enabled(struct pci_dev *dev)
3898{
3899 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3900 u16 value;
3901
3902 if (!pm)
3903 return 0;
3904 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3905 return 0;
3906 return value & PCI_PM_CTRL_PME_ENABLE;
3907}
3908
cd28ab6a
SH		 3909static int __devinit sky2_probe(struct pci_dev *pdev,
3910 const struct pci_device_id *ent)
3911{
7f60c64b 3912 struct net_device *dev;
cd28ab6a 3913 struct sky2_hw *hw;
e3173832 3914 int err, using_dac = 0, wol_default;
cd28ab6a 3915
793b883e
SH		 3916 err = pci_enable_device(pdev);
3917 if (err) {
b02a9258 3918 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3919 goto err_out;
3920 }
3921
793b883e
SH		 3922 err = pci_request_regions(pdev, DRV_NAME);
3923 if (err) {
b02a9258 3924 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 3925 goto err_out_disable;
cd28ab6a
SH		 3926 }
3927
3928 pci_set_master(pdev);
3929
d1f3d4dd
SH		 3930 if (sizeof(dma_addr_t) > sizeof(u32) &&
3931 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3932 using_dac = 1;
3933 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3934 if (err < 0) {
b02a9258
SH		 3935 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3936 "for consistent allocations\n");
d1f3d4dd
SH		 3937 goto err_out_free_regions;
3938 }
d1f3d4dd 3939 } else {
cd28ab6a
SH		 3940 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3941 if (err) {
b02a9258 3942 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3943 goto err_out_free_regions;
3944 }
3945 }
d1f3d4dd 3946
e3173832
SH		 3947 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3948
cd28ab6a 3949 err = -ENOMEM;
6aad85d6 3950 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3951 if (!hw) {
b02a9258 3952 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3953 goto err_out_free_regions;
3954 }
3955
cd28ab6a 3956 hw->pdev = pdev;
cd28ab6a
SH		 3957
3958 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3959 if (!hw->regs) {
b02a9258 3960 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3961 goto err_out_free_hw;
3962 }
3963
56a645cc 3964#ifdef __BIG_ENDIAN
f65b138c
SH		 3965 /* The sk98lin vendor driver uses hardware byte swapping but
3966 * this driver uses software swapping.
3967 */
56a645cc
SH		 3968 {
3969 u32 reg;
56a645cc 3970 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3971 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3972 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3973 }
3974#endif
3975
08c06d8a
SH		 3976 /* ring for status responses */
3977 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3978 &hw->st_dma);
3979 if (!hw->st_le)
3980 goto err_out_iounmap;
3981
e3173832 3982 err = sky2_init(hw);
cd28ab6a 3983 if (err)
793b883e 3984 goto err_out_iounmap;
cd28ab6a 3985
b02a9258 3986 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3987 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3988 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3989 hw->chip_id, hw->chip_rev);
cd28ab6a 3990
e3173832
SH		 3991 sky2_reset(hw);
3992
3993 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3994 if (!dev) {
3995 err = -ENOMEM;
cd28ab6a 3996 goto err_out_free_pci;
7f60c64b 3997 }
cd28ab6a 3998
9fa1b1f3
SH		 3999 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4000 err = sky2_test_msi(hw);
4001 if (err == -EOPNOTSUPP)
4002 pci_disable_msi(pdev);
4003 else if (err)
4004 goto err_out_free_netdev;
4005 }
4006
793b883e
SH		 4007 err = register_netdev(dev);
4008 if (err) {
b02a9258 4009 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4010 goto err_out_free_netdev;
4011 }
4012
b0a20ded
SH		 4013 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
4014 dev->name, hw);
9fa1b1f3 4015 if (err) {
b02a9258 4016 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4017 goto err_out_unregister;
4018 }
4019 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4020
cd28ab6a
SH		 4021 sky2_show_addr(dev);
4022
7f60c64b 4023 if (hw->ports > 1) {
4024 struct net_device *dev1;
4025
e3173832 4026 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4027 if (!dev1)
4028 dev_warn(&pdev->dev, "allocation for second device failed\n");
4029 else if ((err = register_netdev(dev1))) {
4030 dev_warn(&pdev->dev,
4031 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4032 hw->dev[1] = NULL;
4033 free_netdev(dev1);
b02a9258
SH		 4034 } else
4035 sky2_show_addr(dev1);
cd28ab6a
SH		 4036 }
4037
01bd7564 4038 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
81906791
SH		 4039 INIT_WORK(&hw->restart_work, sky2_restart);
4040
eb35cf60 4041 sky2_idle_start(hw);
d27ed387 4042
793b883e
SH		 4043 pci_set_drvdata(pdev, hw);
4044
cd28ab6a
SH		 4045 return 0;
4046
793b883e 4047err_out_unregister:
b0a20ded
SH		 4048 if (hw->msi)
4049 pci_disable_msi(pdev);
793b883e 4050 unregister_netdev(dev);
cd28ab6a
SH		 4051err_out_free_netdev:
4052 free_netdev(dev);
cd28ab6a 4053err_out_free_pci:
793b883e 4054 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4055 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4056err_out_iounmap:
4057 iounmap(hw->regs);
4058err_out_free_hw:
4059 kfree(hw);
4060err_out_free_regions:
4061 pci_release_regions(pdev);
44a1d2e5 4062err_out_disable:
cd28ab6a 4063 pci_disable_device(pdev);
cd28ab6a 4064err_out:
549a68c3 4065 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4066 return err;
4067}
4068
4069static void __devexit sky2_remove(struct pci_dev *pdev)
4070{
793b883e 4071 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 4072 struct net_device *dev0, *dev1;
4073
793b883e 4074 if (!hw)
cd28ab6a
SH		 4075 return;
4076
d27ed387
SH		 4077 del_timer_sync(&hw->idle_timer);
4078
81906791
SH		 4079 flush_scheduled_work();
4080
d27ed387 4081 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 4082 synchronize_irq(hw->pdev->irq);
4083
cd28ab6a 4084 dev0 = hw->dev[0];
793b883e
SH		 4085 dev1 = hw->dev[1];
4086 if (dev1)
4087 unregister_netdev(dev1);
cd28ab6a
SH		 4088 unregister_netdev(dev0);
4089
ae306cca
SH		 4090 sky2_power_aux(hw);
4091
cd28ab6a 4092 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4093 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4094 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4095
4096 free_irq(pdev->irq, hw);
b0a20ded
SH		 4097 if (hw->msi)
4098 pci_disable_msi(pdev);
793b883e 4099 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4100 pci_release_regions(pdev);
4101 pci_disable_device(pdev);
793b883e 4102
cd28ab6a
SH		 4103 if (dev1)
4104 free_netdev(dev1);
4105 free_netdev(dev0);
4106 iounmap(hw->regs);
4107 kfree(hw);
5afa0a9c 4108
cd28ab6a
SH		 4109 pci_set_drvdata(pdev, NULL);
4110}
4111
4112#ifdef CONFIG_PM
4113static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4114{
793b883e 4115 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4116 int i, wol = 0;
cd28ab6a 4117
549a68c3
SH		 4118 if (!hw)
4119 return 0;
4120
eb35cf60 4121 del_timer_sync(&hw->idle_timer);
6a5706b9 4122 netif_poll_disable(hw->dev[0]);
eb35cf60 4123
f05267e7 4124 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4125 struct net_device *dev = hw->dev[i];
e3173832 4126 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4127
e3173832 4128 if (netif_running(dev))
5afa0a9c 4129 sky2_down(dev);
e3173832
SH		 4130
4131 if (sky2->wol)
4132 sky2_wol_init(sky2);
4133
4134 wol |= sky2->wol;
cd28ab6a
SH		 4135 }
4136
8ab8fca2 4137 sky2_write32(hw, B0_IMSK, 0);
ae306cca 4138 sky2_power_aux(hw);
e3173832 4139
d374c1c1 4140 pci_save_state(pdev);
e3173832 4141 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4142 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4143
2ccc99b7 4144 return 0;
cd28ab6a
SH		 4145}
4146
4147static int sky2_resume(struct pci_dev *pdev)
4148{
793b883e 4149 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4150 int i, err;
cd28ab6a 4151
549a68c3
SH		 4152 if (!hw)
4153 return 0;
4154
ae306cca
SH		 4155 err = pci_set_power_state(pdev, PCI_D0);
4156 if (err)
4157 goto out;
4158
4159 err = pci_restore_state(pdev);
4160 if (err)
4161 goto out;
4162
cd28ab6a 4163 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4164
4165 /* Re-enable all clocks */
4166 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
4167 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4168
e3173832 4169 sky2_reset(hw);
cd28ab6a 4170
8ab8fca2
SH		 4171 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4172
f05267e7 4173 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4174 struct net_device *dev = hw->dev[i];
6a5706b9 4175 if (netif_running(dev)) {
08c06d8a
SH		 4176 err = sky2_up(dev);
4177 if (err) {
4178 printk(KERN_ERR PFX "%s: could not up: %d\n",
4179 dev->name, err);
4180 dev_close(dev);
eb35cf60 4181 goto out;
5afa0a9c 4182 }
cd28ab6a
SH		 4183 }
4184 }
eb35cf60 4185
6a5706b9 4186 netif_poll_enable(hw->dev[0]);
eb35cf60 4187 sky2_idle_start(hw);
ae306cca 4188 return 0;
08c06d8a 4189out:
b02a9258 4190 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4191 pci_disable_device(pdev);
08c06d8a 4192 return err;
cd28ab6a
SH		 4193}
4194#endif
4195
e3173832
SH		 4196static void sky2_shutdown(struct pci_dev *pdev)
4197{
4198 struct sky2_hw *hw = pci_get_drvdata(pdev);
4199 int i, wol = 0;
4200
549a68c3
SH		 4201 if (!hw)
4202 return;
4203
e3173832
SH		 4204 del_timer_sync(&hw->idle_timer);
4205 netif_poll_disable(hw->dev[0]);
4206
4207 for (i = 0; i < hw->ports; i++) {
4208 struct net_device *dev = hw->dev[i];
4209 struct sky2_port *sky2 = netdev_priv(dev);
4210
4211 if (sky2->wol) {
4212 wol = 1;
4213 sky2_wol_init(sky2);
4214 }
4215 }
4216
4217 if (wol)
4218 sky2_power_aux(hw);
4219
4220 pci_enable_wake(pdev, PCI_D3hot, wol);
4221 pci_enable_wake(pdev, PCI_D3cold, wol);
4222
4223 pci_disable_device(pdev);
4224 pci_set_power_state(pdev, PCI_D3hot);
4225
4226}
4227
cd28ab6a 4228static struct pci_driver sky2_driver = {
793b883e
SH		 4229 .name = DRV_NAME,
4230 .id_table = sky2_id_table,
4231 .probe = sky2_probe,
4232 .remove = __devexit_p(sky2_remove),
cd28ab6a 4233#ifdef CONFIG_PM
793b883e
SH		 4234 .suspend = sky2_suspend,
4235 .resume = sky2_resume,
cd28ab6a 4236#endif
e3173832 4237 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4238};
4239
4240static int __init sky2_init_module(void)
4241{
3cf26753 4242 sky2_debug_init();
50241c4c 4243 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4244}
4245
4246static void __exit sky2_cleanup_module(void)
4247{
4248 pci_unregister_driver(&sky2_driver);
3cf26753 4249 sky2_debug_cleanup();
cd28ab6a
SH		 4250}
4251
4252module_init(sky2_init_module);
4253module_exit(sky2_cleanup_module);
4254
4255MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4256MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4257MODULE_LICENSE("GPL");
5f4f9dc1 4258MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)