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[PATCH] x86_64: Move ondemand timer into own work queue
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
cd28ab6a 26#include <linux/config.h>
793b883e 27#include <linux/crc32.h>
cd28ab6a
SH		 28#include <linux/kernel.h>
29#include <linux/version.h>
30#include <linux/module.h>
31#include <linux/netdevice.h>
d0bbccfa 32#include <linux/dma-mapping.h>
cd28ab6a
SH		 33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/in.h>
39#include <linux/delay.h>
91c86df5 40#include <linux/workqueue.h>
d1f13708 41#include <linux/if_vlan.h>
d70cd51a 42#include <linux/prefetch.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
bdf9c27d 54#define DRV_VERSION "1.2"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
62 */
63
13210ce5 64#define RX_LE_SIZE 512
cd28ab6a 65#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 66#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 67#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 68#define RX_SKB_ALIGN 8
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77#define ETH_JUMBO_MTU 9000
78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
82static const u32 default_msg =
793b883e
SH		 83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 86
793b883e 87static int debug = -1; /* defaults above */
cd28ab6a
SH		 88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
bdb5c58e
SH		 91static int copybreak __read_mostly = 256;
92module_param(copybreak, int, 0);
93MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
fb2690a9
SH		 95static int disable_msi = 0;
96module_param(disable_msi, int, 0);
97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
cd28ab6a 99static const struct pci_device_id sky2_id_table[] = {
793b883e 100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
cd28ab6a
SH		 102 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
103 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
104 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
cd28ab6a
SH		 117 { 0 }
118};
793b883e 119
cd28ab6a
SH		 120MODULE_DEVICE_TABLE(pci, sky2_id_table);
121
122/* Avoid conditionals by using array */
123static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
124static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
125
92f965e8
SH		 126/* This driver supports yukon2 chipset only */
127static const char *yukon2_name[] = {
128 "XL", /* 0xb3 */
129 "EC Ultra", /* 0xb4 */
130 "UNKNOWN", /* 0xb5 */
131 "EC", /* 0xb6 */
132 "FE", /* 0xb7 */
793b883e
SH		 133};
134
793b883e 135/* Access to external PHY */
ef743d33 136static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 137{
138 int i;
139
140 gma_write16(hw, port, GM_SMI_DATA, val);
141 gma_write16(hw, port, GM_SMI_CTRL,
142 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
143
144 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 145 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 146 return 0;
793b883e 147 udelay(1);
cd28ab6a 148 }
ef743d33 149
793b883e 150 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 151 return -ETIMEDOUT;
cd28ab6a
SH		 152}
153
ef743d33 154static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 155{
156 int i;
157
793b883e 158 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 159 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
160
161 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 162 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
163 *val = gma_read16(hw, port, GM_SMI_DATA);
164 return 0;
165 }
166
793b883e 167 udelay(1);
cd28ab6a
SH		 168 }
169
ef743d33
SH		 170 return -ETIMEDOUT;
171}
172
173static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
174{
175 u16 v;
176
177 if (__gm_phy_read(hw, port, reg, &v) != 0)
178 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
179 return v;
cd28ab6a
SH		 180}
181
5afa0a9c
SH		 182static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
183{
184 u16 power_control;
185 u32 reg1;
186 int vaux;
187 int ret = 0;
188
189 pr_debug("sky2_set_power_state %d\n", state);
190 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
191
56a645cc 192 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 193 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c
SH		 194 (power_control & PCI_PM_CAP_PME_D3cold);
195
56a645cc 196 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c
SH		 197
198 power_control |= PCI_PM_CTRL_PME_STATUS;
199 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
200
201 switch (state) {
202 case PCI_D0:
203 /* switch power to VCC (WA for VAUX problem) */
204 sky2_write8(hw, B0_POWER_CTRL,
205 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
206
207 /* disable Core Clock Division, */
208 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
209
210 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
211 /* enable bits are inverted */
212 sky2_write8(hw, B2_Y2_CLK_GATE,
213 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
214 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
215 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
216 else
217 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
218
219 /* Turn off phy power saving */
56a645cc 220 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c
SH		 221 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
222
d571b694 223 /* looks like this XL is back asswards .. */
5afa0a9c
SH		 224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
225 reg1 |= PCI_Y2_PHY1_COMA;
226 if (hw->ports > 1)
227 reg1 |= PCI_Y2_PHY2_COMA;
228 }
977bdf06
SH		 229
230 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
56a645cc
SH		 231 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
232 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 233 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 234 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
235 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 236 }
237
56a645cc 238 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
977bdf06 239
5afa0a9c
SH		 240 break;
241
242 case PCI_D3hot:
243 case PCI_D3cold:
244 /* Turn on phy power saving */
56a645cc 245 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c
SH		 246 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
247 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
248 else
249 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
56a645cc 250 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
5afa0a9c
SH		 251
252 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
253 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
254 else
255 /* enable bits are inverted */
256 sky2_write8(hw, B2_Y2_CLK_GATE,
257 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
258 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
259 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
260
261 /* switch power to VAUX */
262 if (vaux && state != PCI_D3cold)
263 sky2_write8(hw, B0_POWER_CTRL,
264 (PC_VAUX_ENA | PC_VCC_ENA |
265 PC_VAUX_ON | PC_VCC_OFF));
266 break;
267 default:
268 printk(KERN_ERR PFX "Unknown power state %d\n", state);
269 ret = -1;
270 }
271
56a645cc 272 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c
SH		 273 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
274 return ret;
275}
276
cd28ab6a
SH		 277static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
278{
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
283 /* disable PHY IRQs */
284 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 285
cd28ab6a
SH		 286 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
287 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
288 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
289 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
290
291 reg = gma_read16(hw, port, GM_RX_CTRL);
292 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
293 gma_write16(hw, port, GM_RX_CTRL, reg);
294}
295
296static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
297{
298 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 299 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 300
793b883e 301 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
cd28ab6a
SH		 302 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
303
304 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 305 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 306 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
307
308 if (hw->chip_id == CHIP_ID_YUKON_EC)
309 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
310 else
311 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
312
313 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
314 }
315
316 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
317 if (hw->copper) {
318 if (hw->chip_id == CHIP_ID_YUKON_FE) {
319 /* enable automatic crossover */
320 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
321 } else {
322 /* disable energy detect */
323 ctrl &= ~PHY_M_PC_EN_DET_MSK;
324
325 /* enable automatic crossover */
326 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
327
328 if (sky2->autoneg == AUTONEG_ENABLE &&
329 hw->chip_id == CHIP_ID_YUKON_XL) {
330 ctrl &= ~PHY_M_PC_DSC_MSK;
331 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
332 }
333 }
334 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
335 } else {
336 /* workaround for deviation #4.88 (CRC errors) */
337 /* disable Automatic Crossover */
338
339 ctrl &= ~PHY_M_PC_MDIX_MSK;
340 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
341
342 if (hw->chip_id == CHIP_ID_YUKON_XL) {
343 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
344 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
345 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
346 ctrl &= ~PHY_M_MAC_MD_MSK;
347 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
348 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
349
350 /* select page 1 to access Fiber registers */
351 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
352 }
cd28ab6a
SH		 353 }
354
355 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
356 if (sky2->autoneg == AUTONEG_DISABLE)
357 ctrl &= ~PHY_CT_ANE;
358 else
359 ctrl |= PHY_CT_ANE;
360
361 ctrl |= PHY_CT_RESET;
362 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
363
364 ctrl = 0;
365 ct1000 = 0;
366 adv = PHY_AN_CSMA;
367
368 if (sky2->autoneg == AUTONEG_ENABLE) {
369 if (hw->copper) {
370 if (sky2->advertising & ADVERTISED_1000baseT_Full)
371 ct1000 |= PHY_M_1000C_AFD;
372 if (sky2->advertising & ADVERTISED_1000baseT_Half)
373 ct1000 |= PHY_M_1000C_AHD;
374 if (sky2->advertising & ADVERTISED_100baseT_Full)
375 adv |= PHY_M_AN_100_FD;
376 if (sky2->advertising & ADVERTISED_100baseT_Half)
377 adv |= PHY_M_AN_100_HD;
378 if (sky2->advertising & ADVERTISED_10baseT_Full)
379 adv |= PHY_M_AN_10_FD;
380 if (sky2->advertising & ADVERTISED_10baseT_Half)
381 adv |= PHY_M_AN_10_HD;
793b883e 382 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 383 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
384
385 /* Set Flow-control capabilities */
386 if (sky2->tx_pause && sky2->rx_pause)
793b883e 387 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 388 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 389 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 390 else if (!sky2->rx_pause && sky2->tx_pause)
391 adv |= PHY_AN_PAUSE_ASYM; /* local */
392
393 /* Restart Auto-negotiation */
394 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
395 } else {
396 /* forced speed/duplex settings */
397 ct1000 = PHY_M_1000C_MSE;
398
399 if (sky2->duplex == DUPLEX_FULL)
400 ctrl |= PHY_CT_DUP_MD;
401
402 switch (sky2->speed) {
403 case SPEED_1000:
404 ctrl |= PHY_CT_SP1000;
405 break;
406 case SPEED_100:
407 ctrl |= PHY_CT_SP100;
408 break;
409 }
410
411 ctrl |= PHY_CT_RESET;
412 }
413
414 if (hw->chip_id != CHIP_ID_YUKON_FE)
415 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
416
417 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
418 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
419
420 /* Setup Phy LED's */
421 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
422 ledover = 0;
423
424 switch (hw->chip_id) {
425 case CHIP_ID_YUKON_FE:
426 /* on 88E3082 these bits are at 11..9 (shifted left) */
427 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
428
429 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
430
431 /* delete ACT LED control bits */
432 ctrl &= ~PHY_M_FELP_LED1_MSK;
433 /* change ACT LED control to blink mode */
434 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
435 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
436 break;
437
438 case CHIP_ID_YUKON_XL:
793b883e 439 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 440
441 /* select page 3 to access LED control register */
442 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
443
444 /* set LED Function Control register */
793b883e
SH		 445 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
446 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
447 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
448 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 449
450 /* set Polarity Control register */
451 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 452 (PHY_M_POLC_LS1_P_MIX(4) |
453 PHY_M_POLC_IS0_P_MIX(4) |
454 PHY_M_POLC_LOS_CTRL(2) |
455 PHY_M_POLC_INIT_CTRL(2) |
456 PHY_M_POLC_STA1_CTRL(2) |
457 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 458
459 /* restore page register */
793b883e 460 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 461 break;
462
463 default:
464 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
465 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
466 /* turn off the Rx LED (LED_RX) */
467 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
468 }
469
977bdf06
SH		 470 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
471 /* apply fixes in PHY AFE */
472 gm_phy_write(hw, port, 22, 255);
473 /* increase differential signal amplitude in 10BASE-T */
474 gm_phy_write(hw, port, 24, 0xaa99);
475 gm_phy_write(hw, port, 23, 0x2011);
cd28ab6a 476
977bdf06
SH		 477 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
478 gm_phy_write(hw, port, 24, 0xa204);
479 gm_phy_write(hw, port, 23, 0x2002);
480
481 /* set page register to 0 */
482 gm_phy_write(hw, port, 22, 0);
483 } else {
484 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 485
977bdf06
SH		 486 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
487 /* turn on 100 Mbps LED (LED_LINK100) */
488 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
489 }
cd28ab6a 490
977bdf06
SH		 491 if (ledover)
492 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
493
494 }
d571b694 495 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 496 if (sky2->autoneg == AUTONEG_ENABLE)
497 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
498 else
499 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
500}
501
1b537565
SH		 502/* Force a renegotiation */
503static void sky2_phy_reinit(struct sky2_port *sky2)
504{
e07b1aa8 505 spin_lock_bh(&sky2->phy_lock);
1b537565 506 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 507 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 508}
509
cd28ab6a
SH		 510static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
511{
512 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
513 u16 reg;
514 int i;
515 const u8 *addr = hw->dev[port]->dev_addr;
516
42eeea01
SH		 517 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
518 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 519
520 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
521
793b883e 522 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 523 /* WA DEV_472 -- looks like crossed wires on port 2 */
524 /* clear GMAC 1 Control reset */
525 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
526 do {
527 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
528 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
529 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
530 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
531 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
532 }
533
cd28ab6a
SH		 534 if (sky2->autoneg == AUTONEG_DISABLE) {
535 reg = gma_read16(hw, port, GM_GP_CTRL);
536 reg |= GM_GPCR_AU_ALL_DIS;
537 gma_write16(hw, port, GM_GP_CTRL, reg);
538 gma_read16(hw, port, GM_GP_CTRL);
539
cd28ab6a
SH		 540 switch (sky2->speed) {
541 case SPEED_1000:
6f4c56b2 542 reg &= ~GM_GPCR_SPEED_100;
cd28ab6a 543 reg |= GM_GPCR_SPEED_1000;
6f4c56b2 544 break;
cd28ab6a 545 case SPEED_100:
6f4c56b2 546 reg &= ~GM_GPCR_SPEED_1000;
cd28ab6a 547 reg |= GM_GPCR_SPEED_100;
6f4c56b2
SH		 548 break;
549 case SPEED_10:
550 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
551 break;
cd28ab6a
SH		 552 }
553
554 if (sky2->duplex == DUPLEX_FULL)
555 reg |= GM_GPCR_DUP_FULL;
556 } else
557 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
558
559 if (!sky2->tx_pause && !sky2->rx_pause) {
560 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 561 reg |=
562 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
563 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 564 /* disable Rx flow-control */
565 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
566 }
567
568 gma_write16(hw, port, GM_GP_CTRL, reg);
569
793b883e 570 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 571
e07b1aa8 572 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 573 sky2_phy_init(hw, port);
e07b1aa8 574 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 575
576 /* MIB clear */
577 reg = gma_read16(hw, port, GM_PHY_ADDR);
578 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
579
43f2f104
SH		 580 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
581 gma_read16(hw, port, i);
cd28ab6a
SH		 582 gma_write16(hw, port, GM_PHY_ADDR, reg);
583
584 /* transmit control */
585 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
586
587 /* receive control reg: unicast + multicast + no FCS */
588 gma_write16(hw, port, GM_RX_CTRL,
793b883e 589 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 590
591 /* transmit flow control */
592 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
593
594 /* transmit parameter */
595 gma_write16(hw, port, GM_TX_PARAM,
596 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
597 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
598 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
599 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
600
601 /* serial mode register */
602 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 603 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 604
6b1a3aef 605 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 606 reg |= GM_SMOD_JUMBO_ENA;
607
608 gma_write16(hw, port, GM_SERIAL_MODE, reg);
609
cd28ab6a
SH		 610 /* virtual address for data */
611 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
612
793b883e
SH		 613 /* physical address: used for pause frames */
614 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
615
616 /* ignore counter overflows */
cd28ab6a
SH		 617 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
618 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
619 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
620
621 /* Configure Rx MAC FIFO */
622 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 623 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
624 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 625
d571b694 626 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 627 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 628
793b883e
SH		 629 /* Set threshold to 0xa (64 bytes)
630 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 631 */
632 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
633
634 /* Configure Tx MAC FIFO */
635 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
636 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 637
638 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
639 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
640 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
641 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
642 /* set Tx GMAC FIFO Almost Empty Threshold */
643 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
644 /* Disable Store & Forward mode for TX */
645 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
646 }
647 }
648
cd28ab6a
SH		 649}
650
1c28f6ba
SH		 651/* Assign Ram Buffer allocation.
652 * start and end are in units of 4k bytes
653 * ram registers are in units of 64bit words
654 */
655static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 656{
1c28f6ba 657 u32 start, end;
cd28ab6a 658
1c28f6ba
SH		 659 start = startk * 4096/8;
660 end = (endk * 4096/8) - 1;
793b883e 661
cd28ab6a
SH		 662 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
663 sky2_write32(hw, RB_ADDR(q, RB_START), start);
664 sky2_write32(hw, RB_ADDR(q, RB_END), end);
665 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
666 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
667
668 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 669 u32 space = (endk - startk) * 4096/8;
670 u32 tp = space - space/4;
793b883e 671
1c28f6ba
SH		 672 /* On receive queue's set the thresholds
673 * give receiver priority when > 3/4 full
674 * send pause when down to 2K
675 */
676 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
677 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 678
1c28f6ba
SH		 679 tp = space - 2048/8;
680 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
681 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 682 } else {
683 /* Enable store & forward on Tx queue's because
684 * Tx FIFO is only 1K on Yukon
685 */
686 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
687 }
688
689 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 690 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 691}
692
cd28ab6a 693/* Setup Bus Memory Interface */
af4ed7e6 694static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 695{
696 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
697 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
698 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 699 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 700}
701
cd28ab6a
SH		 702/* Setup prefetch unit registers. This is the interface between
703 * hardware and driver list elements
704 */
8cc048e3 705static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 706 u64 addr, u32 last)
707{
cd28ab6a
SH		 708 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
709 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
710 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
711 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
712 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
713 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 714
715 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 716}
717
793b883e
SH		 718static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
719{
720 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
721
722 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
723 return le;
724}
cd28ab6a 725
290d4de5
SH		 726/* Update chip's next pointer */
727static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 728{
762c2de2 729 wmb();
290d4de5 730 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
762c2de2 731 mmiowb();
cd28ab6a
SH		 732}
733
793b883e 734
cd28ab6a
SH		 735static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
736{
737 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
738 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
739 return le;
740}
741
a018e330
SH		 742/* Return high part of DMA address (could be 32 or 64 bit) */
743static inline u32 high32(dma_addr_t a)
744{
a036119f 745 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 746}
747
793b883e 748/* Build description to hardware about buffer */
28bd181a 749static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 750{
751 struct sky2_rx_le *le;
734d1868
SH		 752 u32 hi = high32(map);
753 u16 len = sky2->rx_bufsize;
cd28ab6a 754
793b883e 755 if (sky2->rx_addr64 != hi) {
cd28ab6a 756 le = sky2_next_rx(sky2);
793b883e 757 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 758 le->ctrl = 0;
759 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 760 sky2->rx_addr64 = high32(map + len);
cd28ab6a 761 }
793b883e 762
cd28ab6a 763 le = sky2_next_rx(sky2);
734d1868
SH		 764 le->addr = cpu_to_le32((u32) map);
765 le->length = cpu_to_le16(len);
cd28ab6a
SH		 766 le->ctrl = 0;
767 le->opcode = OP_PACKET | HW_OWNER;
768}
769
793b883e 770
cd28ab6a
SH		 771/* Tell chip where to start receive checksum.
772 * Actually has two checksums, but set both same to avoid possible byte
773 * order problems.
774 */
793b883e 775static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 776{
777 struct sky2_rx_le *le;
778
cd28ab6a 779 le = sky2_next_rx(sky2);
793b883e 780 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 781 le->ctrl = 0;
782 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 783
793b883e
SH		 784 sky2_write32(sky2->hw,
785 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
786 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 787
788}
789
6b1a3aef
SH		 790/*
791 * The RX Stop command will not work for Yukon-2 if the BMU does not
792 * reach the end of packet and since we can't make sure that we have
793 * incoming data, we must reset the BMU while it is not doing a DMA
794 * transfer. Since it is possible that the RX path is still active,
795 * the RX RAM buffer will be stopped first, so any possible incoming
796 * data will not trigger a DMA. After the RAM buffer is stopped, the
797 * BMU is polled until any DMA in progress is ended and only then it
798 * will be reset.
799 */
800static void sky2_rx_stop(struct sky2_port *sky2)
801{
802 struct sky2_hw *hw = sky2->hw;
803 unsigned rxq = rxqaddr[sky2->port];
804 int i;
805
806 /* disable the RAM Buffer receive queue */
807 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
808
809 for (i = 0; i < 0xffff; i++)
810 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
811 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
812 goto stopped;
813
814 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
815 sky2->netdev->name);
816stopped:
817 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
818
819 /* reset the Rx prefetch unit */
820 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
821}
793b883e 822
d571b694 823/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 824static void sky2_rx_clean(struct sky2_port *sky2)
825{
826 unsigned i;
827
828 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 829 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 830 struct ring_info *re = sky2->rx_ring + i;
831
832 if (re->skb) {
793b883e 833 pci_unmap_single(sky2->hw->pdev,
734d1868 834 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 835 PCI_DMA_FROMDEVICE);
836 kfree_skb(re->skb);
837 re->skb = NULL;
838 }
839 }
840}
841
ef743d33
SH		 842/* Basic MII support */
843static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
844{
845 struct mii_ioctl_data *data = if_mii(ifr);
846 struct sky2_port *sky2 = netdev_priv(dev);
847 struct sky2_hw *hw = sky2->hw;
848 int err = -EOPNOTSUPP;
849
850 if (!netif_running(dev))
851 return -ENODEV; /* Phy still in reset */
852
d89e1343 853 switch (cmd) {
ef743d33
SH		 854 case SIOCGMIIPHY:
855 data->phy_id = PHY_ADDR_MARV;
856
857 /* fallthru */
858 case SIOCGMIIREG: {
859 u16 val = 0;
91c86df5 860
e07b1aa8 861 spin_lock_bh(&sky2->phy_lock);
ef743d33 862 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 863 spin_unlock_bh(&sky2->phy_lock);
91c86df5 864
ef743d33
SH		 865 data->val_out = val;
866 break;
867 }
868
869 case SIOCSMIIREG:
870 if (!capable(CAP_NET_ADMIN))
871 return -EPERM;
872
e07b1aa8 873 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 874 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
875 data->val_in);
e07b1aa8 876 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 877 break;
878 }
879 return err;
880}
881
d1f13708
SH		 882#ifdef SKY2_VLAN_TAG_USED
883static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
884{
885 struct sky2_port *sky2 = netdev_priv(dev);
886 struct sky2_hw *hw = sky2->hw;
887 u16 port = sky2->port;
d1f13708 888
302d1252 889 spin_lock_bh(&sky2->tx_lock);
d1f13708
SH		 890
891 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
892 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
893 sky2->vlgrp = grp;
894
302d1252 895 spin_unlock_bh(&sky2->tx_lock);
d1f13708
SH		 896}
897
898static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
899{
900 struct sky2_port *sky2 = netdev_priv(dev);
901 struct sky2_hw *hw = sky2->hw;
902 u16 port = sky2->port;
d1f13708 903
302d1252 904 spin_lock_bh(&sky2->tx_lock);
d1f13708
SH		 905
906 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
907 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
908 if (sky2->vlgrp)
909 sky2->vlgrp->vlan_devices[vid] = NULL;
910
302d1252 911 spin_unlock_bh(&sky2->tx_lock);
d1f13708
SH		 912}
913#endif
914
82788c7a
SH		 915/*
916 * It appears the hardware has a bug in the FIFO logic that
917 * cause it to hang if the FIFO gets overrun and the receive buffer
918 * is not aligned. ALso alloc_skb() won't align properly if slab
919 * debugging is enabled.
920 */
921static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
922{
923 struct sk_buff *skb;
924
925 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
926 if (likely(skb)) {
927 unsigned long p = (unsigned long) skb->data;
4a15d56f 928 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
82788c7a
SH		 929 }
930
931 return skb;
932}
933
cd28ab6a
SH		 934/*
935 * Allocate and setup receiver buffer pool.
936 * In case of 64 bit dma, there are 2X as many list elements
937 * available as ring entries
938 * and need to reserve one list element so we don't wrap around.
939 */
6b1a3aef 940static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 941{
6b1a3aef 942 struct sky2_hw *hw = sky2->hw;
6b1a3aef
SH		 943 unsigned rxq = rxqaddr[sky2->port];
944 int i;
cd28ab6a 945
6b1a3aef 946 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 947 sky2_qset(hw, rxq);
977bdf06
SH		 948
949 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
950 /* MAC Rx RAM Read is controlled by hardware */
951 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
952 }
953
6b1a3aef
SH		 954 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
955
956 rx_set_checksum(sky2);
793b883e 957 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 958 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 959
82788c7a 960 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
cd28ab6a
SH		 961 if (!re->skb)
962 goto nomem;
963
6b1a3aef 964 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 965 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
966 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 967 }
968
70f1be48
SH		 969 /* Truncate oversize frames */
970 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
971 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
972
6b1a3aef
SH		 973 /* Tell chip about available buffers */
974 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 975 return 0;
976nomem:
977 sky2_rx_clean(sky2);
978 return -ENOMEM;
979}
980
981/* Bring up network interface. */
982static int sky2_up(struct net_device *dev)
983{
984 struct sky2_port *sky2 = netdev_priv(dev);
985 struct sky2_hw *hw = sky2->hw;
986 unsigned port = sky2->port;
e07b1aa8 987 u32 ramsize, rxspace, imask;
cd28ab6a
SH		 988 int err = -ENOMEM;
989
990 if (netif_msg_ifup(sky2))
991 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
992
993 /* must be power of 2 */
994 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 995 TX_RING_SIZE *
996 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 997 &sky2->tx_le_map);
998 if (!sky2->tx_le)
999 goto err_out;
1000
6cdbbdf3 1001 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1002 GFP_KERNEL);
1003 if (!sky2->tx_ring)
1004 goto err_out;
1005 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1006
1007 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1008 &sky2->rx_le_map);
1009 if (!sky2->rx_le)
1010 goto err_out;
1011 memset(sky2->rx_le, 0, RX_LE_BYTES);
1012
6cdbbdf3 1013 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 1014 GFP_KERNEL);
1015 if (!sky2->rx_ring)
1016 goto err_out;
1017
1018 sky2_mac_init(hw, port);
1019
1c28f6ba
SH		 1020 /* Determine available ram buffer space (in 4K blocks).
1021 * Note: not sure about the FE setting below yet
1022 */
1023 if (hw->chip_id == CHIP_ID_YUKON_FE)
1024 ramsize = 4;
1025 else
1026 ramsize = sky2_read8(hw, B2_E_0);
1027
1028 /* Give transmitter one third (rounded up) */
1029 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1030
cd28ab6a 1031 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1032 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1033
793b883e
SH		 1034 /* Make sure SyncQ is disabled */
1035 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1036 RB_RST_SET);
1037
af4ed7e6 1038 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1039
977bdf06
SH		 1040 /* Set almost empty threshold */
1041 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1042 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1043
6b1a3aef
SH		 1044 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1045 TX_RING_SIZE - 1);
cd28ab6a 1046
6b1a3aef 1047 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1048 if (err)
1049 goto err_out;
1050
cd28ab6a 1051 /* Enable interrupts from phy/mac for port */
e07b1aa8
SH		 1052 imask = sky2_read32(hw, B0_IMSK);
1053 imask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1054 sky2_write32(hw, B0_IMSK, imask);
1055
cd28ab6a
SH		 1056 return 0;
1057
1058err_out:
1b537565 1059 if (sky2->rx_le) {
cd28ab6a
SH		 1060 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1061 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1062 sky2->rx_le = NULL;
1063 }
1064 if (sky2->tx_le) {
cd28ab6a
SH		 1065 pci_free_consistent(hw->pdev,
1066 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1067 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1068 sky2->tx_le = NULL;
1069 }
1070 kfree(sky2->tx_ring);
1071 kfree(sky2->rx_ring);
cd28ab6a 1072
1b537565
SH		 1073 sky2->tx_ring = NULL;
1074 sky2->rx_ring = NULL;
cd28ab6a
SH		 1075 return err;
1076}
1077
793b883e
SH		 1078/* Modular subtraction in ring */
1079static inline int tx_dist(unsigned tail, unsigned head)
1080{
129372d0 1081 return (head - tail) % TX_RING_SIZE;
793b883e 1082}
cd28ab6a 1083
793b883e
SH		 1084/* Number of list elements available for next tx */
1085static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1086{
793b883e 1087 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1088}
1089
793b883e 1090/* Estimate of number of transmit list elements required */
28bd181a 1091static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1092{
793b883e
SH		 1093 unsigned count;
1094
1095 count = sizeof(dma_addr_t) / sizeof(u32);
1096 count += skb_shinfo(skb)->nr_frags * count;
1097
1098 if (skb_shinfo(skb)->tso_size)
1099 ++count;
1100
0e3ff6aa 1101 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1102 ++count;
1103
1104 return count;
cd28ab6a
SH		 1105}
1106
793b883e
SH		 1107/*
1108 * Put one packet in ring for transmit.
1109 * A single packet can generate multiple list elements, and
1110 * the number of ring elements will probably be less than the number
1111 * of list elements used.
f2e46561
SH		 1112 *
1113 * No BH disabling for tx_lock here (like tg3)
793b883e 1114 */
cd28ab6a
SH		 1115static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1116{
1117 struct sky2_port *sky2 = netdev_priv(dev);
1118 struct sky2_hw *hw = sky2->hw;
d1f13708 1119 struct sky2_tx_le *le = NULL;
6cdbbdf3 1120 struct tx_ring_info *re;
cd28ab6a 1121 unsigned i, len;
b19666d9 1122 int avail;
cd28ab6a
SH		 1123 dma_addr_t mapping;
1124 u32 addr64;
1125 u16 mss;
1126 u8 ctrl;
1127
302d1252
SH		 1128 /* No BH disabling for tx_lock here. We are running in BH disabled
1129 * context and TX reclaim runs via poll inside of a software
1130 * interrupt, and no related locks in IRQ processing.
1131 */
f2e46561 1132 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1133 return NETDEV_TX_LOCKED;
1134
793b883e 1135 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1136 /* There is a known but harmless race with lockless tx
1137 * and netif_stop_queue.
1138 */
1139 if (!netif_queue_stopped(dev)) {
1140 netif_stop_queue(dev);
3be92a70
SH		 1141 if (net_ratelimit())
1142 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1143 dev->name);
8c463ef7 1144 }
f2e46561 1145 spin_unlock(&sky2->tx_lock);
cd28ab6a 1146
cd28ab6a
SH		 1147 return NETDEV_TX_BUSY;
1148 }
1149
793b883e 1150 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1151 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1152 dev->name, sky2->tx_prod, skb->len);
1153
cd28ab6a
SH		 1154 len = skb_headlen(skb);
1155 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1156 addr64 = high32(mapping);
793b883e
SH		 1157
1158 re = sky2->tx_ring + sky2->tx_prod;
1159
a018e330
SH		 1160 /* Send high bits if changed or crosses boundary */
1161 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1162 le = get_tx_le(sky2);
1163 le->tx.addr = cpu_to_le32(addr64);
1164 le->ctrl = 0;
1165 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1166 sky2->tx_addr64 = high32(mapping + len);
793b883e 1167 }
cd28ab6a
SH		 1168
1169 /* Check for TCP Segmentation Offload */
1170 mss = skb_shinfo(skb)->tso_size;
793b883e 1171 if (mss != 0) {
cd28ab6a
SH		 1172 /* just drop the packet if non-linear expansion fails */
1173 if (skb_header_cloned(skb) &&
1174 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
15240072 1175 dev_kfree_skb(skb);
793b883e 1176 goto out_unlock;
cd28ab6a
SH		 1177 }
1178
1179 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1180 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1181 mss += ETH_HLEN;
793b883e 1182 }
cd28ab6a 1183
793b883e 1184 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1185 le = get_tx_le(sky2);
1186 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1187 le->tx.tso.rsvd = 0;
cd28ab6a 1188 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1189 le->ctrl = 0;
793b883e 1190 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1191 }
1192
cd28ab6a 1193 ctrl = 0;
d1f13708
SH		 1194#ifdef SKY2_VLAN_TAG_USED
1195 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1196 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1197 if (!le) {
1198 le = get_tx_le(sky2);
1199 le->tx.addr = 0;
1200 le->opcode = OP_VLAN|HW_OWNER;
1201 le->ctrl = 0;
1202 } else
1203 le->opcode |= OP_VLAN;
1204 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1205 ctrl |= INS_VLAN;
1206 }
1207#endif
1208
1209 /* Handle TCP checksum offload */
cd28ab6a 1210 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1211 u16 hdr = skb->h.raw - skb->data;
1212 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1213
1214 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1215 if (skb->nh.iph->protocol == IPPROTO_UDP)
1216 ctrl |= UDPTCP;
1217
1218 le = get_tx_le(sky2);
1219 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1220 le->tx.csum.offset = cpu_to_le16(offset);
1221 le->length = 0; /* initial checksum value */
cd28ab6a 1222 le->ctrl = 1; /* one packet */
793b883e 1223 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1224 }
1225
1226 le = get_tx_le(sky2);
1227 le->tx.addr = cpu_to_le32((u32) mapping);
1228 le->length = cpu_to_le16(len);
1229 le->ctrl = ctrl;
793b883e 1230 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1231
793b883e 1232 /* Record the transmit mapping info */
cd28ab6a 1233 re->skb = skb;
6cdbbdf3 1234 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1235
1236 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1237 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1238 struct tx_ring_info *fre;
cd28ab6a
SH		 1239
1240 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1241 frag->size, PCI_DMA_TODEVICE);
a036119f 1242 addr64 = high32(mapping);
793b883e
SH		 1243 if (addr64 != sky2->tx_addr64) {
1244 le = get_tx_le(sky2);
1245 le->tx.addr = cpu_to_le32(addr64);
1246 le->ctrl = 0;
1247 le->opcode = OP_ADDR64 | HW_OWNER;
1248 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1249 }
1250
1251 le = get_tx_le(sky2);
1252 le->tx.addr = cpu_to_le32((u32) mapping);
1253 le->length = cpu_to_le16(frag->size);
1254 le->ctrl = ctrl;
793b883e 1255 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1256
793b883e
SH		 1257 fre = sky2->tx_ring
1258 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
6cdbbdf3 1259 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1260 }
6cdbbdf3 1261
793b883e 1262 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1263 le->ctrl |= EOP;
1264
b19666d9
SH		 1265 avail = tx_avail(sky2);
1266 if (mss != 0 || avail < TX_MIN_PENDING) {
1267 le->ctrl |= FRC_STAT;
1268 if (avail <= MAX_SKB_TX_LE)
1269 netif_stop_queue(dev);
1270 }
1271
290d4de5 1272 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1273
793b883e 1274out_unlock:
f2e46561 1275 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1276
1277 dev->trans_start = jiffies;
1278 return NETDEV_TX_OK;
1279}
1280
cd28ab6a 1281/*
793b883e
SH		 1282 * Free ring elements from starting at tx_cons until "done"
1283 *
1284 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1285 * buffers; these are deferred until completion.
cd28ab6a 1286 */
d11c13e7 1287static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1288{
d11c13e7 1289 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1290 struct pci_dev *pdev = sky2->hw->pdev;
1291 u16 nxt, put;
793b883e 1292 unsigned i;
cd28ab6a 1293
0e3ff6aa 1294 BUG_ON(done >= TX_RING_SIZE);
2224795d 1295
d11c13e7 1296 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1297 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1298 dev->name, done);
cd28ab6a 1299
af2a58ac
SH		 1300 for (put = sky2->tx_cons; put != done; put = nxt) {
1301 struct tx_ring_info *re = sky2->tx_ring + put;
1302 struct sk_buff *skb = re->skb;
cd28ab6a 1303
d89e1343 1304 nxt = re->idx;
af2a58ac 1305 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1306 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1307
793b883e 1308 /* Check for partial status */
af2a58ac
SH		 1309 if (tx_dist(put, done) < tx_dist(put, nxt))
1310 break;
793b883e
SH		 1311
1312 skb = re->skb;
af2a58ac 1313 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1314 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1315
1316 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1317 struct tx_ring_info *fre;
af2a58ac
SH		 1318 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1319 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
d89e1343 1320 skb_shinfo(skb)->frags[i].size,
734d1868 1321 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1322 }
1323
15240072 1324 dev_kfree_skb(skb);
793b883e 1325 }
793b883e 1326
af2a58ac 1327 sky2->tx_cons = put;
8f24664d 1328 if (tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a 1329 netif_wake_queue(dev);
cd28ab6a
SH		 1330}
1331
1332/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1333static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1334{
302d1252 1335 spin_lock_bh(&sky2->tx_lock);
d11c13e7 1336 sky2_tx_complete(sky2, sky2->tx_prod);
302d1252 1337 spin_unlock_bh(&sky2->tx_lock);
cd28ab6a
SH		 1338}
1339
1340/* Network shutdown */
1341static int sky2_down(struct net_device *dev)
1342{
1343 struct sky2_port *sky2 = netdev_priv(dev);
1344 struct sky2_hw *hw = sky2->hw;
1345 unsigned port = sky2->port;
1346 u16 ctrl;
e07b1aa8 1347 u32 imask;
cd28ab6a 1348
1b537565
SH		 1349 /* Never really got started! */
1350 if (!sky2->tx_le)
1351 return 0;
1352
cd28ab6a
SH		 1353 if (netif_msg_ifdown(sky2))
1354 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1355
018d1c66 1356 /* Stop more packets from being queued */
cd28ab6a
SH		 1357 netif_stop_queue(dev);
1358
793b883e
SH		 1359 sky2_phy_reset(hw, port);
1360
cd28ab6a
SH		 1361 /* Stop transmitter */
1362 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1363 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1364
1365 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1366 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1367
1368 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1369 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1370 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1371
1372 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1373
1374 /* Workaround shared GMAC reset */
793b883e
SH		 1375 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1376 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1377 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1378
1379 /* Disable Force Sync bit and Enable Alloc bit */
1380 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1381 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1382
1383 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1384 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1385 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1386
1387 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1388 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1389 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1390
1391 /* Reset the Tx prefetch units */
1392 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1393 PREF_UNIT_RST_SET);
1394
1395 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1396
6b1a3aef 1397 sky2_rx_stop(sky2);
cd28ab6a
SH		 1398
1399 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1400 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1401
e07b1aa8
SH		 1402 /* Disable port IRQ */
1403 imask = sky2_read32(hw, B0_IMSK);
1404 imask &= ~(sky2->port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1405 sky2_write32(hw, B0_IMSK, imask);
1406
d571b694 1407 /* turn off LED's */
cd28ab6a
SH		 1408 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1409
018d1c66
SH		 1410 synchronize_irq(hw->pdev->irq);
1411
cd28ab6a
SH		 1412 sky2_tx_clean(sky2);
1413 sky2_rx_clean(sky2);
1414
1415 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1416 sky2->rx_le, sky2->rx_le_map);
1417 kfree(sky2->rx_ring);
1418
1419 pci_free_consistent(hw->pdev,
1420 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1421 sky2->tx_le, sky2->tx_le_map);
1422 kfree(sky2->tx_ring);
1423
1b537565
SH		 1424 sky2->tx_le = NULL;
1425 sky2->rx_le = NULL;
1426
1427 sky2->rx_ring = NULL;
1428 sky2->tx_ring = NULL;
1429
cd28ab6a
SH		 1430 return 0;
1431}
1432
1433static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1434{
793b883e
SH		 1435 if (!hw->copper)
1436 return SPEED_1000;
1437
cd28ab6a
SH		 1438 if (hw->chip_id == CHIP_ID_YUKON_FE)
1439 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1440
1441 switch (aux & PHY_M_PS_SPEED_MSK) {
1442 case PHY_M_PS_SPEED_1000:
1443 return SPEED_1000;
1444 case PHY_M_PS_SPEED_100:
1445 return SPEED_100;
1446 default:
1447 return SPEED_10;
1448 }
1449}
1450
1451static void sky2_link_up(struct sky2_port *sky2)
1452{
1453 struct sky2_hw *hw = sky2->hw;
1454 unsigned port = sky2->port;
1455 u16 reg;
1456
1457 /* Enable Transmit FIFO Underrun */
793b883e 1458 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1459
1460 reg = gma_read16(hw, port, GM_GP_CTRL);
6f4c56b2
SH		 1461 if (sky2->autoneg == AUTONEG_DISABLE) {
1462 reg |= GM_GPCR_AU_ALL_DIS;
1463
1464 /* Is write/read necessary? Copied from sky2_mac_init */
1465 gma_write16(hw, port, GM_GP_CTRL, reg);
1466 gma_read16(hw, port, GM_GP_CTRL);
1467
1468 switch (sky2->speed) {
1469 case SPEED_1000:
1470 reg &= ~GM_GPCR_SPEED_100;
1471 reg |= GM_GPCR_SPEED_1000;
1472 break;
1473 case SPEED_100:
1474 reg &= ~GM_GPCR_SPEED_1000;
1475 reg |= GM_GPCR_SPEED_100;
1476 break;
1477 case SPEED_10:
1478 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1479 break;
1480 }
1481 } else
1482 reg &= ~GM_GPCR_AU_ALL_DIS;
1483
cd28ab6a
SH		 1484 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1485 reg |= GM_GPCR_DUP_FULL;
1486
cd28ab6a
SH		 1487 /* enable Rx/Tx */
1488 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1489 gma_write16(hw, port, GM_GP_CTRL, reg);
1490 gma_read16(hw, port, GM_GP_CTRL);
1491
1492 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1493
1494 netif_carrier_on(sky2->netdev);
1495 netif_wake_queue(sky2->netdev);
1496
1497 /* Turn on link LED */
793b883e 1498 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1499 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1500
793b883e
SH		 1501 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1502 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1503
1504 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1506 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1507 SPEED_10 ? 7 : 0) |
1508 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1509 SPEED_100 ? 7 : 0) |
1510 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1511 SPEED_1000 ? 7 : 0));
1512 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1513 }
1514
cd28ab6a
SH		 1515 if (netif_msg_link(sky2))
1516 printk(KERN_INFO PFX
d571b694 1517 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1518 sky2->netdev->name, sky2->speed,
1519 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1520 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1521 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1522}
1523
1524static void sky2_link_down(struct sky2_port *sky2)
1525{
1526 struct sky2_hw *hw = sky2->hw;
1527 unsigned port = sky2->port;
1528 u16 reg;
1529
1530 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1531
1532 reg = gma_read16(hw, port, GM_GP_CTRL);
1533 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1534 gma_write16(hw, port, GM_GP_CTRL, reg);
1535 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1536
1537 if (sky2->rx_pause && !sky2->tx_pause) {
1538 /* restore Asymmetric Pause bit */
1539 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1540 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1541 | PHY_M_AN_ASP);
cd28ab6a
SH		 1542 }
1543
cd28ab6a
SH		 1544 netif_carrier_off(sky2->netdev);
1545 netif_stop_queue(sky2->netdev);
1546
1547 /* Turn on link LED */
1548 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1549
1550 if (netif_msg_link(sky2))
1551 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1552 sky2_phy_init(hw, port);
1553}
1554
793b883e
SH		 1555static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1556{
1557 struct sky2_hw *hw = sky2->hw;
1558 unsigned port = sky2->port;
1559 u16 lpa;
1560
1561 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1562
1563 if (lpa & PHY_M_AN_RF) {
1564 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1565 return -1;
1566 }
1567
1568 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1569 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1570 printk(KERN_ERR PFX "%s: master/slave fault",
1571 sky2->netdev->name);
1572 return -1;
1573 }
1574
1575 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1576 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1577 sky2->netdev->name);
1578 return -1;
1579 }
1580
1581 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1582
1583 sky2->speed = sky2_phy_speed(hw, aux);
1584
1585 /* Pause bits are offset (9..8) */
1586 if (hw->chip_id == CHIP_ID_YUKON_XL)
1587 aux >>= 6;
1588
1589 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1590 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1591
1592 if ((sky2->tx_pause || sky2->rx_pause)
1593 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1594 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1595 else
1596 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1597
1598 return 0;
1599}
cd28ab6a 1600
e07b1aa8
SH		 1601/* Interrupt from PHY */
1602static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1603{
e07b1aa8
SH		 1604 struct net_device *dev = hw->dev[port];
1605 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1606 u16 istatus, phystat;
1607
e07b1aa8
SH		 1608 spin_lock(&sky2->phy_lock);
1609 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1610 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1611
1612 if (!netif_running(dev))
1613 goto out;
cd28ab6a
SH		 1614
1615 if (netif_msg_intr(sky2))
1616 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1617 sky2->netdev->name, istatus, phystat);
1618
1619 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1620 if (sky2_autoneg_done(sky2, phystat) == 0)
1621 sky2_link_up(sky2);
1622 goto out;
1623 }
cd28ab6a 1624
793b883e
SH		 1625 if (istatus & PHY_M_IS_LSP_CHANGE)
1626 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1627
793b883e
SH		 1628 if (istatus & PHY_M_IS_DUP_CHANGE)
1629 sky2->duplex =
1630 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1631
793b883e
SH		 1632 if (istatus & PHY_M_IS_LST_CHANGE) {
1633 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1634 sky2_link_up(sky2);
793b883e
SH		 1635 else
1636 sky2_link_down(sky2);
cd28ab6a 1637 }
793b883e 1638out:
e07b1aa8 1639 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1640}
1641
302d1252
SH		 1642
1643/* Transmit timeout is only called if we are running, carries is up
1644 * and tx queue is full (stopped).
1645 */
cd28ab6a
SH		 1646static void sky2_tx_timeout(struct net_device *dev)
1647{
1648 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1649 struct sky2_hw *hw = sky2->hw;
1650 unsigned txq = txqaddr[sky2->port];
8f24664d 1651 u16 report, done;
cd28ab6a
SH		 1652
1653 if (netif_msg_timer(sky2))
1654 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1655
8f24664d
SH		 1656 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1657 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1658
8f24664d
SH		 1659 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1660 dev->name,
1661 sky2->tx_cons, sky2->tx_prod, report, done);
1662
1663 if (report != done) {
1664 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1665
1666 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1667 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1668 } else if (report != sky2->tx_cons) {
1669 printk(KERN_INFO PFX "status report lost?\n");
1670
1671 spin_lock_bh(&sky2->tx_lock);
1672 sky2_tx_complete(sky2, report);
1673 spin_unlock_bh(&sky2->tx_lock);
1674 } else {
1675 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1676
8f24664d
SH		 1677 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1678 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1679
1680 sky2_tx_clean(sky2);
1681
1682 sky2_qset(hw, txq);
1683 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1684 }
cd28ab6a
SH		 1685}
1686
734d1868 1687
70f1be48
SH		 1688/* Want receive buffer size to be multiple of 64 bits
1689 * and incl room for vlan and truncation
1690 */
734d1868
SH		 1691static inline unsigned sky2_buf_size(int mtu)
1692{
4a15d56f 1693 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
734d1868
SH		 1694}
1695
cd28ab6a
SH		 1696static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1697{
6b1a3aef
SH		 1698 struct sky2_port *sky2 = netdev_priv(dev);
1699 struct sky2_hw *hw = sky2->hw;
1700 int err;
1701 u16 ctl, mode;
e07b1aa8 1702 u32 imask;
cd28ab6a
SH		 1703
1704 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1705 return -EINVAL;
1706
5a5b1ea0
SH		 1707 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1708 return -EINVAL;
1709
6b1a3aef
SH		 1710 if (!netif_running(dev)) {
1711 dev->mtu = new_mtu;
1712 return 0;
1713 }
1714
e07b1aa8 1715 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1716 sky2_write32(hw, B0_IMSK, 0);
1717
018d1c66
SH		 1718 dev->trans_start = jiffies; /* prevent tx timeout */
1719 netif_stop_queue(dev);
1720 netif_poll_disable(hw->dev[0]);
1721
e07b1aa8
SH		 1722 synchronize_irq(hw->pdev->irq);
1723
6b1a3aef
SH		 1724 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1725 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1726 sky2_rx_stop(sky2);
1727 sky2_rx_clean(sky2);
cd28ab6a
SH		 1728
1729 dev->mtu = new_mtu;
734d1868 1730 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef
SH		 1731 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1732 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1733
1734 if (dev->mtu > ETH_DATA_LEN)
1735 mode |= GM_SMOD_JUMBO_ENA;
1736
1737 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1738
6b1a3aef 1739 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1740
6b1a3aef 1741 err = sky2_rx_start(sky2);
e07b1aa8 1742 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1743
1b537565
SH		 1744 if (err)
1745 dev_close(dev);
1746 else {
1747 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1748
1749 netif_poll_enable(hw->dev[0]);
1750 netif_wake_queue(dev);
1751 }
1752
cd28ab6a
SH		 1753 return err;
1754}
1755
1756/*
1757 * Receive one packet.
1758 * For small packets or errors, just reuse existing skb.
d571b694 1759 * For larger packets, get new buffer.
cd28ab6a 1760 */
d11c13e7 1761static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1762 u16 length, u32 status)
1763{
cd28ab6a 1764 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1765 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1766
1767 if (unlikely(netif_msg_rx_status(sky2)))
1768 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1769 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1770
793b883e 1771 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1772 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1773
42eeea01 1774 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1775 goto error;
1776
42eeea01
SH		 1777 if (!(status & GMR_FS_RX_OK))
1778 goto resubmit;
1779
70f1be48 1780 if (length > sky2->netdev->mtu + ETH_HLEN)
6e15b712
SH		 1781 goto oversize;
1782
bdb5c58e 1783 if (length < copybreak) {
79e57d32
SH		 1784 skb = alloc_skb(length + 2, GFP_ATOMIC);
1785 if (!skb)
793b883e
SH		 1786 goto resubmit;
1787
79e57d32 1788 skb_reserve(skb, 2);
793b883e
SH		 1789 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1790 length, PCI_DMA_FROMDEVICE);
79e57d32 1791 memcpy(skb->data, re->skb->data, length);
d11c13e7
SH		 1792 skb->ip_summed = re->skb->ip_summed;
1793 skb->csum = re->skb->csum;
793b883e
SH		 1794 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1795 length, PCI_DMA_FROMDEVICE);
793b883e 1796 } else {
79e57d32
SH		 1797 struct sk_buff *nskb;
1798
82788c7a 1799 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1800 if (!nskb)
1801 goto resubmit;
cd28ab6a 1802
793b883e 1803 skb = re->skb;
79e57d32 1804 re->skb = nskb;
793b883e 1805 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1806 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1807 prefetch(skb->data);
cd28ab6a 1808
793b883e 1809 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1810 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1811 }
cd28ab6a 1812
79e57d32 1813 skb_put(skb, length);
793b883e 1814resubmit:
d11c13e7 1815 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1816 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1817
bea86103 1818 /* Tell receiver about new buffers. */
290d4de5 1819 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
bea86103 1820
cd28ab6a
SH		 1821 return skb;
1822
6e15b712
SH		 1823oversize:
1824 ++sky2->net_stats.rx_over_errors;
1825 goto resubmit;
1826
cd28ab6a 1827error:
6e15b712
SH		 1828 ++sky2->net_stats.rx_errors;
1829
3be92a70 1830 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a
SH		 1831 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1832 sky2->netdev->name, status, length);
793b883e
SH		 1833
1834 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1835 sky2->net_stats.rx_length_errors++;
1836 if (status & GMR_FS_FRAGMENT)
1837 sky2->net_stats.rx_frame_errors++;
1838 if (status & GMR_FS_CRC_ERR)
1839 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1840 if (status & GMR_FS_RX_FF_OV)
1841 sky2->net_stats.rx_fifo_errors++;
79e57d32 1842
793b883e 1843 goto resubmit;
cd28ab6a
SH		 1844}
1845
e07b1aa8
SH		 1846/* Transmit complete */
1847static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 1848{
e07b1aa8 1849 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 1850
e07b1aa8
SH		 1851 if (netif_running(dev)) {
1852 spin_lock(&sky2->tx_lock);
1853 sky2_tx_complete(sky2, last);
1854 spin_unlock(&sky2->tx_lock);
2224795d 1855 }
cd28ab6a
SH		 1856}
1857
e07b1aa8
SH		 1858/* Process status response ring */
1859static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 1860{
e07b1aa8 1861 int work_done = 0;
a8fd6266 1862
af2a58ac 1863 rmb();
bea86103 1864
e07b1aa8 1865 for(;;) {
13210ce5
SH		 1866 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1867 struct net_device *dev;
d11c13e7 1868 struct sky2_port *sky2;
cd28ab6a 1869 struct sk_buff *skb;
cd28ab6a
SH		 1870 u32 status;
1871 u16 length;
e07b1aa8
SH		 1872 u8 link, opcode;
1873
1874 opcode = le->opcode;
1875 if (!opcode)
1876 break;
1877 opcode &= ~HW_OWNER;
cd28ab6a 1878
bea86103 1879 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
e07b1aa8 1880 le->opcode = 0;
bea86103 1881
e07b1aa8
SH		 1882 link = le->link;
1883 BUG_ON(link >= 2);
1884 dev = hw->dev[link];
13210ce5
SH		 1885
1886 sky2 = netdev_priv(dev);
e07b1aa8
SH		 1887 length = le->length;
1888 status = le->status;
cd28ab6a 1889
e07b1aa8 1890 switch (opcode) {
cd28ab6a 1891 case OP_RXSTAT:
d11c13e7 1892 skb = sky2_receive(sky2, length, status);
d1f13708
SH		 1893 if (!skb)
1894 break;
13210ce5
SH		 1895
1896 skb->dev = dev;
1897 skb->protocol = eth_type_trans(skb, dev);
1898 dev->last_rx = jiffies;
1899
d1f13708
SH		 1900#ifdef SKY2_VLAN_TAG_USED
1901 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1902 vlan_hwaccel_receive_skb(skb,
1903 sky2->vlgrp,
1904 be16_to_cpu(sky2->rx_tag));
1905 } else
1906#endif
cd28ab6a 1907 netif_receive_skb(skb);
13210ce5
SH		 1908
1909 if (++work_done >= to_do)
1910 goto exit_loop;
cd28ab6a
SH		 1911 break;
1912
d1f13708
SH		 1913#ifdef SKY2_VLAN_TAG_USED
1914 case OP_RXVLAN:
1915 sky2->rx_tag = length;
1916 break;
1917
1918 case OP_RXCHKSVLAN:
1919 sky2->rx_tag = length;
1920 /* fall through */
1921#endif
cd28ab6a 1922 case OP_RXCHKS:
d11c13e7
SH		 1923 skb = sky2->rx_ring[sky2->rx_next].skb;
1924 skb->ip_summed = CHECKSUM_HW;
1925 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1926 break;
1927
1928 case OP_TXINDEXLE:
13b97b74 1929 /* TX index reports status for both ports */
e07b1aa8
SH		 1930 sky2_tx_done(hw->dev[0], status & 0xffff);
1931 if (hw->dev[1])
1932 sky2_tx_done(hw->dev[1],
1933 ((status >> 24) & 0xff)
1934 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 1935 break;
1936
cd28ab6a
SH		 1937 default:
1938 if (net_ratelimit())
793b883e 1939 printk(KERN_WARNING PFX
e07b1aa8 1940 "unknown status opcode 0x%x\n", opcode);
cd28ab6a
SH		 1941 break;
1942 }
13210ce5 1943 }
cd28ab6a 1944
13210ce5 1945exit_loop:
e07b1aa8 1946 return work_done;
cd28ab6a
SH		 1947}
1948
1949static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1950{
1951 struct net_device *dev = hw->dev[port];
1952
3be92a70
SH		 1953 if (net_ratelimit())
1954 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1955 dev->name, status);
cd28ab6a
SH		 1956
1957 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 1958 if (net_ratelimit())
1959 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1960 dev->name);
cd28ab6a
SH		 1961 /* Clear IRQ */
1962 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1963 }
1964
1965 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 1966 if (net_ratelimit())
1967 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1968 dev->name);
cd28ab6a
SH		 1969
1970 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1971 }
1972
1973 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 1974 if (net_ratelimit())
1975 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 1976 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1977 }
1978
1979 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 1980 if (net_ratelimit())
1981 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 1982 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1983 }
1984
1985 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 1986 if (net_ratelimit())
1987 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
1988 dev->name);
cd28ab6a
SH		 1989 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1990 }
1991}
1992
1993static void sky2_hw_intr(struct sky2_hw *hw)
1994{
1995 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1996
793b883e 1997 if (status & Y2_IS_TIST_OV)
cd28ab6a 1998 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 1999
2000 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2001 u16 pci_err;
2002
56a645cc 2003 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2004 if (net_ratelimit())
2005 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2006 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2007
2008 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2009 sky2_pci_write16(hw, PCI_STATUS,
793b883e 2010 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2011 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2012 }
2013
2014 if (status & Y2_IS_PCI_EXP) {
d571b694 2015 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2016 u32 pex_err;
2017
56a645cc 2018 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2019
3be92a70
SH		 2020 if (net_ratelimit())
2021 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2022 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2023
2024 /* clear the interrupt */
2025 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2026 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
793b883e 2027 0xffffffffUL);
cd28ab6a
SH		 2028 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2029
2030 if (pex_err & PEX_FATAL_ERRORS) {
2031 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2032 hwmsk &= ~Y2_IS_PCI_EXP;
2033 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2034 }
2035 }
2036
2037 if (status & Y2_HWE_L1_MASK)
2038 sky2_hw_error(hw, 0, status);
2039 status >>= 8;
2040 if (status & Y2_HWE_L1_MASK)
2041 sky2_hw_error(hw, 1, status);
2042}
2043
2044static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2045{
2046 struct net_device *dev = hw->dev[port];
2047 struct sky2_port *sky2 = netdev_priv(dev);
2048 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2049
2050 if (netif_msg_intr(sky2))
2051 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2052 dev->name, status);
2053
2054 if (status & GM_IS_RX_FF_OR) {
2055 ++sky2->net_stats.rx_fifo_errors;
2056 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2057 }
2058
2059 if (status & GM_IS_TX_FF_UR) {
2060 ++sky2->net_stats.tx_fifo_errors;
2061 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2062 }
cd28ab6a
SH		 2063}
2064
d257924e
SH		 2065/* This should never happen it is a fatal situation */
2066static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2067 const char *rxtx, u32 mask)
2068{
2069 struct net_device *dev = hw->dev[port];
2070 struct sky2_port *sky2 = netdev_priv(dev);
2071 u32 imask;
2072
2073 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2074 dev ? dev->name : "<not registered>", rxtx);
2075
2076 imask = sky2_read32(hw, B0_IMSK);
2077 imask &= ~mask;
2078 sky2_write32(hw, B0_IMSK, imask);
2079
2080 if (dev) {
2081 spin_lock(&sky2->phy_lock);
2082 sky2_link_down(sky2);
2083 spin_unlock(&sky2->phy_lock);
2084 }
2085}
cd28ab6a 2086
d27ed387
SH		 2087/* If idle then force a fake soft NAPI poll once a second
2088 * to work around cases where sharing an edge triggered interrupt.
2089 */
2090static void sky2_idle(unsigned long arg)
2091{
2092 struct net_device *dev = (struct net_device *) arg;
2093
2094 local_irq_disable();
2095 if (__netif_rx_schedule_prep(dev))
2096 __netif_rx_schedule(dev);
2097 local_irq_enable();
2098}
2099
2100
e07b1aa8 2101static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2102{
e07b1aa8
SH		 2103 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2104 int work_limit = min(dev0->quota, *budget);
2105 int work_done = 0;
fb2690a9 2106 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2107
734cbc36 2108 restart_poll:
d257924e
SH		 2109 if (unlikely(status & ~Y2_IS_STAT_BMU)) {
2110 if (status & Y2_IS_HW_ERR)
2111 sky2_hw_intr(hw);
2112
2113 if (status & Y2_IS_IRQ_PHY1)
2114 sky2_phy_intr(hw, 0);
cd28ab6a 2115
d257924e
SH		 2116 if (status & Y2_IS_IRQ_PHY2)
2117 sky2_phy_intr(hw, 1);
cd28ab6a 2118
d257924e
SH		 2119 if (status & Y2_IS_IRQ_MAC1)
2120 sky2_mac_intr(hw, 0);
cd28ab6a 2121
d257924e
SH		 2122 if (status & Y2_IS_IRQ_MAC2)
2123 sky2_mac_intr(hw, 1);
cd28ab6a 2124
d257924e
SH		 2125 if (status & Y2_IS_CHK_RX1)
2126 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2127
2128 if (status & Y2_IS_CHK_RX2)
2129 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2130
2131 if (status & Y2_IS_CHK_TXA1)
2132 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2133
2134 if (status & Y2_IS_CHK_TXA2)
2135 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2136 }
cd28ab6a 2137
e07b1aa8 2138 if (status & Y2_IS_STAT_BMU) {
734cbc36 2139 work_done += sky2_status_intr(hw, work_limit - work_done);
e07b1aa8
SH		 2140 *budget -= work_done;
2141 dev0->quota -= work_done;
2142
2143 if (work_done >= work_limit)
2144 return 1;
2145
2146 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2147 }
2148
d27ed387
SH		 2149 mod_timer(&hw->idle_timer, jiffies + HZ);
2150
734cbc36
SH		 2151 local_irq_disable();
2152 __netif_rx_complete(dev0);
e07b1aa8 2153
fb2690a9 2154 status = sky2_read32(hw, B0_Y2_SP_LISR);
734cbc36
SH		 2155
2156 if (unlikely(status)) {
2157 /* More work pending, try and keep going */
2158 if (__netif_rx_schedule_prep(dev0)) {
2159 __netif_rx_reschedule(dev0, work_done);
2160 status = sky2_read32(hw, B0_Y2_SP_EISR);
2161 local_irq_enable();
2162 goto restart_poll;
2163 }
2164 }
2165
2166 local_irq_enable();
e07b1aa8
SH		 2167 return 0;
2168}
2169
2170static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2171{
2172 struct sky2_hw *hw = dev_id;
2173 struct net_device *dev0 = hw->dev[0];
2174 u32 status;
2175
2176 /* Reading this mask interrupts as side effect */
2177 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2178 if (status == 0 || status == ~0)
2179 return IRQ_NONE;
793b883e 2180
e07b1aa8
SH		 2181 prefetch(&hw->st_le[hw->st_idx]);
2182 if (likely(__netif_rx_schedule_prep(dev0)))
2183 __netif_rx_schedule(dev0);
793b883e 2184
cd28ab6a
SH		 2185 return IRQ_HANDLED;
2186}
2187
2188#ifdef CONFIG_NET_POLL_CONTROLLER
2189static void sky2_netpoll(struct net_device *dev)
2190{
2191 struct sky2_port *sky2 = netdev_priv(dev);
2192
793b883e 2193 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 2194}
2195#endif
2196
2197/* Chip internal frequency for clock calculations */
fb17358f 2198static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2199{
793b883e 2200 switch (hw->chip_id) {
cd28ab6a 2201 case CHIP_ID_YUKON_EC:
5a5b1ea0 2202 case CHIP_ID_YUKON_EC_U:
fb17358f 2203 return 125; /* 125 Mhz */
cd28ab6a 2204 case CHIP_ID_YUKON_FE:
fb17358f 2205 return 100; /* 100 Mhz */
793b883e 2206 default: /* YUKON_XL */
fb17358f 2207 return 156; /* 156 Mhz */
cd28ab6a
SH		 2208 }
2209}
2210
fb17358f 2211static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2212{
fb17358f 2213 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2214}
2215
fb17358f 2216static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2217{
fb17358f 2218 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2219}
2220
fb17358f 2221
98712e5e 2222static int __devinit sky2_reset(struct sky2_hw *hw)
cd28ab6a 2223{
cd28ab6a
SH		 2224 u16 status;
2225 u8 t8, pmd_type;
56a645cc 2226 int i;
cd28ab6a 2227
cd28ab6a 2228 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2229
cd28ab6a
SH		 2230 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2231 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2232 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2233 pci_name(hw->pdev), hw->chip_id);
2234 return -EOPNOTSUPP;
2235 }
2236
290d4de5
SH		 2237 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2238
2239 /* This rev is really old, and requires untested workarounds */
2240 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2241 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2242 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2243 hw->chip_id, hw->chip_rev);
2244 return -EOPNOTSUPP;
2245 }
2246
2247 /* This chip is new and not tested yet */
2248 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
2249 pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n",
2250 pci_name(hw->pdev));
2251 pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n");
2252 }
2253
cd28ab6a
SH		 2254 /* disable ASF */
2255 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2256 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2257 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2258 }
2259
2260 /* do a SW reset */
2261 sky2_write8(hw, B0_CTST, CS_RST_SET);
2262 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2263
2264 /* clear PCI errors, if any */
56a645cc 2265 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2266
cd28ab6a 2267 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2268 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2269
cd28ab6a
SH		 2270
2271 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2272
2273 /* clear any PEX errors */
d89e1343 2274 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
56a645cc
SH		 2275 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2276
cd28ab6a
SH		 2277
2278 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2279 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2280
2281 hw->ports = 1;
2282 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2283 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2284 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2285 ++hw->ports;
2286 }
cd28ab6a 2287
5afa0a9c 2288 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2289
2290 for (i = 0; i < hw->ports; i++) {
2291 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2292 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2293 }
2294
2295 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2296
793b883e
SH		 2297 /* Clear I2C IRQ noise */
2298 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2299
2300 /* turn off hardware timer (unused) */
2301 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2302 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2303
cd28ab6a
SH		 2304 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2305
69634ee7
SH		 2306 /* Turn off descriptor polling */
2307 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2308
2309 /* Turn off receive timestamp */
2310 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2311 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2312
2313 /* enable the Tx Arbiters */
2314 for (i = 0; i < hw->ports; i++)
2315 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2316
2317 /* Initialize ram interface */
2318 for (i = 0; i < hw->ports; i++) {
793b883e 2319 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2320
2321 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2322 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2323 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2324 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2325 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2326 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2327 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2328 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2329 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2330 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2331 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2332 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2333 }
2334
cd28ab6a
SH		 2335 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2336
cd28ab6a
SH		 2337 for (i = 0; i < hw->ports; i++)
2338 sky2_phy_reset(hw, i);
cd28ab6a 2339
cd28ab6a
SH		 2340 memset(hw->st_le, 0, STATUS_LE_BYTES);
2341 hw->st_idx = 0;
2342
2343 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2344 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2345
2346 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2347 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2348
2349 /* Set the list last index */
793b883e 2350 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2351
290d4de5
SH		 2352 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2353 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2354
290d4de5
SH		 2355 /* set Status-FIFO ISR watermark */
2356 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2357 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2358 else
2359 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2360
290d4de5 2361 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2362 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2363 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2364
793b883e 2365 /* enable status unit */
cd28ab6a
SH		 2366 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2367
2368 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2369 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2370 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2371
2372 return 0;
2373}
2374
28bd181a 2375static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a
SH		 2376{
2377 u32 modes;
2378 if (hw->copper) {
793b883e
SH		 2379 modes = SUPPORTED_10baseT_Half
2380 | SUPPORTED_10baseT_Full
2381 | SUPPORTED_100baseT_Half
2382 | SUPPORTED_100baseT_Full
2383 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2384
2385 if (hw->chip_id != CHIP_ID_YUKON_FE)
2386 modes |= SUPPORTED_1000baseT_Half
793b883e 2387 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2388 } else
2389 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2390 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2391 return modes;
2392}
2393
793b883e 2394static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2395{
2396 struct sky2_port *sky2 = netdev_priv(dev);
2397 struct sky2_hw *hw = sky2->hw;
2398
2399 ecmd->transceiver = XCVR_INTERNAL;
2400 ecmd->supported = sky2_supported_modes(hw);
2401 ecmd->phy_address = PHY_ADDR_MARV;
2402 if (hw->copper) {
2403 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2404 | SUPPORTED_10baseT_Full
2405 | SUPPORTED_100baseT_Half
2406 | SUPPORTED_100baseT_Full
2407 | SUPPORTED_1000baseT_Half
2408 | SUPPORTED_1000baseT_Full
2409 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2410 ecmd->port = PORT_TP;
2411 } else
2412 ecmd->port = PORT_FIBRE;
2413
2414 ecmd->advertising = sky2->advertising;
2415 ecmd->autoneg = sky2->autoneg;
2416 ecmd->speed = sky2->speed;
2417 ecmd->duplex = sky2->duplex;
2418 return 0;
2419}
2420
2421static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2422{
2423 struct sky2_port *sky2 = netdev_priv(dev);
2424 const struct sky2_hw *hw = sky2->hw;
2425 u32 supported = sky2_supported_modes(hw);
2426
2427 if (ecmd->autoneg == AUTONEG_ENABLE) {
2428 ecmd->advertising = supported;
2429 sky2->duplex = -1;
2430 sky2->speed = -1;
2431 } else {
2432 u32 setting;
2433
793b883e 2434 switch (ecmd->speed) {
cd28ab6a
SH		 2435 case SPEED_1000:
2436 if (ecmd->duplex == DUPLEX_FULL)
2437 setting = SUPPORTED_1000baseT_Full;
2438 else if (ecmd->duplex == DUPLEX_HALF)
2439 setting = SUPPORTED_1000baseT_Half;
2440 else
2441 return -EINVAL;
2442 break;
2443 case SPEED_100:
2444 if (ecmd->duplex == DUPLEX_FULL)
2445 setting = SUPPORTED_100baseT_Full;
2446 else if (ecmd->duplex == DUPLEX_HALF)
2447 setting = SUPPORTED_100baseT_Half;
2448 else
2449 return -EINVAL;
2450 break;
2451
2452 case SPEED_10:
2453 if (ecmd->duplex == DUPLEX_FULL)
2454 setting = SUPPORTED_10baseT_Full;
2455 else if (ecmd->duplex == DUPLEX_HALF)
2456 setting = SUPPORTED_10baseT_Half;
2457 else
2458 return -EINVAL;
2459 break;
2460 default:
2461 return -EINVAL;
2462 }
2463
2464 if ((setting & supported) == 0)
2465 return -EINVAL;
2466
2467 sky2->speed = ecmd->speed;
2468 sky2->duplex = ecmd->duplex;
2469 }
2470
2471 sky2->autoneg = ecmd->autoneg;
2472 sky2->advertising = ecmd->advertising;
2473
1b537565
SH		 2474 if (netif_running(dev))
2475 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2476
2477 return 0;
2478}
2479
2480static void sky2_get_drvinfo(struct net_device *dev,
2481 struct ethtool_drvinfo *info)
2482{
2483 struct sky2_port *sky2 = netdev_priv(dev);
2484
2485 strcpy(info->driver, DRV_NAME);
2486 strcpy(info->version, DRV_VERSION);
2487 strcpy(info->fw_version, "N/A");
2488 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2489}
2490
2491static const struct sky2_stat {
793b883e
SH		 2492 char name[ETH_GSTRING_LEN];
2493 u16 offset;
cd28ab6a
SH		 2494} sky2_stats[] = {
2495 { "tx_bytes", GM_TXO_OK_HI },
2496 { "rx_bytes", GM_RXO_OK_HI },
2497 { "tx_broadcast", GM_TXF_BC_OK },
2498 { "rx_broadcast", GM_RXF_BC_OK },
2499 { "tx_multicast", GM_TXF_MC_OK },
2500 { "rx_multicast", GM_RXF_MC_OK },
2501 { "tx_unicast", GM_TXF_UC_OK },
2502 { "rx_unicast", GM_RXF_UC_OK },
2503 { "tx_mac_pause", GM_TXF_MPAUSE },
2504 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2505 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2506 { "late_collision",GM_TXF_LAT_COL },
2507 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2508 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2509 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2510
d2604540 2511 { "rx_short", GM_RXF_SHT },
cd28ab6a 2512 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2513 { "rx_64_byte_packets", GM_RXF_64B },
2514 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2515 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2516 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2517 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2518 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2519 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2520 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2521 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2522 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2523 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2524
2525 { "tx_64_byte_packets", GM_TXF_64B },
2526 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2527 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2528 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2529 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2530 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2531 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2532 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2533};
2534
cd28ab6a
SH		 2535static u32 sky2_get_rx_csum(struct net_device *dev)
2536{
2537 struct sky2_port *sky2 = netdev_priv(dev);
2538
2539 return sky2->rx_csum;
2540}
2541
2542static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2543{
2544 struct sky2_port *sky2 = netdev_priv(dev);
2545
2546 sky2->rx_csum = data;
793b883e 2547
cd28ab6a
SH		 2548 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2549 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2550
2551 return 0;
2552}
2553
2554static u32 sky2_get_msglevel(struct net_device *netdev)
2555{
2556 struct sky2_port *sky2 = netdev_priv(netdev);
2557 return sky2->msg_enable;
2558}
2559
9a7ae0a9
SH		 2560static int sky2_nway_reset(struct net_device *dev)
2561{
2562 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2563
2564 if (sky2->autoneg != AUTONEG_ENABLE)
2565 return -EINVAL;
2566
1b537565 2567 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2568
2569 return 0;
2570}
2571
793b883e 2572static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2573{
2574 struct sky2_hw *hw = sky2->hw;
2575 unsigned port = sky2->port;
2576 int i;
2577
2578 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2579 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2580 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2581 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2582
793b883e 2583 for (i = 2; i < count; i++)
cd28ab6a
SH		 2584 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2585}
2586
cd28ab6a
SH		 2587static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2588{
2589 struct sky2_port *sky2 = netdev_priv(netdev);
2590 sky2->msg_enable = value;
2591}
2592
2593static int sky2_get_stats_count(struct net_device *dev)
2594{
2595 return ARRAY_SIZE(sky2_stats);
2596}
2597
2598static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2599 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2600{
2601 struct sky2_port *sky2 = netdev_priv(dev);
2602
793b883e 2603 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2604}
2605
793b883e 2606static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2607{
2608 int i;
2609
2610 switch (stringset) {
2611 case ETH_SS_STATS:
2612 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2613 memcpy(data + i * ETH_GSTRING_LEN,
2614 sky2_stats[i].name, ETH_GSTRING_LEN);
2615 break;
2616 }
2617}
2618
2619/* Use hardware MIB variables for critical path statistics and
2620 * transmit feedback not reported at interrupt.
2621 * Other errors are accounted for in interrupt handler.
2622 */
2623static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2624{
2625 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2626 u64 data[13];
cd28ab6a 2627
793b883e 2628 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2629
2630 sky2->net_stats.tx_bytes = data[0];
2631 sky2->net_stats.rx_bytes = data[1];
2632 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2633 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2634 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2635 sky2->net_stats.collisions = data[10];
2636 sky2->net_stats.tx_aborted_errors = data[12];
2637
2638 return &sky2->net_stats;
2639}
2640
2641static int sky2_set_mac_address(struct net_device *dev, void *p)
2642{
2643 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2644 struct sky2_hw *hw = sky2->hw;
2645 unsigned port = sky2->port;
2646 const struct sockaddr *addr = p;
cd28ab6a
SH		 2647
2648 if (!is_valid_ether_addr(addr->sa_data))
2649 return -EADDRNOTAVAIL;
2650
cd28ab6a 2651 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2652 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2653 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2654 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2655 dev->dev_addr, ETH_ALEN);
1b537565 2656
a8ab1ec0
SH		 2657 /* virtual address for data */
2658 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2659
2660 /* physical address: used for pause frames */
2661 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2662
2663 return 0;
cd28ab6a
SH		 2664}
2665
2666static void sky2_set_multicast(struct net_device *dev)
2667{
2668 struct sky2_port *sky2 = netdev_priv(dev);
2669 struct sky2_hw *hw = sky2->hw;
2670 unsigned port = sky2->port;
2671 struct dev_mc_list *list = dev->mc_list;
2672 u16 reg;
2673 u8 filter[8];
2674
2675 memset(filter, 0, sizeof(filter));
2676
2677 reg = gma_read16(hw, port, GM_RX_CTRL);
2678 reg |= GM_RXCR_UCF_ENA;
2679
d571b694 2680 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2681 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2682 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2683 memset(filter, 0xff, sizeof(filter));
793b883e 2684 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2685 reg &= ~GM_RXCR_MCF_ENA;
2686 else {
2687 int i;
2688 reg |= GM_RXCR_MCF_ENA;
2689
2690 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2691 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2692 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2693 }
2694 }
2695
cd28ab6a 2696 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2697 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2698 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2699 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2700 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2701 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2702 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2703 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2704
2705 gma_write16(hw, port, GM_RX_CTRL, reg);
2706}
2707
2708/* Can have one global because blinking is controlled by
2709 * ethtool and that is always under RTNL mutex
2710 */
91c86df5 2711static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2712{
793b883e
SH		 2713 u16 pg;
2714
793b883e
SH		 2715 switch (hw->chip_id) {
2716 case CHIP_ID_YUKON_XL:
2717 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2718 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2719 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2720 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2721 PHY_M_LEDC_INIT_CTRL(7) |
2722 PHY_M_LEDC_STA1_CTRL(7) |
2723 PHY_M_LEDC_STA0_CTRL(7))
2724 : 0);
2725
2726 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2727 break;
2728
2729 default:
2730 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2731 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2732 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2733 PHY_M_LED_MO_10(MO_LED_ON) |
2734 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2735 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2736 PHY_M_LED_MO_RX(MO_LED_ON)
2737 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2738 PHY_M_LED_MO_10(MO_LED_OFF) |
2739 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2740 PHY_M_LED_MO_1000(MO_LED_OFF) |
2741 PHY_M_LED_MO_RX(MO_LED_OFF));
2742
793b883e 2743 }
cd28ab6a
SH		 2744}
2745
2746/* blink LED's for finding board */
2747static int sky2_phys_id(struct net_device *dev, u32 data)
2748{
2749 struct sky2_port *sky2 = netdev_priv(dev);
2750 struct sky2_hw *hw = sky2->hw;
2751 unsigned port = sky2->port;
793b883e 2752 u16 ledctrl, ledover = 0;
cd28ab6a 2753 long ms;
91c86df5 2754 int interrupted;
cd28ab6a
SH		 2755 int onoff = 1;
2756
793b883e 2757 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2758 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2759 else
2760 ms = data * 1000;
2761
2762 /* save initial values */
e07b1aa8 2763 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2764 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2765 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2766 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2767 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2768 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2769 } else {
2770 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2771 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2772 }
cd28ab6a 2773
91c86df5
SH		 2774 interrupted = 0;
2775 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2776 sky2_led(hw, port, onoff);
2777 onoff = !onoff;
2778
e07b1aa8 2779 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2780 interrupted = msleep_interruptible(250);
e07b1aa8 2781 spin_lock_bh(&sky2->phy_lock);
91c86df5 2782
cd28ab6a
SH		 2783 ms -= 250;
2784 }
2785
2786 /* resume regularly scheduled programming */
793b883e
SH		 2787 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2788 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2789 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2790 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2791 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2792 } else {
2793 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2794 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2795 }
e07b1aa8 2796 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2797
2798 return 0;
2799}
2800
2801static void sky2_get_pauseparam(struct net_device *dev,
2802 struct ethtool_pauseparam *ecmd)
2803{
2804 struct sky2_port *sky2 = netdev_priv(dev);
2805
2806 ecmd->tx_pause = sky2->tx_pause;
2807 ecmd->rx_pause = sky2->rx_pause;
2808 ecmd->autoneg = sky2->autoneg;
2809}
2810
2811static int sky2_set_pauseparam(struct net_device *dev,
2812 struct ethtool_pauseparam *ecmd)
2813{
2814 struct sky2_port *sky2 = netdev_priv(dev);
2815 int err = 0;
2816
2817 sky2->autoneg = ecmd->autoneg;
2818 sky2->tx_pause = ecmd->tx_pause != 0;
2819 sky2->rx_pause = ecmd->rx_pause != 0;
2820
1b537565 2821 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2822
2823 return err;
2824}
2825
fb17358f
SH		 2826static int sky2_get_coalesce(struct net_device *dev,
2827 struct ethtool_coalesce *ecmd)
2828{
2829 struct sky2_port *sky2 = netdev_priv(dev);
2830 struct sky2_hw *hw = sky2->hw;
2831
2832 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2833 ecmd->tx_coalesce_usecs = 0;
2834 else {
2835 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2836 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2837 }
2838 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2839
2840 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2841 ecmd->rx_coalesce_usecs = 0;
2842 else {
2843 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2844 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2845 }
2846 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2847
2848 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2849 ecmd->rx_coalesce_usecs_irq = 0;
2850 else {
2851 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2852 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2853 }
2854
2855 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2856
2857 return 0;
2858}
2859
2860/* Note: this affect both ports */
2861static int sky2_set_coalesce(struct net_device *dev,
2862 struct ethtool_coalesce *ecmd)
2863{
2864 struct sky2_port *sky2 = netdev_priv(dev);
2865 struct sky2_hw *hw = sky2->hw;
77b3d6a2 2866 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 2867
77b3d6a2
SH		 2868 if (ecmd->tx_coalesce_usecs > tmax ||
2869 ecmd->rx_coalesce_usecs > tmax ||
2870 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 2871 return -EINVAL;
2872
ff81fbbe 2873 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 2874 return -EINVAL;
ff81fbbe 2875 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 2876 return -EINVAL;
ff81fbbe 2877 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 2878 return -EINVAL;
2879
2880 if (ecmd->tx_coalesce_usecs == 0)
2881 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2882 else {
2883 sky2_write32(hw, STAT_TX_TIMER_INI,
2884 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2885 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2886 }
2887 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2888
2889 if (ecmd->rx_coalesce_usecs == 0)
2890 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2891 else {
2892 sky2_write32(hw, STAT_LEV_TIMER_INI,
2893 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2894 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2895 }
2896 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2897
2898 if (ecmd->rx_coalesce_usecs_irq == 0)
2899 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2900 else {
d28d4870 2901 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 2902 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2903 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2904 }
2905 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2906 return 0;
2907}
2908
793b883e
SH		 2909static void sky2_get_ringparam(struct net_device *dev,
2910 struct ethtool_ringparam *ering)
2911{
2912 struct sky2_port *sky2 = netdev_priv(dev);
2913
2914 ering->rx_max_pending = RX_MAX_PENDING;
2915 ering->rx_mini_max_pending = 0;
2916 ering->rx_jumbo_max_pending = 0;
2917 ering->tx_max_pending = TX_RING_SIZE - 1;
2918
2919 ering->rx_pending = sky2->rx_pending;
2920 ering->rx_mini_pending = 0;
2921 ering->rx_jumbo_pending = 0;
2922 ering->tx_pending = sky2->tx_pending;
2923}
2924
2925static int sky2_set_ringparam(struct net_device *dev,
2926 struct ethtool_ringparam *ering)
2927{
2928 struct sky2_port *sky2 = netdev_priv(dev);
2929 int err = 0;
2930
2931 if (ering->rx_pending > RX_MAX_PENDING ||
2932 ering->rx_pending < 8 ||
2933 ering->tx_pending < MAX_SKB_TX_LE ||
2934 ering->tx_pending > TX_RING_SIZE - 1)
2935 return -EINVAL;
2936
2937 if (netif_running(dev))
2938 sky2_down(dev);
2939
2940 sky2->rx_pending = ering->rx_pending;
2941 sky2->tx_pending = ering->tx_pending;
2942
1b537565 2943 if (netif_running(dev)) {
793b883e 2944 err = sky2_up(dev);
1b537565
SH		 2945 if (err)
2946 dev_close(dev);
6ed995bb
SH		 2947 else
2948 sky2_set_multicast(dev);
1b537565 2949 }
793b883e
SH		 2950
2951 return err;
2952}
2953
793b883e
SH		 2954static int sky2_get_regs_len(struct net_device *dev)
2955{
6e4cbb34 2956 return 0x4000;
793b883e
SH		 2957}
2958
2959/*
2960 * Returns copy of control register region
6e4cbb34 2961 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 2962 */
2963static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2964 void *p)
2965{
2966 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2967 const void __iomem *io = sky2->hw->regs;
793b883e 2968
6e4cbb34 2969 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 2970 regs->version = 1;
6e4cbb34 2971 memset(p, 0, regs->len);
793b883e 2972
6e4cbb34
SH		 2973 memcpy_fromio(p, io, B3_RAM_ADDR);
2974
2975 memcpy_fromio(p + B3_RI_WTO_R1,
2976 io + B3_RI_WTO_R1,
2977 regs->len - B3_RI_WTO_R1);
793b883e 2978}
cd28ab6a
SH		 2979
2980static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 2981 .get_settings = sky2_get_settings,
2982 .set_settings = sky2_set_settings,
2983 .get_drvinfo = sky2_get_drvinfo,
2984 .get_msglevel = sky2_get_msglevel,
2985 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 2986 .nway_reset = sky2_nway_reset,
793b883e
SH		 2987 .get_regs_len = sky2_get_regs_len,
2988 .get_regs = sky2_get_regs,
2989 .get_link = ethtool_op_get_link,
2990 .get_sg = ethtool_op_get_sg,
2991 .set_sg = ethtool_op_set_sg,
2992 .get_tx_csum = ethtool_op_get_tx_csum,
2993 .set_tx_csum = ethtool_op_set_tx_csum,
2994 .get_tso = ethtool_op_get_tso,
2995 .set_tso = ethtool_op_set_tso,
2996 .get_rx_csum = sky2_get_rx_csum,
2997 .set_rx_csum = sky2_set_rx_csum,
2998 .get_strings = sky2_get_strings,
fb17358f
SH		 2999 .get_coalesce = sky2_get_coalesce,
3000 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3001 .get_ringparam = sky2_get_ringparam,
3002 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3003 .get_pauseparam = sky2_get_pauseparam,
3004 .set_pauseparam = sky2_set_pauseparam,
793b883e 3005 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3006 .get_stats_count = sky2_get_stats_count,
3007 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3008 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3009};
3010
3011/* Initialize network device */
3012static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3013 unsigned port, int highmem)
3014{
3015 struct sky2_port *sky2;
3016 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3017
3018 if (!dev) {
3019 printk(KERN_ERR "sky2 etherdev alloc failed");
3020 return NULL;
3021 }
3022
3023 SET_MODULE_OWNER(dev);
3024 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3025 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3026 dev->open = sky2_up;
3027 dev->stop = sky2_down;
ef743d33 3028 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3029 dev->hard_start_xmit = sky2_xmit_frame;
3030 dev->get_stats = sky2_get_stats;
3031 dev->set_multicast_list = sky2_set_multicast;
3032 dev->set_mac_address = sky2_set_mac_address;
3033 dev->change_mtu = sky2_change_mtu;
3034 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3035 dev->tx_timeout = sky2_tx_timeout;
3036 dev->watchdog_timeo = TX_WATCHDOG;
3037 if (port == 0)
3038 dev->poll = sky2_poll;
3039 dev->weight = NAPI_WEIGHT;
3040#ifdef CONFIG_NET_POLL_CONTROLLER
3041 dev->poll_controller = sky2_netpoll;
3042#endif
cd28ab6a
SH		 3043
3044 sky2 = netdev_priv(dev);
3045 sky2->netdev = dev;
3046 sky2->hw = hw;
3047 sky2->msg_enable = netif_msg_init(debug, default_msg);
3048
3049 spin_lock_init(&sky2->tx_lock);
3050 /* Auto speed and flow control */
3051 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3052 sky2->tx_pause = 1;
cd28ab6a
SH		 3053 sky2->rx_pause = 1;
3054 sky2->duplex = -1;
3055 sky2->speed = -1;
3056 sky2->advertising = sky2_supported_modes(hw);
75d070c5 3057
d89e1343 3058 /* Receive checksum disabled for Yukon XL
75d070c5
SH		 3059 * because of observed problems with incorrect
3060 * values when multiple packets are received in one interrupt
3061 */
3062 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3063
e07b1aa8 3064 spin_lock_init(&sky2->phy_lock);
793b883e 3065 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3066 sky2->rx_pending = RX_DEF_PENDING;
734d1868 3067 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 3068
3069 hw->dev[port] = dev;
3070
3071 sky2->port = port;
3072
5a5b1ea0
SH		 3073 dev->features |= NETIF_F_LLTX;
3074 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3075 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3076 if (highmem)
3077 dev->features |= NETIF_F_HIGHDMA;
793b883e 3078 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3079
d1f13708
SH		 3080#ifdef SKY2_VLAN_TAG_USED
3081 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3082 dev->vlan_rx_register = sky2_vlan_rx_register;
3083 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3084#endif
3085
cd28ab6a 3086 /* read the mac address */
793b883e 3087 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3088 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3089
3090 /* device is off until link detection */
3091 netif_carrier_off(dev);
3092 netif_stop_queue(dev);
3093
3094 return dev;
3095}
3096
28bd181a 3097static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3098{
3099 const struct sky2_port *sky2 = netdev_priv(dev);
3100
3101 if (netif_msg_probe(sky2))
3102 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3103 dev->name,
3104 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3105 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3106}
3107
fb2690a9
SH		 3108/* Handle software interrupt used during MSI test */
3109static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3110 struct pt_regs *regs)
3111{
3112 struct sky2_hw *hw = dev_id;
3113 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3114
3115 if (status == 0)
3116 return IRQ_NONE;
3117
3118 if (status & Y2_IS_IRQ_SW) {
3119 hw->msi_detected = 1;
3120 wake_up(&hw->msi_wait);
3121 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3122 }
3123 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3124
3125 return IRQ_HANDLED;
3126}
3127
3128/* Test interrupt path by forcing a a software IRQ */
3129static int __devinit sky2_test_msi(struct sky2_hw *hw)
3130{
3131 struct pci_dev *pdev = hw->pdev;
3132 int err;
3133
3134 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3135
3136 err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
3137 if (err) {
3138 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3139 pci_name(pdev), pdev->irq);
3140 return err;
3141 }
3142
3143 init_waitqueue_head (&hw->msi_wait);
3144
3145 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3146 wmb();
3147
3148 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3149
3150 if (!hw->msi_detected) {
3151 /* MSI test failed, go back to INTx mode */
3152 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3153 "switching to INTx mode. Please report this failure to "
3154 "the PCI maintainer and include system chipset information.\n",
3155 pci_name(pdev));
3156
3157 err = -EOPNOTSUPP;
3158 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3159 }
3160
3161 sky2_write32(hw, B0_IMSK, 0);
3162
3163 free_irq(pdev->irq, hw);
3164
3165 return err;
3166}
3167
cd28ab6a
SH		 3168static int __devinit sky2_probe(struct pci_dev *pdev,
3169 const struct pci_device_id *ent)
3170{
793b883e 3171 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3172 struct sky2_hw *hw;
5afa0a9c 3173 int err, pm_cap, using_dac = 0;
cd28ab6a 3174
793b883e
SH		 3175 err = pci_enable_device(pdev);
3176 if (err) {
cd28ab6a
SH		 3177 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3178 pci_name(pdev));
3179 goto err_out;
3180 }
3181
793b883e
SH		 3182 err = pci_request_regions(pdev, DRV_NAME);
3183 if (err) {
cd28ab6a
SH		 3184 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3185 pci_name(pdev));
793b883e 3186 goto err_out;
cd28ab6a
SH		 3187 }
3188
3189 pci_set_master(pdev);
3190
5afa0a9c
SH		 3191 /* Find power-management capability. */
3192 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3193 if (pm_cap == 0) {
3194 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3195 "aborting.\n");
3196 err = -EIO;
3197 goto err_out_free_regions;
3198 }
3199
d1f3d4dd
SH		 3200 if (sizeof(dma_addr_t) > sizeof(u32) &&
3201 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3202 using_dac = 1;
3203 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3204 if (err < 0) {
3205 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3206 "for consistent allocations\n", pci_name(pdev));
3207 goto err_out_free_regions;
3208 }
cd28ab6a 3209
d1f3d4dd 3210 } else {
cd28ab6a
SH		 3211 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3212 if (err) {
3213 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3214 pci_name(pdev));
3215 goto err_out_free_regions;
3216 }
3217 }
d1f3d4dd 3218
cd28ab6a 3219 err = -ENOMEM;
6aad85d6 3220 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3221 if (!hw) {
3222 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3223 pci_name(pdev));
3224 goto err_out_free_regions;
3225 }
3226
cd28ab6a 3227 hw->pdev = pdev;
cd28ab6a
SH		 3228
3229 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3230 if (!hw->regs) {
3231 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3232 pci_name(pdev));
3233 goto err_out_free_hw;
3234 }
5afa0a9c 3235 hw->pm_cap = pm_cap;
cd28ab6a 3236
56a645cc
SH		 3237#ifdef __BIG_ENDIAN
3238 /* byte swap descriptors in hardware */
3239 {
3240 u32 reg;
3241
3242 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3243 reg |= PCI_REV_DESC;
3244 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3245 }
3246#endif
3247
08c06d8a
SH		 3248 /* ring for status responses */
3249 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3250 &hw->st_dma);
3251 if (!hw->st_le)
3252 goto err_out_iounmap;
3253
cd28ab6a
SH		 3254 err = sky2_reset(hw);
3255 if (err)
793b883e 3256 goto err_out_iounmap;
cd28ab6a 3257
5f4f9dc1
SH		 3258 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3259 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
92f965e8 3260 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3261 hw->chip_id, hw->chip_rev);
cd28ab6a 3262
793b883e
SH		 3263 dev = sky2_init_netdev(hw, 0, using_dac);
3264 if (!dev)
cd28ab6a
SH		 3265 goto err_out_free_pci;
3266
793b883e
SH		 3267 err = register_netdev(dev);
3268 if (err) {
cd28ab6a
SH		 3269 printk(KERN_ERR PFX "%s: cannot register net device\n",
3270 pci_name(pdev));
3271 goto err_out_free_netdev;
3272 }
3273
3274 sky2_show_addr(dev);
3275
3276 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3277 if (register_netdev(dev1) == 0)
3278 sky2_show_addr(dev1);
3279 else {
3280 /* Failure to register second port need not be fatal */
793b883e
SH		 3281 printk(KERN_WARNING PFX
3282 "register of second port failed\n");
cd28ab6a
SH		 3283 hw->dev[1] = NULL;
3284 free_netdev(dev1);
3285 }
3286 }
3287
fb2690a9
SH		 3288 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3289 err = sky2_test_msi(hw);
3290 if (err == -EOPNOTSUPP)
3291 pci_disable_msi(pdev);
3292 else if (err)
3293 goto err_out_unregister;
3294 }
3295
3296 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
793b883e
SH		 3297 if (err) {
3298 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3299 pci_name(pdev), pdev->irq);
3300 goto err_out_unregister;
3301 }
3302
e07b1aa8 3303 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
793b883e 3304
d27ed387
SH		 3305 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) dev);
3306
793b883e
SH		 3307 pci_set_drvdata(pdev, hw);
3308
cd28ab6a
SH		 3309 return 0;
3310
793b883e 3311err_out_unregister:
fb2690a9 3312 pci_disable_msi(pdev);
793b883e
SH		 3313 if (dev1) {
3314 unregister_netdev(dev1);
3315 free_netdev(dev1);
3316 }
3317 unregister_netdev(dev);
cd28ab6a
SH		 3318err_out_free_netdev:
3319 free_netdev(dev);
cd28ab6a 3320err_out_free_pci:
793b883e 3321 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3322 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3323err_out_iounmap:
3324 iounmap(hw->regs);
3325err_out_free_hw:
3326 kfree(hw);
3327err_out_free_regions:
3328 pci_release_regions(pdev);
cd28ab6a 3329 pci_disable_device(pdev);
cd28ab6a
SH		 3330err_out:
3331 return err;
3332}
3333
3334static void __devexit sky2_remove(struct pci_dev *pdev)
3335{
793b883e 3336 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3337 struct net_device *dev0, *dev1;
3338
793b883e 3339 if (!hw)
cd28ab6a
SH		 3340 return;
3341
d27ed387
SH		 3342 del_timer_sync(&hw->idle_timer);
3343
3344 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 3345 dev0 = hw->dev[0];
793b883e
SH		 3346 dev1 = hw->dev[1];
3347 if (dev1)
3348 unregister_netdev(dev1);
cd28ab6a
SH		 3349 unregister_netdev(dev0);
3350
5afa0a9c 3351 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3352 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3353 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3354 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3355
3356 free_irq(pdev->irq, hw);
fb2690a9 3357 pci_disable_msi(pdev);
793b883e 3358 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3359 pci_release_regions(pdev);
3360 pci_disable_device(pdev);
793b883e 3361
cd28ab6a
SH		 3362 if (dev1)
3363 free_netdev(dev1);
3364 free_netdev(dev0);
3365 iounmap(hw->regs);
3366 kfree(hw);
5afa0a9c 3367
cd28ab6a
SH		 3368 pci_set_drvdata(pdev, NULL);
3369}
3370
3371#ifdef CONFIG_PM
3372static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3373{
793b883e 3374 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3375 int i;
cd28ab6a
SH		 3376
3377 for (i = 0; i < 2; i++) {
3378 struct net_device *dev = hw->dev[i];
3379
3380 if (dev) {
5afa0a9c
SH		 3381 if (!netif_running(dev))
3382 continue;
3383
3384 sky2_down(dev);
cd28ab6a 3385 netif_device_detach(dev);
cd28ab6a
SH		 3386 }
3387 }
3388
5afa0a9c 3389 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
cd28ab6a
SH		 3390}
3391
3392static int sky2_resume(struct pci_dev *pdev)
3393{
793b883e 3394 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3395 int i, err;
cd28ab6a 3396
cd28ab6a
SH		 3397 pci_restore_state(pdev);
3398 pci_enable_wake(pdev, PCI_D0, 0);
08c06d8a
SH		 3399 err = sky2_set_power_state(hw, PCI_D0);
3400 if (err)
3401 goto out;
cd28ab6a 3402
08c06d8a
SH		 3403 err = sky2_reset(hw);
3404 if (err)
3405 goto out;
cd28ab6a
SH		 3406
3407 for (i = 0; i < 2; i++) {
3408 struct net_device *dev = hw->dev[i];
08c06d8a
SH		 3409 if (dev && netif_running(dev)) {
3410 netif_device_attach(dev);
3411 err = sky2_up(dev);
3412 if (err) {
3413 printk(KERN_ERR PFX "%s: could not up: %d\n",
3414 dev->name, err);
3415 dev_close(dev);
3416 break;
5afa0a9c 3417 }
cd28ab6a
SH		 3418 }
3419 }
08c06d8a
SH		 3420out:
3421 return err;
cd28ab6a
SH		 3422}
3423#endif
3424
3425static struct pci_driver sky2_driver = {
793b883e
SH		 3426 .name = DRV_NAME,
3427 .id_table = sky2_id_table,
3428 .probe = sky2_probe,
3429 .remove = __devexit_p(sky2_remove),
cd28ab6a 3430#ifdef CONFIG_PM
793b883e
SH		 3431 .suspend = sky2_suspend,
3432 .resume = sky2_resume,
cd28ab6a
SH		 3433#endif
3434};
3435
3436static int __init sky2_init_module(void)
3437{
50241c4c 3438 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3439}
3440
3441static void __exit sky2_cleanup_module(void)
3442{
3443 pci_unregister_driver(&sky2_driver);
3444}
3445
3446module_init(sky2_init_module);
3447module_exit(sky2_cleanup_module);
3448
3449MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3450MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3451MODULE_LICENSE("GPL");
5f4f9dc1 3452MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)