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sky2: PHY register settings
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
93cd791e 53#define DRV_VERSION "1.14"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 66#define RX_SKB_ALIGN 8
22e11703 67#define RX_BUF_WRITE 16
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
cb5d9547
SH		 80#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
cd28ab6a 82static const u32 default_msg =
793b883e
SH		 83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 86
793b883e 87static int debug = -1; /* defaults above */
cd28ab6a
SH		 88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
14d0263f 91static int copybreak __read_mostly = 128;
bdb5c58e
SH		 92module_param(copybreak, int, 0);
93MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
fb2690a9
SH		 95static int disable_msi = 0;
96module_param(disable_msi, int, 0);
97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
e561a83b 99static int idle_timeout = 0;
01bd7564 100module_param(idle_timeout, int, 0);
e561a83b 101MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 102
cd28ab6a 103static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
78f0b62d 133// { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 134 { 0 }
135};
793b883e 136
cd28ab6a
SH		 137MODULE_DEVICE_TABLE(pci, sky2_id_table);
138
139/* Avoid conditionals by using array */
140static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
141static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 142static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 143
92f965e8
SH		 144/* This driver supports yukon2 chipset only */
145static const char *yukon2_name[] = {
146 "XL", /* 0xb3 */
147 "EC Ultra", /* 0xb4 */
93745494 148 "Extreme", /* 0xb5 */
92f965e8
SH		 149 "EC", /* 0xb6 */
150 "FE", /* 0xb7 */
793b883e
SH		 151};
152
793b883e 153/* Access to external PHY */
ef743d33 154static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 155{
156 int i;
157
158 gma_write16(hw, port, GM_SMI_DATA, val);
159 gma_write16(hw, port, GM_SMI_CTRL,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161
162 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 163 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 164 return 0;
793b883e 165 udelay(1);
cd28ab6a 166 }
ef743d33 167
793b883e 168 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 169 return -ETIMEDOUT;
cd28ab6a
SH		 170}
171
ef743d33 172static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 173{
174 int i;
175
793b883e 176 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 177 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
178
179 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 180 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
181 *val = gma_read16(hw, port, GM_SMI_DATA);
182 return 0;
183 }
184
793b883e 185 udelay(1);
cd28ab6a
SH		 186 }
187
ef743d33
SH		 188 return -ETIMEDOUT;
189}
190
191static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
192{
193 u16 v;
194
195 if (__gm_phy_read(hw, port, reg, &v) != 0)
196 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
197 return v;
cd28ab6a
SH		 198}
199
5afa0a9c 200
ae306cca
SH		 201static void sky2_power_on(struct sky2_hw *hw)
202{
203 /* switch power to VCC (WA for VAUX problem) */
204 sky2_write8(hw, B0_POWER_CTRL,
205 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 206
ae306cca
SH		 207 /* disable Core Clock Division, */
208 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 209
ae306cca
SH		 210 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
211 /* enable bits are inverted */
212 sky2_write8(hw, B2_Y2_CLK_GATE,
213 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
214 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
215 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
216 else
217 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 218
93745494 219 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
ae306cca 220 u32 reg1;
5afa0a9c 221
ae306cca
SH		 222 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
223 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
224 reg1 &= P_ASPM_CONTROL_MSK;
225 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
226 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
5afa0a9c 227 }
ae306cca 228}
5afa0a9c 229
ae306cca
SH		 230static void sky2_power_aux(struct sky2_hw *hw)
231{
232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
233 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
234 else
235 /* enable bits are inverted */
236 sky2_write8(hw, B2_Y2_CLK_GATE,
237 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
238 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
239 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
240
241 /* switch power to VAUX */
242 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
243 sky2_write8(hw, B0_POWER_CTRL,
244 (PC_VAUX_ENA | PC_VCC_ENA |
245 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 246}
247
d3bcfbeb 248static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 249{
250 u16 reg;
251
252 /* disable all GMAC IRQ's */
253 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
254 /* disable PHY IRQs */
255 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 256
cd28ab6a
SH		 257 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
258 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
259 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
260 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
261
262 reg = gma_read16(hw, port, GM_RX_CTRL);
263 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
264 gma_write16(hw, port, GM_RX_CTRL, reg);
265}
266
16ad91e1
SH		 267/* flow control to advertise bits */
268static const u16 copper_fc_adv[] = {
269 [FC_NONE] = 0,
270 [FC_TX] = PHY_M_AN_ASP,
271 [FC_RX] = PHY_M_AN_PC,
272 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
273};
274
275/* flow control to advertise bits when using 1000BaseX */
276static const u16 fiber_fc_adv[] = {
277 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
278 [FC_TX] = PHY_M_P_ASYM_MD_X,
279 [FC_RX] = PHY_M_P_SYM_MD_X,
280 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
281};
282
283/* flow control to GMA disable bits */
284static const u16 gm_fc_disable[] = {
285 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
286 [FC_TX] = GM_GPCR_FC_RX_DIS,
287 [FC_RX] = GM_GPCR_FC_TX_DIS,
288 [FC_BOTH] = 0,
289};
290
291
cd28ab6a
SH		 292static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
293{
294 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 295 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 296
93745494
SH		 297 if (sky2->autoneg == AUTONEG_ENABLE
298 && !(hw->chip_id == CHIP_ID_YUKON_XL
299 || hw->chip_id == CHIP_ID_YUKON_EC_U
300 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 301 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
302
303 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 304 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 305 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
306
53419c68 307 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 308 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 309 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 310 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
311 else
53419c68
SH		 312 /* set master & slave downshift counter to 1x */
313 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 314
315 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
316 }
317
318 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 319 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 320 if (hw->chip_id == CHIP_ID_YUKON_FE) {
321 /* enable automatic crossover */
322 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
323 } else {
324 /* disable energy detect */
325 ctrl &= ~PHY_M_PC_EN_DET_MSK;
326
327 /* enable automatic crossover */
328 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
329
53419c68 330 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494
SH		 331 if (sky2->autoneg == AUTONEG_ENABLE
332 && (hw->chip_id == CHIP_ID_YUKON_XL
333 || hw->chip_id == CHIP_ID_YUKON_EC_U
334 || hw->chip_id == CHIP_ID_YUKON_EX)) {
53419c68 335 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 336 ctrl &= ~PHY_M_PC_DSC_MSK;
337 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
338 }
339 }
cd28ab6a
SH		 340 } else {
341 /* workaround for deviation #4.88 (CRC errors) */
342 /* disable Automatic Crossover */
343
344 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 345 }
cd28ab6a 346
b89165f2
SH		 347 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
348
349 /* special setup for PHY 88E1112 Fiber */
350 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
351 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 352
b89165f2
SH		 353 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
354 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
355 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
356 ctrl &= ~PHY_M_MAC_MD_MSK;
357 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
358 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
359
360 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 361 /* select page 1 to access Fiber registers */
362 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 363
364 /* for SFP-module set SIGDET polarity to low */
365 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
366 ctrl |= PHY_M_FIB_SIGD_POL;
367 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 368 }
b89165f2
SH		 369
370 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 371 }
372
7800fddc 373 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 374 ct1000 = 0;
375 adv = PHY_AN_CSMA;
2eaba1a2 376 reg = 0;
cd28ab6a
SH		 377
378 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 379 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 380 if (sky2->advertising & ADVERTISED_1000baseT_Full)
381 ct1000 |= PHY_M_1000C_AFD;
382 if (sky2->advertising & ADVERTISED_1000baseT_Half)
383 ct1000 |= PHY_M_1000C_AHD;
384 if (sky2->advertising & ADVERTISED_100baseT_Full)
385 adv |= PHY_M_AN_100_FD;
386 if (sky2->advertising & ADVERTISED_100baseT_Half)
387 adv |= PHY_M_AN_100_HD;
388 if (sky2->advertising & ADVERTISED_10baseT_Full)
389 adv |= PHY_M_AN_10_FD;
390 if (sky2->advertising & ADVERTISED_10baseT_Half)
391 adv |= PHY_M_AN_10_HD;
709c6e7b 392
16ad91e1 393 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 394 } else { /* special defines for FIBER (88E1040S only) */
395 if (sky2->advertising & ADVERTISED_1000baseT_Full)
396 adv |= PHY_M_AN_1000X_AFD;
397 if (sky2->advertising & ADVERTISED_1000baseT_Half)
398 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 399
16ad91e1 400 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 401 }
cd28ab6a
SH		 402
403 /* Restart Auto-negotiation */
404 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
405 } else {
406 /* forced speed/duplex settings */
407 ct1000 = PHY_M_1000C_MSE;
408
2eaba1a2
SH		 409 /* Disable auto update for duplex flow control and speed */
410 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 411
412 switch (sky2->speed) {
413 case SPEED_1000:
414 ctrl |= PHY_CT_SP1000;
2eaba1a2 415 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 416 break;
417 case SPEED_100:
418 ctrl |= PHY_CT_SP100;
2eaba1a2 419 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 420 break;
421 }
422
2eaba1a2
SH		 423 if (sky2->duplex == DUPLEX_FULL) {
424 reg |= GM_GPCR_DUP_FULL;
425 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 426 } else if (sky2->speed < SPEED_1000)
427 sky2->flow_mode = FC_NONE;
2eaba1a2 428
2eaba1a2 429
16ad91e1 430 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 431
432 /* Forward pause packets to GMAC? */
16ad91e1 433 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 434 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
435 else
436 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 437 }
438
2eaba1a2
SH		 439 gma_write16(hw, port, GM_GP_CTRL, reg);
440
cd28ab6a
SH		 441 if (hw->chip_id != CHIP_ID_YUKON_FE)
442 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
443
444 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
445 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
446
447 /* Setup Phy LED's */
448 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
449 ledover = 0;
450
451 switch (hw->chip_id) {
452 case CHIP_ID_YUKON_FE:
453 /* on 88E3082 these bits are at 11..9 (shifted left) */
454 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
455
456 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
457
458 /* delete ACT LED control bits */
459 ctrl &= ~PHY_M_FELP_LED1_MSK;
460 /* change ACT LED control to blink mode */
461 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
462 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
463 break;
464
465 case CHIP_ID_YUKON_XL:
793b883e 466 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 467
468 /* select page 3 to access LED control register */
469 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
470
471 /* set LED Function Control register */
ed6d32c7
SH		 472 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
473 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
474 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
475 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
476 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 477
478 /* set Polarity Control register */
479 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 480 (PHY_M_POLC_LS1_P_MIX(4) |
481 PHY_M_POLC_IS0_P_MIX(4) |
482 PHY_M_POLC_LOS_CTRL(2) |
483 PHY_M_POLC_INIT_CTRL(2) |
484 PHY_M_POLC_STA1_CTRL(2) |
485 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 486
487 /* restore page register */
793b883e 488 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 489 break;
93745494 490
ed6d32c7 491 case CHIP_ID_YUKON_EC_U:
93745494 492 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 493 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
494
495 /* select page 3 to access LED control register */
496 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
497
498 /* set LED Function Control register */
499 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
500 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
501 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
502 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
503 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
504
505 /* set Blink Rate in LED Timer Control Register */
506 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
507 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
508 /* restore page register */
509 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
510 break;
cd28ab6a
SH		 511
512 default:
513 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
514 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
515 /* turn off the Rx LED (LED_RX) */
0efdf262 516 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 517 }
518
9467a8fc
SH		 519 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
520 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 521 /* apply fixes in PHY AFE */
ed6d32c7
SH		 522 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
523
977bdf06 524 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 525 gm_phy_write(hw, port, 0x18, 0xaa99);
526 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 527
977bdf06 528 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 529 gm_phy_write(hw, port, 0x18, 0xa204);
530 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 531
532 /* set page register to 0 */
9467a8fc 533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
93745494 534 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 535 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 536
977bdf06
SH		 537 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
538 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 539 ledover |= PHY_M_LED_MO_100;
977bdf06 540 }
cd28ab6a 541
977bdf06
SH		 542 if (ledover)
543 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
544
545 }
2eaba1a2 546
d571b694 547 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 548 if (sky2->autoneg == AUTONEG_ENABLE)
549 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
550 else
551 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
552}
553
d3bcfbeb
SH		 554static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
555{
556 u32 reg1;
557 static const u32 phy_power[]
558 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
559
560 /* looks like this XL is back asswards .. */
561 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
562 onoff = !onoff;
563
aed2cec4 564 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 565 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 566 if (onoff)
567 /* Turn off phy power saving */
568 reg1 &= ~phy_power[port];
569 else
570 reg1 |= phy_power[port];
571
572 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 573 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 574 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 575 udelay(100);
576}
577
1b537565
SH		 578/* Force a renegotiation */
579static void sky2_phy_reinit(struct sky2_port *sky2)
580{
e07b1aa8 581 spin_lock_bh(&sky2->phy_lock);
1b537565 582 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 583 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 584}
585
e3173832
SH		 586/* Put device in state to listen for Wake On Lan */
587static void sky2_wol_init(struct sky2_port *sky2)
588{
589 struct sky2_hw *hw = sky2->hw;
590 unsigned port = sky2->port;
591 enum flow_control save_mode;
592 u16 ctrl;
593 u32 reg1;
594
595 /* Bring hardware out of reset */
596 sky2_write16(hw, B0_CTST, CS_RST_CLR);
597 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
598
599 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
600 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
601
602 /* Force to 10/100
603 * sky2_reset will re-enable on resume
604 */
605 save_mode = sky2->flow_mode;
606 ctrl = sky2->advertising;
607
608 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
609 sky2->flow_mode = FC_NONE;
610 sky2_phy_power(hw, port, 1);
611 sky2_phy_reinit(sky2);
612
613 sky2->flow_mode = save_mode;
614 sky2->advertising = ctrl;
615
616 /* Set GMAC to no flow control and auto update for speed/duplex */
617 gma_write16(hw, port, GM_GP_CTRL,
618 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
619 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
620
621 /* Set WOL address */
622 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
623 sky2->netdev->dev_addr, ETH_ALEN);
624
625 /* Turn on appropriate WOL control bits */
626 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
627 ctrl = 0;
628 if (sky2->wol & WAKE_PHY)
629 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
630 else
631 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
632
633 if (sky2->wol & WAKE_MAGIC)
634 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
635 else
636 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
637
638 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
639 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
640
641 /* Turn on legacy PCI-Express PME mode */
642 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
643 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
644 reg1 |= PCI_Y2_PME_LEGACY;
645 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
646 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
647
648 /* block receiver */
649 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
650
651}
652
cd28ab6a
SH		 653static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
654{
655 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
656 u16 reg;
657 int i;
658 const u8 *addr = hw->dev[port]->dev_addr;
659
42eeea01
SH		 660 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
661 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 662
663 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
664
793b883e 665 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 666 /* WA DEV_472 -- looks like crossed wires on port 2 */
667 /* clear GMAC 1 Control reset */
668 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
669 do {
670 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
671 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
672 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
673 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
674 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
675 }
676
793b883e 677 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 678
2eaba1a2
SH		 679 /* Enable Transmit FIFO Underrun */
680 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
681
e07b1aa8 682 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 683 sky2_phy_init(hw, port);
e07b1aa8 684 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 685
686 /* MIB clear */
687 reg = gma_read16(hw, port, GM_PHY_ADDR);
688 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
689
43f2f104
SH		 690 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
691 gma_read16(hw, port, i);
cd28ab6a
SH		 692 gma_write16(hw, port, GM_PHY_ADDR, reg);
693
694 /* transmit control */
695 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
696
697 /* receive control reg: unicast + multicast + no FCS */
698 gma_write16(hw, port, GM_RX_CTRL,
793b883e 699 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 700
701 /* transmit flow control */
702 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
703
704 /* transmit parameter */
705 gma_write16(hw, port, GM_TX_PARAM,
706 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
707 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
708 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
709 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
710
711 /* serial mode register */
712 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 713 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 714
6b1a3aef 715 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 716 reg |= GM_SMOD_JUMBO_ENA;
717
718 gma_write16(hw, port, GM_SERIAL_MODE, reg);
719
cd28ab6a
SH		 720 /* virtual address for data */
721 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
722
793b883e
SH		 723 /* physical address: used for pause frames */
724 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
725
726 /* ignore counter overflows */
cd28ab6a
SH		 727 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
728 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
729 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
730
731 /* Configure Rx MAC FIFO */
732 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 733 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
734 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 735
d571b694 736 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 737 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 738
8df9a876
SH		 739 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
740 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 741
742 /* Configure Tx MAC FIFO */
743 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
744 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 745
93745494 746 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 747 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 748 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98
SH		 749
750 /* set Tx GMAC FIFO Almost Empty Threshold */
751 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
752 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
753
754 if (hw->dev[port]->mtu > ETH_DATA_LEN)
755 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
756 TX_JUMBO_ENA | TX_STFW_DIS);
757 else
758 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
759 TX_JUMBO_DIS | TX_STFW_ENA);
5a5b1ea0
SH		 760 }
761
cd28ab6a
SH		 762}
763
67712901
SH		 764/* Assign Ram Buffer allocation to queue */
765static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 766{
67712901
SH		 767 u32 end;
768
769 /* convert from K bytes to qwords used for hw register */
770 start *= 1024/8;
771 space *= 1024/8;
772 end = start + space - 1;
793b883e 773
cd28ab6a
SH		 774 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
775 sky2_write32(hw, RB_ADDR(q, RB_START), start);
776 sky2_write32(hw, RB_ADDR(q, RB_END), end);
777 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
778 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
779
780 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 781 u32 tp = space - space/4;
793b883e 782
1c28f6ba
SH		 783 /* On receive queue's set the thresholds
784 * give receiver priority when > 3/4 full
785 * send pause when down to 2K
786 */
787 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
788 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 789
1c28f6ba
SH		 790 tp = space - 2048/8;
791 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
792 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 793 } else {
794 /* Enable store & forward on Tx queue's because
795 * Tx FIFO is only 1K on Yukon
796 */
797 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
798 }
799
800 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 801 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 802}
803
cd28ab6a 804/* Setup Bus Memory Interface */
af4ed7e6 805static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 806{
807 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
808 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
809 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 810 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 811}
812
cd28ab6a
SH		 813/* Setup prefetch unit registers. This is the interface between
814 * hardware and driver list elements
815 */
8cc048e3 816static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 817 u64 addr, u32 last)
818{
cd28ab6a
SH		 819 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
820 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
821 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
822 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
823 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
824 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 825
826 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 827}
828
793b883e
SH		 829static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
830{
831 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
832
cb5d9547 833 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 834 le->ctrl = 0;
793b883e
SH		 835 return le;
836}
cd28ab6a 837
291ea614
SH		 838static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
839 struct sky2_tx_le *le)
840{
841 return sky2->tx_ring + (le - sky2->tx_le);
842}
843
290d4de5
SH		 844/* Update chip's next pointer */
845static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 846{
98232f85 847 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 848 wmb();
98232f85
SH		 849 sky2_write16(hw, q, idx);
850 sky2_read16(hw, q);
cd28ab6a
SH		 851}
852
793b883e 853
cd28ab6a
SH		 854static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
855{
856 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 857 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 858 le->ctrl = 0;
cd28ab6a
SH		 859 return le;
860}
861
a018e330
SH		 862/* Return high part of DMA address (could be 32 or 64 bit) */
863static inline u32 high32(dma_addr_t a)
864{
a036119f 865 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 866}
867
14d0263f
SH		 868/* Build description to hardware for one receive segment */
869static void sky2_rx_add(struct sky2_port *sky2, u8 op,
870 dma_addr_t map, unsigned len)
cd28ab6a
SH		 871{
872 struct sky2_rx_le *le;
734d1868 873 u32 hi = high32(map);
cd28ab6a 874
793b883e 875 if (sky2->rx_addr64 != hi) {
cd28ab6a 876 le = sky2_next_rx(sky2);
793b883e 877 le->addr = cpu_to_le32(hi);
cd28ab6a 878 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 879 sky2->rx_addr64 = high32(map + len);
cd28ab6a 880 }
793b883e 881
cd28ab6a 882 le = sky2_next_rx(sky2);
734d1868
SH		 883 le->addr = cpu_to_le32((u32) map);
884 le->length = cpu_to_le16(len);
14d0263f 885 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 886}
887
14d0263f
SH		 888/* Build description to hardware for one possibly fragmented skb */
889static void sky2_rx_submit(struct sky2_port *sky2,
890 const struct rx_ring_info *re)
891{
892 int i;
893
894 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
895
896 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
897 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
898}
899
900
901static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
902 unsigned size)
903{
904 struct sk_buff *skb = re->skb;
905 int i;
906
907 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
908 pci_unmap_len_set(re, data_size, size);
909
910 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
911 re->frag_addr[i] = pci_map_page(pdev,
912 skb_shinfo(skb)->frags[i].page,
913 skb_shinfo(skb)->frags[i].page_offset,
914 skb_shinfo(skb)->frags[i].size,
915 PCI_DMA_FROMDEVICE);
916}
917
918static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
919{
920 struct sk_buff *skb = re->skb;
921 int i;
922
923 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
924 PCI_DMA_FROMDEVICE);
925
926 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
927 pci_unmap_page(pdev, re->frag_addr[i],
928 skb_shinfo(skb)->frags[i].size,
929 PCI_DMA_FROMDEVICE);
930}
793b883e 931
cd28ab6a
SH		 932/* Tell chip where to start receive checksum.
933 * Actually has two checksums, but set both same to avoid possible byte
934 * order problems.
935 */
793b883e 936static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 937{
938 struct sky2_rx_le *le;
939
cd28ab6a 940 le = sky2_next_rx(sky2);
f65b138c 941 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 942 le->ctrl = 0;
943 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 944
793b883e
SH		 945 sky2_write32(sky2->hw,
946 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
947 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 948
949}
950
6b1a3aef
SH		 951/*
952 * The RX Stop command will not work for Yukon-2 if the BMU does not
953 * reach the end of packet and since we can't make sure that we have
954 * incoming data, we must reset the BMU while it is not doing a DMA
955 * transfer. Since it is possible that the RX path is still active,
956 * the RX RAM buffer will be stopped first, so any possible incoming
957 * data will not trigger a DMA. After the RAM buffer is stopped, the
958 * BMU is polled until any DMA in progress is ended and only then it
959 * will be reset.
960 */
961static void sky2_rx_stop(struct sky2_port *sky2)
962{
963 struct sky2_hw *hw = sky2->hw;
964 unsigned rxq = rxqaddr[sky2->port];
965 int i;
966
967 /* disable the RAM Buffer receive queue */
968 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
969
970 for (i = 0; i < 0xffff; i++)
971 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
972 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
973 goto stopped;
974
975 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
976 sky2->netdev->name);
977stopped:
978 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
979
980 /* reset the Rx prefetch unit */
981 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
982}
793b883e 983
d571b694 984/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 985static void sky2_rx_clean(struct sky2_port *sky2)
986{
987 unsigned i;
988
989 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 990 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 991 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 992
993 if (re->skb) {
14d0263f 994 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 995 kfree_skb(re->skb);
996 re->skb = NULL;
997 }
998 }
999}
1000
ef743d33
SH		 1001/* Basic MII support */
1002static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1003{
1004 struct mii_ioctl_data *data = if_mii(ifr);
1005 struct sky2_port *sky2 = netdev_priv(dev);
1006 struct sky2_hw *hw = sky2->hw;
1007 int err = -EOPNOTSUPP;
1008
1009 if (!netif_running(dev))
1010 return -ENODEV; /* Phy still in reset */
1011
d89e1343 1012 switch (cmd) {
ef743d33
SH		 1013 case SIOCGMIIPHY:
1014 data->phy_id = PHY_ADDR_MARV;
1015
1016 /* fallthru */
1017 case SIOCGMIIREG: {
1018 u16 val = 0;
91c86df5 1019
e07b1aa8 1020 spin_lock_bh(&sky2->phy_lock);
ef743d33 1021 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1022 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1023
ef743d33
SH		 1024 data->val_out = val;
1025 break;
1026 }
1027
1028 case SIOCSMIIREG:
1029 if (!capable(CAP_NET_ADMIN))
1030 return -EPERM;
1031
e07b1aa8 1032 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1033 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1034 data->val_in);
e07b1aa8 1035 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1036 break;
1037 }
1038 return err;
1039}
1040
d1f13708
SH		 1041#ifdef SKY2_VLAN_TAG_USED
1042static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1043{
1044 struct sky2_port *sky2 = netdev_priv(dev);
1045 struct sky2_hw *hw = sky2->hw;
1046 u16 port = sky2->port;
d1f13708 1047
2bb8c262 1048 netif_tx_lock_bh(dev);
d1f13708
SH		 1049
1050 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
1051 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
1052 sky2->vlgrp = grp;
1053
2bb8c262 1054 netif_tx_unlock_bh(dev);
d1f13708
SH		 1055}
1056
1057static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1058{
1059 struct sky2_port *sky2 = netdev_priv(dev);
1060 struct sky2_hw *hw = sky2->hw;
1061 u16 port = sky2->port;
d1f13708 1062
2bb8c262 1063 netif_tx_lock_bh(dev);
d1f13708
SH		 1064
1065 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1066 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
5c15bdec 1067 vlan_group_set_device(sky2->vlgrp, vid, NULL);
d1f13708 1068
2bb8c262 1069 netif_tx_unlock_bh(dev);
d1f13708
SH		 1070}
1071#endif
1072
82788c7a 1073/*
14d0263f
SH		 1074 * Allocate an skb for receiving. If the MTU is large enough
1075 * make the skb non-linear with a fragment list of pages.
1076 *
82788c7a
SH		 1077 * It appears the hardware has a bug in the FIFO logic that
1078 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1079 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1080 * aligned except if slab debugging is enabled.
82788c7a 1081 */
14d0263f 1082static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1083{
1084 struct sk_buff *skb;
14d0263f
SH		 1085 unsigned long p;
1086 int i;
82788c7a 1087
14d0263f
SH		 1088 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1089 if (!skb)
1090 goto nomem;
1091
1092 p = (unsigned long) skb->data;
1093 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1094
1095 for (i = 0; i < sky2->rx_nfrags; i++) {
1096 struct page *page = alloc_page(GFP_ATOMIC);
1097
1098 if (!page)
1099 goto free_partial;
1100 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1101 }
1102
1103 return skb;
14d0263f
SH		 1104free_partial:
1105 kfree_skb(skb);
1106nomem:
1107 return NULL;
82788c7a
SH		 1108}
1109
cd28ab6a
SH		 1110/*
1111 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1112 * Normal case this ends up creating one list element for skb
1113 * in the receive ring. Worst case if using large MTU and each
1114 * allocation falls on a different 64 bit region, that results
1115 * in 6 list elements per ring entry.
1116 * One element is used for checksum enable/disable, and one
1117 * extra to avoid wrap.
cd28ab6a 1118 */
6b1a3aef 1119static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1120{
6b1a3aef 1121 struct sky2_hw *hw = sky2->hw;
14d0263f 1122 struct rx_ring_info *re;
6b1a3aef 1123 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1124 unsigned i, size, space, thresh;
cd28ab6a 1125
6b1a3aef 1126 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1127 sky2_qset(hw, rxq);
977bdf06 1128
c3905bc4
SH		 1129 /* On PCI express lowering the watermark gives better performance */
1130 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1131 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1132
1133 /* These chips have no ram buffer?
1134 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1135 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1136 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1137 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
977bdf06 1138 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
977bdf06 1139
6b1a3aef
SH		 1140 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1141
1142 rx_set_checksum(sky2);
14d0263f
SH		 1143
1144 /* Space needed for frame data + headers rounded up */
1145 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1146 + 8;
1147
1148 /* Stopping point for hardware truncation */
1149 thresh = (size - 8) / sizeof(u32);
1150
1151 /* Account for overhead of skb - to avoid order > 0 allocation */
1152 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1153 + sizeof(struct skb_shared_info);
1154
1155 sky2->rx_nfrags = space >> PAGE_SHIFT;
1156 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1157
1158 if (sky2->rx_nfrags != 0) {
1159 /* Compute residue after pages */
1160 space = sky2->rx_nfrags << PAGE_SHIFT;
1161
1162 if (space < size)
1163 size -= space;
1164 else
1165 size = 0;
1166
1167 /* Optimize to handle small packets and headers */
1168 if (size < copybreak)
1169 size = copybreak;
1170 if (size < ETH_HLEN)
1171 size = ETH_HLEN;
1172 }
1173 sky2->rx_data_size = size;
1174
1175 /* Fill Rx ring */
793b883e 1176 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1177 re = sky2->rx_ring + i;
cd28ab6a 1178
14d0263f 1179 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1180 if (!re->skb)
1181 goto nomem;
1182
14d0263f
SH		 1183 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1184 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1185 }
1186
a1433ac4
SH		 1187 /*
1188 * The receiver hangs if it receives frames larger than the
1189 * packet buffer. As a workaround, truncate oversize frames, but
1190 * the register is limited to 9 bits, so if you do frames > 2052
1191 * you better get the MTU right!
1192 */
a1433ac4
SH		 1193 if (thresh > 0x1ff)
1194 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1195 else {
1196 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1197 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1198 }
1199
6b1a3aef
SH		 1200 /* Tell chip about available buffers */
1201 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1202 return 0;
1203nomem:
1204 sky2_rx_clean(sky2);
1205 return -ENOMEM;
1206}
1207
1208/* Bring up network interface. */
1209static int sky2_up(struct net_device *dev)
1210{
1211 struct sky2_port *sky2 = netdev_priv(dev);
1212 struct sky2_hw *hw = sky2->hw;
1213 unsigned port = sky2->port;
67712901 1214 u32 ramsize, imask;
ee7abb04 1215 int cap, err = -ENOMEM;
843a46f4 1216 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1217
ee7abb04
SH		 1218 /*
1219 * On dual port PCI-X card, there is an problem where status
1220 * can be received out of order due to split transactions
843a46f4 1221 */
ee7abb04
SH		 1222 if (otherdev && netif_running(otherdev) &&
1223 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1224 struct sky2_port *osky2 = netdev_priv(otherdev);
1225 u16 cmd;
1226
1227 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1228 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1229 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1230
1231 sky2->rx_csum = 0;
1232 osky2->rx_csum = 0;
1233 }
843a46f4 1234
cd28ab6a
SH		 1235 if (netif_msg_ifup(sky2))
1236 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1237
1238 /* must be power of 2 */
1239 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1240 TX_RING_SIZE *
1241 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1242 &sky2->tx_le_map);
1243 if (!sky2->tx_le)
1244 goto err_out;
1245
6cdbbdf3 1246 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1247 GFP_KERNEL);
1248 if (!sky2->tx_ring)
1249 goto err_out;
1250 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1251
1252 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1253 &sky2->rx_le_map);
1254 if (!sky2->rx_le)
1255 goto err_out;
1256 memset(sky2->rx_le, 0, RX_LE_BYTES);
1257
291ea614 1258 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1259 GFP_KERNEL);
1260 if (!sky2->rx_ring)
1261 goto err_out;
1262
d3bcfbeb
SH		 1263 sky2_phy_power(hw, port, 1);
1264
cd28ab6a
SH		 1265 sky2_mac_init(hw, port);
1266
67712901
SH		 1267 /* Register is number of 4K blocks on internal RAM buffer. */
1268 ramsize = sky2_read8(hw, B2_E_0) * 4;
1269 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1270
67712901
SH		 1271 if (ramsize > 0) {
1272 u32 rxspace;
cd28ab6a 1273
67712901
SH		 1274 if (ramsize < 16)
1275 rxspace = ramsize / 2;
1276 else
1277 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1278
67712901
SH		 1279 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1280 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1281
1282 /* Make sure SyncQ is disabled */
1283 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1284 RB_RST_SET);
1285 }
793b883e 1286
af4ed7e6 1287 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1288
977bdf06 1289 /* Set almost empty threshold */
c2716fb4
SH		 1290 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1291 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1292 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1293
6b1a3aef
SH		 1294 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1295 TX_RING_SIZE - 1);
cd28ab6a 1296
6b1a3aef 1297 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1298 if (err)
1299 goto err_out;
1300
cd28ab6a 1301 /* Enable interrupts from phy/mac for port */
e07b1aa8 1302 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1303 imask |= portirq_msk[port];
e07b1aa8
SH		 1304 sky2_write32(hw, B0_IMSK, imask);
1305
cd28ab6a
SH		 1306 return 0;
1307
1308err_out:
1b537565 1309 if (sky2->rx_le) {
cd28ab6a
SH		 1310 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1311 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1312 sky2->rx_le = NULL;
1313 }
1314 if (sky2->tx_le) {
cd28ab6a
SH		 1315 pci_free_consistent(hw->pdev,
1316 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1317 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1318 sky2->tx_le = NULL;
1319 }
1320 kfree(sky2->tx_ring);
1321 kfree(sky2->rx_ring);
cd28ab6a 1322
1b537565
SH		 1323 sky2->tx_ring = NULL;
1324 sky2->rx_ring = NULL;
cd28ab6a
SH		 1325 return err;
1326}
1327
793b883e
SH		 1328/* Modular subtraction in ring */
1329static inline int tx_dist(unsigned tail, unsigned head)
1330{
cb5d9547 1331 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1332}
cd28ab6a 1333
793b883e
SH		 1334/* Number of list elements available for next tx */
1335static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1336{
793b883e 1337 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1338}
1339
793b883e 1340/* Estimate of number of transmit list elements required */
28bd181a 1341static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1342{
793b883e
SH		 1343 unsigned count;
1344
1345 count = sizeof(dma_addr_t) / sizeof(u32);
1346 count += skb_shinfo(skb)->nr_frags * count;
1347
89114afd 1348 if (skb_is_gso(skb))
793b883e
SH		 1349 ++count;
1350
84fa7933 1351 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1352 ++count;
1353
1354 return count;
cd28ab6a
SH		 1355}
1356
793b883e
SH		 1357/*
1358 * Put one packet in ring for transmit.
1359 * A single packet can generate multiple list elements, and
1360 * the number of ring elements will probably be less than the number
1361 * of list elements used.
1362 */
cd28ab6a
SH		 1363static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1364{
1365 struct sky2_port *sky2 = netdev_priv(dev);
1366 struct sky2_hw *hw = sky2->hw;
d1f13708 1367 struct sky2_tx_le *le = NULL;
6cdbbdf3 1368 struct tx_ring_info *re;
cd28ab6a
SH		 1369 unsigned i, len;
1370 dma_addr_t mapping;
1371 u32 addr64;
1372 u16 mss;
1373 u8 ctrl;
1374
2bb8c262
SH		 1375 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1376 return NETDEV_TX_BUSY;
cd28ab6a 1377
793b883e 1378 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1379 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1380 dev->name, sky2->tx_prod, skb->len);
1381
cd28ab6a
SH		 1382 len = skb_headlen(skb);
1383 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1384 addr64 = high32(mapping);
793b883e 1385
a018e330
SH		 1386 /* Send high bits if changed or crosses boundary */
1387 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1388 le = get_tx_le(sky2);
f65b138c 1389 le->addr = cpu_to_le32(addr64);
793b883e 1390 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1391 sky2->tx_addr64 = high32(mapping + len);
793b883e 1392 }
cd28ab6a
SH		 1393
1394 /* Check for TCP Segmentation Offload */
7967168c 1395 mss = skb_shinfo(skb)->gso_size;
793b883e 1396 if (mss != 0) {
ab6a5bb6 1397 mss += tcp_optlen(skb); /* TCP options */
c9bdd4b5 1398 mss += ip_hdrlen(skb) + sizeof(struct tcphdr);
cd28ab6a
SH		 1399 mss += ETH_HLEN;
1400
e07560cd
SH		 1401 if (mss != sky2->tx_last_mss) {
1402 le = get_tx_le(sky2);
f65b138c 1403 le->addr = cpu_to_le32(mss);
e07560cd 1404 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1405 sky2->tx_last_mss = mss;
1406 }
cd28ab6a
SH		 1407 }
1408
cd28ab6a 1409 ctrl = 0;
d1f13708
SH		 1410#ifdef SKY2_VLAN_TAG_USED
1411 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1412 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1413 if (!le) {
1414 le = get_tx_le(sky2);
f65b138c 1415 le->addr = 0;
d1f13708 1416 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1417 } else
1418 le->opcode |= OP_VLAN;
1419 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1420 ctrl |= INS_VLAN;
1421 }
1422#endif
1423
1424 /* Handle TCP checksum offload */
84fa7933 1425 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d 1426 const unsigned offset = skb_transport_offset(skb);
f65b138c
SH		 1427 u32 tcpsum;
1428
1429 tcpsum = offset << 16; /* sum start */
ff1dcadb 1430 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a
SH		 1431
1432 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
eddc9ec5 1433 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
cd28ab6a
SH		 1434 ctrl |= UDPTCP;
1435
f65b138c
SH		 1436 if (tcpsum != sky2->tx_tcpsum) {
1437 sky2->tx_tcpsum = tcpsum;
1d179332
SH		 1438
1439 le = get_tx_le(sky2);
f65b138c 1440 le->addr = cpu_to_le32(tcpsum);
1d179332
SH		 1441 le->length = 0; /* initial checksum value */
1442 le->ctrl = 1; /* one packet */
1443 le->opcode = OP_TCPLISW | HW_OWNER;
1444 }
cd28ab6a
SH		 1445 }
1446
1447 le = get_tx_le(sky2);
f65b138c 1448 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1449 le->length = cpu_to_le16(len);
1450 le->ctrl = ctrl;
793b883e 1451 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1452
291ea614 1453 re = tx_le_re(sky2, le);
cd28ab6a 1454 re->skb = skb;
6cdbbdf3 1455 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1456 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1457
1458 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1459 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1460
1461 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1462 frag->size, PCI_DMA_TODEVICE);
a036119f 1463 addr64 = high32(mapping);
793b883e
SH		 1464 if (addr64 != sky2->tx_addr64) {
1465 le = get_tx_le(sky2);
f65b138c 1466 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1467 le->ctrl = 0;
1468 le->opcode = OP_ADDR64 | HW_OWNER;
1469 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1470 }
1471
1472 le = get_tx_le(sky2);
f65b138c 1473 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1474 le->length = cpu_to_le16(frag->size);
1475 le->ctrl = ctrl;
793b883e 1476 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1477
291ea614
SH		 1478 re = tx_le_re(sky2, le);
1479 re->skb = skb;
1480 pci_unmap_addr_set(re, mapaddr, mapping);
1481 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1482 }
6cdbbdf3 1483
cd28ab6a
SH		 1484 le->ctrl |= EOP;
1485
97bda706
SH		 1486 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1487 netif_stop_queue(dev);
b19666d9 1488
290d4de5 1489 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1490
cd28ab6a
SH		 1491 dev->trans_start = jiffies;
1492 return NETDEV_TX_OK;
1493}
1494
cd28ab6a 1495/*
793b883e
SH		 1496 * Free ring elements from starting at tx_cons until "done"
1497 *
1498 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1499 * buffers so make sure not to free skb to early.
cd28ab6a 1500 */
d11c13e7 1501static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1502{
d11c13e7 1503 struct net_device *dev = sky2->netdev;
af2a58ac 1504 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1505 unsigned idx;
cd28ab6a 1506
0e3ff6aa 1507 BUG_ON(done >= TX_RING_SIZE);
2224795d 1508
291ea614
SH		 1509 for (idx = sky2->tx_cons; idx != done;
1510 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1511 struct sky2_tx_le *le = sky2->tx_le + idx;
1512 struct tx_ring_info *re = sky2->tx_ring + idx;
1513
1514 switch(le->opcode & ~HW_OWNER) {
1515 case OP_LARGESEND:
1516 case OP_PACKET:
1517 pci_unmap_single(pdev,
1518 pci_unmap_addr(re, mapaddr),
1519 pci_unmap_len(re, maplen),
1520 PCI_DMA_TODEVICE);
af2a58ac 1521 break;
291ea614
SH		 1522 case OP_BUFFER:
1523 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1524 pci_unmap_len(re, maplen),
734d1868 1525 PCI_DMA_TODEVICE);
291ea614
SH		 1526 break;
1527 }
1528
1529 if (le->ctrl & EOP) {
1530 if (unlikely(netif_msg_tx_done(sky2)))
1531 printk(KERN_DEBUG "%s: tx done %u\n",
1532 dev->name, idx);
2bf56fe2 1533 sky2->net_stats.tx_packets++;
1534 sky2->net_stats.tx_bytes += re->skb->len;
1535
794b2bd2 1536 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1537 }
1538
291ea614 1539 le->opcode = 0; /* paranoia */
793b883e 1540 }
793b883e 1541
291ea614 1542 sky2->tx_cons = idx;
22e11703 1543 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1544 netif_wake_queue(dev);
cd28ab6a
SH		 1545}
1546
1547/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1548static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1549{
2bb8c262
SH		 1550 struct sky2_port *sky2 = netdev_priv(dev);
1551
1552 netif_tx_lock_bh(dev);
d11c13e7 1553 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1554 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1555}
1556
1557/* Network shutdown */
1558static int sky2_down(struct net_device *dev)
1559{
1560 struct sky2_port *sky2 = netdev_priv(dev);
1561 struct sky2_hw *hw = sky2->hw;
1562 unsigned port = sky2->port;
1563 u16 ctrl;
e07b1aa8 1564 u32 imask;
cd28ab6a 1565
1b537565
SH		 1566 /* Never really got started! */
1567 if (!sky2->tx_le)
1568 return 0;
1569
cd28ab6a
SH		 1570 if (netif_msg_ifdown(sky2))
1571 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1572
018d1c66 1573 /* Stop more packets from being queued */
cd28ab6a 1574 netif_stop_queue(dev);
9a87240c 1575 netif_carrier_off(dev);
cd28ab6a 1576
ebc646f6
SH		 1577 /* Disable port IRQ */
1578 imask = sky2_read32(hw, B0_IMSK);
1579 imask &= ~portirq_msk[port];
1580 sky2_write32(hw, B0_IMSK, imask);
1581
25d82d7a
SH		 1582 /*
1583 * Both ports share the NAPI poll on port 0, so if necessary undo the
1584 * the disable that is done in dev_close.
1585 */
1586 if (sky2->port == 0 && hw->ports > 1)
1587 netif_poll_enable(dev);
1588
d3bcfbeb 1589 sky2_gmac_reset(hw, port);
793b883e 1590
cd28ab6a
SH		 1591 /* Stop transmitter */
1592 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1593 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1594
1595 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1596 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1597
1598 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1599 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1600 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1601
1602 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1603
1604 /* Workaround shared GMAC reset */
793b883e
SH		 1605 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1606 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1607 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1608
1609 /* Disable Force Sync bit and Enable Alloc bit */
1610 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1611 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1612
1613 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1614 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1615 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1616
1617 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1618 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1619 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1620
1621 /* Reset the Tx prefetch units */
1622 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1623 PREF_UNIT_RST_SET);
1624
1625 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1626
6b1a3aef 1627 sky2_rx_stop(sky2);
cd28ab6a
SH		 1628
1629 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1630 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1631
d3bcfbeb
SH		 1632 sky2_phy_power(hw, port, 0);
1633
d571b694 1634 /* turn off LED's */
cd28ab6a
SH		 1635 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1636
018d1c66
SH		 1637 synchronize_irq(hw->pdev->irq);
1638
2bb8c262 1639 sky2_tx_clean(dev);
cd28ab6a
SH		 1640 sky2_rx_clean(sky2);
1641
1642 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1643 sky2->rx_le, sky2->rx_le_map);
1644 kfree(sky2->rx_ring);
1645
1646 pci_free_consistent(hw->pdev,
1647 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1648 sky2->tx_le, sky2->tx_le_map);
1649 kfree(sky2->tx_ring);
1650
1b537565
SH		 1651 sky2->tx_le = NULL;
1652 sky2->rx_le = NULL;
1653
1654 sky2->rx_ring = NULL;
1655 sky2->tx_ring = NULL;
1656
cd28ab6a
SH		 1657 return 0;
1658}
1659
1660static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1661{
b89165f2 1662 if (!sky2_is_copper(hw))
793b883e
SH		 1663 return SPEED_1000;
1664
cd28ab6a
SH		 1665 if (hw->chip_id == CHIP_ID_YUKON_FE)
1666 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1667
1668 switch (aux & PHY_M_PS_SPEED_MSK) {
1669 case PHY_M_PS_SPEED_1000:
1670 return SPEED_1000;
1671 case PHY_M_PS_SPEED_100:
1672 return SPEED_100;
1673 default:
1674 return SPEED_10;
1675 }
1676}
1677
1678static void sky2_link_up(struct sky2_port *sky2)
1679{
1680 struct sky2_hw *hw = sky2->hw;
1681 unsigned port = sky2->port;
1682 u16 reg;
16ad91e1
SH		 1683 static const char *fc_name[] = {
1684 [FC_NONE] = "none",
1685 [FC_TX] = "tx",
1686 [FC_RX] = "rx",
1687 [FC_BOTH] = "both",
1688 };
cd28ab6a 1689
cd28ab6a 1690 /* enable Rx/Tx */
2eaba1a2 1691 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1692 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1693 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1694
1695 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1696
1697 netif_carrier_on(sky2->netdev);
1698 netif_wake_queue(sky2->netdev);
1699
1700 /* Turn on link LED */
793b883e 1701 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1702 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1703
93745494
SH		 1704 if (hw->chip_id == CHIP_ID_YUKON_XL
1705 || hw->chip_id == CHIP_ID_YUKON_EC_U
1706 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1707 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1708 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1709
1710 switch(sky2->speed) {
1711 case SPEED_10:
1712 led |= PHY_M_LEDC_INIT_CTRL(7);
1713 break;
1714
1715 case SPEED_100:
1716 led |= PHY_M_LEDC_STA1_CTRL(7);
1717 break;
1718
1719 case SPEED_1000:
1720 led |= PHY_M_LEDC_STA0_CTRL(7);
1721 break;
1722 }
793b883e
SH		 1723
1724 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1725 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1726 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1727 }
1728
cd28ab6a
SH		 1729 if (netif_msg_link(sky2))
1730 printk(KERN_INFO PFX
d571b694 1731 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1732 sky2->netdev->name, sky2->speed,
1733 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1734 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1735}
1736
1737static void sky2_link_down(struct sky2_port *sky2)
1738{
1739 struct sky2_hw *hw = sky2->hw;
1740 unsigned port = sky2->port;
1741 u16 reg;
1742
1743 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1744
1745 reg = gma_read16(hw, port, GM_GP_CTRL);
1746 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1747 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1748
cd28ab6a
SH		 1749 netif_carrier_off(sky2->netdev);
1750 netif_stop_queue(sky2->netdev);
1751
1752 /* Turn on link LED */
1753 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1754
1755 if (netif_msg_link(sky2))
1756 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1757
cd28ab6a
SH		 1758 sky2_phy_init(hw, port);
1759}
1760
16ad91e1
SH		 1761static enum flow_control sky2_flow(int rx, int tx)
1762{
1763 if (rx)
1764 return tx ? FC_BOTH : FC_RX;
1765 else
1766 return tx ? FC_TX : FC_NONE;
1767}
1768
793b883e
SH		 1769static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1770{
1771 struct sky2_hw *hw = sky2->hw;
1772 unsigned port = sky2->port;
da4c1ff4 1773 u16 advert, lpa;
793b883e 1774
da4c1ff4 1775 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1776 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1777 if (lpa & PHY_M_AN_RF) {
1778 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1779 return -1;
1780 }
1781
793b883e
SH		 1782 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1783 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1784 sky2->netdev->name);
1785 return -1;
1786 }
1787
793b883e 1788 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1789 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1790
da4c1ff4
SH		 1791 /* Since the pause result bits seem to in different positions on
1792 * different chips. look at registers.
1793 */
1794 if (!sky2_is_copper(hw)) {
1795 /* Shift for bits in fiber PHY */
1796 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1797 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1798
1799 if (advert & ADVERTISE_1000XPAUSE)
1800 advert |= ADVERTISE_PAUSE_CAP;
1801 if (advert & ADVERTISE_1000XPSE_ASYM)
1802 advert |= ADVERTISE_PAUSE_ASYM;
1803 if (lpa & LPA_1000XPAUSE)
1804 lpa |= LPA_PAUSE_CAP;
1805 if (lpa & LPA_1000XPAUSE_ASYM)
1806 lpa |= LPA_PAUSE_ASYM;
1807 }
793b883e 1808
da4c1ff4
SH		 1809 sky2->flow_status = FC_NONE;
1810 if (advert & ADVERTISE_PAUSE_CAP) {
1811 if (lpa & LPA_PAUSE_CAP)
1812 sky2->flow_status = FC_BOTH;
1813 else if (advert & ADVERTISE_PAUSE_ASYM)
1814 sky2->flow_status = FC_RX;
1815 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1816 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1817 sky2->flow_status = FC_TX;
1818 }
793b883e 1819
16ad91e1 1820 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1821 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1822 sky2->flow_status = FC_NONE;
2eaba1a2 1823
da4c1ff4 1824 if (sky2->flow_status & FC_TX)
793b883e
SH		 1825 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1826 else
1827 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1828
1829 return 0;
1830}
cd28ab6a 1831
e07b1aa8
SH		 1832/* Interrupt from PHY */
1833static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1834{
e07b1aa8
SH		 1835 struct net_device *dev = hw->dev[port];
1836 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1837 u16 istatus, phystat;
1838
ebc646f6
SH		 1839 if (!netif_running(dev))
1840 return;
1841
e07b1aa8
SH		 1842 spin_lock(&sky2->phy_lock);
1843 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1844 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1845
cd28ab6a
SH		 1846 if (netif_msg_intr(sky2))
1847 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1848 sky2->netdev->name, istatus, phystat);
1849
2eaba1a2 1850 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1851 if (sky2_autoneg_done(sky2, phystat) == 0)
1852 sky2_link_up(sky2);
1853 goto out;
1854 }
cd28ab6a 1855
793b883e
SH		 1856 if (istatus & PHY_M_IS_LSP_CHANGE)
1857 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1858
793b883e
SH		 1859 if (istatus & PHY_M_IS_DUP_CHANGE)
1860 sky2->duplex =
1861 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1862
793b883e
SH		 1863 if (istatus & PHY_M_IS_LST_CHANGE) {
1864 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1865 sky2_link_up(sky2);
793b883e
SH		 1866 else
1867 sky2_link_down(sky2);
cd28ab6a 1868 }
793b883e 1869out:
e07b1aa8 1870 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1871}
1872
62335ab0 1873/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1874 * and tx queue is full (stopped).
1875 */
cd28ab6a
SH		 1876static void sky2_tx_timeout(struct net_device *dev)
1877{
1878 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1879 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1880
1881 if (netif_msg_timer(sky2))
1882 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1883
8f24664d 1884 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1885 dev->name, sky2->tx_cons, sky2->tx_prod,
1886 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1887 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1888
81906791
SH		 1889 /* can't restart safely under softirq */
1890 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1891}
1892
1893static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1894{
6b1a3aef
SH		 1895 struct sky2_port *sky2 = netdev_priv(dev);
1896 struct sky2_hw *hw = sky2->hw;
b628ed98 1897 unsigned port = sky2->port;
6b1a3aef
SH		 1898 int err;
1899 u16 ctl, mode;
e07b1aa8 1900 u32 imask;
cd28ab6a
SH		 1901
1902 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1903 return -EINVAL;
1904
d2adf4f6
SH		 1905 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1906 return -EINVAL;
1907
6b1a3aef
SH		 1908 if (!netif_running(dev)) {
1909 dev->mtu = new_mtu;
1910 return 0;
1911 }
1912
e07b1aa8 1913 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1914 sky2_write32(hw, B0_IMSK, 0);
1915
018d1c66
SH		 1916 dev->trans_start = jiffies; /* prevent tx timeout */
1917 netif_stop_queue(dev);
1918 netif_poll_disable(hw->dev[0]);
1919
e07b1aa8
SH		 1920 synchronize_irq(hw->pdev->irq);
1921
b628ed98
SH		 1922 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
1923 if (new_mtu > ETH_DATA_LEN) {
1924 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1925 TX_JUMBO_ENA | TX_STFW_DIS);
1926 dev->features &= NETIF_F_TSO | NETIF_F_SG | NETIF_F_IP_CSUM;
1927 } else
1928 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1929 TX_JUMBO_DIS | TX_STFW_ENA);
1930 }
1931
1932 ctl = gma_read16(hw, port, GM_GP_CTRL);
1933 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 1934 sky2_rx_stop(sky2);
1935 sky2_rx_clean(sky2);
cd28ab6a
SH		 1936
1937 dev->mtu = new_mtu;
14d0263f 1938
6b1a3aef
SH		 1939 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1940 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1941
1942 if (dev->mtu > ETH_DATA_LEN)
1943 mode |= GM_SMOD_JUMBO_ENA;
1944
b628ed98 1945 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 1946
b628ed98 1947 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1948
6b1a3aef 1949 err = sky2_rx_start(sky2);
e07b1aa8 1950 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1951
1b537565
SH		 1952 if (err)
1953 dev_close(dev);
1954 else {
b628ed98 1955 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 1956
1957 netif_poll_enable(hw->dev[0]);
1958 netif_wake_queue(dev);
1959 }
1960
cd28ab6a
SH		 1961 return err;
1962}
1963
14d0263f
SH		 1964/* For small just reuse existing skb for next receive */
1965static struct sk_buff *receive_copy(struct sky2_port *sky2,
1966 const struct rx_ring_info *re,
1967 unsigned length)
1968{
1969 struct sk_buff *skb;
1970
1971 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1972 if (likely(skb)) {
1973 skb_reserve(skb, 2);
1974 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1975 length, PCI_DMA_FROMDEVICE);
d626f62b 1976 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 1977 skb->ip_summed = re->skb->ip_summed;
1978 skb->csum = re->skb->csum;
1979 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1980 length, PCI_DMA_FROMDEVICE);
1981 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1982 skb_put(skb, length);
14d0263f
SH		 1983 }
1984 return skb;
1985}
1986
1987/* Adjust length of skb with fragments to match received data */
1988static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1989 unsigned int length)
1990{
1991 int i, num_frags;
1992 unsigned int size;
1993
1994 /* put header into skb */
1995 size = min(length, hdr_space);
1996 skb->tail += size;
1997 skb->len += size;
1998 length -= size;
1999
2000 num_frags = skb_shinfo(skb)->nr_frags;
2001 for (i = 0; i < num_frags; i++) {
2002 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2003
2004 if (length == 0) {
2005 /* don't need this page */
2006 __free_page(frag->page);
2007 --skb_shinfo(skb)->nr_frags;
2008 } else {
2009 size = min(length, (unsigned) PAGE_SIZE);
2010
2011 frag->size = size;
2012 skb->data_len += size;
2013 skb->truesize += size;
2014 skb->len += size;
2015 length -= size;
2016 }
2017 }
2018}
2019
2020/* Normal packet - take skb from ring element and put in a new one */
2021static struct sk_buff *receive_new(struct sky2_port *sky2,
2022 struct rx_ring_info *re,
2023 unsigned int length)
2024{
2025 struct sk_buff *skb, *nskb;
2026 unsigned hdr_space = sky2->rx_data_size;
2027
2028 pr_debug(PFX "receive new length=%d\n", length);
2029
2030 /* Don't be tricky about reusing pages (yet) */
2031 nskb = sky2_rx_alloc(sky2);
2032 if (unlikely(!nskb))
2033 return NULL;
2034
2035 skb = re->skb;
2036 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2037
2038 prefetch(skb->data);
2039 re->skb = nskb;
2040 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2041
2042 if (skb_shinfo(skb)->nr_frags)
2043 skb_put_frags(skb, hdr_space, length);
2044 else
489b10c1 2045 skb_put(skb, length);
14d0263f
SH		 2046 return skb;
2047}
2048
cd28ab6a
SH		 2049/*
2050 * Receive one packet.
d571b694 2051 * For larger packets, get new buffer.
cd28ab6a 2052 */
497d7c86 2053static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2054 u16 length, u32 status)
2055{
497d7c86 2056 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2057 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2058 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2059
2060 if (unlikely(netif_msg_rx_status(sky2)))
2061 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2062 dev->name, sky2->rx_next, status, length);
cd28ab6a 2063
793b883e 2064 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2065 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2066
42eeea01 2067 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2068 goto error;
2069
42eeea01
SH		 2070 if (!(status & GMR_FS_RX_OK))
2071 goto resubmit;
2072
14d0263f
SH		 2073 if (length < copybreak)
2074 skb = receive_copy(sky2, re, length);
2075 else
2076 skb = receive_new(sky2, re, length);
793b883e 2077resubmit:
14d0263f 2078 sky2_rx_submit(sky2, re);
79e57d32 2079
cd28ab6a
SH		 2080 return skb;
2081
2082error:
6e15b712 2083 ++sky2->net_stats.rx_errors;
b6d77734 2084 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2085 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2086 goto resubmit;
2087 }
6e15b712 2088
3be92a70 2089 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2090 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2091 dev->name, status, length);
793b883e
SH		 2092
2093 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2094 sky2->net_stats.rx_length_errors++;
2095 if (status & GMR_FS_FRAGMENT)
2096 sky2->net_stats.rx_frame_errors++;
2097 if (status & GMR_FS_CRC_ERR)
2098 sky2->net_stats.rx_crc_errors++;
79e57d32 2099
793b883e 2100 goto resubmit;
cd28ab6a
SH		 2101}
2102
e07b1aa8
SH		 2103/* Transmit complete */
2104static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2105{
e07b1aa8 2106 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2107
e07b1aa8 2108 if (netif_running(dev)) {
2bb8c262 2109 netif_tx_lock(dev);
e07b1aa8 2110 sky2_tx_complete(sky2, last);
2bb8c262 2111 netif_tx_unlock(dev);
2224795d 2112 }
cd28ab6a
SH		 2113}
2114
e07b1aa8
SH		 2115/* Process status response ring */
2116static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2117{
22e11703 2118 struct sky2_port *sky2;
e07b1aa8 2119 int work_done = 0;
22e11703 2120 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2121 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2122
af2a58ac 2123 rmb();
bea86103 2124
e71ebd73 2125 while (hw->st_idx != hwidx) {
13210ce5
SH		 2126 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2127 struct net_device *dev;
cd28ab6a 2128 struct sk_buff *skb;
cd28ab6a
SH		 2129 u32 status;
2130 u16 length;
2131
cb5d9547 2132 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2133
e71ebd73
SH		 2134 BUG_ON(le->link >= 2);
2135 dev = hw->dev[le->link];
13210ce5
SH		 2136
2137 sky2 = netdev_priv(dev);
f65b138c
SH		 2138 length = le16_to_cpu(le->length);
2139 status = le32_to_cpu(le->status);
cd28ab6a 2140
e71ebd73 2141 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2142 case OP_RXSTAT:
497d7c86 2143 skb = sky2_receive(dev, length, status);
d1f13708 2144 if (!skb)
5df79111 2145 goto force_update;
13210ce5 2146
13210ce5 2147 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2148 sky2->net_stats.rx_packets++;
2149 sky2->net_stats.rx_bytes += skb->len;
13210ce5
SH		 2150 dev->last_rx = jiffies;
2151
d1f13708
SH		 2152#ifdef SKY2_VLAN_TAG_USED
2153 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2154 vlan_hwaccel_receive_skb(skb,
2155 sky2->vlgrp,
2156 be16_to_cpu(sky2->rx_tag));
2157 } else
2158#endif
cd28ab6a 2159 netif_receive_skb(skb);
13210ce5 2160
22e11703
SH		 2161 /* Update receiver after 16 frames */
2162 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2163force_update:
2164 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2165 buf_write[le->link] = 0;
2166 }
2167
2168 /* Stop after net poll weight */
13210ce5
SH		 2169 if (++work_done >= to_do)
2170 goto exit_loop;
cd28ab6a
SH		 2171 break;
2172
d1f13708
SH		 2173#ifdef SKY2_VLAN_TAG_USED
2174 case OP_RXVLAN:
2175 sky2->rx_tag = length;
2176 break;
2177
2178 case OP_RXCHKSVLAN:
2179 sky2->rx_tag = length;
2180 /* fall through */
2181#endif
cd28ab6a 2182 case OP_RXCHKS:
87418307
SH		 2183 if (!sky2->rx_csum)
2184 break;
2185
2186 /* Both checksum counters are programmed to start at
2187 * the same offset, so unless there is a problem they
2188 * should match. This failure is an early indication that
2189 * hardware receive checksumming won't work.
2190 */
2191 if (likely(status >> 16 == (status & 0xffff))) {
2192 skb = sky2->rx_ring[sky2->rx_next].skb;
2193 skb->ip_summed = CHECKSUM_COMPLETE;
2194 skb->csum = status & 0xffff;
2195 } else {
2196 printk(KERN_NOTICE PFX "%s: hardware receive "
2197 "checksum problem (status = %#x)\n",
2198 dev->name, status);
2199 sky2->rx_csum = 0;
2200 sky2_write32(sky2->hw,
2201 Q_ADDR(rxqaddr[le->link], Q_CSR),
2202 BMU_DIS_RX_CHKSUM);
2203 }
cd28ab6a
SH		 2204 break;
2205
2206 case OP_TXINDEXLE:
13b97b74 2207 /* TX index reports status for both ports */
f55925d7
SH		 2208 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2209 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2210 if (hw->dev[1])
2211 sky2_tx_done(hw->dev[1],
2212 ((status >> 24) & 0xff)
2213 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2214 break;
2215
cd28ab6a
SH		 2216 default:
2217 if (net_ratelimit())
793b883e 2218 printk(KERN_WARNING PFX
e71ebd73
SH		 2219 "unknown status opcode 0x%x\n", le->opcode);
2220 goto exit_loop;
cd28ab6a 2221 }
13210ce5 2222 }
cd28ab6a 2223
fe2a24df
SH		 2224 /* Fully processed status ring so clear irq */
2225 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2226
13210ce5 2227exit_loop:
22e11703
SH		 2228 if (buf_write[0]) {
2229 sky2 = netdev_priv(hw->dev[0]);
2230 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2231 }
2232
2233 if (buf_write[1]) {
2234 sky2 = netdev_priv(hw->dev[1]);
2235 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2236 }
2237
e07b1aa8 2238 return work_done;
cd28ab6a
SH		 2239}
2240
2241static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2242{
2243 struct net_device *dev = hw->dev[port];
2244
3be92a70
SH		 2245 if (net_ratelimit())
2246 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2247 dev->name, status);
cd28ab6a
SH		 2248
2249 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2250 if (net_ratelimit())
2251 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2252 dev->name);
cd28ab6a
SH		 2253 /* Clear IRQ */
2254 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2255 }
2256
2257 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2258 if (net_ratelimit())
2259 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2260 dev->name);
cd28ab6a
SH		 2261
2262 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2263 }
2264
2265 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2266 if (net_ratelimit())
2267 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2268 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2269 }
2270
2271 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2272 if (net_ratelimit())
2273 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2274 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2275 }
2276
2277 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2278 if (net_ratelimit())
2279 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2280 dev->name);
cd28ab6a
SH		 2281 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2282 }
2283}
2284
2285static void sky2_hw_intr(struct sky2_hw *hw)
2286{
2287 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2288
793b883e 2289 if (status & Y2_IS_TIST_OV)
cd28ab6a 2290 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2291
2292 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2293 u16 pci_err;
2294
56a645cc 2295 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2296 if (net_ratelimit())
b02a9258
SH		 2297 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2298 pci_err);
cd28ab6a
SH		 2299
2300 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2301 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2302 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2303 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2304 }
2305
2306 if (status & Y2_IS_PCI_EXP) {
d571b694 2307 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2308 u32 pex_err;
2309
7bd656d1 2310 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2311
3be92a70 2312 if (net_ratelimit())
b02a9258
SH		 2313 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2314 pex_err);
cd28ab6a
SH		 2315
2316 /* clear the interrupt */
2317 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2318 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2319 0xffffffffUL);
cd28ab6a
SH		 2320 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2321
7bd656d1 2322 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2323 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2324 hwmsk &= ~Y2_IS_PCI_EXP;
2325 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2326 }
2327 }
2328
2329 if (status & Y2_HWE_L1_MASK)
2330 sky2_hw_error(hw, 0, status);
2331 status >>= 8;
2332 if (status & Y2_HWE_L1_MASK)
2333 sky2_hw_error(hw, 1, status);
2334}
2335
2336static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2337{
2338 struct net_device *dev = hw->dev[port];
2339 struct sky2_port *sky2 = netdev_priv(dev);
2340 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2341
2342 if (netif_msg_intr(sky2))
2343 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2344 dev->name, status);
2345
2346 if (status & GM_IS_RX_FF_OR) {
2347 ++sky2->net_stats.rx_fifo_errors;
2348 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2349 }
2350
2351 if (status & GM_IS_TX_FF_UR) {
2352 ++sky2->net_stats.tx_fifo_errors;
2353 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2354 }
cd28ab6a
SH		 2355}
2356
40b01727
SH		 2357/* This should never happen it is a bug. */
2358static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2359 u16 q, unsigned ring_size)
d257924e
SH		 2360{
2361 struct net_device *dev = hw->dev[port];
2362 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2363 unsigned idx;
2364 const u64 *le = (q == Q_R1 || q == Q_R2)
2365 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2366
40b01727
SH		 2367 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2368 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2369 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2370 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2371
40b01727 2372 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2373}
cd28ab6a 2374
d27ed387
SH		 2375/* If idle then force a fake soft NAPI poll once a second
2376 * to work around cases where sharing an edge triggered interrupt.
2377 */
eb35cf60
SH		 2378static inline void sky2_idle_start(struct sky2_hw *hw)
2379{
2380 if (idle_timeout > 0)
2381 mod_timer(&hw->idle_timer,
2382 jiffies + msecs_to_jiffies(idle_timeout));
2383}
2384
d27ed387
SH		 2385static void sky2_idle(unsigned long arg)
2386{
01bd7564
SH		 2387 struct sky2_hw *hw = (struct sky2_hw *) arg;
2388 struct net_device *dev = hw->dev[0];
d27ed387 2389
d27ed387
SH		 2390 if (__netif_rx_schedule_prep(dev))
2391 __netif_rx_schedule(dev);
01bd7564
SH		 2392
2393 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2394}
2395
40b01727
SH		 2396/* Hardware/software error handling */
2397static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2398{
40b01727
SH		 2399 if (net_ratelimit())
2400 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2401
1e5f1283
SH		 2402 if (status & Y2_IS_HW_ERR)
2403 sky2_hw_intr(hw);
d257924e 2404
1e5f1283
SH		 2405 if (status & Y2_IS_IRQ_MAC1)
2406 sky2_mac_intr(hw, 0);
cd28ab6a 2407
1e5f1283
SH		 2408 if (status & Y2_IS_IRQ_MAC2)
2409 sky2_mac_intr(hw, 1);
cd28ab6a 2410
1e5f1283 2411 if (status & Y2_IS_CHK_RX1)
40b01727 2412 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2413
1e5f1283 2414 if (status & Y2_IS_CHK_RX2)
40b01727 2415 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2416
1e5f1283 2417 if (status & Y2_IS_CHK_TXA1)
40b01727 2418 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2419
1e5f1283 2420 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2421 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2422}
2423
2424static int sky2_poll(struct net_device *dev0, int *budget)
2425{
2426 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2427 int work_limit = min(dev0->quota, *budget);
2428 int work_done = 0;
2429 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2430
2431 if (unlikely(status & Y2_IS_ERROR))
2432 sky2_err_intr(hw, status);
2433
2434 if (status & Y2_IS_IRQ_PHY1)
2435 sky2_phy_intr(hw, 0);
2436
2437 if (status & Y2_IS_IRQ_PHY2)
2438 sky2_phy_intr(hw, 1);
cd28ab6a 2439
1e5f1283 2440 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2441 if (work_done < work_limit) {
2442 netif_rx_complete(dev0);
86fba634 2443
fe2a24df
SH		 2444 sky2_read32(hw, B0_Y2_SP_LISR);
2445 return 0;
2446 } else {
2447 *budget -= work_done;
2448 dev0->quota -= work_done;
1e5f1283 2449 return 1;
fe2a24df 2450 }
e07b1aa8
SH		 2451}
2452
7d12e780 2453static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2454{
2455 struct sky2_hw *hw = dev_id;
2456 struct net_device *dev0 = hw->dev[0];
2457 u32 status;
2458
2459 /* Reading this mask interrupts as side effect */
2460 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2461 if (status == 0 || status == ~0)
2462 return IRQ_NONE;
793b883e 2463
e07b1aa8
SH		 2464 prefetch(&hw->st_le[hw->st_idx]);
2465 if (likely(__netif_rx_schedule_prep(dev0)))
2466 __netif_rx_schedule(dev0);
793b883e 2467
cd28ab6a
SH		 2468 return IRQ_HANDLED;
2469}
2470
2471#ifdef CONFIG_NET_POLL_CONTROLLER
2472static void sky2_netpoll(struct net_device *dev)
2473{
2474 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2475 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2476
88d11360
SH		 2477 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2478 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2479}
2480#endif
2481
2482/* Chip internal frequency for clock calculations */
fb17358f 2483static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2484{
793b883e 2485 switch (hw->chip_id) {
cd28ab6a 2486 case CHIP_ID_YUKON_EC:
5a5b1ea0 2487 case CHIP_ID_YUKON_EC_U:
93745494 2488 case CHIP_ID_YUKON_EX:
fb17358f 2489 return 125; /* 125 Mhz */
cd28ab6a 2490 case CHIP_ID_YUKON_FE:
fb17358f 2491 return 100; /* 100 Mhz */
793b883e 2492 default: /* YUKON_XL */
fb17358f 2493 return 156; /* 156 Mhz */
cd28ab6a
SH		 2494 }
2495}
2496
fb17358f 2497static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2498{
fb17358f 2499 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2500}
2501
fb17358f 2502static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2503{
fb17358f 2504 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2505}
2506
fb17358f 2507
e3173832 2508static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2509{
b89165f2 2510 u8 t8;
cd28ab6a 2511
cd28ab6a 2512 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2513
cd28ab6a
SH		 2514 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2515 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2516 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2517 hw->chip_id);
cd28ab6a
SH		 2518 return -EOPNOTSUPP;
2519 }
2520
93745494
SH		 2521 if (hw->chip_id == CHIP_ID_YUKON_EX)
2522 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2523 "Please report success or failure to <netdev@vger.kernel.org>\n");
2524
2525 /* Make sure and enable all clocks */
2526 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2527 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2528
290d4de5
SH		 2529 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2530
2531 /* This rev is really old, and requires untested workarounds */
2532 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2533 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2534 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2535 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2536 return -EOPNOTSUPP;
2537 }
2538
e3173832
SH		 2539 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2540 hw->ports = 1;
2541 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2542 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2543 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2544 ++hw->ports;
2545 }
2546
2547 return 0;
2548}
2549
2550static void sky2_reset(struct sky2_hw *hw)
2551{
2552 u16 status;
2553 int i;
2554
cd28ab6a 2555 /* disable ASF */
4f44d8ba
SH		 2556 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2557 status = sky2_read16(hw, HCU_CCSR);
2558 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2559 HCU_CCSR_UC_STATE_MSK);
2560 sky2_write16(hw, HCU_CCSR, status);
2561 } else
2562 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2563 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2564
2565 /* do a SW reset */
2566 sky2_write8(hw, B0_CTST, CS_RST_SET);
2567 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2568
2569 /* clear PCI errors, if any */
56a645cc 2570 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2571
cd28ab6a 2572 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2573 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2574
cd28ab6a
SH		 2575
2576 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2577
2578 /* clear any PEX errors */
7bd656d1
SH		 2579 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2580 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2581
cd28ab6a 2582
ae306cca 2583 sky2_power_on(hw);
cd28ab6a
SH		 2584
2585 for (i = 0; i < hw->ports; i++) {
2586 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2587 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2588 }
2589
2590 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2591
793b883e
SH		 2592 /* Clear I2C IRQ noise */
2593 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2594
2595 /* turn off hardware timer (unused) */
2596 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2597 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2598
cd28ab6a
SH		 2599 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2600
69634ee7
SH		 2601 /* Turn off descriptor polling */
2602 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2603
2604 /* Turn off receive timestamp */
2605 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2606 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2607
2608 /* enable the Tx Arbiters */
2609 for (i = 0; i < hw->ports; i++)
2610 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2611
2612 /* Initialize ram interface */
2613 for (i = 0; i < hw->ports; i++) {
793b883e 2614 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2615
2616 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2617 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2618 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2619 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2620 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2621 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2622 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2623 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2624 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2625 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2626 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2627 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2628 }
2629
7bd656d1 2630 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2631
cd28ab6a 2632 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2633 sky2_gmac_reset(hw, i);
cd28ab6a 2634
cd28ab6a
SH		 2635 memset(hw->st_le, 0, STATUS_LE_BYTES);
2636 hw->st_idx = 0;
2637
2638 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2639 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2640
2641 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2642 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2643
2644 /* Set the list last index */
793b883e 2645 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2646
290d4de5
SH		 2647 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2648 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2649
290d4de5
SH		 2650 /* set Status-FIFO ISR watermark */
2651 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2652 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2653 else
2654 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2655
290d4de5 2656 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2657 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2658 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2659
793b883e 2660 /* enable status unit */
cd28ab6a
SH		 2661 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2662
2663 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2664 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2665 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2666}
2667
81906791
SH		 2668static void sky2_restart(struct work_struct *work)
2669{
2670 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2671 struct net_device *dev;
2672 int i, err;
2673
2674 dev_dbg(&hw->pdev->dev, "restarting\n");
2675
2676 del_timer_sync(&hw->idle_timer);
2677
2678 rtnl_lock();
2679 sky2_write32(hw, B0_IMSK, 0);
2680 sky2_read32(hw, B0_IMSK);
2681
2682 netif_poll_disable(hw->dev[0]);
2683
2684 for (i = 0; i < hw->ports; i++) {
2685 dev = hw->dev[i];
2686 if (netif_running(dev))
2687 sky2_down(dev);
2688 }
2689
2690 sky2_reset(hw);
2691 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2692 netif_poll_enable(hw->dev[0]);
2693
2694 for (i = 0; i < hw->ports; i++) {
2695 dev = hw->dev[i];
2696 if (netif_running(dev)) {
2697 err = sky2_up(dev);
2698 if (err) {
2699 printk(KERN_INFO PFX "%s: could not restart %d\n",
2700 dev->name, err);
2701 dev_close(dev);
2702 }
2703 }
2704 }
2705
2706 sky2_idle_start(hw);
2707
2708 rtnl_unlock();
2709}
2710
e3173832
SH		 2711static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2712{
2713 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2714}
2715
2716static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2717{
2718 const struct sky2_port *sky2 = netdev_priv(dev);
2719
2720 wol->supported = sky2_wol_supported(sky2->hw);
2721 wol->wolopts = sky2->wol;
2722}
2723
2724static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2725{
2726 struct sky2_port *sky2 = netdev_priv(dev);
2727 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2728
e3173832
SH		 2729 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2730 return -EOPNOTSUPP;
2731
2732 sky2->wol = wol->wolopts;
2733
2734 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2735 sky2_write32(hw, B0_CTST, sky2->wol
2736 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2737
2738 if (!netif_running(dev))
2739 sky2_wol_init(sky2);
cd28ab6a
SH		 2740 return 0;
2741}
2742
28bd181a 2743static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2744{
b89165f2
SH		 2745 if (sky2_is_copper(hw)) {
2746 u32 modes = SUPPORTED_10baseT_Half
2747 | SUPPORTED_10baseT_Full
2748 | SUPPORTED_100baseT_Half
2749 | SUPPORTED_100baseT_Full
2750 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2751
2752 if (hw->chip_id != CHIP_ID_YUKON_FE)
2753 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2754 | SUPPORTED_1000baseT_Full;
2755 return modes;
cd28ab6a 2756 } else
b89165f2
SH		 2757 return SUPPORTED_1000baseT_Half
2758 | SUPPORTED_1000baseT_Full
2759 | SUPPORTED_Autoneg
2760 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2761}
2762
793b883e 2763static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2764{
2765 struct sky2_port *sky2 = netdev_priv(dev);
2766 struct sky2_hw *hw = sky2->hw;
2767
2768 ecmd->transceiver = XCVR_INTERNAL;
2769 ecmd->supported = sky2_supported_modes(hw);
2770 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2771 if (sky2_is_copper(hw)) {
cd28ab6a 2772 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2773 | SUPPORTED_10baseT_Full
2774 | SUPPORTED_100baseT_Half
2775 | SUPPORTED_100baseT_Full
2776 | SUPPORTED_1000baseT_Half
2777 | SUPPORTED_1000baseT_Full
2778 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2779 ecmd->port = PORT_TP;
b89165f2
SH		 2780 ecmd->speed = sky2->speed;
2781 } else {
2782 ecmd->speed = SPEED_1000;
cd28ab6a 2783 ecmd->port = PORT_FIBRE;
b89165f2 2784 }
cd28ab6a
SH		 2785
2786 ecmd->advertising = sky2->advertising;
2787 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2788 ecmd->duplex = sky2->duplex;
2789 return 0;
2790}
2791
2792static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2793{
2794 struct sky2_port *sky2 = netdev_priv(dev);
2795 const struct sky2_hw *hw = sky2->hw;
2796 u32 supported = sky2_supported_modes(hw);
2797
2798 if (ecmd->autoneg == AUTONEG_ENABLE) {
2799 ecmd->advertising = supported;
2800 sky2->duplex = -1;
2801 sky2->speed = -1;
2802 } else {
2803 u32 setting;
2804
793b883e 2805 switch (ecmd->speed) {
cd28ab6a
SH		 2806 case SPEED_1000:
2807 if (ecmd->duplex == DUPLEX_FULL)
2808 setting = SUPPORTED_1000baseT_Full;
2809 else if (ecmd->duplex == DUPLEX_HALF)
2810 setting = SUPPORTED_1000baseT_Half;
2811 else
2812 return -EINVAL;
2813 break;
2814 case SPEED_100:
2815 if (ecmd->duplex == DUPLEX_FULL)
2816 setting = SUPPORTED_100baseT_Full;
2817 else if (ecmd->duplex == DUPLEX_HALF)
2818 setting = SUPPORTED_100baseT_Half;
2819 else
2820 return -EINVAL;
2821 break;
2822
2823 case SPEED_10:
2824 if (ecmd->duplex == DUPLEX_FULL)
2825 setting = SUPPORTED_10baseT_Full;
2826 else if (ecmd->duplex == DUPLEX_HALF)
2827 setting = SUPPORTED_10baseT_Half;
2828 else
2829 return -EINVAL;
2830 break;
2831 default:
2832 return -EINVAL;
2833 }
2834
2835 if ((setting & supported) == 0)
2836 return -EINVAL;
2837
2838 sky2->speed = ecmd->speed;
2839 sky2->duplex = ecmd->duplex;
2840 }
2841
2842 sky2->autoneg = ecmd->autoneg;
2843 sky2->advertising = ecmd->advertising;
2844
1b537565
SH		 2845 if (netif_running(dev))
2846 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2847
2848 return 0;
2849}
2850
2851static void sky2_get_drvinfo(struct net_device *dev,
2852 struct ethtool_drvinfo *info)
2853{
2854 struct sky2_port *sky2 = netdev_priv(dev);
2855
2856 strcpy(info->driver, DRV_NAME);
2857 strcpy(info->version, DRV_VERSION);
2858 strcpy(info->fw_version, "N/A");
2859 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2860}
2861
2862static const struct sky2_stat {
793b883e
SH		 2863 char name[ETH_GSTRING_LEN];
2864 u16 offset;
cd28ab6a
SH		 2865} sky2_stats[] = {
2866 { "tx_bytes", GM_TXO_OK_HI },
2867 { "rx_bytes", GM_RXO_OK_HI },
2868 { "tx_broadcast", GM_TXF_BC_OK },
2869 { "rx_broadcast", GM_RXF_BC_OK },
2870 { "tx_multicast", GM_TXF_MC_OK },
2871 { "rx_multicast", GM_RXF_MC_OK },
2872 { "tx_unicast", GM_TXF_UC_OK },
2873 { "rx_unicast", GM_RXF_UC_OK },
2874 { "tx_mac_pause", GM_TXF_MPAUSE },
2875 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2876 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2877 { "late_collision",GM_TXF_LAT_COL },
2878 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2879 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2880 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2881
d2604540 2882 { "rx_short", GM_RXF_SHT },
cd28ab6a 2883 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2884 { "rx_64_byte_packets", GM_RXF_64B },
2885 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2886 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2887 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2888 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2889 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2890 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2891 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2892 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2893 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2894 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2895
2896 { "tx_64_byte_packets", GM_TXF_64B },
2897 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2898 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2899 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2900 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2901 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2902 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2903 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2904};
2905
cd28ab6a
SH		 2906static u32 sky2_get_rx_csum(struct net_device *dev)
2907{
2908 struct sky2_port *sky2 = netdev_priv(dev);
2909
2910 return sky2->rx_csum;
2911}
2912
2913static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2914{
2915 struct sky2_port *sky2 = netdev_priv(dev);
2916
2917 sky2->rx_csum = data;
793b883e 2918
cd28ab6a
SH		 2919 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2920 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2921
2922 return 0;
2923}
2924
2925static u32 sky2_get_msglevel(struct net_device *netdev)
2926{
2927 struct sky2_port *sky2 = netdev_priv(netdev);
2928 return sky2->msg_enable;
2929}
2930
9a7ae0a9
SH		 2931static int sky2_nway_reset(struct net_device *dev)
2932{
2933 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2934
16ad91e1 2935 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2936 return -EINVAL;
2937
1b537565 2938 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2939
2940 return 0;
2941}
2942
793b883e 2943static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2944{
2945 struct sky2_hw *hw = sky2->hw;
2946 unsigned port = sky2->port;
2947 int i;
2948
2949 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2950 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2951 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2952 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2953
793b883e 2954 for (i = 2; i < count; i++)
cd28ab6a
SH		 2955 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2956}
2957
cd28ab6a
SH		 2958static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2959{
2960 struct sky2_port *sky2 = netdev_priv(netdev);
2961 sky2->msg_enable = value;
2962}
2963
2964static int sky2_get_stats_count(struct net_device *dev)
2965{
2966 return ARRAY_SIZE(sky2_stats);
2967}
2968
2969static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2970 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2971{
2972 struct sky2_port *sky2 = netdev_priv(dev);
2973
793b883e 2974 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2975}
2976
793b883e 2977static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2978{
2979 int i;
2980
2981 switch (stringset) {
2982 case ETH_SS_STATS:
2983 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2984 memcpy(data + i * ETH_GSTRING_LEN,
2985 sky2_stats[i].name, ETH_GSTRING_LEN);
2986 break;
2987 }
2988}
2989
cd28ab6a
SH		 2990static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2991{
2992 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2993 return &sky2->net_stats;
2994}
2995
2996static int sky2_set_mac_address(struct net_device *dev, void *p)
2997{
2998 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2999 struct sky2_hw *hw = sky2->hw;
3000 unsigned port = sky2->port;
3001 const struct sockaddr *addr = p;
cd28ab6a
SH		 3002
3003 if (!is_valid_ether_addr(addr->sa_data))
3004 return -EADDRNOTAVAIL;
3005
cd28ab6a 3006 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3007 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3008 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3009 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3010 dev->dev_addr, ETH_ALEN);
1b537565 3011
a8ab1ec0
SH		 3012 /* virtual address for data */
3013 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3014
3015 /* physical address: used for pause frames */
3016 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3017
3018 return 0;
cd28ab6a
SH		 3019}
3020
a052b52f
SH		 3021static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3022{
3023 u32 bit;
3024
3025 bit = ether_crc(ETH_ALEN, addr) & 63;
3026 filter[bit >> 3] |= 1 << (bit & 7);
3027}
3028
cd28ab6a
SH		 3029static void sky2_set_multicast(struct net_device *dev)
3030{
3031 struct sky2_port *sky2 = netdev_priv(dev);
3032 struct sky2_hw *hw = sky2->hw;
3033 unsigned port = sky2->port;
3034 struct dev_mc_list *list = dev->mc_list;
3035 u16 reg;
3036 u8 filter[8];
a052b52f
SH		 3037 int rx_pause;
3038 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3039
a052b52f 3040 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3041 memset(filter, 0, sizeof(filter));
3042
3043 reg = gma_read16(hw, port, GM_RX_CTRL);
3044 reg |= GM_RXCR_UCF_ENA;
3045
d571b694 3046 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3047 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3048 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3049 memset(filter, 0xff, sizeof(filter));
a052b52f 3050 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3051 reg &= ~GM_RXCR_MCF_ENA;
3052 else {
3053 int i;
3054 reg |= GM_RXCR_MCF_ENA;
3055
a052b52f
SH		 3056 if (rx_pause)
3057 sky2_add_filter(filter, pause_mc_addr);
3058
3059 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3060 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3061 }
3062
cd28ab6a 3063 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3064 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3065 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3066 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3067 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3068 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3069 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3070 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3071
3072 gma_write16(hw, port, GM_RX_CTRL, reg);
3073}
3074
3075/* Can have one global because blinking is controlled by
3076 * ethtool and that is always under RTNL mutex
3077 */
91c86df5 3078static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3079{
793b883e
SH		 3080 u16 pg;
3081
793b883e
SH		 3082 switch (hw->chip_id) {
3083 case CHIP_ID_YUKON_XL:
3084 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3085 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3086 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3087 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3088 PHY_M_LEDC_INIT_CTRL(7) |
3089 PHY_M_LEDC_STA1_CTRL(7) |
3090 PHY_M_LEDC_STA0_CTRL(7))
3091 : 0);
3092
3093 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3094 break;
3095
3096 default:
3097 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3098 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3099 on ? PHY_M_LED_ALL : 0);
793b883e 3100 }
cd28ab6a
SH		 3101}
3102
3103/* blink LED's for finding board */
3104static int sky2_phys_id(struct net_device *dev, u32 data)
3105{
3106 struct sky2_port *sky2 = netdev_priv(dev);
3107 struct sky2_hw *hw = sky2->hw;
3108 unsigned port = sky2->port;
793b883e 3109 u16 ledctrl, ledover = 0;
cd28ab6a 3110 long ms;
91c86df5 3111 int interrupted;
cd28ab6a
SH		 3112 int onoff = 1;
3113
793b883e 3114 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3115 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3116 else
3117 ms = data * 1000;
3118
3119 /* save initial values */
e07b1aa8 3120 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3121 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3122 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3123 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3124 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3125 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3126 } else {
3127 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3128 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3129 }
cd28ab6a 3130
91c86df5
SH		 3131 interrupted = 0;
3132 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3133 sky2_led(hw, port, onoff);
3134 onoff = !onoff;
3135
e07b1aa8 3136 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3137 interrupted = msleep_interruptible(250);
e07b1aa8 3138 spin_lock_bh(&sky2->phy_lock);
91c86df5 3139
cd28ab6a
SH		 3140 ms -= 250;
3141 }
3142
3143 /* resume regularly scheduled programming */
793b883e
SH		 3144 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3145 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3146 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3147 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3148 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3149 } else {
3150 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3151 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3152 }
e07b1aa8 3153 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3154
3155 return 0;
3156}
3157
3158static void sky2_get_pauseparam(struct net_device *dev,
3159 struct ethtool_pauseparam *ecmd)
3160{
3161 struct sky2_port *sky2 = netdev_priv(dev);
3162
16ad91e1
SH		 3163 switch (sky2->flow_mode) {
3164 case FC_NONE:
3165 ecmd->tx_pause = ecmd->rx_pause = 0;
3166 break;
3167 case FC_TX:
3168 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3169 break;
3170 case FC_RX:
3171 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3172 break;
3173 case FC_BOTH:
3174 ecmd->tx_pause = ecmd->rx_pause = 1;
3175 }
3176
cd28ab6a
SH		 3177 ecmd->autoneg = sky2->autoneg;
3178}
3179
3180static int sky2_set_pauseparam(struct net_device *dev,
3181 struct ethtool_pauseparam *ecmd)
3182{
3183 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3184
3185 sky2->autoneg = ecmd->autoneg;
16ad91e1 3186 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3187
16ad91e1
SH		 3188 if (netif_running(dev))
3189 sky2_phy_reinit(sky2);
cd28ab6a 3190
2eaba1a2 3191 return 0;
cd28ab6a
SH		 3192}
3193
fb17358f
SH		 3194static int sky2_get_coalesce(struct net_device *dev,
3195 struct ethtool_coalesce *ecmd)
3196{
3197 struct sky2_port *sky2 = netdev_priv(dev);
3198 struct sky2_hw *hw = sky2->hw;
3199
3200 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3201 ecmd->tx_coalesce_usecs = 0;
3202 else {
3203 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3204 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3205 }
3206 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3207
3208 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3209 ecmd->rx_coalesce_usecs = 0;
3210 else {
3211 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3212 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3213 }
3214 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3215
3216 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3217 ecmd->rx_coalesce_usecs_irq = 0;
3218 else {
3219 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3220 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3221 }
3222
3223 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3224
3225 return 0;
3226}
3227
3228/* Note: this affect both ports */
3229static int sky2_set_coalesce(struct net_device *dev,
3230 struct ethtool_coalesce *ecmd)
3231{
3232 struct sky2_port *sky2 = netdev_priv(dev);
3233 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3234 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3235
77b3d6a2
SH		 3236 if (ecmd->tx_coalesce_usecs > tmax ||
3237 ecmd->rx_coalesce_usecs > tmax ||
3238 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3239 return -EINVAL;
3240
ff81fbbe 3241 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3242 return -EINVAL;
ff81fbbe 3243 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3244 return -EINVAL;
ff81fbbe 3245 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3246 return -EINVAL;
3247
3248 if (ecmd->tx_coalesce_usecs == 0)
3249 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3250 else {
3251 sky2_write32(hw, STAT_TX_TIMER_INI,
3252 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3253 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3254 }
3255 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3256
3257 if (ecmd->rx_coalesce_usecs == 0)
3258 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3259 else {
3260 sky2_write32(hw, STAT_LEV_TIMER_INI,
3261 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3262 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3263 }
3264 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3265
3266 if (ecmd->rx_coalesce_usecs_irq == 0)
3267 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3268 else {
d28d4870 3269 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3270 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3271 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3272 }
3273 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3274 return 0;
3275}
3276
793b883e
SH		 3277static void sky2_get_ringparam(struct net_device *dev,
3278 struct ethtool_ringparam *ering)
3279{
3280 struct sky2_port *sky2 = netdev_priv(dev);
3281
3282 ering->rx_max_pending = RX_MAX_PENDING;
3283 ering->rx_mini_max_pending = 0;
3284 ering->rx_jumbo_max_pending = 0;
3285 ering->tx_max_pending = TX_RING_SIZE - 1;
3286
3287 ering->rx_pending = sky2->rx_pending;
3288 ering->rx_mini_pending = 0;
3289 ering->rx_jumbo_pending = 0;
3290 ering->tx_pending = sky2->tx_pending;
3291}
3292
3293static int sky2_set_ringparam(struct net_device *dev,
3294 struct ethtool_ringparam *ering)
3295{
3296 struct sky2_port *sky2 = netdev_priv(dev);
3297 int err = 0;
3298
3299 if (ering->rx_pending > RX_MAX_PENDING ||
3300 ering->rx_pending < 8 ||
3301 ering->tx_pending < MAX_SKB_TX_LE ||
3302 ering->tx_pending > TX_RING_SIZE - 1)
3303 return -EINVAL;
3304
3305 if (netif_running(dev))
3306 sky2_down(dev);
3307
3308 sky2->rx_pending = ering->rx_pending;
3309 sky2->tx_pending = ering->tx_pending;
3310
1b537565 3311 if (netif_running(dev)) {
793b883e 3312 err = sky2_up(dev);
1b537565
SH		 3313 if (err)
3314 dev_close(dev);
6ed995bb
SH		 3315 else
3316 sky2_set_multicast(dev);
1b537565 3317 }
793b883e
SH		 3318
3319 return err;
3320}
3321
793b883e
SH		 3322static int sky2_get_regs_len(struct net_device *dev)
3323{
6e4cbb34 3324 return 0x4000;
793b883e
SH		 3325}
3326
3327/*
3328 * Returns copy of control register region
6e4cbb34 3329 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3330 */
3331static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3332 void *p)
3333{
3334 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3335 const void __iomem *io = sky2->hw->regs;
793b883e 3336
6e4cbb34 3337 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3338 regs->version = 1;
6e4cbb34 3339 memset(p, 0, regs->len);
793b883e 3340
6e4cbb34
SH		 3341 memcpy_fromio(p, io, B3_RAM_ADDR);
3342
3343 memcpy_fromio(p + B3_RI_WTO_R1,
3344 io + B3_RI_WTO_R1,
3345 regs->len - B3_RI_WTO_R1);
793b883e 3346}
cd28ab6a 3347
b628ed98
SH		 3348/* In order to do Jumbo packets on these chips, need to turn off the
3349 * transmit store/forward. Therefore checksum offload won't work.
3350 */
3351static int no_tx_offload(struct net_device *dev)
3352{
3353 const struct sky2_port *sky2 = netdev_priv(dev);
3354 const struct sky2_hw *hw = sky2->hw;
3355
3356 return dev->mtu > ETH_DATA_LEN &&
3357 (hw->chip_id == CHIP_ID_YUKON_EX
3358 || hw->chip_id == CHIP_ID_YUKON_EC_U);
3359}
3360
3361static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3362{
3363 if (data && no_tx_offload(dev))
3364 return -EINVAL;
3365
3366 return ethtool_op_set_tx_csum(dev, data);
3367}
3368
3369
3370static int sky2_set_tso(struct net_device *dev, u32 data)
3371{
3372 if (data && no_tx_offload(dev))
3373 return -EINVAL;
3374
3375 return ethtool_op_set_tso(dev, data);
3376}
3377
7282d491 3378static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3379 .get_settings = sky2_get_settings,
3380 .set_settings = sky2_set_settings,
e3173832
SH		 3381 .get_drvinfo = sky2_get_drvinfo,
3382 .get_wol = sky2_get_wol,
3383 .set_wol = sky2_set_wol,
793b883e
SH		 3384 .get_msglevel = sky2_get_msglevel,
3385 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3386 .nway_reset = sky2_nway_reset,
793b883e
SH		 3387 .get_regs_len = sky2_get_regs_len,
3388 .get_regs = sky2_get_regs,
3389 .get_link = ethtool_op_get_link,
3390 .get_sg = ethtool_op_get_sg,
3391 .set_sg = ethtool_op_set_sg,
3392 .get_tx_csum = ethtool_op_get_tx_csum,
b628ed98 3393 .set_tx_csum = sky2_set_tx_csum,
793b883e 3394 .get_tso = ethtool_op_get_tso,
b628ed98 3395 .set_tso = sky2_set_tso,
793b883e
SH		 3396 .get_rx_csum = sky2_get_rx_csum,
3397 .set_rx_csum = sky2_set_rx_csum,
3398 .get_strings = sky2_get_strings,
fb17358f
SH		 3399 .get_coalesce = sky2_get_coalesce,
3400 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3401 .get_ringparam = sky2_get_ringparam,
3402 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3403 .get_pauseparam = sky2_get_pauseparam,
3404 .set_pauseparam = sky2_set_pauseparam,
793b883e 3405 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3406 .get_stats_count = sky2_get_stats_count,
3407 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3408 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3409};
3410
3411/* Initialize network device */
3412static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3413 unsigned port,
3414 int highmem, int wol)
cd28ab6a
SH		 3415{
3416 struct sky2_port *sky2;
3417 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3418
3419 if (!dev) {
b02a9258 3420 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3421 return NULL;
3422 }
3423
3424 SET_MODULE_OWNER(dev);
3425 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3426 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3427 dev->open = sky2_up;
3428 dev->stop = sky2_down;
ef743d33 3429 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3430 dev->hard_start_xmit = sky2_xmit_frame;
3431 dev->get_stats = sky2_get_stats;
3432 dev->set_multicast_list = sky2_set_multicast;
3433 dev->set_mac_address = sky2_set_mac_address;
3434 dev->change_mtu = sky2_change_mtu;
3435 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3436 dev->tx_timeout = sky2_tx_timeout;
3437 dev->watchdog_timeo = TX_WATCHDOG;
3438 if (port == 0)
3439 dev->poll = sky2_poll;
3440 dev->weight = NAPI_WEIGHT;
3441#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3442 /* Network console (only works on port 0)
3443 * because netpoll makes assumptions about NAPI
3444 */
3445 if (port == 0)
3446 dev->poll_controller = sky2_netpoll;
cd28ab6a 3447#endif
cd28ab6a
SH		 3448
3449 sky2 = netdev_priv(dev);
3450 sky2->netdev = dev;
3451 sky2->hw = hw;
3452 sky2->msg_enable = netif_msg_init(debug, default_msg);
3453
cd28ab6a
SH		 3454 /* Auto speed and flow control */
3455 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3456 sky2->flow_mode = FC_BOTH;
3457
cd28ab6a
SH		 3458 sky2->duplex = -1;
3459 sky2->speed = -1;
3460 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3461 sky2->rx_csum = 1;
e3173832 3462 sky2->wol = wol;
75d070c5 3463
e07b1aa8 3464 spin_lock_init(&sky2->phy_lock);
793b883e 3465 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3466 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3467
3468 hw->dev[port] = dev;
3469
3470 sky2->port = port;
3471
4a50a876 3472 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3473 if (highmem)
3474 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3475
d1f13708
SH		 3476#ifdef SKY2_VLAN_TAG_USED
3477 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3478 dev->vlan_rx_register = sky2_vlan_rx_register;
3479 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3480#endif
3481
cd28ab6a 3482 /* read the mac address */
793b883e 3483 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3484 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3485
3486 /* device is off until link detection */
3487 netif_carrier_off(dev);
3488 netif_stop_queue(dev);
3489
3490 return dev;
3491}
3492
28bd181a 3493static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3494{
3495 const struct sky2_port *sky2 = netdev_priv(dev);
3496
3497 if (netif_msg_probe(sky2))
3498 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3499 dev->name,
3500 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3501 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3502}
3503
fb2690a9 3504/* Handle software interrupt used during MSI test */
7d12e780 3505static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3506{
3507 struct sky2_hw *hw = dev_id;
3508 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3509
3510 if (status == 0)
3511 return IRQ_NONE;
3512
3513 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3514 hw->msi = 1;
fb2690a9
SH		 3515 wake_up(&hw->msi_wait);
3516 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3517 }
3518 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3519
3520 return IRQ_HANDLED;
3521}
3522
3523/* Test interrupt path by forcing a a software IRQ */
3524static int __devinit sky2_test_msi(struct sky2_hw *hw)
3525{
3526 struct pci_dev *pdev = hw->pdev;
3527 int err;
3528
bb507fe1
SH		 3529 init_waitqueue_head (&hw->msi_wait);
3530
fb2690a9
SH		 3531 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3532
b0a20ded 3533 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3534 if (err) {
b02a9258 3535 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3536 return err;
3537 }
3538
fb2690a9 3539 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3540 sky2_read8(hw, B0_CTST);
fb2690a9 3541
b0a20ded 3542 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3543
b0a20ded 3544 if (!hw->msi) {
fb2690a9 3545 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3546 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3547 "switching to INTx mode.\n");
fb2690a9
SH		 3548
3549 err = -EOPNOTSUPP;
3550 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3551 }
3552
3553 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3554 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3555
3556 free_irq(pdev->irq, hw);
3557
3558 return err;
3559}
3560
e3173832
SH		 3561static int __devinit pci_wake_enabled(struct pci_dev *dev)
3562{
3563 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3564 u16 value;
3565
3566 if (!pm)
3567 return 0;
3568 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3569 return 0;
3570 return value & PCI_PM_CTRL_PME_ENABLE;
3571}
3572
cd28ab6a
SH		 3573static int __devinit sky2_probe(struct pci_dev *pdev,
3574 const struct pci_device_id *ent)
3575{
7f60c64b 3576 struct net_device *dev;
cd28ab6a 3577 struct sky2_hw *hw;
e3173832 3578 int err, using_dac = 0, wol_default;
cd28ab6a 3579
793b883e
SH		 3580 err = pci_enable_device(pdev);
3581 if (err) {
b02a9258 3582 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3583 goto err_out;
3584 }
3585
793b883e
SH		 3586 err = pci_request_regions(pdev, DRV_NAME);
3587 if (err) {
b02a9258 3588 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 3589 goto err_out_disable;
cd28ab6a
SH		 3590 }
3591
3592 pci_set_master(pdev);
3593
d1f3d4dd
SH		 3594 if (sizeof(dma_addr_t) > sizeof(u32) &&
3595 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3596 using_dac = 1;
3597 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3598 if (err < 0) {
b02a9258
SH		 3599 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3600 "for consistent allocations\n");
d1f3d4dd
SH		 3601 goto err_out_free_regions;
3602 }
d1f3d4dd 3603 } else {
cd28ab6a
SH		 3604 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3605 if (err) {
b02a9258 3606 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3607 goto err_out_free_regions;
3608 }
3609 }
d1f3d4dd 3610
e3173832
SH		 3611 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3612
cd28ab6a 3613 err = -ENOMEM;
6aad85d6 3614 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3615 if (!hw) {
b02a9258 3616 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3617 goto err_out_free_regions;
3618 }
3619
cd28ab6a 3620 hw->pdev = pdev;
cd28ab6a
SH		 3621
3622 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3623 if (!hw->regs) {
b02a9258 3624 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3625 goto err_out_free_hw;
3626 }
3627
56a645cc 3628#ifdef __BIG_ENDIAN
f65b138c
SH		 3629 /* The sk98lin vendor driver uses hardware byte swapping but
3630 * this driver uses software swapping.
3631 */
56a645cc
SH		 3632 {
3633 u32 reg;
56a645cc 3634 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3635 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3636 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3637 }
3638#endif
3639
08c06d8a
SH		 3640 /* ring for status responses */
3641 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3642 &hw->st_dma);
3643 if (!hw->st_le)
3644 goto err_out_iounmap;
3645
e3173832 3646 err = sky2_init(hw);
cd28ab6a 3647 if (err)
793b883e 3648 goto err_out_iounmap;
cd28ab6a 3649
b02a9258 3650 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3651 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3652 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3653 hw->chip_id, hw->chip_rev);
cd28ab6a 3654
e3173832
SH		 3655 sky2_reset(hw);
3656
3657 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3658 if (!dev) {
3659 err = -ENOMEM;
cd28ab6a 3660 goto err_out_free_pci;
7f60c64b 3661 }
cd28ab6a 3662
9fa1b1f3
SH		 3663 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3664 err = sky2_test_msi(hw);
3665 if (err == -EOPNOTSUPP)
3666 pci_disable_msi(pdev);
3667 else if (err)
3668 goto err_out_free_netdev;
3669 }
3670
793b883e
SH		 3671 err = register_netdev(dev);
3672 if (err) {
b02a9258 3673 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 3674 goto err_out_free_netdev;
3675 }
3676
b0a20ded
SH		 3677 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3678 dev->name, hw);
9fa1b1f3 3679 if (err) {
b02a9258 3680 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 3681 goto err_out_unregister;
3682 }
3683 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3684
cd28ab6a
SH		 3685 sky2_show_addr(dev);
3686
7f60c64b 3687 if (hw->ports > 1) {
3688 struct net_device *dev1;
3689
e3173832 3690 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 3691 if (!dev1)
3692 dev_warn(&pdev->dev, "allocation for second device failed\n");
3693 else if ((err = register_netdev(dev1))) {
3694 dev_warn(&pdev->dev,
3695 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 3696 hw->dev[1] = NULL;
3697 free_netdev(dev1);
b02a9258
SH		 3698 } else
3699 sky2_show_addr(dev1);
cd28ab6a
SH		 3700 }
3701
01bd7564 3702 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
81906791
SH		 3703 INIT_WORK(&hw->restart_work, sky2_restart);
3704
eb35cf60 3705 sky2_idle_start(hw);
d27ed387 3706
793b883e
SH		 3707 pci_set_drvdata(pdev, hw);
3708
cd28ab6a
SH		 3709 return 0;
3710
793b883e 3711err_out_unregister:
b0a20ded
SH		 3712 if (hw->msi)
3713 pci_disable_msi(pdev);
793b883e 3714 unregister_netdev(dev);
cd28ab6a
SH		 3715err_out_free_netdev:
3716 free_netdev(dev);
cd28ab6a 3717err_out_free_pci:
793b883e 3718 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3719 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3720err_out_iounmap:
3721 iounmap(hw->regs);
3722err_out_free_hw:
3723 kfree(hw);
3724err_out_free_regions:
3725 pci_release_regions(pdev);
44a1d2e5 3726err_out_disable:
cd28ab6a 3727 pci_disable_device(pdev);
cd28ab6a 3728err_out:
549a68c3 3729 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 3730 return err;
3731}
3732
3733static void __devexit sky2_remove(struct pci_dev *pdev)
3734{
793b883e 3735 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3736 struct net_device *dev0, *dev1;
3737
793b883e 3738 if (!hw)
cd28ab6a
SH		 3739 return;
3740
d27ed387
SH		 3741 del_timer_sync(&hw->idle_timer);
3742
81906791
SH		 3743 flush_scheduled_work();
3744
d27ed387 3745 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3746 synchronize_irq(hw->pdev->irq);
3747
cd28ab6a 3748 dev0 = hw->dev[0];
793b883e
SH		 3749 dev1 = hw->dev[1];
3750 if (dev1)
3751 unregister_netdev(dev1);
cd28ab6a
SH		 3752 unregister_netdev(dev0);
3753
ae306cca
SH		 3754 sky2_power_aux(hw);
3755
cd28ab6a 3756 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3757 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3758 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3759
3760 free_irq(pdev->irq, hw);
b0a20ded
SH		 3761 if (hw->msi)
3762 pci_disable_msi(pdev);
793b883e 3763 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3764 pci_release_regions(pdev);
3765 pci_disable_device(pdev);
793b883e 3766
cd28ab6a
SH		 3767 if (dev1)
3768 free_netdev(dev1);
3769 free_netdev(dev0);
3770 iounmap(hw->regs);
3771 kfree(hw);
5afa0a9c 3772
cd28ab6a
SH		 3773 pci_set_drvdata(pdev, NULL);
3774}
3775
3776#ifdef CONFIG_PM
3777static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3778{
793b883e 3779 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 3780 int i, wol = 0;
cd28ab6a 3781
549a68c3
SH		 3782 if (!hw)
3783 return 0;
3784
eb35cf60 3785 del_timer_sync(&hw->idle_timer);
6a5706b9 3786 netif_poll_disable(hw->dev[0]);
eb35cf60 3787
f05267e7 3788 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3789 struct net_device *dev = hw->dev[i];
e3173832 3790 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3791
e3173832 3792 if (netif_running(dev))
5afa0a9c 3793 sky2_down(dev);
e3173832
SH		 3794
3795 if (sky2->wol)
3796 sky2_wol_init(sky2);
3797
3798 wol |= sky2->wol;
cd28ab6a
SH		 3799 }
3800
8ab8fca2 3801 sky2_write32(hw, B0_IMSK, 0);
ae306cca 3802 sky2_power_aux(hw);
e3173832 3803
d374c1c1 3804 pci_save_state(pdev);
e3173832 3805 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 3806 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3807
2ccc99b7 3808 return 0;
cd28ab6a
SH		 3809}
3810
3811static int sky2_resume(struct pci_dev *pdev)
3812{
793b883e 3813 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3814 int i, err;
cd28ab6a 3815
549a68c3
SH		 3816 if (!hw)
3817 return 0;
3818
ae306cca
SH		 3819 err = pci_set_power_state(pdev, PCI_D0);
3820 if (err)
3821 goto out;
3822
3823 err = pci_restore_state(pdev);
3824 if (err)
3825 goto out;
3826
cd28ab6a 3827 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 3828
3829 /* Re-enable all clocks */
3830 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3831 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3832
e3173832 3833 sky2_reset(hw);
cd28ab6a 3834
8ab8fca2
SH		 3835 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3836
f05267e7 3837 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3838 struct net_device *dev = hw->dev[i];
6a5706b9 3839 if (netif_running(dev)) {
08c06d8a
SH		 3840 err = sky2_up(dev);
3841 if (err) {
3842 printk(KERN_ERR PFX "%s: could not up: %d\n",
3843 dev->name, err);
3844 dev_close(dev);
eb35cf60 3845 goto out;
5afa0a9c 3846 }
cd28ab6a
SH		 3847 }
3848 }
eb35cf60 3849
6a5706b9 3850 netif_poll_enable(hw->dev[0]);
eb35cf60 3851 sky2_idle_start(hw);
ae306cca 3852 return 0;
08c06d8a 3853out:
b02a9258 3854 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 3855 pci_disable_device(pdev);
08c06d8a 3856 return err;
cd28ab6a
SH		 3857}
3858#endif
3859
e3173832
SH		 3860static void sky2_shutdown(struct pci_dev *pdev)
3861{
3862 struct sky2_hw *hw = pci_get_drvdata(pdev);
3863 int i, wol = 0;
3864
549a68c3
SH		 3865 if (!hw)
3866 return;
3867
e3173832
SH		 3868 del_timer_sync(&hw->idle_timer);
3869 netif_poll_disable(hw->dev[0]);
3870
3871 for (i = 0; i < hw->ports; i++) {
3872 struct net_device *dev = hw->dev[i];
3873 struct sky2_port *sky2 = netdev_priv(dev);
3874
3875 if (sky2->wol) {
3876 wol = 1;
3877 sky2_wol_init(sky2);
3878 }
3879 }
3880
3881 if (wol)
3882 sky2_power_aux(hw);
3883
3884 pci_enable_wake(pdev, PCI_D3hot, wol);
3885 pci_enable_wake(pdev, PCI_D3cold, wol);
3886
3887 pci_disable_device(pdev);
3888 pci_set_power_state(pdev, PCI_D3hot);
3889
3890}
3891
cd28ab6a 3892static struct pci_driver sky2_driver = {
793b883e
SH		 3893 .name = DRV_NAME,
3894 .id_table = sky2_id_table,
3895 .probe = sky2_probe,
3896 .remove = __devexit_p(sky2_remove),
cd28ab6a 3897#ifdef CONFIG_PM
793b883e
SH		 3898 .suspend = sky2_suspend,
3899 .resume = sky2_resume,
cd28ab6a 3900#endif
e3173832 3901 .shutdown = sky2_shutdown,
cd28ab6a
SH		 3902};
3903
3904static int __init sky2_init_module(void)
3905{
50241c4c 3906 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3907}
3908
3909static void __exit sky2_cleanup_module(void)
3910{
3911 pci_unregister_driver(&sky2_driver);
3912}
3913
3914module_init(sky2_init_module);
3915module_exit(sky2_cleanup_module);
3916
3917MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 3918MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 3919MODULE_LICENSE("GPL");
5f4f9dc1 3920MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)