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KVM: x86 emulator: introduce struct x86_exception to communicate faults
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
a03490ed
CO		 63#define CR0_RESERVED_BITS \
64 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
65 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
66 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
67#define CR4_RESERVED_BITS \
68 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
69 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
70 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 71 | X86_CR4_OSXSAVE \
a03490ed
CO		 72 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
73
74#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 75
76#define KVM_MAX_MCE_BANKS 32
5854dbca 77#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 78
50a37eb4
JR		 79/* EFER defaults:
80 * - enable syscall per default because its emulated by KVM
81 * - enable LME and LMA per default on 64 bit KVM
82 */
83#ifdef CONFIG_X86_64
84static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
85#else
86static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 93static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
94 struct kvm_cpuid_entry2 __user *entries);
95
97896d04 96struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
ed85c068
AP		 99int ignore_msrs = 0;
100module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
101
18863bdd
AK		 102#define KVM_NR_SHARED_MSRS 16
103
104struct kvm_shared_msrs_global {
105 int nr;
2bf78fa7 106 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 107};
108
109struct kvm_shared_msrs {
110 struct user_return_notifier urn;
111 bool registered;
2bf78fa7
SY		 112 struct kvm_shared_msr_values {
113 u64 host;
114 u64 curr;
115 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 116};
117
118static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
119static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
120
417bc304 121struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 122 { "pf_fixed", VCPU_STAT(pf_fixed) },
123 { "pf_guest", VCPU_STAT(pf_guest) },
124 { "tlb_flush", VCPU_STAT(tlb_flush) },
125 { "invlpg", VCPU_STAT(invlpg) },
126 { "exits", VCPU_STAT(exits) },
127 { "io_exits", VCPU_STAT(io_exits) },
128 { "mmio_exits", VCPU_STAT(mmio_exits) },
129 { "signal_exits", VCPU_STAT(signal_exits) },
130 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 131 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 132 { "halt_exits", VCPU_STAT(halt_exits) },
133 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 134 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 135 { "request_irq", VCPU_STAT(request_irq_exits) },
136 { "irq_exits", VCPU_STAT(irq_exits) },
137 { "host_state_reload", VCPU_STAT(host_state_reload) },
138 { "efer_reload", VCPU_STAT(efer_reload) },
139 { "fpu_reload", VCPU_STAT(fpu_reload) },
140 { "insn_emulation", VCPU_STAT(insn_emulation) },
141 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 142 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 143 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 144 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
145 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
146 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
147 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
148 { "mmu_flooded", VM_STAT(mmu_flooded) },
149 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 150 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 151 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 152 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 153 { "largepages", VM_STAT(lpages) },
417bc304
HB		 154 { NULL }
155};
156
2acf923e
DC		 157u64 __read_mostly host_xcr0;
158
af585b92
GN		 159static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
160{
161 int i;
162 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
163 vcpu->arch.apf.gfns[i] = ~0;
164}
165
18863bdd
AK		 166static void kvm_on_user_return(struct user_return_notifier *urn)
167{
168 unsigned slot;
18863bdd
AK		 169 struct kvm_shared_msrs *locals
170 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 171 struct kvm_shared_msr_values *values;
18863bdd
AK		 172
173 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 174 values = &locals->values[slot];
175 if (values->host != values->curr) {
176 wrmsrl(shared_msrs_global.msrs[slot], values->host);
177 values->curr = values->host;
18863bdd
AK		 178 }
179 }
180 locals->registered = false;
181 user_return_notifier_unregister(urn);
182}
183
2bf78fa7 184static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 185{
2bf78fa7 186 struct kvm_shared_msrs *smsr;
18863bdd
AK		 187 u64 value;
188
2bf78fa7
SY		 189 smsr = &__get_cpu_var(shared_msrs);
190 /* only read, and nobody should modify it at this time,
191 * so don't need lock */
192 if (slot >= shared_msrs_global.nr) {
193 printk(KERN_ERR "kvm: invalid MSR slot!");
194 return;
195 }
196 rdmsrl_safe(msr, &value);
197 smsr->values[slot].host = value;
198 smsr->values[slot].curr = value;
199}
200
201void kvm_define_shared_msr(unsigned slot, u32 msr)
202{
18863bdd
AK		 203 if (slot >= shared_msrs_global.nr)
204 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 205 shared_msrs_global.msrs[slot] = msr;
206 /* we need ensured the shared_msr_global have been updated */
207 smp_wmb();
18863bdd
AK		 208}
209EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
210
211static void kvm_shared_msr_cpu_online(void)
212{
213 unsigned i;
18863bdd
AK		 214
215 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 216 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 217}
218
d5696725 219void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
2bf78fa7 223 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 224 return;
2bf78fa7
SY		 225 smsr->values[slot].curr = value;
226 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 227 if (!smsr->registered) {
228 smsr->urn.on_user_return = kvm_on_user_return;
229 user_return_notifier_register(&smsr->urn);
230 smsr->registered = true;
231 }
232}
233EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
234
3548bab5
AK		 235static void drop_user_return_notifiers(void *ignore)
236{
237 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
238
239 if (smsr->registered)
240 kvm_on_user_return(&smsr->urn);
241}
242
6866b83e
CO		 243u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
244{
245 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e 247 else
ad312c7c 248 return vcpu->arch.apic_base;
6866b83e
CO		 249}
250EXPORT_SYMBOL_GPL(kvm_get_apic_base);
251
252void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
253{
254 /* TODO: reserve bits check */
255 if (irqchip_in_kernel(vcpu->kvm))
256 kvm_lapic_set_base(vcpu, data);
257 else
ad312c7c 258 vcpu->arch.apic_base = data;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_set_apic_base);
261
3fd28fce
ED		 262#define EXCPT_BENIGN 0
263#define EXCPT_CONTRIBUTORY 1
264#define EXCPT_PF 2
265
266static int exception_class(int vector)
267{
268 switch (vector) {
269 case PF_VECTOR:
270 return EXCPT_PF;
271 case DE_VECTOR:
272 case TS_VECTOR:
273 case NP_VECTOR:
274 case SS_VECTOR:
275 case GP_VECTOR:
276 return EXCPT_CONTRIBUTORY;
277 default:
278 break;
279 }
280 return EXCPT_BENIGN;
281}
282
283static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 284 unsigned nr, bool has_error, u32 error_code,
285 bool reinject)
3fd28fce
ED		 286{
287 u32 prev_nr;
288 int class1, class2;
289
3842d135
AK		 290 kvm_make_request(KVM_REQ_EVENT, vcpu);
291
3fd28fce
ED		 292 if (!vcpu->arch.exception.pending) {
293 queue:
294 vcpu->arch.exception.pending = true;
295 vcpu->arch.exception.has_error_code = has_error;
296 vcpu->arch.exception.nr = nr;
297 vcpu->arch.exception.error_code = error_code;
3f0fd292 298 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 299 return;
300 }
301
302 /* to check exception */
303 prev_nr = vcpu->arch.exception.nr;
304 if (prev_nr == DF_VECTOR) {
305 /* triple fault -> shutdown */
a8eeb04a 306 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 307 return;
308 }
309 class1 = exception_class(prev_nr);
310 class2 = exception_class(nr);
311 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
312 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
313 /* generate double fault per SDM Table 5-5 */
314 vcpu->arch.exception.pending = true;
315 vcpu->arch.exception.has_error_code = true;
316 vcpu->arch.exception.nr = DF_VECTOR;
317 vcpu->arch.exception.error_code = 0;
318 } else
319 /* replace previous exception with a new one in a hope
320 that instruction re-execution will regenerate lost
321 exception */
322 goto queue;
323}
324
298101da
AK		 325void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
326{
ce7ddec4 327 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 328}
329EXPORT_SYMBOL_GPL(kvm_queue_exception);
330
ce7ddec4
JR		 331void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
333 kvm_multiple_exception(vcpu, nr, false, 0, true);
334}
335EXPORT_SYMBOL_GPL(kvm_requeue_exception);
336
8df25a32 337void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
c3c91fee 338{
8df25a32
JR		 339 unsigned error_code = vcpu->arch.fault.error_code;
340
c3c91fee 341 ++vcpu->stat.pf_guest;
8df25a32 342 vcpu->arch.cr2 = vcpu->arch.fault.address;
c3c91fee
AK		 343 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
344}
345
d4f8cf66
JR		 346void kvm_propagate_fault(struct kvm_vcpu *vcpu)
347{
0959ffac 348 if (mmu_is_nested(vcpu) && !vcpu->arch.fault.nested)
d4f8cf66
JR		 349 vcpu->arch.nested_mmu.inject_page_fault(vcpu);
350 else
351 vcpu->arch.mmu.inject_page_fault(vcpu);
0959ffac
JR		 352
353 vcpu->arch.fault.nested = false;
d4f8cf66
JR		 354}
355
3419ffc8
SY		 356void kvm_inject_nmi(struct kvm_vcpu *vcpu)
357{
3842d135 358 kvm_make_request(KVM_REQ_EVENT, vcpu);
3419ffc8
SY		 359 vcpu->arch.nmi_pending = 1;
360}
361EXPORT_SYMBOL_GPL(kvm_inject_nmi);
362
298101da
AK		 363void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
364{
ce7ddec4 365 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 366}
367EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
368
ce7ddec4
JR		 369void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
370{
371 kvm_multiple_exception(vcpu, nr, true, error_code, true);
372}
373EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
374
0a79b009
AK		 375/*
376 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
377 * a #GP and return false.
378 */
379bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 380{
0a79b009
AK		 381 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
382 return true;
383 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
384 return false;
298101da 385}
0a79b009 386EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 387
ec92fe44
JR		 388/*
389 * This function will be used to read from the physical memory of the currently
390 * running guest. The difference to kvm_read_guest_page is that this function
391 * can read from guest physical or from the guest's guest physical memory.
392 */
393int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
394 gfn_t ngfn, void *data, int offset, int len,
395 u32 access)
396{
397 gfn_t real_gfn;
398 gpa_t ngpa;
399
400 ngpa = gfn_to_gpa(ngfn);
401 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
402 if (real_gfn == UNMAPPED_GVA)
403 return -EFAULT;
404
405 real_gfn = gpa_to_gfn(real_gfn);
406
407 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
408}
409EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
410
3d06b8bf
JR		 411int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
412 void *data, int offset, int len, u32 access)
413{
414 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
415 data, offset, len, access);
416}
417
a03490ed
CO		 418/*
419 * Load the pae pdptrs. Return true is they are all valid.
420 */
ff03a073 421int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 422{
423 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
424 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
425 int i;
426 int ret;
ff03a073 427 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 428
ff03a073
JR		 429 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
430 offset * sizeof(u64), sizeof(pdpte),
431 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 432 if (ret < 0) {
433 ret = 0;
434 goto out;
435 }
436 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 437 if (is_present_gpte(pdpte[i]) &&
20c466b5 438 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 439 ret = 0;
440 goto out;
441 }
442 }
443 ret = 1;
444
ff03a073 445 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 446 __set_bit(VCPU_EXREG_PDPTR,
447 (unsigned long *)&vcpu->arch.regs_avail);
448 __set_bit(VCPU_EXREG_PDPTR,
449 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 450out:
a03490ed
CO		 451
452 return ret;
453}
cc4b6871 454EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 455
d835dfec
AK		 456static bool pdptrs_changed(struct kvm_vcpu *vcpu)
457{
ff03a073 458 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 459 bool changed = true;
3d06b8bf
JR		 460 int offset;
461 gfn_t gfn;
d835dfec
AK		 462 int r;
463
464 if (is_long_mode(vcpu) || !is_pae(vcpu))
465 return false;
466
6de4f3ad
AK		 467 if (!test_bit(VCPU_EXREG_PDPTR,
468 (unsigned long *)&vcpu->arch.regs_avail))
469 return true;
470
3d06b8bf
JR		 471 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
472 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
473 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
474 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 475 if (r < 0)
476 goto out;
ff03a073 477 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 478out:
d835dfec
AK		 479
480 return changed;
481}
482
49a9b07e 483int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 484{
aad82703
SY		 485 unsigned long old_cr0 = kvm_read_cr0(vcpu);
486 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
487 X86_CR0_CD | X86_CR0_NW;
488
f9a48e6a
AK		 489 cr0 |= X86_CR0_ET;
490
ab344828 491#ifdef CONFIG_X86_64
0f12244f
GN		 492 if (cr0 & 0xffffffff00000000UL)
493 return 1;
ab344828
GN		 494#endif
495
496 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 497
0f12244f
GN		 498 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
499 return 1;
a03490ed 500
0f12244f
GN		 501 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
502 return 1;
a03490ed
CO		 503
504 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
505#ifdef CONFIG_X86_64
f6801dff 506 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 507 int cs_db, cs_l;
508
0f12244f
GN		 509 if (!is_pae(vcpu))
510 return 1;
a03490ed 511 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 512 if (cs_l)
513 return 1;
a03490ed
CO		 514 } else
515#endif
ff03a073
JR		 516 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
517 vcpu->arch.cr3))
0f12244f 518 return 1;
a03490ed
CO		 519 }
520
521 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 522
e5f3f027
XG		 523 if ((cr0 ^ old_cr0) & X86_CR0_PG)
524 kvm_clear_async_pf_completion_queue(vcpu);
525
aad82703
SY		 526 if ((cr0 ^ old_cr0) & update_bits)
527 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 528 return 0;
529}
2d3ad1f4 530EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 531
2d3ad1f4 532void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 533{
49a9b07e 534 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 535}
2d3ad1f4 536EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 537
2acf923e
DC		 538int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
539{
540 u64 xcr0;
541
542 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
543 if (index != XCR_XFEATURE_ENABLED_MASK)
544 return 1;
545 xcr0 = xcr;
546 if (kvm_x86_ops->get_cpl(vcpu) != 0)
547 return 1;
548 if (!(xcr0 & XSTATE_FP))
549 return 1;
550 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
551 return 1;
552 if (xcr0 & ~host_xcr0)
553 return 1;
554 vcpu->arch.xcr0 = xcr0;
555 vcpu->guest_xcr0_loaded = 0;
556 return 0;
557}
558
559int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
560{
561 if (__kvm_set_xcr(vcpu, index, xcr)) {
562 kvm_inject_gp(vcpu, 0);
563 return 1;
564 }
565 return 0;
566}
567EXPORT_SYMBOL_GPL(kvm_set_xcr);
568
569static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
570{
571 struct kvm_cpuid_entry2 *best;
572
573 best = kvm_find_cpuid_entry(vcpu, 1, 0);
574 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
575}
576
577static void update_cpuid(struct kvm_vcpu *vcpu)
578{
579 struct kvm_cpuid_entry2 *best;
580
581 best = kvm_find_cpuid_entry(vcpu, 1, 0);
582 if (!best)
583 return;
584
585 /* Update OSXSAVE bit */
586 if (cpu_has_xsave && best->function == 0x1) {
587 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
588 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
589 best->ecx |= bit(X86_FEATURE_OSXSAVE);
590 }
591}
592
a83b29c6 593int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 594{
fc78f519 595 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 596 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
597
0f12244f
GN		 598 if (cr4 & CR4_RESERVED_BITS)
599 return 1;
a03490ed 600
2acf923e
DC		 601 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
602 return 1;
603
a03490ed 604 if (is_long_mode(vcpu)) {
0f12244f
GN		 605 if (!(cr4 & X86_CR4_PAE))
606 return 1;
a2edf57f
AK		 607 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
608 && ((cr4 ^ old_cr4) & pdptr_bits)
ff03a073 609 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
0f12244f
GN		 610 return 1;
611
612 if (cr4 & X86_CR4_VMXE)
613 return 1;
a03490ed 614
a03490ed 615 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 616
aad82703
SY		 617 if ((cr4 ^ old_cr4) & pdptr_bits)
618 kvm_mmu_reset_context(vcpu);
0f12244f 619
2acf923e
DC		 620 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
621 update_cpuid(vcpu);
622
0f12244f
GN		 623 return 0;
624}
2d3ad1f4 625EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 626
2390218b 627int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 628{
ad312c7c 629 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 630 kvm_mmu_sync_roots(vcpu);
d835dfec 631 kvm_mmu_flush_tlb(vcpu);
0f12244f 632 return 0;
d835dfec
AK		 633 }
634
a03490ed 635 if (is_long_mode(vcpu)) {
0f12244f
GN		 636 if (cr3 & CR3_L_MODE_RESERVED_BITS)
637 return 1;
a03490ed
CO		 638 } else {
639 if (is_pae(vcpu)) {
0f12244f
GN		 640 if (cr3 & CR3_PAE_RESERVED_BITS)
641 return 1;
ff03a073
JR		 642 if (is_paging(vcpu) &&
643 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 644 return 1;
a03490ed
CO		 645 }
646 /*
647 * We don't check reserved bits in nonpae mode, because
648 * this isn't enforced, and VMware depends on this.
649 */
650 }
651
a03490ed
CO		 652 /*
653 * Does the new cr3 value map to physical memory? (Note, we
654 * catch an invalid cr3 even in real-mode, because it would
655 * cause trouble later on when we turn on paging anyway.)
656 *
657 * A real CPU would silently accept an invalid cr3 and would
658 * attempt to use it - with largely undefined (and often hard
659 * to debug) behavior on the guest side.
660 */
661 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 662 return 1;
663 vcpu->arch.cr3 = cr3;
664 vcpu->arch.mmu.new_cr3(vcpu);
665 return 0;
666}
2d3ad1f4 667EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 668
0f12244f 669int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 670{
0f12244f
GN		 671 if (cr8 & CR8_RESERVED_BITS)
672 return 1;
a03490ed
CO		 673 if (irqchip_in_kernel(vcpu->kvm))
674 kvm_lapic_set_tpr(vcpu, cr8);
675 else
ad312c7c 676 vcpu->arch.cr8 = cr8;
0f12244f
GN		 677 return 0;
678}
679
680void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
681{
682 if (__kvm_set_cr8(vcpu, cr8))
683 kvm_inject_gp(vcpu, 0);
a03490ed 684}
2d3ad1f4 685EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 686
2d3ad1f4 687unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 688{
689 if (irqchip_in_kernel(vcpu->kvm))
690 return kvm_lapic_get_cr8(vcpu);
691 else
ad312c7c 692 return vcpu->arch.cr8;
a03490ed 693}
2d3ad1f4 694EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 695
338dbc97 696static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 697{
698 switch (dr) {
699 case 0 ... 3:
700 vcpu->arch.db[dr] = val;
701 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
702 vcpu->arch.eff_db[dr] = val;
703 break;
704 case 4:
338dbc97
GN		 705 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
706 return 1; /* #UD */
020df079
GN		 707 /* fall through */
708 case 6:
338dbc97
GN		 709 if (val & 0xffffffff00000000ULL)
710 return -1; /* #GP */
020df079
GN		 711 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
712 break;
713 case 5:
338dbc97
GN		 714 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
715 return 1; /* #UD */
020df079
GN		 716 /* fall through */
717 default: /* 7 */
338dbc97
GN		 718 if (val & 0xffffffff00000000ULL)
719 return -1; /* #GP */
020df079
GN		 720 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
721 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
722 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
723 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
724 }
725 break;
726 }
727
728 return 0;
729}
338dbc97
GN		 730
731int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
732{
733 int res;
734
735 res = __kvm_set_dr(vcpu, dr, val);
736 if (res > 0)
737 kvm_queue_exception(vcpu, UD_VECTOR);
738 else if (res < 0)
739 kvm_inject_gp(vcpu, 0);
740
741 return res;
742}
020df079
GN		 743EXPORT_SYMBOL_GPL(kvm_set_dr);
744
338dbc97 745static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 746{
747 switch (dr) {
748 case 0 ... 3:
749 *val = vcpu->arch.db[dr];
750 break;
751 case 4:
338dbc97 752 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 753 return 1;
020df079
GN		 754 /* fall through */
755 case 6:
756 *val = vcpu->arch.dr6;
757 break;
758 case 5:
338dbc97 759 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 760 return 1;
020df079
GN		 761 /* fall through */
762 default: /* 7 */
763 *val = vcpu->arch.dr7;
764 break;
765 }
766
767 return 0;
768}
338dbc97
GN		 769
770int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
771{
772 if (_kvm_get_dr(vcpu, dr, val)) {
773 kvm_queue_exception(vcpu, UD_VECTOR);
774 return 1;
775 }
776 return 0;
777}
020df079
GN		 778EXPORT_SYMBOL_GPL(kvm_get_dr);
779
043405e1
CO		 780/*
781 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
782 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
783 *
784 * This list is modified at module load time to reflect the
e3267cbb
GC		 785 * capabilities of the host cpu. This capabilities test skips MSRs that are
786 * kvm-specific. Those are put in the beginning of the list.
043405e1 787 */
e3267cbb 788
344d9588 789#define KVM_SAVE_MSRS_BEGIN 8
043405e1 790static u32 msrs_to_save[] = {
e3267cbb 791 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 792 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 793 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
344d9588 794 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
043405e1 795 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 796 MSR_STAR,
043405e1
CO		 797#ifdef CONFIG_X86_64
798 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
799#endif
e90aa41e 800 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 801};
802
803static unsigned num_msrs_to_save;
804
805static u32 emulated_msrs[] = {
806 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 807 MSR_IA32_MCG_STATUS,
808 MSR_IA32_MCG_CTL,
043405e1
CO		 809};
810
b69e8cae 811static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 812{
aad82703
SY		 813 u64 old_efer = vcpu->arch.efer;
814
b69e8cae
RJ		 815 if (efer & efer_reserved_bits)
816 return 1;
15c4a640
CO		 817
818 if (is_paging(vcpu)
b69e8cae
RJ		 819 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
820 return 1;
15c4a640 821
1b2fd70c
AG		 822 if (efer & EFER_FFXSR) {
823 struct kvm_cpuid_entry2 *feat;
824
825 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 826 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
827 return 1;
1b2fd70c
AG		 828 }
829
d8017474
AG		 830 if (efer & EFER_SVME) {
831 struct kvm_cpuid_entry2 *feat;
832
833 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 834 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
835 return 1;
d8017474
AG		 836 }
837
15c4a640 838 efer &= ~EFER_LMA;
f6801dff 839 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 840
a3d204e2
SY		 841 kvm_x86_ops->set_efer(vcpu, efer);
842
9645bb56 843 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 844
aad82703
SY		 845 /* Update reserved bits */
846 if ((efer ^ old_efer) & EFER_NX)
847 kvm_mmu_reset_context(vcpu);
848
b69e8cae 849 return 0;
15c4a640
CO		 850}
851
f2b4b7dd
JR		 852void kvm_enable_efer_bits(u64 mask)
853{
854 efer_reserved_bits &= ~mask;
855}
856EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
857
858
15c4a640
CO		 859/*
860 * Writes msr value into into the appropriate "register".
861 * Returns 0 on success, non-0 otherwise.
862 * Assumes vcpu_load() was already called.
863 */
864int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
865{
866 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
867}
868
313a3dc7
CO		 869/*
870 * Adapt set_msr() to msr_io()'s calling convention
871 */
872static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
873{
874 return kvm_set_msr(vcpu, index, *data);
875}
876
18068523
GOC		 877static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
878{
9ed3c444
AK		 879 int version;
880 int r;
50d0a0f9 881 struct pvclock_wall_clock wc;
923de3cf 882 struct timespec boot;
18068523
GOC		 883
884 if (!wall_clock)
885 return;
886
9ed3c444
AK		 887 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
888 if (r)
889 return;
890
891 if (version & 1)
892 ++version; /* first time write, random junk */
893
894 ++version;
18068523 895
18068523
GOC		 896 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
897
50d0a0f9
GH		 898 /*
899 * The guest calculates current wall clock time by adding
34c238a1 900 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 901 * wall clock specified here. guest system time equals host
902 * system time for us, thus we must fill in host boot time here.
903 */
923de3cf 904 getboottime(&boot);
50d0a0f9
GH		 905
906 wc.sec = boot.tv_sec;
907 wc.nsec = boot.tv_nsec;
908 wc.version = version;
18068523
GOC		 909
910 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
911
912 version++;
913 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 914}
915
50d0a0f9
GH		 916static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
917{
918 uint32_t quotient, remainder;
919
920 /* Don't try to replace with do_div(), this one calculates
921 * "(dividend << 32) / divisor" */
922 __asm__ ( "divl %4"
923 : "=a" (quotient), "=d" (remainder)
924 : "0" (0), "1" (dividend), "r" (divisor) );
925 return quotient;
926}
927
5f4e3f88
ZA		 928static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
929 s8 *pshift, u32 *pmultiplier)
50d0a0f9 930{
5f4e3f88 931 uint64_t scaled64;
50d0a0f9
GH		 932 int32_t shift = 0;
933 uint64_t tps64;
934 uint32_t tps32;
935
5f4e3f88
ZA		 936 tps64 = base_khz * 1000LL;
937 scaled64 = scaled_khz * 1000LL;
50933623 938 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 939 tps64 >>= 1;
940 shift--;
941 }
942
943 tps32 = (uint32_t)tps64;
50933623
JK		 944 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
945 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 946 scaled64 >>= 1;
947 else
948 tps32 <<= 1;
50d0a0f9
GH		 949 shift++;
950 }
951
5f4e3f88
ZA		 952 *pshift = shift;
953 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 954
5f4e3f88
ZA		 955 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
956 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 957}
958
759379dd
ZA		 959static inline u64 get_kernel_ns(void)
960{
961 struct timespec ts;
962
963 WARN_ON(preemptible());
964 ktime_get_ts(&ts);
965 monotonic_to_bootbased(&ts);
966 return timespec_to_ns(&ts);
50d0a0f9
GH		 967}
968
c8076604 969static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 970unsigned long max_tsc_khz;
c8076604 971
8cfdc000
ZA		 972static inline int kvm_tsc_changes_freq(void)
973{
974 int cpu = get_cpu();
975 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
976 cpufreq_quick_get(cpu) != 0;
977 put_cpu();
978 return ret;
979}
980
759379dd
ZA		 981static inline u64 nsec_to_cycles(u64 nsec)
982{
217fc9cf
AK		 983 u64 ret;
984
759379dd
ZA		 985 WARN_ON(preemptible());
986 if (kvm_tsc_changes_freq())
987 printk_once(KERN_WARNING
988 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 989 ret = nsec * __get_cpu_var(cpu_tsc_khz);
990 do_div(ret, USEC_PER_SEC);
991 return ret;
759379dd
ZA		 992}
993
c285545f
ZA		 994static void kvm_arch_set_tsc_khz(struct kvm *kvm, u32 this_tsc_khz)
995{
996 /* Compute a scale to convert nanoseconds in TSC cycles */
997 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
998 &kvm->arch.virtual_tsc_shift,
999 &kvm->arch.virtual_tsc_mult);
1000 kvm->arch.virtual_tsc_khz = this_tsc_khz;
1001}
1002
1003static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1004{
1005 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1006 vcpu->kvm->arch.virtual_tsc_mult,
1007 vcpu->kvm->arch.virtual_tsc_shift);
1008 tsc += vcpu->arch.last_tsc_write;
1009 return tsc;
1010}
1011
99e3e30a
ZA		 1012void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1013{
1014 struct kvm *kvm = vcpu->kvm;
f38e098f 1015 u64 offset, ns, elapsed;
99e3e30a 1016 unsigned long flags;
46543ba4 1017 s64 sdiff;
99e3e30a
ZA		 1018
1019 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1020 offset = data - native_read_tsc();
759379dd 1021 ns = get_kernel_ns();
f38e098f 1022 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1023 sdiff = data - kvm->arch.last_tsc_write;
1024 if (sdiff < 0)
1025 sdiff = -sdiff;
f38e098f
ZA		 1026
1027 /*
46543ba4 1028 * Special case: close write to TSC within 5 seconds of
f38e098f 1029 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 1030 * The 5 seconds is to accomodate host load / swapping as
1031 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1032 *
1033 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1034 * or make a best guest using elapsed value.
f38e098f 1035 */
46543ba4
ZA		 1036 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1037 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1038 if (!check_tsc_unstable()) {
1039 offset = kvm->arch.last_tsc_offset;
1040 pr_debug("kvm: matched tsc offset for %llu\n", data);
1041 } else {
759379dd
ZA		 1042 u64 delta = nsec_to_cycles(elapsed);
1043 offset += delta;
1044 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1045 }
1046 ns = kvm->arch.last_tsc_nsec;
1047 }
1048 kvm->arch.last_tsc_nsec = ns;
1049 kvm->arch.last_tsc_write = data;
1050 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1051 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1052 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1053
1054 /* Reset of TSC must disable overshoot protection below */
1055 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1056 vcpu->arch.last_tsc_write = data;
1057 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1058}
1059EXPORT_SYMBOL_GPL(kvm_write_tsc);
1060
34c238a1 1061static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1062{
18068523
GOC		 1063 unsigned long flags;
1064 struct kvm_vcpu_arch *vcpu = &v->arch;
1065 void *shared_kaddr;
463656c0 1066 unsigned long this_tsc_khz;
1d5f066e
ZA		 1067 s64 kernel_ns, max_kernel_ns;
1068 u64 tsc_timestamp;
18068523 1069
18068523
GOC		 1070 /* Keep irq disabled to prevent changes to the clock */
1071 local_irq_save(flags);
1d5f066e 1072 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1073 kernel_ns = get_kernel_ns();
8cfdc000 1074 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523 1075
8cfdc000 1076 if (unlikely(this_tsc_khz == 0)) {
c285545f 1077 local_irq_restore(flags);
34c238a1 1078 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1079 return 1;
1080 }
18068523 1081
c285545f
ZA		 1082 /*
1083 * We may have to catch up the TSC to match elapsed wall clock
1084 * time for two reasons, even if kvmclock is used.
1085 * 1) CPU could have been running below the maximum TSC rate
1086 * 2) Broken TSC compensation resets the base at each VCPU
1087 * entry to avoid unknown leaps of TSC even when running
1088 * again on the same CPU. This may cause apparent elapsed
1089 * time to disappear, and the guest to stand still or run
1090 * very slowly.
1091 */
1092 if (vcpu->tsc_catchup) {
1093 u64 tsc = compute_guest_tsc(v, kernel_ns);
1094 if (tsc > tsc_timestamp) {
1095 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1096 tsc_timestamp = tsc;
1097 }
50d0a0f9
GH		 1098 }
1099
18068523
GOC		 1100 local_irq_restore(flags);
1101
c285545f
ZA		 1102 if (!vcpu->time_page)
1103 return 0;
18068523 1104
1d5f066e
ZA		 1105 /*
1106 * Time as measured by the TSC may go backwards when resetting the base
1107 * tsc_timestamp. The reason for this is that the TSC resolution is
1108 * higher than the resolution of the other clock scales. Thus, many
1109 * possible measurments of the TSC correspond to one measurement of any
1110 * other clock, and so a spread of values is possible. This is not a
1111 * problem for the computation of the nanosecond clock; with TSC rates
1112 * around 1GHZ, there can only be a few cycles which correspond to one
1113 * nanosecond value, and any path through this code will inevitably
1114 * take longer than that. However, with the kernel_ns value itself,
1115 * the precision may be much lower, down to HZ granularity. If the
1116 * first sampling of TSC against kernel_ns ends in the low part of the
1117 * range, and the second in the high end of the range, we can get:
1118 *
1119 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1120 *
1121 * As the sampling errors potentially range in the thousands of cycles,
1122 * it is possible such a time value has already been observed by the
1123 * guest. To protect against this, we must compute the system time as
1124 * observed by the guest and ensure the new system time is greater.
1125 */
1126 max_kernel_ns = 0;
1127 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1128 max_kernel_ns = vcpu->last_guest_tsc -
1129 vcpu->hv_clock.tsc_timestamp;
1130 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1131 vcpu->hv_clock.tsc_to_system_mul,
1132 vcpu->hv_clock.tsc_shift);
1133 max_kernel_ns += vcpu->last_kernel_ns;
1134 }
afbcf7ab 1135
e48672fa 1136 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1137 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1138 &vcpu->hv_clock.tsc_shift,
1139 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1140 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1141 }
1142
1d5f066e
ZA		 1143 if (max_kernel_ns > kernel_ns)
1144 kernel_ns = max_kernel_ns;
1145
8cfdc000 1146 /* With all the info we got, fill in the values */
1d5f066e 1147 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1148 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1149 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1150 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1151 vcpu->hv_clock.flags = 0;
1152
18068523
GOC		 1153 /*
1154 * The interface expects us to write an even number signaling that the
1155 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1156 * state, we just increase by 2 at the end.
18068523 1157 */
50d0a0f9 1158 vcpu->hv_clock.version += 2;
18068523
GOC		 1159
1160 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1161
1162 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1163 sizeof(vcpu->hv_clock));
18068523
GOC		 1164
1165 kunmap_atomic(shared_kaddr, KM_USER0);
1166
1167 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1168 return 0;
c8076604
GH		 1169}
1170
9ba075a6
AK		 1171static bool msr_mtrr_valid(unsigned msr)
1172{
1173 switch (msr) {
1174 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1175 case MSR_MTRRfix64K_00000:
1176 case MSR_MTRRfix16K_80000:
1177 case MSR_MTRRfix16K_A0000:
1178 case MSR_MTRRfix4K_C0000:
1179 case MSR_MTRRfix4K_C8000:
1180 case MSR_MTRRfix4K_D0000:
1181 case MSR_MTRRfix4K_D8000:
1182 case MSR_MTRRfix4K_E0000:
1183 case MSR_MTRRfix4K_E8000:
1184 case MSR_MTRRfix4K_F0000:
1185 case MSR_MTRRfix4K_F8000:
1186 case MSR_MTRRdefType:
1187 case MSR_IA32_CR_PAT:
1188 return true;
1189 case 0x2f8:
1190 return true;
1191 }
1192 return false;
1193}
1194
d6289b93
MT		 1195static bool valid_pat_type(unsigned t)
1196{
1197 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1198}
1199
1200static bool valid_mtrr_type(unsigned t)
1201{
1202 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1203}
1204
1205static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1206{
1207 int i;
1208
1209 if (!msr_mtrr_valid(msr))
1210 return false;
1211
1212 if (msr == MSR_IA32_CR_PAT) {
1213 for (i = 0; i < 8; i++)
1214 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1215 return false;
1216 return true;
1217 } else if (msr == MSR_MTRRdefType) {
1218 if (data & ~0xcff)
1219 return false;
1220 return valid_mtrr_type(data & 0xff);
1221 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1222 for (i = 0; i < 8 ; i++)
1223 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1224 return false;
1225 return true;
1226 }
1227
1228 /* variable MTRRs */
1229 return valid_mtrr_type(data & 0xff);
1230}
1231
9ba075a6
AK		 1232static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1233{
0bed3b56
SY		 1234 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1235
d6289b93 1236 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1237 return 1;
1238
0bed3b56
SY		 1239 if (msr == MSR_MTRRdefType) {
1240 vcpu->arch.mtrr_state.def_type = data;
1241 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1242 } else if (msr == MSR_MTRRfix64K_00000)
1243 p[0] = data;
1244 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1245 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1246 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1247 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1248 else if (msr == MSR_IA32_CR_PAT)
1249 vcpu->arch.pat = data;
1250 else { /* Variable MTRRs */
1251 int idx, is_mtrr_mask;
1252 u64 *pt;
1253
1254 idx = (msr - 0x200) / 2;
1255 is_mtrr_mask = msr - 0x200 - 2 * idx;
1256 if (!is_mtrr_mask)
1257 pt =
1258 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1259 else
1260 pt =
1261 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1262 *pt = data;
1263 }
1264
1265 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1266 return 0;
1267}
15c4a640 1268
890ca9ae 1269static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1270{
890ca9ae
HY		 1271 u64 mcg_cap = vcpu->arch.mcg_cap;
1272 unsigned bank_num = mcg_cap & 0xff;
1273
15c4a640 1274 switch (msr) {
15c4a640 1275 case MSR_IA32_MCG_STATUS:
890ca9ae 1276 vcpu->arch.mcg_status = data;
15c4a640 1277 break;
c7ac679c 1278 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1279 if (!(mcg_cap & MCG_CTL_P))
1280 return 1;
1281 if (data != 0 && data != ~(u64)0)
1282 return -1;
1283 vcpu->arch.mcg_ctl = data;
1284 break;
1285 default:
1286 if (msr >= MSR_IA32_MC0_CTL &&
1287 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1288 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1289 /* only 0 or all 1s can be written to IA32_MCi_CTL
1290 * some Linux kernels though clear bit 10 in bank 4 to
1291 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1292 * this to avoid an uncatched #GP in the guest
1293 */
890ca9ae 1294 if ((offset & 0x3) == 0 &&
114be429 1295 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1296 return -1;
1297 vcpu->arch.mce_banks[offset] = data;
1298 break;
1299 }
1300 return 1;
1301 }
1302 return 0;
1303}
1304
ffde22ac
ES		 1305static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1306{
1307 struct kvm *kvm = vcpu->kvm;
1308 int lm = is_long_mode(vcpu);
1309 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1310 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1311 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1312 : kvm->arch.xen_hvm_config.blob_size_32;
1313 u32 page_num = data & ~PAGE_MASK;
1314 u64 page_addr = data & PAGE_MASK;
1315 u8 *page;
1316 int r;
1317
1318 r = -E2BIG;
1319 if (page_num >= blob_size)
1320 goto out;
1321 r = -ENOMEM;
1322 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1323 if (!page)
1324 goto out;
1325 r = -EFAULT;
1326 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1327 goto out_free;
1328 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1329 goto out_free;
1330 r = 0;
1331out_free:
1332 kfree(page);
1333out:
1334 return r;
1335}
1336
55cd8e5a
GN		 1337static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1338{
1339 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1340}
1341
1342static bool kvm_hv_msr_partition_wide(u32 msr)
1343{
1344 bool r = false;
1345 switch (msr) {
1346 case HV_X64_MSR_GUEST_OS_ID:
1347 case HV_X64_MSR_HYPERCALL:
1348 r = true;
1349 break;
1350 }
1351
1352 return r;
1353}
1354
1355static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1356{
1357 struct kvm *kvm = vcpu->kvm;
1358
1359 switch (msr) {
1360 case HV_X64_MSR_GUEST_OS_ID:
1361 kvm->arch.hv_guest_os_id = data;
1362 /* setting guest os id to zero disables hypercall page */
1363 if (!kvm->arch.hv_guest_os_id)
1364 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1365 break;
1366 case HV_X64_MSR_HYPERCALL: {
1367 u64 gfn;
1368 unsigned long addr;
1369 u8 instructions[4];
1370
1371 /* if guest os id is not set hypercall should remain disabled */
1372 if (!kvm->arch.hv_guest_os_id)
1373 break;
1374 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1375 kvm->arch.hv_hypercall = data;
1376 break;
1377 }
1378 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1379 addr = gfn_to_hva(kvm, gfn);
1380 if (kvm_is_error_hva(addr))
1381 return 1;
1382 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1383 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1384 if (copy_to_user((void __user *)addr, instructions, 4))
1385 return 1;
1386 kvm->arch.hv_hypercall = data;
1387 break;
1388 }
1389 default:
1390 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1391 "data 0x%llx\n", msr, data);
1392 return 1;
1393 }
1394 return 0;
1395}
1396
1397static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1398{
10388a07
GN		 1399 switch (msr) {
1400 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1401 unsigned long addr;
55cd8e5a 1402
10388a07
GN		 1403 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1404 vcpu->arch.hv_vapic = data;
1405 break;
1406 }
1407 addr = gfn_to_hva(vcpu->kvm, data >>
1408 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1409 if (kvm_is_error_hva(addr))
1410 return 1;
1411 if (clear_user((void __user *)addr, PAGE_SIZE))
1412 return 1;
1413 vcpu->arch.hv_vapic = data;
1414 break;
1415 }
1416 case HV_X64_MSR_EOI:
1417 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1418 case HV_X64_MSR_ICR:
1419 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1420 case HV_X64_MSR_TPR:
1421 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1422 default:
1423 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1424 "data 0x%llx\n", msr, data);
1425 return 1;
1426 }
1427
1428 return 0;
55cd8e5a
GN		 1429}
1430
344d9588
GN		 1431static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1432{
1433 gpa_t gpa = data & ~0x3f;
1434
6adba527
GN		 1435 /* Bits 2:5 are resrved, Should be zero */
1436 if (data & 0x3c)
344d9588
GN		 1437 return 1;
1438
1439 vcpu->arch.apf.msr_val = data;
1440
1441 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1442 kvm_clear_async_pf_completion_queue(vcpu);
1443 kvm_async_pf_hash_reset(vcpu);
1444 return 0;
1445 }
1446
1447 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1448 return 1;
1449
6adba527 1450 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1451 kvm_async_pf_wakeup_all(vcpu);
1452 return 0;
1453}
1454
15c4a640
CO		 1455int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1456{
1457 switch (msr) {
15c4a640 1458 case MSR_EFER:
b69e8cae 1459 return set_efer(vcpu, data);
8f1589d9
AP		 1460 case MSR_K7_HWCR:
1461 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1462 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1463 if (data != 0) {
1464 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1465 data);
1466 return 1;
1467 }
15c4a640 1468 break;
f7c6d140
AP		 1469 case MSR_FAM10H_MMIO_CONF_BASE:
1470 if (data != 0) {
1471 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1472 "0x%llx\n", data);
1473 return 1;
1474 }
15c4a640 1475 break;
c323c0e5 1476 case MSR_AMD64_NB_CFG:
c7ac679c 1477 break;
b5e2fec0
AG		 1478 case MSR_IA32_DEBUGCTLMSR:
1479 if (!data) {
1480 /* We support the non-activated case already */
1481 break;
1482 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1483 /* Values other than LBR and BTF are vendor-specific,
1484 thus reserved and should throw a #GP */
1485 return 1;
1486 }
1487 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1488 __func__, data);
1489 break;
15c4a640
CO		 1490 case MSR_IA32_UCODE_REV:
1491 case MSR_IA32_UCODE_WRITE:
61a6bd67 1492 case MSR_VM_HSAVE_PA:
6098ca93 1493 case MSR_AMD64_PATCH_LOADER:
15c4a640 1494 break;
9ba075a6
AK		 1495 case 0x200 ... 0x2ff:
1496 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1497 case MSR_IA32_APICBASE:
1498 kvm_set_apic_base(vcpu, data);
1499 break;
0105d1a5
GN		 1500 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1501 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1502 case MSR_IA32_MISC_ENABLE:
ad312c7c 1503 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1504 break;
11c6bffa 1505 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1506 case MSR_KVM_WALL_CLOCK:
1507 vcpu->kvm->arch.wall_clock = data;
1508 kvm_write_wall_clock(vcpu->kvm, data);
1509 break;
11c6bffa 1510 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1511 case MSR_KVM_SYSTEM_TIME: {
1512 if (vcpu->arch.time_page) {
1513 kvm_release_page_dirty(vcpu->arch.time_page);
1514 vcpu->arch.time_page = NULL;
1515 }
1516
1517 vcpu->arch.time = data;
c285545f 1518 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1519
1520 /* we verify if the enable bit is set... */
1521 if (!(data & 1))
1522 break;
1523
1524 /* ...but clean it before doing the actual write */
1525 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1526
18068523
GOC		 1527 vcpu->arch.time_page =
1528 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1529
1530 if (is_error_page(vcpu->arch.time_page)) {
1531 kvm_release_page_clean(vcpu->arch.time_page);
1532 vcpu->arch.time_page = NULL;
1533 }
18068523
GOC		 1534 break;
1535 }
344d9588
GN		 1536 case MSR_KVM_ASYNC_PF_EN:
1537 if (kvm_pv_enable_async_pf(vcpu, data))
1538 return 1;
1539 break;
890ca9ae
HY		 1540 case MSR_IA32_MCG_CTL:
1541 case MSR_IA32_MCG_STATUS:
1542 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1543 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1544
1545 /* Performance counters are not protected by a CPUID bit,
1546 * so we should check all of them in the generic path for the sake of
1547 * cross vendor migration.
1548 * Writing a zero into the event select MSRs disables them,
1549 * which we perfectly emulate ;-). Any other value should be at least
1550 * reported, some guests depend on them.
1551 */
1552 case MSR_P6_EVNTSEL0:
1553 case MSR_P6_EVNTSEL1:
1554 case MSR_K7_EVNTSEL0:
1555 case MSR_K7_EVNTSEL1:
1556 case MSR_K7_EVNTSEL2:
1557 case MSR_K7_EVNTSEL3:
1558 if (data != 0)
1559 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1560 "0x%x data 0x%llx\n", msr, data);
1561 break;
1562 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1563 * so we ignore writes to make it happy.
1564 */
1565 case MSR_P6_PERFCTR0:
1566 case MSR_P6_PERFCTR1:
1567 case MSR_K7_PERFCTR0:
1568 case MSR_K7_PERFCTR1:
1569 case MSR_K7_PERFCTR2:
1570 case MSR_K7_PERFCTR3:
1571 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1572 "0x%x data 0x%llx\n", msr, data);
1573 break;
84e0cefa
JS		 1574 case MSR_K7_CLK_CTL:
1575 /*
1576 * Ignore all writes to this no longer documented MSR.
1577 * Writes are only relevant for old K7 processors,
1578 * all pre-dating SVM, but a recommended workaround from
1579 * AMD for these chips. It is possible to speicify the
1580 * affected processor models on the command line, hence
1581 * the need to ignore the workaround.
1582 */
1583 break;
55cd8e5a
GN		 1584 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1585 if (kvm_hv_msr_partition_wide(msr)) {
1586 int r;
1587 mutex_lock(&vcpu->kvm->lock);
1588 r = set_msr_hyperv_pw(vcpu, msr, data);
1589 mutex_unlock(&vcpu->kvm->lock);
1590 return r;
1591 } else
1592 return set_msr_hyperv(vcpu, msr, data);
1593 break;
15c4a640 1594 default:
ffde22ac
ES		 1595 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1596 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1597 if (!ignore_msrs) {
1598 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1599 msr, data);
1600 return 1;
1601 } else {
1602 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1603 msr, data);
1604 break;
1605 }
15c4a640
CO		 1606 }
1607 return 0;
1608}
1609EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1610
1611
1612/*
1613 * Reads an msr value (of 'msr_index') into 'pdata'.
1614 * Returns 0 on success, non-0 otherwise.
1615 * Assumes vcpu_load() was already called.
1616 */
1617int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1618{
1619 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1620}
1621
9ba075a6
AK		 1622static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1623{
0bed3b56
SY		 1624 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1625
9ba075a6
AK		 1626 if (!msr_mtrr_valid(msr))
1627 return 1;
1628
0bed3b56
SY		 1629 if (msr == MSR_MTRRdefType)
1630 *pdata = vcpu->arch.mtrr_state.def_type +
1631 (vcpu->arch.mtrr_state.enabled << 10);
1632 else if (msr == MSR_MTRRfix64K_00000)
1633 *pdata = p[0];
1634 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1635 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1636 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1637 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1638 else if (msr == MSR_IA32_CR_PAT)
1639 *pdata = vcpu->arch.pat;
1640 else { /* Variable MTRRs */
1641 int idx, is_mtrr_mask;
1642 u64 *pt;
1643
1644 idx = (msr - 0x200) / 2;
1645 is_mtrr_mask = msr - 0x200 - 2 * idx;
1646 if (!is_mtrr_mask)
1647 pt =
1648 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1649 else
1650 pt =
1651 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1652 *pdata = *pt;
1653 }
1654
9ba075a6
AK		 1655 return 0;
1656}
1657
890ca9ae 1658static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1659{
1660 u64 data;
890ca9ae
HY		 1661 u64 mcg_cap = vcpu->arch.mcg_cap;
1662 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1663
1664 switch (msr) {
15c4a640
CO		 1665 case MSR_IA32_P5_MC_ADDR:
1666 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1667 data = 0;
1668 break;
15c4a640 1669 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1670 data = vcpu->arch.mcg_cap;
1671 break;
c7ac679c 1672 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1673 if (!(mcg_cap & MCG_CTL_P))
1674 return 1;
1675 data = vcpu->arch.mcg_ctl;
1676 break;
1677 case MSR_IA32_MCG_STATUS:
1678 data = vcpu->arch.mcg_status;
1679 break;
1680 default:
1681 if (msr >= MSR_IA32_MC0_CTL &&
1682 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1683 u32 offset = msr - MSR_IA32_MC0_CTL;
1684 data = vcpu->arch.mce_banks[offset];
1685 break;
1686 }
1687 return 1;
1688 }
1689 *pdata = data;
1690 return 0;
1691}
1692
55cd8e5a
GN		 1693static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1694{
1695 u64 data = 0;
1696 struct kvm *kvm = vcpu->kvm;
1697
1698 switch (msr) {
1699 case HV_X64_MSR_GUEST_OS_ID:
1700 data = kvm->arch.hv_guest_os_id;
1701 break;
1702 case HV_X64_MSR_HYPERCALL:
1703 data = kvm->arch.hv_hypercall;
1704 break;
1705 default:
1706 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1707 return 1;
1708 }
1709
1710 *pdata = data;
1711 return 0;
1712}
1713
1714static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1715{
1716 u64 data = 0;
1717
1718 switch (msr) {
1719 case HV_X64_MSR_VP_INDEX: {
1720 int r;
1721 struct kvm_vcpu *v;
1722 kvm_for_each_vcpu(r, v, vcpu->kvm)
1723 if (v == vcpu)
1724 data = r;
1725 break;
1726 }
10388a07
GN		 1727 case HV_X64_MSR_EOI:
1728 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1729 case HV_X64_MSR_ICR:
1730 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1731 case HV_X64_MSR_TPR:
1732 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1733 default:
1734 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1735 return 1;
1736 }
1737 *pdata = data;
1738 return 0;
1739}
1740
890ca9ae
HY		 1741int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1742{
1743 u64 data;
1744
1745 switch (msr) {
890ca9ae 1746 case MSR_IA32_PLATFORM_ID:
15c4a640 1747 case MSR_IA32_UCODE_REV:
15c4a640 1748 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1749 case MSR_IA32_DEBUGCTLMSR:
1750 case MSR_IA32_LASTBRANCHFROMIP:
1751 case MSR_IA32_LASTBRANCHTOIP:
1752 case MSR_IA32_LASTINTFROMIP:
1753 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1754 case MSR_K8_SYSCFG:
1755 case MSR_K7_HWCR:
61a6bd67 1756 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1757 case MSR_P6_PERFCTR0:
1758 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1759 case MSR_P6_EVNTSEL0:
1760 case MSR_P6_EVNTSEL1:
9e699624 1761 case MSR_K7_EVNTSEL0:
1f3ee616 1762 case MSR_K7_PERFCTR0:
1fdbd48c 1763 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1764 case MSR_AMD64_NB_CFG:
f7c6d140 1765 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1766 data = 0;
1767 break;
9ba075a6
AK		 1768 case MSR_MTRRcap:
1769 data = 0x500 | KVM_NR_VAR_MTRR;
1770 break;
1771 case 0x200 ... 0x2ff:
1772 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1773 case 0xcd: /* fsb frequency */
1774 data = 3;
1775 break;
7b914098
JS		 1776 /*
1777 * MSR_EBC_FREQUENCY_ID
1778 * Conservative value valid for even the basic CPU models.
1779 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1780 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1781 * and 266MHz for model 3, or 4. Set Core Clock
1782 * Frequency to System Bus Frequency Ratio to 1 (bits
1783 * 31:24) even though these are only valid for CPU
1784 * models > 2, however guests may end up dividing or
1785 * multiplying by zero otherwise.
1786 */
1787 case MSR_EBC_FREQUENCY_ID:
1788 data = 1 << 24;
1789 break;
15c4a640
CO		 1790 case MSR_IA32_APICBASE:
1791 data = kvm_get_apic_base(vcpu);
1792 break;
0105d1a5
GN		 1793 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1794 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1795 break;
15c4a640 1796 case MSR_IA32_MISC_ENABLE:
ad312c7c 1797 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1798 break;
847f0ad8
AG		 1799 case MSR_IA32_PERF_STATUS:
1800 /* TSC increment by tick */
1801 data = 1000ULL;
1802 /* CPU multiplier */
1803 data |= (((uint64_t)4ULL) << 40);
1804 break;
15c4a640 1805 case MSR_EFER:
f6801dff 1806 data = vcpu->arch.efer;
15c4a640 1807 break;
18068523 1808 case MSR_KVM_WALL_CLOCK:
11c6bffa 1809 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1810 data = vcpu->kvm->arch.wall_clock;
1811 break;
1812 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1813 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1814 data = vcpu->arch.time;
1815 break;
344d9588
GN		 1816 case MSR_KVM_ASYNC_PF_EN:
1817 data = vcpu->arch.apf.msr_val;
1818 break;
890ca9ae
HY		 1819 case MSR_IA32_P5_MC_ADDR:
1820 case MSR_IA32_P5_MC_TYPE:
1821 case MSR_IA32_MCG_CAP:
1822 case MSR_IA32_MCG_CTL:
1823 case MSR_IA32_MCG_STATUS:
1824 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1825 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1826 case MSR_K7_CLK_CTL:
1827 /*
1828 * Provide expected ramp-up count for K7. All other
1829 * are set to zero, indicating minimum divisors for
1830 * every field.
1831 *
1832 * This prevents guest kernels on AMD host with CPU
1833 * type 6, model 8 and higher from exploding due to
1834 * the rdmsr failing.
1835 */
1836 data = 0x20000000;
1837 break;
55cd8e5a
GN		 1838 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1839 if (kvm_hv_msr_partition_wide(msr)) {
1840 int r;
1841 mutex_lock(&vcpu->kvm->lock);
1842 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1843 mutex_unlock(&vcpu->kvm->lock);
1844 return r;
1845 } else
1846 return get_msr_hyperv(vcpu, msr, pdata);
1847 break;
15c4a640 1848 default:
ed85c068
AP		 1849 if (!ignore_msrs) {
1850 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1851 return 1;
1852 } else {
1853 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1854 data = 0;
1855 }
1856 break;
15c4a640
CO		 1857 }
1858 *pdata = data;
1859 return 0;
1860}
1861EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1862
313a3dc7
CO		 1863/*
1864 * Read or write a bunch of msrs. All parameters are kernel addresses.
1865 *
1866 * @return number of msrs set successfully.
1867 */
1868static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1869 struct kvm_msr_entry *entries,
1870 int (*do_msr)(struct kvm_vcpu *vcpu,
1871 unsigned index, u64 *data))
1872{
f656ce01 1873 int i, idx;
313a3dc7 1874
f656ce01 1875 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1876 for (i = 0; i < msrs->nmsrs; ++i)
1877 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1878 break;
f656ce01 1879 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1880
313a3dc7
CO		 1881 return i;
1882}
1883
1884/*
1885 * Read or write a bunch of msrs. Parameters are user addresses.
1886 *
1887 * @return number of msrs set successfully.
1888 */
1889static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1890 int (*do_msr)(struct kvm_vcpu *vcpu,
1891 unsigned index, u64 *data),
1892 int writeback)
1893{
1894 struct kvm_msrs msrs;
1895 struct kvm_msr_entry *entries;
1896 int r, n;
1897 unsigned size;
1898
1899 r = -EFAULT;
1900 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1901 goto out;
1902
1903 r = -E2BIG;
1904 if (msrs.nmsrs >= MAX_IO_MSRS)
1905 goto out;
1906
1907 r = -ENOMEM;
1908 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1909 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1910 if (!entries)
1911 goto out;
1912
1913 r = -EFAULT;
1914 if (copy_from_user(entries, user_msrs->entries, size))
1915 goto out_free;
1916
1917 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1918 if (r < 0)
1919 goto out_free;
1920
1921 r = -EFAULT;
1922 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1923 goto out_free;
1924
1925 r = n;
1926
1927out_free:
7a73c028 1928 kfree(entries);
313a3dc7
CO		 1929out:
1930 return r;
1931}
1932
018d00d2
ZX		 1933int kvm_dev_ioctl_check_extension(long ext)
1934{
1935 int r;
1936
1937 switch (ext) {
1938 case KVM_CAP_IRQCHIP:
1939 case KVM_CAP_HLT:
1940 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1941 case KVM_CAP_SET_TSS_ADDR:
07716717 1942 case KVM_CAP_EXT_CPUID:
c8076604 1943 case KVM_CAP_CLOCKSOURCE:
7837699f 1944 case KVM_CAP_PIT:
a28e4f5a 1945 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1946 case KVM_CAP_MP_STATE:
ed848624 1947 case KVM_CAP_SYNC_MMU:
52d939a0 1948 case KVM_CAP_REINJECT_CONTROL:
4925663a 1949 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1950 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1951 case KVM_CAP_IRQFD:
d34e6b17 1952 case KVM_CAP_IOEVENTFD:
c5ff41ce 1953 case KVM_CAP_PIT2:
e9f42757 1954 case KVM_CAP_PIT_STATE2:
b927a3ce 1955 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1956 case KVM_CAP_XEN_HVM:
afbcf7ab 1957 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1958 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1959 case KVM_CAP_HYPERV:
10388a07 1960 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1961 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1962 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1963 case KVM_CAP_DEBUGREGS:
d2be1651 1964 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1965 case KVM_CAP_XSAVE:
344d9588 1966 case KVM_CAP_ASYNC_PF:
018d00d2
ZX		 1967 r = 1;
1968 break;
542472b5
LV		 1969 case KVM_CAP_COALESCED_MMIO:
1970 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1971 break;
774ead3a
AK		 1972 case KVM_CAP_VAPIC:
1973 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1974 break;
f725230a
AK		 1975 case KVM_CAP_NR_VCPUS:
1976 r = KVM_MAX_VCPUS;
1977 break;
a988b910
AK		 1978 case KVM_CAP_NR_MEMSLOTS:
1979 r = KVM_MEMORY_SLOTS;
1980 break;
a68a6a72
MT		 1981 case KVM_CAP_PV_MMU: /* obsolete */
1982 r = 0;
2f333bcb 1983 break;
62c476c7 1984 case KVM_CAP_IOMMU:
19de40a8 1985 r = iommu_found();
62c476c7 1986 break;
890ca9ae
HY		 1987 case KVM_CAP_MCE:
1988 r = KVM_MAX_MCE_BANKS;
1989 break;
2d5b5a66
SY		 1990 case KVM_CAP_XCRS:
1991 r = cpu_has_xsave;
1992 break;
018d00d2
ZX		 1993 default:
1994 r = 0;
1995 break;
1996 }
1997 return r;
1998
1999}
2000
043405e1
CO		 2001long kvm_arch_dev_ioctl(struct file *filp,
2002 unsigned int ioctl, unsigned long arg)
2003{
2004 void __user *argp = (void __user *)arg;
2005 long r;
2006
2007 switch (ioctl) {
2008 case KVM_GET_MSR_INDEX_LIST: {
2009 struct kvm_msr_list __user *user_msr_list = argp;
2010 struct kvm_msr_list msr_list;
2011 unsigned n;
2012
2013 r = -EFAULT;
2014 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2015 goto out;
2016 n = msr_list.nmsrs;
2017 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2018 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2019 goto out;
2020 r = -E2BIG;
e125e7b6 2021 if (n < msr_list.nmsrs)
043405e1
CO		 2022 goto out;
2023 r = -EFAULT;
2024 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2025 num_msrs_to_save * sizeof(u32)))
2026 goto out;
e125e7b6 2027 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2028 &emulated_msrs,
2029 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2030 goto out;
2031 r = 0;
2032 break;
2033 }
674eea0f
AK		 2034 case KVM_GET_SUPPORTED_CPUID: {
2035 struct kvm_cpuid2 __user *cpuid_arg = argp;
2036 struct kvm_cpuid2 cpuid;
2037
2038 r = -EFAULT;
2039 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2040 goto out;
2041 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2042 cpuid_arg->entries);
674eea0f
AK		 2043 if (r)
2044 goto out;
2045
2046 r = -EFAULT;
2047 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2048 goto out;
2049 r = 0;
2050 break;
2051 }
890ca9ae
HY		 2052 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2053 u64 mce_cap;
2054
2055 mce_cap = KVM_MCE_CAP_SUPPORTED;
2056 r = -EFAULT;
2057 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2058 goto out;
2059 r = 0;
2060 break;
2061 }
043405e1
CO		 2062 default:
2063 r = -EINVAL;
2064 }
2065out:
2066 return r;
2067}
2068
f5f48ee1
SY		 2069static void wbinvd_ipi(void *garbage)
2070{
2071 wbinvd();
2072}
2073
2074static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2075{
2076 return vcpu->kvm->arch.iommu_domain &&
2077 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2078}
2079
313a3dc7
CO		 2080void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2081{
f5f48ee1
SY		 2082 /* Address WBINVD may be executed by guest */
2083 if (need_emulate_wbinvd(vcpu)) {
2084 if (kvm_x86_ops->has_wbinvd_exit())
2085 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2086 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2087 smp_call_function_single(vcpu->cpu,
2088 wbinvd_ipi, NULL, 1);
2089 }
2090
313a3dc7 2091 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2092 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2093 /* Make sure TSC doesn't go backwards */
2094 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2095 native_read_tsc() - vcpu->arch.last_host_tsc;
2096 if (tsc_delta < 0)
2097 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2098 if (check_tsc_unstable()) {
e48672fa 2099 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f
ZA		 2100 vcpu->arch.tsc_catchup = 1;
2101 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2102 }
2103 if (vcpu->cpu != cpu)
2104 kvm_migrate_timers(vcpu);
e48672fa 2105 vcpu->cpu = cpu;
6b7d7e76 2106 }
313a3dc7
CO		 2107}
2108
2109void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2110{
02daab21 2111 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2112 kvm_put_guest_fpu(vcpu);
e48672fa 2113 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2114}
2115
07716717 2116static int is_efer_nx(void)
313a3dc7 2117{
e286e86e 2118 unsigned long long efer = 0;
313a3dc7 2119
e286e86e 2120 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2121 return efer & EFER_NX;
2122}
2123
2124static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2125{
2126 int i;
2127 struct kvm_cpuid_entry2 *e, *entry;
2128
313a3dc7 2129 entry = NULL;
ad312c7c
ZX		 2130 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2131 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2132 if (e->function == 0x80000001) {
2133 entry = e;
2134 break;
2135 }
2136 }
07716717 2137 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2138 entry->edx &= ~(1 << 20);
2139 printk(KERN_INFO "kvm: guest NX capability removed\n");
2140 }
2141}
2142
07716717 2143/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2144static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2145 struct kvm_cpuid *cpuid,
2146 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2147{
2148 int r, i;
2149 struct kvm_cpuid_entry *cpuid_entries;
2150
2151 r = -E2BIG;
2152 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2153 goto out;
2154 r = -ENOMEM;
2155 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2156 if (!cpuid_entries)
2157 goto out;
2158 r = -EFAULT;
2159 if (copy_from_user(cpuid_entries, entries,
2160 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2161 goto out_free;
2162 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2163 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2164 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2165 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2166 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2167 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2168 vcpu->arch.cpuid_entries[i].index = 0;
2169 vcpu->arch.cpuid_entries[i].flags = 0;
2170 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2171 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2172 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2173 }
2174 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2175 cpuid_fix_nx_cap(vcpu);
2176 r = 0;
fc61b800 2177 kvm_apic_set_version(vcpu);
0e851880 2178 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2179 update_cpuid(vcpu);
07716717
DK		 2180
2181out_free:
2182 vfree(cpuid_entries);
2183out:
2184 return r;
2185}
2186
2187static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2188 struct kvm_cpuid2 *cpuid,
2189 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2190{
2191 int r;
2192
2193 r = -E2BIG;
2194 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2195 goto out;
2196 r = -EFAULT;
ad312c7c 2197 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2198 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2199 goto out;
ad312c7c 2200 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2201 kvm_apic_set_version(vcpu);
0e851880 2202 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2203 update_cpuid(vcpu);
313a3dc7
CO		 2204 return 0;
2205
2206out:
2207 return r;
2208}
2209
07716717 2210static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2211 struct kvm_cpuid2 *cpuid,
2212 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2213{
2214 int r;
2215
2216 r = -E2BIG;
ad312c7c 2217 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2218 goto out;
2219 r = -EFAULT;
ad312c7c 2220 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2221 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2222 goto out;
2223 return 0;
2224
2225out:
ad312c7c 2226 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2227 return r;
2228}
2229
945ee35e
AK		 2230static void cpuid_mask(u32 *word, int wordnum)
2231{
2232 *word &= boot_cpu_data.x86_capability[wordnum];
2233}
2234
07716717 2235static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2236 u32 index)
07716717
DK		 2237{
2238 entry->function = function;
2239 entry->index = index;
2240 cpuid_count(entry->function, entry->index,
19355475 2241 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2242 entry->flags = 0;
2243}
2244
7faa4ee1
AK		 2245#define F(x) bit(X86_FEATURE_##x)
2246
07716717
DK		 2247static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2248 u32 index, int *nent, int maxnent)
2249{
7faa4ee1 2250 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2251#ifdef CONFIG_X86_64
17cc3935
SY		 2252 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2253 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2254 unsigned f_lm = F(LM);
2255#else
17cc3935 2256 unsigned f_gbpages = 0;
7faa4ee1 2257 unsigned f_lm = 0;
07716717 2258#endif
4e47c7a6 2259 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2260
2261 /* cpuid 1.edx */
2262 const u32 kvm_supported_word0_x86_features =
2263 F(FPU) | F(VME) | F(DE) | F(PSE) |
2264 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2265 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2266 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2267 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2268 0 /* Reserved, DS, ACPI */ | F(MMX) |
2269 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2270 0 /* HTT, TM, Reserved, PBE */;
2271 /* cpuid 0x80000001.edx */
2272 const u32 kvm_supported_word1_x86_features =
2273 F(FPU) | F(VME) | F(DE) | F(PSE) |
2274 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2275 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2276 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2277 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2278 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2279 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2280 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2281 /* cpuid 1.ecx */
2282 const u32 kvm_supported_word4_x86_features =
6c3f6041 2283 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2284 0 /* DS-CPL, VMX, SMX, EST */ |
2285 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2286 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2287 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2288 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2289 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2290 F(F16C);
7faa4ee1 2291 /* cpuid 0x80000001.ecx */
07716717 2292 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2293 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2294 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2295 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2296 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2297
19355475 2298 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2299 get_cpu();
2300 do_cpuid_1_ent(entry, function, index);
2301 ++*nent;
2302
2303 switch (function) {
2304 case 0:
2acf923e 2305 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2306 break;
2307 case 1:
2308 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2309 cpuid_mask(&entry->edx, 0);
7faa4ee1 2310 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2311 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2312 /* we support x2apic emulation even if host does not support
2313 * it since we emulate x2apic in software */
2314 entry->ecx |= F(X2APIC);
07716717
DK		 2315 break;
2316 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2317 * may return different values. This forces us to get_cpu() before
2318 * issuing the first command, and also to emulate this annoying behavior
2319 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2320 case 2: {
2321 int t, times = entry->eax & 0xff;
2322
2323 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2324 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2325 for (t = 1; t < times && *nent < maxnent; ++t) {
2326 do_cpuid_1_ent(&entry[t], function, 0);
2327 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2328 ++*nent;
2329 }
2330 break;
2331 }
2332 /* function 4 and 0xb have additional index. */
2333 case 4: {
14af3f3c 2334 int i, cache_type;
07716717
DK		 2335
2336 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2337 /* read more entries until cache_type is zero */
14af3f3c
HH		 2338 for (i = 1; *nent < maxnent; ++i) {
2339 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2340 if (!cache_type)
2341 break;
14af3f3c
HH		 2342 do_cpuid_1_ent(&entry[i], function, i);
2343 entry[i].flags |=
07716717
DK		 2344 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2345 ++*nent;
2346 }
2347 break;
2348 }
2349 case 0xb: {
14af3f3c 2350 int i, level_type;
07716717
DK		 2351
2352 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2353 /* read more entries until level_type is zero */
14af3f3c 2354 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2355 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2356 if (!level_type)
2357 break;
14af3f3c
HH		 2358 do_cpuid_1_ent(&entry[i], function, i);
2359 entry[i].flags |=
07716717
DK		 2360 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2361 ++*nent;
2362 }
2363 break;
2364 }
2acf923e
DC		 2365 case 0xd: {
2366 int i;
2367
2368 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2369 for (i = 1; *nent < maxnent; ++i) {
2370 if (entry[i - 1].eax == 0 && i != 2)
2371 break;
2372 do_cpuid_1_ent(&entry[i], function, i);
2373 entry[i].flags |=
2374 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2375 ++*nent;
2376 }
2377 break;
2378 }
84478c82
GC		 2379 case KVM_CPUID_SIGNATURE: {
2380 char signature[12] = "KVMKVMKVM\0\0";
2381 u32 *sigptr = (u32 *)signature;
2382 entry->eax = 0;
2383 entry->ebx = sigptr[0];
2384 entry->ecx = sigptr[1];
2385 entry->edx = sigptr[2];
2386 break;
2387 }
2388 case KVM_CPUID_FEATURES:
2389 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2390 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2391 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2392 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2393 entry->ebx = 0;
2394 entry->ecx = 0;
2395 entry->edx = 0;
2396 break;
07716717
DK		 2397 case 0x80000000:
2398 entry->eax = min(entry->eax, 0x8000001a);
2399 break;
2400 case 0x80000001:
2401 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2402 cpuid_mask(&entry->edx, 1);
07716717 2403 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2404 cpuid_mask(&entry->ecx, 6);
07716717
DK		 2405 break;
2406 }
d4330ef2
JR		 2407
2408 kvm_x86_ops->set_supported_cpuid(function, entry);
2409
07716717
DK		 2410 put_cpu();
2411}
2412
7faa4ee1
AK		 2413#undef F
2414
674eea0f 2415static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2416 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2417{
2418 struct kvm_cpuid_entry2 *cpuid_entries;
2419 int limit, nent = 0, r = -E2BIG;
2420 u32 func;
2421
2422 if (cpuid->nent < 1)
2423 goto out;
6a544355
AK		 2424 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2425 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2426 r = -ENOMEM;
2427 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2428 if (!cpuid_entries)
2429 goto out;
2430
2431 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2432 limit = cpuid_entries[0].eax;
2433 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2434 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2435 &nent, cpuid->nent);
07716717
DK		 2436 r = -E2BIG;
2437 if (nent >= cpuid->nent)
2438 goto out_free;
2439
2440 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2441 limit = cpuid_entries[nent - 1].eax;
2442 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2443 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2444 &nent, cpuid->nent);
84478c82
GC		 2445
2446
2447
2448 r = -E2BIG;
2449 if (nent >= cpuid->nent)
2450 goto out_free;
2451
2452 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2453 cpuid->nent);
2454
2455 r = -E2BIG;
2456 if (nent >= cpuid->nent)
2457 goto out_free;
2458
2459 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2460 cpuid->nent);
2461
cb007648
MM		 2462 r = -E2BIG;
2463 if (nent >= cpuid->nent)
2464 goto out_free;
2465
07716717
DK		 2466 r = -EFAULT;
2467 if (copy_to_user(entries, cpuid_entries,
19355475 2468 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2469 goto out_free;
2470 cpuid->nent = nent;
2471 r = 0;
2472
2473out_free:
2474 vfree(cpuid_entries);
2475out:
2476 return r;
2477}
2478
313a3dc7
CO		 2479static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2480 struct kvm_lapic_state *s)
2481{
ad312c7c 2482 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2483
2484 return 0;
2485}
2486
2487static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2488 struct kvm_lapic_state *s)
2489{
ad312c7c 2490 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2491 kvm_apic_post_state_restore(vcpu);
cb142eb7 2492 update_cr8_intercept(vcpu);
313a3dc7
CO		 2493
2494 return 0;
2495}
2496
f77bc6a4
ZX		 2497static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2498 struct kvm_interrupt *irq)
2499{
2500 if (irq->irq < 0 || irq->irq >= 256)
2501 return -EINVAL;
2502 if (irqchip_in_kernel(vcpu->kvm))
2503 return -ENXIO;
f77bc6a4 2504
66fd3f7f 2505 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2506 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2507
f77bc6a4
ZX		 2508 return 0;
2509}
2510
c4abb7c9
JK		 2511static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2512{
c4abb7c9 2513 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2514
2515 return 0;
2516}
2517
b209749f
AK		 2518static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2519 struct kvm_tpr_access_ctl *tac)
2520{
2521 if (tac->flags)
2522 return -EINVAL;
2523 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2524 return 0;
2525}
2526
890ca9ae
HY		 2527static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2528 u64 mcg_cap)
2529{
2530 int r;
2531 unsigned bank_num = mcg_cap & 0xff, bank;
2532
2533 r = -EINVAL;
a9e38c3e 2534 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2535 goto out;
2536 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2537 goto out;
2538 r = 0;
2539 vcpu->arch.mcg_cap = mcg_cap;
2540 /* Init IA32_MCG_CTL to all 1s */
2541 if (mcg_cap & MCG_CTL_P)
2542 vcpu->arch.mcg_ctl = ~(u64)0;
2543 /* Init IA32_MCi_CTL to all 1s */
2544 for (bank = 0; bank < bank_num; bank++)
2545 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2546out:
2547 return r;
2548}
2549
2550static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2551 struct kvm_x86_mce *mce)
2552{
2553 u64 mcg_cap = vcpu->arch.mcg_cap;
2554 unsigned bank_num = mcg_cap & 0xff;
2555 u64 *banks = vcpu->arch.mce_banks;
2556
2557 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2558 return -EINVAL;
2559 /*
2560 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2561 * reporting is disabled
2562 */
2563 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2564 vcpu->arch.mcg_ctl != ~(u64)0)
2565 return 0;
2566 banks += 4 * mce->bank;
2567 /*
2568 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2569 * reporting is disabled for the bank
2570 */
2571 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2572 return 0;
2573 if (mce->status & MCI_STATUS_UC) {
2574 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2575 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2576 printk(KERN_DEBUG "kvm: set_mce: "
2577 "injects mce exception while "
2578 "previous one is in progress!\n");
a8eeb04a 2579 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2580 return 0;
2581 }
2582 if (banks[1] & MCI_STATUS_VAL)
2583 mce->status |= MCI_STATUS_OVER;
2584 banks[2] = mce->addr;
2585 banks[3] = mce->misc;
2586 vcpu->arch.mcg_status = mce->mcg_status;
2587 banks[1] = mce->status;
2588 kvm_queue_exception(vcpu, MC_VECTOR);
2589 } else if (!(banks[1] & MCI_STATUS_VAL)
2590 || !(banks[1] & MCI_STATUS_UC)) {
2591 if (banks[1] & MCI_STATUS_VAL)
2592 mce->status |= MCI_STATUS_OVER;
2593 banks[2] = mce->addr;
2594 banks[3] = mce->misc;
2595 banks[1] = mce->status;
2596 } else
2597 banks[1] |= MCI_STATUS_OVER;
2598 return 0;
2599}
2600
3cfc3092
JK		 2601static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2602 struct kvm_vcpu_events *events)
2603{
03b82a30
JK		 2604 events->exception.injected =
2605 vcpu->arch.exception.pending &&
2606 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2607 events->exception.nr = vcpu->arch.exception.nr;
2608 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2609 events->exception.pad = 0;
3cfc3092
JK		 2610 events->exception.error_code = vcpu->arch.exception.error_code;
2611
03b82a30
JK		 2612 events->interrupt.injected =
2613 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2614 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2615 events->interrupt.soft = 0;
48005f64
JK		 2616 events->interrupt.shadow =
2617 kvm_x86_ops->get_interrupt_shadow(vcpu,
2618 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2619
2620 events->nmi.injected = vcpu->arch.nmi_injected;
2621 events->nmi.pending = vcpu->arch.nmi_pending;
2622 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2623 events->nmi.pad = 0;
3cfc3092
JK		 2624
2625 events->sipi_vector = vcpu->arch.sipi_vector;
2626
dab4b911 2627 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2628 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2629 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2630 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2631}
2632
2633static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2634 struct kvm_vcpu_events *events)
2635{
dab4b911 2636 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2637 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2638 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2639 return -EINVAL;
2640
3cfc3092
JK		 2641 vcpu->arch.exception.pending = events->exception.injected;
2642 vcpu->arch.exception.nr = events->exception.nr;
2643 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2644 vcpu->arch.exception.error_code = events->exception.error_code;
2645
2646 vcpu->arch.interrupt.pending = events->interrupt.injected;
2647 vcpu->arch.interrupt.nr = events->interrupt.nr;
2648 vcpu->arch.interrupt.soft = events->interrupt.soft;
2649 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2650 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2651 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2652 kvm_x86_ops->set_interrupt_shadow(vcpu,
2653 events->interrupt.shadow);
3cfc3092
JK		 2654
2655 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2656 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2657 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2658 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2659
dab4b911
JK		 2660 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2661 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2662
3842d135
AK		 2663 kvm_make_request(KVM_REQ_EVENT, vcpu);
2664
3cfc3092
JK		 2665 return 0;
2666}
2667
a1efbe77
JK		 2668static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2669 struct kvm_debugregs *dbgregs)
2670{
a1efbe77
JK		 2671 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2672 dbgregs->dr6 = vcpu->arch.dr6;
2673 dbgregs->dr7 = vcpu->arch.dr7;
2674 dbgregs->flags = 0;
97e69aa6 2675 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2676}
2677
2678static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2679 struct kvm_debugregs *dbgregs)
2680{
2681 if (dbgregs->flags)
2682 return -EINVAL;
2683
a1efbe77
JK		 2684 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2685 vcpu->arch.dr6 = dbgregs->dr6;
2686 vcpu->arch.dr7 = dbgregs->dr7;
2687
a1efbe77
JK		 2688 return 0;
2689}
2690
2d5b5a66
SY		 2691static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2692 struct kvm_xsave *guest_xsave)
2693{
2694 if (cpu_has_xsave)
2695 memcpy(guest_xsave->region,
2696 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2697 xstate_size);
2d5b5a66
SY		 2698 else {
2699 memcpy(guest_xsave->region,
2700 &vcpu->arch.guest_fpu.state->fxsave,
2701 sizeof(struct i387_fxsave_struct));
2702 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2703 XSTATE_FPSSE;
2704 }
2705}
2706
2707static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2708 struct kvm_xsave *guest_xsave)
2709{
2710 u64 xstate_bv =
2711 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2712
2713 if (cpu_has_xsave)
2714 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2715 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2716 else {
2717 if (xstate_bv & ~XSTATE_FPSSE)
2718 return -EINVAL;
2719 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2720 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2721 }
2722 return 0;
2723}
2724
2725static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2726 struct kvm_xcrs *guest_xcrs)
2727{
2728 if (!cpu_has_xsave) {
2729 guest_xcrs->nr_xcrs = 0;
2730 return;
2731 }
2732
2733 guest_xcrs->nr_xcrs = 1;
2734 guest_xcrs->flags = 0;
2735 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2736 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2737}
2738
2739static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2740 struct kvm_xcrs *guest_xcrs)
2741{
2742 int i, r = 0;
2743
2744 if (!cpu_has_xsave)
2745 return -EINVAL;
2746
2747 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2748 return -EINVAL;
2749
2750 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2751 /* Only support XCR0 currently */
2752 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2753 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2754 guest_xcrs->xcrs[0].value);
2755 break;
2756 }
2757 if (r)
2758 r = -EINVAL;
2759 return r;
2760}
2761
313a3dc7
CO		 2762long kvm_arch_vcpu_ioctl(struct file *filp,
2763 unsigned int ioctl, unsigned long arg)
2764{
2765 struct kvm_vcpu *vcpu = filp->private_data;
2766 void __user *argp = (void __user *)arg;
2767 int r;
d1ac91d8
AK		 2768 union {
2769 struct kvm_lapic_state *lapic;
2770 struct kvm_xsave *xsave;
2771 struct kvm_xcrs *xcrs;
2772 void *buffer;
2773 } u;
2774
2775 u.buffer = NULL;
313a3dc7
CO		 2776 switch (ioctl) {
2777 case KVM_GET_LAPIC: {
2204ae3c
MT		 2778 r = -EINVAL;
2779 if (!vcpu->arch.apic)
2780 goto out;
d1ac91d8 2781 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2782
b772ff36 2783 r = -ENOMEM;
d1ac91d8 2784 if (!u.lapic)
b772ff36 2785 goto out;
d1ac91d8 2786 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2787 if (r)
2788 goto out;
2789 r = -EFAULT;
d1ac91d8 2790 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2791 goto out;
2792 r = 0;
2793 break;
2794 }
2795 case KVM_SET_LAPIC: {
2204ae3c
MT		 2796 r = -EINVAL;
2797 if (!vcpu->arch.apic)
2798 goto out;
d1ac91d8 2799 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2800 r = -ENOMEM;
d1ac91d8 2801 if (!u.lapic)
b772ff36 2802 goto out;
313a3dc7 2803 r = -EFAULT;
d1ac91d8 2804 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2805 goto out;
d1ac91d8 2806 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2807 if (r)
2808 goto out;
2809 r = 0;
2810 break;
2811 }
f77bc6a4
ZX		 2812 case KVM_INTERRUPT: {
2813 struct kvm_interrupt irq;
2814
2815 r = -EFAULT;
2816 if (copy_from_user(&irq, argp, sizeof irq))
2817 goto out;
2818 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2819 if (r)
2820 goto out;
2821 r = 0;
2822 break;
2823 }
c4abb7c9
JK		 2824 case KVM_NMI: {
2825 r = kvm_vcpu_ioctl_nmi(vcpu);
2826 if (r)
2827 goto out;
2828 r = 0;
2829 break;
2830 }
313a3dc7
CO		 2831 case KVM_SET_CPUID: {
2832 struct kvm_cpuid __user *cpuid_arg = argp;
2833 struct kvm_cpuid cpuid;
2834
2835 r = -EFAULT;
2836 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2837 goto out;
2838 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2839 if (r)
2840 goto out;
2841 break;
2842 }
07716717
DK		 2843 case KVM_SET_CPUID2: {
2844 struct kvm_cpuid2 __user *cpuid_arg = argp;
2845 struct kvm_cpuid2 cpuid;
2846
2847 r = -EFAULT;
2848 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2849 goto out;
2850 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2851 cpuid_arg->entries);
07716717
DK		 2852 if (r)
2853 goto out;
2854 break;
2855 }
2856 case KVM_GET_CPUID2: {
2857 struct kvm_cpuid2 __user *cpuid_arg = argp;
2858 struct kvm_cpuid2 cpuid;
2859
2860 r = -EFAULT;
2861 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2862 goto out;
2863 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2864 cpuid_arg->entries);
07716717
DK		 2865 if (r)
2866 goto out;
2867 r = -EFAULT;
2868 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2869 goto out;
2870 r = 0;
2871 break;
2872 }
313a3dc7
CO		 2873 case KVM_GET_MSRS:
2874 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2875 break;
2876 case KVM_SET_MSRS:
2877 r = msr_io(vcpu, argp, do_set_msr, 0);
2878 break;
b209749f
AK		 2879 case KVM_TPR_ACCESS_REPORTING: {
2880 struct kvm_tpr_access_ctl tac;
2881
2882 r = -EFAULT;
2883 if (copy_from_user(&tac, argp, sizeof tac))
2884 goto out;
2885 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2886 if (r)
2887 goto out;
2888 r = -EFAULT;
2889 if (copy_to_user(argp, &tac, sizeof tac))
2890 goto out;
2891 r = 0;
2892 break;
2893 };
b93463aa
AK		 2894 case KVM_SET_VAPIC_ADDR: {
2895 struct kvm_vapic_addr va;
2896
2897 r = -EINVAL;
2898 if (!irqchip_in_kernel(vcpu->kvm))
2899 goto out;
2900 r = -EFAULT;
2901 if (copy_from_user(&va, argp, sizeof va))
2902 goto out;
2903 r = 0;
2904 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2905 break;
2906 }
890ca9ae
HY		 2907 case KVM_X86_SETUP_MCE: {
2908 u64 mcg_cap;
2909
2910 r = -EFAULT;
2911 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2912 goto out;
2913 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2914 break;
2915 }
2916 case KVM_X86_SET_MCE: {
2917 struct kvm_x86_mce mce;
2918
2919 r = -EFAULT;
2920 if (copy_from_user(&mce, argp, sizeof mce))
2921 goto out;
2922 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2923 break;
2924 }
3cfc3092
JK		 2925 case KVM_GET_VCPU_EVENTS: {
2926 struct kvm_vcpu_events events;
2927
2928 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2929
2930 r = -EFAULT;
2931 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2932 break;
2933 r = 0;
2934 break;
2935 }
2936 case KVM_SET_VCPU_EVENTS: {
2937 struct kvm_vcpu_events events;
2938
2939 r = -EFAULT;
2940 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2941 break;
2942
2943 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2944 break;
2945 }
a1efbe77
JK		 2946 case KVM_GET_DEBUGREGS: {
2947 struct kvm_debugregs dbgregs;
2948
2949 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2950
2951 r = -EFAULT;
2952 if (copy_to_user(argp, &dbgregs,
2953 sizeof(struct kvm_debugregs)))
2954 break;
2955 r = 0;
2956 break;
2957 }
2958 case KVM_SET_DEBUGREGS: {
2959 struct kvm_debugregs dbgregs;
2960
2961 r = -EFAULT;
2962 if (copy_from_user(&dbgregs, argp,
2963 sizeof(struct kvm_debugregs)))
2964 break;
2965
2966 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2967 break;
2968 }
2d5b5a66 2969 case KVM_GET_XSAVE: {
d1ac91d8 2970 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2971 r = -ENOMEM;
d1ac91d8 2972 if (!u.xsave)
2d5b5a66
SY		 2973 break;
2974
d1ac91d8 2975 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2976
2977 r = -EFAULT;
d1ac91d8 2978 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2979 break;
2980 r = 0;
2981 break;
2982 }
2983 case KVM_SET_XSAVE: {
d1ac91d8 2984 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2985 r = -ENOMEM;
d1ac91d8 2986 if (!u.xsave)
2d5b5a66
SY		 2987 break;
2988
2989 r = -EFAULT;
d1ac91d8 2990 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2991 break;
2992
d1ac91d8 2993 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2994 break;
2995 }
2996 case KVM_GET_XCRS: {
d1ac91d8 2997 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2998 r = -ENOMEM;
d1ac91d8 2999 if (!u.xcrs)
2d5b5a66
SY		 3000 break;
3001
d1ac91d8 3002 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3003
3004 r = -EFAULT;
d1ac91d8 3005 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3006 sizeof(struct kvm_xcrs)))
3007 break;
3008 r = 0;
3009 break;
3010 }
3011 case KVM_SET_XCRS: {
d1ac91d8 3012 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3013 r = -ENOMEM;
d1ac91d8 3014 if (!u.xcrs)
2d5b5a66
SY		 3015 break;
3016
3017 r = -EFAULT;
d1ac91d8 3018 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3019 sizeof(struct kvm_xcrs)))
3020 break;
3021
d1ac91d8 3022 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3023 break;
3024 }
313a3dc7
CO		 3025 default:
3026 r = -EINVAL;
3027 }
3028out:
d1ac91d8 3029 kfree(u.buffer);
313a3dc7
CO		 3030 return r;
3031}
3032
1fe779f8
CO		 3033static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3034{
3035 int ret;
3036
3037 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3038 return -1;
3039 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3040 return ret;
3041}
3042
b927a3ce
SY		 3043static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3044 u64 ident_addr)
3045{
3046 kvm->arch.ept_identity_map_addr = ident_addr;
3047 return 0;
3048}
3049
1fe779f8
CO		 3050static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3051 u32 kvm_nr_mmu_pages)
3052{
3053 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3054 return -EINVAL;
3055
79fac95e 3056 mutex_lock(&kvm->slots_lock);
7c8a83b7 3057 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3058
3059 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3060 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3061
7c8a83b7 3062 spin_unlock(&kvm->mmu_lock);
79fac95e 3063 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3064 return 0;
3065}
3066
3067static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3068{
39de71ec 3069 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3070}
3071
1fe779f8
CO		 3072static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3073{
3074 int r;
3075
3076 r = 0;
3077 switch (chip->chip_id) {
3078 case KVM_IRQCHIP_PIC_MASTER:
3079 memcpy(&chip->chip.pic,
3080 &pic_irqchip(kvm)->pics[0],
3081 sizeof(struct kvm_pic_state));
3082 break;
3083 case KVM_IRQCHIP_PIC_SLAVE:
3084 memcpy(&chip->chip.pic,
3085 &pic_irqchip(kvm)->pics[1],
3086 sizeof(struct kvm_pic_state));
3087 break;
3088 case KVM_IRQCHIP_IOAPIC:
eba0226b 3089 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3090 break;
3091 default:
3092 r = -EINVAL;
3093 break;
3094 }
3095 return r;
3096}
3097
3098static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3099{
3100 int r;
3101
3102 r = 0;
3103 switch (chip->chip_id) {
3104 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3105 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3106 memcpy(&pic_irqchip(kvm)->pics[0],
3107 &chip->chip.pic,
3108 sizeof(struct kvm_pic_state));
f4f51050 3109 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3110 break;
3111 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3112 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3113 memcpy(&pic_irqchip(kvm)->pics[1],
3114 &chip->chip.pic,
3115 sizeof(struct kvm_pic_state));
f4f51050 3116 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3117 break;
3118 case KVM_IRQCHIP_IOAPIC:
eba0226b 3119 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3120 break;
3121 default:
3122 r = -EINVAL;
3123 break;
3124 }
3125 kvm_pic_update_irq(pic_irqchip(kvm));
3126 return r;
3127}
3128
e0f63cb9
SY		 3129static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3130{
3131 int r = 0;
3132
894a9c55 3133 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3134 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3135 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3136 return r;
3137}
3138
3139static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3140{
3141 int r = 0;
3142
894a9c55 3143 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3144 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3145 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3146 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3147 return r;
3148}
3149
3150static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3151{
3152 int r = 0;
3153
3154 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3155 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3156 sizeof(ps->channels));
3157 ps->flags = kvm->arch.vpit->pit_state.flags;
3158 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3159 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3160 return r;
3161}
3162
3163static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3164{
3165 int r = 0, start = 0;
3166 u32 prev_legacy, cur_legacy;
3167 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3168 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3169 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3170 if (!prev_legacy && cur_legacy)
3171 start = 1;
3172 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3173 sizeof(kvm->arch.vpit->pit_state.channels));
3174 kvm->arch.vpit->pit_state.flags = ps->flags;
3175 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3176 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3177 return r;
3178}
3179
52d939a0
MT		 3180static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3181 struct kvm_reinject_control *control)
3182{
3183 if (!kvm->arch.vpit)
3184 return -ENXIO;
894a9c55 3185 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3186 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3187 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3188 return 0;
3189}
3190
5bb064dc
ZX		 3191/*
3192 * Get (and clear) the dirty memory log for a memory slot.
3193 */
3194int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3195 struct kvm_dirty_log *log)
3196{
87bf6e7d 3197 int r, i;
5bb064dc 3198 struct kvm_memory_slot *memslot;
87bf6e7d 3199 unsigned long n;
b050b015 3200 unsigned long is_dirty = 0;
5bb064dc 3201
79fac95e 3202 mutex_lock(&kvm->slots_lock);
5bb064dc 3203
b050b015
MT		 3204 r = -EINVAL;
3205 if (log->slot >= KVM_MEMORY_SLOTS)
3206 goto out;
3207
3208 memslot = &kvm->memslots->memslots[log->slot];
3209 r = -ENOENT;
3210 if (!memslot->dirty_bitmap)
3211 goto out;
3212
87bf6e7d 3213 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3214
b050b015
MT		 3215 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3216 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3217
3218 /* If nothing is dirty, don't bother messing with page tables. */
3219 if (is_dirty) {
b050b015 3220 struct kvm_memslots *slots, *old_slots;
914ebccd 3221 unsigned long *dirty_bitmap;
b050b015 3222
515a0127
TY		 3223 dirty_bitmap = memslot->dirty_bitmap_head;
3224 if (memslot->dirty_bitmap == dirty_bitmap)
3225 dirty_bitmap += n / sizeof(long);
914ebccd 3226 memset(dirty_bitmap, 0, n);
b050b015 3227
914ebccd
TY		 3228 r = -ENOMEM;
3229 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3230 if (!slots)
914ebccd 3231 goto out;
b050b015
MT		 3232 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3233 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3234 slots->generation++;
b050b015
MT		 3235
3236 old_slots = kvm->memslots;
3237 rcu_assign_pointer(kvm->memslots, slots);
3238 synchronize_srcu_expedited(&kvm->srcu);
3239 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3240 kfree(old_slots);
914ebccd 3241
edde99ce
MT		 3242 spin_lock(&kvm->mmu_lock);
3243 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3244 spin_unlock(&kvm->mmu_lock);
3245
914ebccd 3246 r = -EFAULT;
515a0127 3247 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3248 goto out;
914ebccd
TY		 3249 } else {
3250 r = -EFAULT;
3251 if (clear_user(log->dirty_bitmap, n))
3252 goto out;
5bb064dc 3253 }
b050b015 3254
5bb064dc
ZX		 3255 r = 0;
3256out:
79fac95e 3257 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3258 return r;
3259}
3260
1fe779f8
CO		 3261long kvm_arch_vm_ioctl(struct file *filp,
3262 unsigned int ioctl, unsigned long arg)
3263{
3264 struct kvm *kvm = filp->private_data;
3265 void __user *argp = (void __user *)arg;
367e1319 3266 int r = -ENOTTY;
f0d66275
DH		 3267 /*
3268 * This union makes it completely explicit to gcc-3.x
3269 * that these two variables' stack usage should be
3270 * combined, not added together.
3271 */
3272 union {
3273 struct kvm_pit_state ps;
e9f42757 3274 struct kvm_pit_state2 ps2;
c5ff41ce 3275 struct kvm_pit_config pit_config;
f0d66275 3276 } u;
1fe779f8
CO		 3277
3278 switch (ioctl) {
3279 case KVM_SET_TSS_ADDR:
3280 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3281 if (r < 0)
3282 goto out;
3283 break;
b927a3ce
SY		 3284 case KVM_SET_IDENTITY_MAP_ADDR: {
3285 u64 ident_addr;
3286
3287 r = -EFAULT;
3288 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3289 goto out;
3290 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3291 if (r < 0)
3292 goto out;
3293 break;
3294 }
1fe779f8
CO		 3295 case KVM_SET_NR_MMU_PAGES:
3296 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3297 if (r)
3298 goto out;
3299 break;
3300 case KVM_GET_NR_MMU_PAGES:
3301 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3302 break;
3ddea128
MT		 3303 case KVM_CREATE_IRQCHIP: {
3304 struct kvm_pic *vpic;
3305
3306 mutex_lock(&kvm->lock);
3307 r = -EEXIST;
3308 if (kvm->arch.vpic)
3309 goto create_irqchip_unlock;
1fe779f8 3310 r = -ENOMEM;
3ddea128
MT		 3311 vpic = kvm_create_pic(kvm);
3312 if (vpic) {
1fe779f8
CO		 3313 r = kvm_ioapic_init(kvm);
3314 if (r) {
72bb2fcd
WY		 3315 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3316 &vpic->dev);
3ddea128
MT		 3317 kfree(vpic);
3318 goto create_irqchip_unlock;
1fe779f8
CO		 3319 }
3320 } else
3ddea128
MT		 3321 goto create_irqchip_unlock;
3322 smp_wmb();
3323 kvm->arch.vpic = vpic;
3324 smp_wmb();
399ec807
AK		 3325 r = kvm_setup_default_irq_routing(kvm);
3326 if (r) {
3ddea128 3327 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3328 kvm_ioapic_destroy(kvm);
3329 kvm_destroy_pic(kvm);
3ddea128 3330 mutex_unlock(&kvm->irq_lock);
399ec807 3331 }
3ddea128
MT		 3332 create_irqchip_unlock:
3333 mutex_unlock(&kvm->lock);
1fe779f8 3334 break;
3ddea128 3335 }
7837699f 3336 case KVM_CREATE_PIT:
c5ff41ce
JK		 3337 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3338 goto create_pit;
3339 case KVM_CREATE_PIT2:
3340 r = -EFAULT;
3341 if (copy_from_user(&u.pit_config, argp,
3342 sizeof(struct kvm_pit_config)))
3343 goto out;
3344 create_pit:
79fac95e 3345 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3346 r = -EEXIST;
3347 if (kvm->arch.vpit)
3348 goto create_pit_unlock;
7837699f 3349 r = -ENOMEM;
c5ff41ce 3350 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3351 if (kvm->arch.vpit)
3352 r = 0;
269e05e4 3353 create_pit_unlock:
79fac95e 3354 mutex_unlock(&kvm->slots_lock);
7837699f 3355 break;
4925663a 3356 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3357 case KVM_IRQ_LINE: {
3358 struct kvm_irq_level irq_event;
3359
3360 r = -EFAULT;
3361 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3362 goto out;
160d2f6c 3363 r = -ENXIO;
1fe779f8 3364 if (irqchip_in_kernel(kvm)) {
4925663a 3365 __s32 status;
4925663a
GN		 3366 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3367 irq_event.irq, irq_event.level);
4925663a 3368 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3369 r = -EFAULT;
4925663a
GN		 3370 irq_event.status = status;
3371 if (copy_to_user(argp, &irq_event,
3372 sizeof irq_event))
3373 goto out;
3374 }
1fe779f8
CO		 3375 r = 0;
3376 }
3377 break;
3378 }
3379 case KVM_GET_IRQCHIP: {
3380 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3381 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3382
f0d66275
DH		 3383 r = -ENOMEM;
3384 if (!chip)
1fe779f8 3385 goto out;
f0d66275
DH		 3386 r = -EFAULT;
3387 if (copy_from_user(chip, argp, sizeof *chip))
3388 goto get_irqchip_out;
1fe779f8
CO		 3389 r = -ENXIO;
3390 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3391 goto get_irqchip_out;
3392 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3393 if (r)
f0d66275 3394 goto get_irqchip_out;
1fe779f8 3395 r = -EFAULT;
f0d66275
DH		 3396 if (copy_to_user(argp, chip, sizeof *chip))
3397 goto get_irqchip_out;
1fe779f8 3398 r = 0;
f0d66275
DH		 3399 get_irqchip_out:
3400 kfree(chip);
3401 if (r)
3402 goto out;
1fe779f8
CO		 3403 break;
3404 }
3405 case KVM_SET_IRQCHIP: {
3406 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3407 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3408
f0d66275
DH		 3409 r = -ENOMEM;
3410 if (!chip)
1fe779f8 3411 goto out;
f0d66275
DH		 3412 r = -EFAULT;
3413 if (copy_from_user(chip, argp, sizeof *chip))
3414 goto set_irqchip_out;
1fe779f8
CO		 3415 r = -ENXIO;
3416 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3417 goto set_irqchip_out;
3418 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3419 if (r)
f0d66275 3420 goto set_irqchip_out;
1fe779f8 3421 r = 0;
f0d66275
DH		 3422 set_irqchip_out:
3423 kfree(chip);
3424 if (r)
3425 goto out;
1fe779f8
CO		 3426 break;
3427 }
e0f63cb9 3428 case KVM_GET_PIT: {
e0f63cb9 3429 r = -EFAULT;
f0d66275 3430 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3431 goto out;
3432 r = -ENXIO;
3433 if (!kvm->arch.vpit)
3434 goto out;
f0d66275 3435 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3436 if (r)
3437 goto out;
3438 r = -EFAULT;
f0d66275 3439 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3440 goto out;
3441 r = 0;
3442 break;
3443 }
3444 case KVM_SET_PIT: {
e0f63cb9 3445 r = -EFAULT;
f0d66275 3446 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3447 goto out;
3448 r = -ENXIO;
3449 if (!kvm->arch.vpit)
3450 goto out;
f0d66275 3451 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3452 if (r)
3453 goto out;
3454 r = 0;
3455 break;
3456 }
e9f42757
BK		 3457 case KVM_GET_PIT2: {
3458 r = -ENXIO;
3459 if (!kvm->arch.vpit)
3460 goto out;
3461 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3462 if (r)
3463 goto out;
3464 r = -EFAULT;
3465 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3466 goto out;
3467 r = 0;
3468 break;
3469 }
3470 case KVM_SET_PIT2: {
3471 r = -EFAULT;
3472 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3473 goto out;
3474 r = -ENXIO;
3475 if (!kvm->arch.vpit)
3476 goto out;
3477 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3478 if (r)
3479 goto out;
3480 r = 0;
3481 break;
3482 }
52d939a0
MT		 3483 case KVM_REINJECT_CONTROL: {
3484 struct kvm_reinject_control control;
3485 r = -EFAULT;
3486 if (copy_from_user(&control, argp, sizeof(control)))
3487 goto out;
3488 r = kvm_vm_ioctl_reinject(kvm, &control);
3489 if (r)
3490 goto out;
3491 r = 0;
3492 break;
3493 }
ffde22ac
ES		 3494 case KVM_XEN_HVM_CONFIG: {
3495 r = -EFAULT;
3496 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3497 sizeof(struct kvm_xen_hvm_config)))
3498 goto out;
3499 r = -EINVAL;
3500 if (kvm->arch.xen_hvm_config.flags)
3501 goto out;
3502 r = 0;
3503 break;
3504 }
afbcf7ab 3505 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3506 struct kvm_clock_data user_ns;
3507 u64 now_ns;
3508 s64 delta;
3509
3510 r = -EFAULT;
3511 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3512 goto out;
3513
3514 r = -EINVAL;
3515 if (user_ns.flags)
3516 goto out;
3517
3518 r = 0;
395c6b0a 3519 local_irq_disable();
759379dd 3520 now_ns = get_kernel_ns();
afbcf7ab 3521 delta = user_ns.clock - now_ns;
395c6b0a 3522 local_irq_enable();
afbcf7ab
GC		 3523 kvm->arch.kvmclock_offset = delta;
3524 break;
3525 }
3526 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3527 struct kvm_clock_data user_ns;
3528 u64 now_ns;
3529
395c6b0a 3530 local_irq_disable();
759379dd 3531 now_ns = get_kernel_ns();
afbcf7ab 3532 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3533 local_irq_enable();
afbcf7ab 3534 user_ns.flags = 0;
97e69aa6 3535 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3536
3537 r = -EFAULT;
3538 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3539 goto out;
3540 r = 0;
3541 break;
3542 }
3543
1fe779f8
CO		 3544 default:
3545 ;
3546 }
3547out:
3548 return r;
3549}
3550
a16b043c 3551static void kvm_init_msr_list(void)
043405e1
CO		 3552{
3553 u32 dummy[2];
3554 unsigned i, j;
3555
e3267cbb
GC		 3556 /* skip the first msrs in the list. KVM-specific */
3557 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3558 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3559 continue;
3560 if (j < i)
3561 msrs_to_save[j] = msrs_to_save[i];
3562 j++;
3563 }
3564 num_msrs_to_save = j;
3565}
3566
bda9020e
MT		 3567static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3568 const void *v)
bbd9b64e 3569{
bda9020e
MT		 3570 if (vcpu->arch.apic &&
3571 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3572 return 0;
bbd9b64e 3573
e93f8a0f 3574 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3575}
3576
bda9020e 3577static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3578{
bda9020e
MT		 3579 if (vcpu->arch.apic &&
3580 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3581 return 0;
bbd9b64e 3582
e93f8a0f 3583 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3584}
3585
2dafc6c2
GN		 3586static void kvm_set_segment(struct kvm_vcpu *vcpu,
3587 struct kvm_segment *var, int seg)
3588{
3589 kvm_x86_ops->set_segment(vcpu, var, seg);
3590}
3591
3592void kvm_get_segment(struct kvm_vcpu *vcpu,
3593 struct kvm_segment *var, int seg)
3594{
3595 kvm_x86_ops->get_segment(vcpu, var, seg);
3596}
3597
c30a358d
JR		 3598static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3599{
3600 return gpa;
3601}
3602
02f59dc9
JR		 3603static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3604{
3605 gpa_t t_gpa;
3606 u32 error;
3607
3608 BUG_ON(!mmu_is_nested(vcpu));
3609
3610 /* NPT walks are always user-walks */
3611 access |= PFERR_USER_MASK;
3612 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &error);
3613 if (t_gpa == UNMAPPED_GVA)
0959ffac 3614 vcpu->arch.fault.nested = true;
02f59dc9
JR		 3615
3616 return t_gpa;
3617}
3618
1871c602
GN		 3619gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3620{
3621 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
14dfe855 3622 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3623}
3624
3625 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3626{
3627 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3628 access |= PFERR_FETCH_MASK;
14dfe855 3629 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3630}
3631
3632gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3633{
3634 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3635 access |= PFERR_WRITE_MASK;
14dfe855 3636 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3637}
3638
3639/* uses this to access any guest's mapped memory without checking CPL */
3640gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3641{
14dfe855 3642 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error);
1871c602
GN		 3643}
3644
3645static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3646 struct kvm_vcpu *vcpu, u32 access,
3647 u32 *error)
bbd9b64e
CO		 3648{
3649 void *data = val;
10589a46 3650 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3651
3652 while (bytes) {
14dfe855
JR		 3653 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3654 error);
bbd9b64e 3655 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3656 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3657 int ret;
3658
10589a46
MT		 3659 if (gpa == UNMAPPED_GVA) {
3660 r = X86EMUL_PROPAGATE_FAULT;
3661 goto out;
3662 }
77c2002e 3663 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3664 if (ret < 0) {
c3cd7ffa 3665 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3666 goto out;
3667 }
bbd9b64e 3668
77c2002e
IE		 3669 bytes -= toread;
3670 data += toread;
3671 addr += toread;
bbd9b64e 3672 }
10589a46 3673out:
10589a46 3674 return r;
bbd9b64e 3675}
77c2002e 3676
1871c602
GN		 3677/* used for instruction fetching */
3678static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3679 struct kvm_vcpu *vcpu, u32 *error)
3680{
3681 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3682 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3683 access | PFERR_FETCH_MASK, error);
3684}
3685
3686static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3687 struct kvm_vcpu *vcpu, u32 *error)
3688{
3689 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3690 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3691 error);
3692}
3693
3694static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3695 struct kvm_vcpu *vcpu, u32 *error)
3696{
3697 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3698}
3699
7972995b 3700static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3701 unsigned int bytes,
7972995b 3702 struct kvm_vcpu *vcpu,
2dafc6c2 3703 u32 *error)
77c2002e
IE		 3704{
3705 void *data = val;
3706 int r = X86EMUL_CONTINUE;
3707
3708 while (bytes) {
14dfe855
JR		 3709 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3710 PFERR_WRITE_MASK,
3711 error);
77c2002e
IE		 3712 unsigned offset = addr & (PAGE_SIZE-1);
3713 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3714 int ret;
3715
3716 if (gpa == UNMAPPED_GVA) {
3717 r = X86EMUL_PROPAGATE_FAULT;
3718 goto out;
3719 }
3720 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3721 if (ret < 0) {
c3cd7ffa 3722 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3723 goto out;
3724 }
3725
3726 bytes -= towrite;
3727 data += towrite;
3728 addr += towrite;
3729 }
3730out:
3731 return r;
3732}
3733
bbd9b64e
CO		 3734static int emulator_read_emulated(unsigned long addr,
3735 void *val,
3736 unsigned int bytes,
8fe681e9 3737 unsigned int *error_code,
bbd9b64e
CO		 3738 struct kvm_vcpu *vcpu)
3739{
bbd9b64e
CO		 3740 gpa_t gpa;
3741
3742 if (vcpu->mmio_read_completed) {
3743 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3744 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3745 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3746 vcpu->mmio_read_completed = 0;
3747 return X86EMUL_CONTINUE;
3748 }
3749
8fe681e9 3750 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3751
8fe681e9 3752 if (gpa == UNMAPPED_GVA)
1871c602 3753 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3754
3755 /* For APIC access vmexit */
3756 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3757 goto mmio;
3758
1871c602 3759 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3760 == X86EMUL_CONTINUE)
bbd9b64e 3761 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3762
3763mmio:
3764 /*
3765 * Is this MMIO handled locally?
3766 */
aec51dc4
AK		 3767 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3768 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3769 return X86EMUL_CONTINUE;
3770 }
aec51dc4
AK		 3771
3772 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3773
3774 vcpu->mmio_needed = 1;
411c35b7
GN		 3775 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3776 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3777 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3778 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3779
c3cd7ffa 3780 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3781}
3782
3200f405 3783int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3784 const void *val, int bytes)
bbd9b64e
CO		 3785{
3786 int ret;
3787
3788 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3789 if (ret < 0)
bbd9b64e 3790 return 0;
ad218f85 3791 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3792 return 1;
3793}
3794
3795static int emulator_write_emulated_onepage(unsigned long addr,
3796 const void *val,
3797 unsigned int bytes,
8fe681e9 3798 unsigned int *error_code,
bbd9b64e
CO		 3799 struct kvm_vcpu *vcpu)
3800{
10589a46
MT		 3801 gpa_t gpa;
3802
8fe681e9 3803 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3804
8fe681e9 3805 if (gpa == UNMAPPED_GVA)
bbd9b64e 3806 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3807
3808 /* For APIC access vmexit */
3809 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3810 goto mmio;
3811
3812 if (emulator_write_phys(vcpu, gpa, val, bytes))
3813 return X86EMUL_CONTINUE;
3814
3815mmio:
aec51dc4 3816 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3817 /*
3818 * Is this MMIO handled locally?
3819 */
bda9020e 3820 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3821 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3822
3823 vcpu->mmio_needed = 1;
411c35b7
GN		 3824 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3825 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3826 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3827 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3828 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3829
3830 return X86EMUL_CONTINUE;
3831}
3832
3833int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3834 const void *val,
3835 unsigned int bytes,
8fe681e9 3836 unsigned int *error_code,
8f6abd06 3837 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3838{
3839 /* Crossing a page boundary? */
3840 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3841 int rc, now;
3842
3843 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3844 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3845 vcpu);
bbd9b64e
CO		 3846 if (rc != X86EMUL_CONTINUE)
3847 return rc;
3848 addr += now;
3849 val += now;
3850 bytes -= now;
3851 }
8fe681e9
GN		 3852 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3853 vcpu);
bbd9b64e 3854}
bbd9b64e 3855
daea3e73
AK		 3856#define CMPXCHG_TYPE(t, ptr, old, new) \
3857 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3858
3859#ifdef CONFIG_X86_64
3860# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3861#else
3862# define CMPXCHG64(ptr, old, new) \
9749a6c0 3863 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3864#endif
3865
bbd9b64e
CO		 3866static int emulator_cmpxchg_emulated(unsigned long addr,
3867 const void *old,
3868 const void *new,
3869 unsigned int bytes,
8fe681e9 3870 unsigned int *error_code,
bbd9b64e
CO		 3871 struct kvm_vcpu *vcpu)
3872{
daea3e73
AK		 3873 gpa_t gpa;
3874 struct page *page;
3875 char *kaddr;
3876 bool exchanged;
2bacc55c 3877
daea3e73
AK		 3878 /* guests cmpxchg8b have to be emulated atomically */
3879 if (bytes > 8 || (bytes & (bytes - 1)))
3880 goto emul_write;
10589a46 3881
daea3e73 3882 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3883
daea3e73
AK		 3884 if (gpa == UNMAPPED_GVA ||
3885 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3886 goto emul_write;
2bacc55c 3887
daea3e73
AK		 3888 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3889 goto emul_write;
72dc67a6 3890
daea3e73 3891 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3892 if (is_error_page(page)) {
3893 kvm_release_page_clean(page);
3894 goto emul_write;
3895 }
72dc67a6 3896
daea3e73
AK		 3897 kaddr = kmap_atomic(page, KM_USER0);
3898 kaddr += offset_in_page(gpa);
3899 switch (bytes) {
3900 case 1:
3901 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3902 break;
3903 case 2:
3904 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3905 break;
3906 case 4:
3907 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3908 break;
3909 case 8:
3910 exchanged = CMPXCHG64(kaddr, old, new);
3911 break;
3912 default:
3913 BUG();
2bacc55c 3914 }
daea3e73
AK		 3915 kunmap_atomic(kaddr, KM_USER0);
3916 kvm_release_page_dirty(page);
3917
3918 if (!exchanged)
3919 return X86EMUL_CMPXCHG_FAILED;
3920
8f6abd06
GN		 3921 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3922
3923 return X86EMUL_CONTINUE;
4a5f48f6 3924
3200f405 3925emul_write:
daea3e73 3926 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3927
8fe681e9 3928 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3929}
3930
cf8f70bf
GN		 3931static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3932{
3933 /* TODO: String I/O for in kernel device */
3934 int r;
3935
3936 if (vcpu->arch.pio.in)
3937 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3938 vcpu->arch.pio.size, pd);
3939 else
3940 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3941 vcpu->arch.pio.port, vcpu->arch.pio.size,
3942 pd);
3943 return r;
3944}
3945
3946
3947static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3948 unsigned int count, struct kvm_vcpu *vcpu)
3949{
7972995b 3950 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3951 goto data_avail;
3952
c41a15dd 3953 trace_kvm_pio(0, port, size, 1);
cf8f70bf
GN		 3954
3955 vcpu->arch.pio.port = port;
3956 vcpu->arch.pio.in = 1;
7972995b 3957 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3958 vcpu->arch.pio.size = size;
3959
3960 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3961 data_avail:
3962 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3963 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3964 return 1;
3965 }
3966
3967 vcpu->run->exit_reason = KVM_EXIT_IO;
3968 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3969 vcpu->run->io.size = size;
3970 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3971 vcpu->run->io.count = count;
3972 vcpu->run->io.port = port;
3973
3974 return 0;
3975}
3976
3977static int emulator_pio_out_emulated(int size, unsigned short port,
3978 const void *val, unsigned int count,
3979 struct kvm_vcpu *vcpu)
3980{
c41a15dd 3981 trace_kvm_pio(1, port, size, 1);
cf8f70bf
GN		 3982
3983 vcpu->arch.pio.port = port;
3984 vcpu->arch.pio.in = 0;
7972995b 3985 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3986 vcpu->arch.pio.size = size;
3987
3988 memcpy(vcpu->arch.pio_data, val, size * count);
3989
3990 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3991 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3992 return 1;
3993 }
3994
3995 vcpu->run->exit_reason = KVM_EXIT_IO;
3996 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3997 vcpu->run->io.size = size;
3998 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3999 vcpu->run->io.count = count;
4000 vcpu->run->io.port = port;
4001
4002 return 0;
4003}
4004
bbd9b64e
CO		 4005static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4006{
4007 return kvm_x86_ops->get_segment_base(vcpu, seg);
4008}
4009
4010int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
4011{
a7052897 4012 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 4013 return X86EMUL_CONTINUE;
4014}
4015
f5f48ee1
SY		 4016int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4017{
4018 if (!need_emulate_wbinvd(vcpu))
4019 return X86EMUL_CONTINUE;
4020
4021 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4022 int cpu = get_cpu();
4023
4024 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4025 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4026 wbinvd_ipi, NULL, 1);
2eec7343 4027 put_cpu();
f5f48ee1 4028 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4029 } else
4030 wbinvd();
f5f48ee1
SY		 4031 return X86EMUL_CONTINUE;
4032}
4033EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4034
bbd9b64e
CO		 4035int emulate_clts(struct kvm_vcpu *vcpu)
4036{
4d4ec087 4037 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 4038 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 4039 return X86EMUL_CONTINUE;
4040}
4041
35aa5375 4042int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 4043{
338dbc97 4044 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 4045}
4046
35aa5375 4047int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 4048{
338dbc97
GN		 4049
4050 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 4051}
4052
52a46617 4053static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4054{
52a46617 4055 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4056}
4057
52a46617 4058static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 4059{
52a46617
GN		 4060 unsigned long value;
4061
4062 switch (cr) {
4063 case 0:
4064 value = kvm_read_cr0(vcpu);
4065 break;
4066 case 2:
4067 value = vcpu->arch.cr2;
4068 break;
4069 case 3:
4070 value = vcpu->arch.cr3;
4071 break;
4072 case 4:
4073 value = kvm_read_cr4(vcpu);
4074 break;
4075 case 8:
4076 value = kvm_get_cr8(vcpu);
4077 break;
4078 default:
4079 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4080 return 0;
4081 }
4082
4083 return value;
4084}
4085
0f12244f 4086static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 4087{
0f12244f
GN		 4088 int res = 0;
4089
52a46617
GN		 4090 switch (cr) {
4091 case 0:
49a9b07e 4092 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4093 break;
4094 case 2:
4095 vcpu->arch.cr2 = val;
4096 break;
4097 case 3:
2390218b 4098 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4099 break;
4100 case 4:
a83b29c6 4101 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4102 break;
4103 case 8:
0f12244f 4104 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 4105 break;
4106 default:
4107 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4108 res = -1;
52a46617 4109 }
0f12244f
GN		 4110
4111 return res;
52a46617
GN		 4112}
4113
9c537244
GN		 4114static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4115{
4116 return kvm_x86_ops->get_cpl(vcpu);
4117}
4118
2dafc6c2
GN		 4119static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4120{
4121 kvm_x86_ops->get_gdt(vcpu, dt);
4122}
4123
160ce1f1
MG		 4124static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4125{
4126 kvm_x86_ops->get_idt(vcpu, dt);
4127}
4128
5951c442
GN		 4129static unsigned long emulator_get_cached_segment_base(int seg,
4130 struct kvm_vcpu *vcpu)
4131{
4132 return get_segment_base(vcpu, seg);
4133}
4134
2dafc6c2
GN		 4135static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4136 struct kvm_vcpu *vcpu)
4137{
4138 struct kvm_segment var;
4139
4140 kvm_get_segment(vcpu, &var, seg);
4141
4142 if (var.unusable)
4143 return false;
4144
4145 if (var.g)
4146 var.limit >>= 12;
4147 set_desc_limit(desc, var.limit);
4148 set_desc_base(desc, (unsigned long)var.base);
4149 desc->type = var.type;
4150 desc->s = var.s;
4151 desc->dpl = var.dpl;
4152 desc->p = var.present;
4153 desc->avl = var.avl;
4154 desc->l = var.l;
4155 desc->d = var.db;
4156 desc->g = var.g;
4157
4158 return true;
4159}
4160
4161static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4162 struct kvm_vcpu *vcpu)
4163{
4164 struct kvm_segment var;
4165
4166 /* needed to preserve selector */
4167 kvm_get_segment(vcpu, &var, seg);
4168
4169 var.base = get_desc_base(desc);
4170 var.limit = get_desc_limit(desc);
4171 if (desc->g)
4172 var.limit = (var.limit << 12) | 0xfff;
4173 var.type = desc->type;
4174 var.present = desc->p;
4175 var.dpl = desc->dpl;
4176 var.db = desc->d;
4177 var.s = desc->s;
4178 var.l = desc->l;
4179 var.g = desc->g;
4180 var.avl = desc->avl;
4181 var.present = desc->p;
4182 var.unusable = !var.present;
4183 var.padding = 0;
4184
4185 kvm_set_segment(vcpu, &var, seg);
4186 return;
4187}
4188
4189static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4190{
4191 struct kvm_segment kvm_seg;
4192
4193 kvm_get_segment(vcpu, &kvm_seg, seg);
4194 return kvm_seg.selector;
4195}
4196
4197static void emulator_set_segment_selector(u16 sel, int seg,
4198 struct kvm_vcpu *vcpu)
4199{
4200 struct kvm_segment kvm_seg;
4201
4202 kvm_get_segment(vcpu, &kvm_seg, seg);
4203 kvm_seg.selector = sel;
4204 kvm_set_segment(vcpu, &kvm_seg, seg);
4205}
4206
14af3f3c 4207static struct x86_emulate_ops emulate_ops = {
1871c602 4208 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4209 .write_std = kvm_write_guest_virt_system,
1871c602 4210 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4211 .read_emulated = emulator_read_emulated,
4212 .write_emulated = emulator_write_emulated,
4213 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4214 .pio_in_emulated = emulator_pio_in_emulated,
4215 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4216 .get_cached_descriptor = emulator_get_cached_descriptor,
4217 .set_cached_descriptor = emulator_set_cached_descriptor,
4218 .get_segment_selector = emulator_get_segment_selector,
4219 .set_segment_selector = emulator_set_segment_selector,
5951c442 4220 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4221 .get_gdt = emulator_get_gdt,
160ce1f1 4222 .get_idt = emulator_get_idt,
52a46617
GN		 4223 .get_cr = emulator_get_cr,
4224 .set_cr = emulator_set_cr,
9c537244 4225 .cpl = emulator_get_cpl,
35aa5375
GN		 4226 .get_dr = emulator_get_dr,
4227 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4228 .set_msr = kvm_set_msr,
4229 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4230};
4231
5fdbf976
MT		 4232static void cache_all_regs(struct kvm_vcpu *vcpu)
4233{
4234 kvm_register_read(vcpu, VCPU_REGS_RAX);
4235 kvm_register_read(vcpu, VCPU_REGS_RSP);
4236 kvm_register_read(vcpu, VCPU_REGS_RIP);
4237 vcpu->arch.regs_dirty = ~0;
4238}
4239
95cb2295
GN		 4240static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4241{
4242 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4243 /*
4244 * an sti; sti; sequence only disable interrupts for the first
4245 * instruction. So, if the last instruction, be it emulated or
4246 * not, left the system with the INT_STI flag enabled, it
4247 * means that the last instruction is an sti. We should not
4248 * leave the flag on in this case. The same goes for mov ss
4249 */
4250 if (!(int_shadow & mask))
4251 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4252}
4253
54b8486f
GN		 4254static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4255{
4256 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4257 if (ctxt->exception.vector == PF_VECTOR)
d4f8cf66 4258 kvm_propagate_fault(vcpu);
da9cb575
AK		 4259 else if (ctxt->exception.error_code_valid)
4260 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4261 ctxt->exception.error_code);
54b8486f 4262 else
da9cb575 4263 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4264}
4265
8ec4722d
MG		 4266static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4267{
4268 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4269 int cs_db, cs_l;
4270
4271 cache_all_regs(vcpu);
4272
4273 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4274
4275 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4276 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4277 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4278 vcpu->arch.emulate_ctxt.mode =
4279 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4280 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4281 ? X86EMUL_MODE_VM86 : cs_l
4282 ? X86EMUL_MODE_PROT64 : cs_db
4283 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4284 memset(c, 0, sizeof(struct decode_cache));
4285 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4286}
4287
63995653
MG		 4288int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4289{
4290 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4291 int ret;
4292
4293 init_emulate_ctxt(vcpu);
4294
4295 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4296 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4297 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4298 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4299
4300 if (ret != X86EMUL_CONTINUE)
4301 return EMULATE_FAIL;
4302
4303 vcpu->arch.emulate_ctxt.eip = c->eip;
4304 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4305 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4306 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4307
4308 if (irq == NMI_VECTOR)
4309 vcpu->arch.nmi_pending = false;
4310 else
4311 vcpu->arch.interrupt.pending = false;
4312
4313 return EMULATE_DONE;
4314}
4315EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4316
6d77dbfc
GN		 4317static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4318{
6d77dbfc
GN		 4319 ++vcpu->stat.insn_emulation_fail;
4320 trace_kvm_emulate_insn_failed(vcpu);
4321 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4322 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4323 vcpu->run->internal.ndata = 0;
4324 kvm_queue_exception(vcpu, UD_VECTOR);
4325 return EMULATE_FAIL;
4326}
4327
a6f177ef
GN		 4328static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4329{
4330 gpa_t gpa;
4331
68be0803
GN		 4332 if (tdp_enabled)
4333 return false;
4334
a6f177ef
GN		 4335 /*
4336 * if emulation was due to access to shadowed page table
4337 * and it failed try to unshadow page and re-entetr the
4338 * guest to let CPU execute the instruction.
4339 */
4340 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4341 return true;
4342
4343 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4344
4345 if (gpa == UNMAPPED_GVA)
4346 return true; /* let cpu generate fault */
4347
4348 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4349 return true;
4350
4351 return false;
4352}
4353
bbd9b64e 4354int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4355 unsigned long cr2,
4356 u16 error_code,
571008da 4357 int emulation_type)
bbd9b64e 4358{
95cb2295 4359 int r;
4d2179e1 4360 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4361
26eef70c 4362 kvm_clear_exception_queue(vcpu);
ad312c7c 4363 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4364 /*
56e82318 4365 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4366 * instead of direct ->regs accesses, can save hundred cycles
4367 * on Intel for instructions that don't read/change RSP, for
4368 * for example.
4369 */
4370 cache_all_regs(vcpu);
bbd9b64e 4371
571008da 4372 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4373 init_emulate_ctxt(vcpu);
95cb2295 4374 vcpu->arch.emulate_ctxt.interruptibility = 0;
da9cb575 4375 vcpu->arch.emulate_ctxt.have_exception = false;
4fc40f07 4376 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4377
9aabc88f 4378 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
d47f00a6
JR		 4379 if (r == X86EMUL_PROPAGATE_FAULT)
4380 goto done;
bbd9b64e 4381
e46479f8 4382 trace_kvm_emulate_insn_start(vcpu);
571008da 4383
0cb5762e
AP		 4384 /* Only allow emulation of specific instructions on #UD
4385 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4386 if (emulation_type & EMULTYPE_TRAP_UD) {
4387 if (!c->twobyte)
4388 return EMULATE_FAIL;
4389 switch (c->b) {
4390 case 0x01: /* VMMCALL */
4391 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4392 return EMULATE_FAIL;
4393 break;
4394 case 0x34: /* sysenter */
4395 case 0x35: /* sysexit */
4396 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4397 return EMULATE_FAIL;
4398 break;
4399 case 0x05: /* syscall */
4400 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4401 return EMULATE_FAIL;
4402 break;
4403 default:
4404 return EMULATE_FAIL;
4405 }
4406
4407 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4408 return EMULATE_FAIL;
4409 }
571008da 4410
f2b5756b 4411 ++vcpu->stat.insn_emulation;
bbd9b64e 4412 if (r) {
a6f177ef 4413 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4414 return EMULATE_DONE;
6d77dbfc
GN		 4415 if (emulation_type & EMULTYPE_SKIP)
4416 return EMULATE_FAIL;
4417 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4418 }
4419 }
4420
ba8afb6b
GN		 4421 if (emulation_type & EMULTYPE_SKIP) {
4422 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4423 return EMULATE_DONE;
4424 }
4425
4d2179e1
GN		 4426 /* this is needed for vmware backdor interface to work since it
4427 changes registers values during IO operation */
4428 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4429
5cd21917 4430restart:
9aabc88f 4431 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4432
d2ddd1c4 4433 if (r == EMULATION_FAILED) {
a6f177ef 4434 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4435 return EMULATE_DONE;
4436
6d77dbfc 4437 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4438 }
4439
d47f00a6 4440done:
da9cb575 4441 if (vcpu->arch.emulate_ctxt.have_exception) {
54b8486f 4442 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4443 r = EMULATE_DONE;
4444 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4445 if (!vcpu->arch.pio.in)
4446 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4447 r = EMULATE_DO_MMIO;
4448 } else if (vcpu->mmio_needed) {
3457e419
GN		 4449 if (vcpu->mmio_is_write)
4450 vcpu->mmio_needed = 0;
e85d28f8 4451 r = EMULATE_DO_MMIO;
d2ddd1c4 4452 } else if (r == EMULATION_RESTART)
5cd21917 4453 goto restart;
d2ddd1c4
GN		 4454 else
4455 r = EMULATE_DONE;
f850e2e6 4456
e85d28f8
GN		 4457 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4458 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4459 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4460 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4461 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4462
4463 return r;
de7d789a 4464}
bbd9b64e 4465EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4466
cf8f70bf 4467int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4468{
cf8f70bf
GN		 4469 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4470 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4471 /* do not return to emulator after return from userspace */
7972995b 4472 vcpu->arch.pio.count = 0;
de7d789a
CO		 4473 return ret;
4474}
cf8f70bf 4475EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4476
8cfdc000
ZA		 4477static void tsc_bad(void *info)
4478{
4479 __get_cpu_var(cpu_tsc_khz) = 0;
4480}
4481
4482static void tsc_khz_changed(void *data)
c8076604 4483{
8cfdc000
ZA		 4484 struct cpufreq_freqs *freq = data;
4485 unsigned long khz = 0;
4486
4487 if (data)
4488 khz = freq->new;
4489 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4490 khz = cpufreq_quick_get(raw_smp_processor_id());
4491 if (!khz)
4492 khz = tsc_khz;
4493 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4494}
4495
c8076604
GH		 4496static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4497 void *data)
4498{
4499 struct cpufreq_freqs *freq = data;
4500 struct kvm *kvm;
4501 struct kvm_vcpu *vcpu;
4502 int i, send_ipi = 0;
4503
8cfdc000
ZA		 4504 /*
4505 * We allow guests to temporarily run on slowing clocks,
4506 * provided we notify them after, or to run on accelerating
4507 * clocks, provided we notify them before. Thus time never
4508 * goes backwards.
4509 *
4510 * However, we have a problem. We can't atomically update
4511 * the frequency of a given CPU from this function; it is
4512 * merely a notifier, which can be called from any CPU.
4513 * Changing the TSC frequency at arbitrary points in time
4514 * requires a recomputation of local variables related to
4515 * the TSC for each VCPU. We must flag these local variables
4516 * to be updated and be sure the update takes place with the
4517 * new frequency before any guests proceed.
4518 *
4519 * Unfortunately, the combination of hotplug CPU and frequency
4520 * change creates an intractable locking scenario; the order
4521 * of when these callouts happen is undefined with respect to
4522 * CPU hotplug, and they can race with each other. As such,
4523 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4524 * undefined; you can actually have a CPU frequency change take
4525 * place in between the computation of X and the setting of the
4526 * variable. To protect against this problem, all updates of
4527 * the per_cpu tsc_khz variable are done in an interrupt
4528 * protected IPI, and all callers wishing to update the value
4529 * must wait for a synchronous IPI to complete (which is trivial
4530 * if the caller is on the CPU already). This establishes the
4531 * necessary total order on variable updates.
4532 *
4533 * Note that because a guest time update may take place
4534 * anytime after the setting of the VCPU's request bit, the
4535 * correct TSC value must be set before the request. However,
4536 * to ensure the update actually makes it to any guest which
4537 * starts running in hardware virtualization between the set
4538 * and the acquisition of the spinlock, we must also ping the
4539 * CPU after setting the request bit.
4540 *
4541 */
4542
c8076604
GH		 4543 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4544 return 0;
4545 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4546 return 0;
8cfdc000
ZA		 4547
4548 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4549
4550 spin_lock(&kvm_lock);
4551 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4552 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4553 if (vcpu->cpu != freq->cpu)
4554 continue;
c285545f 4555 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4556 if (vcpu->cpu != smp_processor_id())
8cfdc000 4557 send_ipi = 1;
c8076604
GH		 4558 }
4559 }
4560 spin_unlock(&kvm_lock);
4561
4562 if (freq->old < freq->new && send_ipi) {
4563 /*
4564 * We upscale the frequency. Must make the guest
4565 * doesn't see old kvmclock values while running with
4566 * the new frequency, otherwise we risk the guest sees
4567 * time go backwards.
4568 *
4569 * In case we update the frequency for another cpu
4570 * (which might be in guest context) send an interrupt
4571 * to kick the cpu out of guest context. Next time
4572 * guest context is entered kvmclock will be updated,
4573 * so the guest will not see stale values.
4574 */
8cfdc000 4575 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4576 }
4577 return 0;
4578}
4579
4580static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4581 .notifier_call = kvmclock_cpufreq_notifier
4582};
4583
4584static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4585 unsigned long action, void *hcpu)
4586{
4587 unsigned int cpu = (unsigned long)hcpu;
4588
4589 switch (action) {
4590 case CPU_ONLINE:
4591 case CPU_DOWN_FAILED:
4592 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4593 break;
4594 case CPU_DOWN_PREPARE:
4595 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4596 break;
4597 }
4598 return NOTIFY_OK;
4599}
4600
4601static struct notifier_block kvmclock_cpu_notifier_block = {
4602 .notifier_call = kvmclock_cpu_notifier,
4603 .priority = -INT_MAX
c8076604
GH		 4604};
4605
b820cc0c
ZA		 4606static void kvm_timer_init(void)
4607{
4608 int cpu;
4609
c285545f 4610 max_tsc_khz = tsc_khz;
8cfdc000 4611 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4612 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4613#ifdef CONFIG_CPU_FREQ
4614 struct cpufreq_policy policy;
4615 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4616 cpu = get_cpu();
4617 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4618 if (policy.cpuinfo.max_freq)
4619 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4620 put_cpu();
c285545f 4621#endif
b820cc0c
ZA		 4622 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4623 CPUFREQ_TRANSITION_NOTIFIER);
4624 }
c285545f 4625 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4626 for_each_online_cpu(cpu)
4627 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4628}
4629
ff9d07a0
ZY		 4630static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4631
4632static int kvm_is_in_guest(void)
4633{
4634 return percpu_read(current_vcpu) != NULL;
4635}
4636
4637static int kvm_is_user_mode(void)
4638{
4639 int user_mode = 3;
dcf46b94 4640
ff9d07a0
ZY		 4641 if (percpu_read(current_vcpu))
4642 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4643
ff9d07a0
ZY		 4644 return user_mode != 0;
4645}
4646
4647static unsigned long kvm_get_guest_ip(void)
4648{
4649 unsigned long ip = 0;
dcf46b94 4650
ff9d07a0
ZY		 4651 if (percpu_read(current_vcpu))
4652 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4653
ff9d07a0
ZY		 4654 return ip;
4655}
4656
4657static struct perf_guest_info_callbacks kvm_guest_cbs = {
4658 .is_in_guest = kvm_is_in_guest,
4659 .is_user_mode = kvm_is_user_mode,
4660 .get_guest_ip = kvm_get_guest_ip,
4661};
4662
4663void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4664{
4665 percpu_write(current_vcpu, vcpu);
4666}
4667EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4668
4669void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4670{
4671 percpu_write(current_vcpu, NULL);
4672}
4673EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4674
f8c16bba 4675int kvm_arch_init(void *opaque)
043405e1 4676{
b820cc0c 4677 int r;
f8c16bba
ZX		 4678 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4679
f8c16bba
ZX		 4680 if (kvm_x86_ops) {
4681 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4682 r = -EEXIST;
4683 goto out;
f8c16bba
ZX		 4684 }
4685
4686 if (!ops->cpu_has_kvm_support()) {
4687 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4688 r = -EOPNOTSUPP;
4689 goto out;
f8c16bba
ZX		 4690 }
4691 if (ops->disabled_by_bios()) {
4692 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4693 r = -EOPNOTSUPP;
4694 goto out;
f8c16bba
ZX		 4695 }
4696
97db56ce
AK		 4697 r = kvm_mmu_module_init();
4698 if (r)
4699 goto out;
4700
4701 kvm_init_msr_list();
4702
f8c16bba 4703 kvm_x86_ops = ops;
56c6d28a 4704 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e 4705 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4706 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4707
b820cc0c 4708 kvm_timer_init();
c8076604 4709
ff9d07a0
ZY		 4710 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4711
2acf923e
DC		 4712 if (cpu_has_xsave)
4713 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4714
f8c16bba 4715 return 0;
56c6d28a
ZX		 4716
4717out:
56c6d28a 4718 return r;
043405e1 4719}
8776e519 4720
f8c16bba
ZX		 4721void kvm_arch_exit(void)
4722{
ff9d07a0
ZY		 4723 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4724
888d256e
JK		 4725 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4726 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4727 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4728 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4729 kvm_x86_ops = NULL;
56c6d28a
ZX		 4730 kvm_mmu_module_exit();
4731}
f8c16bba 4732
8776e519
HB		 4733int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4734{
4735 ++vcpu->stat.halt_exits;
4736 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4737 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4738 return 1;
4739 } else {
4740 vcpu->run->exit_reason = KVM_EXIT_HLT;
4741 return 0;
4742 }
4743}
4744EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4745
2f333bcb
MT		 4746static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4747 unsigned long a1)
4748{
4749 if (is_long_mode(vcpu))
4750 return a0;
4751 else
4752 return a0 | ((gpa_t)a1 << 32);
4753}
4754
55cd8e5a
GN		 4755int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4756{
4757 u64 param, ingpa, outgpa, ret;
4758 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4759 bool fast, longmode;
4760 int cs_db, cs_l;
4761
4762 /*
4763 * hypercall generates UD from non zero cpl and real mode
4764 * per HYPER-V spec
4765 */
3eeb3288 4766 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4767 kvm_queue_exception(vcpu, UD_VECTOR);
4768 return 0;
4769 }
4770
4771 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4772 longmode = is_long_mode(vcpu) && cs_l == 1;
4773
4774 if (!longmode) {
ccd46936
GN		 4775 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4776 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4777 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4778 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4779 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4780 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4781 }
4782#ifdef CONFIG_X86_64
4783 else {
4784 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4785 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4786 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4787 }
4788#endif
4789
4790 code = param & 0xffff;
4791 fast = (param >> 16) & 0x1;
4792 rep_cnt = (param >> 32) & 0xfff;
4793 rep_idx = (param >> 48) & 0xfff;
4794
4795 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4796
c25bc163
GN		 4797 switch (code) {
4798 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4799 kvm_vcpu_on_spin(vcpu);
4800 break;
4801 default:
4802 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4803 break;
4804 }
55cd8e5a
GN		 4805
4806 ret = res | (((u64)rep_done & 0xfff) << 32);
4807 if (longmode) {
4808 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4809 } else {
4810 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4811 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4812 }
4813
4814 return 1;
4815}
4816
8776e519
HB		 4817int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4818{
4819 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4820 int r = 1;
8776e519 4821
55cd8e5a
GN		 4822 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4823 return kvm_hv_hypercall(vcpu);
4824
5fdbf976
MT		 4825 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4826 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4827 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4828 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4829 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4830
229456fc 4831 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4832
8776e519
HB		 4833 if (!is_long_mode(vcpu)) {
4834 nr &= 0xFFFFFFFF;
4835 a0 &= 0xFFFFFFFF;
4836 a1 &= 0xFFFFFFFF;
4837 a2 &= 0xFFFFFFFF;
4838 a3 &= 0xFFFFFFFF;
4839 }
4840
07708c4a
JK		 4841 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4842 ret = -KVM_EPERM;
4843 goto out;
4844 }
4845
8776e519 4846 switch (nr) {
b93463aa
AK		 4847 case KVM_HC_VAPIC_POLL_IRQ:
4848 ret = 0;
4849 break;
2f333bcb
MT		 4850 case KVM_HC_MMU_OP:
4851 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4852 break;
8776e519
HB		 4853 default:
4854 ret = -KVM_ENOSYS;
4855 break;
4856 }
07708c4a 4857out:
5fdbf976 4858 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4859 ++vcpu->stat.hypercalls;
2f333bcb 4860 return r;
8776e519
HB		 4861}
4862EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4863
4864int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4865{
4866 char instruction[3];
5fdbf976 4867 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4868
8776e519
HB		 4869 /*
4870 * Blow out the MMU to ensure that no other VCPU has an active mapping
4871 * to ensure that the updated hypercall appears atomically across all
4872 * VCPUs.
4873 */
4874 kvm_mmu_zap_all(vcpu->kvm);
4875
8776e519 4876 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4877
8fe681e9 4878 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4879}
4880
8776e519
HB		 4881void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4882{
89a27f4d 4883 struct desc_ptr dt = { limit, base };
8776e519
HB		 4884
4885 kvm_x86_ops->set_gdt(vcpu, &dt);
4886}
4887
4888void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4889{
89a27f4d 4890 struct desc_ptr dt = { limit, base };
8776e519
HB		 4891
4892 kvm_x86_ops->set_idt(vcpu, &dt);
4893}
4894
07716717
DK		 4895static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4896{
ad312c7c
ZX		 4897 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4898 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4899
4900 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4901 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4902 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4903 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4904 if (ej->function == e->function) {
4905 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4906 return j;
4907 }
4908 }
4909 return 0; /* silence gcc, even though control never reaches here */
4910}
4911
4912/* find an entry with matching function, matching index (if needed), and that
4913 * should be read next (if it's stateful) */
4914static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4915 u32 function, u32 index)
4916{
4917 if (e->function != function)
4918 return 0;
4919 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4920 return 0;
4921 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4922 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4923 return 0;
4924 return 1;
4925}
4926
d8017474
AG		 4927struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4928 u32 function, u32 index)
8776e519
HB		 4929{
4930 int i;
d8017474 4931 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4932
ad312c7c 4933 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4934 struct kvm_cpuid_entry2 *e;
4935
ad312c7c 4936 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4937 if (is_matching_cpuid_entry(e, function, index)) {
4938 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4939 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4940 best = e;
4941 break;
4942 }
4943 /*
4944 * Both basic or both extended?
4945 */
4946 if (((e->function ^ function) & 0x80000000) == 0)
4947 if (!best || e->function > best->function)
4948 best = e;
4949 }
d8017474
AG		 4950 return best;
4951}
0e851880 4952EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4953
82725b20
DE		 4954int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4955{
4956 struct kvm_cpuid_entry2 *best;
4957
f7a71197
AK		 4958 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4959 if (!best || best->eax < 0x80000008)
4960 goto not_found;
82725b20
DE		 4961 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4962 if (best)
4963 return best->eax & 0xff;
f7a71197 4964not_found:
82725b20
DE		 4965 return 36;
4966}
4967
d8017474
AG		 4968void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4969{
4970 u32 function, index;
4971 struct kvm_cpuid_entry2 *best;
4972
4973 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4974 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4975 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4976 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4977 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4978 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4979 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4980 if (best) {
5fdbf976
MT		 4981 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4982 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4983 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4984 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4985 }
8776e519 4986 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4987 trace_kvm_cpuid(function,
4988 kvm_register_read(vcpu, VCPU_REGS_RAX),
4989 kvm_register_read(vcpu, VCPU_REGS_RBX),
4990 kvm_register_read(vcpu, VCPU_REGS_RCX),
4991 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4992}
4993EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4994
b6c7a5dc
HB		 4995/*
4996 * Check if userspace requested an interrupt window, and that the
4997 * interrupt window is open.
4998 *
4999 * No need to exit to userspace if we already have an interrupt queued.
5000 */
851ba692 5001static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5002{
8061823a 5003 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5004 vcpu->run->request_interrupt_window &&
5df56646 5005 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5006}
5007
851ba692 5008static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5009{
851ba692
AK		 5010 struct kvm_run *kvm_run = vcpu->run;
5011
91586a3b 5012 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5013 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5014 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5015 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5016 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5017 else
b6c7a5dc 5018 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5019 kvm_arch_interrupt_allowed(vcpu) &&
5020 !kvm_cpu_has_interrupt(vcpu) &&
5021 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5022}
5023
b93463aa
AK		 5024static void vapic_enter(struct kvm_vcpu *vcpu)
5025{
5026 struct kvm_lapic *apic = vcpu->arch.apic;
5027 struct page *page;
5028
5029 if (!apic || !apic->vapic_addr)
5030 return;
5031
5032 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5033
5034 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5035}
5036
5037static void vapic_exit(struct kvm_vcpu *vcpu)
5038{
5039 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5040 int idx;
b93463aa
AK		 5041
5042 if (!apic || !apic->vapic_addr)
5043 return;
5044
f656ce01 5045 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5046 kvm_release_page_dirty(apic->vapic_page);
5047 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5048 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5049}
5050
95ba8273
GN		 5051static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5052{
5053 int max_irr, tpr;
5054
5055 if (!kvm_x86_ops->update_cr8_intercept)
5056 return;
5057
88c808fd
AK		 5058 if (!vcpu->arch.apic)
5059 return;
5060
8db3baa2
GN		 5061 if (!vcpu->arch.apic->vapic_addr)
5062 max_irr = kvm_lapic_find_highest_irr(vcpu);
5063 else
5064 max_irr = -1;
95ba8273
GN		 5065
5066 if (max_irr != -1)
5067 max_irr >>= 4;
5068
5069 tpr = kvm_lapic_get_cr8(vcpu);
5070
5071 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5072}
5073
851ba692 5074static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5075{
5076 /* try to reinject previous events if any */
b59bb7bd 5077 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5078 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5079 vcpu->arch.exception.has_error_code,
5080 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5081 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5082 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5083 vcpu->arch.exception.error_code,
5084 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5085 return;
5086 }
5087
95ba8273
GN		 5088 if (vcpu->arch.nmi_injected) {
5089 kvm_x86_ops->set_nmi(vcpu);
5090 return;
5091 }
5092
5093 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5094 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5095 return;
5096 }
5097
5098 /* try to inject new event if pending */
5099 if (vcpu->arch.nmi_pending) {
5100 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5101 vcpu->arch.nmi_pending = false;
5102 vcpu->arch.nmi_injected = true;
5103 kvm_x86_ops->set_nmi(vcpu);
5104 }
5105 } else if (kvm_cpu_has_interrupt(vcpu)) {
5106 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5107 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5108 false);
5109 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5110 }
5111 }
5112}
5113
2acf923e
DC		 5114static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5115{
5116 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5117 !vcpu->guest_xcr0_loaded) {
5118 /* kvm_set_xcr() also depends on this */
5119 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5120 vcpu->guest_xcr0_loaded = 1;
5121 }
5122}
5123
5124static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5125{
5126 if (vcpu->guest_xcr0_loaded) {
5127 if (vcpu->arch.xcr0 != host_xcr0)
5128 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5129 vcpu->guest_xcr0_loaded = 0;
5130 }
5131}
5132
851ba692 5133static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5134{
5135 int r;
6a8b1d13 5136 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5137 vcpu->run->request_interrupt_window;
b6c7a5dc 5138
3e007509 5139 if (vcpu->requests) {
a8eeb04a 5140 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5141 kvm_mmu_unload(vcpu);
a8eeb04a 5142 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5143 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5144 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5145 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5146 if (unlikely(r))
5147 goto out;
5148 }
a8eeb04a 5149 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5150 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5151 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5152 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5153 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5154 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5155 r = 0;
5156 goto out;
5157 }
a8eeb04a 5158 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5159 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5160 r = 0;
5161 goto out;
5162 }
a8eeb04a 5163 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5164 vcpu->fpu_active = 0;
5165 kvm_x86_ops->fpu_deactivate(vcpu);
5166 }
af585b92
GN		 5167 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5168 /* Page is swapped out. Do synthetic halt */
5169 vcpu->arch.apf.halted = true;
5170 r = 1;
5171 goto out;
5172 }
2f52d58c 5173 }
b93463aa 5174
3e007509
AK		 5175 r = kvm_mmu_reload(vcpu);
5176 if (unlikely(r))
5177 goto out;
5178
b463a6f7
AK		 5179 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5180 inject_pending_event(vcpu);
5181
5182 /* enable NMI/IRQ window open exits if needed */
5183 if (vcpu->arch.nmi_pending)
5184 kvm_x86_ops->enable_nmi_window(vcpu);
5185 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5186 kvm_x86_ops->enable_irq_window(vcpu);
5187
5188 if (kvm_lapic_enabled(vcpu)) {
5189 update_cr8_intercept(vcpu);
5190 kvm_lapic_sync_to_vapic(vcpu);
5191 }
5192 }
5193
b6c7a5dc
HB		 5194 preempt_disable();
5195
5196 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5197 if (vcpu->fpu_active)
5198 kvm_load_guest_fpu(vcpu);
2acf923e 5199 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5200
d94e1dc9
AK		 5201 atomic_set(&vcpu->guest_mode, 1);
5202 smp_wmb();
b6c7a5dc 5203
d94e1dc9 5204 local_irq_disable();
32f88400 5205
d94e1dc9
AK		 5206 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5207 || need_resched() || signal_pending(current)) {
5208 atomic_set(&vcpu->guest_mode, 0);
5209 smp_wmb();
6c142801
AK		 5210 local_irq_enable();
5211 preempt_enable();
b463a6f7 5212 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5213 r = 1;
5214 goto out;
5215 }
5216
f656ce01 5217 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5218
b6c7a5dc
HB		 5219 kvm_guest_enter();
5220
42dbaa5a 5221 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5222 set_debugreg(0, 7);
5223 set_debugreg(vcpu->arch.eff_db[0], 0);
5224 set_debugreg(vcpu->arch.eff_db[1], 1);
5225 set_debugreg(vcpu->arch.eff_db[2], 2);
5226 set_debugreg(vcpu->arch.eff_db[3], 3);
5227 }
b6c7a5dc 5228
229456fc 5229 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5230 kvm_x86_ops->run(vcpu);
b6c7a5dc 5231
24f1e32c
FW		 5232 /*
5233 * If the guest has used debug registers, at least dr7
5234 * will be disabled while returning to the host.
5235 * If we don't have active breakpoints in the host, we don't
5236 * care about the messed up debug address registers. But if
5237 * we have some of them active, restore the old state.
5238 */
59d8eb53 5239 if (hw_breakpoint_active())
24f1e32c 5240 hw_breakpoint_restore();
42dbaa5a 5241
1d5f066e
ZA		 5242 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5243
d94e1dc9
AK		 5244 atomic_set(&vcpu->guest_mode, 0);
5245 smp_wmb();
b6c7a5dc
HB		 5246 local_irq_enable();
5247
5248 ++vcpu->stat.exits;
5249
5250 /*
5251 * We must have an instruction between local_irq_enable() and
5252 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5253 * the interrupt shadow. The stat.exits increment will do nicely.
5254 * But we need to prevent reordering, hence this barrier():
5255 */
5256 barrier();
5257
5258 kvm_guest_exit();
5259
5260 preempt_enable();
5261
f656ce01 5262 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5263
b6c7a5dc
HB		 5264 /*
5265 * Profile KVM exit RIPs:
5266 */
5267 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5268 unsigned long rip = kvm_rip_read(vcpu);
5269 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5270 }
5271
298101da 5272
b93463aa
AK		 5273 kvm_lapic_sync_from_vapic(vcpu);
5274
851ba692 5275 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5276out:
5277 return r;
5278}
b6c7a5dc 5279
09cec754 5280
851ba692 5281static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5282{
5283 int r;
f656ce01 5284 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5285
5286 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5287 pr_debug("vcpu %d received sipi with vector # %x\n",
5288 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5289 kvm_lapic_reset(vcpu);
5f179287 5290 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5291 if (r)
5292 return r;
5293 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5294 }
5295
f656ce01 5296 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5297 vapic_enter(vcpu);
5298
5299 r = 1;
5300 while (r > 0) {
af585b92
GN		 5301 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5302 !vcpu->arch.apf.halted)
851ba692 5303 r = vcpu_enter_guest(vcpu);
d7690175 5304 else {
f656ce01 5305 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5306 kvm_vcpu_block(vcpu);
f656ce01 5307 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5308 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5309 {
5310 switch(vcpu->arch.mp_state) {
5311 case KVM_MP_STATE_HALTED:
d7690175 5312 vcpu->arch.mp_state =
09cec754
GN		 5313 KVM_MP_STATE_RUNNABLE;
5314 case KVM_MP_STATE_RUNNABLE:
af585b92 5315 vcpu->arch.apf.halted = false;
09cec754
GN		 5316 break;
5317 case KVM_MP_STATE_SIPI_RECEIVED:
5318 default:
5319 r = -EINTR;
5320 break;
5321 }
5322 }
d7690175
MT		 5323 }
5324
09cec754
GN		 5325 if (r <= 0)
5326 break;
5327
5328 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5329 if (kvm_cpu_has_pending_timer(vcpu))
5330 kvm_inject_pending_timer_irqs(vcpu);
5331
851ba692 5332 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5333 r = -EINTR;
851ba692 5334 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5335 ++vcpu->stat.request_irq_exits;
5336 }
af585b92
GN		 5337
5338 kvm_check_async_pf_completion(vcpu);
5339
09cec754
GN		 5340 if (signal_pending(current)) {
5341 r = -EINTR;
851ba692 5342 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5343 ++vcpu->stat.signal_exits;
5344 }
5345 if (need_resched()) {
f656ce01 5346 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5347 kvm_resched(vcpu);
f656ce01 5348 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5349 }
b6c7a5dc
HB		 5350 }
5351
f656ce01 5352 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5353
b93463aa
AK		 5354 vapic_exit(vcpu);
5355
b6c7a5dc
HB		 5356 return r;
5357}
5358
5359int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5360{
5361 int r;
5362 sigset_t sigsaved;
5363
ac9f6dc0
AK		 5364 if (vcpu->sigset_active)
5365 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5366
a4535290 5367 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5368 kvm_vcpu_block(vcpu);
d7690175 5369 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5370 r = -EAGAIN;
5371 goto out;
b6c7a5dc
HB		 5372 }
5373
b6c7a5dc
HB		 5374 /* re-sync apic's tpr */
5375 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5376 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5377
d2ddd1c4 5378 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5379 if (vcpu->mmio_needed) {
5380 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5381 vcpu->mmio_read_completed = 1;
5382 vcpu->mmio_needed = 0;
b6c7a5dc 5383 }
f656ce01 5384 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5385 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5386 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5387 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5388 r = 0;
5389 goto out;
5390 }
5391 }
5fdbf976
MT		 5392 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5393 kvm_register_write(vcpu, VCPU_REGS_RAX,
5394 kvm_run->hypercall.ret);
b6c7a5dc 5395
851ba692 5396 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5397
5398out:
f1d86e46 5399 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5400 if (vcpu->sigset_active)
5401 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5402
b6c7a5dc
HB		 5403 return r;
5404}
5405
5406int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5407{
5fdbf976
MT		 5408 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5409 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5410 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5411 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5412 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5413 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5414 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5415 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5416#ifdef CONFIG_X86_64
5fdbf976
MT		 5417 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5418 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5419 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5420 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5421 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5422 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5423 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5424 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5425#endif
5426
5fdbf976 5427 regs->rip = kvm_rip_read(vcpu);
91586a3b 5428 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5429
b6c7a5dc
HB		 5430 return 0;
5431}
5432
5433int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5434{
5fdbf976
MT		 5435 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5436 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5437 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5438 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5439 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5440 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5441 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5442 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5443#ifdef CONFIG_X86_64
5fdbf976
MT		 5444 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5445 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5446 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5447 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5448 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5449 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5450 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5451 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5452#endif
5453
5fdbf976 5454 kvm_rip_write(vcpu, regs->rip);
91586a3b 5455 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5456
b4f14abd
JK		 5457 vcpu->arch.exception.pending = false;
5458
3842d135
AK		 5459 kvm_make_request(KVM_REQ_EVENT, vcpu);
5460
b6c7a5dc
HB		 5461 return 0;
5462}
5463
b6c7a5dc
HB		 5464void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5465{
5466 struct kvm_segment cs;
5467
3e6e0aab 5468 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5469 *db = cs.db;
5470 *l = cs.l;
5471}
5472EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5473
5474int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5475 struct kvm_sregs *sregs)
5476{
89a27f4d 5477 struct desc_ptr dt;
b6c7a5dc 5478
3e6e0aab
GT		 5479 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5480 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5481 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5482 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5483 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5484 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5485
3e6e0aab
GT		 5486 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5487 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5488
5489 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5490 sregs->idt.limit = dt.size;
5491 sregs->idt.base = dt.address;
b6c7a5dc 5492 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5493 sregs->gdt.limit = dt.size;
5494 sregs->gdt.base = dt.address;
b6c7a5dc 5495
4d4ec087 5496 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5497 sregs->cr2 = vcpu->arch.cr2;
5498 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5499 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5500 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5501 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5502 sregs->apic_base = kvm_get_apic_base(vcpu);
5503
923c61bb 5504 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5505
36752c9b 5506 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5507 set_bit(vcpu->arch.interrupt.nr,
5508 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5509
b6c7a5dc
HB		 5510 return 0;
5511}
5512
62d9f0db
MT		 5513int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5514 struct kvm_mp_state *mp_state)
5515{
62d9f0db 5516 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5517 return 0;
5518}
5519
5520int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5521 struct kvm_mp_state *mp_state)
5522{
62d9f0db 5523 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5524 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5525 return 0;
5526}
5527
e269fb21
JK		 5528int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5529 bool has_error_code, u32 error_code)
b6c7a5dc 5530{
4d2179e1 5531 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5532 int ret;
e01c2426 5533
8ec4722d 5534 init_emulate_ctxt(vcpu);
c697518a 5535
9aabc88f 5536 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5537 tss_selector, reason, has_error_code,
5538 error_code);
c697518a 5539
c697518a 5540 if (ret)
19d04437 5541 return EMULATE_FAIL;
37817f29 5542
4d2179e1 5543 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5544 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437 5545 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5546 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5547 return EMULATE_DONE;
37817f29
IE		 5548}
5549EXPORT_SYMBOL_GPL(kvm_task_switch);
5550
b6c7a5dc
HB		 5551int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5552 struct kvm_sregs *sregs)
5553{
5554 int mmu_reset_needed = 0;
923c61bb 5555 int pending_vec, max_bits;
89a27f4d 5556 struct desc_ptr dt;
b6c7a5dc 5557
89a27f4d
GN		 5558 dt.size = sregs->idt.limit;
5559 dt.address = sregs->idt.base;
b6c7a5dc 5560 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5561 dt.size = sregs->gdt.limit;
5562 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5563 kvm_x86_ops->set_gdt(vcpu, &dt);
5564
ad312c7c
ZX		 5565 vcpu->arch.cr2 = sregs->cr2;
5566 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5567 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5568
2d3ad1f4 5569 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5570
f6801dff 5571 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5572 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5573 kvm_set_apic_base(vcpu, sregs->apic_base);
5574
4d4ec087 5575 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5576 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5577 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5578
fc78f519 5579 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5580 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5581 if (sregs->cr4 & X86_CR4_OSXSAVE)
5582 update_cpuid(vcpu);
7c93be44 5583 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ff03a073 5584 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
7c93be44
MT		 5585 mmu_reset_needed = 1;
5586 }
b6c7a5dc
HB		 5587
5588 if (mmu_reset_needed)
5589 kvm_mmu_reset_context(vcpu);
5590
923c61bb
GN		 5591 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5592 pending_vec = find_first_bit(
5593 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5594 if (pending_vec < max_bits) {
66fd3f7f 5595 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5596 pr_debug("Set back pending irq %d\n", pending_vec);
5597 if (irqchip_in_kernel(vcpu->kvm))
5598 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5599 }
5600
3e6e0aab
GT		 5601 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5602 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5603 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5604 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5605 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5606 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5607
3e6e0aab
GT		 5608 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5609 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5610
5f0269f5
ME		 5611 update_cr8_intercept(vcpu);
5612
9c3e4aab 5613 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5614 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5615 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5616 !is_protmode(vcpu))
9c3e4aab
MT		 5617 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5618
3842d135
AK		 5619 kvm_make_request(KVM_REQ_EVENT, vcpu);
5620
b6c7a5dc
HB		 5621 return 0;
5622}
5623
d0bfb940
JK		 5624int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5625 struct kvm_guest_debug *dbg)
b6c7a5dc 5626{
355be0b9 5627 unsigned long rflags;
ae675ef0 5628 int i, r;
b6c7a5dc 5629
4f926bf2
JK		 5630 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5631 r = -EBUSY;
5632 if (vcpu->arch.exception.pending)
2122ff5e 5633 goto out;
4f926bf2
JK		 5634 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5635 kvm_queue_exception(vcpu, DB_VECTOR);
5636 else
5637 kvm_queue_exception(vcpu, BP_VECTOR);
5638 }
5639
91586a3b
JK		 5640 /*
5641 * Read rflags as long as potentially injected trace flags are still
5642 * filtered out.
5643 */
5644 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5645
5646 vcpu->guest_debug = dbg->control;
5647 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5648 vcpu->guest_debug = 0;
5649
5650 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5651 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5652 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5653 vcpu->arch.switch_db_regs =
5654 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5655 } else {
5656 for (i = 0; i < KVM_NR_DB_REGS; i++)
5657 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5658 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5659 }
5660
f92653ee
JK		 5661 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5662 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5663 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5664
91586a3b
JK		 5665 /*
5666 * Trigger an rflags update that will inject or remove the trace
5667 * flags.
5668 */
5669 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5670
355be0b9 5671 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5672
4f926bf2 5673 r = 0;
d0bfb940 5674
2122ff5e 5675out:
b6c7a5dc
HB		 5676
5677 return r;
5678}
5679
8b006791
ZX		 5680/*
5681 * Translate a guest virtual address to a guest physical address.
5682 */
5683int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5684 struct kvm_translation *tr)
5685{
5686 unsigned long vaddr = tr->linear_address;
5687 gpa_t gpa;
f656ce01 5688 int idx;
8b006791 5689
f656ce01 5690 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5691 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5692 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5693 tr->physical_address = gpa;
5694 tr->valid = gpa != UNMAPPED_GVA;
5695 tr->writeable = 1;
5696 tr->usermode = 0;
8b006791
ZX		 5697
5698 return 0;
5699}
5700
d0752060
HB		 5701int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5702{
98918833
SY		 5703 struct i387_fxsave_struct *fxsave =
5704 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5705
d0752060
HB		 5706 memcpy(fpu->fpr, fxsave->st_space, 128);
5707 fpu->fcw = fxsave->cwd;
5708 fpu->fsw = fxsave->swd;
5709 fpu->ftwx = fxsave->twd;
5710 fpu->last_opcode = fxsave->fop;
5711 fpu->last_ip = fxsave->rip;
5712 fpu->last_dp = fxsave->rdp;
5713 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5714
d0752060
HB		 5715 return 0;
5716}
5717
5718int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5719{
98918833
SY		 5720 struct i387_fxsave_struct *fxsave =
5721 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5722
d0752060
HB		 5723 memcpy(fxsave->st_space, fpu->fpr, 128);
5724 fxsave->cwd = fpu->fcw;
5725 fxsave->swd = fpu->fsw;
5726 fxsave->twd = fpu->ftwx;
5727 fxsave->fop = fpu->last_opcode;
5728 fxsave->rip = fpu->last_ip;
5729 fxsave->rdp = fpu->last_dp;
5730 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5731
d0752060
HB		 5732 return 0;
5733}
5734
10ab25cd 5735int fx_init(struct kvm_vcpu *vcpu)
d0752060 5736{
10ab25cd
JK		 5737 int err;
5738
5739 err = fpu_alloc(&vcpu->arch.guest_fpu);
5740 if (err)
5741 return err;
5742
98918833 5743 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5744
2acf923e
DC		 5745 /*
5746 * Ensure guest xcr0 is valid for loading
5747 */
5748 vcpu->arch.xcr0 = XSTATE_FP;
5749
ad312c7c 5750 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5751
5752 return 0;
d0752060
HB		 5753}
5754EXPORT_SYMBOL_GPL(fx_init);
5755
98918833
SY		 5756static void fx_free(struct kvm_vcpu *vcpu)
5757{
5758 fpu_free(&vcpu->arch.guest_fpu);
5759}
5760
d0752060
HB		 5761void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5762{
2608d7a1 5763 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5764 return;
5765
2acf923e
DC		 5766 /*
5767 * Restore all possible states in the guest,
5768 * and assume host would use all available bits.
5769 * Guest xcr0 would be loaded later.
5770 */
5771 kvm_put_guest_xcr0(vcpu);
d0752060 5772 vcpu->guest_fpu_loaded = 1;
7cf30855 5773 unlazy_fpu(current);
98918833 5774 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5775 trace_kvm_fpu(1);
d0752060 5776}
d0752060
HB		 5777
5778void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5779{
2acf923e
DC		 5780 kvm_put_guest_xcr0(vcpu);
5781
d0752060
HB		 5782 if (!vcpu->guest_fpu_loaded)
5783 return;
5784
5785 vcpu->guest_fpu_loaded = 0;
98918833 5786 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5787 ++vcpu->stat.fpu_reload;
a8eeb04a 5788 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5789 trace_kvm_fpu(0);
d0752060 5790}
e9b11c17
ZX		 5791
5792void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5793{
7f1ea208
JR		 5794 if (vcpu->arch.time_page) {
5795 kvm_release_page_dirty(vcpu->arch.time_page);
5796 vcpu->arch.time_page = NULL;
5797 }
5798
f5f48ee1 5799 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5800 fx_free(vcpu);
e9b11c17
ZX		 5801 kvm_x86_ops->vcpu_free(vcpu);
5802}
5803
5804struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5805 unsigned int id)
5806{
6755bae8
ZA		 5807 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5808 printk_once(KERN_WARNING
5809 "kvm: SMP vm created on host with unstable TSC; "
5810 "guest TSC will not be reliable\n");
26e5215f
AK		 5811 return kvm_x86_ops->vcpu_create(kvm, id);
5812}
e9b11c17 5813
26e5215f
AK		 5814int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5815{
5816 int r;
e9b11c17 5817
0bed3b56 5818 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5819 vcpu_load(vcpu);
5820 r = kvm_arch_vcpu_reset(vcpu);
5821 if (r == 0)
5822 r = kvm_mmu_setup(vcpu);
5823 vcpu_put(vcpu);
5824 if (r < 0)
5825 goto free_vcpu;
5826
26e5215f 5827 return 0;
e9b11c17
ZX		 5828free_vcpu:
5829 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5830 return r;
e9b11c17
ZX		 5831}
5832
d40ccc62 5833void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5834{
344d9588
GN		 5835 vcpu->arch.apf.msr_val = 0;
5836
e9b11c17
ZX		 5837 vcpu_load(vcpu);
5838 kvm_mmu_unload(vcpu);
5839 vcpu_put(vcpu);
5840
98918833 5841 fx_free(vcpu);
e9b11c17
ZX		 5842 kvm_x86_ops->vcpu_free(vcpu);
5843}
5844
5845int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5846{
448fa4a9
JK		 5847 vcpu->arch.nmi_pending = false;
5848 vcpu->arch.nmi_injected = false;
5849
42dbaa5a
JK		 5850 vcpu->arch.switch_db_regs = 0;
5851 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5852 vcpu->arch.dr6 = DR6_FIXED_1;
5853 vcpu->arch.dr7 = DR7_FIXED_1;
5854
3842d135 5855 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 5856 vcpu->arch.apf.msr_val = 0;
3842d135 5857
af585b92
GN		 5858 kvm_clear_async_pf_completion_queue(vcpu);
5859 kvm_async_pf_hash_reset(vcpu);
5860 vcpu->arch.apf.halted = false;
5861
e9b11c17
ZX		 5862 return kvm_x86_ops->vcpu_reset(vcpu);
5863}
5864
10474ae8 5865int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5866{
ca84d1a2
ZA		 5867 struct kvm *kvm;
5868 struct kvm_vcpu *vcpu;
5869 int i;
18863bdd
AK		 5870
5871 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5872 list_for_each_entry(kvm, &vm_list, vm_list)
5873 kvm_for_each_vcpu(i, vcpu, kvm)
5874 if (vcpu->cpu == smp_processor_id())
c285545f 5875 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 5876 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5877}
5878
5879void kvm_arch_hardware_disable(void *garbage)
5880{
5881 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5882 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5883}
5884
5885int kvm_arch_hardware_setup(void)
5886{
5887 return kvm_x86_ops->hardware_setup();
5888}
5889
5890void kvm_arch_hardware_unsetup(void)
5891{
5892 kvm_x86_ops->hardware_unsetup();
5893}
5894
5895void kvm_arch_check_processor_compat(void *rtn)
5896{
5897 kvm_x86_ops->check_processor_compatibility(rtn);
5898}
5899
5900int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5901{
5902 struct page *page;
5903 struct kvm *kvm;
5904 int r;
5905
5906 BUG_ON(vcpu->kvm == NULL);
5907 kvm = vcpu->kvm;
5908
9aabc88f 5909 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5910 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5911 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5912 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5913 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5914 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5915 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5916 else
a4535290 5917 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5918
5919 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5920 if (!page) {
5921 r = -ENOMEM;
5922 goto fail;
5923 }
ad312c7c 5924 vcpu->arch.pio_data = page_address(page);
e9b11c17 5925
c285545f
ZA		 5926 if (!kvm->arch.virtual_tsc_khz)
5927 kvm_arch_set_tsc_khz(kvm, max_tsc_khz);
5928
e9b11c17
ZX		 5929 r = kvm_mmu_create(vcpu);
5930 if (r < 0)
5931 goto fail_free_pio_data;
5932
5933 if (irqchip_in_kernel(kvm)) {
5934 r = kvm_create_lapic(vcpu);
5935 if (r < 0)
5936 goto fail_mmu_destroy;
5937 }
5938
890ca9ae
HY		 5939 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5940 GFP_KERNEL);
5941 if (!vcpu->arch.mce_banks) {
5942 r = -ENOMEM;
443c39bc 5943 goto fail_free_lapic;
890ca9ae
HY		 5944 }
5945 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5946
f5f48ee1
SY		 5947 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5948 goto fail_free_mce_banks;
5949
af585b92
GN		 5950 kvm_async_pf_hash_reset(vcpu);
5951
e9b11c17 5952 return 0;
f5f48ee1
SY		 5953fail_free_mce_banks:
5954 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5955fail_free_lapic:
5956 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5957fail_mmu_destroy:
5958 kvm_mmu_destroy(vcpu);
5959fail_free_pio_data:
ad312c7c 5960 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5961fail:
5962 return r;
5963}
5964
5965void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5966{
f656ce01
MT		 5967 int idx;
5968
36cb93fd 5969 kfree(vcpu->arch.mce_banks);
e9b11c17 5970 kvm_free_lapic(vcpu);
f656ce01 5971 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5972 kvm_mmu_destroy(vcpu);
f656ce01 5973 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5974 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5975}
d19a9cd2 5976
d89f5eff 5977int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 5978{
f05e70ac 5979 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5980 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5981
5550af4d
SY		 5982 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5983 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5984
99e3e30a 5985 spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 5986
d89f5eff 5987 return 0;
d19a9cd2
ZX		 5988}
5989
5990static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5991{
5992 vcpu_load(vcpu);
5993 kvm_mmu_unload(vcpu);
5994 vcpu_put(vcpu);
5995}
5996
5997static void kvm_free_vcpus(struct kvm *kvm)
5998{
5999 unsigned int i;
988a2cae 6000 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6001
6002 /*
6003 * Unpin any mmu pages first.
6004 */
af585b92
GN		 6005 kvm_for_each_vcpu(i, vcpu, kvm) {
6006 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6007 kvm_unload_vcpu_mmu(vcpu);
af585b92 6008 }
988a2cae
GN		 6009 kvm_for_each_vcpu(i, vcpu, kvm)
6010 kvm_arch_vcpu_free(vcpu);
6011
6012 mutex_lock(&kvm->lock);
6013 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6014 kvm->vcpus[i] = NULL;
d19a9cd2 6015
988a2cae
GN		 6016 atomic_set(&kvm->online_vcpus, 0);
6017 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6018}
6019
ad8ba2cd
SY		 6020void kvm_arch_sync_events(struct kvm *kvm)
6021{
ba4cef31 6022 kvm_free_all_assigned_devices(kvm);
aea924f6 6023 kvm_free_pit(kvm);
ad8ba2cd
SY		 6024}
6025
d19a9cd2
ZX		 6026void kvm_arch_destroy_vm(struct kvm *kvm)
6027{
6eb55818 6028 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6029 kfree(kvm->arch.vpic);
6030 kfree(kvm->arch.vioapic);
d19a9cd2 6031 kvm_free_vcpus(kvm);
3d45830c
AK		 6032 if (kvm->arch.apic_access_page)
6033 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6034 if (kvm->arch.ept_identity_pagetable)
6035 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6036}
0de10343 6037
f7784b8e
MT		 6038int kvm_arch_prepare_memory_region(struct kvm *kvm,
6039 struct kvm_memory_slot *memslot,
0de10343 6040 struct kvm_memory_slot old,
f7784b8e 6041 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6042 int user_alloc)
6043{
f7784b8e 6044 int npages = memslot->npages;
7ac77099
AK		 6045 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6046
6047 /* Prevent internal slot pages from being moved by fork()/COW. */
6048 if (memslot->id >= KVM_MEMORY_SLOTS)
6049 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6050
6051 /*To keep backward compatibility with older userspace,
6052 *x86 needs to hanlde !user_alloc case.
6053 */
6054 if (!user_alloc) {
6055 if (npages && !old.rmap) {
604b38ac
AA		 6056 unsigned long userspace_addr;
6057
72dc67a6 6058 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6059 userspace_addr = do_mmap(NULL, 0,
6060 npages * PAGE_SIZE,
6061 PROT_READ | PROT_WRITE,
7ac77099 6062 map_flags,
604b38ac 6063 0);
72dc67a6 6064 up_write(&current->mm->mmap_sem);
0de10343 6065
604b38ac
AA		 6066 if (IS_ERR((void *)userspace_addr))
6067 return PTR_ERR((void *)userspace_addr);
6068
604b38ac 6069 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6070 }
6071 }
6072
f7784b8e
MT		 6073
6074 return 0;
6075}
6076
6077void kvm_arch_commit_memory_region(struct kvm *kvm,
6078 struct kvm_userspace_memory_region *mem,
6079 struct kvm_memory_slot old,
6080 int user_alloc)
6081{
6082
6083 int npages = mem->memory_size >> PAGE_SHIFT;
6084
6085 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6086 int ret;
6087
6088 down_write(&current->mm->mmap_sem);
6089 ret = do_munmap(current->mm, old.userspace_addr,
6090 old.npages * PAGE_SIZE);
6091 up_write(&current->mm->mmap_sem);
6092 if (ret < 0)
6093 printk(KERN_WARNING
6094 "kvm_vm_ioctl_set_memory_region: "
6095 "failed to munmap memory\n");
6096 }
6097
7c8a83b7 6098 spin_lock(&kvm->mmu_lock);
f05e70ac 6099 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 6100 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6101 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6102 }
6103
6104 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6105 spin_unlock(&kvm->mmu_lock);
0de10343 6106}
1d737c8a 6107
34d4cb8f
MT		 6108void kvm_arch_flush_shadow(struct kvm *kvm)
6109{
6110 kvm_mmu_zap_all(kvm);
8986ecc0 6111 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6112}
6113
1d737c8a
ZX		 6114int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6115{
af585b92
GN		 6116 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6117 !vcpu->arch.apf.halted)
6118 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6119 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6120 || vcpu->arch.nmi_pending ||
6121 (kvm_arch_interrupt_allowed(vcpu) &&
6122 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6123}
5736199a 6124
5736199a
ZX		 6125void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6126{
32f88400
MT		 6127 int me;
6128 int cpu = vcpu->cpu;
5736199a
ZX		 6129
6130 if (waitqueue_active(&vcpu->wq)) {
6131 wake_up_interruptible(&vcpu->wq);
6132 ++vcpu->stat.halt_wakeup;
6133 }
32f88400
MT		 6134
6135 me = get_cpu();
6136 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 6137 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 6138 smp_send_reschedule(cpu);
e9571ed5 6139 put_cpu();
5736199a 6140}
78646121
GN		 6141
6142int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6143{
6144 return kvm_x86_ops->interrupt_allowed(vcpu);
6145}
229456fc 6146
f92653ee
JK		 6147bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6148{
6149 unsigned long current_rip = kvm_rip_read(vcpu) +
6150 get_segment_base(vcpu, VCPU_SREG_CS);
6151
6152 return current_rip == linear_rip;
6153}
6154EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6155
94fe45da
JK		 6156unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6157{
6158 unsigned long rflags;
6159
6160 rflags = kvm_x86_ops->get_rflags(vcpu);
6161 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6162 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6163 return rflags;
6164}
6165EXPORT_SYMBOL_GPL(kvm_get_rflags);
6166
6167void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6168{
6169 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6170 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6171 rflags |= X86_EFLAGS_TF;
94fe45da 6172 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6173 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6174}
6175EXPORT_SYMBOL_GPL(kvm_set_rflags);
6176
56028d08
GN		 6177void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6178{
6179 int r;
6180
c4806acd
XG		 6181 if (!vcpu->arch.mmu.direct_map || !work->arch.direct_map ||
6182 is_error_page(work->page))
56028d08
GN		 6183 return;
6184
6185 r = kvm_mmu_reload(vcpu);
6186 if (unlikely(r))
6187 return;
6188
6189 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6190}
6191
af585b92
GN		 6192static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6193{
6194 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6195}
6196
6197static inline u32 kvm_async_pf_next_probe(u32 key)
6198{
6199 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6200}
6201
6202static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6203{
6204 u32 key = kvm_async_pf_hash_fn(gfn);
6205
6206 while (vcpu->arch.apf.gfns[key] != ~0)
6207 key = kvm_async_pf_next_probe(key);
6208
6209 vcpu->arch.apf.gfns[key] = gfn;
6210}
6211
6212static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6213{
6214 int i;
6215 u32 key = kvm_async_pf_hash_fn(gfn);
6216
6217 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6218 (vcpu->arch.apf.gfns[key] != gfn &&
6219 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6220 key = kvm_async_pf_next_probe(key);
6221
6222 return key;
6223}
6224
6225bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6226{
6227 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6228}
6229
6230static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6231{
6232 u32 i, j, k;
6233
6234 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6235 while (true) {
6236 vcpu->arch.apf.gfns[i] = ~0;
6237 do {
6238 j = kvm_async_pf_next_probe(j);
6239 if (vcpu->arch.apf.gfns[j] == ~0)
6240 return;
6241 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6242 /*
6243 * k lies cyclically in ]i,j]
6244 * | i.k.j |
6245 * |....j i.k.| or |.k..j i...|
6246 */
6247 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6248 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6249 i = j;
6250 }
6251}
6252
7c90705b
GN		 6253static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6254{
6255
6256 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6257 sizeof(val));
6258}
6259
af585b92
GN		 6260void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6261 struct kvm_async_pf *work)
6262{
7c90705b 6263 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6264 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6265
6266 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6267 (vcpu->arch.apf.send_user_only &&
6268 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6269 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6270 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6271 vcpu->arch.fault.error_code = 0;
6272 vcpu->arch.fault.address = work->arch.token;
6273 kvm_inject_page_fault(vcpu);
6274 }
af585b92
GN		 6275}
6276
6277void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6278 struct kvm_async_pf *work)
6279{
7c90705b
GN		 6280 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6281 if (is_error_page(work->page))
6282 work->arch.token = ~0; /* broadcast wakeup */
6283 else
6284 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6285
6286 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6287 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6288 vcpu->arch.fault.error_code = 0;
6289 vcpu->arch.fault.address = work->arch.token;
6290 kvm_inject_page_fault(vcpu);
6291 }
e6d53e3b 6292 vcpu->arch.apf.halted = false;
7c90705b
GN		 6293}
6294
6295bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6296{
6297 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6298 return true;
6299 else
6300 return !kvm_event_needs_reinjection(vcpu) &&
6301 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6302}
6303
229456fc
MT		 6304EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6305EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6306EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6307EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6308EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6309EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6310EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6311EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6312EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6313EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6314EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6315EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)