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KVM: cpu_relax() during spin waiting for reboot
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
221d059d 9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
1d5f066e 58#include <asm/pvclock.h>
217fc9cf 59#include <asm/div64.h>
043405e1 60
313a3dc7 61#define MAX_IO_MSRS 256
a03490ed
CO		 62#define CR0_RESERVED_BITS \
63 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
64 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
65 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
66#define CR4_RESERVED_BITS \
67 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
68 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
69 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 70 | X86_CR4_OSXSAVE \
a03490ed
CO		 71 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
72
73#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 74
75#define KVM_MAX_MCE_BANKS 32
76#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
84#else
85static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
86#endif
313a3dc7 87
ba1389b7
AK		 88#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
89#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 90
cb142eb7 91static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 92static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
93 struct kvm_cpuid_entry2 __user *entries);
94
97896d04 95struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 96EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 97
ed85c068
AP		 98int ignore_msrs = 0;
99module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
100
18863bdd
AK		 101#define KVM_NR_SHARED_MSRS 16
102
103struct kvm_shared_msrs_global {
104 int nr;
2bf78fa7 105 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 106};
107
108struct kvm_shared_msrs {
109 struct user_return_notifier urn;
110 bool registered;
2bf78fa7
SY		 111 struct kvm_shared_msr_values {
112 u64 host;
113 u64 curr;
114 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 115};
116
117static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
118static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
119
417bc304 120struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 121 { "pf_fixed", VCPU_STAT(pf_fixed) },
122 { "pf_guest", VCPU_STAT(pf_guest) },
123 { "tlb_flush", VCPU_STAT(tlb_flush) },
124 { "invlpg", VCPU_STAT(invlpg) },
125 { "exits", VCPU_STAT(exits) },
126 { "io_exits", VCPU_STAT(io_exits) },
127 { "mmio_exits", VCPU_STAT(mmio_exits) },
128 { "signal_exits", VCPU_STAT(signal_exits) },
129 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 130 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 131 { "halt_exits", VCPU_STAT(halt_exits) },
132 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 133 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 134 { "request_irq", VCPU_STAT(request_irq_exits) },
135 { "irq_exits", VCPU_STAT(irq_exits) },
136 { "host_state_reload", VCPU_STAT(host_state_reload) },
137 { "efer_reload", VCPU_STAT(efer_reload) },
138 { "fpu_reload", VCPU_STAT(fpu_reload) },
139 { "insn_emulation", VCPU_STAT(insn_emulation) },
140 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 141 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 142 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 143 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
144 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
145 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
146 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
147 { "mmu_flooded", VM_STAT(mmu_flooded) },
148 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 149 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 150 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 151 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 152 { "largepages", VM_STAT(lpages) },
417bc304
HB		 153 { NULL }
154};
155
2acf923e
DC		 156u64 __read_mostly host_xcr0;
157
158static inline u32 bit(int bitno)
159{
160 return 1 << (bitno & 31);
161}
162
18863bdd
AK		 163static void kvm_on_user_return(struct user_return_notifier *urn)
164{
165 unsigned slot;
18863bdd
AK		 166 struct kvm_shared_msrs *locals
167 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 168 struct kvm_shared_msr_values *values;
18863bdd
AK		 169
170 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 171 values = &locals->values[slot];
172 if (values->host != values->curr) {
173 wrmsrl(shared_msrs_global.msrs[slot], values->host);
174 values->curr = values->host;
18863bdd
AK		 175 }
176 }
177 locals->registered = false;
178 user_return_notifier_unregister(urn);
179}
180
2bf78fa7 181static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 182{
2bf78fa7 183 struct kvm_shared_msrs *smsr;
18863bdd
AK		 184 u64 value;
185
2bf78fa7
SY		 186 smsr = &__get_cpu_var(shared_msrs);
187 /* only read, and nobody should modify it at this time,
188 * so don't need lock */
189 if (slot >= shared_msrs_global.nr) {
190 printk(KERN_ERR "kvm: invalid MSR slot!");
191 return;
192 }
193 rdmsrl_safe(msr, &value);
194 smsr->values[slot].host = value;
195 smsr->values[slot].curr = value;
196}
197
198void kvm_define_shared_msr(unsigned slot, u32 msr)
199{
18863bdd
AK		 200 if (slot >= shared_msrs_global.nr)
201 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 202 shared_msrs_global.msrs[slot] = msr;
203 /* we need ensured the shared_msr_global have been updated */
204 smp_wmb();
18863bdd
AK		 205}
206EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
207
208static void kvm_shared_msr_cpu_online(void)
209{
210 unsigned i;
18863bdd
AK		 211
212 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 213 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 214}
215
d5696725 216void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 217{
218 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
219
2bf78fa7 220 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 221 return;
2bf78fa7
SY		 222 smsr->values[slot].curr = value;
223 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 224 if (!smsr->registered) {
225 smsr->urn.on_user_return = kvm_on_user_return;
226 user_return_notifier_register(&smsr->urn);
227 smsr->registered = true;
228 }
229}
230EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
231
3548bab5
AK		 232static void drop_user_return_notifiers(void *ignore)
233{
234 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
235
236 if (smsr->registered)
237 kvm_on_user_return(&smsr->urn);
238}
239
6866b83e
CO		 240u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
241{
242 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e 244 else
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e
CO		 246}
247EXPORT_SYMBOL_GPL(kvm_get_apic_base);
248
249void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
250{
251 /* TODO: reserve bits check */
252 if (irqchip_in_kernel(vcpu->kvm))
253 kvm_lapic_set_base(vcpu, data);
254 else
ad312c7c 255 vcpu->arch.apic_base = data;
6866b83e
CO		 256}
257EXPORT_SYMBOL_GPL(kvm_set_apic_base);
258
3fd28fce
ED		 259#define EXCPT_BENIGN 0
260#define EXCPT_CONTRIBUTORY 1
261#define EXCPT_PF 2
262
263static int exception_class(int vector)
264{
265 switch (vector) {
266 case PF_VECTOR:
267 return EXCPT_PF;
268 case DE_VECTOR:
269 case TS_VECTOR:
270 case NP_VECTOR:
271 case SS_VECTOR:
272 case GP_VECTOR:
273 return EXCPT_CONTRIBUTORY;
274 default:
275 break;
276 }
277 return EXCPT_BENIGN;
278}
279
280static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 281 unsigned nr, bool has_error, u32 error_code,
282 bool reinject)
3fd28fce
ED		 283{
284 u32 prev_nr;
285 int class1, class2;
286
3842d135
AK		 287 kvm_make_request(KVM_REQ_EVENT, vcpu);
288
3fd28fce
ED		 289 if (!vcpu->arch.exception.pending) {
290 queue:
291 vcpu->arch.exception.pending = true;
292 vcpu->arch.exception.has_error_code = has_error;
293 vcpu->arch.exception.nr = nr;
294 vcpu->arch.exception.error_code = error_code;
3f0fd292 295 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 296 return;
297 }
298
299 /* to check exception */
300 prev_nr = vcpu->arch.exception.nr;
301 if (prev_nr == DF_VECTOR) {
302 /* triple fault -> shutdown */
a8eeb04a 303 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 304 return;
305 }
306 class1 = exception_class(prev_nr);
307 class2 = exception_class(nr);
308 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
309 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
310 /* generate double fault per SDM Table 5-5 */
311 vcpu->arch.exception.pending = true;
312 vcpu->arch.exception.has_error_code = true;
313 vcpu->arch.exception.nr = DF_VECTOR;
314 vcpu->arch.exception.error_code = 0;
315 } else
316 /* replace previous exception with a new one in a hope
317 that instruction re-execution will regenerate lost
318 exception */
319 goto queue;
320}
321
298101da
AK		 322void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
323{
ce7ddec4 324 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 325}
326EXPORT_SYMBOL_GPL(kvm_queue_exception);
327
ce7ddec4
JR		 328void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
329{
330 kvm_multiple_exception(vcpu, nr, false, 0, true);
331}
332EXPORT_SYMBOL_GPL(kvm_requeue_exception);
333
8df25a32 334void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
c3c91fee 335{
8df25a32
JR		 336 unsigned error_code = vcpu->arch.fault.error_code;
337
c3c91fee 338 ++vcpu->stat.pf_guest;
8df25a32 339 vcpu->arch.cr2 = vcpu->arch.fault.address;
c3c91fee
AK		 340 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
341}
342
d4f8cf66
JR		 343void kvm_propagate_fault(struct kvm_vcpu *vcpu)
344{
0959ffac 345 if (mmu_is_nested(vcpu) && !vcpu->arch.fault.nested)
d4f8cf66
JR		 346 vcpu->arch.nested_mmu.inject_page_fault(vcpu);
347 else
348 vcpu->arch.mmu.inject_page_fault(vcpu);
0959ffac
JR		 349
350 vcpu->arch.fault.nested = false;
d4f8cf66
JR		 351}
352
3419ffc8
SY		 353void kvm_inject_nmi(struct kvm_vcpu *vcpu)
354{
3842d135 355 kvm_make_request(KVM_REQ_EVENT, vcpu);
3419ffc8
SY		 356 vcpu->arch.nmi_pending = 1;
357}
358EXPORT_SYMBOL_GPL(kvm_inject_nmi);
359
298101da
AK		 360void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
361{
ce7ddec4 362 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 363}
364EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
365
ce7ddec4
JR		 366void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
367{
368 kvm_multiple_exception(vcpu, nr, true, error_code, true);
369}
370EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
371
0a79b009
AK		 372/*
373 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
374 * a #GP and return false.
375 */
376bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 377{
0a79b009
AK		 378 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
379 return true;
380 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
381 return false;
298101da 382}
0a79b009 383EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 384
ec92fe44
JR		 385/*
386 * This function will be used to read from the physical memory of the currently
387 * running guest. The difference to kvm_read_guest_page is that this function
388 * can read from guest physical or from the guest's guest physical memory.
389 */
390int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
391 gfn_t ngfn, void *data, int offset, int len,
392 u32 access)
393{
394 gfn_t real_gfn;
395 gpa_t ngpa;
396
397 ngpa = gfn_to_gpa(ngfn);
398 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
399 if (real_gfn == UNMAPPED_GVA)
400 return -EFAULT;
401
402 real_gfn = gpa_to_gfn(real_gfn);
403
404 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
405}
406EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
407
3d06b8bf
JR		 408int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
409 void *data, int offset, int len, u32 access)
410{
411 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
412 data, offset, len, access);
413}
414
a03490ed
CO		 415/*
416 * Load the pae pdptrs. Return true is they are all valid.
417 */
ff03a073 418int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 419{
420 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
421 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
422 int i;
423 int ret;
ff03a073 424 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 425
ff03a073
JR		 426 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
427 offset * sizeof(u64), sizeof(pdpte),
428 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 429 if (ret < 0) {
430 ret = 0;
431 goto out;
432 }
433 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 434 if (is_present_gpte(pdpte[i]) &&
20c466b5 435 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 436 ret = 0;
437 goto out;
438 }
439 }
440 ret = 1;
441
ff03a073 442 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 443 __set_bit(VCPU_EXREG_PDPTR,
444 (unsigned long *)&vcpu->arch.regs_avail);
445 __set_bit(VCPU_EXREG_PDPTR,
446 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 447out:
a03490ed
CO		 448
449 return ret;
450}
cc4b6871 451EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 452
d835dfec
AK		 453static bool pdptrs_changed(struct kvm_vcpu *vcpu)
454{
ff03a073 455 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 456 bool changed = true;
3d06b8bf
JR		 457 int offset;
458 gfn_t gfn;
d835dfec
AK		 459 int r;
460
461 if (is_long_mode(vcpu) || !is_pae(vcpu))
462 return false;
463
6de4f3ad
AK		 464 if (!test_bit(VCPU_EXREG_PDPTR,
465 (unsigned long *)&vcpu->arch.regs_avail))
466 return true;
467
3d06b8bf
JR		 468 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
469 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
470 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
471 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 472 if (r < 0)
473 goto out;
ff03a073 474 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 475out:
d835dfec
AK		 476
477 return changed;
478}
479
49a9b07e 480int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 481{
aad82703
SY		 482 unsigned long old_cr0 = kvm_read_cr0(vcpu);
483 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
484 X86_CR0_CD | X86_CR0_NW;
485
f9a48e6a
AK		 486 cr0 |= X86_CR0_ET;
487
ab344828 488#ifdef CONFIG_X86_64
0f12244f
GN		 489 if (cr0 & 0xffffffff00000000UL)
490 return 1;
ab344828
GN		 491#endif
492
493 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 494
0f12244f
GN		 495 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
496 return 1;
a03490ed 497
0f12244f
GN		 498 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
499 return 1;
a03490ed
CO		 500
501 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
502#ifdef CONFIG_X86_64
f6801dff 503 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 504 int cs_db, cs_l;
505
0f12244f
GN		 506 if (!is_pae(vcpu))
507 return 1;
a03490ed 508 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 509 if (cs_l)
510 return 1;
a03490ed
CO		 511 } else
512#endif
ff03a073
JR		 513 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
514 vcpu->arch.cr3))
0f12244f 515 return 1;
a03490ed
CO		 516 }
517
518 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 519
aad82703
SY		 520 if ((cr0 ^ old_cr0) & update_bits)
521 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 522 return 0;
523}
2d3ad1f4 524EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 525
2d3ad1f4 526void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 527{
49a9b07e 528 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 529}
2d3ad1f4 530EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 531
2acf923e
DC		 532int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
533{
534 u64 xcr0;
535
536 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
537 if (index != XCR_XFEATURE_ENABLED_MASK)
538 return 1;
539 xcr0 = xcr;
540 if (kvm_x86_ops->get_cpl(vcpu) != 0)
541 return 1;
542 if (!(xcr0 & XSTATE_FP))
543 return 1;
544 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
545 return 1;
546 if (xcr0 & ~host_xcr0)
547 return 1;
548 vcpu->arch.xcr0 = xcr0;
549 vcpu->guest_xcr0_loaded = 0;
550 return 0;
551}
552
553int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
554{
555 if (__kvm_set_xcr(vcpu, index, xcr)) {
556 kvm_inject_gp(vcpu, 0);
557 return 1;
558 }
559 return 0;
560}
561EXPORT_SYMBOL_GPL(kvm_set_xcr);
562
563static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
564{
565 struct kvm_cpuid_entry2 *best;
566
567 best = kvm_find_cpuid_entry(vcpu, 1, 0);
568 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
569}
570
571static void update_cpuid(struct kvm_vcpu *vcpu)
572{
573 struct kvm_cpuid_entry2 *best;
574
575 best = kvm_find_cpuid_entry(vcpu, 1, 0);
576 if (!best)
577 return;
578
579 /* Update OSXSAVE bit */
580 if (cpu_has_xsave && best->function == 0x1) {
581 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
582 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
583 best->ecx |= bit(X86_FEATURE_OSXSAVE);
584 }
585}
586
a83b29c6 587int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 588{
fc78f519 589 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 590 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
591
0f12244f
GN		 592 if (cr4 & CR4_RESERVED_BITS)
593 return 1;
a03490ed 594
2acf923e
DC		 595 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
596 return 1;
597
a03490ed 598 if (is_long_mode(vcpu)) {
0f12244f
GN		 599 if (!(cr4 & X86_CR4_PAE))
600 return 1;
a2edf57f
AK		 601 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
602 && ((cr4 ^ old_cr4) & pdptr_bits)
ff03a073 603 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
0f12244f
GN		 604 return 1;
605
606 if (cr4 & X86_CR4_VMXE)
607 return 1;
a03490ed 608
a03490ed 609 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 610
aad82703
SY		 611 if ((cr4 ^ old_cr4) & pdptr_bits)
612 kvm_mmu_reset_context(vcpu);
0f12244f 613
2acf923e
DC		 614 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
615 update_cpuid(vcpu);
616
0f12244f
GN		 617 return 0;
618}
2d3ad1f4 619EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 620
2390218b 621int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 622{
ad312c7c 623 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 624 kvm_mmu_sync_roots(vcpu);
d835dfec 625 kvm_mmu_flush_tlb(vcpu);
0f12244f 626 return 0;
d835dfec
AK		 627 }
628
a03490ed 629 if (is_long_mode(vcpu)) {
0f12244f
GN		 630 if (cr3 & CR3_L_MODE_RESERVED_BITS)
631 return 1;
a03490ed
CO		 632 } else {
633 if (is_pae(vcpu)) {
0f12244f
GN		 634 if (cr3 & CR3_PAE_RESERVED_BITS)
635 return 1;
ff03a073
JR		 636 if (is_paging(vcpu) &&
637 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 638 return 1;
a03490ed
CO		 639 }
640 /*
641 * We don't check reserved bits in nonpae mode, because
642 * this isn't enforced, and VMware depends on this.
643 */
644 }
645
a03490ed
CO		 646 /*
647 * Does the new cr3 value map to physical memory? (Note, we
648 * catch an invalid cr3 even in real-mode, because it would
649 * cause trouble later on when we turn on paging anyway.)
650 *
651 * A real CPU would silently accept an invalid cr3 and would
652 * attempt to use it - with largely undefined (and often hard
653 * to debug) behavior on the guest side.
654 */
655 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 656 return 1;
657 vcpu->arch.cr3 = cr3;
658 vcpu->arch.mmu.new_cr3(vcpu);
659 return 0;
660}
2d3ad1f4 661EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 662
0f12244f 663int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 664{
0f12244f
GN		 665 if (cr8 & CR8_RESERVED_BITS)
666 return 1;
a03490ed
CO		 667 if (irqchip_in_kernel(vcpu->kvm))
668 kvm_lapic_set_tpr(vcpu, cr8);
669 else
ad312c7c 670 vcpu->arch.cr8 = cr8;
0f12244f
GN		 671 return 0;
672}
673
674void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
675{
676 if (__kvm_set_cr8(vcpu, cr8))
677 kvm_inject_gp(vcpu, 0);
a03490ed 678}
2d3ad1f4 679EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 680
2d3ad1f4 681unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 682{
683 if (irqchip_in_kernel(vcpu->kvm))
684 return kvm_lapic_get_cr8(vcpu);
685 else
ad312c7c 686 return vcpu->arch.cr8;
a03490ed 687}
2d3ad1f4 688EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 689
338dbc97 690static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 691{
692 switch (dr) {
693 case 0 ... 3:
694 vcpu->arch.db[dr] = val;
695 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
696 vcpu->arch.eff_db[dr] = val;
697 break;
698 case 4:
338dbc97
GN		 699 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
700 return 1; /* #UD */
020df079
GN		 701 /* fall through */
702 case 6:
338dbc97
GN		 703 if (val & 0xffffffff00000000ULL)
704 return -1; /* #GP */
020df079
GN		 705 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
706 break;
707 case 5:
338dbc97
GN		 708 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
709 return 1; /* #UD */
020df079
GN		 710 /* fall through */
711 default: /* 7 */
338dbc97
GN		 712 if (val & 0xffffffff00000000ULL)
713 return -1; /* #GP */
020df079
GN		 714 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
715 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
716 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
717 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
718 }
719 break;
720 }
721
722 return 0;
723}
338dbc97
GN		 724
725int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
726{
727 int res;
728
729 res = __kvm_set_dr(vcpu, dr, val);
730 if (res > 0)
731 kvm_queue_exception(vcpu, UD_VECTOR);
732 else if (res < 0)
733 kvm_inject_gp(vcpu, 0);
734
735 return res;
736}
020df079
GN		 737EXPORT_SYMBOL_GPL(kvm_set_dr);
738
338dbc97 739static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 740{
741 switch (dr) {
742 case 0 ... 3:
743 *val = vcpu->arch.db[dr];
744 break;
745 case 4:
338dbc97 746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 747 return 1;
020df079
GN		 748 /* fall through */
749 case 6:
750 *val = vcpu->arch.dr6;
751 break;
752 case 5:
338dbc97 753 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 754 return 1;
020df079
GN		 755 /* fall through */
756 default: /* 7 */
757 *val = vcpu->arch.dr7;
758 break;
759 }
760
761 return 0;
762}
338dbc97
GN		 763
764int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
765{
766 if (_kvm_get_dr(vcpu, dr, val)) {
767 kvm_queue_exception(vcpu, UD_VECTOR);
768 return 1;
769 }
770 return 0;
771}
020df079
GN		 772EXPORT_SYMBOL_GPL(kvm_get_dr);
773
043405e1
CO		 774/*
775 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
776 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
777 *
778 * This list is modified at module load time to reflect the
e3267cbb
GC		 779 * capabilities of the host cpu. This capabilities test skips MSRs that are
780 * kvm-specific. Those are put in the beginning of the list.
043405e1 781 */
e3267cbb 782
11c6bffa 783#define KVM_SAVE_MSRS_BEGIN 7
043405e1 784static u32 msrs_to_save[] = {
e3267cbb 785 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 786 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 787 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 788 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1 789 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 790 MSR_STAR,
043405e1
CO		 791#ifdef CONFIG_X86_64
792 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
793#endif
e90aa41e 794 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 795};
796
797static unsigned num_msrs_to_save;
798
799static u32 emulated_msrs[] = {
800 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 801 MSR_IA32_MCG_STATUS,
802 MSR_IA32_MCG_CTL,
043405e1
CO		 803};
804
b69e8cae 805static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 806{
aad82703
SY		 807 u64 old_efer = vcpu->arch.efer;
808
b69e8cae
RJ		 809 if (efer & efer_reserved_bits)
810 return 1;
15c4a640
CO		 811
812 if (is_paging(vcpu)
b69e8cae
RJ		 813 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
814 return 1;
15c4a640 815
1b2fd70c
AG		 816 if (efer & EFER_FFXSR) {
817 struct kvm_cpuid_entry2 *feat;
818
819 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 820 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
821 return 1;
1b2fd70c
AG		 822 }
823
d8017474
AG		 824 if (efer & EFER_SVME) {
825 struct kvm_cpuid_entry2 *feat;
826
827 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 828 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
829 return 1;
d8017474
AG		 830 }
831
15c4a640 832 efer &= ~EFER_LMA;
f6801dff 833 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 834
a3d204e2
SY		 835 kvm_x86_ops->set_efer(vcpu, efer);
836
9645bb56
AK		 837 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
838 kvm_mmu_reset_context(vcpu);
b69e8cae 839
aad82703
SY		 840 /* Update reserved bits */
841 if ((efer ^ old_efer) & EFER_NX)
842 kvm_mmu_reset_context(vcpu);
843
b69e8cae 844 return 0;
15c4a640
CO		 845}
846
f2b4b7dd
JR		 847void kvm_enable_efer_bits(u64 mask)
848{
849 efer_reserved_bits &= ~mask;
850}
851EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
852
853
15c4a640
CO		 854/*
855 * Writes msr value into into the appropriate "register".
856 * Returns 0 on success, non-0 otherwise.
857 * Assumes vcpu_load() was already called.
858 */
859int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
860{
861 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
862}
863
313a3dc7
CO		 864/*
865 * Adapt set_msr() to msr_io()'s calling convention
866 */
867static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
868{
869 return kvm_set_msr(vcpu, index, *data);
870}
871
18068523
GOC		 872static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
873{
9ed3c444
AK		 874 int version;
875 int r;
50d0a0f9 876 struct pvclock_wall_clock wc;
923de3cf 877 struct timespec boot;
18068523
GOC		 878
879 if (!wall_clock)
880 return;
881
9ed3c444
AK		 882 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
883 if (r)
884 return;
885
886 if (version & 1)
887 ++version; /* first time write, random junk */
888
889 ++version;
18068523 890
18068523
GOC		 891 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
892
50d0a0f9
GH		 893 /*
894 * The guest calculates current wall clock time by adding
895 * system time (updated by kvm_write_guest_time below) to the
896 * wall clock specified here. guest system time equals host
897 * system time for us, thus we must fill in host boot time here.
898 */
923de3cf 899 getboottime(&boot);
50d0a0f9
GH		 900
901 wc.sec = boot.tv_sec;
902 wc.nsec = boot.tv_nsec;
903 wc.version = version;
18068523
GOC		 904
905 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
906
907 version++;
908 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 909}
910
50d0a0f9
GH		 911static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
912{
913 uint32_t quotient, remainder;
914
915 /* Don't try to replace with do_div(), this one calculates
916 * "(dividend << 32) / divisor" */
917 __asm__ ( "divl %4"
918 : "=a" (quotient), "=d" (remainder)
919 : "0" (0), "1" (dividend), "r" (divisor) );
920 return quotient;
921}
922
923static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
924{
925 uint64_t nsecs = 1000000000LL;
926 int32_t shift = 0;
927 uint64_t tps64;
928 uint32_t tps32;
929
930 tps64 = tsc_khz * 1000LL;
931 while (tps64 > nsecs*2) {
932 tps64 >>= 1;
933 shift--;
934 }
935
936 tps32 = (uint32_t)tps64;
937 while (tps32 <= (uint32_t)nsecs) {
938 tps32 <<= 1;
939 shift++;
940 }
941
942 hv_clock->tsc_shift = shift;
943 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
944
945 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 946 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 947 hv_clock->tsc_to_system_mul);
948}
949
759379dd
ZA		 950static inline u64 get_kernel_ns(void)
951{
952 struct timespec ts;
953
954 WARN_ON(preemptible());
955 ktime_get_ts(&ts);
956 monotonic_to_bootbased(&ts);
957 return timespec_to_ns(&ts);
958}
959
c8076604
GH		 960static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
961
8cfdc000
ZA		 962static inline int kvm_tsc_changes_freq(void)
963{
964 int cpu = get_cpu();
965 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
966 cpufreq_quick_get(cpu) != 0;
967 put_cpu();
968 return ret;
969}
970
759379dd
ZA		 971static inline u64 nsec_to_cycles(u64 nsec)
972{
217fc9cf
AK		 973 u64 ret;
974
759379dd
ZA		 975 WARN_ON(preemptible());
976 if (kvm_tsc_changes_freq())
977 printk_once(KERN_WARNING
978 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 979 ret = nsec * __get_cpu_var(cpu_tsc_khz);
980 do_div(ret, USEC_PER_SEC);
981 return ret;
759379dd
ZA		 982}
983
99e3e30a
ZA		 984void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
985{
986 struct kvm *kvm = vcpu->kvm;
f38e098f 987 u64 offset, ns, elapsed;
99e3e30a 988 unsigned long flags;
46543ba4 989 s64 sdiff;
99e3e30a
ZA		 990
991 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
992 offset = data - native_read_tsc();
759379dd 993 ns = get_kernel_ns();
f38e098f 994 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 995 sdiff = data - kvm->arch.last_tsc_write;
996 if (sdiff < 0)
997 sdiff = -sdiff;
f38e098f
ZA		 998
999 /*
46543ba4 1000 * Special case: close write to TSC within 5 seconds of
f38e098f 1001 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 1002 * The 5 seconds is to accomodate host load / swapping as
1003 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1004 *
1005 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1006 * or make a best guest using elapsed value.
f38e098f 1007 */
46543ba4
ZA		 1008 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1009 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1010 if (!check_tsc_unstable()) {
1011 offset = kvm->arch.last_tsc_offset;
1012 pr_debug("kvm: matched tsc offset for %llu\n", data);
1013 } else {
759379dd
ZA		 1014 u64 delta = nsec_to_cycles(elapsed);
1015 offset += delta;
1016 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1017 }
1018 ns = kvm->arch.last_tsc_nsec;
1019 }
1020 kvm->arch.last_tsc_nsec = ns;
1021 kvm->arch.last_tsc_write = data;
1022 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1023 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1024 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1025
1026 /* Reset of TSC must disable overshoot protection below */
1027 vcpu->arch.hv_clock.tsc_timestamp = 0;
1028}
1029EXPORT_SYMBOL_GPL(kvm_write_tsc);
1030
8cfdc000 1031static int kvm_write_guest_time(struct kvm_vcpu *v)
18068523 1032{
18068523
GOC		 1033 unsigned long flags;
1034 struct kvm_vcpu_arch *vcpu = &v->arch;
1035 void *shared_kaddr;
463656c0 1036 unsigned long this_tsc_khz;
1d5f066e
ZA		 1037 s64 kernel_ns, max_kernel_ns;
1038 u64 tsc_timestamp;
18068523
GOC		 1039
1040 if ((!vcpu->time_page))
8cfdc000 1041 return 0;
50d0a0f9 1042
18068523
GOC		 1043 /* Keep irq disabled to prevent changes to the clock */
1044 local_irq_save(flags);
1d5f066e 1045 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1046 kernel_ns = get_kernel_ns();
8cfdc000 1047 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523
GOC		 1048 local_irq_restore(flags);
1049
8cfdc000
ZA		 1050 if (unlikely(this_tsc_khz == 0)) {
1051 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
1052 return 1;
1053 }
18068523 1054
1d5f066e
ZA		 1055 /*
1056 * Time as measured by the TSC may go backwards when resetting the base
1057 * tsc_timestamp. The reason for this is that the TSC resolution is
1058 * higher than the resolution of the other clock scales. Thus, many
1059 * possible measurments of the TSC correspond to one measurement of any
1060 * other clock, and so a spread of values is possible. This is not a
1061 * problem for the computation of the nanosecond clock; with TSC rates
1062 * around 1GHZ, there can only be a few cycles which correspond to one
1063 * nanosecond value, and any path through this code will inevitably
1064 * take longer than that. However, with the kernel_ns value itself,
1065 * the precision may be much lower, down to HZ granularity. If the
1066 * first sampling of TSC against kernel_ns ends in the low part of the
1067 * range, and the second in the high end of the range, we can get:
1068 *
1069 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1070 *
1071 * As the sampling errors potentially range in the thousands of cycles,
1072 * it is possible such a time value has already been observed by the
1073 * guest. To protect against this, we must compute the system time as
1074 * observed by the guest and ensure the new system time is greater.
1075 */
1076 max_kernel_ns = 0;
1077 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1078 max_kernel_ns = vcpu->last_guest_tsc -
1079 vcpu->hv_clock.tsc_timestamp;
1080 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1081 vcpu->hv_clock.tsc_to_system_mul,
1082 vcpu->hv_clock.tsc_shift);
1083 max_kernel_ns += vcpu->last_kernel_ns;
1084 }
1085
e48672fa 1086 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
8cfdc000 1087 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
e48672fa 1088 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1089 }
1090
1d5f066e
ZA		 1091 if (max_kernel_ns > kernel_ns)
1092 kernel_ns = max_kernel_ns;
1093
8cfdc000 1094 /* With all the info we got, fill in the values */
1d5f066e 1095 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1096 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1097 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1098 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1099 vcpu->hv_clock.flags = 0;
1100
18068523
GOC		 1101 /*
1102 * The interface expects us to write an even number signaling that the
1103 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1104 * state, we just increase by 2 at the end.
18068523 1105 */
50d0a0f9 1106 vcpu->hv_clock.version += 2;
18068523
GOC		 1107
1108 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1109
1110 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1111 sizeof(vcpu->hv_clock));
18068523
GOC		 1112
1113 kunmap_atomic(shared_kaddr, KM_USER0);
1114
1115 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1116 return 0;
18068523
GOC		 1117}
1118
c8076604
GH		 1119static int kvm_request_guest_time_update(struct kvm_vcpu *v)
1120{
1121 struct kvm_vcpu_arch *vcpu = &v->arch;
1122
1123 if (!vcpu->time_page)
1124 return 0;
a8eeb04a 1125 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
c8076604
GH		 1126 return 1;
1127}
1128
9ba075a6
AK		 1129static bool msr_mtrr_valid(unsigned msr)
1130{
1131 switch (msr) {
1132 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1133 case MSR_MTRRfix64K_00000:
1134 case MSR_MTRRfix16K_80000:
1135 case MSR_MTRRfix16K_A0000:
1136 case MSR_MTRRfix4K_C0000:
1137 case MSR_MTRRfix4K_C8000:
1138 case MSR_MTRRfix4K_D0000:
1139 case MSR_MTRRfix4K_D8000:
1140 case MSR_MTRRfix4K_E0000:
1141 case MSR_MTRRfix4K_E8000:
1142 case MSR_MTRRfix4K_F0000:
1143 case MSR_MTRRfix4K_F8000:
1144 case MSR_MTRRdefType:
1145 case MSR_IA32_CR_PAT:
1146 return true;
1147 case 0x2f8:
1148 return true;
1149 }
1150 return false;
1151}
1152
d6289b93
MT		 1153static bool valid_pat_type(unsigned t)
1154{
1155 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1156}
1157
1158static bool valid_mtrr_type(unsigned t)
1159{
1160 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1161}
1162
1163static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1164{
1165 int i;
1166
1167 if (!msr_mtrr_valid(msr))
1168 return false;
1169
1170 if (msr == MSR_IA32_CR_PAT) {
1171 for (i = 0; i < 8; i++)
1172 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1173 return false;
1174 return true;
1175 } else if (msr == MSR_MTRRdefType) {
1176 if (data & ~0xcff)
1177 return false;
1178 return valid_mtrr_type(data & 0xff);
1179 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1180 for (i = 0; i < 8 ; i++)
1181 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1182 return false;
1183 return true;
1184 }
1185
1186 /* variable MTRRs */
1187 return valid_mtrr_type(data & 0xff);
1188}
1189
9ba075a6
AK		 1190static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1191{
0bed3b56
SY		 1192 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1193
d6289b93 1194 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1195 return 1;
1196
0bed3b56
SY		 1197 if (msr == MSR_MTRRdefType) {
1198 vcpu->arch.mtrr_state.def_type = data;
1199 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1200 } else if (msr == MSR_MTRRfix64K_00000)
1201 p[0] = data;
1202 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1203 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1204 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1205 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1206 else if (msr == MSR_IA32_CR_PAT)
1207 vcpu->arch.pat = data;
1208 else { /* Variable MTRRs */
1209 int idx, is_mtrr_mask;
1210 u64 *pt;
1211
1212 idx = (msr - 0x200) / 2;
1213 is_mtrr_mask = msr - 0x200 - 2 * idx;
1214 if (!is_mtrr_mask)
1215 pt =
1216 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1217 else
1218 pt =
1219 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1220 *pt = data;
1221 }
1222
1223 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1224 return 0;
1225}
15c4a640 1226
890ca9ae 1227static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1228{
890ca9ae
HY		 1229 u64 mcg_cap = vcpu->arch.mcg_cap;
1230 unsigned bank_num = mcg_cap & 0xff;
1231
15c4a640 1232 switch (msr) {
15c4a640 1233 case MSR_IA32_MCG_STATUS:
890ca9ae 1234 vcpu->arch.mcg_status = data;
15c4a640 1235 break;
c7ac679c 1236 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1237 if (!(mcg_cap & MCG_CTL_P))
1238 return 1;
1239 if (data != 0 && data != ~(u64)0)
1240 return -1;
1241 vcpu->arch.mcg_ctl = data;
1242 break;
1243 default:
1244 if (msr >= MSR_IA32_MC0_CTL &&
1245 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1246 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1247 /* only 0 or all 1s can be written to IA32_MCi_CTL
1248 * some Linux kernels though clear bit 10 in bank 4 to
1249 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1250 * this to avoid an uncatched #GP in the guest
1251 */
890ca9ae 1252 if ((offset & 0x3) == 0 &&
114be429 1253 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1254 return -1;
1255 vcpu->arch.mce_banks[offset] = data;
1256 break;
1257 }
1258 return 1;
1259 }
1260 return 0;
1261}
1262
ffde22ac
ES		 1263static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1264{
1265 struct kvm *kvm = vcpu->kvm;
1266 int lm = is_long_mode(vcpu);
1267 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1268 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1269 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1270 : kvm->arch.xen_hvm_config.blob_size_32;
1271 u32 page_num = data & ~PAGE_MASK;
1272 u64 page_addr = data & PAGE_MASK;
1273 u8 *page;
1274 int r;
1275
1276 r = -E2BIG;
1277 if (page_num >= blob_size)
1278 goto out;
1279 r = -ENOMEM;
1280 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1281 if (!page)
1282 goto out;
1283 r = -EFAULT;
1284 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1285 goto out_free;
1286 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1287 goto out_free;
1288 r = 0;
1289out_free:
1290 kfree(page);
1291out:
1292 return r;
1293}
1294
55cd8e5a
GN		 1295static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1296{
1297 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1298}
1299
1300static bool kvm_hv_msr_partition_wide(u32 msr)
1301{
1302 bool r = false;
1303 switch (msr) {
1304 case HV_X64_MSR_GUEST_OS_ID:
1305 case HV_X64_MSR_HYPERCALL:
1306 r = true;
1307 break;
1308 }
1309
1310 return r;
1311}
1312
1313static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1314{
1315 struct kvm *kvm = vcpu->kvm;
1316
1317 switch (msr) {
1318 case HV_X64_MSR_GUEST_OS_ID:
1319 kvm->arch.hv_guest_os_id = data;
1320 /* setting guest os id to zero disables hypercall page */
1321 if (!kvm->arch.hv_guest_os_id)
1322 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1323 break;
1324 case HV_X64_MSR_HYPERCALL: {
1325 u64 gfn;
1326 unsigned long addr;
1327 u8 instructions[4];
1328
1329 /* if guest os id is not set hypercall should remain disabled */
1330 if (!kvm->arch.hv_guest_os_id)
1331 break;
1332 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1333 kvm->arch.hv_hypercall = data;
1334 break;
1335 }
1336 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1337 addr = gfn_to_hva(kvm, gfn);
1338 if (kvm_is_error_hva(addr))
1339 return 1;
1340 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1341 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1342 if (copy_to_user((void __user *)addr, instructions, 4))
1343 return 1;
1344 kvm->arch.hv_hypercall = data;
1345 break;
1346 }
1347 default:
1348 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1349 "data 0x%llx\n", msr, data);
1350 return 1;
1351 }
1352 return 0;
1353}
1354
1355static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1356{
10388a07
GN		 1357 switch (msr) {
1358 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1359 unsigned long addr;
55cd8e5a 1360
10388a07
GN		 1361 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1362 vcpu->arch.hv_vapic = data;
1363 break;
1364 }
1365 addr = gfn_to_hva(vcpu->kvm, data >>
1366 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1367 if (kvm_is_error_hva(addr))
1368 return 1;
1369 if (clear_user((void __user *)addr, PAGE_SIZE))
1370 return 1;
1371 vcpu->arch.hv_vapic = data;
1372 break;
1373 }
1374 case HV_X64_MSR_EOI:
1375 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1376 case HV_X64_MSR_ICR:
1377 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1378 case HV_X64_MSR_TPR:
1379 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1380 default:
1381 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1382 "data 0x%llx\n", msr, data);
1383 return 1;
1384 }
1385
1386 return 0;
55cd8e5a
GN		 1387}
1388
15c4a640
CO		 1389int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1390{
1391 switch (msr) {
15c4a640 1392 case MSR_EFER:
b69e8cae 1393 return set_efer(vcpu, data);
8f1589d9
AP		 1394 case MSR_K7_HWCR:
1395 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1396 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1397 if (data != 0) {
1398 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1399 data);
1400 return 1;
1401 }
15c4a640 1402 break;
f7c6d140
AP		 1403 case MSR_FAM10H_MMIO_CONF_BASE:
1404 if (data != 0) {
1405 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1406 "0x%llx\n", data);
1407 return 1;
1408 }
15c4a640 1409 break;
c323c0e5 1410 case MSR_AMD64_NB_CFG:
c7ac679c 1411 break;
b5e2fec0
AG		 1412 case MSR_IA32_DEBUGCTLMSR:
1413 if (!data) {
1414 /* We support the non-activated case already */
1415 break;
1416 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1417 /* Values other than LBR and BTF are vendor-specific,
1418 thus reserved and should throw a #GP */
1419 return 1;
1420 }
1421 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1422 __func__, data);
1423 break;
15c4a640
CO		 1424 case MSR_IA32_UCODE_REV:
1425 case MSR_IA32_UCODE_WRITE:
61a6bd67 1426 case MSR_VM_HSAVE_PA:
6098ca93 1427 case MSR_AMD64_PATCH_LOADER:
15c4a640 1428 break;
9ba075a6
AK		 1429 case 0x200 ... 0x2ff:
1430 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1431 case MSR_IA32_APICBASE:
1432 kvm_set_apic_base(vcpu, data);
1433 break;
0105d1a5
GN		 1434 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1435 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1436 case MSR_IA32_MISC_ENABLE:
ad312c7c 1437 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1438 break;
11c6bffa 1439 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1440 case MSR_KVM_WALL_CLOCK:
1441 vcpu->kvm->arch.wall_clock = data;
1442 kvm_write_wall_clock(vcpu->kvm, data);
1443 break;
11c6bffa 1444 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1445 case MSR_KVM_SYSTEM_TIME: {
1446 if (vcpu->arch.time_page) {
1447 kvm_release_page_dirty(vcpu->arch.time_page);
1448 vcpu->arch.time_page = NULL;
1449 }
1450
1451 vcpu->arch.time = data;
1452
1453 /* we verify if the enable bit is set... */
1454 if (!(data & 1))
1455 break;
1456
1457 /* ...but clean it before doing the actual write */
1458 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1459
18068523
GOC		 1460 vcpu->arch.time_page =
1461 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1462
1463 if (is_error_page(vcpu->arch.time_page)) {
1464 kvm_release_page_clean(vcpu->arch.time_page);
1465 vcpu->arch.time_page = NULL;
1466 }
1467
c8076604 1468 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1469 break;
1470 }
890ca9ae
HY		 1471 case MSR_IA32_MCG_CTL:
1472 case MSR_IA32_MCG_STATUS:
1473 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1474 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1475
1476 /* Performance counters are not protected by a CPUID bit,
1477 * so we should check all of them in the generic path for the sake of
1478 * cross vendor migration.
1479 * Writing a zero into the event select MSRs disables them,
1480 * which we perfectly emulate ;-). Any other value should be at least
1481 * reported, some guests depend on them.
1482 */
1483 case MSR_P6_EVNTSEL0:
1484 case MSR_P6_EVNTSEL1:
1485 case MSR_K7_EVNTSEL0:
1486 case MSR_K7_EVNTSEL1:
1487 case MSR_K7_EVNTSEL2:
1488 case MSR_K7_EVNTSEL3:
1489 if (data != 0)
1490 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1491 "0x%x data 0x%llx\n", msr, data);
1492 break;
1493 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1494 * so we ignore writes to make it happy.
1495 */
1496 case MSR_P6_PERFCTR0:
1497 case MSR_P6_PERFCTR1:
1498 case MSR_K7_PERFCTR0:
1499 case MSR_K7_PERFCTR1:
1500 case MSR_K7_PERFCTR2:
1501 case MSR_K7_PERFCTR3:
1502 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1503 "0x%x data 0x%llx\n", msr, data);
1504 break;
84e0cefa
JS		 1505 case MSR_K7_CLK_CTL:
1506 /*
1507 * Ignore all writes to this no longer documented MSR.
1508 * Writes are only relevant for old K7 processors,
1509 * all pre-dating SVM, but a recommended workaround from
1510 * AMD for these chips. It is possible to speicify the
1511 * affected processor models on the command line, hence
1512 * the need to ignore the workaround.
1513 */
1514 break;
55cd8e5a
GN		 1515 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1516 if (kvm_hv_msr_partition_wide(msr)) {
1517 int r;
1518 mutex_lock(&vcpu->kvm->lock);
1519 r = set_msr_hyperv_pw(vcpu, msr, data);
1520 mutex_unlock(&vcpu->kvm->lock);
1521 return r;
1522 } else
1523 return set_msr_hyperv(vcpu, msr, data);
1524 break;
15c4a640 1525 default:
ffde22ac
ES		 1526 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1527 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1528 if (!ignore_msrs) {
1529 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1530 msr, data);
1531 return 1;
1532 } else {
1533 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1534 msr, data);
1535 break;
1536 }
15c4a640
CO		 1537 }
1538 return 0;
1539}
1540EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1541
1542
1543/*
1544 * Reads an msr value (of 'msr_index') into 'pdata'.
1545 * Returns 0 on success, non-0 otherwise.
1546 * Assumes vcpu_load() was already called.
1547 */
1548int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1549{
1550 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1551}
1552
9ba075a6
AK		 1553static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1554{
0bed3b56
SY		 1555 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1556
9ba075a6
AK		 1557 if (!msr_mtrr_valid(msr))
1558 return 1;
1559
0bed3b56
SY		 1560 if (msr == MSR_MTRRdefType)
1561 *pdata = vcpu->arch.mtrr_state.def_type +
1562 (vcpu->arch.mtrr_state.enabled << 10);
1563 else if (msr == MSR_MTRRfix64K_00000)
1564 *pdata = p[0];
1565 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1566 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1567 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1568 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1569 else if (msr == MSR_IA32_CR_PAT)
1570 *pdata = vcpu->arch.pat;
1571 else { /* Variable MTRRs */
1572 int idx, is_mtrr_mask;
1573 u64 *pt;
1574
1575 idx = (msr - 0x200) / 2;
1576 is_mtrr_mask = msr - 0x200 - 2 * idx;
1577 if (!is_mtrr_mask)
1578 pt =
1579 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1580 else
1581 pt =
1582 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1583 *pdata = *pt;
1584 }
1585
9ba075a6
AK		 1586 return 0;
1587}
1588
890ca9ae 1589static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1590{
1591 u64 data;
890ca9ae
HY		 1592 u64 mcg_cap = vcpu->arch.mcg_cap;
1593 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1594
1595 switch (msr) {
15c4a640
CO		 1596 case MSR_IA32_P5_MC_ADDR:
1597 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1598 data = 0;
1599 break;
15c4a640 1600 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1601 data = vcpu->arch.mcg_cap;
1602 break;
c7ac679c 1603 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1604 if (!(mcg_cap & MCG_CTL_P))
1605 return 1;
1606 data = vcpu->arch.mcg_ctl;
1607 break;
1608 case MSR_IA32_MCG_STATUS:
1609 data = vcpu->arch.mcg_status;
1610 break;
1611 default:
1612 if (msr >= MSR_IA32_MC0_CTL &&
1613 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1614 u32 offset = msr - MSR_IA32_MC0_CTL;
1615 data = vcpu->arch.mce_banks[offset];
1616 break;
1617 }
1618 return 1;
1619 }
1620 *pdata = data;
1621 return 0;
1622}
1623
55cd8e5a
GN		 1624static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1625{
1626 u64 data = 0;
1627 struct kvm *kvm = vcpu->kvm;
1628
1629 switch (msr) {
1630 case HV_X64_MSR_GUEST_OS_ID:
1631 data = kvm->arch.hv_guest_os_id;
1632 break;
1633 case HV_X64_MSR_HYPERCALL:
1634 data = kvm->arch.hv_hypercall;
1635 break;
1636 default:
1637 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1638 return 1;
1639 }
1640
1641 *pdata = data;
1642 return 0;
1643}
1644
1645static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1646{
1647 u64 data = 0;
1648
1649 switch (msr) {
1650 case HV_X64_MSR_VP_INDEX: {
1651 int r;
1652 struct kvm_vcpu *v;
1653 kvm_for_each_vcpu(r, v, vcpu->kvm)
1654 if (v == vcpu)
1655 data = r;
1656 break;
1657 }
10388a07
GN		 1658 case HV_X64_MSR_EOI:
1659 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1660 case HV_X64_MSR_ICR:
1661 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1662 case HV_X64_MSR_TPR:
1663 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1664 default:
1665 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1666 return 1;
1667 }
1668 *pdata = data;
1669 return 0;
1670}
1671
890ca9ae
HY		 1672int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1673{
1674 u64 data;
1675
1676 switch (msr) {
890ca9ae 1677 case MSR_IA32_PLATFORM_ID:
15c4a640 1678 case MSR_IA32_UCODE_REV:
15c4a640 1679 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1680 case MSR_IA32_DEBUGCTLMSR:
1681 case MSR_IA32_LASTBRANCHFROMIP:
1682 case MSR_IA32_LASTBRANCHTOIP:
1683 case MSR_IA32_LASTINTFROMIP:
1684 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1685 case MSR_K8_SYSCFG:
1686 case MSR_K7_HWCR:
61a6bd67 1687 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1688 case MSR_P6_PERFCTR0:
1689 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1690 case MSR_P6_EVNTSEL0:
1691 case MSR_P6_EVNTSEL1:
9e699624 1692 case MSR_K7_EVNTSEL0:
1f3ee616 1693 case MSR_K7_PERFCTR0:
1fdbd48c 1694 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1695 case MSR_AMD64_NB_CFG:
f7c6d140 1696 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1697 data = 0;
1698 break;
9ba075a6
AK		 1699 case MSR_MTRRcap:
1700 data = 0x500 | KVM_NR_VAR_MTRR;
1701 break;
1702 case 0x200 ... 0x2ff:
1703 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1704 case 0xcd: /* fsb frequency */
1705 data = 3;
1706 break;
7b914098
JS		 1707 /*
1708 * MSR_EBC_FREQUENCY_ID
1709 * Conservative value valid for even the basic CPU models.
1710 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1711 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1712 * and 266MHz for model 3, or 4. Set Core Clock
1713 * Frequency to System Bus Frequency Ratio to 1 (bits
1714 * 31:24) even though these are only valid for CPU
1715 * models > 2, however guests may end up dividing or
1716 * multiplying by zero otherwise.
1717 */
1718 case MSR_EBC_FREQUENCY_ID:
1719 data = 1 << 24;
1720 break;
15c4a640
CO		 1721 case MSR_IA32_APICBASE:
1722 data = kvm_get_apic_base(vcpu);
1723 break;
0105d1a5
GN		 1724 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1725 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1726 break;
15c4a640 1727 case MSR_IA32_MISC_ENABLE:
ad312c7c 1728 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1729 break;
847f0ad8
AG		 1730 case MSR_IA32_PERF_STATUS:
1731 /* TSC increment by tick */
1732 data = 1000ULL;
1733 /* CPU multiplier */
1734 data |= (((uint64_t)4ULL) << 40);
1735 break;
15c4a640 1736 case MSR_EFER:
f6801dff 1737 data = vcpu->arch.efer;
15c4a640 1738 break;
18068523 1739 case MSR_KVM_WALL_CLOCK:
11c6bffa 1740 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1741 data = vcpu->kvm->arch.wall_clock;
1742 break;
1743 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1744 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1745 data = vcpu->arch.time;
1746 break;
890ca9ae
HY		 1747 case MSR_IA32_P5_MC_ADDR:
1748 case MSR_IA32_P5_MC_TYPE:
1749 case MSR_IA32_MCG_CAP:
1750 case MSR_IA32_MCG_CTL:
1751 case MSR_IA32_MCG_STATUS:
1752 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1753 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1754 case MSR_K7_CLK_CTL:
1755 /*
1756 * Provide expected ramp-up count for K7. All other
1757 * are set to zero, indicating minimum divisors for
1758 * every field.
1759 *
1760 * This prevents guest kernels on AMD host with CPU
1761 * type 6, model 8 and higher from exploding due to
1762 * the rdmsr failing.
1763 */
1764 data = 0x20000000;
1765 break;
55cd8e5a
GN		 1766 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1767 if (kvm_hv_msr_partition_wide(msr)) {
1768 int r;
1769 mutex_lock(&vcpu->kvm->lock);
1770 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1771 mutex_unlock(&vcpu->kvm->lock);
1772 return r;
1773 } else
1774 return get_msr_hyperv(vcpu, msr, pdata);
1775 break;
15c4a640 1776 default:
ed85c068
AP		 1777 if (!ignore_msrs) {
1778 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1779 return 1;
1780 } else {
1781 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1782 data = 0;
1783 }
1784 break;
15c4a640
CO		 1785 }
1786 *pdata = data;
1787 return 0;
1788}
1789EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1790
313a3dc7
CO		 1791/*
1792 * Read or write a bunch of msrs. All parameters are kernel addresses.
1793 *
1794 * @return number of msrs set successfully.
1795 */
1796static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1797 struct kvm_msr_entry *entries,
1798 int (*do_msr)(struct kvm_vcpu *vcpu,
1799 unsigned index, u64 *data))
1800{
f656ce01 1801 int i, idx;
313a3dc7 1802
f656ce01 1803 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1804 for (i = 0; i < msrs->nmsrs; ++i)
1805 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1806 break;
f656ce01 1807 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1808
313a3dc7
CO		 1809 return i;
1810}
1811
1812/*
1813 * Read or write a bunch of msrs. Parameters are user addresses.
1814 *
1815 * @return number of msrs set successfully.
1816 */
1817static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1818 int (*do_msr)(struct kvm_vcpu *vcpu,
1819 unsigned index, u64 *data),
1820 int writeback)
1821{
1822 struct kvm_msrs msrs;
1823 struct kvm_msr_entry *entries;
1824 int r, n;
1825 unsigned size;
1826
1827 r = -EFAULT;
1828 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1829 goto out;
1830
1831 r = -E2BIG;
1832 if (msrs.nmsrs >= MAX_IO_MSRS)
1833 goto out;
1834
1835 r = -ENOMEM;
1836 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1837 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1838 if (!entries)
1839 goto out;
1840
1841 r = -EFAULT;
1842 if (copy_from_user(entries, user_msrs->entries, size))
1843 goto out_free;
1844
1845 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1846 if (r < 0)
1847 goto out_free;
1848
1849 r = -EFAULT;
1850 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1851 goto out_free;
1852
1853 r = n;
1854
1855out_free:
7a73c028 1856 kfree(entries);
313a3dc7
CO		 1857out:
1858 return r;
1859}
1860
018d00d2
ZX		 1861int kvm_dev_ioctl_check_extension(long ext)
1862{
1863 int r;
1864
1865 switch (ext) {
1866 case KVM_CAP_IRQCHIP:
1867 case KVM_CAP_HLT:
1868 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1869 case KVM_CAP_SET_TSS_ADDR:
07716717 1870 case KVM_CAP_EXT_CPUID:
c8076604 1871 case KVM_CAP_CLOCKSOURCE:
7837699f 1872 case KVM_CAP_PIT:
a28e4f5a 1873 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1874 case KVM_CAP_MP_STATE:
ed848624 1875 case KVM_CAP_SYNC_MMU:
52d939a0 1876 case KVM_CAP_REINJECT_CONTROL:
4925663a 1877 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1878 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1879 case KVM_CAP_IRQFD:
d34e6b17 1880 case KVM_CAP_IOEVENTFD:
c5ff41ce 1881 case KVM_CAP_PIT2:
e9f42757 1882 case KVM_CAP_PIT_STATE2:
b927a3ce 1883 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1884 case KVM_CAP_XEN_HVM:
afbcf7ab 1885 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1886 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1887 case KVM_CAP_HYPERV:
10388a07 1888 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1889 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1890 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1891 case KVM_CAP_DEBUGREGS:
d2be1651 1892 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1893 case KVM_CAP_XSAVE:
018d00d2
ZX		 1894 r = 1;
1895 break;
542472b5
LV		 1896 case KVM_CAP_COALESCED_MMIO:
1897 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1898 break;
774ead3a
AK		 1899 case KVM_CAP_VAPIC:
1900 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1901 break;
f725230a
AK		 1902 case KVM_CAP_NR_VCPUS:
1903 r = KVM_MAX_VCPUS;
1904 break;
a988b910
AK		 1905 case KVM_CAP_NR_MEMSLOTS:
1906 r = KVM_MEMORY_SLOTS;
1907 break;
a68a6a72
MT		 1908 case KVM_CAP_PV_MMU: /* obsolete */
1909 r = 0;
2f333bcb 1910 break;
62c476c7 1911 case KVM_CAP_IOMMU:
19de40a8 1912 r = iommu_found();
62c476c7 1913 break;
890ca9ae
HY		 1914 case KVM_CAP_MCE:
1915 r = KVM_MAX_MCE_BANKS;
1916 break;
2d5b5a66
SY		 1917 case KVM_CAP_XCRS:
1918 r = cpu_has_xsave;
1919 break;
018d00d2
ZX		 1920 default:
1921 r = 0;
1922 break;
1923 }
1924 return r;
1925
1926}
1927
043405e1
CO		 1928long kvm_arch_dev_ioctl(struct file *filp,
1929 unsigned int ioctl, unsigned long arg)
1930{
1931 void __user *argp = (void __user *)arg;
1932 long r;
1933
1934 switch (ioctl) {
1935 case KVM_GET_MSR_INDEX_LIST: {
1936 struct kvm_msr_list __user *user_msr_list = argp;
1937 struct kvm_msr_list msr_list;
1938 unsigned n;
1939
1940 r = -EFAULT;
1941 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1942 goto out;
1943 n = msr_list.nmsrs;
1944 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1945 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1946 goto out;
1947 r = -E2BIG;
e125e7b6 1948 if (n < msr_list.nmsrs)
043405e1
CO		 1949 goto out;
1950 r = -EFAULT;
1951 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1952 num_msrs_to_save * sizeof(u32)))
1953 goto out;
e125e7b6 1954 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1955 &emulated_msrs,
1956 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1957 goto out;
1958 r = 0;
1959 break;
1960 }
674eea0f
AK		 1961 case KVM_GET_SUPPORTED_CPUID: {
1962 struct kvm_cpuid2 __user *cpuid_arg = argp;
1963 struct kvm_cpuid2 cpuid;
1964
1965 r = -EFAULT;
1966 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1967 goto out;
1968 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1969 cpuid_arg->entries);
674eea0f
AK		 1970 if (r)
1971 goto out;
1972
1973 r = -EFAULT;
1974 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1975 goto out;
1976 r = 0;
1977 break;
1978 }
890ca9ae
HY		 1979 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1980 u64 mce_cap;
1981
1982 mce_cap = KVM_MCE_CAP_SUPPORTED;
1983 r = -EFAULT;
1984 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1985 goto out;
1986 r = 0;
1987 break;
1988 }
043405e1
CO		 1989 default:
1990 r = -EINVAL;
1991 }
1992out:
1993 return r;
1994}
1995
f5f48ee1
SY		 1996static void wbinvd_ipi(void *garbage)
1997{
1998 wbinvd();
1999}
2000
2001static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2002{
2003 return vcpu->kvm->arch.iommu_domain &&
2004 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2005}
2006
313a3dc7
CO		 2007void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2008{
f5f48ee1
SY		 2009 /* Address WBINVD may be executed by guest */
2010 if (need_emulate_wbinvd(vcpu)) {
2011 if (kvm_x86_ops->has_wbinvd_exit())
2012 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2013 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2014 smp_call_function_single(vcpu->cpu,
2015 wbinvd_ipi, NULL, 1);
2016 }
2017
313a3dc7 2018 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2019 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2020 /* Make sure TSC doesn't go backwards */
2021 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2022 native_read_tsc() - vcpu->arch.last_host_tsc;
2023 if (tsc_delta < 0)
2024 mark_tsc_unstable("KVM discovered backwards TSC");
2025 if (check_tsc_unstable())
2026 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
2027 kvm_migrate_timers(vcpu);
2028 vcpu->cpu = cpu;
2029 }
313a3dc7
CO		 2030}
2031
2032void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2033{
02daab21 2034 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2035 kvm_put_guest_fpu(vcpu);
e48672fa 2036 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2037}
2038
07716717 2039static int is_efer_nx(void)
313a3dc7 2040{
e286e86e 2041 unsigned long long efer = 0;
313a3dc7 2042
e286e86e 2043 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2044 return efer & EFER_NX;
2045}
2046
2047static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2048{
2049 int i;
2050 struct kvm_cpuid_entry2 *e, *entry;
2051
313a3dc7 2052 entry = NULL;
ad312c7c
ZX		 2053 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2054 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2055 if (e->function == 0x80000001) {
2056 entry = e;
2057 break;
2058 }
2059 }
07716717 2060 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2061 entry->edx &= ~(1 << 20);
2062 printk(KERN_INFO "kvm: guest NX capability removed\n");
2063 }
2064}
2065
07716717 2066/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2067static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2068 struct kvm_cpuid *cpuid,
2069 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2070{
2071 int r, i;
2072 struct kvm_cpuid_entry *cpuid_entries;
2073
2074 r = -E2BIG;
2075 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2076 goto out;
2077 r = -ENOMEM;
2078 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2079 if (!cpuid_entries)
2080 goto out;
2081 r = -EFAULT;
2082 if (copy_from_user(cpuid_entries, entries,
2083 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2084 goto out_free;
2085 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2086 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2087 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2088 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2089 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2090 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2091 vcpu->arch.cpuid_entries[i].index = 0;
2092 vcpu->arch.cpuid_entries[i].flags = 0;
2093 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2094 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2095 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2096 }
2097 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2098 cpuid_fix_nx_cap(vcpu);
2099 r = 0;
fc61b800 2100 kvm_apic_set_version(vcpu);
0e851880 2101 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2102 update_cpuid(vcpu);
07716717
DK		 2103
2104out_free:
2105 vfree(cpuid_entries);
2106out:
2107 return r;
2108}
2109
2110static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2111 struct kvm_cpuid2 *cpuid,
2112 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2113{
2114 int r;
2115
2116 r = -E2BIG;
2117 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2118 goto out;
2119 r = -EFAULT;
ad312c7c 2120 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2121 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2122 goto out;
ad312c7c 2123 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2124 kvm_apic_set_version(vcpu);
0e851880 2125 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2126 update_cpuid(vcpu);
313a3dc7
CO		 2127 return 0;
2128
2129out:
2130 return r;
2131}
2132
07716717 2133static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2134 struct kvm_cpuid2 *cpuid,
2135 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2136{
2137 int r;
2138
2139 r = -E2BIG;
ad312c7c 2140 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2141 goto out;
2142 r = -EFAULT;
ad312c7c 2143 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2144 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2145 goto out;
2146 return 0;
2147
2148out:
ad312c7c 2149 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2150 return r;
2151}
2152
07716717 2153static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2154 u32 index)
07716717
DK		 2155{
2156 entry->function = function;
2157 entry->index = index;
2158 cpuid_count(entry->function, entry->index,
19355475 2159 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2160 entry->flags = 0;
2161}
2162
7faa4ee1
AK		 2163#define F(x) bit(X86_FEATURE_##x)
2164
07716717
DK		 2165static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2166 u32 index, int *nent, int maxnent)
2167{
7faa4ee1 2168 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2169#ifdef CONFIG_X86_64
17cc3935
SY		 2170 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2171 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2172 unsigned f_lm = F(LM);
2173#else
17cc3935 2174 unsigned f_gbpages = 0;
7faa4ee1 2175 unsigned f_lm = 0;
07716717 2176#endif
4e47c7a6 2177 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2178
2179 /* cpuid 1.edx */
2180 const u32 kvm_supported_word0_x86_features =
2181 F(FPU) | F(VME) | F(DE) | F(PSE) |
2182 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2183 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2184 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2185 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2186 0 /* Reserved, DS, ACPI */ | F(MMX) |
2187 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2188 0 /* HTT, TM, Reserved, PBE */;
2189 /* cpuid 0x80000001.edx */
2190 const u32 kvm_supported_word1_x86_features =
2191 F(FPU) | F(VME) | F(DE) | F(PSE) |
2192 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2193 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2194 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2195 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2196 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2197 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2198 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2199 /* cpuid 1.ecx */
2200 const u32 kvm_supported_word4_x86_features =
6c3f6041 2201 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2202 0 /* DS-CPL, VMX, SMX, EST */ |
2203 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2204 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2205 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2206 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6c3f6041 2207 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
7faa4ee1 2208 /* cpuid 0x80000001.ecx */
07716717 2209 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2210 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1
AK		 2211 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2212 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
2213 0 /* SKINIT */ | 0 /* WDT */;
07716717 2214
19355475 2215 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2216 get_cpu();
2217 do_cpuid_1_ent(entry, function, index);
2218 ++*nent;
2219
2220 switch (function) {
2221 case 0:
2acf923e 2222 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2223 break;
2224 case 1:
2225 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2226 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2227 /* we support x2apic emulation even if host does not support
2228 * it since we emulate x2apic in software */
2229 entry->ecx |= F(X2APIC);
07716717
DK		 2230 break;
2231 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2232 * may return different values. This forces us to get_cpu() before
2233 * issuing the first command, and also to emulate this annoying behavior
2234 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2235 case 2: {
2236 int t, times = entry->eax & 0xff;
2237
2238 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2239 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2240 for (t = 1; t < times && *nent < maxnent; ++t) {
2241 do_cpuid_1_ent(&entry[t], function, 0);
2242 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2243 ++*nent;
2244 }
2245 break;
2246 }
2247 /* function 4 and 0xb have additional index. */
2248 case 4: {
14af3f3c 2249 int i, cache_type;
07716717
DK		 2250
2251 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2252 /* read more entries until cache_type is zero */
14af3f3c
HH		 2253 for (i = 1; *nent < maxnent; ++i) {
2254 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2255 if (!cache_type)
2256 break;
14af3f3c
HH		 2257 do_cpuid_1_ent(&entry[i], function, i);
2258 entry[i].flags |=
07716717
DK		 2259 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2260 ++*nent;
2261 }
2262 break;
2263 }
2264 case 0xb: {
14af3f3c 2265 int i, level_type;
07716717
DK		 2266
2267 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2268 /* read more entries until level_type is zero */
14af3f3c 2269 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2270 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2271 if (!level_type)
2272 break;
14af3f3c
HH		 2273 do_cpuid_1_ent(&entry[i], function, i);
2274 entry[i].flags |=
07716717
DK		 2275 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2276 ++*nent;
2277 }
2278 break;
2279 }
2acf923e
DC		 2280 case 0xd: {
2281 int i;
2282
2283 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2284 for (i = 1; *nent < maxnent; ++i) {
2285 if (entry[i - 1].eax == 0 && i != 2)
2286 break;
2287 do_cpuid_1_ent(&entry[i], function, i);
2288 entry[i].flags |=
2289 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2290 ++*nent;
2291 }
2292 break;
2293 }
84478c82
GC		 2294 case KVM_CPUID_SIGNATURE: {
2295 char signature[12] = "KVMKVMKVM\0\0";
2296 u32 *sigptr = (u32 *)signature;
2297 entry->eax = 0;
2298 entry->ebx = sigptr[0];
2299 entry->ecx = sigptr[1];
2300 entry->edx = sigptr[2];
2301 break;
2302 }
2303 case KVM_CPUID_FEATURES:
2304 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2305 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2306 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2307 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2308 entry->ebx = 0;
2309 entry->ecx = 0;
2310 entry->edx = 0;
2311 break;
07716717
DK		 2312 case 0x80000000:
2313 entry->eax = min(entry->eax, 0x8000001a);
2314 break;
2315 case 0x80000001:
2316 entry->edx &= kvm_supported_word1_x86_features;
2317 entry->ecx &= kvm_supported_word6_x86_features;
2318 break;
2319 }
d4330ef2
JR		 2320
2321 kvm_x86_ops->set_supported_cpuid(function, entry);
2322
07716717
DK		 2323 put_cpu();
2324}
2325
7faa4ee1
AK		 2326#undef F
2327
674eea0f 2328static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2329 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2330{
2331 struct kvm_cpuid_entry2 *cpuid_entries;
2332 int limit, nent = 0, r = -E2BIG;
2333 u32 func;
2334
2335 if (cpuid->nent < 1)
2336 goto out;
6a544355
AK		 2337 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2338 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2339 r = -ENOMEM;
2340 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2341 if (!cpuid_entries)
2342 goto out;
2343
2344 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2345 limit = cpuid_entries[0].eax;
2346 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2347 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2348 &nent, cpuid->nent);
07716717
DK		 2349 r = -E2BIG;
2350 if (nent >= cpuid->nent)
2351 goto out_free;
2352
2353 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2354 limit = cpuid_entries[nent - 1].eax;
2355 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2356 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2357 &nent, cpuid->nent);
84478c82
GC		 2358
2359
2360
2361 r = -E2BIG;
2362 if (nent >= cpuid->nent)
2363 goto out_free;
2364
2365 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2366 cpuid->nent);
2367
2368 r = -E2BIG;
2369 if (nent >= cpuid->nent)
2370 goto out_free;
2371
2372 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2373 cpuid->nent);
2374
cb007648
MM		 2375 r = -E2BIG;
2376 if (nent >= cpuid->nent)
2377 goto out_free;
2378
07716717
DK		 2379 r = -EFAULT;
2380 if (copy_to_user(entries, cpuid_entries,
19355475 2381 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2382 goto out_free;
2383 cpuid->nent = nent;
2384 r = 0;
2385
2386out_free:
2387 vfree(cpuid_entries);
2388out:
2389 return r;
2390}
2391
313a3dc7
CO		 2392static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2393 struct kvm_lapic_state *s)
2394{
ad312c7c 2395 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2396
2397 return 0;
2398}
2399
2400static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2401 struct kvm_lapic_state *s)
2402{
ad312c7c 2403 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2404 kvm_apic_post_state_restore(vcpu);
cb142eb7 2405 update_cr8_intercept(vcpu);
313a3dc7
CO		 2406
2407 return 0;
2408}
2409
f77bc6a4
ZX		 2410static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2411 struct kvm_interrupt *irq)
2412{
2413 if (irq->irq < 0 || irq->irq >= 256)
2414 return -EINVAL;
2415 if (irqchip_in_kernel(vcpu->kvm))
2416 return -ENXIO;
f77bc6a4 2417
66fd3f7f 2418 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2419 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2420
f77bc6a4
ZX		 2421 return 0;
2422}
2423
c4abb7c9
JK		 2424static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2425{
c4abb7c9 2426 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2427
2428 return 0;
2429}
2430
b209749f
AK		 2431static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2432 struct kvm_tpr_access_ctl *tac)
2433{
2434 if (tac->flags)
2435 return -EINVAL;
2436 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2437 return 0;
2438}
2439
890ca9ae
HY		 2440static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2441 u64 mcg_cap)
2442{
2443 int r;
2444 unsigned bank_num = mcg_cap & 0xff, bank;
2445
2446 r = -EINVAL;
a9e38c3e 2447 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2448 goto out;
2449 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2450 goto out;
2451 r = 0;
2452 vcpu->arch.mcg_cap = mcg_cap;
2453 /* Init IA32_MCG_CTL to all 1s */
2454 if (mcg_cap & MCG_CTL_P)
2455 vcpu->arch.mcg_ctl = ~(u64)0;
2456 /* Init IA32_MCi_CTL to all 1s */
2457 for (bank = 0; bank < bank_num; bank++)
2458 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2459out:
2460 return r;
2461}
2462
2463static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2464 struct kvm_x86_mce *mce)
2465{
2466 u64 mcg_cap = vcpu->arch.mcg_cap;
2467 unsigned bank_num = mcg_cap & 0xff;
2468 u64 *banks = vcpu->arch.mce_banks;
2469
2470 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2471 return -EINVAL;
2472 /*
2473 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2474 * reporting is disabled
2475 */
2476 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2477 vcpu->arch.mcg_ctl != ~(u64)0)
2478 return 0;
2479 banks += 4 * mce->bank;
2480 /*
2481 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2482 * reporting is disabled for the bank
2483 */
2484 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2485 return 0;
2486 if (mce->status & MCI_STATUS_UC) {
2487 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2488 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2489 printk(KERN_DEBUG "kvm: set_mce: "
2490 "injects mce exception while "
2491 "previous one is in progress!\n");
a8eeb04a 2492 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2493 return 0;
2494 }
2495 if (banks[1] & MCI_STATUS_VAL)
2496 mce->status |= MCI_STATUS_OVER;
2497 banks[2] = mce->addr;
2498 banks[3] = mce->misc;
2499 vcpu->arch.mcg_status = mce->mcg_status;
2500 banks[1] = mce->status;
2501 kvm_queue_exception(vcpu, MC_VECTOR);
2502 } else if (!(banks[1] & MCI_STATUS_VAL)
2503 || !(banks[1] & MCI_STATUS_UC)) {
2504 if (banks[1] & MCI_STATUS_VAL)
2505 mce->status |= MCI_STATUS_OVER;
2506 banks[2] = mce->addr;
2507 banks[3] = mce->misc;
2508 banks[1] = mce->status;
2509 } else
2510 banks[1] |= MCI_STATUS_OVER;
2511 return 0;
2512}
2513
3cfc3092
JK		 2514static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2515 struct kvm_vcpu_events *events)
2516{
03b82a30
JK		 2517 events->exception.injected =
2518 vcpu->arch.exception.pending &&
2519 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2520 events->exception.nr = vcpu->arch.exception.nr;
2521 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2522 events->exception.error_code = vcpu->arch.exception.error_code;
2523
03b82a30
JK		 2524 events->interrupt.injected =
2525 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2526 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2527 events->interrupt.soft = 0;
48005f64
JK		 2528 events->interrupt.shadow =
2529 kvm_x86_ops->get_interrupt_shadow(vcpu,
2530 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2531
2532 events->nmi.injected = vcpu->arch.nmi_injected;
2533 events->nmi.pending = vcpu->arch.nmi_pending;
2534 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2535
2536 events->sipi_vector = vcpu->arch.sipi_vector;
2537
dab4b911 2538 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2539 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2540 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2541}
2542
2543static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2544 struct kvm_vcpu_events *events)
2545{
dab4b911 2546 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2547 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2548 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2549 return -EINVAL;
2550
3cfc3092
JK		 2551 vcpu->arch.exception.pending = events->exception.injected;
2552 vcpu->arch.exception.nr = events->exception.nr;
2553 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2554 vcpu->arch.exception.error_code = events->exception.error_code;
2555
2556 vcpu->arch.interrupt.pending = events->interrupt.injected;
2557 vcpu->arch.interrupt.nr = events->interrupt.nr;
2558 vcpu->arch.interrupt.soft = events->interrupt.soft;
2559 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2560 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2561 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2562 kvm_x86_ops->set_interrupt_shadow(vcpu,
2563 events->interrupt.shadow);
3cfc3092
JK		 2564
2565 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2566 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2567 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2568 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2569
dab4b911
JK		 2570 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2571 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2572
3842d135
AK		 2573 kvm_make_request(KVM_REQ_EVENT, vcpu);
2574
3cfc3092
JK		 2575 return 0;
2576}
2577
a1efbe77
JK		 2578static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2579 struct kvm_debugregs *dbgregs)
2580{
a1efbe77
JK		 2581 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2582 dbgregs->dr6 = vcpu->arch.dr6;
2583 dbgregs->dr7 = vcpu->arch.dr7;
2584 dbgregs->flags = 0;
a1efbe77
JK		 2585}
2586
2587static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2588 struct kvm_debugregs *dbgregs)
2589{
2590 if (dbgregs->flags)
2591 return -EINVAL;
2592
a1efbe77
JK		 2593 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2594 vcpu->arch.dr6 = dbgregs->dr6;
2595 vcpu->arch.dr7 = dbgregs->dr7;
2596
a1efbe77
JK		 2597 return 0;
2598}
2599
2d5b5a66
SY		 2600static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2601 struct kvm_xsave *guest_xsave)
2602{
2603 if (cpu_has_xsave)
2604 memcpy(guest_xsave->region,
2605 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2606 xstate_size);
2d5b5a66
SY		 2607 else {
2608 memcpy(guest_xsave->region,
2609 &vcpu->arch.guest_fpu.state->fxsave,
2610 sizeof(struct i387_fxsave_struct));
2611 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2612 XSTATE_FPSSE;
2613 }
2614}
2615
2616static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2617 struct kvm_xsave *guest_xsave)
2618{
2619 u64 xstate_bv =
2620 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2621
2622 if (cpu_has_xsave)
2623 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2624 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2625 else {
2626 if (xstate_bv & ~XSTATE_FPSSE)
2627 return -EINVAL;
2628 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2629 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2630 }
2631 return 0;
2632}
2633
2634static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2635 struct kvm_xcrs *guest_xcrs)
2636{
2637 if (!cpu_has_xsave) {
2638 guest_xcrs->nr_xcrs = 0;
2639 return;
2640 }
2641
2642 guest_xcrs->nr_xcrs = 1;
2643 guest_xcrs->flags = 0;
2644 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2645 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2646}
2647
2648static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2649 struct kvm_xcrs *guest_xcrs)
2650{
2651 int i, r = 0;
2652
2653 if (!cpu_has_xsave)
2654 return -EINVAL;
2655
2656 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2657 return -EINVAL;
2658
2659 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2660 /* Only support XCR0 currently */
2661 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2662 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2663 guest_xcrs->xcrs[0].value);
2664 break;
2665 }
2666 if (r)
2667 r = -EINVAL;
2668 return r;
2669}
2670
313a3dc7
CO		 2671long kvm_arch_vcpu_ioctl(struct file *filp,
2672 unsigned int ioctl, unsigned long arg)
2673{
2674 struct kvm_vcpu *vcpu = filp->private_data;
2675 void __user *argp = (void __user *)arg;
2676 int r;
d1ac91d8
AK		 2677 union {
2678 struct kvm_lapic_state *lapic;
2679 struct kvm_xsave *xsave;
2680 struct kvm_xcrs *xcrs;
2681 void *buffer;
2682 } u;
2683
2684 u.buffer = NULL;
313a3dc7
CO		 2685 switch (ioctl) {
2686 case KVM_GET_LAPIC: {
2204ae3c
MT		 2687 r = -EINVAL;
2688 if (!vcpu->arch.apic)
2689 goto out;
d1ac91d8 2690 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2691
b772ff36 2692 r = -ENOMEM;
d1ac91d8 2693 if (!u.lapic)
b772ff36 2694 goto out;
d1ac91d8 2695 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2696 if (r)
2697 goto out;
2698 r = -EFAULT;
d1ac91d8 2699 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2700 goto out;
2701 r = 0;
2702 break;
2703 }
2704 case KVM_SET_LAPIC: {
2204ae3c
MT		 2705 r = -EINVAL;
2706 if (!vcpu->arch.apic)
2707 goto out;
d1ac91d8 2708 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2709 r = -ENOMEM;
d1ac91d8 2710 if (!u.lapic)
b772ff36 2711 goto out;
313a3dc7 2712 r = -EFAULT;
d1ac91d8 2713 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2714 goto out;
d1ac91d8 2715 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2716 if (r)
2717 goto out;
2718 r = 0;
2719 break;
2720 }
f77bc6a4
ZX		 2721 case KVM_INTERRUPT: {
2722 struct kvm_interrupt irq;
2723
2724 r = -EFAULT;
2725 if (copy_from_user(&irq, argp, sizeof irq))
2726 goto out;
2727 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2728 if (r)
2729 goto out;
2730 r = 0;
2731 break;
2732 }
c4abb7c9
JK		 2733 case KVM_NMI: {
2734 r = kvm_vcpu_ioctl_nmi(vcpu);
2735 if (r)
2736 goto out;
2737 r = 0;
2738 break;
2739 }
313a3dc7
CO		 2740 case KVM_SET_CPUID: {
2741 struct kvm_cpuid __user *cpuid_arg = argp;
2742 struct kvm_cpuid cpuid;
2743
2744 r = -EFAULT;
2745 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2746 goto out;
2747 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2748 if (r)
2749 goto out;
2750 break;
2751 }
07716717
DK		 2752 case KVM_SET_CPUID2: {
2753 struct kvm_cpuid2 __user *cpuid_arg = argp;
2754 struct kvm_cpuid2 cpuid;
2755
2756 r = -EFAULT;
2757 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2758 goto out;
2759 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2760 cpuid_arg->entries);
07716717
DK		 2761 if (r)
2762 goto out;
2763 break;
2764 }
2765 case KVM_GET_CPUID2: {
2766 struct kvm_cpuid2 __user *cpuid_arg = argp;
2767 struct kvm_cpuid2 cpuid;
2768
2769 r = -EFAULT;
2770 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2771 goto out;
2772 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2773 cpuid_arg->entries);
07716717
DK		 2774 if (r)
2775 goto out;
2776 r = -EFAULT;
2777 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2778 goto out;
2779 r = 0;
2780 break;
2781 }
313a3dc7
CO		 2782 case KVM_GET_MSRS:
2783 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2784 break;
2785 case KVM_SET_MSRS:
2786 r = msr_io(vcpu, argp, do_set_msr, 0);
2787 break;
b209749f
AK		 2788 case KVM_TPR_ACCESS_REPORTING: {
2789 struct kvm_tpr_access_ctl tac;
2790
2791 r = -EFAULT;
2792 if (copy_from_user(&tac, argp, sizeof tac))
2793 goto out;
2794 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2795 if (r)
2796 goto out;
2797 r = -EFAULT;
2798 if (copy_to_user(argp, &tac, sizeof tac))
2799 goto out;
2800 r = 0;
2801 break;
2802 };
b93463aa
AK		 2803 case KVM_SET_VAPIC_ADDR: {
2804 struct kvm_vapic_addr va;
2805
2806 r = -EINVAL;
2807 if (!irqchip_in_kernel(vcpu->kvm))
2808 goto out;
2809 r = -EFAULT;
2810 if (copy_from_user(&va, argp, sizeof va))
2811 goto out;
2812 r = 0;
2813 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2814 break;
2815 }
890ca9ae
HY		 2816 case KVM_X86_SETUP_MCE: {
2817 u64 mcg_cap;
2818
2819 r = -EFAULT;
2820 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2821 goto out;
2822 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2823 break;
2824 }
2825 case KVM_X86_SET_MCE: {
2826 struct kvm_x86_mce mce;
2827
2828 r = -EFAULT;
2829 if (copy_from_user(&mce, argp, sizeof mce))
2830 goto out;
2831 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2832 break;
2833 }
3cfc3092
JK		 2834 case KVM_GET_VCPU_EVENTS: {
2835 struct kvm_vcpu_events events;
2836
2837 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2838
2839 r = -EFAULT;
2840 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2841 break;
2842 r = 0;
2843 break;
2844 }
2845 case KVM_SET_VCPU_EVENTS: {
2846 struct kvm_vcpu_events events;
2847
2848 r = -EFAULT;
2849 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2850 break;
2851
2852 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2853 break;
2854 }
a1efbe77
JK		 2855 case KVM_GET_DEBUGREGS: {
2856 struct kvm_debugregs dbgregs;
2857
2858 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2859
2860 r = -EFAULT;
2861 if (copy_to_user(argp, &dbgregs,
2862 sizeof(struct kvm_debugregs)))
2863 break;
2864 r = 0;
2865 break;
2866 }
2867 case KVM_SET_DEBUGREGS: {
2868 struct kvm_debugregs dbgregs;
2869
2870 r = -EFAULT;
2871 if (copy_from_user(&dbgregs, argp,
2872 sizeof(struct kvm_debugregs)))
2873 break;
2874
2875 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2876 break;
2877 }
2d5b5a66 2878 case KVM_GET_XSAVE: {
d1ac91d8 2879 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2880 r = -ENOMEM;
d1ac91d8 2881 if (!u.xsave)
2d5b5a66
SY		 2882 break;
2883
d1ac91d8 2884 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2885
2886 r = -EFAULT;
d1ac91d8 2887 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2888 break;
2889 r = 0;
2890 break;
2891 }
2892 case KVM_SET_XSAVE: {
d1ac91d8 2893 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2894 r = -ENOMEM;
d1ac91d8 2895 if (!u.xsave)
2d5b5a66
SY		 2896 break;
2897
2898 r = -EFAULT;
d1ac91d8 2899 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2900 break;
2901
d1ac91d8 2902 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2903 break;
2904 }
2905 case KVM_GET_XCRS: {
d1ac91d8 2906 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2907 r = -ENOMEM;
d1ac91d8 2908 if (!u.xcrs)
2d5b5a66
SY		 2909 break;
2910
d1ac91d8 2911 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2912
2913 r = -EFAULT;
d1ac91d8 2914 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2915 sizeof(struct kvm_xcrs)))
2916 break;
2917 r = 0;
2918 break;
2919 }
2920 case KVM_SET_XCRS: {
d1ac91d8 2921 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2922 r = -ENOMEM;
d1ac91d8 2923 if (!u.xcrs)
2d5b5a66
SY		 2924 break;
2925
2926 r = -EFAULT;
d1ac91d8 2927 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2928 sizeof(struct kvm_xcrs)))
2929 break;
2930
d1ac91d8 2931 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2932 break;
2933 }
313a3dc7
CO		 2934 default:
2935 r = -EINVAL;
2936 }
2937out:
d1ac91d8 2938 kfree(u.buffer);
313a3dc7
CO		 2939 return r;
2940}
2941
1fe779f8
CO		 2942static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2943{
2944 int ret;
2945
2946 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2947 return -1;
2948 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2949 return ret;
2950}
2951
b927a3ce
SY		 2952static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2953 u64 ident_addr)
2954{
2955 kvm->arch.ept_identity_map_addr = ident_addr;
2956 return 0;
2957}
2958
1fe779f8
CO		 2959static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2960 u32 kvm_nr_mmu_pages)
2961{
2962 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2963 return -EINVAL;
2964
79fac95e 2965 mutex_lock(&kvm->slots_lock);
7c8a83b7 2966 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2967
2968 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2969 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2970
7c8a83b7 2971 spin_unlock(&kvm->mmu_lock);
79fac95e 2972 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2973 return 0;
2974}
2975
2976static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2977{
39de71ec 2978 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2979}
2980
1fe779f8
CO		 2981static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2982{
2983 int r;
2984
2985 r = 0;
2986 switch (chip->chip_id) {
2987 case KVM_IRQCHIP_PIC_MASTER:
2988 memcpy(&chip->chip.pic,
2989 &pic_irqchip(kvm)->pics[0],
2990 sizeof(struct kvm_pic_state));
2991 break;
2992 case KVM_IRQCHIP_PIC_SLAVE:
2993 memcpy(&chip->chip.pic,
2994 &pic_irqchip(kvm)->pics[1],
2995 sizeof(struct kvm_pic_state));
2996 break;
2997 case KVM_IRQCHIP_IOAPIC:
eba0226b 2998 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2999 break;
3000 default:
3001 r = -EINVAL;
3002 break;
3003 }
3004 return r;
3005}
3006
3007static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3008{
3009 int r;
3010
3011 r = 0;
3012 switch (chip->chip_id) {
3013 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3014 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3015 memcpy(&pic_irqchip(kvm)->pics[0],
3016 &chip->chip.pic,
3017 sizeof(struct kvm_pic_state));
f4f51050 3018 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3019 break;
3020 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3021 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3022 memcpy(&pic_irqchip(kvm)->pics[1],
3023 &chip->chip.pic,
3024 sizeof(struct kvm_pic_state));
f4f51050 3025 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3026 break;
3027 case KVM_IRQCHIP_IOAPIC:
eba0226b 3028 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3029 break;
3030 default:
3031 r = -EINVAL;
3032 break;
3033 }
3034 kvm_pic_update_irq(pic_irqchip(kvm));
3035 return r;
3036}
3037
e0f63cb9
SY		 3038static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3039{
3040 int r = 0;
3041
894a9c55 3042 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3043 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3044 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3045 return r;
3046}
3047
3048static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3049{
3050 int r = 0;
3051
894a9c55 3052 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3053 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3054 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3055 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3056 return r;
3057}
3058
3059static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3060{
3061 int r = 0;
3062
3063 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3064 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3065 sizeof(ps->channels));
3066 ps->flags = kvm->arch.vpit->pit_state.flags;
3067 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3068 return r;
3069}
3070
3071static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3072{
3073 int r = 0, start = 0;
3074 u32 prev_legacy, cur_legacy;
3075 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3076 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3077 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3078 if (!prev_legacy && cur_legacy)
3079 start = 1;
3080 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3081 sizeof(kvm->arch.vpit->pit_state.channels));
3082 kvm->arch.vpit->pit_state.flags = ps->flags;
3083 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3084 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3085 return r;
3086}
3087
52d939a0
MT		 3088static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3089 struct kvm_reinject_control *control)
3090{
3091 if (!kvm->arch.vpit)
3092 return -ENXIO;
894a9c55 3093 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3094 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3095 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3096 return 0;
3097}
3098
5bb064dc
ZX		 3099/*
3100 * Get (and clear) the dirty memory log for a memory slot.
3101 */
3102int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3103 struct kvm_dirty_log *log)
3104{
87bf6e7d 3105 int r, i;
5bb064dc 3106 struct kvm_memory_slot *memslot;
87bf6e7d 3107 unsigned long n;
b050b015 3108 unsigned long is_dirty = 0;
5bb064dc 3109
79fac95e 3110 mutex_lock(&kvm->slots_lock);
5bb064dc 3111
b050b015
MT		 3112 r = -EINVAL;
3113 if (log->slot >= KVM_MEMORY_SLOTS)
3114 goto out;
3115
3116 memslot = &kvm->memslots->memslots[log->slot];
3117 r = -ENOENT;
3118 if (!memslot->dirty_bitmap)
3119 goto out;
3120
87bf6e7d 3121 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3122
b050b015
MT		 3123 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3124 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3125
3126 /* If nothing is dirty, don't bother messing with page tables. */
3127 if (is_dirty) {
b050b015 3128 struct kvm_memslots *slots, *old_slots;
914ebccd 3129 unsigned long *dirty_bitmap;
b050b015 3130
7c8a83b7 3131 spin_lock(&kvm->mmu_lock);
5bb064dc 3132 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 3133 spin_unlock(&kvm->mmu_lock);
b050b015 3134
914ebccd
TY		 3135 r = -ENOMEM;
3136 dirty_bitmap = vmalloc(n);
3137 if (!dirty_bitmap)
3138 goto out;
3139 memset(dirty_bitmap, 0, n);
b050b015 3140
914ebccd
TY		 3141 r = -ENOMEM;
3142 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3143 if (!slots) {
3144 vfree(dirty_bitmap);
3145 goto out;
3146 }
b050b015
MT		 3147 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3148 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3149
3150 old_slots = kvm->memslots;
3151 rcu_assign_pointer(kvm->memslots, slots);
3152 synchronize_srcu_expedited(&kvm->srcu);
3153 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3154 kfree(old_slots);
914ebccd
TY		 3155
3156 r = -EFAULT;
3157 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3158 vfree(dirty_bitmap);
3159 goto out;
3160 }
3161 vfree(dirty_bitmap);
3162 } else {
3163 r = -EFAULT;
3164 if (clear_user(log->dirty_bitmap, n))
3165 goto out;
5bb064dc 3166 }
b050b015 3167
5bb064dc
ZX		 3168 r = 0;
3169out:
79fac95e 3170 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3171 return r;
3172}
3173
1fe779f8
CO		 3174long kvm_arch_vm_ioctl(struct file *filp,
3175 unsigned int ioctl, unsigned long arg)
3176{
3177 struct kvm *kvm = filp->private_data;
3178 void __user *argp = (void __user *)arg;
367e1319 3179 int r = -ENOTTY;
f0d66275
DH		 3180 /*
3181 * This union makes it completely explicit to gcc-3.x
3182 * that these two variables' stack usage should be
3183 * combined, not added together.
3184 */
3185 union {
3186 struct kvm_pit_state ps;
e9f42757 3187 struct kvm_pit_state2 ps2;
c5ff41ce 3188 struct kvm_pit_config pit_config;
f0d66275 3189 } u;
1fe779f8
CO		 3190
3191 switch (ioctl) {
3192 case KVM_SET_TSS_ADDR:
3193 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3194 if (r < 0)
3195 goto out;
3196 break;
b927a3ce
SY		 3197 case KVM_SET_IDENTITY_MAP_ADDR: {
3198 u64 ident_addr;
3199
3200 r = -EFAULT;
3201 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3202 goto out;
3203 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3204 if (r < 0)
3205 goto out;
3206 break;
3207 }
1fe779f8
CO		 3208 case KVM_SET_NR_MMU_PAGES:
3209 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3210 if (r)
3211 goto out;
3212 break;
3213 case KVM_GET_NR_MMU_PAGES:
3214 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3215 break;
3ddea128
MT		 3216 case KVM_CREATE_IRQCHIP: {
3217 struct kvm_pic *vpic;
3218
3219 mutex_lock(&kvm->lock);
3220 r = -EEXIST;
3221 if (kvm->arch.vpic)
3222 goto create_irqchip_unlock;
1fe779f8 3223 r = -ENOMEM;
3ddea128
MT		 3224 vpic = kvm_create_pic(kvm);
3225 if (vpic) {
1fe779f8
CO		 3226 r = kvm_ioapic_init(kvm);
3227 if (r) {
72bb2fcd
WY		 3228 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3229 &vpic->dev);
3ddea128
MT		 3230 kfree(vpic);
3231 goto create_irqchip_unlock;
1fe779f8
CO		 3232 }
3233 } else
3ddea128
MT		 3234 goto create_irqchip_unlock;
3235 smp_wmb();
3236 kvm->arch.vpic = vpic;
3237 smp_wmb();
399ec807
AK		 3238 r = kvm_setup_default_irq_routing(kvm);
3239 if (r) {
3ddea128 3240 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3241 kvm_ioapic_destroy(kvm);
3242 kvm_destroy_pic(kvm);
3ddea128 3243 mutex_unlock(&kvm->irq_lock);
399ec807 3244 }
3ddea128
MT		 3245 create_irqchip_unlock:
3246 mutex_unlock(&kvm->lock);
1fe779f8 3247 break;
3ddea128 3248 }
7837699f 3249 case KVM_CREATE_PIT:
c5ff41ce
JK		 3250 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3251 goto create_pit;
3252 case KVM_CREATE_PIT2:
3253 r = -EFAULT;
3254 if (copy_from_user(&u.pit_config, argp,
3255 sizeof(struct kvm_pit_config)))
3256 goto out;
3257 create_pit:
79fac95e 3258 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3259 r = -EEXIST;
3260 if (kvm->arch.vpit)
3261 goto create_pit_unlock;
7837699f 3262 r = -ENOMEM;
c5ff41ce 3263 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3264 if (kvm->arch.vpit)
3265 r = 0;
269e05e4 3266 create_pit_unlock:
79fac95e 3267 mutex_unlock(&kvm->slots_lock);
7837699f 3268 break;
4925663a 3269 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3270 case KVM_IRQ_LINE: {
3271 struct kvm_irq_level irq_event;
3272
3273 r = -EFAULT;
3274 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3275 goto out;
160d2f6c 3276 r = -ENXIO;
1fe779f8 3277 if (irqchip_in_kernel(kvm)) {
4925663a 3278 __s32 status;
4925663a
GN		 3279 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3280 irq_event.irq, irq_event.level);
4925663a 3281 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3282 r = -EFAULT;
4925663a
GN		 3283 irq_event.status = status;
3284 if (copy_to_user(argp, &irq_event,
3285 sizeof irq_event))
3286 goto out;
3287 }
1fe779f8
CO		 3288 r = 0;
3289 }
3290 break;
3291 }
3292 case KVM_GET_IRQCHIP: {
3293 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3294 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3295
f0d66275
DH		 3296 r = -ENOMEM;
3297 if (!chip)
1fe779f8 3298 goto out;
f0d66275
DH		 3299 r = -EFAULT;
3300 if (copy_from_user(chip, argp, sizeof *chip))
3301 goto get_irqchip_out;
1fe779f8
CO		 3302 r = -ENXIO;
3303 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3304 goto get_irqchip_out;
3305 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3306 if (r)
f0d66275 3307 goto get_irqchip_out;
1fe779f8 3308 r = -EFAULT;
f0d66275
DH		 3309 if (copy_to_user(argp, chip, sizeof *chip))
3310 goto get_irqchip_out;
1fe779f8 3311 r = 0;
f0d66275
DH		 3312 get_irqchip_out:
3313 kfree(chip);
3314 if (r)
3315 goto out;
1fe779f8
CO		 3316 break;
3317 }
3318 case KVM_SET_IRQCHIP: {
3319 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3320 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3321
f0d66275
DH		 3322 r = -ENOMEM;
3323 if (!chip)
1fe779f8 3324 goto out;
f0d66275
DH		 3325 r = -EFAULT;
3326 if (copy_from_user(chip, argp, sizeof *chip))
3327 goto set_irqchip_out;
1fe779f8
CO		 3328 r = -ENXIO;
3329 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3330 goto set_irqchip_out;
3331 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3332 if (r)
f0d66275 3333 goto set_irqchip_out;
1fe779f8 3334 r = 0;
f0d66275
DH		 3335 set_irqchip_out:
3336 kfree(chip);
3337 if (r)
3338 goto out;
1fe779f8
CO		 3339 break;
3340 }
e0f63cb9 3341 case KVM_GET_PIT: {
e0f63cb9 3342 r = -EFAULT;
f0d66275 3343 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3344 goto out;
3345 r = -ENXIO;
3346 if (!kvm->arch.vpit)
3347 goto out;
f0d66275 3348 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3349 if (r)
3350 goto out;
3351 r = -EFAULT;
f0d66275 3352 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3353 goto out;
3354 r = 0;
3355 break;
3356 }
3357 case KVM_SET_PIT: {
e0f63cb9 3358 r = -EFAULT;
f0d66275 3359 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3360 goto out;
3361 r = -ENXIO;
3362 if (!kvm->arch.vpit)
3363 goto out;
f0d66275 3364 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3365 if (r)
3366 goto out;
3367 r = 0;
3368 break;
3369 }
e9f42757
BK		 3370 case KVM_GET_PIT2: {
3371 r = -ENXIO;
3372 if (!kvm->arch.vpit)
3373 goto out;
3374 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3375 if (r)
3376 goto out;
3377 r = -EFAULT;
3378 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3379 goto out;
3380 r = 0;
3381 break;
3382 }
3383 case KVM_SET_PIT2: {
3384 r = -EFAULT;
3385 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3386 goto out;
3387 r = -ENXIO;
3388 if (!kvm->arch.vpit)
3389 goto out;
3390 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3391 if (r)
3392 goto out;
3393 r = 0;
3394 break;
3395 }
52d939a0
MT		 3396 case KVM_REINJECT_CONTROL: {
3397 struct kvm_reinject_control control;
3398 r = -EFAULT;
3399 if (copy_from_user(&control, argp, sizeof(control)))
3400 goto out;
3401 r = kvm_vm_ioctl_reinject(kvm, &control);
3402 if (r)
3403 goto out;
3404 r = 0;
3405 break;
3406 }
ffde22ac
ES		 3407 case KVM_XEN_HVM_CONFIG: {
3408 r = -EFAULT;
3409 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3410 sizeof(struct kvm_xen_hvm_config)))
3411 goto out;
3412 r = -EINVAL;
3413 if (kvm->arch.xen_hvm_config.flags)
3414 goto out;
3415 r = 0;
3416 break;
3417 }
afbcf7ab 3418 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3419 struct kvm_clock_data user_ns;
3420 u64 now_ns;
3421 s64 delta;
3422
3423 r = -EFAULT;
3424 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3425 goto out;
3426
3427 r = -EINVAL;
3428 if (user_ns.flags)
3429 goto out;
3430
3431 r = 0;
759379dd 3432 now_ns = get_kernel_ns();
afbcf7ab
GC		 3433 delta = user_ns.clock - now_ns;
3434 kvm->arch.kvmclock_offset = delta;
3435 break;
3436 }
3437 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3438 struct kvm_clock_data user_ns;
3439 u64 now_ns;
3440
759379dd 3441 now_ns = get_kernel_ns();
afbcf7ab
GC		 3442 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3443 user_ns.flags = 0;
3444
3445 r = -EFAULT;
3446 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3447 goto out;
3448 r = 0;
3449 break;
3450 }
3451
1fe779f8
CO		 3452 default:
3453 ;
3454 }
3455out:
3456 return r;
3457}
3458
a16b043c 3459static void kvm_init_msr_list(void)
043405e1
CO		 3460{
3461 u32 dummy[2];
3462 unsigned i, j;
3463
e3267cbb
GC		 3464 /* skip the first msrs in the list. KVM-specific */
3465 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3466 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3467 continue;
3468 if (j < i)
3469 msrs_to_save[j] = msrs_to_save[i];
3470 j++;
3471 }
3472 num_msrs_to_save = j;
3473}
3474
bda9020e
MT		 3475static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3476 const void *v)
bbd9b64e 3477{
bda9020e
MT		 3478 if (vcpu->arch.apic &&
3479 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3480 return 0;
bbd9b64e 3481
e93f8a0f 3482 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3483}
3484
bda9020e 3485static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3486{
bda9020e
MT		 3487 if (vcpu->arch.apic &&
3488 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3489 return 0;
bbd9b64e 3490
e93f8a0f 3491 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3492}
3493
2dafc6c2
GN		 3494static void kvm_set_segment(struct kvm_vcpu *vcpu,
3495 struct kvm_segment *var, int seg)
3496{
3497 kvm_x86_ops->set_segment(vcpu, var, seg);
3498}
3499
3500void kvm_get_segment(struct kvm_vcpu *vcpu,
3501 struct kvm_segment *var, int seg)
3502{
3503 kvm_x86_ops->get_segment(vcpu, var, seg);
3504}
3505
c30a358d
JR		 3506static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3507{
3508 return gpa;
3509}
3510
02f59dc9
JR		 3511static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3512{
3513 gpa_t t_gpa;
3514 u32 error;
3515
3516 BUG_ON(!mmu_is_nested(vcpu));
3517
3518 /* NPT walks are always user-walks */
3519 access |= PFERR_USER_MASK;
3520 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &error);
3521 if (t_gpa == UNMAPPED_GVA)
0959ffac 3522 vcpu->arch.fault.nested = true;
02f59dc9
JR		 3523
3524 return t_gpa;
3525}
3526
1871c602
GN		 3527gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3528{
3529 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
14dfe855 3530 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3531}
3532
3533 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3534{
3535 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3536 access |= PFERR_FETCH_MASK;
14dfe855 3537 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3538}
3539
3540gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3541{
3542 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3543 access |= PFERR_WRITE_MASK;
14dfe855 3544 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3545}
3546
3547/* uses this to access any guest's mapped memory without checking CPL */
3548gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3549{
14dfe855 3550 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error);
1871c602
GN		 3551}
3552
3553static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3554 struct kvm_vcpu *vcpu, u32 access,
3555 u32 *error)
bbd9b64e
CO		 3556{
3557 void *data = val;
10589a46 3558 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3559
3560 while (bytes) {
14dfe855
JR		 3561 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3562 error);
bbd9b64e 3563 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3564 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3565 int ret;
3566
10589a46
MT		 3567 if (gpa == UNMAPPED_GVA) {
3568 r = X86EMUL_PROPAGATE_FAULT;
3569 goto out;
3570 }
77c2002e 3571 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3572 if (ret < 0) {
c3cd7ffa 3573 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3574 goto out;
3575 }
bbd9b64e 3576
77c2002e
IE		 3577 bytes -= toread;
3578 data += toread;
3579 addr += toread;
bbd9b64e 3580 }
10589a46 3581out:
10589a46 3582 return r;
bbd9b64e 3583}
77c2002e 3584
1871c602
GN		 3585/* used for instruction fetching */
3586static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3587 struct kvm_vcpu *vcpu, u32 *error)
3588{
3589 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3590 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3591 access | PFERR_FETCH_MASK, error);
3592}
3593
3594static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3595 struct kvm_vcpu *vcpu, u32 *error)
3596{
3597 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3598 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3599 error);
3600}
3601
3602static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3603 struct kvm_vcpu *vcpu, u32 *error)
3604{
3605 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3606}
3607
7972995b 3608static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3609 unsigned int bytes,
7972995b 3610 struct kvm_vcpu *vcpu,
2dafc6c2 3611 u32 *error)
77c2002e
IE		 3612{
3613 void *data = val;
3614 int r = X86EMUL_CONTINUE;
3615
3616 while (bytes) {
14dfe855
JR		 3617 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3618 PFERR_WRITE_MASK,
3619 error);
77c2002e
IE		 3620 unsigned offset = addr & (PAGE_SIZE-1);
3621 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3622 int ret;
3623
3624 if (gpa == UNMAPPED_GVA) {
3625 r = X86EMUL_PROPAGATE_FAULT;
3626 goto out;
3627 }
3628 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3629 if (ret < 0) {
c3cd7ffa 3630 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3631 goto out;
3632 }
3633
3634 bytes -= towrite;
3635 data += towrite;
3636 addr += towrite;
3637 }
3638out:
3639 return r;
3640}
3641
bbd9b64e
CO		 3642static int emulator_read_emulated(unsigned long addr,
3643 void *val,
3644 unsigned int bytes,
8fe681e9 3645 unsigned int *error_code,
bbd9b64e
CO		 3646 struct kvm_vcpu *vcpu)
3647{
bbd9b64e
CO		 3648 gpa_t gpa;
3649
3650 if (vcpu->mmio_read_completed) {
3651 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3652 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3653 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3654 vcpu->mmio_read_completed = 0;
3655 return X86EMUL_CONTINUE;
3656 }
3657
8fe681e9 3658 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3659
8fe681e9 3660 if (gpa == UNMAPPED_GVA)
1871c602 3661 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3662
3663 /* For APIC access vmexit */
3664 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3665 goto mmio;
3666
1871c602 3667 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3668 == X86EMUL_CONTINUE)
bbd9b64e 3669 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3670
3671mmio:
3672 /*
3673 * Is this MMIO handled locally?
3674 */
aec51dc4
AK		 3675 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3676 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3677 return X86EMUL_CONTINUE;
3678 }
aec51dc4
AK		 3679
3680 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3681
3682 vcpu->mmio_needed = 1;
411c35b7
GN		 3683 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3684 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3685 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3686 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3687
c3cd7ffa 3688 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3689}
3690
3200f405 3691int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3692 const void *val, int bytes)
bbd9b64e
CO		 3693{
3694 int ret;
3695
3696 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3697 if (ret < 0)
bbd9b64e 3698 return 0;
ad218f85 3699 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3700 return 1;
3701}
3702
3703static int emulator_write_emulated_onepage(unsigned long addr,
3704 const void *val,
3705 unsigned int bytes,
8fe681e9 3706 unsigned int *error_code,
bbd9b64e
CO		 3707 struct kvm_vcpu *vcpu)
3708{
10589a46
MT		 3709 gpa_t gpa;
3710
8fe681e9 3711 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3712
8fe681e9 3713 if (gpa == UNMAPPED_GVA)
bbd9b64e 3714 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3715
3716 /* For APIC access vmexit */
3717 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3718 goto mmio;
3719
3720 if (emulator_write_phys(vcpu, gpa, val, bytes))
3721 return X86EMUL_CONTINUE;
3722
3723mmio:
aec51dc4 3724 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3725 /*
3726 * Is this MMIO handled locally?
3727 */
bda9020e 3728 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3729 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3730
3731 vcpu->mmio_needed = 1;
411c35b7
GN		 3732 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3733 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3734 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3735 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3736 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3737
3738 return X86EMUL_CONTINUE;
3739}
3740
3741int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3742 const void *val,
3743 unsigned int bytes,
8fe681e9 3744 unsigned int *error_code,
8f6abd06 3745 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3746{
3747 /* Crossing a page boundary? */
3748 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3749 int rc, now;
3750
3751 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3752 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3753 vcpu);
bbd9b64e
CO		 3754 if (rc != X86EMUL_CONTINUE)
3755 return rc;
3756 addr += now;
3757 val += now;
3758 bytes -= now;
3759 }
8fe681e9
GN		 3760 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3761 vcpu);
bbd9b64e 3762}
bbd9b64e 3763
daea3e73
AK		 3764#define CMPXCHG_TYPE(t, ptr, old, new) \
3765 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3766
3767#ifdef CONFIG_X86_64
3768# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3769#else
3770# define CMPXCHG64(ptr, old, new) \
9749a6c0 3771 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3772#endif
3773
bbd9b64e
CO		 3774static int emulator_cmpxchg_emulated(unsigned long addr,
3775 const void *old,
3776 const void *new,
3777 unsigned int bytes,
8fe681e9 3778 unsigned int *error_code,
bbd9b64e
CO		 3779 struct kvm_vcpu *vcpu)
3780{
daea3e73
AK		 3781 gpa_t gpa;
3782 struct page *page;
3783 char *kaddr;
3784 bool exchanged;
2bacc55c 3785
daea3e73
AK		 3786 /* guests cmpxchg8b have to be emulated atomically */
3787 if (bytes > 8 || (bytes & (bytes - 1)))
3788 goto emul_write;
10589a46 3789
daea3e73 3790 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3791
daea3e73
AK		 3792 if (gpa == UNMAPPED_GVA ||
3793 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3794 goto emul_write;
2bacc55c 3795
daea3e73
AK		 3796 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3797 goto emul_write;
72dc67a6 3798
daea3e73 3799 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3800 if (is_error_page(page)) {
3801 kvm_release_page_clean(page);
3802 goto emul_write;
3803 }
72dc67a6 3804
daea3e73
AK		 3805 kaddr = kmap_atomic(page, KM_USER0);
3806 kaddr += offset_in_page(gpa);
3807 switch (bytes) {
3808 case 1:
3809 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3810 break;
3811 case 2:
3812 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3813 break;
3814 case 4:
3815 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3816 break;
3817 case 8:
3818 exchanged = CMPXCHG64(kaddr, old, new);
3819 break;
3820 default:
3821 BUG();
2bacc55c 3822 }
daea3e73
AK		 3823 kunmap_atomic(kaddr, KM_USER0);
3824 kvm_release_page_dirty(page);
3825
3826 if (!exchanged)
3827 return X86EMUL_CMPXCHG_FAILED;
3828
8f6abd06
GN		 3829 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3830
3831 return X86EMUL_CONTINUE;
4a5f48f6 3832
3200f405 3833emul_write:
daea3e73 3834 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3835
8fe681e9 3836 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3837}
3838
cf8f70bf
GN		 3839static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3840{
3841 /* TODO: String I/O for in kernel device */
3842 int r;
3843
3844 if (vcpu->arch.pio.in)
3845 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3846 vcpu->arch.pio.size, pd);
3847 else
3848 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3849 vcpu->arch.pio.port, vcpu->arch.pio.size,
3850 pd);
3851 return r;
3852}
3853
3854
3855static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3856 unsigned int count, struct kvm_vcpu *vcpu)
3857{
7972995b 3858 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3859 goto data_avail;
3860
c41a15dd 3861 trace_kvm_pio(0, port, size, 1);
cf8f70bf
GN		 3862
3863 vcpu->arch.pio.port = port;
3864 vcpu->arch.pio.in = 1;
7972995b 3865 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3866 vcpu->arch.pio.size = size;
3867
3868 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3869 data_avail:
3870 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3871 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3872 return 1;
3873 }
3874
3875 vcpu->run->exit_reason = KVM_EXIT_IO;
3876 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3877 vcpu->run->io.size = size;
3878 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3879 vcpu->run->io.count = count;
3880 vcpu->run->io.port = port;
3881
3882 return 0;
3883}
3884
3885static int emulator_pio_out_emulated(int size, unsigned short port,
3886 const void *val, unsigned int count,
3887 struct kvm_vcpu *vcpu)
3888{
c41a15dd 3889 trace_kvm_pio(1, port, size, 1);
cf8f70bf
GN		 3890
3891 vcpu->arch.pio.port = port;
3892 vcpu->arch.pio.in = 0;
7972995b 3893 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3894 vcpu->arch.pio.size = size;
3895
3896 memcpy(vcpu->arch.pio_data, val, size * count);
3897
3898 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3899 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3900 return 1;
3901 }
3902
3903 vcpu->run->exit_reason = KVM_EXIT_IO;
3904 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3905 vcpu->run->io.size = size;
3906 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3907 vcpu->run->io.count = count;
3908 vcpu->run->io.port = port;
3909
3910 return 0;
3911}
3912
bbd9b64e
CO		 3913static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3914{
3915 return kvm_x86_ops->get_segment_base(vcpu, seg);
3916}
3917
3918int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3919{
a7052897 3920 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3921 return X86EMUL_CONTINUE;
3922}
3923
f5f48ee1
SY		 3924int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3925{
3926 if (!need_emulate_wbinvd(vcpu))
3927 return X86EMUL_CONTINUE;
3928
3929 if (kvm_x86_ops->has_wbinvd_exit()) {
3930 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3931 wbinvd_ipi, NULL, 1);
3932 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3933 }
3934 wbinvd();
3935 return X86EMUL_CONTINUE;
3936}
3937EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3938
bbd9b64e
CO		 3939int emulate_clts(struct kvm_vcpu *vcpu)
3940{
4d4ec087 3941 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3942 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3943 return X86EMUL_CONTINUE;
3944}
3945
35aa5375 3946int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3947{
338dbc97 3948 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3949}
3950
35aa5375 3951int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3952{
338dbc97
GN		 3953
3954 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3955}
3956
52a46617 3957static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3958{
52a46617 3959 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3960}
3961
52a46617 3962static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3963{
52a46617
GN		 3964 unsigned long value;
3965
3966 switch (cr) {
3967 case 0:
3968 value = kvm_read_cr0(vcpu);
3969 break;
3970 case 2:
3971 value = vcpu->arch.cr2;
3972 break;
3973 case 3:
3974 value = vcpu->arch.cr3;
3975 break;
3976 case 4:
3977 value = kvm_read_cr4(vcpu);
3978 break;
3979 case 8:
3980 value = kvm_get_cr8(vcpu);
3981 break;
3982 default:
3983 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3984 return 0;
3985 }
3986
3987 return value;
3988}
3989
0f12244f 3990static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3991{
0f12244f
GN		 3992 int res = 0;
3993
52a46617
GN		 3994 switch (cr) {
3995 case 0:
49a9b07e 3996 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3997 break;
3998 case 2:
3999 vcpu->arch.cr2 = val;
4000 break;
4001 case 3:
2390218b 4002 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4003 break;
4004 case 4:
a83b29c6 4005 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4006 break;
4007 case 8:
0f12244f 4008 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 4009 break;
4010 default:
4011 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4012 res = -1;
52a46617 4013 }
0f12244f
GN		 4014
4015 return res;
52a46617
GN		 4016}
4017
9c537244
GN		 4018static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4019{
4020 return kvm_x86_ops->get_cpl(vcpu);
4021}
4022
2dafc6c2
GN		 4023static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4024{
4025 kvm_x86_ops->get_gdt(vcpu, dt);
4026}
4027
160ce1f1
MG		 4028static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4029{
4030 kvm_x86_ops->get_idt(vcpu, dt);
4031}
4032
5951c442
GN		 4033static unsigned long emulator_get_cached_segment_base(int seg,
4034 struct kvm_vcpu *vcpu)
4035{
4036 return get_segment_base(vcpu, seg);
4037}
4038
2dafc6c2
GN		 4039static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4040 struct kvm_vcpu *vcpu)
4041{
4042 struct kvm_segment var;
4043
4044 kvm_get_segment(vcpu, &var, seg);
4045
4046 if (var.unusable)
4047 return false;
4048
4049 if (var.g)
4050 var.limit >>= 12;
4051 set_desc_limit(desc, var.limit);
4052 set_desc_base(desc, (unsigned long)var.base);
4053 desc->type = var.type;
4054 desc->s = var.s;
4055 desc->dpl = var.dpl;
4056 desc->p = var.present;
4057 desc->avl = var.avl;
4058 desc->l = var.l;
4059 desc->d = var.db;
4060 desc->g = var.g;
4061
4062 return true;
4063}
4064
4065static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4066 struct kvm_vcpu *vcpu)
4067{
4068 struct kvm_segment var;
4069
4070 /* needed to preserve selector */
4071 kvm_get_segment(vcpu, &var, seg);
4072
4073 var.base = get_desc_base(desc);
4074 var.limit = get_desc_limit(desc);
4075 if (desc->g)
4076 var.limit = (var.limit << 12) | 0xfff;
4077 var.type = desc->type;
4078 var.present = desc->p;
4079 var.dpl = desc->dpl;
4080 var.db = desc->d;
4081 var.s = desc->s;
4082 var.l = desc->l;
4083 var.g = desc->g;
4084 var.avl = desc->avl;
4085 var.present = desc->p;
4086 var.unusable = !var.present;
4087 var.padding = 0;
4088
4089 kvm_set_segment(vcpu, &var, seg);
4090 return;
4091}
4092
4093static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4094{
4095 struct kvm_segment kvm_seg;
4096
4097 kvm_get_segment(vcpu, &kvm_seg, seg);
4098 return kvm_seg.selector;
4099}
4100
4101static void emulator_set_segment_selector(u16 sel, int seg,
4102 struct kvm_vcpu *vcpu)
4103{
4104 struct kvm_segment kvm_seg;
4105
4106 kvm_get_segment(vcpu, &kvm_seg, seg);
4107 kvm_seg.selector = sel;
4108 kvm_set_segment(vcpu, &kvm_seg, seg);
4109}
4110
14af3f3c 4111static struct x86_emulate_ops emulate_ops = {
1871c602 4112 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4113 .write_std = kvm_write_guest_virt_system,
1871c602 4114 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4115 .read_emulated = emulator_read_emulated,
4116 .write_emulated = emulator_write_emulated,
4117 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4118 .pio_in_emulated = emulator_pio_in_emulated,
4119 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4120 .get_cached_descriptor = emulator_get_cached_descriptor,
4121 .set_cached_descriptor = emulator_set_cached_descriptor,
4122 .get_segment_selector = emulator_get_segment_selector,
4123 .set_segment_selector = emulator_set_segment_selector,
5951c442 4124 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4125 .get_gdt = emulator_get_gdt,
160ce1f1 4126 .get_idt = emulator_get_idt,
52a46617
GN		 4127 .get_cr = emulator_get_cr,
4128 .set_cr = emulator_set_cr,
9c537244 4129 .cpl = emulator_get_cpl,
35aa5375
GN		 4130 .get_dr = emulator_get_dr,
4131 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4132 .set_msr = kvm_set_msr,
4133 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4134};
4135
5fdbf976
MT		 4136static void cache_all_regs(struct kvm_vcpu *vcpu)
4137{
4138 kvm_register_read(vcpu, VCPU_REGS_RAX);
4139 kvm_register_read(vcpu, VCPU_REGS_RSP);
4140 kvm_register_read(vcpu, VCPU_REGS_RIP);
4141 vcpu->arch.regs_dirty = ~0;
4142}
4143
95cb2295
GN		 4144static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4145{
4146 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4147 /*
4148 * an sti; sti; sequence only disable interrupts for the first
4149 * instruction. So, if the last instruction, be it emulated or
4150 * not, left the system with the INT_STI flag enabled, it
4151 * means that the last instruction is an sti. We should not
4152 * leave the flag on in this case. The same goes for mov ss
4153 */
4154 if (!(int_shadow & mask))
4155 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4156}
4157
54b8486f
GN		 4158static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4159{
4160 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4161 if (ctxt->exception == PF_VECTOR)
d4f8cf66 4162 kvm_propagate_fault(vcpu);
54b8486f
GN		 4163 else if (ctxt->error_code_valid)
4164 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4165 else
4166 kvm_queue_exception(vcpu, ctxt->exception);
4167}
4168
8ec4722d
MG		 4169static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4170{
4171 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4172 int cs_db, cs_l;
4173
4174 cache_all_regs(vcpu);
4175
4176 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4177
4178 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4179 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4180 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4181 vcpu->arch.emulate_ctxt.mode =
4182 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4183 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4184 ? X86EMUL_MODE_VM86 : cs_l
4185 ? X86EMUL_MODE_PROT64 : cs_db
4186 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4187 memset(c, 0, sizeof(struct decode_cache));
4188 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4189}
4190
63995653
MG		 4191int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4192{
4193 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4194 int ret;
4195
4196 init_emulate_ctxt(vcpu);
4197
4198 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4199 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4200 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4201 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4202
4203 if (ret != X86EMUL_CONTINUE)
4204 return EMULATE_FAIL;
4205
4206 vcpu->arch.emulate_ctxt.eip = c->eip;
4207 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4208 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4209 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4210
4211 if (irq == NMI_VECTOR)
4212 vcpu->arch.nmi_pending = false;
4213 else
4214 vcpu->arch.interrupt.pending = false;
4215
4216 return EMULATE_DONE;
4217}
4218EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4219
6d77dbfc
GN		 4220static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4221{
6d77dbfc
GN		 4222 ++vcpu->stat.insn_emulation_fail;
4223 trace_kvm_emulate_insn_failed(vcpu);
4224 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4225 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4226 vcpu->run->internal.ndata = 0;
4227 kvm_queue_exception(vcpu, UD_VECTOR);
4228 return EMULATE_FAIL;
4229}
4230
a6f177ef
GN		 4231static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4232{
4233 gpa_t gpa;
4234
68be0803
GN		 4235 if (tdp_enabled)
4236 return false;
4237
a6f177ef
GN		 4238 /*
4239 * if emulation was due to access to shadowed page table
4240 * and it failed try to unshadow page and re-entetr the
4241 * guest to let CPU execute the instruction.
4242 */
4243 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4244 return true;
4245
4246 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4247
4248 if (gpa == UNMAPPED_GVA)
4249 return true; /* let cpu generate fault */
4250
4251 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4252 return true;
4253
4254 return false;
4255}
4256
bbd9b64e 4257int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4258 unsigned long cr2,
4259 u16 error_code,
571008da 4260 int emulation_type)
bbd9b64e 4261{
95cb2295 4262 int r;
4d2179e1 4263 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4264
26eef70c 4265 kvm_clear_exception_queue(vcpu);
ad312c7c 4266 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4267 /*
56e82318 4268 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4269 * instead of direct ->regs accesses, can save hundred cycles
4270 * on Intel for instructions that don't read/change RSP, for
4271 * for example.
4272 */
4273 cache_all_regs(vcpu);
bbd9b64e 4274
571008da 4275 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4276 init_emulate_ctxt(vcpu);
95cb2295 4277 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4278 vcpu->arch.emulate_ctxt.exception = -1;
4fc40f07 4279 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4280
9aabc88f 4281 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
d47f00a6
JR		 4282 if (r == X86EMUL_PROPAGATE_FAULT)
4283 goto done;
4284
e46479f8 4285 trace_kvm_emulate_insn_start(vcpu);
571008da 4286
0cb5762e
AP		 4287 /* Only allow emulation of specific instructions on #UD
4288 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4289 if (emulation_type & EMULTYPE_TRAP_UD) {
4290 if (!c->twobyte)
4291 return EMULATE_FAIL;
4292 switch (c->b) {
4293 case 0x01: /* VMMCALL */
4294 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4295 return EMULATE_FAIL;
4296 break;
4297 case 0x34: /* sysenter */
4298 case 0x35: /* sysexit */
4299 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4300 return EMULATE_FAIL;
4301 break;
4302 case 0x05: /* syscall */
4303 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4304 return EMULATE_FAIL;
4305 break;
4306 default:
4307 return EMULATE_FAIL;
4308 }
4309
4310 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4311 return EMULATE_FAIL;
4312 }
571008da 4313
f2b5756b 4314 ++vcpu->stat.insn_emulation;
bbd9b64e 4315 if (r) {
a6f177ef 4316 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4317 return EMULATE_DONE;
6d77dbfc
GN		 4318 if (emulation_type & EMULTYPE_SKIP)
4319 return EMULATE_FAIL;
4320 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4321 }
4322 }
4323
ba8afb6b
GN		 4324 if (emulation_type & EMULTYPE_SKIP) {
4325 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4326 return EMULATE_DONE;
4327 }
4328
4d2179e1
GN		 4329 /* this is needed for vmware backdor interface to work since it
4330 changes registers values during IO operation */
4331 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4332
5cd21917 4333restart:
9aabc88f 4334 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4335
d2ddd1c4 4336 if (r == EMULATION_FAILED) {
a6f177ef 4337 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4338 return EMULATE_DONE;
4339
6d77dbfc 4340 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4341 }
4342
d47f00a6 4343done:
d2ddd1c4 4344 if (vcpu->arch.emulate_ctxt.exception >= 0) {
54b8486f 4345 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4346 r = EMULATE_DONE;
4347 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4348 if (!vcpu->arch.pio.in)
4349 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4350 r = EMULATE_DO_MMIO;
4351 } else if (vcpu->mmio_needed) {
3457e419
GN		 4352 if (vcpu->mmio_is_write)
4353 vcpu->mmio_needed = 0;
e85d28f8 4354 r = EMULATE_DO_MMIO;
d2ddd1c4 4355 } else if (r == EMULATION_RESTART)
5cd21917 4356 goto restart;
d2ddd1c4
GN		 4357 else
4358 r = EMULATE_DONE;
f850e2e6 4359
e85d28f8
GN		 4360 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4361 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4362 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4363 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4364 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4365
4366 return r;
de7d789a 4367}
bbd9b64e 4368EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4369
cf8f70bf 4370int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4371{
cf8f70bf
GN		 4372 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4373 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4374 /* do not return to emulator after return from userspace */
7972995b 4375 vcpu->arch.pio.count = 0;
de7d789a
CO		 4376 return ret;
4377}
cf8f70bf 4378EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4379
8cfdc000
ZA		 4380static void tsc_bad(void *info)
4381{
4382 __get_cpu_var(cpu_tsc_khz) = 0;
4383}
4384
4385static void tsc_khz_changed(void *data)
c8076604 4386{
8cfdc000
ZA		 4387 struct cpufreq_freqs *freq = data;
4388 unsigned long khz = 0;
4389
4390 if (data)
4391 khz = freq->new;
4392 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4393 khz = cpufreq_quick_get(raw_smp_processor_id());
4394 if (!khz)
4395 khz = tsc_khz;
4396 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4397}
4398
c8076604
GH		 4399static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4400 void *data)
4401{
4402 struct cpufreq_freqs *freq = data;
4403 struct kvm *kvm;
4404 struct kvm_vcpu *vcpu;
4405 int i, send_ipi = 0;
4406
8cfdc000
ZA		 4407 /*
4408 * We allow guests to temporarily run on slowing clocks,
4409 * provided we notify them after, or to run on accelerating
4410 * clocks, provided we notify them before. Thus time never
4411 * goes backwards.
4412 *
4413 * However, we have a problem. We can't atomically update
4414 * the frequency of a given CPU from this function; it is
4415 * merely a notifier, which can be called from any CPU.
4416 * Changing the TSC frequency at arbitrary points in time
4417 * requires a recomputation of local variables related to
4418 * the TSC for each VCPU. We must flag these local variables
4419 * to be updated and be sure the update takes place with the
4420 * new frequency before any guests proceed.
4421 *
4422 * Unfortunately, the combination of hotplug CPU and frequency
4423 * change creates an intractable locking scenario; the order
4424 * of when these callouts happen is undefined with respect to
4425 * CPU hotplug, and they can race with each other. As such,
4426 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4427 * undefined; you can actually have a CPU frequency change take
4428 * place in between the computation of X and the setting of the
4429 * variable. To protect against this problem, all updates of
4430 * the per_cpu tsc_khz variable are done in an interrupt
4431 * protected IPI, and all callers wishing to update the value
4432 * must wait for a synchronous IPI to complete (which is trivial
4433 * if the caller is on the CPU already). This establishes the
4434 * necessary total order on variable updates.
4435 *
4436 * Note that because a guest time update may take place
4437 * anytime after the setting of the VCPU's request bit, the
4438 * correct TSC value must be set before the request. However,
4439 * to ensure the update actually makes it to any guest which
4440 * starts running in hardware virtualization between the set
4441 * and the acquisition of the spinlock, we must also ping the
4442 * CPU after setting the request bit.
4443 *
4444 */
4445
c8076604
GH		 4446 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4447 return 0;
4448 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4449 return 0;
8cfdc000
ZA		 4450
4451 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4452
4453 spin_lock(&kvm_lock);
4454 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4455 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4456 if (vcpu->cpu != freq->cpu)
4457 continue;
4458 if (!kvm_request_guest_time_update(vcpu))
4459 continue;
4460 if (vcpu->cpu != smp_processor_id())
8cfdc000 4461 send_ipi = 1;
c8076604
GH		 4462 }
4463 }
4464 spin_unlock(&kvm_lock);
4465
4466 if (freq->old < freq->new && send_ipi) {
4467 /*
4468 * We upscale the frequency. Must make the guest
4469 * doesn't see old kvmclock values while running with
4470 * the new frequency, otherwise we risk the guest sees
4471 * time go backwards.
4472 *
4473 * In case we update the frequency for another cpu
4474 * (which might be in guest context) send an interrupt
4475 * to kick the cpu out of guest context. Next time
4476 * guest context is entered kvmclock will be updated,
4477 * so the guest will not see stale values.
4478 */
8cfdc000 4479 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4480 }
4481 return 0;
4482}
4483
4484static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4485 .notifier_call = kvmclock_cpufreq_notifier
4486};
4487
4488static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4489 unsigned long action, void *hcpu)
4490{
4491 unsigned int cpu = (unsigned long)hcpu;
4492
4493 switch (action) {
4494 case CPU_ONLINE:
4495 case CPU_DOWN_FAILED:
4496 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4497 break;
4498 case CPU_DOWN_PREPARE:
4499 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4500 break;
4501 }
4502 return NOTIFY_OK;
4503}
4504
4505static struct notifier_block kvmclock_cpu_notifier_block = {
4506 .notifier_call = kvmclock_cpu_notifier,
4507 .priority = -INT_MAX
c8076604
GH		 4508};
4509
b820cc0c
ZA		 4510static void kvm_timer_init(void)
4511{
4512 int cpu;
4513
8cfdc000 4514 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4515 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4516 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4517 CPUFREQ_TRANSITION_NOTIFIER);
4518 }
8cfdc000
ZA		 4519 for_each_online_cpu(cpu)
4520 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4521}
4522
ff9d07a0
ZY		 4523static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4524
4525static int kvm_is_in_guest(void)
4526{
4527 return percpu_read(current_vcpu) != NULL;
4528}
4529
4530static int kvm_is_user_mode(void)
4531{
4532 int user_mode = 3;
dcf46b94 4533
ff9d07a0
ZY		 4534 if (percpu_read(current_vcpu))
4535 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4536
ff9d07a0
ZY		 4537 return user_mode != 0;
4538}
4539
4540static unsigned long kvm_get_guest_ip(void)
4541{
4542 unsigned long ip = 0;
dcf46b94 4543
ff9d07a0
ZY		 4544 if (percpu_read(current_vcpu))
4545 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4546
ff9d07a0
ZY		 4547 return ip;
4548}
4549
4550static struct perf_guest_info_callbacks kvm_guest_cbs = {
4551 .is_in_guest = kvm_is_in_guest,
4552 .is_user_mode = kvm_is_user_mode,
4553 .get_guest_ip = kvm_get_guest_ip,
4554};
4555
4556void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4557{
4558 percpu_write(current_vcpu, vcpu);
4559}
4560EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4561
4562void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4563{
4564 percpu_write(current_vcpu, NULL);
4565}
4566EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4567
f8c16bba 4568int kvm_arch_init(void *opaque)
043405e1 4569{
b820cc0c 4570 int r;
f8c16bba
ZX		 4571 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4572
f8c16bba
ZX		 4573 if (kvm_x86_ops) {
4574 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4575 r = -EEXIST;
4576 goto out;
f8c16bba
ZX		 4577 }
4578
4579 if (!ops->cpu_has_kvm_support()) {
4580 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4581 r = -EOPNOTSUPP;
4582 goto out;
f8c16bba
ZX		 4583 }
4584 if (ops->disabled_by_bios()) {
4585 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4586 r = -EOPNOTSUPP;
4587 goto out;
f8c16bba
ZX		 4588 }
4589
97db56ce
AK		 4590 r = kvm_mmu_module_init();
4591 if (r)
4592 goto out;
4593
4594 kvm_init_msr_list();
4595
f8c16bba 4596 kvm_x86_ops = ops;
56c6d28a 4597 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4598 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4599 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4600 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4601
b820cc0c 4602 kvm_timer_init();
c8076604 4603
ff9d07a0
ZY		 4604 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4605
2acf923e
DC		 4606 if (cpu_has_xsave)
4607 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4608
f8c16bba 4609 return 0;
56c6d28a
ZX		 4610
4611out:
56c6d28a 4612 return r;
043405e1 4613}
8776e519 4614
f8c16bba
ZX		 4615void kvm_arch_exit(void)
4616{
ff9d07a0
ZY		 4617 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4618
888d256e
JK		 4619 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4620 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4621 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4622 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4623 kvm_x86_ops = NULL;
56c6d28a
ZX		 4624 kvm_mmu_module_exit();
4625}
f8c16bba 4626
8776e519
HB		 4627int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4628{
4629 ++vcpu->stat.halt_exits;
4630 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4631 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4632 return 1;
4633 } else {
4634 vcpu->run->exit_reason = KVM_EXIT_HLT;
4635 return 0;
4636 }
4637}
4638EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4639
2f333bcb
MT		 4640static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4641 unsigned long a1)
4642{
4643 if (is_long_mode(vcpu))
4644 return a0;
4645 else
4646 return a0 | ((gpa_t)a1 << 32);
4647}
4648
55cd8e5a
GN		 4649int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4650{
4651 u64 param, ingpa, outgpa, ret;
4652 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4653 bool fast, longmode;
4654 int cs_db, cs_l;
4655
4656 /*
4657 * hypercall generates UD from non zero cpl and real mode
4658 * per HYPER-V spec
4659 */
3eeb3288 4660 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4661 kvm_queue_exception(vcpu, UD_VECTOR);
4662 return 0;
4663 }
4664
4665 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4666 longmode = is_long_mode(vcpu) && cs_l == 1;
4667
4668 if (!longmode) {
ccd46936
GN		 4669 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4670 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4671 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4672 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4673 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4674 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4675 }
4676#ifdef CONFIG_X86_64
4677 else {
4678 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4679 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4680 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4681 }
4682#endif
4683
4684 code = param & 0xffff;
4685 fast = (param >> 16) & 0x1;
4686 rep_cnt = (param >> 32) & 0xfff;
4687 rep_idx = (param >> 48) & 0xfff;
4688
4689 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4690
c25bc163
GN		 4691 switch (code) {
4692 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4693 kvm_vcpu_on_spin(vcpu);
4694 break;
4695 default:
4696 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4697 break;
4698 }
55cd8e5a
GN		 4699
4700 ret = res | (((u64)rep_done & 0xfff) << 32);
4701 if (longmode) {
4702 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4703 } else {
4704 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4705 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4706 }
4707
4708 return 1;
4709}
4710
8776e519
HB		 4711int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4712{
4713 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4714 int r = 1;
8776e519 4715
55cd8e5a
GN		 4716 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4717 return kvm_hv_hypercall(vcpu);
4718
5fdbf976
MT		 4719 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4720 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4721 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4722 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4723 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4724
229456fc 4725 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4726
8776e519
HB		 4727 if (!is_long_mode(vcpu)) {
4728 nr &= 0xFFFFFFFF;
4729 a0 &= 0xFFFFFFFF;
4730 a1 &= 0xFFFFFFFF;
4731 a2 &= 0xFFFFFFFF;
4732 a3 &= 0xFFFFFFFF;
4733 }
4734
07708c4a
JK		 4735 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4736 ret = -KVM_EPERM;
4737 goto out;
4738 }
4739
8776e519 4740 switch (nr) {
b93463aa
AK		 4741 case KVM_HC_VAPIC_POLL_IRQ:
4742 ret = 0;
4743 break;
2f333bcb
MT		 4744 case KVM_HC_MMU_OP:
4745 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4746 break;
8776e519
HB		 4747 default:
4748 ret = -KVM_ENOSYS;
4749 break;
4750 }
07708c4a 4751out:
5fdbf976 4752 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4753 ++vcpu->stat.hypercalls;
2f333bcb 4754 return r;
8776e519
HB		 4755}
4756EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4757
4758int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4759{
4760 char instruction[3];
5fdbf976 4761 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4762
8776e519
HB		 4763 /*
4764 * Blow out the MMU to ensure that no other VCPU has an active mapping
4765 * to ensure that the updated hypercall appears atomically across all
4766 * VCPUs.
4767 */
4768 kvm_mmu_zap_all(vcpu->kvm);
4769
8776e519 4770 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4771
8fe681e9 4772 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4773}
4774
8776e519
HB		 4775void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4776{
89a27f4d 4777 struct desc_ptr dt = { limit, base };
8776e519
HB		 4778
4779 kvm_x86_ops->set_gdt(vcpu, &dt);
4780}
4781
4782void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4783{
89a27f4d 4784 struct desc_ptr dt = { limit, base };
8776e519
HB		 4785
4786 kvm_x86_ops->set_idt(vcpu, &dt);
4787}
4788
07716717
DK		 4789static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4790{
ad312c7c
ZX		 4791 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4792 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4793
4794 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4795 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4796 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4797 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4798 if (ej->function == e->function) {
4799 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4800 return j;
4801 }
4802 }
4803 return 0; /* silence gcc, even though control never reaches here */
4804}
4805
4806/* find an entry with matching function, matching index (if needed), and that
4807 * should be read next (if it's stateful) */
4808static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4809 u32 function, u32 index)
4810{
4811 if (e->function != function)
4812 return 0;
4813 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4814 return 0;
4815 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4816 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4817 return 0;
4818 return 1;
4819}
4820
d8017474
AG		 4821struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4822 u32 function, u32 index)
8776e519
HB		 4823{
4824 int i;
d8017474 4825 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4826
ad312c7c 4827 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4828 struct kvm_cpuid_entry2 *e;
4829
ad312c7c 4830 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4831 if (is_matching_cpuid_entry(e, function, index)) {
4832 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4833 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4834 best = e;
4835 break;
4836 }
4837 /*
4838 * Both basic or both extended?
4839 */
4840 if (((e->function ^ function) & 0x80000000) == 0)
4841 if (!best || e->function > best->function)
4842 best = e;
4843 }
d8017474
AG		 4844 return best;
4845}
0e851880 4846EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4847
82725b20
DE		 4848int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4849{
4850 struct kvm_cpuid_entry2 *best;
4851
f7a71197
AK		 4852 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4853 if (!best || best->eax < 0x80000008)
4854 goto not_found;
82725b20
DE		 4855 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4856 if (best)
4857 return best->eax & 0xff;
f7a71197 4858not_found:
82725b20
DE		 4859 return 36;
4860}
4861
d8017474
AG		 4862void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4863{
4864 u32 function, index;
4865 struct kvm_cpuid_entry2 *best;
4866
4867 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4868 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4869 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4870 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4871 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4872 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4873 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4874 if (best) {
5fdbf976
MT		 4875 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4876 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4877 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4878 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4879 }
8776e519 4880 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4881 trace_kvm_cpuid(function,
4882 kvm_register_read(vcpu, VCPU_REGS_RAX),
4883 kvm_register_read(vcpu, VCPU_REGS_RBX),
4884 kvm_register_read(vcpu, VCPU_REGS_RCX),
4885 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4886}
4887EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4888
b6c7a5dc
HB		 4889/*
4890 * Check if userspace requested an interrupt window, and that the
4891 * interrupt window is open.
4892 *
4893 * No need to exit to userspace if we already have an interrupt queued.
4894 */
851ba692 4895static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4896{
8061823a 4897 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4898 vcpu->run->request_interrupt_window &&
5df56646 4899 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4900}
4901
851ba692 4902static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4903{
851ba692
AK		 4904 struct kvm_run *kvm_run = vcpu->run;
4905
91586a3b 4906 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4907 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4908 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4909 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4910 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4911 else
b6c7a5dc 4912 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4913 kvm_arch_interrupt_allowed(vcpu) &&
4914 !kvm_cpu_has_interrupt(vcpu) &&
4915 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4916}
4917
b93463aa
AK		 4918static void vapic_enter(struct kvm_vcpu *vcpu)
4919{
4920 struct kvm_lapic *apic = vcpu->arch.apic;
4921 struct page *page;
4922
4923 if (!apic || !apic->vapic_addr)
4924 return;
4925
4926 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4927
4928 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4929}
4930
4931static void vapic_exit(struct kvm_vcpu *vcpu)
4932{
4933 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4934 int idx;
b93463aa
AK		 4935
4936 if (!apic || !apic->vapic_addr)
4937 return;
4938
f656ce01 4939 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4940 kvm_release_page_dirty(apic->vapic_page);
4941 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4942 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4943}
4944
95ba8273
GN		 4945static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4946{
4947 int max_irr, tpr;
4948
4949 if (!kvm_x86_ops->update_cr8_intercept)
4950 return;
4951
88c808fd
AK		 4952 if (!vcpu->arch.apic)
4953 return;
4954
8db3baa2
GN		 4955 if (!vcpu->arch.apic->vapic_addr)
4956 max_irr = kvm_lapic_find_highest_irr(vcpu);
4957 else
4958 max_irr = -1;
95ba8273
GN		 4959
4960 if (max_irr != -1)
4961 max_irr >>= 4;
4962
4963 tpr = kvm_lapic_get_cr8(vcpu);
4964
4965 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4966}
4967
851ba692 4968static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4969{
4970 /* try to reinject previous events if any */
b59bb7bd 4971 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4972 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4973 vcpu->arch.exception.has_error_code,
4974 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4975 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4976 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4977 vcpu->arch.exception.error_code,
4978 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4979 return;
4980 }
4981
95ba8273
GN		 4982 if (vcpu->arch.nmi_injected) {
4983 kvm_x86_ops->set_nmi(vcpu);
4984 return;
4985 }
4986
4987 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4988 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4989 return;
4990 }
4991
4992 /* try to inject new event if pending */
4993 if (vcpu->arch.nmi_pending) {
4994 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4995 vcpu->arch.nmi_pending = false;
4996 vcpu->arch.nmi_injected = true;
4997 kvm_x86_ops->set_nmi(vcpu);
4998 }
4999 } else if (kvm_cpu_has_interrupt(vcpu)) {
5000 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5001 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5002 false);
5003 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5004 }
5005 }
5006}
5007
2acf923e
DC		 5008static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5009{
5010 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5011 !vcpu->guest_xcr0_loaded) {
5012 /* kvm_set_xcr() also depends on this */
5013 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5014 vcpu->guest_xcr0_loaded = 1;
5015 }
5016}
5017
5018static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5019{
5020 if (vcpu->guest_xcr0_loaded) {
5021 if (vcpu->arch.xcr0 != host_xcr0)
5022 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5023 vcpu->guest_xcr0_loaded = 0;
5024 }
5025}
5026
851ba692 5027static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5028{
5029 int r;
6a8b1d13 5030 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5031 vcpu->run->request_interrupt_window;
b6c7a5dc 5032
3e007509 5033 if (vcpu->requests) {
a8eeb04a 5034 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5035 kvm_mmu_unload(vcpu);
a8eeb04a 5036 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5037 __kvm_migrate_timers(vcpu);
8cfdc000
ZA		 5038 if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu)) {
5039 r = kvm_write_guest_time(vcpu);
5040 if (unlikely(r))
5041 goto out;
5042 }
a8eeb04a 5043 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5044 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5045 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5046 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5047 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5048 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5049 r = 0;
5050 goto out;
5051 }
a8eeb04a 5052 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5053 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5054 r = 0;
5055 goto out;
5056 }
a8eeb04a 5057 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5058 vcpu->fpu_active = 0;
5059 kvm_x86_ops->fpu_deactivate(vcpu);
5060 }
2f52d58c 5061 }
b93463aa 5062
3e007509
AK		 5063 r = kvm_mmu_reload(vcpu);
5064 if (unlikely(r))
5065 goto out;
5066
b463a6f7
AK		 5067 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5068 inject_pending_event(vcpu);
5069
5070 /* enable NMI/IRQ window open exits if needed */
5071 if (vcpu->arch.nmi_pending)
5072 kvm_x86_ops->enable_nmi_window(vcpu);
5073 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5074 kvm_x86_ops->enable_irq_window(vcpu);
5075
5076 if (kvm_lapic_enabled(vcpu)) {
5077 update_cr8_intercept(vcpu);
5078 kvm_lapic_sync_to_vapic(vcpu);
5079 }
5080 }
5081
b6c7a5dc
HB		 5082 preempt_disable();
5083
5084 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5085 if (vcpu->fpu_active)
5086 kvm_load_guest_fpu(vcpu);
2acf923e 5087 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5088
d94e1dc9
AK		 5089 atomic_set(&vcpu->guest_mode, 1);
5090 smp_wmb();
b6c7a5dc 5091
d94e1dc9 5092 local_irq_disable();
32f88400 5093
d94e1dc9
AK		 5094 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5095 || need_resched() || signal_pending(current)) {
5096 atomic_set(&vcpu->guest_mode, 0);
5097 smp_wmb();
6c142801
AK		 5098 local_irq_enable();
5099 preempt_enable();
b463a6f7 5100 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5101 r = 1;
5102 goto out;
5103 }
5104
f656ce01 5105 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5106
b6c7a5dc
HB		 5107 kvm_guest_enter();
5108
42dbaa5a 5109 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5110 set_debugreg(0, 7);
5111 set_debugreg(vcpu->arch.eff_db[0], 0);
5112 set_debugreg(vcpu->arch.eff_db[1], 1);
5113 set_debugreg(vcpu->arch.eff_db[2], 2);
5114 set_debugreg(vcpu->arch.eff_db[3], 3);
5115 }
b6c7a5dc 5116
229456fc 5117 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5118 kvm_x86_ops->run(vcpu);
b6c7a5dc 5119
24f1e32c
FW		 5120 /*
5121 * If the guest has used debug registers, at least dr7
5122 * will be disabled while returning to the host.
5123 * If we don't have active breakpoints in the host, we don't
5124 * care about the messed up debug address registers. But if
5125 * we have some of them active, restore the old state.
5126 */
59d8eb53 5127 if (hw_breakpoint_active())
24f1e32c 5128 hw_breakpoint_restore();
42dbaa5a 5129
1d5f066e
ZA		 5130 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5131
d94e1dc9
AK		 5132 atomic_set(&vcpu->guest_mode, 0);
5133 smp_wmb();
b6c7a5dc
HB		 5134 local_irq_enable();
5135
5136 ++vcpu->stat.exits;
5137
5138 /*
5139 * We must have an instruction between local_irq_enable() and
5140 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5141 * the interrupt shadow. The stat.exits increment will do nicely.
5142 * But we need to prevent reordering, hence this barrier():
5143 */
5144 barrier();
5145
5146 kvm_guest_exit();
5147
5148 preempt_enable();
5149
f656ce01 5150 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5151
b6c7a5dc
HB		 5152 /*
5153 * Profile KVM exit RIPs:
5154 */
5155 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5156 unsigned long rip = kvm_rip_read(vcpu);
5157 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5158 }
5159
298101da 5160
b93463aa
AK		 5161 kvm_lapic_sync_from_vapic(vcpu);
5162
851ba692 5163 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5164out:
5165 return r;
5166}
b6c7a5dc 5167
09cec754 5168
851ba692 5169static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5170{
5171 int r;
f656ce01 5172 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5173
5174 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5175 pr_debug("vcpu %d received sipi with vector # %x\n",
5176 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5177 kvm_lapic_reset(vcpu);
5f179287 5178 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5179 if (r)
5180 return r;
5181 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5182 }
5183
f656ce01 5184 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5185 vapic_enter(vcpu);
5186
5187 r = 1;
5188 while (r > 0) {
af2152f5 5189 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 5190 r = vcpu_enter_guest(vcpu);
d7690175 5191 else {
f656ce01 5192 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5193 kvm_vcpu_block(vcpu);
f656ce01 5194 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5195 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5196 {
5197 switch(vcpu->arch.mp_state) {
5198 case KVM_MP_STATE_HALTED:
d7690175 5199 vcpu->arch.mp_state =
09cec754
GN		 5200 KVM_MP_STATE_RUNNABLE;
5201 case KVM_MP_STATE_RUNNABLE:
5202 break;
5203 case KVM_MP_STATE_SIPI_RECEIVED:
5204 default:
5205 r = -EINTR;
5206 break;
5207 }
5208 }
d7690175
MT		 5209 }
5210
09cec754
GN		 5211 if (r <= 0)
5212 break;
5213
5214 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5215 if (kvm_cpu_has_pending_timer(vcpu))
5216 kvm_inject_pending_timer_irqs(vcpu);
5217
851ba692 5218 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5219 r = -EINTR;
851ba692 5220 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5221 ++vcpu->stat.request_irq_exits;
5222 }
5223 if (signal_pending(current)) {
5224 r = -EINTR;
851ba692 5225 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5226 ++vcpu->stat.signal_exits;
5227 }
5228 if (need_resched()) {
f656ce01 5229 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5230 kvm_resched(vcpu);
f656ce01 5231 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5232 }
b6c7a5dc
HB		 5233 }
5234
f656ce01 5235 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5236
b93463aa
AK		 5237 vapic_exit(vcpu);
5238
b6c7a5dc
HB		 5239 return r;
5240}
5241
5242int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5243{
5244 int r;
5245 sigset_t sigsaved;
5246
ac9f6dc0
AK		 5247 if (vcpu->sigset_active)
5248 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5249
a4535290 5250 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5251 kvm_vcpu_block(vcpu);
d7690175 5252 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5253 r = -EAGAIN;
5254 goto out;
b6c7a5dc
HB		 5255 }
5256
b6c7a5dc
HB		 5257 /* re-sync apic's tpr */
5258 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5259 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5260
d2ddd1c4 5261 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5262 if (vcpu->mmio_needed) {
5263 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5264 vcpu->mmio_read_completed = 1;
5265 vcpu->mmio_needed = 0;
b6c7a5dc 5266 }
f656ce01 5267 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5268 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5269 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5270 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5271 r = 0;
5272 goto out;
5273 }
5274 }
5fdbf976
MT		 5275 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5276 kvm_register_write(vcpu, VCPU_REGS_RAX,
5277 kvm_run->hypercall.ret);
b6c7a5dc 5278
851ba692 5279 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5280
5281out:
f1d86e46 5282 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5283 if (vcpu->sigset_active)
5284 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5285
b6c7a5dc
HB		 5286 return r;
5287}
5288
5289int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5290{
5fdbf976
MT		 5291 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5292 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5293 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5294 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5295 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5296 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5297 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5298 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5299#ifdef CONFIG_X86_64
5fdbf976
MT		 5300 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5301 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5302 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5303 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5304 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5305 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5306 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5307 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5308#endif
5309
5fdbf976 5310 regs->rip = kvm_rip_read(vcpu);
91586a3b 5311 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5312
b6c7a5dc
HB		 5313 return 0;
5314}
5315
5316int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5317{
5fdbf976
MT		 5318 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5319 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5320 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5321 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5322 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5323 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5324 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5325 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5326#ifdef CONFIG_X86_64
5fdbf976
MT		 5327 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5328 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5329 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5330 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5331 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5332 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5333 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5334 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5335#endif
5336
5fdbf976 5337 kvm_rip_write(vcpu, regs->rip);
91586a3b 5338 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5339
b4f14abd
JK		 5340 vcpu->arch.exception.pending = false;
5341
3842d135
AK		 5342 kvm_make_request(KVM_REQ_EVENT, vcpu);
5343
b6c7a5dc
HB		 5344 return 0;
5345}
5346
b6c7a5dc
HB		 5347void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5348{
5349 struct kvm_segment cs;
5350
3e6e0aab 5351 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5352 *db = cs.db;
5353 *l = cs.l;
5354}
5355EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5356
5357int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5358 struct kvm_sregs *sregs)
5359{
89a27f4d 5360 struct desc_ptr dt;
b6c7a5dc 5361
3e6e0aab
GT		 5362 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5363 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5364 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5365 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5366 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5367 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5368
3e6e0aab
GT		 5369 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5370 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5371
5372 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5373 sregs->idt.limit = dt.size;
5374 sregs->idt.base = dt.address;
b6c7a5dc 5375 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5376 sregs->gdt.limit = dt.size;
5377 sregs->gdt.base = dt.address;
b6c7a5dc 5378
4d4ec087 5379 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5380 sregs->cr2 = vcpu->arch.cr2;
5381 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5382 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5383 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5384 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5385 sregs->apic_base = kvm_get_apic_base(vcpu);
5386
923c61bb 5387 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5388
36752c9b 5389 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5390 set_bit(vcpu->arch.interrupt.nr,
5391 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5392
b6c7a5dc
HB		 5393 return 0;
5394}
5395
62d9f0db
MT		 5396int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5397 struct kvm_mp_state *mp_state)
5398{
62d9f0db 5399 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5400 return 0;
5401}
5402
5403int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5404 struct kvm_mp_state *mp_state)
5405{
62d9f0db 5406 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5407 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5408 return 0;
5409}
5410
e269fb21
JK		 5411int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5412 bool has_error_code, u32 error_code)
b6c7a5dc 5413{
4d2179e1 5414 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5415 int ret;
e01c2426 5416
8ec4722d 5417 init_emulate_ctxt(vcpu);
c697518a 5418
9aabc88f 5419 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5420 tss_selector, reason, has_error_code,
5421 error_code);
c697518a 5422
c697518a 5423 if (ret)
19d04437 5424 return EMULATE_FAIL;
37817f29 5425
4d2179e1 5426 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5427 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437 5428 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5429 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5430 return EMULATE_DONE;
37817f29
IE		 5431}
5432EXPORT_SYMBOL_GPL(kvm_task_switch);
5433
b6c7a5dc
HB		 5434int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5435 struct kvm_sregs *sregs)
5436{
5437 int mmu_reset_needed = 0;
923c61bb 5438 int pending_vec, max_bits;
89a27f4d 5439 struct desc_ptr dt;
b6c7a5dc 5440
89a27f4d
GN		 5441 dt.size = sregs->idt.limit;
5442 dt.address = sregs->idt.base;
b6c7a5dc 5443 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5444 dt.size = sregs->gdt.limit;
5445 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5446 kvm_x86_ops->set_gdt(vcpu, &dt);
5447
ad312c7c
ZX		 5448 vcpu->arch.cr2 = sregs->cr2;
5449 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5450 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5451
2d3ad1f4 5452 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5453
f6801dff 5454 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5455 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5456 kvm_set_apic_base(vcpu, sregs->apic_base);
5457
4d4ec087 5458 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5459 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5460 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5461
fc78f519 5462 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5463 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5464 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ff03a073 5465 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
7c93be44
MT		 5466 mmu_reset_needed = 1;
5467 }
b6c7a5dc
HB		 5468
5469 if (mmu_reset_needed)
5470 kvm_mmu_reset_context(vcpu);
5471
923c61bb
GN		 5472 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5473 pending_vec = find_first_bit(
5474 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5475 if (pending_vec < max_bits) {
66fd3f7f 5476 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5477 pr_debug("Set back pending irq %d\n", pending_vec);
5478 if (irqchip_in_kernel(vcpu->kvm))
5479 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5480 }
5481
3e6e0aab
GT		 5482 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5483 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5484 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5485 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5486 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5487 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5488
3e6e0aab
GT		 5489 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5490 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5491
5f0269f5
ME		 5492 update_cr8_intercept(vcpu);
5493
9c3e4aab 5494 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5495 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5496 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5497 !is_protmode(vcpu))
9c3e4aab
MT		 5498 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5499
3842d135
AK		 5500 kvm_make_request(KVM_REQ_EVENT, vcpu);
5501
b6c7a5dc
HB		 5502 return 0;
5503}
5504
d0bfb940
JK		 5505int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5506 struct kvm_guest_debug *dbg)
b6c7a5dc 5507{
355be0b9 5508 unsigned long rflags;
ae675ef0 5509 int i, r;
b6c7a5dc 5510
4f926bf2
JK		 5511 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5512 r = -EBUSY;
5513 if (vcpu->arch.exception.pending)
2122ff5e 5514 goto out;
4f926bf2
JK		 5515 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5516 kvm_queue_exception(vcpu, DB_VECTOR);
5517 else
5518 kvm_queue_exception(vcpu, BP_VECTOR);
5519 }
5520
91586a3b
JK		 5521 /*
5522 * Read rflags as long as potentially injected trace flags are still
5523 * filtered out.
5524 */
5525 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5526
5527 vcpu->guest_debug = dbg->control;
5528 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5529 vcpu->guest_debug = 0;
5530
5531 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5532 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5533 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5534 vcpu->arch.switch_db_regs =
5535 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5536 } else {
5537 for (i = 0; i < KVM_NR_DB_REGS; i++)
5538 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5539 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5540 }
5541
f92653ee
JK		 5542 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5543 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5544 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5545
91586a3b
JK		 5546 /*
5547 * Trigger an rflags update that will inject or remove the trace
5548 * flags.
5549 */
5550 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5551
355be0b9 5552 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5553
4f926bf2 5554 r = 0;
d0bfb940 5555
2122ff5e 5556out:
b6c7a5dc
HB		 5557
5558 return r;
5559}
5560
8b006791
ZX		 5561/*
5562 * Translate a guest virtual address to a guest physical address.
5563 */
5564int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5565 struct kvm_translation *tr)
5566{
5567 unsigned long vaddr = tr->linear_address;
5568 gpa_t gpa;
f656ce01 5569 int idx;
8b006791 5570
f656ce01 5571 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5572 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5573 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5574 tr->physical_address = gpa;
5575 tr->valid = gpa != UNMAPPED_GVA;
5576 tr->writeable = 1;
5577 tr->usermode = 0;
8b006791
ZX		 5578
5579 return 0;
5580}
5581
d0752060
HB		 5582int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5583{
98918833
SY		 5584 struct i387_fxsave_struct *fxsave =
5585 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5586
d0752060
HB		 5587 memcpy(fpu->fpr, fxsave->st_space, 128);
5588 fpu->fcw = fxsave->cwd;
5589 fpu->fsw = fxsave->swd;
5590 fpu->ftwx = fxsave->twd;
5591 fpu->last_opcode = fxsave->fop;
5592 fpu->last_ip = fxsave->rip;
5593 fpu->last_dp = fxsave->rdp;
5594 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5595
d0752060
HB		 5596 return 0;
5597}
5598
5599int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5600{
98918833
SY		 5601 struct i387_fxsave_struct *fxsave =
5602 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5603
d0752060
HB		 5604 memcpy(fxsave->st_space, fpu->fpr, 128);
5605 fxsave->cwd = fpu->fcw;
5606 fxsave->swd = fpu->fsw;
5607 fxsave->twd = fpu->ftwx;
5608 fxsave->fop = fpu->last_opcode;
5609 fxsave->rip = fpu->last_ip;
5610 fxsave->rdp = fpu->last_dp;
5611 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5612
d0752060
HB		 5613 return 0;
5614}
5615
10ab25cd 5616int fx_init(struct kvm_vcpu *vcpu)
d0752060 5617{
10ab25cd
JK		 5618 int err;
5619
5620 err = fpu_alloc(&vcpu->arch.guest_fpu);
5621 if (err)
5622 return err;
5623
98918833 5624 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5625
2acf923e
DC		 5626 /*
5627 * Ensure guest xcr0 is valid for loading
5628 */
5629 vcpu->arch.xcr0 = XSTATE_FP;
5630
ad312c7c 5631 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5632
5633 return 0;
d0752060
HB		 5634}
5635EXPORT_SYMBOL_GPL(fx_init);
5636
98918833
SY		 5637static void fx_free(struct kvm_vcpu *vcpu)
5638{
5639 fpu_free(&vcpu->arch.guest_fpu);
5640}
5641
d0752060
HB		 5642void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5643{
2608d7a1 5644 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5645 return;
5646
2acf923e
DC		 5647 /*
5648 * Restore all possible states in the guest,
5649 * and assume host would use all available bits.
5650 * Guest xcr0 would be loaded later.
5651 */
5652 kvm_put_guest_xcr0(vcpu);
d0752060 5653 vcpu->guest_fpu_loaded = 1;
7cf30855 5654 unlazy_fpu(current);
98918833 5655 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5656 trace_kvm_fpu(1);
d0752060 5657}
d0752060
HB		 5658
5659void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5660{
2acf923e
DC		 5661 kvm_put_guest_xcr0(vcpu);
5662
d0752060
HB		 5663 if (!vcpu->guest_fpu_loaded)
5664 return;
5665
5666 vcpu->guest_fpu_loaded = 0;
98918833 5667 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5668 ++vcpu->stat.fpu_reload;
a8eeb04a 5669 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5670 trace_kvm_fpu(0);
d0752060 5671}
e9b11c17
ZX		 5672
5673void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5674{
7f1ea208
JR		 5675 if (vcpu->arch.time_page) {
5676 kvm_release_page_dirty(vcpu->arch.time_page);
5677 vcpu->arch.time_page = NULL;
5678 }
5679
f5f48ee1 5680 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5681 fx_free(vcpu);
e9b11c17
ZX		 5682 kvm_x86_ops->vcpu_free(vcpu);
5683}
5684
5685struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5686 unsigned int id)
5687{
6755bae8
ZA		 5688 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5689 printk_once(KERN_WARNING
5690 "kvm: SMP vm created on host with unstable TSC; "
5691 "guest TSC will not be reliable\n");
26e5215f
AK		 5692 return kvm_x86_ops->vcpu_create(kvm, id);
5693}
e9b11c17 5694
26e5215f
AK		 5695int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5696{
5697 int r;
e9b11c17 5698
0bed3b56 5699 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5700 vcpu_load(vcpu);
5701 r = kvm_arch_vcpu_reset(vcpu);
5702 if (r == 0)
5703 r = kvm_mmu_setup(vcpu);
5704 vcpu_put(vcpu);
5705 if (r < 0)
5706 goto free_vcpu;
5707
26e5215f 5708 return 0;
e9b11c17
ZX		 5709free_vcpu:
5710 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5711 return r;
e9b11c17
ZX		 5712}
5713
d40ccc62 5714void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5715{
5716 vcpu_load(vcpu);
5717 kvm_mmu_unload(vcpu);
5718 vcpu_put(vcpu);
5719
98918833 5720 fx_free(vcpu);
e9b11c17
ZX		 5721 kvm_x86_ops->vcpu_free(vcpu);
5722}
5723
5724int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5725{
448fa4a9
JK		 5726 vcpu->arch.nmi_pending = false;
5727 vcpu->arch.nmi_injected = false;
5728
42dbaa5a
JK		 5729 vcpu->arch.switch_db_regs = 0;
5730 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5731 vcpu->arch.dr6 = DR6_FIXED_1;
5732 vcpu->arch.dr7 = DR7_FIXED_1;
5733
3842d135
AK		 5734 kvm_make_request(KVM_REQ_EVENT, vcpu);
5735
e9b11c17
ZX		 5736 return kvm_x86_ops->vcpu_reset(vcpu);
5737}
5738
10474ae8 5739int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5740{
ca84d1a2
ZA		 5741 struct kvm *kvm;
5742 struct kvm_vcpu *vcpu;
5743 int i;
5744
18863bdd 5745 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5746 list_for_each_entry(kvm, &vm_list, vm_list)
5747 kvm_for_each_vcpu(i, vcpu, kvm)
5748 if (vcpu->cpu == smp_processor_id())
5749 kvm_request_guest_time_update(vcpu);
10474ae8 5750 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5751}
5752
5753void kvm_arch_hardware_disable(void *garbage)
5754{
5755 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5756 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5757}
5758
5759int kvm_arch_hardware_setup(void)
5760{
5761 return kvm_x86_ops->hardware_setup();
5762}
5763
5764void kvm_arch_hardware_unsetup(void)
5765{
5766 kvm_x86_ops->hardware_unsetup();
5767}
5768
5769void kvm_arch_check_processor_compat(void *rtn)
5770{
5771 kvm_x86_ops->check_processor_compatibility(rtn);
5772}
5773
5774int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5775{
5776 struct page *page;
5777 struct kvm *kvm;
5778 int r;
5779
5780 BUG_ON(vcpu->kvm == NULL);
5781 kvm = vcpu->kvm;
5782
9aabc88f 5783 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5784 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5785 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5786 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5787 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5788 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5789 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5790 else
a4535290 5791 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5792
5793 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5794 if (!page) {
5795 r = -ENOMEM;
5796 goto fail;
5797 }
ad312c7c 5798 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5799
5800 r = kvm_mmu_create(vcpu);
5801 if (r < 0)
5802 goto fail_free_pio_data;
5803
5804 if (irqchip_in_kernel(kvm)) {
5805 r = kvm_create_lapic(vcpu);
5806 if (r < 0)
5807 goto fail_mmu_destroy;
5808 }
5809
890ca9ae
HY		 5810 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5811 GFP_KERNEL);
5812 if (!vcpu->arch.mce_banks) {
5813 r = -ENOMEM;
443c39bc 5814 goto fail_free_lapic;
890ca9ae
HY		 5815 }
5816 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5817
f5f48ee1
SY		 5818 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5819 goto fail_free_mce_banks;
5820
e9b11c17 5821 return 0;
f5f48ee1
SY		 5822fail_free_mce_banks:
5823 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5824fail_free_lapic:
5825 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5826fail_mmu_destroy:
5827 kvm_mmu_destroy(vcpu);
5828fail_free_pio_data:
ad312c7c 5829 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5830fail:
5831 return r;
5832}
5833
5834void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5835{
f656ce01
MT		 5836 int idx;
5837
36cb93fd 5838 kfree(vcpu->arch.mce_banks);
e9b11c17 5839 kvm_free_lapic(vcpu);
f656ce01 5840 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5841 kvm_mmu_destroy(vcpu);
f656ce01 5842 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5843 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5844}
d19a9cd2
ZX		 5845
5846struct kvm *kvm_arch_create_vm(void)
5847{
5848 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5849
5850 if (!kvm)
5851 return ERR_PTR(-ENOMEM);
5852
f05e70ac 5853 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5854 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5855
5550af4d
SY		 5856 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5857 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5858
99e3e30a
ZA		 5859 spin_lock_init(&kvm->arch.tsc_write_lock);
5860
d19a9cd2
ZX		 5861 return kvm;
5862}
5863
5864static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5865{
5866 vcpu_load(vcpu);
5867 kvm_mmu_unload(vcpu);
5868 vcpu_put(vcpu);
5869}
5870
5871static void kvm_free_vcpus(struct kvm *kvm)
5872{
5873 unsigned int i;
988a2cae 5874 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5875
5876 /*
5877 * Unpin any mmu pages first.
5878 */
988a2cae
GN		 5879 kvm_for_each_vcpu(i, vcpu, kvm)
5880 kvm_unload_vcpu_mmu(vcpu);
5881 kvm_for_each_vcpu(i, vcpu, kvm)
5882 kvm_arch_vcpu_free(vcpu);
5883
5884 mutex_lock(&kvm->lock);
5885 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5886 kvm->vcpus[i] = NULL;
d19a9cd2 5887
988a2cae
GN		 5888 atomic_set(&kvm->online_vcpus, 0);
5889 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5890}
5891
ad8ba2cd
SY		 5892void kvm_arch_sync_events(struct kvm *kvm)
5893{
ba4cef31 5894 kvm_free_all_assigned_devices(kvm);
aea924f6 5895 kvm_free_pit(kvm);
ad8ba2cd
SY		 5896}
5897
d19a9cd2
ZX		 5898void kvm_arch_destroy_vm(struct kvm *kvm)
5899{
6eb55818 5900 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5901 kfree(kvm->arch.vpic);
5902 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5903 kvm_free_vcpus(kvm);
5904 kvm_free_physmem(kvm);
3d45830c
AK		 5905 if (kvm->arch.apic_access_page)
5906 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5907 if (kvm->arch.ept_identity_pagetable)
5908 put_page(kvm->arch.ept_identity_pagetable);
64749204 5909 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5910 kfree(kvm);
5911}
0de10343 5912
f7784b8e
MT		 5913int kvm_arch_prepare_memory_region(struct kvm *kvm,
5914 struct kvm_memory_slot *memslot,
0de10343 5915 struct kvm_memory_slot old,
f7784b8e 5916 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5917 int user_alloc)
5918{
f7784b8e 5919 int npages = memslot->npages;
7ac77099
AK		 5920 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5921
5922 /* Prevent internal slot pages from being moved by fork()/COW. */
5923 if (memslot->id >= KVM_MEMORY_SLOTS)
5924 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5925
5926 /*To keep backward compatibility with older userspace,
5927 *x86 needs to hanlde !user_alloc case.
5928 */
5929 if (!user_alloc) {
5930 if (npages && !old.rmap) {
604b38ac
AA		 5931 unsigned long userspace_addr;
5932
72dc67a6 5933 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5934 userspace_addr = do_mmap(NULL, 0,
5935 npages * PAGE_SIZE,
5936 PROT_READ | PROT_WRITE,
7ac77099 5937 map_flags,
604b38ac 5938 0);
72dc67a6 5939 up_write(&current->mm->mmap_sem);
0de10343 5940
604b38ac
AA		 5941 if (IS_ERR((void *)userspace_addr))
5942 return PTR_ERR((void *)userspace_addr);
5943
604b38ac 5944 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5945 }
5946 }
5947
f7784b8e
MT		 5948
5949 return 0;
5950}
5951
5952void kvm_arch_commit_memory_region(struct kvm *kvm,
5953 struct kvm_userspace_memory_region *mem,
5954 struct kvm_memory_slot old,
5955 int user_alloc)
5956{
5957
5958 int npages = mem->memory_size >> PAGE_SHIFT;
5959
5960 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5961 int ret;
5962
5963 down_write(&current->mm->mmap_sem);
5964 ret = do_munmap(current->mm, old.userspace_addr,
5965 old.npages * PAGE_SIZE);
5966 up_write(&current->mm->mmap_sem);
5967 if (ret < 0)
5968 printk(KERN_WARNING
5969 "kvm_vm_ioctl_set_memory_region: "
5970 "failed to munmap memory\n");
5971 }
5972
7c8a83b7 5973 spin_lock(&kvm->mmu_lock);
f05e70ac 5974 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5975 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5976 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5977 }
5978
5979 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5980 spin_unlock(&kvm->mmu_lock);
0de10343 5981}
1d737c8a 5982
34d4cb8f
MT		 5983void kvm_arch_flush_shadow(struct kvm *kvm)
5984{
5985 kvm_mmu_zap_all(kvm);
8986ecc0 5986 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5987}
5988
1d737c8a
ZX		 5989int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5990{
a4535290 5991 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5992 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5993 || vcpu->arch.nmi_pending ||
5994 (kvm_arch_interrupt_allowed(vcpu) &&
5995 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5996}
5736199a 5997
5736199a
ZX		 5998void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5999{
32f88400
MT		 6000 int me;
6001 int cpu = vcpu->cpu;
5736199a
ZX		 6002
6003 if (waitqueue_active(&vcpu->wq)) {
6004 wake_up_interruptible(&vcpu->wq);
6005 ++vcpu->stat.halt_wakeup;
6006 }
32f88400
MT		 6007
6008 me = get_cpu();
6009 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 6010 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 6011 smp_send_reschedule(cpu);
e9571ed5 6012 put_cpu();
5736199a 6013}
78646121
GN		 6014
6015int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6016{
6017 return kvm_x86_ops->interrupt_allowed(vcpu);
6018}
229456fc 6019
f92653ee
JK		 6020bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6021{
6022 unsigned long current_rip = kvm_rip_read(vcpu) +
6023 get_segment_base(vcpu, VCPU_SREG_CS);
6024
6025 return current_rip == linear_rip;
6026}
6027EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6028
94fe45da
JK		 6029unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6030{
6031 unsigned long rflags;
6032
6033 rflags = kvm_x86_ops->get_rflags(vcpu);
6034 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6035 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6036 return rflags;
6037}
6038EXPORT_SYMBOL_GPL(kvm_get_rflags);
6039
6040void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6041{
6042 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6043 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6044 rflags |= X86_EFLAGS_TF;
94fe45da 6045 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6046 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6047}
6048EXPORT_SYMBOL_GPL(kvm_set_rflags);
6049
229456fc
MT		 6050EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6051EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6052EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6053EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6054EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6055EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6056EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6057EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6058EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6059EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6060EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6061EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)