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KVM: x86: Make math work for other scales
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
221d059d 9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
1d5f066e 58#include <asm/pvclock.h>
217fc9cf 59#include <asm/div64.h>
043405e1 60
313a3dc7 61#define MAX_IO_MSRS 256
a03490ed
CO		 62#define CR0_RESERVED_BITS \
63 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
64 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
65 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
66#define CR4_RESERVED_BITS \
67 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
68 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
69 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 70 | X86_CR4_OSXSAVE \
a03490ed
CO		 71 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
72
73#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 74
75#define KVM_MAX_MCE_BANKS 32
76#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
84#else
85static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
86#endif
313a3dc7 87
ba1389b7
AK		 88#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
89#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 90
cb142eb7 91static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 92static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
93 struct kvm_cpuid_entry2 __user *entries);
94
97896d04 95struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 96EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 97
ed85c068
AP		 98int ignore_msrs = 0;
99module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
100
18863bdd
AK		 101#define KVM_NR_SHARED_MSRS 16
102
103struct kvm_shared_msrs_global {
104 int nr;
2bf78fa7 105 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 106};
107
108struct kvm_shared_msrs {
109 struct user_return_notifier urn;
110 bool registered;
2bf78fa7
SY		 111 struct kvm_shared_msr_values {
112 u64 host;
113 u64 curr;
114 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 115};
116
117static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
118static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
119
417bc304 120struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 121 { "pf_fixed", VCPU_STAT(pf_fixed) },
122 { "pf_guest", VCPU_STAT(pf_guest) },
123 { "tlb_flush", VCPU_STAT(tlb_flush) },
124 { "invlpg", VCPU_STAT(invlpg) },
125 { "exits", VCPU_STAT(exits) },
126 { "io_exits", VCPU_STAT(io_exits) },
127 { "mmio_exits", VCPU_STAT(mmio_exits) },
128 { "signal_exits", VCPU_STAT(signal_exits) },
129 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 130 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 131 { "halt_exits", VCPU_STAT(halt_exits) },
132 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 133 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 134 { "request_irq", VCPU_STAT(request_irq_exits) },
135 { "irq_exits", VCPU_STAT(irq_exits) },
136 { "host_state_reload", VCPU_STAT(host_state_reload) },
137 { "efer_reload", VCPU_STAT(efer_reload) },
138 { "fpu_reload", VCPU_STAT(fpu_reload) },
139 { "insn_emulation", VCPU_STAT(insn_emulation) },
140 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 141 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 142 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 143 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
144 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
145 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
146 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
147 { "mmu_flooded", VM_STAT(mmu_flooded) },
148 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 149 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 150 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 151 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 152 { "largepages", VM_STAT(lpages) },
417bc304
HB		 153 { NULL }
154};
155
2acf923e
DC		 156u64 __read_mostly host_xcr0;
157
158static inline u32 bit(int bitno)
159{
160 return 1 << (bitno & 31);
161}
162
18863bdd
AK		 163static void kvm_on_user_return(struct user_return_notifier *urn)
164{
165 unsigned slot;
18863bdd
AK		 166 struct kvm_shared_msrs *locals
167 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 168 struct kvm_shared_msr_values *values;
18863bdd
AK		 169
170 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 171 values = &locals->values[slot];
172 if (values->host != values->curr) {
173 wrmsrl(shared_msrs_global.msrs[slot], values->host);
174 values->curr = values->host;
18863bdd
AK		 175 }
176 }
177 locals->registered = false;
178 user_return_notifier_unregister(urn);
179}
180
2bf78fa7 181static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 182{
2bf78fa7 183 struct kvm_shared_msrs *smsr;
18863bdd
AK		 184 u64 value;
185
2bf78fa7
SY		 186 smsr = &__get_cpu_var(shared_msrs);
187 /* only read, and nobody should modify it at this time,
188 * so don't need lock */
189 if (slot >= shared_msrs_global.nr) {
190 printk(KERN_ERR "kvm: invalid MSR slot!");
191 return;
192 }
193 rdmsrl_safe(msr, &value);
194 smsr->values[slot].host = value;
195 smsr->values[slot].curr = value;
196}
197
198void kvm_define_shared_msr(unsigned slot, u32 msr)
199{
18863bdd
AK		 200 if (slot >= shared_msrs_global.nr)
201 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 202 shared_msrs_global.msrs[slot] = msr;
203 /* we need ensured the shared_msr_global have been updated */
204 smp_wmb();
18863bdd
AK		 205}
206EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
207
208static void kvm_shared_msr_cpu_online(void)
209{
210 unsigned i;
18863bdd
AK		 211
212 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 213 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 214}
215
d5696725 216void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 217{
218 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
219
2bf78fa7 220 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 221 return;
2bf78fa7
SY		 222 smsr->values[slot].curr = value;
223 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 224 if (!smsr->registered) {
225 smsr->urn.on_user_return = kvm_on_user_return;
226 user_return_notifier_register(&smsr->urn);
227 smsr->registered = true;
228 }
229}
230EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
231
3548bab5
AK		 232static void drop_user_return_notifiers(void *ignore)
233{
234 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
235
236 if (smsr->registered)
237 kvm_on_user_return(&smsr->urn);
238}
239
6866b83e
CO		 240u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
241{
242 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e 244 else
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e
CO		 246}
247EXPORT_SYMBOL_GPL(kvm_get_apic_base);
248
249void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
250{
251 /* TODO: reserve bits check */
252 if (irqchip_in_kernel(vcpu->kvm))
253 kvm_lapic_set_base(vcpu, data);
254 else
ad312c7c 255 vcpu->arch.apic_base = data;
6866b83e
CO		 256}
257EXPORT_SYMBOL_GPL(kvm_set_apic_base);
258
3fd28fce
ED		 259#define EXCPT_BENIGN 0
260#define EXCPT_CONTRIBUTORY 1
261#define EXCPT_PF 2
262
263static int exception_class(int vector)
264{
265 switch (vector) {
266 case PF_VECTOR:
267 return EXCPT_PF;
268 case DE_VECTOR:
269 case TS_VECTOR:
270 case NP_VECTOR:
271 case SS_VECTOR:
272 case GP_VECTOR:
273 return EXCPT_CONTRIBUTORY;
274 default:
275 break;
276 }
277 return EXCPT_BENIGN;
278}
279
280static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 281 unsigned nr, bool has_error, u32 error_code,
282 bool reinject)
3fd28fce
ED		 283{
284 u32 prev_nr;
285 int class1, class2;
286
3842d135
AK		 287 kvm_make_request(KVM_REQ_EVENT, vcpu);
288
3fd28fce
ED		 289 if (!vcpu->arch.exception.pending) {
290 queue:
291 vcpu->arch.exception.pending = true;
292 vcpu->arch.exception.has_error_code = has_error;
293 vcpu->arch.exception.nr = nr;
294 vcpu->arch.exception.error_code = error_code;
3f0fd292 295 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 296 return;
297 }
298
299 /* to check exception */
300 prev_nr = vcpu->arch.exception.nr;
301 if (prev_nr == DF_VECTOR) {
302 /* triple fault -> shutdown */
a8eeb04a 303 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 304 return;
305 }
306 class1 = exception_class(prev_nr);
307 class2 = exception_class(nr);
308 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
309 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
310 /* generate double fault per SDM Table 5-5 */
311 vcpu->arch.exception.pending = true;
312 vcpu->arch.exception.has_error_code = true;
313 vcpu->arch.exception.nr = DF_VECTOR;
314 vcpu->arch.exception.error_code = 0;
315 } else
316 /* replace previous exception with a new one in a hope
317 that instruction re-execution will regenerate lost
318 exception */
319 goto queue;
320}
321
298101da
AK		 322void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
323{
ce7ddec4 324 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 325}
326EXPORT_SYMBOL_GPL(kvm_queue_exception);
327
ce7ddec4
JR		 328void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
329{
330 kvm_multiple_exception(vcpu, nr, false, 0, true);
331}
332EXPORT_SYMBOL_GPL(kvm_requeue_exception);
333
8df25a32 334void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
c3c91fee 335{
8df25a32
JR		 336 unsigned error_code = vcpu->arch.fault.error_code;
337
c3c91fee 338 ++vcpu->stat.pf_guest;
8df25a32 339 vcpu->arch.cr2 = vcpu->arch.fault.address;
c3c91fee
AK		 340 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
341}
342
d4f8cf66
JR		 343void kvm_propagate_fault(struct kvm_vcpu *vcpu)
344{
0959ffac 345 if (mmu_is_nested(vcpu) && !vcpu->arch.fault.nested)
d4f8cf66
JR		 346 vcpu->arch.nested_mmu.inject_page_fault(vcpu);
347 else
348 vcpu->arch.mmu.inject_page_fault(vcpu);
0959ffac
JR		 349
350 vcpu->arch.fault.nested = false;
d4f8cf66
JR		 351}
352
3419ffc8
SY		 353void kvm_inject_nmi(struct kvm_vcpu *vcpu)
354{
3842d135 355 kvm_make_request(KVM_REQ_EVENT, vcpu);
3419ffc8
SY		 356 vcpu->arch.nmi_pending = 1;
357}
358EXPORT_SYMBOL_GPL(kvm_inject_nmi);
359
298101da
AK		 360void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
361{
ce7ddec4 362 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 363}
364EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
365
ce7ddec4
JR		 366void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
367{
368 kvm_multiple_exception(vcpu, nr, true, error_code, true);
369}
370EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
371
0a79b009
AK		 372/*
373 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
374 * a #GP and return false.
375 */
376bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 377{
0a79b009
AK		 378 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
379 return true;
380 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
381 return false;
298101da 382}
0a79b009 383EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 384
ec92fe44
JR		 385/*
386 * This function will be used to read from the physical memory of the currently
387 * running guest. The difference to kvm_read_guest_page is that this function
388 * can read from guest physical or from the guest's guest physical memory.
389 */
390int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
391 gfn_t ngfn, void *data, int offset, int len,
392 u32 access)
393{
394 gfn_t real_gfn;
395 gpa_t ngpa;
396
397 ngpa = gfn_to_gpa(ngfn);
398 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
399 if (real_gfn == UNMAPPED_GVA)
400 return -EFAULT;
401
402 real_gfn = gpa_to_gfn(real_gfn);
403
404 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
405}
406EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
407
3d06b8bf
JR		 408int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
409 void *data, int offset, int len, u32 access)
410{
411 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
412 data, offset, len, access);
413}
414
a03490ed
CO		 415/*
416 * Load the pae pdptrs. Return true is they are all valid.
417 */
ff03a073 418int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 419{
420 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
421 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
422 int i;
423 int ret;
ff03a073 424 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 425
ff03a073
JR		 426 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
427 offset * sizeof(u64), sizeof(pdpte),
428 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 429 if (ret < 0) {
430 ret = 0;
431 goto out;
432 }
433 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 434 if (is_present_gpte(pdpte[i]) &&
20c466b5 435 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 436 ret = 0;
437 goto out;
438 }
439 }
440 ret = 1;
441
ff03a073 442 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 443 __set_bit(VCPU_EXREG_PDPTR,
444 (unsigned long *)&vcpu->arch.regs_avail);
445 __set_bit(VCPU_EXREG_PDPTR,
446 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 447out:
a03490ed
CO		 448
449 return ret;
450}
cc4b6871 451EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 452
d835dfec
AK		 453static bool pdptrs_changed(struct kvm_vcpu *vcpu)
454{
ff03a073 455 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 456 bool changed = true;
3d06b8bf
JR		 457 int offset;
458 gfn_t gfn;
d835dfec
AK		 459 int r;
460
461 if (is_long_mode(vcpu) || !is_pae(vcpu))
462 return false;
463
6de4f3ad
AK		 464 if (!test_bit(VCPU_EXREG_PDPTR,
465 (unsigned long *)&vcpu->arch.regs_avail))
466 return true;
467
3d06b8bf
JR		 468 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
469 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
470 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
471 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 472 if (r < 0)
473 goto out;
ff03a073 474 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 475out:
d835dfec
AK		 476
477 return changed;
478}
479
49a9b07e 480int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 481{
aad82703
SY		 482 unsigned long old_cr0 = kvm_read_cr0(vcpu);
483 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
484 X86_CR0_CD | X86_CR0_NW;
485
f9a48e6a
AK		 486 cr0 |= X86_CR0_ET;
487
ab344828 488#ifdef CONFIG_X86_64
0f12244f
GN		 489 if (cr0 & 0xffffffff00000000UL)
490 return 1;
ab344828
GN		 491#endif
492
493 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 494
0f12244f
GN		 495 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
496 return 1;
a03490ed 497
0f12244f
GN		 498 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
499 return 1;
a03490ed
CO		 500
501 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
502#ifdef CONFIG_X86_64
f6801dff 503 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 504 int cs_db, cs_l;
505
0f12244f
GN		 506 if (!is_pae(vcpu))
507 return 1;
a03490ed 508 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 509 if (cs_l)
510 return 1;
a03490ed
CO		 511 } else
512#endif
ff03a073
JR		 513 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
514 vcpu->arch.cr3))
0f12244f 515 return 1;
a03490ed
CO		 516 }
517
518 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 519
aad82703
SY		 520 if ((cr0 ^ old_cr0) & update_bits)
521 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 522 return 0;
523}
2d3ad1f4 524EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 525
2d3ad1f4 526void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 527{
49a9b07e 528 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 529}
2d3ad1f4 530EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 531
2acf923e
DC		 532int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
533{
534 u64 xcr0;
535
536 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
537 if (index != XCR_XFEATURE_ENABLED_MASK)
538 return 1;
539 xcr0 = xcr;
540 if (kvm_x86_ops->get_cpl(vcpu) != 0)
541 return 1;
542 if (!(xcr0 & XSTATE_FP))
543 return 1;
544 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
545 return 1;
546 if (xcr0 & ~host_xcr0)
547 return 1;
548 vcpu->arch.xcr0 = xcr0;
549 vcpu->guest_xcr0_loaded = 0;
550 return 0;
551}
552
553int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
554{
555 if (__kvm_set_xcr(vcpu, index, xcr)) {
556 kvm_inject_gp(vcpu, 0);
557 return 1;
558 }
559 return 0;
560}
561EXPORT_SYMBOL_GPL(kvm_set_xcr);
562
563static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
564{
565 struct kvm_cpuid_entry2 *best;
566
567 best = kvm_find_cpuid_entry(vcpu, 1, 0);
568 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
569}
570
571static void update_cpuid(struct kvm_vcpu *vcpu)
572{
573 struct kvm_cpuid_entry2 *best;
574
575 best = kvm_find_cpuid_entry(vcpu, 1, 0);
576 if (!best)
577 return;
578
579 /* Update OSXSAVE bit */
580 if (cpu_has_xsave && best->function == 0x1) {
581 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
582 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
583 best->ecx |= bit(X86_FEATURE_OSXSAVE);
584 }
585}
586
a83b29c6 587int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 588{
fc78f519 589 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 590 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
591
0f12244f
GN		 592 if (cr4 & CR4_RESERVED_BITS)
593 return 1;
a03490ed 594
2acf923e
DC		 595 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
596 return 1;
597
a03490ed 598 if (is_long_mode(vcpu)) {
0f12244f
GN		 599 if (!(cr4 & X86_CR4_PAE))
600 return 1;
a2edf57f
AK		 601 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
602 && ((cr4 ^ old_cr4) & pdptr_bits)
ff03a073 603 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
0f12244f
GN		 604 return 1;
605
606 if (cr4 & X86_CR4_VMXE)
607 return 1;
a03490ed 608
a03490ed 609 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 610
aad82703
SY		 611 if ((cr4 ^ old_cr4) & pdptr_bits)
612 kvm_mmu_reset_context(vcpu);
0f12244f 613
2acf923e
DC		 614 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
615 update_cpuid(vcpu);
616
0f12244f
GN		 617 return 0;
618}
2d3ad1f4 619EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 620
2390218b 621int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 622{
ad312c7c 623 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 624 kvm_mmu_sync_roots(vcpu);
d835dfec 625 kvm_mmu_flush_tlb(vcpu);
0f12244f 626 return 0;
d835dfec
AK		 627 }
628
a03490ed 629 if (is_long_mode(vcpu)) {
0f12244f
GN		 630 if (cr3 & CR3_L_MODE_RESERVED_BITS)
631 return 1;
a03490ed
CO		 632 } else {
633 if (is_pae(vcpu)) {
0f12244f
GN		 634 if (cr3 & CR3_PAE_RESERVED_BITS)
635 return 1;
ff03a073
JR		 636 if (is_paging(vcpu) &&
637 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 638 return 1;
a03490ed
CO		 639 }
640 /*
641 * We don't check reserved bits in nonpae mode, because
642 * this isn't enforced, and VMware depends on this.
643 */
644 }
645
a03490ed
CO		 646 /*
647 * Does the new cr3 value map to physical memory? (Note, we
648 * catch an invalid cr3 even in real-mode, because it would
649 * cause trouble later on when we turn on paging anyway.)
650 *
651 * A real CPU would silently accept an invalid cr3 and would
652 * attempt to use it - with largely undefined (and often hard
653 * to debug) behavior on the guest side.
654 */
655 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 656 return 1;
657 vcpu->arch.cr3 = cr3;
658 vcpu->arch.mmu.new_cr3(vcpu);
659 return 0;
660}
2d3ad1f4 661EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 662
0f12244f 663int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 664{
0f12244f
GN		 665 if (cr8 & CR8_RESERVED_BITS)
666 return 1;
a03490ed
CO		 667 if (irqchip_in_kernel(vcpu->kvm))
668 kvm_lapic_set_tpr(vcpu, cr8);
669 else
ad312c7c 670 vcpu->arch.cr8 = cr8;
0f12244f
GN		 671 return 0;
672}
673
674void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
675{
676 if (__kvm_set_cr8(vcpu, cr8))
677 kvm_inject_gp(vcpu, 0);
a03490ed 678}
2d3ad1f4 679EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 680
2d3ad1f4 681unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 682{
683 if (irqchip_in_kernel(vcpu->kvm))
684 return kvm_lapic_get_cr8(vcpu);
685 else
ad312c7c 686 return vcpu->arch.cr8;
a03490ed 687}
2d3ad1f4 688EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 689
338dbc97 690static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 691{
692 switch (dr) {
693 case 0 ... 3:
694 vcpu->arch.db[dr] = val;
695 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
696 vcpu->arch.eff_db[dr] = val;
697 break;
698 case 4:
338dbc97
GN		 699 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
700 return 1; /* #UD */
020df079
GN		 701 /* fall through */
702 case 6:
338dbc97
GN		 703 if (val & 0xffffffff00000000ULL)
704 return -1; /* #GP */
020df079
GN		 705 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
706 break;
707 case 5:
338dbc97
GN		 708 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
709 return 1; /* #UD */
020df079
GN		 710 /* fall through */
711 default: /* 7 */
338dbc97
GN		 712 if (val & 0xffffffff00000000ULL)
713 return -1; /* #GP */
020df079
GN		 714 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
715 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
716 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
717 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
718 }
719 break;
720 }
721
722 return 0;
723}
338dbc97
GN		 724
725int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
726{
727 int res;
728
729 res = __kvm_set_dr(vcpu, dr, val);
730 if (res > 0)
731 kvm_queue_exception(vcpu, UD_VECTOR);
732 else if (res < 0)
733 kvm_inject_gp(vcpu, 0);
734
735 return res;
736}
020df079
GN		 737EXPORT_SYMBOL_GPL(kvm_set_dr);
738
338dbc97 739static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 740{
741 switch (dr) {
742 case 0 ... 3:
743 *val = vcpu->arch.db[dr];
744 break;
745 case 4:
338dbc97 746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 747 return 1;
020df079
GN		 748 /* fall through */
749 case 6:
750 *val = vcpu->arch.dr6;
751 break;
752 case 5:
338dbc97 753 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 754 return 1;
020df079
GN		 755 /* fall through */
756 default: /* 7 */
757 *val = vcpu->arch.dr7;
758 break;
759 }
760
761 return 0;
762}
338dbc97
GN		 763
764int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
765{
766 if (_kvm_get_dr(vcpu, dr, val)) {
767 kvm_queue_exception(vcpu, UD_VECTOR);
768 return 1;
769 }
770 return 0;
771}
020df079
GN		 772EXPORT_SYMBOL_GPL(kvm_get_dr);
773
043405e1
CO		 774/*
775 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
776 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
777 *
778 * This list is modified at module load time to reflect the
e3267cbb
GC		 779 * capabilities of the host cpu. This capabilities test skips MSRs that are
780 * kvm-specific. Those are put in the beginning of the list.
043405e1 781 */
e3267cbb 782
11c6bffa 783#define KVM_SAVE_MSRS_BEGIN 7
043405e1 784static u32 msrs_to_save[] = {
e3267cbb 785 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 786 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 787 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 788 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1 789 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 790 MSR_STAR,
043405e1
CO		 791#ifdef CONFIG_X86_64
792 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
793#endif
e90aa41e 794 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 795};
796
797static unsigned num_msrs_to_save;
798
799static u32 emulated_msrs[] = {
800 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 801 MSR_IA32_MCG_STATUS,
802 MSR_IA32_MCG_CTL,
043405e1
CO		 803};
804
b69e8cae 805static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 806{
aad82703
SY		 807 u64 old_efer = vcpu->arch.efer;
808
b69e8cae
RJ		 809 if (efer & efer_reserved_bits)
810 return 1;
15c4a640
CO		 811
812 if (is_paging(vcpu)
b69e8cae
RJ		 813 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
814 return 1;
15c4a640 815
1b2fd70c
AG		 816 if (efer & EFER_FFXSR) {
817 struct kvm_cpuid_entry2 *feat;
818
819 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 820 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
821 return 1;
1b2fd70c
AG		 822 }
823
d8017474
AG		 824 if (efer & EFER_SVME) {
825 struct kvm_cpuid_entry2 *feat;
826
827 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 828 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
829 return 1;
d8017474
AG		 830 }
831
15c4a640 832 efer &= ~EFER_LMA;
f6801dff 833 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 834
a3d204e2
SY		 835 kvm_x86_ops->set_efer(vcpu, efer);
836
9645bb56
AK		 837 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
838 kvm_mmu_reset_context(vcpu);
b69e8cae 839
aad82703
SY		 840 /* Update reserved bits */
841 if ((efer ^ old_efer) & EFER_NX)
842 kvm_mmu_reset_context(vcpu);
843
b69e8cae 844 return 0;
15c4a640
CO		 845}
846
f2b4b7dd
JR		 847void kvm_enable_efer_bits(u64 mask)
848{
849 efer_reserved_bits &= ~mask;
850}
851EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
852
853
15c4a640
CO		 854/*
855 * Writes msr value into into the appropriate "register".
856 * Returns 0 on success, non-0 otherwise.
857 * Assumes vcpu_load() was already called.
858 */
859int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
860{
861 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
862}
863
313a3dc7
CO		 864/*
865 * Adapt set_msr() to msr_io()'s calling convention
866 */
867static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
868{
869 return kvm_set_msr(vcpu, index, *data);
870}
871
18068523
GOC		 872static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
873{
9ed3c444
AK		 874 int version;
875 int r;
50d0a0f9 876 struct pvclock_wall_clock wc;
923de3cf 877 struct timespec boot;
18068523
GOC		 878
879 if (!wall_clock)
880 return;
881
9ed3c444
AK		 882 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
883 if (r)
884 return;
885
886 if (version & 1)
887 ++version; /* first time write, random junk */
888
889 ++version;
18068523 890
18068523
GOC		 891 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
892
50d0a0f9
GH		 893 /*
894 * The guest calculates current wall clock time by adding
895 * system time (updated by kvm_write_guest_time below) to the
896 * wall clock specified here. guest system time equals host
897 * system time for us, thus we must fill in host boot time here.
898 */
923de3cf 899 getboottime(&boot);
50d0a0f9
GH		 900
901 wc.sec = boot.tv_sec;
902 wc.nsec = boot.tv_nsec;
903 wc.version = version;
18068523
GOC		 904
905 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
906
907 version++;
908 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 909}
910
50d0a0f9
GH		 911static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
912{
913 uint32_t quotient, remainder;
914
915 /* Don't try to replace with do_div(), this one calculates
916 * "(dividend << 32) / divisor" */
917 __asm__ ( "divl %4"
918 : "=a" (quotient), "=d" (remainder)
919 : "0" (0), "1" (dividend), "r" (divisor) );
920 return quotient;
921}
922
5f4e3f88
ZA		 923static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
924 s8 *pshift, u32 *pmultiplier)
50d0a0f9 925{
5f4e3f88 926 uint64_t scaled64;
50d0a0f9
GH		 927 int32_t shift = 0;
928 uint64_t tps64;
929 uint32_t tps32;
930
5f4e3f88
ZA		 931 tps64 = base_khz * 1000LL;
932 scaled64 = scaled_khz * 1000LL;
933 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000UL) {
50d0a0f9
GH		 934 tps64 >>= 1;
935 shift--;
936 }
937
938 tps32 = (uint32_t)tps64;
5f4e3f88
ZA		 939 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000UL) {
940 if (scaled64 & 0xffffffff00000000UL || tps32 & 0x80000000)
941 scaled64 >>= 1;
942 else
943 tps32 <<= 1;
50d0a0f9
GH		 944 shift++;
945 }
946
5f4e3f88
ZA		 947 *pshift = shift;
948 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 949
5f4e3f88
ZA		 950 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
951 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 952}
953
759379dd
ZA		 954static inline u64 get_kernel_ns(void)
955{
956 struct timespec ts;
957
958 WARN_ON(preemptible());
959 ktime_get_ts(&ts);
960 monotonic_to_bootbased(&ts);
961 return timespec_to_ns(&ts);
962}
963
c8076604
GH		 964static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
965
8cfdc000
ZA		 966static inline int kvm_tsc_changes_freq(void)
967{
968 int cpu = get_cpu();
969 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
970 cpufreq_quick_get(cpu) != 0;
971 put_cpu();
972 return ret;
973}
974
759379dd
ZA		 975static inline u64 nsec_to_cycles(u64 nsec)
976{
217fc9cf
AK		 977 u64 ret;
978
759379dd
ZA		 979 WARN_ON(preemptible());
980 if (kvm_tsc_changes_freq())
981 printk_once(KERN_WARNING
982 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 983 ret = nsec * __get_cpu_var(cpu_tsc_khz);
984 do_div(ret, USEC_PER_SEC);
985 return ret;
759379dd
ZA		 986}
987
99e3e30a
ZA		 988void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
989{
990 struct kvm *kvm = vcpu->kvm;
f38e098f 991 u64 offset, ns, elapsed;
99e3e30a 992 unsigned long flags;
46543ba4 993 s64 sdiff;
99e3e30a
ZA		 994
995 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
996 offset = data - native_read_tsc();
759379dd 997 ns = get_kernel_ns();
f38e098f 998 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 999 sdiff = data - kvm->arch.last_tsc_write;
1000 if (sdiff < 0)
1001 sdiff = -sdiff;
f38e098f
ZA		 1002
1003 /*
46543ba4 1004 * Special case: close write to TSC within 5 seconds of
f38e098f 1005 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 1006 * The 5 seconds is to accomodate host load / swapping as
1007 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1008 *
1009 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1010 * or make a best guest using elapsed value.
f38e098f 1011 */
46543ba4
ZA		 1012 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1013 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1014 if (!check_tsc_unstable()) {
1015 offset = kvm->arch.last_tsc_offset;
1016 pr_debug("kvm: matched tsc offset for %llu\n", data);
1017 } else {
759379dd
ZA		 1018 u64 delta = nsec_to_cycles(elapsed);
1019 offset += delta;
1020 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1021 }
1022 ns = kvm->arch.last_tsc_nsec;
1023 }
1024 kvm->arch.last_tsc_nsec = ns;
1025 kvm->arch.last_tsc_write = data;
1026 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1027 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1028 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1029
1030 /* Reset of TSC must disable overshoot protection below */
1031 vcpu->arch.hv_clock.tsc_timestamp = 0;
1032}
1033EXPORT_SYMBOL_GPL(kvm_write_tsc);
1034
8cfdc000 1035static int kvm_write_guest_time(struct kvm_vcpu *v)
18068523 1036{
18068523
GOC		 1037 unsigned long flags;
1038 struct kvm_vcpu_arch *vcpu = &v->arch;
1039 void *shared_kaddr;
463656c0 1040 unsigned long this_tsc_khz;
1d5f066e
ZA		 1041 s64 kernel_ns, max_kernel_ns;
1042 u64 tsc_timestamp;
18068523
GOC		 1043
1044 if ((!vcpu->time_page))
8cfdc000 1045 return 0;
50d0a0f9 1046
18068523
GOC		 1047 /* Keep irq disabled to prevent changes to the clock */
1048 local_irq_save(flags);
1d5f066e 1049 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1050 kernel_ns = get_kernel_ns();
8cfdc000 1051 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523
GOC		 1052 local_irq_restore(flags);
1053
8cfdc000
ZA		 1054 if (unlikely(this_tsc_khz == 0)) {
1055 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
1056 return 1;
1057 }
18068523 1058
1d5f066e
ZA		 1059 /*
1060 * Time as measured by the TSC may go backwards when resetting the base
1061 * tsc_timestamp. The reason for this is that the TSC resolution is
1062 * higher than the resolution of the other clock scales. Thus, many
1063 * possible measurments of the TSC correspond to one measurement of any
1064 * other clock, and so a spread of values is possible. This is not a
1065 * problem for the computation of the nanosecond clock; with TSC rates
1066 * around 1GHZ, there can only be a few cycles which correspond to one
1067 * nanosecond value, and any path through this code will inevitably
1068 * take longer than that. However, with the kernel_ns value itself,
1069 * the precision may be much lower, down to HZ granularity. If the
1070 * first sampling of TSC against kernel_ns ends in the low part of the
1071 * range, and the second in the high end of the range, we can get:
1072 *
1073 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1074 *
1075 * As the sampling errors potentially range in the thousands of cycles,
1076 * it is possible such a time value has already been observed by the
1077 * guest. To protect against this, we must compute the system time as
1078 * observed by the guest and ensure the new system time is greater.
1079 */
1080 max_kernel_ns = 0;
1081 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1082 max_kernel_ns = vcpu->last_guest_tsc -
1083 vcpu->hv_clock.tsc_timestamp;
1084 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1085 vcpu->hv_clock.tsc_to_system_mul,
1086 vcpu->hv_clock.tsc_shift);
1087 max_kernel_ns += vcpu->last_kernel_ns;
1088 }
1089
e48672fa 1090 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1091 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1092 &vcpu->hv_clock.tsc_shift,
1093 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1094 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1095 }
1096
1d5f066e
ZA		 1097 if (max_kernel_ns > kernel_ns)
1098 kernel_ns = max_kernel_ns;
1099
8cfdc000 1100 /* With all the info we got, fill in the values */
1d5f066e 1101 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1102 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1103 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1104 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1105 vcpu->hv_clock.flags = 0;
1106
18068523
GOC		 1107 /*
1108 * The interface expects us to write an even number signaling that the
1109 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1110 * state, we just increase by 2 at the end.
18068523 1111 */
50d0a0f9 1112 vcpu->hv_clock.version += 2;
18068523
GOC		 1113
1114 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1115
1116 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1117 sizeof(vcpu->hv_clock));
18068523
GOC		 1118
1119 kunmap_atomic(shared_kaddr, KM_USER0);
1120
1121 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1122 return 0;
18068523
GOC		 1123}
1124
c8076604
GH		 1125static int kvm_request_guest_time_update(struct kvm_vcpu *v)
1126{
1127 struct kvm_vcpu_arch *vcpu = &v->arch;
1128
1129 if (!vcpu->time_page)
1130 return 0;
a8eeb04a 1131 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
c8076604
GH		 1132 return 1;
1133}
1134
9ba075a6
AK		 1135static bool msr_mtrr_valid(unsigned msr)
1136{
1137 switch (msr) {
1138 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1139 case MSR_MTRRfix64K_00000:
1140 case MSR_MTRRfix16K_80000:
1141 case MSR_MTRRfix16K_A0000:
1142 case MSR_MTRRfix4K_C0000:
1143 case MSR_MTRRfix4K_C8000:
1144 case MSR_MTRRfix4K_D0000:
1145 case MSR_MTRRfix4K_D8000:
1146 case MSR_MTRRfix4K_E0000:
1147 case MSR_MTRRfix4K_E8000:
1148 case MSR_MTRRfix4K_F0000:
1149 case MSR_MTRRfix4K_F8000:
1150 case MSR_MTRRdefType:
1151 case MSR_IA32_CR_PAT:
1152 return true;
1153 case 0x2f8:
1154 return true;
1155 }
1156 return false;
1157}
1158
d6289b93
MT		 1159static bool valid_pat_type(unsigned t)
1160{
1161 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1162}
1163
1164static bool valid_mtrr_type(unsigned t)
1165{
1166 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1167}
1168
1169static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1170{
1171 int i;
1172
1173 if (!msr_mtrr_valid(msr))
1174 return false;
1175
1176 if (msr == MSR_IA32_CR_PAT) {
1177 for (i = 0; i < 8; i++)
1178 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1179 return false;
1180 return true;
1181 } else if (msr == MSR_MTRRdefType) {
1182 if (data & ~0xcff)
1183 return false;
1184 return valid_mtrr_type(data & 0xff);
1185 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1186 for (i = 0; i < 8 ; i++)
1187 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1188 return false;
1189 return true;
1190 }
1191
1192 /* variable MTRRs */
1193 return valid_mtrr_type(data & 0xff);
1194}
1195
9ba075a6
AK		 1196static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1197{
0bed3b56
SY		 1198 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1199
d6289b93 1200 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1201 return 1;
1202
0bed3b56
SY		 1203 if (msr == MSR_MTRRdefType) {
1204 vcpu->arch.mtrr_state.def_type = data;
1205 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1206 } else if (msr == MSR_MTRRfix64K_00000)
1207 p[0] = data;
1208 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1209 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1210 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1211 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1212 else if (msr == MSR_IA32_CR_PAT)
1213 vcpu->arch.pat = data;
1214 else { /* Variable MTRRs */
1215 int idx, is_mtrr_mask;
1216 u64 *pt;
1217
1218 idx = (msr - 0x200) / 2;
1219 is_mtrr_mask = msr - 0x200 - 2 * idx;
1220 if (!is_mtrr_mask)
1221 pt =
1222 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1223 else
1224 pt =
1225 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1226 *pt = data;
1227 }
1228
1229 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1230 return 0;
1231}
15c4a640 1232
890ca9ae 1233static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1234{
890ca9ae
HY		 1235 u64 mcg_cap = vcpu->arch.mcg_cap;
1236 unsigned bank_num = mcg_cap & 0xff;
1237
15c4a640 1238 switch (msr) {
15c4a640 1239 case MSR_IA32_MCG_STATUS:
890ca9ae 1240 vcpu->arch.mcg_status = data;
15c4a640 1241 break;
c7ac679c 1242 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1243 if (!(mcg_cap & MCG_CTL_P))
1244 return 1;
1245 if (data != 0 && data != ~(u64)0)
1246 return -1;
1247 vcpu->arch.mcg_ctl = data;
1248 break;
1249 default:
1250 if (msr >= MSR_IA32_MC0_CTL &&
1251 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1252 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1253 /* only 0 or all 1s can be written to IA32_MCi_CTL
1254 * some Linux kernels though clear bit 10 in bank 4 to
1255 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1256 * this to avoid an uncatched #GP in the guest
1257 */
890ca9ae 1258 if ((offset & 0x3) == 0 &&
114be429 1259 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1260 return -1;
1261 vcpu->arch.mce_banks[offset] = data;
1262 break;
1263 }
1264 return 1;
1265 }
1266 return 0;
1267}
1268
ffde22ac
ES		 1269static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1270{
1271 struct kvm *kvm = vcpu->kvm;
1272 int lm = is_long_mode(vcpu);
1273 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1274 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1275 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1276 : kvm->arch.xen_hvm_config.blob_size_32;
1277 u32 page_num = data & ~PAGE_MASK;
1278 u64 page_addr = data & PAGE_MASK;
1279 u8 *page;
1280 int r;
1281
1282 r = -E2BIG;
1283 if (page_num >= blob_size)
1284 goto out;
1285 r = -ENOMEM;
1286 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1287 if (!page)
1288 goto out;
1289 r = -EFAULT;
1290 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1291 goto out_free;
1292 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1293 goto out_free;
1294 r = 0;
1295out_free:
1296 kfree(page);
1297out:
1298 return r;
1299}
1300
55cd8e5a
GN		 1301static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1302{
1303 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1304}
1305
1306static bool kvm_hv_msr_partition_wide(u32 msr)
1307{
1308 bool r = false;
1309 switch (msr) {
1310 case HV_X64_MSR_GUEST_OS_ID:
1311 case HV_X64_MSR_HYPERCALL:
1312 r = true;
1313 break;
1314 }
1315
1316 return r;
1317}
1318
1319static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1320{
1321 struct kvm *kvm = vcpu->kvm;
1322
1323 switch (msr) {
1324 case HV_X64_MSR_GUEST_OS_ID:
1325 kvm->arch.hv_guest_os_id = data;
1326 /* setting guest os id to zero disables hypercall page */
1327 if (!kvm->arch.hv_guest_os_id)
1328 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1329 break;
1330 case HV_X64_MSR_HYPERCALL: {
1331 u64 gfn;
1332 unsigned long addr;
1333 u8 instructions[4];
1334
1335 /* if guest os id is not set hypercall should remain disabled */
1336 if (!kvm->arch.hv_guest_os_id)
1337 break;
1338 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1339 kvm->arch.hv_hypercall = data;
1340 break;
1341 }
1342 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1343 addr = gfn_to_hva(kvm, gfn);
1344 if (kvm_is_error_hva(addr))
1345 return 1;
1346 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1347 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1348 if (copy_to_user((void __user *)addr, instructions, 4))
1349 return 1;
1350 kvm->arch.hv_hypercall = data;
1351 break;
1352 }
1353 default:
1354 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1355 "data 0x%llx\n", msr, data);
1356 return 1;
1357 }
1358 return 0;
1359}
1360
1361static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1362{
10388a07
GN		 1363 switch (msr) {
1364 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1365 unsigned long addr;
55cd8e5a 1366
10388a07
GN		 1367 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1368 vcpu->arch.hv_vapic = data;
1369 break;
1370 }
1371 addr = gfn_to_hva(vcpu->kvm, data >>
1372 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1373 if (kvm_is_error_hva(addr))
1374 return 1;
1375 if (clear_user((void __user *)addr, PAGE_SIZE))
1376 return 1;
1377 vcpu->arch.hv_vapic = data;
1378 break;
1379 }
1380 case HV_X64_MSR_EOI:
1381 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1382 case HV_X64_MSR_ICR:
1383 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1384 case HV_X64_MSR_TPR:
1385 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1386 default:
1387 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1388 "data 0x%llx\n", msr, data);
1389 return 1;
1390 }
1391
1392 return 0;
55cd8e5a
GN		 1393}
1394
15c4a640
CO		 1395int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1396{
1397 switch (msr) {
15c4a640 1398 case MSR_EFER:
b69e8cae 1399 return set_efer(vcpu, data);
8f1589d9
AP		 1400 case MSR_K7_HWCR:
1401 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1402 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1403 if (data != 0) {
1404 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1405 data);
1406 return 1;
1407 }
15c4a640 1408 break;
f7c6d140
AP		 1409 case MSR_FAM10H_MMIO_CONF_BASE:
1410 if (data != 0) {
1411 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1412 "0x%llx\n", data);
1413 return 1;
1414 }
15c4a640 1415 break;
c323c0e5 1416 case MSR_AMD64_NB_CFG:
c7ac679c 1417 break;
b5e2fec0
AG		 1418 case MSR_IA32_DEBUGCTLMSR:
1419 if (!data) {
1420 /* We support the non-activated case already */
1421 break;
1422 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1423 /* Values other than LBR and BTF are vendor-specific,
1424 thus reserved and should throw a #GP */
1425 return 1;
1426 }
1427 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1428 __func__, data);
1429 break;
15c4a640
CO		 1430 case MSR_IA32_UCODE_REV:
1431 case MSR_IA32_UCODE_WRITE:
61a6bd67 1432 case MSR_VM_HSAVE_PA:
6098ca93 1433 case MSR_AMD64_PATCH_LOADER:
15c4a640 1434 break;
9ba075a6
AK		 1435 case 0x200 ... 0x2ff:
1436 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1437 case MSR_IA32_APICBASE:
1438 kvm_set_apic_base(vcpu, data);
1439 break;
0105d1a5
GN		 1440 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1441 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1442 case MSR_IA32_MISC_ENABLE:
ad312c7c 1443 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1444 break;
11c6bffa 1445 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1446 case MSR_KVM_WALL_CLOCK:
1447 vcpu->kvm->arch.wall_clock = data;
1448 kvm_write_wall_clock(vcpu->kvm, data);
1449 break;
11c6bffa 1450 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1451 case MSR_KVM_SYSTEM_TIME: {
1452 if (vcpu->arch.time_page) {
1453 kvm_release_page_dirty(vcpu->arch.time_page);
1454 vcpu->arch.time_page = NULL;
1455 }
1456
1457 vcpu->arch.time = data;
1458
1459 /* we verify if the enable bit is set... */
1460 if (!(data & 1))
1461 break;
1462
1463 /* ...but clean it before doing the actual write */
1464 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1465
18068523
GOC		 1466 vcpu->arch.time_page =
1467 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1468
1469 if (is_error_page(vcpu->arch.time_page)) {
1470 kvm_release_page_clean(vcpu->arch.time_page);
1471 vcpu->arch.time_page = NULL;
1472 }
1473
c8076604 1474 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1475 break;
1476 }
890ca9ae
HY		 1477 case MSR_IA32_MCG_CTL:
1478 case MSR_IA32_MCG_STATUS:
1479 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1480 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1481
1482 /* Performance counters are not protected by a CPUID bit,
1483 * so we should check all of them in the generic path for the sake of
1484 * cross vendor migration.
1485 * Writing a zero into the event select MSRs disables them,
1486 * which we perfectly emulate ;-). Any other value should be at least
1487 * reported, some guests depend on them.
1488 */
1489 case MSR_P6_EVNTSEL0:
1490 case MSR_P6_EVNTSEL1:
1491 case MSR_K7_EVNTSEL0:
1492 case MSR_K7_EVNTSEL1:
1493 case MSR_K7_EVNTSEL2:
1494 case MSR_K7_EVNTSEL3:
1495 if (data != 0)
1496 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1497 "0x%x data 0x%llx\n", msr, data);
1498 break;
1499 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1500 * so we ignore writes to make it happy.
1501 */
1502 case MSR_P6_PERFCTR0:
1503 case MSR_P6_PERFCTR1:
1504 case MSR_K7_PERFCTR0:
1505 case MSR_K7_PERFCTR1:
1506 case MSR_K7_PERFCTR2:
1507 case MSR_K7_PERFCTR3:
1508 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1509 "0x%x data 0x%llx\n", msr, data);
1510 break;
84e0cefa
JS		 1511 case MSR_K7_CLK_CTL:
1512 /*
1513 * Ignore all writes to this no longer documented MSR.
1514 * Writes are only relevant for old K7 processors,
1515 * all pre-dating SVM, but a recommended workaround from
1516 * AMD for these chips. It is possible to speicify the
1517 * affected processor models on the command line, hence
1518 * the need to ignore the workaround.
1519 */
1520 break;
55cd8e5a
GN		 1521 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1522 if (kvm_hv_msr_partition_wide(msr)) {
1523 int r;
1524 mutex_lock(&vcpu->kvm->lock);
1525 r = set_msr_hyperv_pw(vcpu, msr, data);
1526 mutex_unlock(&vcpu->kvm->lock);
1527 return r;
1528 } else
1529 return set_msr_hyperv(vcpu, msr, data);
1530 break;
15c4a640 1531 default:
ffde22ac
ES		 1532 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1533 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1534 if (!ignore_msrs) {
1535 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1536 msr, data);
1537 return 1;
1538 } else {
1539 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1540 msr, data);
1541 break;
1542 }
15c4a640
CO		 1543 }
1544 return 0;
1545}
1546EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1547
1548
1549/*
1550 * Reads an msr value (of 'msr_index') into 'pdata'.
1551 * Returns 0 on success, non-0 otherwise.
1552 * Assumes vcpu_load() was already called.
1553 */
1554int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1555{
1556 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1557}
1558
9ba075a6
AK		 1559static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1560{
0bed3b56
SY		 1561 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1562
9ba075a6
AK		 1563 if (!msr_mtrr_valid(msr))
1564 return 1;
1565
0bed3b56
SY		 1566 if (msr == MSR_MTRRdefType)
1567 *pdata = vcpu->arch.mtrr_state.def_type +
1568 (vcpu->arch.mtrr_state.enabled << 10);
1569 else if (msr == MSR_MTRRfix64K_00000)
1570 *pdata = p[0];
1571 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1572 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1573 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1574 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1575 else if (msr == MSR_IA32_CR_PAT)
1576 *pdata = vcpu->arch.pat;
1577 else { /* Variable MTRRs */
1578 int idx, is_mtrr_mask;
1579 u64 *pt;
1580
1581 idx = (msr - 0x200) / 2;
1582 is_mtrr_mask = msr - 0x200 - 2 * idx;
1583 if (!is_mtrr_mask)
1584 pt =
1585 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1586 else
1587 pt =
1588 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1589 *pdata = *pt;
1590 }
1591
9ba075a6
AK		 1592 return 0;
1593}
1594
890ca9ae 1595static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1596{
1597 u64 data;
890ca9ae
HY		 1598 u64 mcg_cap = vcpu->arch.mcg_cap;
1599 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1600
1601 switch (msr) {
15c4a640
CO		 1602 case MSR_IA32_P5_MC_ADDR:
1603 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1604 data = 0;
1605 break;
15c4a640 1606 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1607 data = vcpu->arch.mcg_cap;
1608 break;
c7ac679c 1609 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1610 if (!(mcg_cap & MCG_CTL_P))
1611 return 1;
1612 data = vcpu->arch.mcg_ctl;
1613 break;
1614 case MSR_IA32_MCG_STATUS:
1615 data = vcpu->arch.mcg_status;
1616 break;
1617 default:
1618 if (msr >= MSR_IA32_MC0_CTL &&
1619 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1620 u32 offset = msr - MSR_IA32_MC0_CTL;
1621 data = vcpu->arch.mce_banks[offset];
1622 break;
1623 }
1624 return 1;
1625 }
1626 *pdata = data;
1627 return 0;
1628}
1629
55cd8e5a
GN		 1630static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1631{
1632 u64 data = 0;
1633 struct kvm *kvm = vcpu->kvm;
1634
1635 switch (msr) {
1636 case HV_X64_MSR_GUEST_OS_ID:
1637 data = kvm->arch.hv_guest_os_id;
1638 break;
1639 case HV_X64_MSR_HYPERCALL:
1640 data = kvm->arch.hv_hypercall;
1641 break;
1642 default:
1643 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1644 return 1;
1645 }
1646
1647 *pdata = data;
1648 return 0;
1649}
1650
1651static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1652{
1653 u64 data = 0;
1654
1655 switch (msr) {
1656 case HV_X64_MSR_VP_INDEX: {
1657 int r;
1658 struct kvm_vcpu *v;
1659 kvm_for_each_vcpu(r, v, vcpu->kvm)
1660 if (v == vcpu)
1661 data = r;
1662 break;
1663 }
10388a07
GN		 1664 case HV_X64_MSR_EOI:
1665 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1666 case HV_X64_MSR_ICR:
1667 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1668 case HV_X64_MSR_TPR:
1669 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1670 default:
1671 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1672 return 1;
1673 }
1674 *pdata = data;
1675 return 0;
1676}
1677
890ca9ae
HY		 1678int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1679{
1680 u64 data;
1681
1682 switch (msr) {
890ca9ae 1683 case MSR_IA32_PLATFORM_ID:
15c4a640 1684 case MSR_IA32_UCODE_REV:
15c4a640 1685 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1686 case MSR_IA32_DEBUGCTLMSR:
1687 case MSR_IA32_LASTBRANCHFROMIP:
1688 case MSR_IA32_LASTBRANCHTOIP:
1689 case MSR_IA32_LASTINTFROMIP:
1690 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1691 case MSR_K8_SYSCFG:
1692 case MSR_K7_HWCR:
61a6bd67 1693 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1694 case MSR_P6_PERFCTR0:
1695 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1696 case MSR_P6_EVNTSEL0:
1697 case MSR_P6_EVNTSEL1:
9e699624 1698 case MSR_K7_EVNTSEL0:
1f3ee616 1699 case MSR_K7_PERFCTR0:
1fdbd48c 1700 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1701 case MSR_AMD64_NB_CFG:
f7c6d140 1702 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1703 data = 0;
1704 break;
9ba075a6
AK		 1705 case MSR_MTRRcap:
1706 data = 0x500 | KVM_NR_VAR_MTRR;
1707 break;
1708 case 0x200 ... 0x2ff:
1709 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1710 case 0xcd: /* fsb frequency */
1711 data = 3;
1712 break;
7b914098
JS		 1713 /*
1714 * MSR_EBC_FREQUENCY_ID
1715 * Conservative value valid for even the basic CPU models.
1716 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1717 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1718 * and 266MHz for model 3, or 4. Set Core Clock
1719 * Frequency to System Bus Frequency Ratio to 1 (bits
1720 * 31:24) even though these are only valid for CPU
1721 * models > 2, however guests may end up dividing or
1722 * multiplying by zero otherwise.
1723 */
1724 case MSR_EBC_FREQUENCY_ID:
1725 data = 1 << 24;
1726 break;
15c4a640
CO		 1727 case MSR_IA32_APICBASE:
1728 data = kvm_get_apic_base(vcpu);
1729 break;
0105d1a5
GN		 1730 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1731 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1732 break;
15c4a640 1733 case MSR_IA32_MISC_ENABLE:
ad312c7c 1734 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1735 break;
847f0ad8
AG		 1736 case MSR_IA32_PERF_STATUS:
1737 /* TSC increment by tick */
1738 data = 1000ULL;
1739 /* CPU multiplier */
1740 data |= (((uint64_t)4ULL) << 40);
1741 break;
15c4a640 1742 case MSR_EFER:
f6801dff 1743 data = vcpu->arch.efer;
15c4a640 1744 break;
18068523 1745 case MSR_KVM_WALL_CLOCK:
11c6bffa 1746 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1747 data = vcpu->kvm->arch.wall_clock;
1748 break;
1749 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1750 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1751 data = vcpu->arch.time;
1752 break;
890ca9ae
HY		 1753 case MSR_IA32_P5_MC_ADDR:
1754 case MSR_IA32_P5_MC_TYPE:
1755 case MSR_IA32_MCG_CAP:
1756 case MSR_IA32_MCG_CTL:
1757 case MSR_IA32_MCG_STATUS:
1758 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1759 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1760 case MSR_K7_CLK_CTL:
1761 /*
1762 * Provide expected ramp-up count for K7. All other
1763 * are set to zero, indicating minimum divisors for
1764 * every field.
1765 *
1766 * This prevents guest kernels on AMD host with CPU
1767 * type 6, model 8 and higher from exploding due to
1768 * the rdmsr failing.
1769 */
1770 data = 0x20000000;
1771 break;
55cd8e5a
GN		 1772 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1773 if (kvm_hv_msr_partition_wide(msr)) {
1774 int r;
1775 mutex_lock(&vcpu->kvm->lock);
1776 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1777 mutex_unlock(&vcpu->kvm->lock);
1778 return r;
1779 } else
1780 return get_msr_hyperv(vcpu, msr, pdata);
1781 break;
15c4a640 1782 default:
ed85c068
AP		 1783 if (!ignore_msrs) {
1784 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1785 return 1;
1786 } else {
1787 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1788 data = 0;
1789 }
1790 break;
15c4a640
CO		 1791 }
1792 *pdata = data;
1793 return 0;
1794}
1795EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1796
313a3dc7
CO		 1797/*
1798 * Read or write a bunch of msrs. All parameters are kernel addresses.
1799 *
1800 * @return number of msrs set successfully.
1801 */
1802static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1803 struct kvm_msr_entry *entries,
1804 int (*do_msr)(struct kvm_vcpu *vcpu,
1805 unsigned index, u64 *data))
1806{
f656ce01 1807 int i, idx;
313a3dc7 1808
f656ce01 1809 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1810 for (i = 0; i < msrs->nmsrs; ++i)
1811 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1812 break;
f656ce01 1813 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1814
313a3dc7
CO		 1815 return i;
1816}
1817
1818/*
1819 * Read or write a bunch of msrs. Parameters are user addresses.
1820 *
1821 * @return number of msrs set successfully.
1822 */
1823static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1824 int (*do_msr)(struct kvm_vcpu *vcpu,
1825 unsigned index, u64 *data),
1826 int writeback)
1827{
1828 struct kvm_msrs msrs;
1829 struct kvm_msr_entry *entries;
1830 int r, n;
1831 unsigned size;
1832
1833 r = -EFAULT;
1834 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1835 goto out;
1836
1837 r = -E2BIG;
1838 if (msrs.nmsrs >= MAX_IO_MSRS)
1839 goto out;
1840
1841 r = -ENOMEM;
1842 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1843 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1844 if (!entries)
1845 goto out;
1846
1847 r = -EFAULT;
1848 if (copy_from_user(entries, user_msrs->entries, size))
1849 goto out_free;
1850
1851 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1852 if (r < 0)
1853 goto out_free;
1854
1855 r = -EFAULT;
1856 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1857 goto out_free;
1858
1859 r = n;
1860
1861out_free:
7a73c028 1862 kfree(entries);
313a3dc7
CO		 1863out:
1864 return r;
1865}
1866
018d00d2
ZX		 1867int kvm_dev_ioctl_check_extension(long ext)
1868{
1869 int r;
1870
1871 switch (ext) {
1872 case KVM_CAP_IRQCHIP:
1873 case KVM_CAP_HLT:
1874 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1875 case KVM_CAP_SET_TSS_ADDR:
07716717 1876 case KVM_CAP_EXT_CPUID:
c8076604 1877 case KVM_CAP_CLOCKSOURCE:
7837699f 1878 case KVM_CAP_PIT:
a28e4f5a 1879 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1880 case KVM_CAP_MP_STATE:
ed848624 1881 case KVM_CAP_SYNC_MMU:
52d939a0 1882 case KVM_CAP_REINJECT_CONTROL:
4925663a 1883 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1884 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1885 case KVM_CAP_IRQFD:
d34e6b17 1886 case KVM_CAP_IOEVENTFD:
c5ff41ce 1887 case KVM_CAP_PIT2:
e9f42757 1888 case KVM_CAP_PIT_STATE2:
b927a3ce 1889 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1890 case KVM_CAP_XEN_HVM:
afbcf7ab 1891 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1892 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1893 case KVM_CAP_HYPERV:
10388a07 1894 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1895 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1896 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1897 case KVM_CAP_DEBUGREGS:
d2be1651 1898 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1899 case KVM_CAP_XSAVE:
018d00d2
ZX		 1900 r = 1;
1901 break;
542472b5
LV		 1902 case KVM_CAP_COALESCED_MMIO:
1903 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1904 break;
774ead3a
AK		 1905 case KVM_CAP_VAPIC:
1906 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1907 break;
f725230a
AK		 1908 case KVM_CAP_NR_VCPUS:
1909 r = KVM_MAX_VCPUS;
1910 break;
a988b910
AK		 1911 case KVM_CAP_NR_MEMSLOTS:
1912 r = KVM_MEMORY_SLOTS;
1913 break;
a68a6a72
MT		 1914 case KVM_CAP_PV_MMU: /* obsolete */
1915 r = 0;
2f333bcb 1916 break;
62c476c7 1917 case KVM_CAP_IOMMU:
19de40a8 1918 r = iommu_found();
62c476c7 1919 break;
890ca9ae
HY		 1920 case KVM_CAP_MCE:
1921 r = KVM_MAX_MCE_BANKS;
1922 break;
2d5b5a66
SY		 1923 case KVM_CAP_XCRS:
1924 r = cpu_has_xsave;
1925 break;
018d00d2
ZX		 1926 default:
1927 r = 0;
1928 break;
1929 }
1930 return r;
1931
1932}
1933
043405e1
CO		 1934long kvm_arch_dev_ioctl(struct file *filp,
1935 unsigned int ioctl, unsigned long arg)
1936{
1937 void __user *argp = (void __user *)arg;
1938 long r;
1939
1940 switch (ioctl) {
1941 case KVM_GET_MSR_INDEX_LIST: {
1942 struct kvm_msr_list __user *user_msr_list = argp;
1943 struct kvm_msr_list msr_list;
1944 unsigned n;
1945
1946 r = -EFAULT;
1947 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1948 goto out;
1949 n = msr_list.nmsrs;
1950 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1951 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1952 goto out;
1953 r = -E2BIG;
e125e7b6 1954 if (n < msr_list.nmsrs)
043405e1
CO		 1955 goto out;
1956 r = -EFAULT;
1957 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1958 num_msrs_to_save * sizeof(u32)))
1959 goto out;
e125e7b6 1960 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1961 &emulated_msrs,
1962 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1963 goto out;
1964 r = 0;
1965 break;
1966 }
674eea0f
AK		 1967 case KVM_GET_SUPPORTED_CPUID: {
1968 struct kvm_cpuid2 __user *cpuid_arg = argp;
1969 struct kvm_cpuid2 cpuid;
1970
1971 r = -EFAULT;
1972 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1973 goto out;
1974 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1975 cpuid_arg->entries);
674eea0f
AK		 1976 if (r)
1977 goto out;
1978
1979 r = -EFAULT;
1980 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1981 goto out;
1982 r = 0;
1983 break;
1984 }
890ca9ae
HY		 1985 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1986 u64 mce_cap;
1987
1988 mce_cap = KVM_MCE_CAP_SUPPORTED;
1989 r = -EFAULT;
1990 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1991 goto out;
1992 r = 0;
1993 break;
1994 }
043405e1
CO		 1995 default:
1996 r = -EINVAL;
1997 }
1998out:
1999 return r;
2000}
2001
f5f48ee1
SY		 2002static void wbinvd_ipi(void *garbage)
2003{
2004 wbinvd();
2005}
2006
2007static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2008{
2009 return vcpu->kvm->arch.iommu_domain &&
2010 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2011}
2012
313a3dc7
CO		 2013void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2014{
f5f48ee1
SY		 2015 /* Address WBINVD may be executed by guest */
2016 if (need_emulate_wbinvd(vcpu)) {
2017 if (kvm_x86_ops->has_wbinvd_exit())
2018 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2019 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2020 smp_call_function_single(vcpu->cpu,
2021 wbinvd_ipi, NULL, 1);
2022 }
2023
313a3dc7 2024 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2025 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2026 /* Make sure TSC doesn't go backwards */
2027 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2028 native_read_tsc() - vcpu->arch.last_host_tsc;
2029 if (tsc_delta < 0)
2030 mark_tsc_unstable("KVM discovered backwards TSC");
2031 if (check_tsc_unstable())
2032 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
2033 kvm_migrate_timers(vcpu);
2034 vcpu->cpu = cpu;
2035 }
313a3dc7
CO		 2036}
2037
2038void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2039{
02daab21 2040 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2041 kvm_put_guest_fpu(vcpu);
e48672fa 2042 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2043}
2044
07716717 2045static int is_efer_nx(void)
313a3dc7 2046{
e286e86e 2047 unsigned long long efer = 0;
313a3dc7 2048
e286e86e 2049 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2050 return efer & EFER_NX;
2051}
2052
2053static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2054{
2055 int i;
2056 struct kvm_cpuid_entry2 *e, *entry;
2057
313a3dc7 2058 entry = NULL;
ad312c7c
ZX		 2059 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2060 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2061 if (e->function == 0x80000001) {
2062 entry = e;
2063 break;
2064 }
2065 }
07716717 2066 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2067 entry->edx &= ~(1 << 20);
2068 printk(KERN_INFO "kvm: guest NX capability removed\n");
2069 }
2070}
2071
07716717 2072/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2073static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2074 struct kvm_cpuid *cpuid,
2075 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2076{
2077 int r, i;
2078 struct kvm_cpuid_entry *cpuid_entries;
2079
2080 r = -E2BIG;
2081 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2082 goto out;
2083 r = -ENOMEM;
2084 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2085 if (!cpuid_entries)
2086 goto out;
2087 r = -EFAULT;
2088 if (copy_from_user(cpuid_entries, entries,
2089 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2090 goto out_free;
2091 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2092 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2093 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2094 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2095 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2096 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2097 vcpu->arch.cpuid_entries[i].index = 0;
2098 vcpu->arch.cpuid_entries[i].flags = 0;
2099 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2100 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2101 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2102 }
2103 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2104 cpuid_fix_nx_cap(vcpu);
2105 r = 0;
fc61b800 2106 kvm_apic_set_version(vcpu);
0e851880 2107 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2108 update_cpuid(vcpu);
07716717
DK		 2109
2110out_free:
2111 vfree(cpuid_entries);
2112out:
2113 return r;
2114}
2115
2116static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2117 struct kvm_cpuid2 *cpuid,
2118 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2119{
2120 int r;
2121
2122 r = -E2BIG;
2123 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2124 goto out;
2125 r = -EFAULT;
ad312c7c 2126 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2127 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2128 goto out;
ad312c7c 2129 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2130 kvm_apic_set_version(vcpu);
0e851880 2131 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2132 update_cpuid(vcpu);
313a3dc7
CO		 2133 return 0;
2134
2135out:
2136 return r;
2137}
2138
07716717 2139static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2140 struct kvm_cpuid2 *cpuid,
2141 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2142{
2143 int r;
2144
2145 r = -E2BIG;
ad312c7c 2146 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2147 goto out;
2148 r = -EFAULT;
ad312c7c 2149 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2150 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2151 goto out;
2152 return 0;
2153
2154out:
ad312c7c 2155 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2156 return r;
2157}
2158
07716717 2159static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2160 u32 index)
07716717
DK		 2161{
2162 entry->function = function;
2163 entry->index = index;
2164 cpuid_count(entry->function, entry->index,
19355475 2165 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2166 entry->flags = 0;
2167}
2168
7faa4ee1
AK		 2169#define F(x) bit(X86_FEATURE_##x)
2170
07716717
DK		 2171static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2172 u32 index, int *nent, int maxnent)
2173{
7faa4ee1 2174 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2175#ifdef CONFIG_X86_64
17cc3935
SY		 2176 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2177 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2178 unsigned f_lm = F(LM);
2179#else
17cc3935 2180 unsigned f_gbpages = 0;
7faa4ee1 2181 unsigned f_lm = 0;
07716717 2182#endif
4e47c7a6 2183 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2184
2185 /* cpuid 1.edx */
2186 const u32 kvm_supported_word0_x86_features =
2187 F(FPU) | F(VME) | F(DE) | F(PSE) |
2188 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2189 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2190 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2191 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2192 0 /* Reserved, DS, ACPI */ | F(MMX) |
2193 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2194 0 /* HTT, TM, Reserved, PBE */;
2195 /* cpuid 0x80000001.edx */
2196 const u32 kvm_supported_word1_x86_features =
2197 F(FPU) | F(VME) | F(DE) | F(PSE) |
2198 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2199 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2200 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2201 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2202 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2203 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2204 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2205 /* cpuid 1.ecx */
2206 const u32 kvm_supported_word4_x86_features =
6c3f6041 2207 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2208 0 /* DS-CPL, VMX, SMX, EST */ |
2209 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2210 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2211 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2212 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6c3f6041 2213 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
7faa4ee1 2214 /* cpuid 0x80000001.ecx */
07716717 2215 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2216 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1
AK		 2217 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2218 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
2219 0 /* SKINIT */ | 0 /* WDT */;
07716717 2220
19355475 2221 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2222 get_cpu();
2223 do_cpuid_1_ent(entry, function, index);
2224 ++*nent;
2225
2226 switch (function) {
2227 case 0:
2acf923e 2228 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2229 break;
2230 case 1:
2231 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2232 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2233 /* we support x2apic emulation even if host does not support
2234 * it since we emulate x2apic in software */
2235 entry->ecx |= F(X2APIC);
07716717
DK		 2236 break;
2237 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2238 * may return different values. This forces us to get_cpu() before
2239 * issuing the first command, and also to emulate this annoying behavior
2240 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2241 case 2: {
2242 int t, times = entry->eax & 0xff;
2243
2244 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2245 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2246 for (t = 1; t < times && *nent < maxnent; ++t) {
2247 do_cpuid_1_ent(&entry[t], function, 0);
2248 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2249 ++*nent;
2250 }
2251 break;
2252 }
2253 /* function 4 and 0xb have additional index. */
2254 case 4: {
14af3f3c 2255 int i, cache_type;
07716717
DK		 2256
2257 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2258 /* read more entries until cache_type is zero */
14af3f3c
HH		 2259 for (i = 1; *nent < maxnent; ++i) {
2260 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2261 if (!cache_type)
2262 break;
14af3f3c
HH		 2263 do_cpuid_1_ent(&entry[i], function, i);
2264 entry[i].flags |=
07716717
DK		 2265 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2266 ++*nent;
2267 }
2268 break;
2269 }
2270 case 0xb: {
14af3f3c 2271 int i, level_type;
07716717
DK		 2272
2273 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2274 /* read more entries until level_type is zero */
14af3f3c 2275 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2276 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2277 if (!level_type)
2278 break;
14af3f3c
HH		 2279 do_cpuid_1_ent(&entry[i], function, i);
2280 entry[i].flags |=
07716717
DK		 2281 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2282 ++*nent;
2283 }
2284 break;
2285 }
2acf923e
DC		 2286 case 0xd: {
2287 int i;
2288
2289 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2290 for (i = 1; *nent < maxnent; ++i) {
2291 if (entry[i - 1].eax == 0 && i != 2)
2292 break;
2293 do_cpuid_1_ent(&entry[i], function, i);
2294 entry[i].flags |=
2295 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2296 ++*nent;
2297 }
2298 break;
2299 }
84478c82
GC		 2300 case KVM_CPUID_SIGNATURE: {
2301 char signature[12] = "KVMKVMKVM\0\0";
2302 u32 *sigptr = (u32 *)signature;
2303 entry->eax = 0;
2304 entry->ebx = sigptr[0];
2305 entry->ecx = sigptr[1];
2306 entry->edx = sigptr[2];
2307 break;
2308 }
2309 case KVM_CPUID_FEATURES:
2310 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2311 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2312 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2313 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2314 entry->ebx = 0;
2315 entry->ecx = 0;
2316 entry->edx = 0;
2317 break;
07716717
DK		 2318 case 0x80000000:
2319 entry->eax = min(entry->eax, 0x8000001a);
2320 break;
2321 case 0x80000001:
2322 entry->edx &= kvm_supported_word1_x86_features;
2323 entry->ecx &= kvm_supported_word6_x86_features;
2324 break;
2325 }
d4330ef2
JR		 2326
2327 kvm_x86_ops->set_supported_cpuid(function, entry);
2328
07716717
DK		 2329 put_cpu();
2330}
2331
7faa4ee1
AK		 2332#undef F
2333
674eea0f 2334static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2335 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2336{
2337 struct kvm_cpuid_entry2 *cpuid_entries;
2338 int limit, nent = 0, r = -E2BIG;
2339 u32 func;
2340
2341 if (cpuid->nent < 1)
2342 goto out;
6a544355
AK		 2343 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2344 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2345 r = -ENOMEM;
2346 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2347 if (!cpuid_entries)
2348 goto out;
2349
2350 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2351 limit = cpuid_entries[0].eax;
2352 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2353 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2354 &nent, cpuid->nent);
07716717
DK		 2355 r = -E2BIG;
2356 if (nent >= cpuid->nent)
2357 goto out_free;
2358
2359 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2360 limit = cpuid_entries[nent - 1].eax;
2361 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2362 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2363 &nent, cpuid->nent);
84478c82
GC		 2364
2365
2366
2367 r = -E2BIG;
2368 if (nent >= cpuid->nent)
2369 goto out_free;
2370
2371 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2372 cpuid->nent);
2373
2374 r = -E2BIG;
2375 if (nent >= cpuid->nent)
2376 goto out_free;
2377
2378 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2379 cpuid->nent);
2380
cb007648
MM		 2381 r = -E2BIG;
2382 if (nent >= cpuid->nent)
2383 goto out_free;
2384
07716717
DK		 2385 r = -EFAULT;
2386 if (copy_to_user(entries, cpuid_entries,
19355475 2387 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2388 goto out_free;
2389 cpuid->nent = nent;
2390 r = 0;
2391
2392out_free:
2393 vfree(cpuid_entries);
2394out:
2395 return r;
2396}
2397
313a3dc7
CO		 2398static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2399 struct kvm_lapic_state *s)
2400{
ad312c7c 2401 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2402
2403 return 0;
2404}
2405
2406static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2407 struct kvm_lapic_state *s)
2408{
ad312c7c 2409 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2410 kvm_apic_post_state_restore(vcpu);
cb142eb7 2411 update_cr8_intercept(vcpu);
313a3dc7
CO		 2412
2413 return 0;
2414}
2415
f77bc6a4
ZX		 2416static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2417 struct kvm_interrupt *irq)
2418{
2419 if (irq->irq < 0 || irq->irq >= 256)
2420 return -EINVAL;
2421 if (irqchip_in_kernel(vcpu->kvm))
2422 return -ENXIO;
f77bc6a4 2423
66fd3f7f 2424 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2425 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2426
f77bc6a4
ZX		 2427 return 0;
2428}
2429
c4abb7c9
JK		 2430static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2431{
c4abb7c9 2432 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2433
2434 return 0;
2435}
2436
b209749f
AK		 2437static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2438 struct kvm_tpr_access_ctl *tac)
2439{
2440 if (tac->flags)
2441 return -EINVAL;
2442 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2443 return 0;
2444}
2445
890ca9ae
HY		 2446static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2447 u64 mcg_cap)
2448{
2449 int r;
2450 unsigned bank_num = mcg_cap & 0xff, bank;
2451
2452 r = -EINVAL;
a9e38c3e 2453 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2454 goto out;
2455 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2456 goto out;
2457 r = 0;
2458 vcpu->arch.mcg_cap = mcg_cap;
2459 /* Init IA32_MCG_CTL to all 1s */
2460 if (mcg_cap & MCG_CTL_P)
2461 vcpu->arch.mcg_ctl = ~(u64)0;
2462 /* Init IA32_MCi_CTL to all 1s */
2463 for (bank = 0; bank < bank_num; bank++)
2464 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2465out:
2466 return r;
2467}
2468
2469static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2470 struct kvm_x86_mce *mce)
2471{
2472 u64 mcg_cap = vcpu->arch.mcg_cap;
2473 unsigned bank_num = mcg_cap & 0xff;
2474 u64 *banks = vcpu->arch.mce_banks;
2475
2476 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2477 return -EINVAL;
2478 /*
2479 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2480 * reporting is disabled
2481 */
2482 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2483 vcpu->arch.mcg_ctl != ~(u64)0)
2484 return 0;
2485 banks += 4 * mce->bank;
2486 /*
2487 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2488 * reporting is disabled for the bank
2489 */
2490 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2491 return 0;
2492 if (mce->status & MCI_STATUS_UC) {
2493 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2494 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2495 printk(KERN_DEBUG "kvm: set_mce: "
2496 "injects mce exception while "
2497 "previous one is in progress!\n");
a8eeb04a 2498 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2499 return 0;
2500 }
2501 if (banks[1] & MCI_STATUS_VAL)
2502 mce->status |= MCI_STATUS_OVER;
2503 banks[2] = mce->addr;
2504 banks[3] = mce->misc;
2505 vcpu->arch.mcg_status = mce->mcg_status;
2506 banks[1] = mce->status;
2507 kvm_queue_exception(vcpu, MC_VECTOR);
2508 } else if (!(banks[1] & MCI_STATUS_VAL)
2509 || !(banks[1] & MCI_STATUS_UC)) {
2510 if (banks[1] & MCI_STATUS_VAL)
2511 mce->status |= MCI_STATUS_OVER;
2512 banks[2] = mce->addr;
2513 banks[3] = mce->misc;
2514 banks[1] = mce->status;
2515 } else
2516 banks[1] |= MCI_STATUS_OVER;
2517 return 0;
2518}
2519
3cfc3092
JK		 2520static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2521 struct kvm_vcpu_events *events)
2522{
03b82a30
JK		 2523 events->exception.injected =
2524 vcpu->arch.exception.pending &&
2525 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2526 events->exception.nr = vcpu->arch.exception.nr;
2527 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2528 events->exception.error_code = vcpu->arch.exception.error_code;
2529
03b82a30
JK		 2530 events->interrupt.injected =
2531 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2532 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2533 events->interrupt.soft = 0;
48005f64
JK		 2534 events->interrupt.shadow =
2535 kvm_x86_ops->get_interrupt_shadow(vcpu,
2536 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2537
2538 events->nmi.injected = vcpu->arch.nmi_injected;
2539 events->nmi.pending = vcpu->arch.nmi_pending;
2540 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2541
2542 events->sipi_vector = vcpu->arch.sipi_vector;
2543
dab4b911 2544 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2545 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2546 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2547}
2548
2549static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2550 struct kvm_vcpu_events *events)
2551{
dab4b911 2552 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2553 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2554 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2555 return -EINVAL;
2556
3cfc3092
JK		 2557 vcpu->arch.exception.pending = events->exception.injected;
2558 vcpu->arch.exception.nr = events->exception.nr;
2559 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2560 vcpu->arch.exception.error_code = events->exception.error_code;
2561
2562 vcpu->arch.interrupt.pending = events->interrupt.injected;
2563 vcpu->arch.interrupt.nr = events->interrupt.nr;
2564 vcpu->arch.interrupt.soft = events->interrupt.soft;
2565 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2566 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2567 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2568 kvm_x86_ops->set_interrupt_shadow(vcpu,
2569 events->interrupt.shadow);
3cfc3092
JK		 2570
2571 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2572 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2573 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2574 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2575
dab4b911
JK		 2576 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2577 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2578
3842d135
AK		 2579 kvm_make_request(KVM_REQ_EVENT, vcpu);
2580
3cfc3092
JK		 2581 return 0;
2582}
2583
a1efbe77
JK		 2584static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2585 struct kvm_debugregs *dbgregs)
2586{
a1efbe77
JK		 2587 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2588 dbgregs->dr6 = vcpu->arch.dr6;
2589 dbgregs->dr7 = vcpu->arch.dr7;
2590 dbgregs->flags = 0;
a1efbe77
JK		 2591}
2592
2593static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2594 struct kvm_debugregs *dbgregs)
2595{
2596 if (dbgregs->flags)
2597 return -EINVAL;
2598
a1efbe77
JK		 2599 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2600 vcpu->arch.dr6 = dbgregs->dr6;
2601 vcpu->arch.dr7 = dbgregs->dr7;
2602
a1efbe77
JK		 2603 return 0;
2604}
2605
2d5b5a66
SY		 2606static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2607 struct kvm_xsave *guest_xsave)
2608{
2609 if (cpu_has_xsave)
2610 memcpy(guest_xsave->region,
2611 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2612 xstate_size);
2d5b5a66
SY		 2613 else {
2614 memcpy(guest_xsave->region,
2615 &vcpu->arch.guest_fpu.state->fxsave,
2616 sizeof(struct i387_fxsave_struct));
2617 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2618 XSTATE_FPSSE;
2619 }
2620}
2621
2622static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2623 struct kvm_xsave *guest_xsave)
2624{
2625 u64 xstate_bv =
2626 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2627
2628 if (cpu_has_xsave)
2629 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2630 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2631 else {
2632 if (xstate_bv & ~XSTATE_FPSSE)
2633 return -EINVAL;
2634 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2635 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2636 }
2637 return 0;
2638}
2639
2640static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2641 struct kvm_xcrs *guest_xcrs)
2642{
2643 if (!cpu_has_xsave) {
2644 guest_xcrs->nr_xcrs = 0;
2645 return;
2646 }
2647
2648 guest_xcrs->nr_xcrs = 1;
2649 guest_xcrs->flags = 0;
2650 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2651 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2652}
2653
2654static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2655 struct kvm_xcrs *guest_xcrs)
2656{
2657 int i, r = 0;
2658
2659 if (!cpu_has_xsave)
2660 return -EINVAL;
2661
2662 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2663 return -EINVAL;
2664
2665 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2666 /* Only support XCR0 currently */
2667 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2668 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2669 guest_xcrs->xcrs[0].value);
2670 break;
2671 }
2672 if (r)
2673 r = -EINVAL;
2674 return r;
2675}
2676
313a3dc7
CO		 2677long kvm_arch_vcpu_ioctl(struct file *filp,
2678 unsigned int ioctl, unsigned long arg)
2679{
2680 struct kvm_vcpu *vcpu = filp->private_data;
2681 void __user *argp = (void __user *)arg;
2682 int r;
d1ac91d8
AK		 2683 union {
2684 struct kvm_lapic_state *lapic;
2685 struct kvm_xsave *xsave;
2686 struct kvm_xcrs *xcrs;
2687 void *buffer;
2688 } u;
2689
2690 u.buffer = NULL;
313a3dc7
CO		 2691 switch (ioctl) {
2692 case KVM_GET_LAPIC: {
2204ae3c
MT		 2693 r = -EINVAL;
2694 if (!vcpu->arch.apic)
2695 goto out;
d1ac91d8 2696 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2697
b772ff36 2698 r = -ENOMEM;
d1ac91d8 2699 if (!u.lapic)
b772ff36 2700 goto out;
d1ac91d8 2701 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2702 if (r)
2703 goto out;
2704 r = -EFAULT;
d1ac91d8 2705 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2706 goto out;
2707 r = 0;
2708 break;
2709 }
2710 case KVM_SET_LAPIC: {
2204ae3c
MT		 2711 r = -EINVAL;
2712 if (!vcpu->arch.apic)
2713 goto out;
d1ac91d8 2714 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2715 r = -ENOMEM;
d1ac91d8 2716 if (!u.lapic)
b772ff36 2717 goto out;
313a3dc7 2718 r = -EFAULT;
d1ac91d8 2719 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2720 goto out;
d1ac91d8 2721 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2722 if (r)
2723 goto out;
2724 r = 0;
2725 break;
2726 }
f77bc6a4
ZX		 2727 case KVM_INTERRUPT: {
2728 struct kvm_interrupt irq;
2729
2730 r = -EFAULT;
2731 if (copy_from_user(&irq, argp, sizeof irq))
2732 goto out;
2733 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2734 if (r)
2735 goto out;
2736 r = 0;
2737 break;
2738 }
c4abb7c9
JK		 2739 case KVM_NMI: {
2740 r = kvm_vcpu_ioctl_nmi(vcpu);
2741 if (r)
2742 goto out;
2743 r = 0;
2744 break;
2745 }
313a3dc7
CO		 2746 case KVM_SET_CPUID: {
2747 struct kvm_cpuid __user *cpuid_arg = argp;
2748 struct kvm_cpuid cpuid;
2749
2750 r = -EFAULT;
2751 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2752 goto out;
2753 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2754 if (r)
2755 goto out;
2756 break;
2757 }
07716717
DK		 2758 case KVM_SET_CPUID2: {
2759 struct kvm_cpuid2 __user *cpuid_arg = argp;
2760 struct kvm_cpuid2 cpuid;
2761
2762 r = -EFAULT;
2763 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2764 goto out;
2765 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2766 cpuid_arg->entries);
07716717
DK		 2767 if (r)
2768 goto out;
2769 break;
2770 }
2771 case KVM_GET_CPUID2: {
2772 struct kvm_cpuid2 __user *cpuid_arg = argp;
2773 struct kvm_cpuid2 cpuid;
2774
2775 r = -EFAULT;
2776 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2777 goto out;
2778 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2779 cpuid_arg->entries);
07716717
DK		 2780 if (r)
2781 goto out;
2782 r = -EFAULT;
2783 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2784 goto out;
2785 r = 0;
2786 break;
2787 }
313a3dc7
CO		 2788 case KVM_GET_MSRS:
2789 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2790 break;
2791 case KVM_SET_MSRS:
2792 r = msr_io(vcpu, argp, do_set_msr, 0);
2793 break;
b209749f
AK		 2794 case KVM_TPR_ACCESS_REPORTING: {
2795 struct kvm_tpr_access_ctl tac;
2796
2797 r = -EFAULT;
2798 if (copy_from_user(&tac, argp, sizeof tac))
2799 goto out;
2800 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2801 if (r)
2802 goto out;
2803 r = -EFAULT;
2804 if (copy_to_user(argp, &tac, sizeof tac))
2805 goto out;
2806 r = 0;
2807 break;
2808 };
b93463aa
AK		 2809 case KVM_SET_VAPIC_ADDR: {
2810 struct kvm_vapic_addr va;
2811
2812 r = -EINVAL;
2813 if (!irqchip_in_kernel(vcpu->kvm))
2814 goto out;
2815 r = -EFAULT;
2816 if (copy_from_user(&va, argp, sizeof va))
2817 goto out;
2818 r = 0;
2819 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2820 break;
2821 }
890ca9ae
HY		 2822 case KVM_X86_SETUP_MCE: {
2823 u64 mcg_cap;
2824
2825 r = -EFAULT;
2826 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2827 goto out;
2828 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2829 break;
2830 }
2831 case KVM_X86_SET_MCE: {
2832 struct kvm_x86_mce mce;
2833
2834 r = -EFAULT;
2835 if (copy_from_user(&mce, argp, sizeof mce))
2836 goto out;
2837 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2838 break;
2839 }
3cfc3092
JK		 2840 case KVM_GET_VCPU_EVENTS: {
2841 struct kvm_vcpu_events events;
2842
2843 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2844
2845 r = -EFAULT;
2846 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2847 break;
2848 r = 0;
2849 break;
2850 }
2851 case KVM_SET_VCPU_EVENTS: {
2852 struct kvm_vcpu_events events;
2853
2854 r = -EFAULT;
2855 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2856 break;
2857
2858 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2859 break;
2860 }
a1efbe77
JK		 2861 case KVM_GET_DEBUGREGS: {
2862 struct kvm_debugregs dbgregs;
2863
2864 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2865
2866 r = -EFAULT;
2867 if (copy_to_user(argp, &dbgregs,
2868 sizeof(struct kvm_debugregs)))
2869 break;
2870 r = 0;
2871 break;
2872 }
2873 case KVM_SET_DEBUGREGS: {
2874 struct kvm_debugregs dbgregs;
2875
2876 r = -EFAULT;
2877 if (copy_from_user(&dbgregs, argp,
2878 sizeof(struct kvm_debugregs)))
2879 break;
2880
2881 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2882 break;
2883 }
2d5b5a66 2884 case KVM_GET_XSAVE: {
d1ac91d8 2885 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2886 r = -ENOMEM;
d1ac91d8 2887 if (!u.xsave)
2d5b5a66
SY		 2888 break;
2889
d1ac91d8 2890 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2891
2892 r = -EFAULT;
d1ac91d8 2893 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2894 break;
2895 r = 0;
2896 break;
2897 }
2898 case KVM_SET_XSAVE: {
d1ac91d8 2899 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2900 r = -ENOMEM;
d1ac91d8 2901 if (!u.xsave)
2d5b5a66
SY		 2902 break;
2903
2904 r = -EFAULT;
d1ac91d8 2905 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2906 break;
2907
d1ac91d8 2908 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2909 break;
2910 }
2911 case KVM_GET_XCRS: {
d1ac91d8 2912 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2913 r = -ENOMEM;
d1ac91d8 2914 if (!u.xcrs)
2d5b5a66
SY		 2915 break;
2916
d1ac91d8 2917 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2918
2919 r = -EFAULT;
d1ac91d8 2920 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2921 sizeof(struct kvm_xcrs)))
2922 break;
2923 r = 0;
2924 break;
2925 }
2926 case KVM_SET_XCRS: {
d1ac91d8 2927 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2928 r = -ENOMEM;
d1ac91d8 2929 if (!u.xcrs)
2d5b5a66
SY		 2930 break;
2931
2932 r = -EFAULT;
d1ac91d8 2933 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2934 sizeof(struct kvm_xcrs)))
2935 break;
2936
d1ac91d8 2937 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2938 break;
2939 }
313a3dc7
CO		 2940 default:
2941 r = -EINVAL;
2942 }
2943out:
d1ac91d8 2944 kfree(u.buffer);
313a3dc7
CO		 2945 return r;
2946}
2947
1fe779f8
CO		 2948static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2949{
2950 int ret;
2951
2952 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2953 return -1;
2954 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2955 return ret;
2956}
2957
b927a3ce
SY		 2958static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2959 u64 ident_addr)
2960{
2961 kvm->arch.ept_identity_map_addr = ident_addr;
2962 return 0;
2963}
2964
1fe779f8
CO		 2965static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2966 u32 kvm_nr_mmu_pages)
2967{
2968 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2969 return -EINVAL;
2970
79fac95e 2971 mutex_lock(&kvm->slots_lock);
7c8a83b7 2972 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2973
2974 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2975 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2976
7c8a83b7 2977 spin_unlock(&kvm->mmu_lock);
79fac95e 2978 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2979 return 0;
2980}
2981
2982static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2983{
39de71ec 2984 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2985}
2986
1fe779f8
CO		 2987static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2988{
2989 int r;
2990
2991 r = 0;
2992 switch (chip->chip_id) {
2993 case KVM_IRQCHIP_PIC_MASTER:
2994 memcpy(&chip->chip.pic,
2995 &pic_irqchip(kvm)->pics[0],
2996 sizeof(struct kvm_pic_state));
2997 break;
2998 case KVM_IRQCHIP_PIC_SLAVE:
2999 memcpy(&chip->chip.pic,
3000 &pic_irqchip(kvm)->pics[1],
3001 sizeof(struct kvm_pic_state));
3002 break;
3003 case KVM_IRQCHIP_IOAPIC:
eba0226b 3004 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3005 break;
3006 default:
3007 r = -EINVAL;
3008 break;
3009 }
3010 return r;
3011}
3012
3013static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3014{
3015 int r;
3016
3017 r = 0;
3018 switch (chip->chip_id) {
3019 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3020 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3021 memcpy(&pic_irqchip(kvm)->pics[0],
3022 &chip->chip.pic,
3023 sizeof(struct kvm_pic_state));
f4f51050 3024 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3025 break;
3026 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3027 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3028 memcpy(&pic_irqchip(kvm)->pics[1],
3029 &chip->chip.pic,
3030 sizeof(struct kvm_pic_state));
f4f51050 3031 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3032 break;
3033 case KVM_IRQCHIP_IOAPIC:
eba0226b 3034 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3035 break;
3036 default:
3037 r = -EINVAL;
3038 break;
3039 }
3040 kvm_pic_update_irq(pic_irqchip(kvm));
3041 return r;
3042}
3043
e0f63cb9
SY		 3044static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3045{
3046 int r = 0;
3047
894a9c55 3048 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3049 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3050 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3051 return r;
3052}
3053
3054static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3055{
3056 int r = 0;
3057
894a9c55 3058 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3059 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3060 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3061 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3062 return r;
3063}
3064
3065static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3066{
3067 int r = 0;
3068
3069 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3070 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3071 sizeof(ps->channels));
3072 ps->flags = kvm->arch.vpit->pit_state.flags;
3073 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3074 return r;
3075}
3076
3077static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3078{
3079 int r = 0, start = 0;
3080 u32 prev_legacy, cur_legacy;
3081 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3082 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3083 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3084 if (!prev_legacy && cur_legacy)
3085 start = 1;
3086 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3087 sizeof(kvm->arch.vpit->pit_state.channels));
3088 kvm->arch.vpit->pit_state.flags = ps->flags;
3089 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3090 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3091 return r;
3092}
3093
52d939a0
MT		 3094static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3095 struct kvm_reinject_control *control)
3096{
3097 if (!kvm->arch.vpit)
3098 return -ENXIO;
894a9c55 3099 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3100 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3101 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3102 return 0;
3103}
3104
5bb064dc
ZX		 3105/*
3106 * Get (and clear) the dirty memory log for a memory slot.
3107 */
3108int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3109 struct kvm_dirty_log *log)
3110{
87bf6e7d 3111 int r, i;
5bb064dc 3112 struct kvm_memory_slot *memslot;
87bf6e7d 3113 unsigned long n;
b050b015 3114 unsigned long is_dirty = 0;
5bb064dc 3115
79fac95e 3116 mutex_lock(&kvm->slots_lock);
5bb064dc 3117
b050b015
MT		 3118 r = -EINVAL;
3119 if (log->slot >= KVM_MEMORY_SLOTS)
3120 goto out;
3121
3122 memslot = &kvm->memslots->memslots[log->slot];
3123 r = -ENOENT;
3124 if (!memslot->dirty_bitmap)
3125 goto out;
3126
87bf6e7d 3127 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3128
b050b015
MT		 3129 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3130 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3131
3132 /* If nothing is dirty, don't bother messing with page tables. */
3133 if (is_dirty) {
b050b015 3134 struct kvm_memslots *slots, *old_slots;
914ebccd 3135 unsigned long *dirty_bitmap;
b050b015 3136
7c8a83b7 3137 spin_lock(&kvm->mmu_lock);
5bb064dc 3138 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 3139 spin_unlock(&kvm->mmu_lock);
b050b015 3140
914ebccd
TY		 3141 r = -ENOMEM;
3142 dirty_bitmap = vmalloc(n);
3143 if (!dirty_bitmap)
3144 goto out;
3145 memset(dirty_bitmap, 0, n);
b050b015 3146
914ebccd
TY		 3147 r = -ENOMEM;
3148 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3149 if (!slots) {
3150 vfree(dirty_bitmap);
3151 goto out;
3152 }
b050b015
MT		 3153 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3154 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3155
3156 old_slots = kvm->memslots;
3157 rcu_assign_pointer(kvm->memslots, slots);
3158 synchronize_srcu_expedited(&kvm->srcu);
3159 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3160 kfree(old_slots);
914ebccd
TY		 3161
3162 r = -EFAULT;
3163 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3164 vfree(dirty_bitmap);
3165 goto out;
3166 }
3167 vfree(dirty_bitmap);
3168 } else {
3169 r = -EFAULT;
3170 if (clear_user(log->dirty_bitmap, n))
3171 goto out;
5bb064dc 3172 }
b050b015 3173
5bb064dc
ZX		 3174 r = 0;
3175out:
79fac95e 3176 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3177 return r;
3178}
3179
1fe779f8
CO		 3180long kvm_arch_vm_ioctl(struct file *filp,
3181 unsigned int ioctl, unsigned long arg)
3182{
3183 struct kvm *kvm = filp->private_data;
3184 void __user *argp = (void __user *)arg;
367e1319 3185 int r = -ENOTTY;
f0d66275
DH		 3186 /*
3187 * This union makes it completely explicit to gcc-3.x
3188 * that these two variables' stack usage should be
3189 * combined, not added together.
3190 */
3191 union {
3192 struct kvm_pit_state ps;
e9f42757 3193 struct kvm_pit_state2 ps2;
c5ff41ce 3194 struct kvm_pit_config pit_config;
f0d66275 3195 } u;
1fe779f8
CO		 3196
3197 switch (ioctl) {
3198 case KVM_SET_TSS_ADDR:
3199 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3200 if (r < 0)
3201 goto out;
3202 break;
b927a3ce
SY		 3203 case KVM_SET_IDENTITY_MAP_ADDR: {
3204 u64 ident_addr;
3205
3206 r = -EFAULT;
3207 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3208 goto out;
3209 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3210 if (r < 0)
3211 goto out;
3212 break;
3213 }
1fe779f8
CO		 3214 case KVM_SET_NR_MMU_PAGES:
3215 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3216 if (r)
3217 goto out;
3218 break;
3219 case KVM_GET_NR_MMU_PAGES:
3220 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3221 break;
3ddea128
MT		 3222 case KVM_CREATE_IRQCHIP: {
3223 struct kvm_pic *vpic;
3224
3225 mutex_lock(&kvm->lock);
3226 r = -EEXIST;
3227 if (kvm->arch.vpic)
3228 goto create_irqchip_unlock;
1fe779f8 3229 r = -ENOMEM;
3ddea128
MT		 3230 vpic = kvm_create_pic(kvm);
3231 if (vpic) {
1fe779f8
CO		 3232 r = kvm_ioapic_init(kvm);
3233 if (r) {
72bb2fcd
WY		 3234 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3235 &vpic->dev);
3ddea128
MT		 3236 kfree(vpic);
3237 goto create_irqchip_unlock;
1fe779f8
CO		 3238 }
3239 } else
3ddea128
MT		 3240 goto create_irqchip_unlock;
3241 smp_wmb();
3242 kvm->arch.vpic = vpic;
3243 smp_wmb();
399ec807
AK		 3244 r = kvm_setup_default_irq_routing(kvm);
3245 if (r) {
3ddea128 3246 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3247 kvm_ioapic_destroy(kvm);
3248 kvm_destroy_pic(kvm);
3ddea128 3249 mutex_unlock(&kvm->irq_lock);
399ec807 3250 }
3ddea128
MT		 3251 create_irqchip_unlock:
3252 mutex_unlock(&kvm->lock);
1fe779f8 3253 break;
3ddea128 3254 }
7837699f 3255 case KVM_CREATE_PIT:
c5ff41ce
JK		 3256 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3257 goto create_pit;
3258 case KVM_CREATE_PIT2:
3259 r = -EFAULT;
3260 if (copy_from_user(&u.pit_config, argp,
3261 sizeof(struct kvm_pit_config)))
3262 goto out;
3263 create_pit:
79fac95e 3264 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3265 r = -EEXIST;
3266 if (kvm->arch.vpit)
3267 goto create_pit_unlock;
7837699f 3268 r = -ENOMEM;
c5ff41ce 3269 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3270 if (kvm->arch.vpit)
3271 r = 0;
269e05e4 3272 create_pit_unlock:
79fac95e 3273 mutex_unlock(&kvm->slots_lock);
7837699f 3274 break;
4925663a 3275 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3276 case KVM_IRQ_LINE: {
3277 struct kvm_irq_level irq_event;
3278
3279 r = -EFAULT;
3280 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3281 goto out;
160d2f6c 3282 r = -ENXIO;
1fe779f8 3283 if (irqchip_in_kernel(kvm)) {
4925663a 3284 __s32 status;
4925663a
GN		 3285 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3286 irq_event.irq, irq_event.level);
4925663a 3287 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3288 r = -EFAULT;
4925663a
GN		 3289 irq_event.status = status;
3290 if (copy_to_user(argp, &irq_event,
3291 sizeof irq_event))
3292 goto out;
3293 }
1fe779f8
CO		 3294 r = 0;
3295 }
3296 break;
3297 }
3298 case KVM_GET_IRQCHIP: {
3299 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3300 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3301
f0d66275
DH		 3302 r = -ENOMEM;
3303 if (!chip)
1fe779f8 3304 goto out;
f0d66275
DH		 3305 r = -EFAULT;
3306 if (copy_from_user(chip, argp, sizeof *chip))
3307 goto get_irqchip_out;
1fe779f8
CO		 3308 r = -ENXIO;
3309 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3310 goto get_irqchip_out;
3311 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3312 if (r)
f0d66275 3313 goto get_irqchip_out;
1fe779f8 3314 r = -EFAULT;
f0d66275
DH		 3315 if (copy_to_user(argp, chip, sizeof *chip))
3316 goto get_irqchip_out;
1fe779f8 3317 r = 0;
f0d66275
DH		 3318 get_irqchip_out:
3319 kfree(chip);
3320 if (r)
3321 goto out;
1fe779f8
CO		 3322 break;
3323 }
3324 case KVM_SET_IRQCHIP: {
3325 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3326 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3327
f0d66275
DH		 3328 r = -ENOMEM;
3329 if (!chip)
1fe779f8 3330 goto out;
f0d66275
DH		 3331 r = -EFAULT;
3332 if (copy_from_user(chip, argp, sizeof *chip))
3333 goto set_irqchip_out;
1fe779f8
CO		 3334 r = -ENXIO;
3335 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3336 goto set_irqchip_out;
3337 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3338 if (r)
f0d66275 3339 goto set_irqchip_out;
1fe779f8 3340 r = 0;
f0d66275
DH		 3341 set_irqchip_out:
3342 kfree(chip);
3343 if (r)
3344 goto out;
1fe779f8
CO		 3345 break;
3346 }
e0f63cb9 3347 case KVM_GET_PIT: {
e0f63cb9 3348 r = -EFAULT;
f0d66275 3349 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3350 goto out;
3351 r = -ENXIO;
3352 if (!kvm->arch.vpit)
3353 goto out;
f0d66275 3354 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3355 if (r)
3356 goto out;
3357 r = -EFAULT;
f0d66275 3358 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3359 goto out;
3360 r = 0;
3361 break;
3362 }
3363 case KVM_SET_PIT: {
e0f63cb9 3364 r = -EFAULT;
f0d66275 3365 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3366 goto out;
3367 r = -ENXIO;
3368 if (!kvm->arch.vpit)
3369 goto out;
f0d66275 3370 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3371 if (r)
3372 goto out;
3373 r = 0;
3374 break;
3375 }
e9f42757
BK		 3376 case KVM_GET_PIT2: {
3377 r = -ENXIO;
3378 if (!kvm->arch.vpit)
3379 goto out;
3380 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3381 if (r)
3382 goto out;
3383 r = -EFAULT;
3384 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3385 goto out;
3386 r = 0;
3387 break;
3388 }
3389 case KVM_SET_PIT2: {
3390 r = -EFAULT;
3391 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3392 goto out;
3393 r = -ENXIO;
3394 if (!kvm->arch.vpit)
3395 goto out;
3396 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3397 if (r)
3398 goto out;
3399 r = 0;
3400 break;
3401 }
52d939a0
MT		 3402 case KVM_REINJECT_CONTROL: {
3403 struct kvm_reinject_control control;
3404 r = -EFAULT;
3405 if (copy_from_user(&control, argp, sizeof(control)))
3406 goto out;
3407 r = kvm_vm_ioctl_reinject(kvm, &control);
3408 if (r)
3409 goto out;
3410 r = 0;
3411 break;
3412 }
ffde22ac
ES		 3413 case KVM_XEN_HVM_CONFIG: {
3414 r = -EFAULT;
3415 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3416 sizeof(struct kvm_xen_hvm_config)))
3417 goto out;
3418 r = -EINVAL;
3419 if (kvm->arch.xen_hvm_config.flags)
3420 goto out;
3421 r = 0;
3422 break;
3423 }
afbcf7ab 3424 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3425 struct kvm_clock_data user_ns;
3426 u64 now_ns;
3427 s64 delta;
3428
3429 r = -EFAULT;
3430 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3431 goto out;
3432
3433 r = -EINVAL;
3434 if (user_ns.flags)
3435 goto out;
3436
3437 r = 0;
759379dd 3438 now_ns = get_kernel_ns();
afbcf7ab
GC		 3439 delta = user_ns.clock - now_ns;
3440 kvm->arch.kvmclock_offset = delta;
3441 break;
3442 }
3443 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3444 struct kvm_clock_data user_ns;
3445 u64 now_ns;
3446
759379dd 3447 now_ns = get_kernel_ns();
afbcf7ab
GC		 3448 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3449 user_ns.flags = 0;
3450
3451 r = -EFAULT;
3452 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3453 goto out;
3454 r = 0;
3455 break;
3456 }
3457
1fe779f8
CO		 3458 default:
3459 ;
3460 }
3461out:
3462 return r;
3463}
3464
a16b043c 3465static void kvm_init_msr_list(void)
043405e1
CO		 3466{
3467 u32 dummy[2];
3468 unsigned i, j;
3469
e3267cbb
GC		 3470 /* skip the first msrs in the list. KVM-specific */
3471 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3472 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3473 continue;
3474 if (j < i)
3475 msrs_to_save[j] = msrs_to_save[i];
3476 j++;
3477 }
3478 num_msrs_to_save = j;
3479}
3480
bda9020e
MT		 3481static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3482 const void *v)
bbd9b64e 3483{
bda9020e
MT		 3484 if (vcpu->arch.apic &&
3485 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3486 return 0;
bbd9b64e 3487
e93f8a0f 3488 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3489}
3490
bda9020e 3491static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3492{
bda9020e
MT		 3493 if (vcpu->arch.apic &&
3494 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3495 return 0;
bbd9b64e 3496
e93f8a0f 3497 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3498}
3499
2dafc6c2
GN		 3500static void kvm_set_segment(struct kvm_vcpu *vcpu,
3501 struct kvm_segment *var, int seg)
3502{
3503 kvm_x86_ops->set_segment(vcpu, var, seg);
3504}
3505
3506void kvm_get_segment(struct kvm_vcpu *vcpu,
3507 struct kvm_segment *var, int seg)
3508{
3509 kvm_x86_ops->get_segment(vcpu, var, seg);
3510}
3511
c30a358d
JR		 3512static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3513{
3514 return gpa;
3515}
3516
02f59dc9
JR		 3517static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3518{
3519 gpa_t t_gpa;
3520 u32 error;
3521
3522 BUG_ON(!mmu_is_nested(vcpu));
3523
3524 /* NPT walks are always user-walks */
3525 access |= PFERR_USER_MASK;
3526 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &error);
3527 if (t_gpa == UNMAPPED_GVA)
0959ffac 3528 vcpu->arch.fault.nested = true;
02f59dc9
JR		 3529
3530 return t_gpa;
3531}
3532
1871c602
GN		 3533gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3534{
3535 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
14dfe855 3536 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3537}
3538
3539 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3540{
3541 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3542 access |= PFERR_FETCH_MASK;
14dfe855 3543 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3544}
3545
3546gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3547{
3548 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3549 access |= PFERR_WRITE_MASK;
14dfe855 3550 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3551}
3552
3553/* uses this to access any guest's mapped memory without checking CPL */
3554gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3555{
14dfe855 3556 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error);
1871c602
GN		 3557}
3558
3559static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3560 struct kvm_vcpu *vcpu, u32 access,
3561 u32 *error)
bbd9b64e
CO		 3562{
3563 void *data = val;
10589a46 3564 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3565
3566 while (bytes) {
14dfe855
JR		 3567 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3568 error);
bbd9b64e 3569 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3570 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3571 int ret;
3572
10589a46
MT		 3573 if (gpa == UNMAPPED_GVA) {
3574 r = X86EMUL_PROPAGATE_FAULT;
3575 goto out;
3576 }
77c2002e 3577 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3578 if (ret < 0) {
c3cd7ffa 3579 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3580 goto out;
3581 }
bbd9b64e 3582
77c2002e
IE		 3583 bytes -= toread;
3584 data += toread;
3585 addr += toread;
bbd9b64e 3586 }
10589a46 3587out:
10589a46 3588 return r;
bbd9b64e 3589}
77c2002e 3590
1871c602
GN		 3591/* used for instruction fetching */
3592static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3593 struct kvm_vcpu *vcpu, u32 *error)
3594{
3595 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3596 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3597 access | PFERR_FETCH_MASK, error);
3598}
3599
3600static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3601 struct kvm_vcpu *vcpu, u32 *error)
3602{
3603 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3604 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3605 error);
3606}
3607
3608static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3609 struct kvm_vcpu *vcpu, u32 *error)
3610{
3611 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3612}
3613
7972995b 3614static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3615 unsigned int bytes,
7972995b 3616 struct kvm_vcpu *vcpu,
2dafc6c2 3617 u32 *error)
77c2002e
IE		 3618{
3619 void *data = val;
3620 int r = X86EMUL_CONTINUE;
3621
3622 while (bytes) {
14dfe855
JR		 3623 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3624 PFERR_WRITE_MASK,
3625 error);
77c2002e
IE		 3626 unsigned offset = addr & (PAGE_SIZE-1);
3627 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3628 int ret;
3629
3630 if (gpa == UNMAPPED_GVA) {
3631 r = X86EMUL_PROPAGATE_FAULT;
3632 goto out;
3633 }
3634 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3635 if (ret < 0) {
c3cd7ffa 3636 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3637 goto out;
3638 }
3639
3640 bytes -= towrite;
3641 data += towrite;
3642 addr += towrite;
3643 }
3644out:
3645 return r;
3646}
3647
bbd9b64e
CO		 3648static int emulator_read_emulated(unsigned long addr,
3649 void *val,
3650 unsigned int bytes,
8fe681e9 3651 unsigned int *error_code,
bbd9b64e
CO		 3652 struct kvm_vcpu *vcpu)
3653{
bbd9b64e
CO		 3654 gpa_t gpa;
3655
3656 if (vcpu->mmio_read_completed) {
3657 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3658 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3659 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3660 vcpu->mmio_read_completed = 0;
3661 return X86EMUL_CONTINUE;
3662 }
3663
8fe681e9 3664 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3665
8fe681e9 3666 if (gpa == UNMAPPED_GVA)
1871c602 3667 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3668
3669 /* For APIC access vmexit */
3670 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3671 goto mmio;
3672
1871c602 3673 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3674 == X86EMUL_CONTINUE)
bbd9b64e 3675 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3676
3677mmio:
3678 /*
3679 * Is this MMIO handled locally?
3680 */
aec51dc4
AK		 3681 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3682 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3683 return X86EMUL_CONTINUE;
3684 }
aec51dc4
AK		 3685
3686 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3687
3688 vcpu->mmio_needed = 1;
411c35b7
GN		 3689 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3690 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3691 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3692 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3693
c3cd7ffa 3694 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3695}
3696
3200f405 3697int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3698 const void *val, int bytes)
bbd9b64e
CO		 3699{
3700 int ret;
3701
3702 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3703 if (ret < 0)
bbd9b64e 3704 return 0;
ad218f85 3705 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3706 return 1;
3707}
3708
3709static int emulator_write_emulated_onepage(unsigned long addr,
3710 const void *val,
3711 unsigned int bytes,
8fe681e9 3712 unsigned int *error_code,
bbd9b64e
CO		 3713 struct kvm_vcpu *vcpu)
3714{
10589a46
MT		 3715 gpa_t gpa;
3716
8fe681e9 3717 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3718
8fe681e9 3719 if (gpa == UNMAPPED_GVA)
bbd9b64e 3720 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3721
3722 /* For APIC access vmexit */
3723 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3724 goto mmio;
3725
3726 if (emulator_write_phys(vcpu, gpa, val, bytes))
3727 return X86EMUL_CONTINUE;
3728
3729mmio:
aec51dc4 3730 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3731 /*
3732 * Is this MMIO handled locally?
3733 */
bda9020e 3734 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3735 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3736
3737 vcpu->mmio_needed = 1;
411c35b7
GN		 3738 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3739 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3740 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3741 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3742 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3743
3744 return X86EMUL_CONTINUE;
3745}
3746
3747int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3748 const void *val,
3749 unsigned int bytes,
8fe681e9 3750 unsigned int *error_code,
8f6abd06 3751 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3752{
3753 /* Crossing a page boundary? */
3754 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3755 int rc, now;
3756
3757 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3758 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3759 vcpu);
bbd9b64e
CO		 3760 if (rc != X86EMUL_CONTINUE)
3761 return rc;
3762 addr += now;
3763 val += now;
3764 bytes -= now;
3765 }
8fe681e9
GN		 3766 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3767 vcpu);
bbd9b64e 3768}
bbd9b64e 3769
daea3e73
AK		 3770#define CMPXCHG_TYPE(t, ptr, old, new) \
3771 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3772
3773#ifdef CONFIG_X86_64
3774# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3775#else
3776# define CMPXCHG64(ptr, old, new) \
9749a6c0 3777 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3778#endif
3779
bbd9b64e
CO		 3780static int emulator_cmpxchg_emulated(unsigned long addr,
3781 const void *old,
3782 const void *new,
3783 unsigned int bytes,
8fe681e9 3784 unsigned int *error_code,
bbd9b64e
CO		 3785 struct kvm_vcpu *vcpu)
3786{
daea3e73
AK		 3787 gpa_t gpa;
3788 struct page *page;
3789 char *kaddr;
3790 bool exchanged;
2bacc55c 3791
daea3e73
AK		 3792 /* guests cmpxchg8b have to be emulated atomically */
3793 if (bytes > 8 || (bytes & (bytes - 1)))
3794 goto emul_write;
10589a46 3795
daea3e73 3796 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3797
daea3e73
AK		 3798 if (gpa == UNMAPPED_GVA ||
3799 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3800 goto emul_write;
2bacc55c 3801
daea3e73
AK		 3802 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3803 goto emul_write;
72dc67a6 3804
daea3e73 3805 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3806 if (is_error_page(page)) {
3807 kvm_release_page_clean(page);
3808 goto emul_write;
3809 }
72dc67a6 3810
daea3e73
AK		 3811 kaddr = kmap_atomic(page, KM_USER0);
3812 kaddr += offset_in_page(gpa);
3813 switch (bytes) {
3814 case 1:
3815 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3816 break;
3817 case 2:
3818 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3819 break;
3820 case 4:
3821 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3822 break;
3823 case 8:
3824 exchanged = CMPXCHG64(kaddr, old, new);
3825 break;
3826 default:
3827 BUG();
2bacc55c 3828 }
daea3e73
AK		 3829 kunmap_atomic(kaddr, KM_USER0);
3830 kvm_release_page_dirty(page);
3831
3832 if (!exchanged)
3833 return X86EMUL_CMPXCHG_FAILED;
3834
8f6abd06
GN		 3835 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3836
3837 return X86EMUL_CONTINUE;
4a5f48f6 3838
3200f405 3839emul_write:
daea3e73 3840 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3841
8fe681e9 3842 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3843}
3844
cf8f70bf
GN		 3845static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3846{
3847 /* TODO: String I/O for in kernel device */
3848 int r;
3849
3850 if (vcpu->arch.pio.in)
3851 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3852 vcpu->arch.pio.size, pd);
3853 else
3854 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3855 vcpu->arch.pio.port, vcpu->arch.pio.size,
3856 pd);
3857 return r;
3858}
3859
3860
3861static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3862 unsigned int count, struct kvm_vcpu *vcpu)
3863{
7972995b 3864 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3865 goto data_avail;
3866
c41a15dd 3867 trace_kvm_pio(0, port, size, 1);
cf8f70bf
GN		 3868
3869 vcpu->arch.pio.port = port;
3870 vcpu->arch.pio.in = 1;
7972995b 3871 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3872 vcpu->arch.pio.size = size;
3873
3874 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3875 data_avail:
3876 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3877 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3878 return 1;
3879 }
3880
3881 vcpu->run->exit_reason = KVM_EXIT_IO;
3882 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3883 vcpu->run->io.size = size;
3884 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3885 vcpu->run->io.count = count;
3886 vcpu->run->io.port = port;
3887
3888 return 0;
3889}
3890
3891static int emulator_pio_out_emulated(int size, unsigned short port,
3892 const void *val, unsigned int count,
3893 struct kvm_vcpu *vcpu)
3894{
c41a15dd 3895 trace_kvm_pio(1, port, size, 1);
cf8f70bf
GN		 3896
3897 vcpu->arch.pio.port = port;
3898 vcpu->arch.pio.in = 0;
7972995b 3899 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3900 vcpu->arch.pio.size = size;
3901
3902 memcpy(vcpu->arch.pio_data, val, size * count);
3903
3904 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3905 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3906 return 1;
3907 }
3908
3909 vcpu->run->exit_reason = KVM_EXIT_IO;
3910 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3911 vcpu->run->io.size = size;
3912 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3913 vcpu->run->io.count = count;
3914 vcpu->run->io.port = port;
3915
3916 return 0;
3917}
3918
bbd9b64e
CO		 3919static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3920{
3921 return kvm_x86_ops->get_segment_base(vcpu, seg);
3922}
3923
3924int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3925{
a7052897 3926 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3927 return X86EMUL_CONTINUE;
3928}
3929
f5f48ee1
SY		 3930int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3931{
3932 if (!need_emulate_wbinvd(vcpu))
3933 return X86EMUL_CONTINUE;
3934
3935 if (kvm_x86_ops->has_wbinvd_exit()) {
3936 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3937 wbinvd_ipi, NULL, 1);
3938 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3939 }
3940 wbinvd();
3941 return X86EMUL_CONTINUE;
3942}
3943EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3944
bbd9b64e
CO		 3945int emulate_clts(struct kvm_vcpu *vcpu)
3946{
4d4ec087 3947 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3948 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3949 return X86EMUL_CONTINUE;
3950}
3951
35aa5375 3952int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3953{
338dbc97 3954 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3955}
3956
35aa5375 3957int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3958{
338dbc97
GN		 3959
3960 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3961}
3962
52a46617 3963static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3964{
52a46617 3965 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3966}
3967
52a46617 3968static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3969{
52a46617
GN		 3970 unsigned long value;
3971
3972 switch (cr) {
3973 case 0:
3974 value = kvm_read_cr0(vcpu);
3975 break;
3976 case 2:
3977 value = vcpu->arch.cr2;
3978 break;
3979 case 3:
3980 value = vcpu->arch.cr3;
3981 break;
3982 case 4:
3983 value = kvm_read_cr4(vcpu);
3984 break;
3985 case 8:
3986 value = kvm_get_cr8(vcpu);
3987 break;
3988 default:
3989 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3990 return 0;
3991 }
3992
3993 return value;
3994}
3995
0f12244f 3996static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3997{
0f12244f
GN		 3998 int res = 0;
3999
52a46617
GN		 4000 switch (cr) {
4001 case 0:
49a9b07e 4002 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4003 break;
4004 case 2:
4005 vcpu->arch.cr2 = val;
4006 break;
4007 case 3:
2390218b 4008 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4009 break;
4010 case 4:
a83b29c6 4011 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4012 break;
4013 case 8:
0f12244f 4014 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 4015 break;
4016 default:
4017 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4018 res = -1;
52a46617 4019 }
0f12244f
GN		 4020
4021 return res;
52a46617
GN		 4022}
4023
9c537244
GN		 4024static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4025{
4026 return kvm_x86_ops->get_cpl(vcpu);
4027}
4028
2dafc6c2
GN		 4029static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4030{
4031 kvm_x86_ops->get_gdt(vcpu, dt);
4032}
4033
160ce1f1
MG		 4034static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4035{
4036 kvm_x86_ops->get_idt(vcpu, dt);
4037}
4038
5951c442
GN		 4039static unsigned long emulator_get_cached_segment_base(int seg,
4040 struct kvm_vcpu *vcpu)
4041{
4042 return get_segment_base(vcpu, seg);
4043}
4044
2dafc6c2
GN		 4045static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4046 struct kvm_vcpu *vcpu)
4047{
4048 struct kvm_segment var;
4049
4050 kvm_get_segment(vcpu, &var, seg);
4051
4052 if (var.unusable)
4053 return false;
4054
4055 if (var.g)
4056 var.limit >>= 12;
4057 set_desc_limit(desc, var.limit);
4058 set_desc_base(desc, (unsigned long)var.base);
4059 desc->type = var.type;
4060 desc->s = var.s;
4061 desc->dpl = var.dpl;
4062 desc->p = var.present;
4063 desc->avl = var.avl;
4064 desc->l = var.l;
4065 desc->d = var.db;
4066 desc->g = var.g;
4067
4068 return true;
4069}
4070
4071static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4072 struct kvm_vcpu *vcpu)
4073{
4074 struct kvm_segment var;
4075
4076 /* needed to preserve selector */
4077 kvm_get_segment(vcpu, &var, seg);
4078
4079 var.base = get_desc_base(desc);
4080 var.limit = get_desc_limit(desc);
4081 if (desc->g)
4082 var.limit = (var.limit << 12) | 0xfff;
4083 var.type = desc->type;
4084 var.present = desc->p;
4085 var.dpl = desc->dpl;
4086 var.db = desc->d;
4087 var.s = desc->s;
4088 var.l = desc->l;
4089 var.g = desc->g;
4090 var.avl = desc->avl;
4091 var.present = desc->p;
4092 var.unusable = !var.present;
4093 var.padding = 0;
4094
4095 kvm_set_segment(vcpu, &var, seg);
4096 return;
4097}
4098
4099static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4100{
4101 struct kvm_segment kvm_seg;
4102
4103 kvm_get_segment(vcpu, &kvm_seg, seg);
4104 return kvm_seg.selector;
4105}
4106
4107static void emulator_set_segment_selector(u16 sel, int seg,
4108 struct kvm_vcpu *vcpu)
4109{
4110 struct kvm_segment kvm_seg;
4111
4112 kvm_get_segment(vcpu, &kvm_seg, seg);
4113 kvm_seg.selector = sel;
4114 kvm_set_segment(vcpu, &kvm_seg, seg);
4115}
4116
14af3f3c 4117static struct x86_emulate_ops emulate_ops = {
1871c602 4118 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4119 .write_std = kvm_write_guest_virt_system,
1871c602 4120 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4121 .read_emulated = emulator_read_emulated,
4122 .write_emulated = emulator_write_emulated,
4123 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4124 .pio_in_emulated = emulator_pio_in_emulated,
4125 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4126 .get_cached_descriptor = emulator_get_cached_descriptor,
4127 .set_cached_descriptor = emulator_set_cached_descriptor,
4128 .get_segment_selector = emulator_get_segment_selector,
4129 .set_segment_selector = emulator_set_segment_selector,
5951c442 4130 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4131 .get_gdt = emulator_get_gdt,
160ce1f1 4132 .get_idt = emulator_get_idt,
52a46617
GN		 4133 .get_cr = emulator_get_cr,
4134 .set_cr = emulator_set_cr,
9c537244 4135 .cpl = emulator_get_cpl,
35aa5375
GN		 4136 .get_dr = emulator_get_dr,
4137 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4138 .set_msr = kvm_set_msr,
4139 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4140};
4141
5fdbf976
MT		 4142static void cache_all_regs(struct kvm_vcpu *vcpu)
4143{
4144 kvm_register_read(vcpu, VCPU_REGS_RAX);
4145 kvm_register_read(vcpu, VCPU_REGS_RSP);
4146 kvm_register_read(vcpu, VCPU_REGS_RIP);
4147 vcpu->arch.regs_dirty = ~0;
4148}
4149
95cb2295
GN		 4150static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4151{
4152 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4153 /*
4154 * an sti; sti; sequence only disable interrupts for the first
4155 * instruction. So, if the last instruction, be it emulated or
4156 * not, left the system with the INT_STI flag enabled, it
4157 * means that the last instruction is an sti. We should not
4158 * leave the flag on in this case. The same goes for mov ss
4159 */
4160 if (!(int_shadow & mask))
4161 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4162}
4163
54b8486f
GN		 4164static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4165{
4166 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4167 if (ctxt->exception == PF_VECTOR)
d4f8cf66 4168 kvm_propagate_fault(vcpu);
54b8486f
GN		 4169 else if (ctxt->error_code_valid)
4170 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4171 else
4172 kvm_queue_exception(vcpu, ctxt->exception);
4173}
4174
8ec4722d
MG		 4175static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4176{
4177 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4178 int cs_db, cs_l;
4179
4180 cache_all_regs(vcpu);
4181
4182 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4183
4184 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4185 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4186 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4187 vcpu->arch.emulate_ctxt.mode =
4188 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4189 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4190 ? X86EMUL_MODE_VM86 : cs_l
4191 ? X86EMUL_MODE_PROT64 : cs_db
4192 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4193 memset(c, 0, sizeof(struct decode_cache));
4194 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4195}
4196
63995653
MG		 4197int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4198{
4199 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4200 int ret;
4201
4202 init_emulate_ctxt(vcpu);
4203
4204 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4205 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4206 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4207 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4208
4209 if (ret != X86EMUL_CONTINUE)
4210 return EMULATE_FAIL;
4211
4212 vcpu->arch.emulate_ctxt.eip = c->eip;
4213 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4214 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4215 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4216
4217 if (irq == NMI_VECTOR)
4218 vcpu->arch.nmi_pending = false;
4219 else
4220 vcpu->arch.interrupt.pending = false;
4221
4222 return EMULATE_DONE;
4223}
4224EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4225
6d77dbfc
GN		 4226static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4227{
6d77dbfc
GN		 4228 ++vcpu->stat.insn_emulation_fail;
4229 trace_kvm_emulate_insn_failed(vcpu);
4230 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4231 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4232 vcpu->run->internal.ndata = 0;
4233 kvm_queue_exception(vcpu, UD_VECTOR);
4234 return EMULATE_FAIL;
4235}
4236
a6f177ef
GN		 4237static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4238{
4239 gpa_t gpa;
4240
68be0803
GN		 4241 if (tdp_enabled)
4242 return false;
4243
a6f177ef
GN		 4244 /*
4245 * if emulation was due to access to shadowed page table
4246 * and it failed try to unshadow page and re-entetr the
4247 * guest to let CPU execute the instruction.
4248 */
4249 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4250 return true;
4251
4252 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4253
4254 if (gpa == UNMAPPED_GVA)
4255 return true; /* let cpu generate fault */
4256
4257 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4258 return true;
4259
4260 return false;
4261}
4262
bbd9b64e 4263int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4264 unsigned long cr2,
4265 u16 error_code,
571008da 4266 int emulation_type)
bbd9b64e 4267{
95cb2295 4268 int r;
4d2179e1 4269 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4270
26eef70c 4271 kvm_clear_exception_queue(vcpu);
ad312c7c 4272 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4273 /*
56e82318 4274 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4275 * instead of direct ->regs accesses, can save hundred cycles
4276 * on Intel for instructions that don't read/change RSP, for
4277 * for example.
4278 */
4279 cache_all_regs(vcpu);
bbd9b64e 4280
571008da 4281 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4282 init_emulate_ctxt(vcpu);
95cb2295 4283 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4284 vcpu->arch.emulate_ctxt.exception = -1;
4fc40f07 4285 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4286
9aabc88f 4287 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
d47f00a6
JR		 4288 if (r == X86EMUL_PROPAGATE_FAULT)
4289 goto done;
4290
e46479f8 4291 trace_kvm_emulate_insn_start(vcpu);
571008da 4292
0cb5762e
AP		 4293 /* Only allow emulation of specific instructions on #UD
4294 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4295 if (emulation_type & EMULTYPE_TRAP_UD) {
4296 if (!c->twobyte)
4297 return EMULATE_FAIL;
4298 switch (c->b) {
4299 case 0x01: /* VMMCALL */
4300 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4301 return EMULATE_FAIL;
4302 break;
4303 case 0x34: /* sysenter */
4304 case 0x35: /* sysexit */
4305 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4306 return EMULATE_FAIL;
4307 break;
4308 case 0x05: /* syscall */
4309 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4310 return EMULATE_FAIL;
4311 break;
4312 default:
4313 return EMULATE_FAIL;
4314 }
4315
4316 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4317 return EMULATE_FAIL;
4318 }
571008da 4319
f2b5756b 4320 ++vcpu->stat.insn_emulation;
bbd9b64e 4321 if (r) {
a6f177ef 4322 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4323 return EMULATE_DONE;
6d77dbfc
GN		 4324 if (emulation_type & EMULTYPE_SKIP)
4325 return EMULATE_FAIL;
4326 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4327 }
4328 }
4329
ba8afb6b
GN		 4330 if (emulation_type & EMULTYPE_SKIP) {
4331 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4332 return EMULATE_DONE;
4333 }
4334
4d2179e1
GN		 4335 /* this is needed for vmware backdor interface to work since it
4336 changes registers values during IO operation */
4337 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4338
5cd21917 4339restart:
9aabc88f 4340 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4341
d2ddd1c4 4342 if (r == EMULATION_FAILED) {
a6f177ef 4343 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4344 return EMULATE_DONE;
4345
6d77dbfc 4346 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4347 }
4348
d47f00a6 4349done:
d2ddd1c4 4350 if (vcpu->arch.emulate_ctxt.exception >= 0) {
54b8486f 4351 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4352 r = EMULATE_DONE;
4353 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4354 if (!vcpu->arch.pio.in)
4355 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4356 r = EMULATE_DO_MMIO;
4357 } else if (vcpu->mmio_needed) {
3457e419
GN		 4358 if (vcpu->mmio_is_write)
4359 vcpu->mmio_needed = 0;
e85d28f8 4360 r = EMULATE_DO_MMIO;
d2ddd1c4 4361 } else if (r == EMULATION_RESTART)
5cd21917 4362 goto restart;
d2ddd1c4
GN		 4363 else
4364 r = EMULATE_DONE;
f850e2e6 4365
e85d28f8
GN		 4366 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4367 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4368 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4369 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4370 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4371
4372 return r;
de7d789a 4373}
bbd9b64e 4374EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4375
cf8f70bf 4376int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4377{
cf8f70bf
GN		 4378 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4379 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4380 /* do not return to emulator after return from userspace */
7972995b 4381 vcpu->arch.pio.count = 0;
de7d789a
CO		 4382 return ret;
4383}
cf8f70bf 4384EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4385
8cfdc000
ZA		 4386static void tsc_bad(void *info)
4387{
4388 __get_cpu_var(cpu_tsc_khz) = 0;
4389}
4390
4391static void tsc_khz_changed(void *data)
c8076604 4392{
8cfdc000
ZA		 4393 struct cpufreq_freqs *freq = data;
4394 unsigned long khz = 0;
4395
4396 if (data)
4397 khz = freq->new;
4398 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4399 khz = cpufreq_quick_get(raw_smp_processor_id());
4400 if (!khz)
4401 khz = tsc_khz;
4402 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4403}
4404
c8076604
GH		 4405static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4406 void *data)
4407{
4408 struct cpufreq_freqs *freq = data;
4409 struct kvm *kvm;
4410 struct kvm_vcpu *vcpu;
4411 int i, send_ipi = 0;
4412
8cfdc000
ZA		 4413 /*
4414 * We allow guests to temporarily run on slowing clocks,
4415 * provided we notify them after, or to run on accelerating
4416 * clocks, provided we notify them before. Thus time never
4417 * goes backwards.
4418 *
4419 * However, we have a problem. We can't atomically update
4420 * the frequency of a given CPU from this function; it is
4421 * merely a notifier, which can be called from any CPU.
4422 * Changing the TSC frequency at arbitrary points in time
4423 * requires a recomputation of local variables related to
4424 * the TSC for each VCPU. We must flag these local variables
4425 * to be updated and be sure the update takes place with the
4426 * new frequency before any guests proceed.
4427 *
4428 * Unfortunately, the combination of hotplug CPU and frequency
4429 * change creates an intractable locking scenario; the order
4430 * of when these callouts happen is undefined with respect to
4431 * CPU hotplug, and they can race with each other. As such,
4432 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4433 * undefined; you can actually have a CPU frequency change take
4434 * place in between the computation of X and the setting of the
4435 * variable. To protect against this problem, all updates of
4436 * the per_cpu tsc_khz variable are done in an interrupt
4437 * protected IPI, and all callers wishing to update the value
4438 * must wait for a synchronous IPI to complete (which is trivial
4439 * if the caller is on the CPU already). This establishes the
4440 * necessary total order on variable updates.
4441 *
4442 * Note that because a guest time update may take place
4443 * anytime after the setting of the VCPU's request bit, the
4444 * correct TSC value must be set before the request. However,
4445 * to ensure the update actually makes it to any guest which
4446 * starts running in hardware virtualization between the set
4447 * and the acquisition of the spinlock, we must also ping the
4448 * CPU after setting the request bit.
4449 *
4450 */
4451
c8076604
GH		 4452 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4453 return 0;
4454 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4455 return 0;
8cfdc000
ZA		 4456
4457 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4458
4459 spin_lock(&kvm_lock);
4460 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4461 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4462 if (vcpu->cpu != freq->cpu)
4463 continue;
4464 if (!kvm_request_guest_time_update(vcpu))
4465 continue;
4466 if (vcpu->cpu != smp_processor_id())
8cfdc000 4467 send_ipi = 1;
c8076604
GH		 4468 }
4469 }
4470 spin_unlock(&kvm_lock);
4471
4472 if (freq->old < freq->new && send_ipi) {
4473 /*
4474 * We upscale the frequency. Must make the guest
4475 * doesn't see old kvmclock values while running with
4476 * the new frequency, otherwise we risk the guest sees
4477 * time go backwards.
4478 *
4479 * In case we update the frequency for another cpu
4480 * (which might be in guest context) send an interrupt
4481 * to kick the cpu out of guest context. Next time
4482 * guest context is entered kvmclock will be updated,
4483 * so the guest will not see stale values.
4484 */
8cfdc000 4485 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4486 }
4487 return 0;
4488}
4489
4490static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4491 .notifier_call = kvmclock_cpufreq_notifier
4492};
4493
4494static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4495 unsigned long action, void *hcpu)
4496{
4497 unsigned int cpu = (unsigned long)hcpu;
4498
4499 switch (action) {
4500 case CPU_ONLINE:
4501 case CPU_DOWN_FAILED:
4502 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4503 break;
4504 case CPU_DOWN_PREPARE:
4505 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4506 break;
4507 }
4508 return NOTIFY_OK;
4509}
4510
4511static struct notifier_block kvmclock_cpu_notifier_block = {
4512 .notifier_call = kvmclock_cpu_notifier,
4513 .priority = -INT_MAX
c8076604
GH		 4514};
4515
b820cc0c
ZA		 4516static void kvm_timer_init(void)
4517{
4518 int cpu;
4519
8cfdc000 4520 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4521 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4522 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4523 CPUFREQ_TRANSITION_NOTIFIER);
4524 }
8cfdc000
ZA		 4525 for_each_online_cpu(cpu)
4526 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4527}
4528
ff9d07a0
ZY		 4529static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4530
4531static int kvm_is_in_guest(void)
4532{
4533 return percpu_read(current_vcpu) != NULL;
4534}
4535
4536static int kvm_is_user_mode(void)
4537{
4538 int user_mode = 3;
dcf46b94 4539
ff9d07a0
ZY		 4540 if (percpu_read(current_vcpu))
4541 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4542
ff9d07a0
ZY		 4543 return user_mode != 0;
4544}
4545
4546static unsigned long kvm_get_guest_ip(void)
4547{
4548 unsigned long ip = 0;
dcf46b94 4549
ff9d07a0
ZY		 4550 if (percpu_read(current_vcpu))
4551 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4552
ff9d07a0
ZY		 4553 return ip;
4554}
4555
4556static struct perf_guest_info_callbacks kvm_guest_cbs = {
4557 .is_in_guest = kvm_is_in_guest,
4558 .is_user_mode = kvm_is_user_mode,
4559 .get_guest_ip = kvm_get_guest_ip,
4560};
4561
4562void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4563{
4564 percpu_write(current_vcpu, vcpu);
4565}
4566EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4567
4568void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4569{
4570 percpu_write(current_vcpu, NULL);
4571}
4572EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4573
f8c16bba 4574int kvm_arch_init(void *opaque)
043405e1 4575{
b820cc0c 4576 int r;
f8c16bba
ZX		 4577 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4578
f8c16bba
ZX		 4579 if (kvm_x86_ops) {
4580 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4581 r = -EEXIST;
4582 goto out;
f8c16bba
ZX		 4583 }
4584
4585 if (!ops->cpu_has_kvm_support()) {
4586 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4587 r = -EOPNOTSUPP;
4588 goto out;
f8c16bba
ZX		 4589 }
4590 if (ops->disabled_by_bios()) {
4591 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4592 r = -EOPNOTSUPP;
4593 goto out;
f8c16bba
ZX		 4594 }
4595
97db56ce
AK		 4596 r = kvm_mmu_module_init();
4597 if (r)
4598 goto out;
4599
4600 kvm_init_msr_list();
4601
f8c16bba 4602 kvm_x86_ops = ops;
56c6d28a 4603 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4604 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4605 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4606 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4607
b820cc0c 4608 kvm_timer_init();
c8076604 4609
ff9d07a0
ZY		 4610 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4611
2acf923e
DC		 4612 if (cpu_has_xsave)
4613 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4614
f8c16bba 4615 return 0;
56c6d28a
ZX		 4616
4617out:
56c6d28a 4618 return r;
043405e1 4619}
8776e519 4620
f8c16bba
ZX		 4621void kvm_arch_exit(void)
4622{
ff9d07a0
ZY		 4623 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4624
888d256e
JK		 4625 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4626 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4627 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4628 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4629 kvm_x86_ops = NULL;
56c6d28a
ZX		 4630 kvm_mmu_module_exit();
4631}
f8c16bba 4632
8776e519
HB		 4633int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4634{
4635 ++vcpu->stat.halt_exits;
4636 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4637 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4638 return 1;
4639 } else {
4640 vcpu->run->exit_reason = KVM_EXIT_HLT;
4641 return 0;
4642 }
4643}
4644EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4645
2f333bcb
MT		 4646static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4647 unsigned long a1)
4648{
4649 if (is_long_mode(vcpu))
4650 return a0;
4651 else
4652 return a0 | ((gpa_t)a1 << 32);
4653}
4654
55cd8e5a
GN		 4655int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4656{
4657 u64 param, ingpa, outgpa, ret;
4658 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4659 bool fast, longmode;
4660 int cs_db, cs_l;
4661
4662 /*
4663 * hypercall generates UD from non zero cpl and real mode
4664 * per HYPER-V spec
4665 */
3eeb3288 4666 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4667 kvm_queue_exception(vcpu, UD_VECTOR);
4668 return 0;
4669 }
4670
4671 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4672 longmode = is_long_mode(vcpu) && cs_l == 1;
4673
4674 if (!longmode) {
ccd46936
GN		 4675 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4676 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4677 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4678 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4679 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4680 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4681 }
4682#ifdef CONFIG_X86_64
4683 else {
4684 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4685 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4686 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4687 }
4688#endif
4689
4690 code = param & 0xffff;
4691 fast = (param >> 16) & 0x1;
4692 rep_cnt = (param >> 32) & 0xfff;
4693 rep_idx = (param >> 48) & 0xfff;
4694
4695 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4696
c25bc163
GN		 4697 switch (code) {
4698 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4699 kvm_vcpu_on_spin(vcpu);
4700 break;
4701 default:
4702 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4703 break;
4704 }
55cd8e5a
GN		 4705
4706 ret = res | (((u64)rep_done & 0xfff) << 32);
4707 if (longmode) {
4708 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4709 } else {
4710 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4711 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4712 }
4713
4714 return 1;
4715}
4716
8776e519
HB		 4717int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4718{
4719 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4720 int r = 1;
8776e519 4721
55cd8e5a
GN		 4722 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4723 return kvm_hv_hypercall(vcpu);
4724
5fdbf976
MT		 4725 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4726 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4727 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4728 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4729 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4730
229456fc 4731 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4732
8776e519
HB		 4733 if (!is_long_mode(vcpu)) {
4734 nr &= 0xFFFFFFFF;
4735 a0 &= 0xFFFFFFFF;
4736 a1 &= 0xFFFFFFFF;
4737 a2 &= 0xFFFFFFFF;
4738 a3 &= 0xFFFFFFFF;
4739 }
4740
07708c4a
JK		 4741 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4742 ret = -KVM_EPERM;
4743 goto out;
4744 }
4745
8776e519 4746 switch (nr) {
b93463aa
AK		 4747 case KVM_HC_VAPIC_POLL_IRQ:
4748 ret = 0;
4749 break;
2f333bcb
MT		 4750 case KVM_HC_MMU_OP:
4751 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4752 break;
8776e519
HB		 4753 default:
4754 ret = -KVM_ENOSYS;
4755 break;
4756 }
07708c4a 4757out:
5fdbf976 4758 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4759 ++vcpu->stat.hypercalls;
2f333bcb 4760 return r;
8776e519
HB		 4761}
4762EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4763
4764int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4765{
4766 char instruction[3];
5fdbf976 4767 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4768
8776e519
HB		 4769 /*
4770 * Blow out the MMU to ensure that no other VCPU has an active mapping
4771 * to ensure that the updated hypercall appears atomically across all
4772 * VCPUs.
4773 */
4774 kvm_mmu_zap_all(vcpu->kvm);
4775
8776e519 4776 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4777
8fe681e9 4778 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4779}
4780
8776e519
HB		 4781void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4782{
89a27f4d 4783 struct desc_ptr dt = { limit, base };
8776e519
HB		 4784
4785 kvm_x86_ops->set_gdt(vcpu, &dt);
4786}
4787
4788void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4789{
89a27f4d 4790 struct desc_ptr dt = { limit, base };
8776e519
HB		 4791
4792 kvm_x86_ops->set_idt(vcpu, &dt);
4793}
4794
07716717
DK		 4795static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4796{
ad312c7c
ZX		 4797 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4798 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4799
4800 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4801 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4802 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4803 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4804 if (ej->function == e->function) {
4805 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4806 return j;
4807 }
4808 }
4809 return 0; /* silence gcc, even though control never reaches here */
4810}
4811
4812/* find an entry with matching function, matching index (if needed), and that
4813 * should be read next (if it's stateful) */
4814static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4815 u32 function, u32 index)
4816{
4817 if (e->function != function)
4818 return 0;
4819 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4820 return 0;
4821 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4822 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4823 return 0;
4824 return 1;
4825}
4826
d8017474
AG		 4827struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4828 u32 function, u32 index)
8776e519
HB		 4829{
4830 int i;
d8017474 4831 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4832
ad312c7c 4833 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4834 struct kvm_cpuid_entry2 *e;
4835
ad312c7c 4836 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4837 if (is_matching_cpuid_entry(e, function, index)) {
4838 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4839 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4840 best = e;
4841 break;
4842 }
4843 /*
4844 * Both basic or both extended?
4845 */
4846 if (((e->function ^ function) & 0x80000000) == 0)
4847 if (!best || e->function > best->function)
4848 best = e;
4849 }
d8017474
AG		 4850 return best;
4851}
0e851880 4852EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4853
82725b20
DE		 4854int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4855{
4856 struct kvm_cpuid_entry2 *best;
4857
f7a71197
AK		 4858 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4859 if (!best || best->eax < 0x80000008)
4860 goto not_found;
82725b20
DE		 4861 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4862 if (best)
4863 return best->eax & 0xff;
f7a71197 4864not_found:
82725b20
DE		 4865 return 36;
4866}
4867
d8017474
AG		 4868void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4869{
4870 u32 function, index;
4871 struct kvm_cpuid_entry2 *best;
4872
4873 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4874 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4875 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4876 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4877 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4878 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4879 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4880 if (best) {
5fdbf976
MT		 4881 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4882 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4883 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4884 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4885 }
8776e519 4886 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4887 trace_kvm_cpuid(function,
4888 kvm_register_read(vcpu, VCPU_REGS_RAX),
4889 kvm_register_read(vcpu, VCPU_REGS_RBX),
4890 kvm_register_read(vcpu, VCPU_REGS_RCX),
4891 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4892}
4893EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4894
b6c7a5dc
HB		 4895/*
4896 * Check if userspace requested an interrupt window, and that the
4897 * interrupt window is open.
4898 *
4899 * No need to exit to userspace if we already have an interrupt queued.
4900 */
851ba692 4901static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4902{
8061823a 4903 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4904 vcpu->run->request_interrupt_window &&
5df56646 4905 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4906}
4907
851ba692 4908static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4909{
851ba692
AK		 4910 struct kvm_run *kvm_run = vcpu->run;
4911
91586a3b 4912 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4913 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4914 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4915 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4916 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4917 else
b6c7a5dc 4918 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4919 kvm_arch_interrupt_allowed(vcpu) &&
4920 !kvm_cpu_has_interrupt(vcpu) &&
4921 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4922}
4923
b93463aa
AK		 4924static void vapic_enter(struct kvm_vcpu *vcpu)
4925{
4926 struct kvm_lapic *apic = vcpu->arch.apic;
4927 struct page *page;
4928
4929 if (!apic || !apic->vapic_addr)
4930 return;
4931
4932 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4933
4934 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4935}
4936
4937static void vapic_exit(struct kvm_vcpu *vcpu)
4938{
4939 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4940 int idx;
b93463aa
AK		 4941
4942 if (!apic || !apic->vapic_addr)
4943 return;
4944
f656ce01 4945 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4946 kvm_release_page_dirty(apic->vapic_page);
4947 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4948 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4949}
4950
95ba8273
GN		 4951static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4952{
4953 int max_irr, tpr;
4954
4955 if (!kvm_x86_ops->update_cr8_intercept)
4956 return;
4957
88c808fd
AK		 4958 if (!vcpu->arch.apic)
4959 return;
4960
8db3baa2
GN		 4961 if (!vcpu->arch.apic->vapic_addr)
4962 max_irr = kvm_lapic_find_highest_irr(vcpu);
4963 else
4964 max_irr = -1;
95ba8273
GN		 4965
4966 if (max_irr != -1)
4967 max_irr >>= 4;
4968
4969 tpr = kvm_lapic_get_cr8(vcpu);
4970
4971 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4972}
4973
851ba692 4974static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4975{
4976 /* try to reinject previous events if any */
b59bb7bd 4977 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4978 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4979 vcpu->arch.exception.has_error_code,
4980 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4981 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4982 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4983 vcpu->arch.exception.error_code,
4984 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4985 return;
4986 }
4987
95ba8273
GN		 4988 if (vcpu->arch.nmi_injected) {
4989 kvm_x86_ops->set_nmi(vcpu);
4990 return;
4991 }
4992
4993 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4994 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4995 return;
4996 }
4997
4998 /* try to inject new event if pending */
4999 if (vcpu->arch.nmi_pending) {
5000 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5001 vcpu->arch.nmi_pending = false;
5002 vcpu->arch.nmi_injected = true;
5003 kvm_x86_ops->set_nmi(vcpu);
5004 }
5005 } else if (kvm_cpu_has_interrupt(vcpu)) {
5006 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5007 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5008 false);
5009 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5010 }
5011 }
5012}
5013
2acf923e
DC		 5014static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5015{
5016 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5017 !vcpu->guest_xcr0_loaded) {
5018 /* kvm_set_xcr() also depends on this */
5019 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5020 vcpu->guest_xcr0_loaded = 1;
5021 }
5022}
5023
5024static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5025{
5026 if (vcpu->guest_xcr0_loaded) {
5027 if (vcpu->arch.xcr0 != host_xcr0)
5028 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5029 vcpu->guest_xcr0_loaded = 0;
5030 }
5031}
5032
851ba692 5033static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5034{
5035 int r;
6a8b1d13 5036 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5037 vcpu->run->request_interrupt_window;
b6c7a5dc 5038
3e007509 5039 if (vcpu->requests) {
a8eeb04a 5040 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5041 kvm_mmu_unload(vcpu);
a8eeb04a 5042 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5043 __kvm_migrate_timers(vcpu);
8cfdc000
ZA		 5044 if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu)) {
5045 r = kvm_write_guest_time(vcpu);
5046 if (unlikely(r))
5047 goto out;
5048 }
a8eeb04a 5049 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5050 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5051 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5052 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5053 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5054 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5055 r = 0;
5056 goto out;
5057 }
a8eeb04a 5058 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5059 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5060 r = 0;
5061 goto out;
5062 }
a8eeb04a 5063 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5064 vcpu->fpu_active = 0;
5065 kvm_x86_ops->fpu_deactivate(vcpu);
5066 }
2f52d58c 5067 }
b93463aa 5068
3e007509
AK		 5069 r = kvm_mmu_reload(vcpu);
5070 if (unlikely(r))
5071 goto out;
5072
b463a6f7
AK		 5073 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5074 inject_pending_event(vcpu);
5075
5076 /* enable NMI/IRQ window open exits if needed */
5077 if (vcpu->arch.nmi_pending)
5078 kvm_x86_ops->enable_nmi_window(vcpu);
5079 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5080 kvm_x86_ops->enable_irq_window(vcpu);
5081
5082 if (kvm_lapic_enabled(vcpu)) {
5083 update_cr8_intercept(vcpu);
5084 kvm_lapic_sync_to_vapic(vcpu);
5085 }
5086 }
5087
b6c7a5dc
HB		 5088 preempt_disable();
5089
5090 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5091 if (vcpu->fpu_active)
5092 kvm_load_guest_fpu(vcpu);
2acf923e 5093 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5094
d94e1dc9
AK		 5095 atomic_set(&vcpu->guest_mode, 1);
5096 smp_wmb();
b6c7a5dc 5097
d94e1dc9 5098 local_irq_disable();
32f88400 5099
d94e1dc9
AK		 5100 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5101 || need_resched() || signal_pending(current)) {
5102 atomic_set(&vcpu->guest_mode, 0);
5103 smp_wmb();
6c142801
AK		 5104 local_irq_enable();
5105 preempt_enable();
b463a6f7 5106 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5107 r = 1;
5108 goto out;
5109 }
5110
f656ce01 5111 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5112
b6c7a5dc
HB		 5113 kvm_guest_enter();
5114
42dbaa5a 5115 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5116 set_debugreg(0, 7);
5117 set_debugreg(vcpu->arch.eff_db[0], 0);
5118 set_debugreg(vcpu->arch.eff_db[1], 1);
5119 set_debugreg(vcpu->arch.eff_db[2], 2);
5120 set_debugreg(vcpu->arch.eff_db[3], 3);
5121 }
b6c7a5dc 5122
229456fc 5123 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5124 kvm_x86_ops->run(vcpu);
b6c7a5dc 5125
24f1e32c
FW		 5126 /*
5127 * If the guest has used debug registers, at least dr7
5128 * will be disabled while returning to the host.
5129 * If we don't have active breakpoints in the host, we don't
5130 * care about the messed up debug address registers. But if
5131 * we have some of them active, restore the old state.
5132 */
59d8eb53 5133 if (hw_breakpoint_active())
24f1e32c 5134 hw_breakpoint_restore();
42dbaa5a 5135
1d5f066e
ZA		 5136 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5137
d94e1dc9
AK		 5138 atomic_set(&vcpu->guest_mode, 0);
5139 smp_wmb();
b6c7a5dc
HB		 5140 local_irq_enable();
5141
5142 ++vcpu->stat.exits;
5143
5144 /*
5145 * We must have an instruction between local_irq_enable() and
5146 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5147 * the interrupt shadow. The stat.exits increment will do nicely.
5148 * But we need to prevent reordering, hence this barrier():
5149 */
5150 barrier();
5151
5152 kvm_guest_exit();
5153
5154 preempt_enable();
5155
f656ce01 5156 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5157
b6c7a5dc
HB		 5158 /*
5159 * Profile KVM exit RIPs:
5160 */
5161 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5162 unsigned long rip = kvm_rip_read(vcpu);
5163 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5164 }
5165
298101da 5166
b93463aa
AK		 5167 kvm_lapic_sync_from_vapic(vcpu);
5168
851ba692 5169 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5170out:
5171 return r;
5172}
b6c7a5dc 5173
09cec754 5174
851ba692 5175static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5176{
5177 int r;
f656ce01 5178 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5179
5180 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5181 pr_debug("vcpu %d received sipi with vector # %x\n",
5182 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5183 kvm_lapic_reset(vcpu);
5f179287 5184 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5185 if (r)
5186 return r;
5187 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5188 }
5189
f656ce01 5190 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5191 vapic_enter(vcpu);
5192
5193 r = 1;
5194 while (r > 0) {
af2152f5 5195 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 5196 r = vcpu_enter_guest(vcpu);
d7690175 5197 else {
f656ce01 5198 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5199 kvm_vcpu_block(vcpu);
f656ce01 5200 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5201 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5202 {
5203 switch(vcpu->arch.mp_state) {
5204 case KVM_MP_STATE_HALTED:
d7690175 5205 vcpu->arch.mp_state =
09cec754
GN		 5206 KVM_MP_STATE_RUNNABLE;
5207 case KVM_MP_STATE_RUNNABLE:
5208 break;
5209 case KVM_MP_STATE_SIPI_RECEIVED:
5210 default:
5211 r = -EINTR;
5212 break;
5213 }
5214 }
d7690175
MT		 5215 }
5216
09cec754
GN		 5217 if (r <= 0)
5218 break;
5219
5220 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5221 if (kvm_cpu_has_pending_timer(vcpu))
5222 kvm_inject_pending_timer_irqs(vcpu);
5223
851ba692 5224 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5225 r = -EINTR;
851ba692 5226 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5227 ++vcpu->stat.request_irq_exits;
5228 }
5229 if (signal_pending(current)) {
5230 r = -EINTR;
851ba692 5231 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5232 ++vcpu->stat.signal_exits;
5233 }
5234 if (need_resched()) {
f656ce01 5235 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5236 kvm_resched(vcpu);
f656ce01 5237 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5238 }
b6c7a5dc
HB		 5239 }
5240
f656ce01 5241 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5242
b93463aa
AK		 5243 vapic_exit(vcpu);
5244
b6c7a5dc
HB		 5245 return r;
5246}
5247
5248int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5249{
5250 int r;
5251 sigset_t sigsaved;
5252
ac9f6dc0
AK		 5253 if (vcpu->sigset_active)
5254 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5255
a4535290 5256 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5257 kvm_vcpu_block(vcpu);
d7690175 5258 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5259 r = -EAGAIN;
5260 goto out;
b6c7a5dc
HB		 5261 }
5262
b6c7a5dc
HB		 5263 /* re-sync apic's tpr */
5264 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5265 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5266
d2ddd1c4 5267 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5268 if (vcpu->mmio_needed) {
5269 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5270 vcpu->mmio_read_completed = 1;
5271 vcpu->mmio_needed = 0;
b6c7a5dc 5272 }
f656ce01 5273 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5274 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5275 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5276 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5277 r = 0;
5278 goto out;
5279 }
5280 }
5fdbf976
MT		 5281 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5282 kvm_register_write(vcpu, VCPU_REGS_RAX,
5283 kvm_run->hypercall.ret);
b6c7a5dc 5284
851ba692 5285 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5286
5287out:
f1d86e46 5288 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5289 if (vcpu->sigset_active)
5290 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5291
b6c7a5dc
HB		 5292 return r;
5293}
5294
5295int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5296{
5fdbf976
MT		 5297 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5298 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5299 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5300 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5301 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5302 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5303 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5304 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5305#ifdef CONFIG_X86_64
5fdbf976
MT		 5306 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5307 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5308 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5309 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5310 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5311 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5312 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5313 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5314#endif
5315
5fdbf976 5316 regs->rip = kvm_rip_read(vcpu);
91586a3b 5317 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5318
b6c7a5dc
HB		 5319 return 0;
5320}
5321
5322int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5323{
5fdbf976
MT		 5324 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5325 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5326 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5327 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5328 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5329 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5330 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5331 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5332#ifdef CONFIG_X86_64
5fdbf976
MT		 5333 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5334 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5335 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5336 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5337 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5338 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5339 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5340 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5341#endif
5342
5fdbf976 5343 kvm_rip_write(vcpu, regs->rip);
91586a3b 5344 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5345
b4f14abd
JK		 5346 vcpu->arch.exception.pending = false;
5347
3842d135
AK		 5348 kvm_make_request(KVM_REQ_EVENT, vcpu);
5349
b6c7a5dc
HB		 5350 return 0;
5351}
5352
b6c7a5dc
HB		 5353void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5354{
5355 struct kvm_segment cs;
5356
3e6e0aab 5357 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5358 *db = cs.db;
5359 *l = cs.l;
5360}
5361EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5362
5363int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5364 struct kvm_sregs *sregs)
5365{
89a27f4d 5366 struct desc_ptr dt;
b6c7a5dc 5367
3e6e0aab
GT		 5368 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5369 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5370 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5371 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5372 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5373 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5374
3e6e0aab
GT		 5375 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5376 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5377
5378 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5379 sregs->idt.limit = dt.size;
5380 sregs->idt.base = dt.address;
b6c7a5dc 5381 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5382 sregs->gdt.limit = dt.size;
5383 sregs->gdt.base = dt.address;
b6c7a5dc 5384
4d4ec087 5385 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5386 sregs->cr2 = vcpu->arch.cr2;
5387 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5388 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5389 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5390 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5391 sregs->apic_base = kvm_get_apic_base(vcpu);
5392
923c61bb 5393 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5394
36752c9b 5395 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5396 set_bit(vcpu->arch.interrupt.nr,
5397 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5398
b6c7a5dc
HB		 5399 return 0;
5400}
5401
62d9f0db
MT		 5402int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5403 struct kvm_mp_state *mp_state)
5404{
62d9f0db 5405 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5406 return 0;
5407}
5408
5409int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5410 struct kvm_mp_state *mp_state)
5411{
62d9f0db 5412 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5413 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5414 return 0;
5415}
5416
e269fb21
JK		 5417int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5418 bool has_error_code, u32 error_code)
b6c7a5dc 5419{
4d2179e1 5420 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5421 int ret;
e01c2426 5422
8ec4722d 5423 init_emulate_ctxt(vcpu);
c697518a 5424
9aabc88f 5425 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5426 tss_selector, reason, has_error_code,
5427 error_code);
c697518a 5428
c697518a 5429 if (ret)
19d04437 5430 return EMULATE_FAIL;
37817f29 5431
4d2179e1 5432 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5433 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437 5434 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5435 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5436 return EMULATE_DONE;
37817f29
IE		 5437}
5438EXPORT_SYMBOL_GPL(kvm_task_switch);
5439
b6c7a5dc
HB		 5440int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5441 struct kvm_sregs *sregs)
5442{
5443 int mmu_reset_needed = 0;
923c61bb 5444 int pending_vec, max_bits;
89a27f4d 5445 struct desc_ptr dt;
b6c7a5dc 5446
89a27f4d
GN		 5447 dt.size = sregs->idt.limit;
5448 dt.address = sregs->idt.base;
b6c7a5dc 5449 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5450 dt.size = sregs->gdt.limit;
5451 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5452 kvm_x86_ops->set_gdt(vcpu, &dt);
5453
ad312c7c
ZX		 5454 vcpu->arch.cr2 = sregs->cr2;
5455 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5456 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5457
2d3ad1f4 5458 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5459
f6801dff 5460 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5461 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5462 kvm_set_apic_base(vcpu, sregs->apic_base);
5463
4d4ec087 5464 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5465 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5466 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5467
fc78f519 5468 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5469 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5470 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ff03a073 5471 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
7c93be44
MT		 5472 mmu_reset_needed = 1;
5473 }
b6c7a5dc
HB		 5474
5475 if (mmu_reset_needed)
5476 kvm_mmu_reset_context(vcpu);
5477
923c61bb
GN		 5478 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5479 pending_vec = find_first_bit(
5480 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5481 if (pending_vec < max_bits) {
66fd3f7f 5482 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5483 pr_debug("Set back pending irq %d\n", pending_vec);
5484 if (irqchip_in_kernel(vcpu->kvm))
5485 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5486 }
5487
3e6e0aab
GT		 5488 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5489 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5490 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5491 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5492 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5493 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5494
3e6e0aab
GT		 5495 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5496 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5497
5f0269f5
ME		 5498 update_cr8_intercept(vcpu);
5499
9c3e4aab 5500 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5501 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5502 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5503 !is_protmode(vcpu))
9c3e4aab
MT		 5504 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5505
3842d135
AK		 5506 kvm_make_request(KVM_REQ_EVENT, vcpu);
5507
b6c7a5dc
HB		 5508 return 0;
5509}
5510
d0bfb940
JK		 5511int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5512 struct kvm_guest_debug *dbg)
b6c7a5dc 5513{
355be0b9 5514 unsigned long rflags;
ae675ef0 5515 int i, r;
b6c7a5dc 5516
4f926bf2
JK		 5517 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5518 r = -EBUSY;
5519 if (vcpu->arch.exception.pending)
2122ff5e 5520 goto out;
4f926bf2
JK		 5521 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5522 kvm_queue_exception(vcpu, DB_VECTOR);
5523 else
5524 kvm_queue_exception(vcpu, BP_VECTOR);
5525 }
5526
91586a3b
JK		 5527 /*
5528 * Read rflags as long as potentially injected trace flags are still
5529 * filtered out.
5530 */
5531 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5532
5533 vcpu->guest_debug = dbg->control;
5534 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5535 vcpu->guest_debug = 0;
5536
5537 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5538 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5539 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5540 vcpu->arch.switch_db_regs =
5541 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5542 } else {
5543 for (i = 0; i < KVM_NR_DB_REGS; i++)
5544 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5545 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5546 }
5547
f92653ee
JK		 5548 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5549 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5550 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5551
91586a3b
JK		 5552 /*
5553 * Trigger an rflags update that will inject or remove the trace
5554 * flags.
5555 */
5556 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5557
355be0b9 5558 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5559
4f926bf2 5560 r = 0;
d0bfb940 5561
2122ff5e 5562out:
b6c7a5dc
HB		 5563
5564 return r;
5565}
5566
8b006791
ZX		 5567/*
5568 * Translate a guest virtual address to a guest physical address.
5569 */
5570int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5571 struct kvm_translation *tr)
5572{
5573 unsigned long vaddr = tr->linear_address;
5574 gpa_t gpa;
f656ce01 5575 int idx;
8b006791 5576
f656ce01 5577 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5578 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5579 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5580 tr->physical_address = gpa;
5581 tr->valid = gpa != UNMAPPED_GVA;
5582 tr->writeable = 1;
5583 tr->usermode = 0;
8b006791
ZX		 5584
5585 return 0;
5586}
5587
d0752060
HB		 5588int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5589{
98918833
SY		 5590 struct i387_fxsave_struct *fxsave =
5591 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5592
d0752060
HB		 5593 memcpy(fpu->fpr, fxsave->st_space, 128);
5594 fpu->fcw = fxsave->cwd;
5595 fpu->fsw = fxsave->swd;
5596 fpu->ftwx = fxsave->twd;
5597 fpu->last_opcode = fxsave->fop;
5598 fpu->last_ip = fxsave->rip;
5599 fpu->last_dp = fxsave->rdp;
5600 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5601
d0752060
HB		 5602 return 0;
5603}
5604
5605int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5606{
98918833
SY		 5607 struct i387_fxsave_struct *fxsave =
5608 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5609
d0752060
HB		 5610 memcpy(fxsave->st_space, fpu->fpr, 128);
5611 fxsave->cwd = fpu->fcw;
5612 fxsave->swd = fpu->fsw;
5613 fxsave->twd = fpu->ftwx;
5614 fxsave->fop = fpu->last_opcode;
5615 fxsave->rip = fpu->last_ip;
5616 fxsave->rdp = fpu->last_dp;
5617 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5618
d0752060
HB		 5619 return 0;
5620}
5621
10ab25cd 5622int fx_init(struct kvm_vcpu *vcpu)
d0752060 5623{
10ab25cd
JK		 5624 int err;
5625
5626 err = fpu_alloc(&vcpu->arch.guest_fpu);
5627 if (err)
5628 return err;
5629
98918833 5630 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5631
2acf923e
DC		 5632 /*
5633 * Ensure guest xcr0 is valid for loading
5634 */
5635 vcpu->arch.xcr0 = XSTATE_FP;
5636
ad312c7c 5637 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5638
5639 return 0;
d0752060
HB		 5640}
5641EXPORT_SYMBOL_GPL(fx_init);
5642
98918833
SY		 5643static void fx_free(struct kvm_vcpu *vcpu)
5644{
5645 fpu_free(&vcpu->arch.guest_fpu);
5646}
5647
d0752060
HB		 5648void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5649{
2608d7a1 5650 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5651 return;
5652
2acf923e
DC		 5653 /*
5654 * Restore all possible states in the guest,
5655 * and assume host would use all available bits.
5656 * Guest xcr0 would be loaded later.
5657 */
5658 kvm_put_guest_xcr0(vcpu);
d0752060 5659 vcpu->guest_fpu_loaded = 1;
7cf30855 5660 unlazy_fpu(current);
98918833 5661 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5662 trace_kvm_fpu(1);
d0752060 5663}
d0752060
HB		 5664
5665void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5666{
2acf923e
DC		 5667 kvm_put_guest_xcr0(vcpu);
5668
d0752060
HB		 5669 if (!vcpu->guest_fpu_loaded)
5670 return;
5671
5672 vcpu->guest_fpu_loaded = 0;
98918833 5673 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5674 ++vcpu->stat.fpu_reload;
a8eeb04a 5675 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5676 trace_kvm_fpu(0);
d0752060 5677}
e9b11c17
ZX		 5678
5679void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5680{
7f1ea208
JR		 5681 if (vcpu->arch.time_page) {
5682 kvm_release_page_dirty(vcpu->arch.time_page);
5683 vcpu->arch.time_page = NULL;
5684 }
5685
f5f48ee1 5686 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5687 fx_free(vcpu);
e9b11c17
ZX		 5688 kvm_x86_ops->vcpu_free(vcpu);
5689}
5690
5691struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5692 unsigned int id)
5693{
6755bae8
ZA		 5694 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5695 printk_once(KERN_WARNING
5696 "kvm: SMP vm created on host with unstable TSC; "
5697 "guest TSC will not be reliable\n");
26e5215f
AK		 5698 return kvm_x86_ops->vcpu_create(kvm, id);
5699}
e9b11c17 5700
26e5215f
AK		 5701int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5702{
5703 int r;
e9b11c17 5704
0bed3b56 5705 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5706 vcpu_load(vcpu);
5707 r = kvm_arch_vcpu_reset(vcpu);
5708 if (r == 0)
5709 r = kvm_mmu_setup(vcpu);
5710 vcpu_put(vcpu);
5711 if (r < 0)
5712 goto free_vcpu;
5713
26e5215f 5714 return 0;
e9b11c17
ZX		 5715free_vcpu:
5716 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5717 return r;
e9b11c17
ZX		 5718}
5719
d40ccc62 5720void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5721{
5722 vcpu_load(vcpu);
5723 kvm_mmu_unload(vcpu);
5724 vcpu_put(vcpu);
5725
98918833 5726 fx_free(vcpu);
e9b11c17
ZX		 5727 kvm_x86_ops->vcpu_free(vcpu);
5728}
5729
5730int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5731{
448fa4a9
JK		 5732 vcpu->arch.nmi_pending = false;
5733 vcpu->arch.nmi_injected = false;
5734
42dbaa5a
JK		 5735 vcpu->arch.switch_db_regs = 0;
5736 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5737 vcpu->arch.dr6 = DR6_FIXED_1;
5738 vcpu->arch.dr7 = DR7_FIXED_1;
5739
3842d135
AK		 5740 kvm_make_request(KVM_REQ_EVENT, vcpu);
5741
e9b11c17
ZX		 5742 return kvm_x86_ops->vcpu_reset(vcpu);
5743}
5744
10474ae8 5745int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5746{
ca84d1a2
ZA		 5747 struct kvm *kvm;
5748 struct kvm_vcpu *vcpu;
5749 int i;
5750
18863bdd 5751 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5752 list_for_each_entry(kvm, &vm_list, vm_list)
5753 kvm_for_each_vcpu(i, vcpu, kvm)
5754 if (vcpu->cpu == smp_processor_id())
5755 kvm_request_guest_time_update(vcpu);
10474ae8 5756 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5757}
5758
5759void kvm_arch_hardware_disable(void *garbage)
5760{
5761 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5762 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5763}
5764
5765int kvm_arch_hardware_setup(void)
5766{
5767 return kvm_x86_ops->hardware_setup();
5768}
5769
5770void kvm_arch_hardware_unsetup(void)
5771{
5772 kvm_x86_ops->hardware_unsetup();
5773}
5774
5775void kvm_arch_check_processor_compat(void *rtn)
5776{
5777 kvm_x86_ops->check_processor_compatibility(rtn);
5778}
5779
5780int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5781{
5782 struct page *page;
5783 struct kvm *kvm;
5784 int r;
5785
5786 BUG_ON(vcpu->kvm == NULL);
5787 kvm = vcpu->kvm;
5788
9aabc88f 5789 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5790 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5791 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5792 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5793 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5794 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5795 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5796 else
a4535290 5797 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5798
5799 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5800 if (!page) {
5801 r = -ENOMEM;
5802 goto fail;
5803 }
ad312c7c 5804 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5805
5806 r = kvm_mmu_create(vcpu);
5807 if (r < 0)
5808 goto fail_free_pio_data;
5809
5810 if (irqchip_in_kernel(kvm)) {
5811 r = kvm_create_lapic(vcpu);
5812 if (r < 0)
5813 goto fail_mmu_destroy;
5814 }
5815
890ca9ae
HY		 5816 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5817 GFP_KERNEL);
5818 if (!vcpu->arch.mce_banks) {
5819 r = -ENOMEM;
443c39bc 5820 goto fail_free_lapic;
890ca9ae
HY		 5821 }
5822 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5823
f5f48ee1
SY		 5824 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5825 goto fail_free_mce_banks;
5826
e9b11c17 5827 return 0;
f5f48ee1
SY		 5828fail_free_mce_banks:
5829 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5830fail_free_lapic:
5831 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5832fail_mmu_destroy:
5833 kvm_mmu_destroy(vcpu);
5834fail_free_pio_data:
ad312c7c 5835 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5836fail:
5837 return r;
5838}
5839
5840void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5841{
f656ce01
MT		 5842 int idx;
5843
36cb93fd 5844 kfree(vcpu->arch.mce_banks);
e9b11c17 5845 kvm_free_lapic(vcpu);
f656ce01 5846 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5847 kvm_mmu_destroy(vcpu);
f656ce01 5848 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5849 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5850}
d19a9cd2
ZX		 5851
5852struct kvm *kvm_arch_create_vm(void)
5853{
5854 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5855
5856 if (!kvm)
5857 return ERR_PTR(-ENOMEM);
5858
f05e70ac 5859 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5860 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5861
5550af4d
SY		 5862 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5863 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5864
99e3e30a
ZA		 5865 spin_lock_init(&kvm->arch.tsc_write_lock);
5866
d19a9cd2
ZX		 5867 return kvm;
5868}
5869
5870static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5871{
5872 vcpu_load(vcpu);
5873 kvm_mmu_unload(vcpu);
5874 vcpu_put(vcpu);
5875}
5876
5877static void kvm_free_vcpus(struct kvm *kvm)
5878{
5879 unsigned int i;
988a2cae 5880 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5881
5882 /*
5883 * Unpin any mmu pages first.
5884 */
988a2cae
GN		 5885 kvm_for_each_vcpu(i, vcpu, kvm)
5886 kvm_unload_vcpu_mmu(vcpu);
5887 kvm_for_each_vcpu(i, vcpu, kvm)
5888 kvm_arch_vcpu_free(vcpu);
5889
5890 mutex_lock(&kvm->lock);
5891 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5892 kvm->vcpus[i] = NULL;
d19a9cd2 5893
988a2cae
GN		 5894 atomic_set(&kvm->online_vcpus, 0);
5895 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5896}
5897
ad8ba2cd
SY		 5898void kvm_arch_sync_events(struct kvm *kvm)
5899{
ba4cef31 5900 kvm_free_all_assigned_devices(kvm);
aea924f6 5901 kvm_free_pit(kvm);
ad8ba2cd
SY		 5902}
5903
d19a9cd2
ZX		 5904void kvm_arch_destroy_vm(struct kvm *kvm)
5905{
6eb55818 5906 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5907 kfree(kvm->arch.vpic);
5908 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5909 kvm_free_vcpus(kvm);
5910 kvm_free_physmem(kvm);
3d45830c
AK		 5911 if (kvm->arch.apic_access_page)
5912 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5913 if (kvm->arch.ept_identity_pagetable)
5914 put_page(kvm->arch.ept_identity_pagetable);
64749204 5915 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5916 kfree(kvm);
5917}
0de10343 5918
f7784b8e
MT		 5919int kvm_arch_prepare_memory_region(struct kvm *kvm,
5920 struct kvm_memory_slot *memslot,
0de10343 5921 struct kvm_memory_slot old,
f7784b8e 5922 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5923 int user_alloc)
5924{
f7784b8e 5925 int npages = memslot->npages;
7ac77099
AK		 5926 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5927
5928 /* Prevent internal slot pages from being moved by fork()/COW. */
5929 if (memslot->id >= KVM_MEMORY_SLOTS)
5930 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5931
5932 /*To keep backward compatibility with older userspace,
5933 *x86 needs to hanlde !user_alloc case.
5934 */
5935 if (!user_alloc) {
5936 if (npages && !old.rmap) {
604b38ac
AA		 5937 unsigned long userspace_addr;
5938
72dc67a6 5939 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5940 userspace_addr = do_mmap(NULL, 0,
5941 npages * PAGE_SIZE,
5942 PROT_READ | PROT_WRITE,
7ac77099 5943 map_flags,
604b38ac 5944 0);
72dc67a6 5945 up_write(&current->mm->mmap_sem);
0de10343 5946
604b38ac
AA		 5947 if (IS_ERR((void *)userspace_addr))
5948 return PTR_ERR((void *)userspace_addr);
5949
604b38ac 5950 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5951 }
5952 }
5953
f7784b8e
MT		 5954
5955 return 0;
5956}
5957
5958void kvm_arch_commit_memory_region(struct kvm *kvm,
5959 struct kvm_userspace_memory_region *mem,
5960 struct kvm_memory_slot old,
5961 int user_alloc)
5962{
5963
5964 int npages = mem->memory_size >> PAGE_SHIFT;
5965
5966 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5967 int ret;
5968
5969 down_write(&current->mm->mmap_sem);
5970 ret = do_munmap(current->mm, old.userspace_addr,
5971 old.npages * PAGE_SIZE);
5972 up_write(&current->mm->mmap_sem);
5973 if (ret < 0)
5974 printk(KERN_WARNING
5975 "kvm_vm_ioctl_set_memory_region: "
5976 "failed to munmap memory\n");
5977 }
5978
7c8a83b7 5979 spin_lock(&kvm->mmu_lock);
f05e70ac 5980 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5981 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5982 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5983 }
5984
5985 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5986 spin_unlock(&kvm->mmu_lock);
0de10343 5987}
1d737c8a 5988
34d4cb8f
MT		 5989void kvm_arch_flush_shadow(struct kvm *kvm)
5990{
5991 kvm_mmu_zap_all(kvm);
8986ecc0 5992 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5993}
5994
1d737c8a
ZX		 5995int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5996{
a4535290 5997 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5998 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5999 || vcpu->arch.nmi_pending ||
6000 (kvm_arch_interrupt_allowed(vcpu) &&
6001 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6002}
5736199a 6003
5736199a
ZX		 6004void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6005{
32f88400
MT		 6006 int me;
6007 int cpu = vcpu->cpu;
5736199a
ZX		 6008
6009 if (waitqueue_active(&vcpu->wq)) {
6010 wake_up_interruptible(&vcpu->wq);
6011 ++vcpu->stat.halt_wakeup;
6012 }
32f88400
MT		 6013
6014 me = get_cpu();
6015 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 6016 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 6017 smp_send_reschedule(cpu);
e9571ed5 6018 put_cpu();
5736199a 6019}
78646121
GN		 6020
6021int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6022{
6023 return kvm_x86_ops->interrupt_allowed(vcpu);
6024}
229456fc 6025
f92653ee
JK		 6026bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6027{
6028 unsigned long current_rip = kvm_rip_read(vcpu) +
6029 get_segment_base(vcpu, VCPU_SREG_CS);
6030
6031 return current_rip == linear_rip;
6032}
6033EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6034
94fe45da
JK		 6035unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6036{
6037 unsigned long rflags;
6038
6039 rflags = kvm_x86_ops->get_rflags(vcpu);
6040 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6041 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6042 return rflags;
6043}
6044EXPORT_SYMBOL_GPL(kvm_get_rflags);
6045
6046void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6047{
6048 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6049 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6050 rflags |= X86_EFLAGS_TF;
94fe45da 6051 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6052 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6053}
6054EXPORT_SYMBOL_GPL(kvm_set_rflags);
6055
229456fc
MT		 6056EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6057EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6058EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6059EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6060EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6061EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6062EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6063EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6064EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6065EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6066EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6067EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)