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KVM: SVM: Report Nested Paging support to userspace
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
221d059d 9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
1d5f066e 58#include <asm/pvclock.h>
217fc9cf 59#include <asm/div64.h>
043405e1 60
313a3dc7 61#define MAX_IO_MSRS 256
a03490ed
CO		 62#define CR0_RESERVED_BITS \
63 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
64 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
65 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
66#define CR4_RESERVED_BITS \
67 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
68 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
69 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 70 | X86_CR4_OSXSAVE \
a03490ed
CO		 71 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
72
73#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 74
75#define KVM_MAX_MCE_BANKS 32
76#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
84#else
85static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
86#endif
313a3dc7 87
ba1389b7
AK		 88#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
89#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 90
cb142eb7 91static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 92static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
93 struct kvm_cpuid_entry2 __user *entries);
94
97896d04 95struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 96EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 97
ed85c068
AP		 98int ignore_msrs = 0;
99module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
100
18863bdd
AK		 101#define KVM_NR_SHARED_MSRS 16
102
103struct kvm_shared_msrs_global {
104 int nr;
2bf78fa7 105 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 106};
107
108struct kvm_shared_msrs {
109 struct user_return_notifier urn;
110 bool registered;
2bf78fa7
SY		 111 struct kvm_shared_msr_values {
112 u64 host;
113 u64 curr;
114 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 115};
116
117static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
118static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
119
417bc304 120struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 121 { "pf_fixed", VCPU_STAT(pf_fixed) },
122 { "pf_guest", VCPU_STAT(pf_guest) },
123 { "tlb_flush", VCPU_STAT(tlb_flush) },
124 { "invlpg", VCPU_STAT(invlpg) },
125 { "exits", VCPU_STAT(exits) },
126 { "io_exits", VCPU_STAT(io_exits) },
127 { "mmio_exits", VCPU_STAT(mmio_exits) },
128 { "signal_exits", VCPU_STAT(signal_exits) },
129 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 130 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 131 { "halt_exits", VCPU_STAT(halt_exits) },
132 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 133 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 134 { "request_irq", VCPU_STAT(request_irq_exits) },
135 { "irq_exits", VCPU_STAT(irq_exits) },
136 { "host_state_reload", VCPU_STAT(host_state_reload) },
137 { "efer_reload", VCPU_STAT(efer_reload) },
138 { "fpu_reload", VCPU_STAT(fpu_reload) },
139 { "insn_emulation", VCPU_STAT(insn_emulation) },
140 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 141 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 142 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 143 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
144 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
145 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
146 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
147 { "mmu_flooded", VM_STAT(mmu_flooded) },
148 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 149 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 150 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 151 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 152 { "largepages", VM_STAT(lpages) },
417bc304
HB		 153 { NULL }
154};
155
2acf923e
DC		 156u64 __read_mostly host_xcr0;
157
158static inline u32 bit(int bitno)
159{
160 return 1 << (bitno & 31);
161}
162
18863bdd
AK		 163static void kvm_on_user_return(struct user_return_notifier *urn)
164{
165 unsigned slot;
18863bdd
AK		 166 struct kvm_shared_msrs *locals
167 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 168 struct kvm_shared_msr_values *values;
18863bdd
AK		 169
170 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 171 values = &locals->values[slot];
172 if (values->host != values->curr) {
173 wrmsrl(shared_msrs_global.msrs[slot], values->host);
174 values->curr = values->host;
18863bdd
AK		 175 }
176 }
177 locals->registered = false;
178 user_return_notifier_unregister(urn);
179}
180
2bf78fa7 181static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 182{
2bf78fa7 183 struct kvm_shared_msrs *smsr;
18863bdd
AK		 184 u64 value;
185
2bf78fa7
SY		 186 smsr = &__get_cpu_var(shared_msrs);
187 /* only read, and nobody should modify it at this time,
188 * so don't need lock */
189 if (slot >= shared_msrs_global.nr) {
190 printk(KERN_ERR "kvm: invalid MSR slot!");
191 return;
192 }
193 rdmsrl_safe(msr, &value);
194 smsr->values[slot].host = value;
195 smsr->values[slot].curr = value;
196}
197
198void kvm_define_shared_msr(unsigned slot, u32 msr)
199{
18863bdd
AK		 200 if (slot >= shared_msrs_global.nr)
201 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 202 shared_msrs_global.msrs[slot] = msr;
203 /* we need ensured the shared_msr_global have been updated */
204 smp_wmb();
18863bdd
AK		 205}
206EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
207
208static void kvm_shared_msr_cpu_online(void)
209{
210 unsigned i;
18863bdd
AK		 211
212 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 213 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 214}
215
d5696725 216void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 217{
218 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
219
2bf78fa7 220 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 221 return;
2bf78fa7
SY		 222 smsr->values[slot].curr = value;
223 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 224 if (!smsr->registered) {
225 smsr->urn.on_user_return = kvm_on_user_return;
226 user_return_notifier_register(&smsr->urn);
227 smsr->registered = true;
228 }
229}
230EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
231
3548bab5
AK		 232static void drop_user_return_notifiers(void *ignore)
233{
234 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
235
236 if (smsr->registered)
237 kvm_on_user_return(&smsr->urn);
238}
239
6866b83e
CO		 240u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
241{
242 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e 244 else
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e
CO		 246}
247EXPORT_SYMBOL_GPL(kvm_get_apic_base);
248
249void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
250{
251 /* TODO: reserve bits check */
252 if (irqchip_in_kernel(vcpu->kvm))
253 kvm_lapic_set_base(vcpu, data);
254 else
ad312c7c 255 vcpu->arch.apic_base = data;
6866b83e
CO		 256}
257EXPORT_SYMBOL_GPL(kvm_set_apic_base);
258
3fd28fce
ED		 259#define EXCPT_BENIGN 0
260#define EXCPT_CONTRIBUTORY 1
261#define EXCPT_PF 2
262
263static int exception_class(int vector)
264{
265 switch (vector) {
266 case PF_VECTOR:
267 return EXCPT_PF;
268 case DE_VECTOR:
269 case TS_VECTOR:
270 case NP_VECTOR:
271 case SS_VECTOR:
272 case GP_VECTOR:
273 return EXCPT_CONTRIBUTORY;
274 default:
275 break;
276 }
277 return EXCPT_BENIGN;
278}
279
280static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 281 unsigned nr, bool has_error, u32 error_code,
282 bool reinject)
3fd28fce
ED		 283{
284 u32 prev_nr;
285 int class1, class2;
286
287 if (!vcpu->arch.exception.pending) {
288 queue:
289 vcpu->arch.exception.pending = true;
290 vcpu->arch.exception.has_error_code = has_error;
291 vcpu->arch.exception.nr = nr;
292 vcpu->arch.exception.error_code = error_code;
3f0fd292 293 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 294 return;
295 }
296
297 /* to check exception */
298 prev_nr = vcpu->arch.exception.nr;
299 if (prev_nr == DF_VECTOR) {
300 /* triple fault -> shutdown */
a8eeb04a 301 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 302 return;
303 }
304 class1 = exception_class(prev_nr);
305 class2 = exception_class(nr);
306 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
307 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
308 /* generate double fault per SDM Table 5-5 */
309 vcpu->arch.exception.pending = true;
310 vcpu->arch.exception.has_error_code = true;
311 vcpu->arch.exception.nr = DF_VECTOR;
312 vcpu->arch.exception.error_code = 0;
313 } else
314 /* replace previous exception with a new one in a hope
315 that instruction re-execution will regenerate lost
316 exception */
317 goto queue;
318}
319
298101da
AK		 320void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
321{
ce7ddec4 322 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 323}
324EXPORT_SYMBOL_GPL(kvm_queue_exception);
325
ce7ddec4
JR		 326void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
327{
328 kvm_multiple_exception(vcpu, nr, false, 0, true);
329}
330EXPORT_SYMBOL_GPL(kvm_requeue_exception);
331
8df25a32 332void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
c3c91fee 333{
8df25a32
JR		 334 unsigned error_code = vcpu->arch.fault.error_code;
335
c3c91fee 336 ++vcpu->stat.pf_guest;
8df25a32 337 vcpu->arch.cr2 = vcpu->arch.fault.address;
c3c91fee
AK		 338 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
339}
340
d4f8cf66
JR		 341void kvm_propagate_fault(struct kvm_vcpu *vcpu)
342{
343 u32 nested, error;
344
345 error = vcpu->arch.fault.error_code;
346 nested = error & PFERR_NESTED_MASK;
347 error = error & ~PFERR_NESTED_MASK;
348
349 vcpu->arch.fault.error_code = error;
350
351 if (mmu_is_nested(vcpu) && !nested)
352 vcpu->arch.nested_mmu.inject_page_fault(vcpu);
353 else
354 vcpu->arch.mmu.inject_page_fault(vcpu);
355}
356
3419ffc8
SY		 357void kvm_inject_nmi(struct kvm_vcpu *vcpu)
358{
359 vcpu->arch.nmi_pending = 1;
360}
361EXPORT_SYMBOL_GPL(kvm_inject_nmi);
362
298101da
AK		 363void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
364{
ce7ddec4 365 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 366}
367EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
368
ce7ddec4
JR		 369void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
370{
371 kvm_multiple_exception(vcpu, nr, true, error_code, true);
372}
373EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
374
0a79b009
AK		 375/*
376 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
377 * a #GP and return false.
378 */
379bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 380{
0a79b009
AK		 381 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
382 return true;
383 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
384 return false;
298101da 385}
0a79b009 386EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 387
ec92fe44
JR		 388/*
389 * This function will be used to read from the physical memory of the currently
390 * running guest. The difference to kvm_read_guest_page is that this function
391 * can read from guest physical or from the guest's guest physical memory.
392 */
393int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
394 gfn_t ngfn, void *data, int offset, int len,
395 u32 access)
396{
397 gfn_t real_gfn;
398 gpa_t ngpa;
399
400 ngpa = gfn_to_gpa(ngfn);
401 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
402 if (real_gfn == UNMAPPED_GVA)
403 return -EFAULT;
404
405 real_gfn = gpa_to_gfn(real_gfn);
406
407 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
408}
409EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
410
3d06b8bf
JR		 411int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
412 void *data, int offset, int len, u32 access)
413{
414 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
415 data, offset, len, access);
416}
417
a03490ed
CO		 418/*
419 * Load the pae pdptrs. Return true is they are all valid.
420 */
ff03a073 421int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 422{
423 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
424 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
425 int i;
426 int ret;
ff03a073 427 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 428
ff03a073
JR		 429 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
430 offset * sizeof(u64), sizeof(pdpte),
431 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 432 if (ret < 0) {
433 ret = 0;
434 goto out;
435 }
436 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 437 if (is_present_gpte(pdpte[i]) &&
20c466b5 438 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 439 ret = 0;
440 goto out;
441 }
442 }
443 ret = 1;
444
ff03a073 445 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 446 __set_bit(VCPU_EXREG_PDPTR,
447 (unsigned long *)&vcpu->arch.regs_avail);
448 __set_bit(VCPU_EXREG_PDPTR,
449 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 450out:
a03490ed
CO		 451
452 return ret;
453}
cc4b6871 454EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 455
d835dfec
AK		 456static bool pdptrs_changed(struct kvm_vcpu *vcpu)
457{
ff03a073 458 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 459 bool changed = true;
3d06b8bf
JR		 460 int offset;
461 gfn_t gfn;
d835dfec
AK		 462 int r;
463
464 if (is_long_mode(vcpu) || !is_pae(vcpu))
465 return false;
466
6de4f3ad
AK		 467 if (!test_bit(VCPU_EXREG_PDPTR,
468 (unsigned long *)&vcpu->arch.regs_avail))
469 return true;
470
3d06b8bf
JR		 471 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
472 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
473 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
474 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 475 if (r < 0)
476 goto out;
ff03a073 477 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 478out:
d835dfec
AK		 479
480 return changed;
481}
482
49a9b07e 483int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 484{
aad82703
SY		 485 unsigned long old_cr0 = kvm_read_cr0(vcpu);
486 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
487 X86_CR0_CD | X86_CR0_NW;
488
f9a48e6a
AK		 489 cr0 |= X86_CR0_ET;
490
ab344828 491#ifdef CONFIG_X86_64
0f12244f
GN		 492 if (cr0 & 0xffffffff00000000UL)
493 return 1;
ab344828
GN		 494#endif
495
496 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 497
0f12244f
GN		 498 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
499 return 1;
a03490ed 500
0f12244f
GN		 501 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
502 return 1;
a03490ed
CO		 503
504 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
505#ifdef CONFIG_X86_64
f6801dff 506 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 507 int cs_db, cs_l;
508
0f12244f
GN		 509 if (!is_pae(vcpu))
510 return 1;
a03490ed 511 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 512 if (cs_l)
513 return 1;
a03490ed
CO		 514 } else
515#endif
ff03a073
JR		 516 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
517 vcpu->arch.cr3))
0f12244f 518 return 1;
a03490ed
CO		 519 }
520
521 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 522
aad82703
SY		 523 if ((cr0 ^ old_cr0) & update_bits)
524 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 525 return 0;
526}
2d3ad1f4 527EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 528
2d3ad1f4 529void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 530{
49a9b07e 531 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 532}
2d3ad1f4 533EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 534
2acf923e
DC		 535int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
536{
537 u64 xcr0;
538
539 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
540 if (index != XCR_XFEATURE_ENABLED_MASK)
541 return 1;
542 xcr0 = xcr;
543 if (kvm_x86_ops->get_cpl(vcpu) != 0)
544 return 1;
545 if (!(xcr0 & XSTATE_FP))
546 return 1;
547 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
548 return 1;
549 if (xcr0 & ~host_xcr0)
550 return 1;
551 vcpu->arch.xcr0 = xcr0;
552 vcpu->guest_xcr0_loaded = 0;
553 return 0;
554}
555
556int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
557{
558 if (__kvm_set_xcr(vcpu, index, xcr)) {
559 kvm_inject_gp(vcpu, 0);
560 return 1;
561 }
562 return 0;
563}
564EXPORT_SYMBOL_GPL(kvm_set_xcr);
565
566static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
567{
568 struct kvm_cpuid_entry2 *best;
569
570 best = kvm_find_cpuid_entry(vcpu, 1, 0);
571 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
572}
573
574static void update_cpuid(struct kvm_vcpu *vcpu)
575{
576 struct kvm_cpuid_entry2 *best;
577
578 best = kvm_find_cpuid_entry(vcpu, 1, 0);
579 if (!best)
580 return;
581
582 /* Update OSXSAVE bit */
583 if (cpu_has_xsave && best->function == 0x1) {
584 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
585 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
586 best->ecx |= bit(X86_FEATURE_OSXSAVE);
587 }
588}
589
a83b29c6 590int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 591{
fc78f519 592 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 593 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
594
0f12244f
GN		 595 if (cr4 & CR4_RESERVED_BITS)
596 return 1;
a03490ed 597
2acf923e
DC		 598 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
599 return 1;
600
a03490ed 601 if (is_long_mode(vcpu)) {
0f12244f
GN		 602 if (!(cr4 & X86_CR4_PAE))
603 return 1;
a2edf57f
AK		 604 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
605 && ((cr4 ^ old_cr4) & pdptr_bits)
ff03a073 606 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
0f12244f
GN		 607 return 1;
608
609 if (cr4 & X86_CR4_VMXE)
610 return 1;
a03490ed 611
a03490ed 612 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 613
aad82703
SY		 614 if ((cr4 ^ old_cr4) & pdptr_bits)
615 kvm_mmu_reset_context(vcpu);
0f12244f 616
2acf923e
DC		 617 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
618 update_cpuid(vcpu);
619
0f12244f
GN		 620 return 0;
621}
2d3ad1f4 622EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 623
2390218b 624int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 625{
ad312c7c 626 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 627 kvm_mmu_sync_roots(vcpu);
d835dfec 628 kvm_mmu_flush_tlb(vcpu);
0f12244f 629 return 0;
d835dfec
AK		 630 }
631
a03490ed 632 if (is_long_mode(vcpu)) {
0f12244f
GN		 633 if (cr3 & CR3_L_MODE_RESERVED_BITS)
634 return 1;
a03490ed
CO		 635 } else {
636 if (is_pae(vcpu)) {
0f12244f
GN		 637 if (cr3 & CR3_PAE_RESERVED_BITS)
638 return 1;
ff03a073
JR		 639 if (is_paging(vcpu) &&
640 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 641 return 1;
a03490ed
CO		 642 }
643 /*
644 * We don't check reserved bits in nonpae mode, because
645 * this isn't enforced, and VMware depends on this.
646 */
647 }
648
a03490ed
CO		 649 /*
650 * Does the new cr3 value map to physical memory? (Note, we
651 * catch an invalid cr3 even in real-mode, because it would
652 * cause trouble later on when we turn on paging anyway.)
653 *
654 * A real CPU would silently accept an invalid cr3 and would
655 * attempt to use it - with largely undefined (and often hard
656 * to debug) behavior on the guest side.
657 */
658 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 659 return 1;
660 vcpu->arch.cr3 = cr3;
661 vcpu->arch.mmu.new_cr3(vcpu);
662 return 0;
663}
2d3ad1f4 664EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 665
0f12244f 666int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 667{
0f12244f
GN		 668 if (cr8 & CR8_RESERVED_BITS)
669 return 1;
a03490ed
CO		 670 if (irqchip_in_kernel(vcpu->kvm))
671 kvm_lapic_set_tpr(vcpu, cr8);
672 else
ad312c7c 673 vcpu->arch.cr8 = cr8;
0f12244f
GN		 674 return 0;
675}
676
677void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
678{
679 if (__kvm_set_cr8(vcpu, cr8))
680 kvm_inject_gp(vcpu, 0);
a03490ed 681}
2d3ad1f4 682EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 683
2d3ad1f4 684unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 685{
686 if (irqchip_in_kernel(vcpu->kvm))
687 return kvm_lapic_get_cr8(vcpu);
688 else
ad312c7c 689 return vcpu->arch.cr8;
a03490ed 690}
2d3ad1f4 691EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 692
338dbc97 693static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 694{
695 switch (dr) {
696 case 0 ... 3:
697 vcpu->arch.db[dr] = val;
698 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
699 vcpu->arch.eff_db[dr] = val;
700 break;
701 case 4:
338dbc97
GN		 702 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
703 return 1; /* #UD */
020df079
GN		 704 /* fall through */
705 case 6:
338dbc97
GN		 706 if (val & 0xffffffff00000000ULL)
707 return -1; /* #GP */
020df079
GN		 708 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
709 break;
710 case 5:
338dbc97
GN		 711 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
712 return 1; /* #UD */
020df079
GN		 713 /* fall through */
714 default: /* 7 */
338dbc97
GN		 715 if (val & 0xffffffff00000000ULL)
716 return -1; /* #GP */
020df079
GN		 717 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
718 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
719 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
720 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
721 }
722 break;
723 }
724
725 return 0;
726}
338dbc97
GN		 727
728int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
729{
730 int res;
731
732 res = __kvm_set_dr(vcpu, dr, val);
733 if (res > 0)
734 kvm_queue_exception(vcpu, UD_VECTOR);
735 else if (res < 0)
736 kvm_inject_gp(vcpu, 0);
737
738 return res;
739}
020df079
GN		 740EXPORT_SYMBOL_GPL(kvm_set_dr);
741
338dbc97 742static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 743{
744 switch (dr) {
745 case 0 ... 3:
746 *val = vcpu->arch.db[dr];
747 break;
748 case 4:
338dbc97 749 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 750 return 1;
020df079
GN		 751 /* fall through */
752 case 6:
753 *val = vcpu->arch.dr6;
754 break;
755 case 5:
338dbc97 756 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 757 return 1;
020df079
GN		 758 /* fall through */
759 default: /* 7 */
760 *val = vcpu->arch.dr7;
761 break;
762 }
763
764 return 0;
765}
338dbc97
GN		 766
767int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
768{
769 if (_kvm_get_dr(vcpu, dr, val)) {
770 kvm_queue_exception(vcpu, UD_VECTOR);
771 return 1;
772 }
773 return 0;
774}
020df079
GN		 775EXPORT_SYMBOL_GPL(kvm_get_dr);
776
043405e1
CO		 777/*
778 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
779 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
780 *
781 * This list is modified at module load time to reflect the
e3267cbb
GC		 782 * capabilities of the host cpu. This capabilities test skips MSRs that are
783 * kvm-specific. Those are put in the beginning of the list.
043405e1 784 */
e3267cbb 785
11c6bffa 786#define KVM_SAVE_MSRS_BEGIN 7
043405e1 787static u32 msrs_to_save[] = {
e3267cbb 788 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 789 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 790 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 791 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1 792 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 793 MSR_STAR,
043405e1
CO		 794#ifdef CONFIG_X86_64
795 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
796#endif
e90aa41e 797 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 798};
799
800static unsigned num_msrs_to_save;
801
802static u32 emulated_msrs[] = {
803 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 804 MSR_IA32_MCG_STATUS,
805 MSR_IA32_MCG_CTL,
043405e1
CO		 806};
807
b69e8cae 808static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 809{
aad82703
SY		 810 u64 old_efer = vcpu->arch.efer;
811
b69e8cae
RJ		 812 if (efer & efer_reserved_bits)
813 return 1;
15c4a640
CO		 814
815 if (is_paging(vcpu)
b69e8cae
RJ		 816 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
817 return 1;
15c4a640 818
1b2fd70c
AG		 819 if (efer & EFER_FFXSR) {
820 struct kvm_cpuid_entry2 *feat;
821
822 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 823 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
824 return 1;
1b2fd70c
AG		 825 }
826
d8017474
AG		 827 if (efer & EFER_SVME) {
828 struct kvm_cpuid_entry2 *feat;
829
830 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 831 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
832 return 1;
d8017474
AG		 833 }
834
15c4a640 835 efer &= ~EFER_LMA;
f6801dff 836 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 837
a3d204e2
SY		 838 kvm_x86_ops->set_efer(vcpu, efer);
839
9645bb56
AK		 840 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
841 kvm_mmu_reset_context(vcpu);
b69e8cae 842
aad82703
SY		 843 /* Update reserved bits */
844 if ((efer ^ old_efer) & EFER_NX)
845 kvm_mmu_reset_context(vcpu);
846
b69e8cae 847 return 0;
15c4a640
CO		 848}
849
f2b4b7dd
JR		 850void kvm_enable_efer_bits(u64 mask)
851{
852 efer_reserved_bits &= ~mask;
853}
854EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
855
856
15c4a640
CO		 857/*
858 * Writes msr value into into the appropriate "register".
859 * Returns 0 on success, non-0 otherwise.
860 * Assumes vcpu_load() was already called.
861 */
862int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
863{
864 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
865}
866
313a3dc7
CO		 867/*
868 * Adapt set_msr() to msr_io()'s calling convention
869 */
870static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
871{
872 return kvm_set_msr(vcpu, index, *data);
873}
874
18068523
GOC		 875static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
876{
9ed3c444
AK		 877 int version;
878 int r;
50d0a0f9 879 struct pvclock_wall_clock wc;
923de3cf 880 struct timespec boot;
18068523
GOC		 881
882 if (!wall_clock)
883 return;
884
9ed3c444
AK		 885 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
886 if (r)
887 return;
888
889 if (version & 1)
890 ++version; /* first time write, random junk */
891
892 ++version;
18068523 893
18068523
GOC		 894 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
895
50d0a0f9
GH		 896 /*
897 * The guest calculates current wall clock time by adding
898 * system time (updated by kvm_write_guest_time below) to the
899 * wall clock specified here. guest system time equals host
900 * system time for us, thus we must fill in host boot time here.
901 */
923de3cf 902 getboottime(&boot);
50d0a0f9
GH		 903
904 wc.sec = boot.tv_sec;
905 wc.nsec = boot.tv_nsec;
906 wc.version = version;
18068523
GOC		 907
908 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
909
910 version++;
911 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 912}
913
50d0a0f9
GH		 914static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
915{
916 uint32_t quotient, remainder;
917
918 /* Don't try to replace with do_div(), this one calculates
919 * "(dividend << 32) / divisor" */
920 __asm__ ( "divl %4"
921 : "=a" (quotient), "=d" (remainder)
922 : "0" (0), "1" (dividend), "r" (divisor) );
923 return quotient;
924}
925
926static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
927{
928 uint64_t nsecs = 1000000000LL;
929 int32_t shift = 0;
930 uint64_t tps64;
931 uint32_t tps32;
932
933 tps64 = tsc_khz * 1000LL;
934 while (tps64 > nsecs*2) {
935 tps64 >>= 1;
936 shift--;
937 }
938
939 tps32 = (uint32_t)tps64;
940 while (tps32 <= (uint32_t)nsecs) {
941 tps32 <<= 1;
942 shift++;
943 }
944
945 hv_clock->tsc_shift = shift;
946 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
947
948 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 949 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 950 hv_clock->tsc_to_system_mul);
951}
952
759379dd
ZA		 953static inline u64 get_kernel_ns(void)
954{
955 struct timespec ts;
956
957 WARN_ON(preemptible());
958 ktime_get_ts(&ts);
959 monotonic_to_bootbased(&ts);
960 return timespec_to_ns(&ts);
961}
962
c8076604
GH		 963static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
964
8cfdc000
ZA		 965static inline int kvm_tsc_changes_freq(void)
966{
967 int cpu = get_cpu();
968 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
969 cpufreq_quick_get(cpu) != 0;
970 put_cpu();
971 return ret;
972}
973
759379dd
ZA		 974static inline u64 nsec_to_cycles(u64 nsec)
975{
217fc9cf
AK		 976 u64 ret;
977
759379dd
ZA		 978 WARN_ON(preemptible());
979 if (kvm_tsc_changes_freq())
980 printk_once(KERN_WARNING
981 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 982 ret = nsec * __get_cpu_var(cpu_tsc_khz);
983 do_div(ret, USEC_PER_SEC);
984 return ret;
759379dd
ZA		 985}
986
99e3e30a
ZA		 987void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
988{
989 struct kvm *kvm = vcpu->kvm;
f38e098f 990 u64 offset, ns, elapsed;
99e3e30a 991 unsigned long flags;
46543ba4 992 s64 sdiff;
99e3e30a
ZA		 993
994 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
995 offset = data - native_read_tsc();
759379dd 996 ns = get_kernel_ns();
f38e098f 997 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 998 sdiff = data - kvm->arch.last_tsc_write;
999 if (sdiff < 0)
1000 sdiff = -sdiff;
f38e098f
ZA		 1001
1002 /*
46543ba4 1003 * Special case: close write to TSC within 5 seconds of
f38e098f 1004 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 1005 * The 5 seconds is to accomodate host load / swapping as
1006 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1007 *
1008 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1009 * or make a best guest using elapsed value.
f38e098f 1010 */
46543ba4
ZA		 1011 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1012 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1013 if (!check_tsc_unstable()) {
1014 offset = kvm->arch.last_tsc_offset;
1015 pr_debug("kvm: matched tsc offset for %llu\n", data);
1016 } else {
759379dd
ZA		 1017 u64 delta = nsec_to_cycles(elapsed);
1018 offset += delta;
1019 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1020 }
1021 ns = kvm->arch.last_tsc_nsec;
1022 }
1023 kvm->arch.last_tsc_nsec = ns;
1024 kvm->arch.last_tsc_write = data;
1025 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1026 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1027 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1028
1029 /* Reset of TSC must disable overshoot protection below */
1030 vcpu->arch.hv_clock.tsc_timestamp = 0;
1031}
1032EXPORT_SYMBOL_GPL(kvm_write_tsc);
1033
8cfdc000 1034static int kvm_write_guest_time(struct kvm_vcpu *v)
18068523 1035{
18068523
GOC		 1036 unsigned long flags;
1037 struct kvm_vcpu_arch *vcpu = &v->arch;
1038 void *shared_kaddr;
463656c0 1039 unsigned long this_tsc_khz;
1d5f066e
ZA		 1040 s64 kernel_ns, max_kernel_ns;
1041 u64 tsc_timestamp;
18068523
GOC		 1042
1043 if ((!vcpu->time_page))
8cfdc000 1044 return 0;
50d0a0f9 1045
18068523
GOC		 1046 /* Keep irq disabled to prevent changes to the clock */
1047 local_irq_save(flags);
1d5f066e 1048 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1049 kernel_ns = get_kernel_ns();
8cfdc000 1050 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523
GOC		 1051 local_irq_restore(flags);
1052
8cfdc000
ZA		 1053 if (unlikely(this_tsc_khz == 0)) {
1054 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
1055 return 1;
1056 }
18068523 1057
1d5f066e
ZA		 1058 /*
1059 * Time as measured by the TSC may go backwards when resetting the base
1060 * tsc_timestamp. The reason for this is that the TSC resolution is
1061 * higher than the resolution of the other clock scales. Thus, many
1062 * possible measurments of the TSC correspond to one measurement of any
1063 * other clock, and so a spread of values is possible. This is not a
1064 * problem for the computation of the nanosecond clock; with TSC rates
1065 * around 1GHZ, there can only be a few cycles which correspond to one
1066 * nanosecond value, and any path through this code will inevitably
1067 * take longer than that. However, with the kernel_ns value itself,
1068 * the precision may be much lower, down to HZ granularity. If the
1069 * first sampling of TSC against kernel_ns ends in the low part of the
1070 * range, and the second in the high end of the range, we can get:
1071 *
1072 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1073 *
1074 * As the sampling errors potentially range in the thousands of cycles,
1075 * it is possible such a time value has already been observed by the
1076 * guest. To protect against this, we must compute the system time as
1077 * observed by the guest and ensure the new system time is greater.
1078 */
1079 max_kernel_ns = 0;
1080 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1081 max_kernel_ns = vcpu->last_guest_tsc -
1082 vcpu->hv_clock.tsc_timestamp;
1083 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1084 vcpu->hv_clock.tsc_to_system_mul,
1085 vcpu->hv_clock.tsc_shift);
1086 max_kernel_ns += vcpu->last_kernel_ns;
1087 }
1088
e48672fa 1089 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
8cfdc000 1090 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
e48672fa 1091 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1092 }
1093
1d5f066e
ZA		 1094 if (max_kernel_ns > kernel_ns)
1095 kernel_ns = max_kernel_ns;
1096
8cfdc000 1097 /* With all the info we got, fill in the values */
1d5f066e 1098 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1099 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1100 vcpu->last_kernel_ns = kernel_ns;
371bcf64
GC		 1101 vcpu->hv_clock.flags = 0;
1102
18068523
GOC		 1103 /*
1104 * The interface expects us to write an even number signaling that the
1105 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1106 * state, we just increase by 2 at the end.
18068523 1107 */
50d0a0f9 1108 vcpu->hv_clock.version += 2;
18068523
GOC		 1109
1110 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1111
1112 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1113 sizeof(vcpu->hv_clock));
18068523
GOC		 1114
1115 kunmap_atomic(shared_kaddr, KM_USER0);
1116
1117 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1118 return 0;
18068523
GOC		 1119}
1120
c8076604
GH		 1121static int kvm_request_guest_time_update(struct kvm_vcpu *v)
1122{
1123 struct kvm_vcpu_arch *vcpu = &v->arch;
1124
1125 if (!vcpu->time_page)
1126 return 0;
a8eeb04a 1127 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
c8076604
GH		 1128 return 1;
1129}
1130
9ba075a6
AK		 1131static bool msr_mtrr_valid(unsigned msr)
1132{
1133 switch (msr) {
1134 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1135 case MSR_MTRRfix64K_00000:
1136 case MSR_MTRRfix16K_80000:
1137 case MSR_MTRRfix16K_A0000:
1138 case MSR_MTRRfix4K_C0000:
1139 case MSR_MTRRfix4K_C8000:
1140 case MSR_MTRRfix4K_D0000:
1141 case MSR_MTRRfix4K_D8000:
1142 case MSR_MTRRfix4K_E0000:
1143 case MSR_MTRRfix4K_E8000:
1144 case MSR_MTRRfix4K_F0000:
1145 case MSR_MTRRfix4K_F8000:
1146 case MSR_MTRRdefType:
1147 case MSR_IA32_CR_PAT:
1148 return true;
1149 case 0x2f8:
1150 return true;
1151 }
1152 return false;
1153}
1154
d6289b93
MT		 1155static bool valid_pat_type(unsigned t)
1156{
1157 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1158}
1159
1160static bool valid_mtrr_type(unsigned t)
1161{
1162 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1163}
1164
1165static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1166{
1167 int i;
1168
1169 if (!msr_mtrr_valid(msr))
1170 return false;
1171
1172 if (msr == MSR_IA32_CR_PAT) {
1173 for (i = 0; i < 8; i++)
1174 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1175 return false;
1176 return true;
1177 } else if (msr == MSR_MTRRdefType) {
1178 if (data & ~0xcff)
1179 return false;
1180 return valid_mtrr_type(data & 0xff);
1181 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1182 for (i = 0; i < 8 ; i++)
1183 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1184 return false;
1185 return true;
1186 }
1187
1188 /* variable MTRRs */
1189 return valid_mtrr_type(data & 0xff);
1190}
1191
9ba075a6
AK		 1192static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1193{
0bed3b56
SY		 1194 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1195
d6289b93 1196 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1197 return 1;
1198
0bed3b56
SY		 1199 if (msr == MSR_MTRRdefType) {
1200 vcpu->arch.mtrr_state.def_type = data;
1201 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1202 } else if (msr == MSR_MTRRfix64K_00000)
1203 p[0] = data;
1204 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1205 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1206 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1207 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1208 else if (msr == MSR_IA32_CR_PAT)
1209 vcpu->arch.pat = data;
1210 else { /* Variable MTRRs */
1211 int idx, is_mtrr_mask;
1212 u64 *pt;
1213
1214 idx = (msr - 0x200) / 2;
1215 is_mtrr_mask = msr - 0x200 - 2 * idx;
1216 if (!is_mtrr_mask)
1217 pt =
1218 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1219 else
1220 pt =
1221 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1222 *pt = data;
1223 }
1224
1225 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1226 return 0;
1227}
15c4a640 1228
890ca9ae 1229static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1230{
890ca9ae
HY		 1231 u64 mcg_cap = vcpu->arch.mcg_cap;
1232 unsigned bank_num = mcg_cap & 0xff;
1233
15c4a640 1234 switch (msr) {
15c4a640 1235 case MSR_IA32_MCG_STATUS:
890ca9ae 1236 vcpu->arch.mcg_status = data;
15c4a640 1237 break;
c7ac679c 1238 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1239 if (!(mcg_cap & MCG_CTL_P))
1240 return 1;
1241 if (data != 0 && data != ~(u64)0)
1242 return -1;
1243 vcpu->arch.mcg_ctl = data;
1244 break;
1245 default:
1246 if (msr >= MSR_IA32_MC0_CTL &&
1247 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1248 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1249 /* only 0 or all 1s can be written to IA32_MCi_CTL
1250 * some Linux kernels though clear bit 10 in bank 4 to
1251 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1252 * this to avoid an uncatched #GP in the guest
1253 */
890ca9ae 1254 if ((offset & 0x3) == 0 &&
114be429 1255 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1256 return -1;
1257 vcpu->arch.mce_banks[offset] = data;
1258 break;
1259 }
1260 return 1;
1261 }
1262 return 0;
1263}
1264
ffde22ac
ES		 1265static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1266{
1267 struct kvm *kvm = vcpu->kvm;
1268 int lm = is_long_mode(vcpu);
1269 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1270 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1271 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1272 : kvm->arch.xen_hvm_config.blob_size_32;
1273 u32 page_num = data & ~PAGE_MASK;
1274 u64 page_addr = data & PAGE_MASK;
1275 u8 *page;
1276 int r;
1277
1278 r = -E2BIG;
1279 if (page_num >= blob_size)
1280 goto out;
1281 r = -ENOMEM;
1282 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1283 if (!page)
1284 goto out;
1285 r = -EFAULT;
1286 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1287 goto out_free;
1288 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1289 goto out_free;
1290 r = 0;
1291out_free:
1292 kfree(page);
1293out:
1294 return r;
1295}
1296
55cd8e5a
GN		 1297static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1298{
1299 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1300}
1301
1302static bool kvm_hv_msr_partition_wide(u32 msr)
1303{
1304 bool r = false;
1305 switch (msr) {
1306 case HV_X64_MSR_GUEST_OS_ID:
1307 case HV_X64_MSR_HYPERCALL:
1308 r = true;
1309 break;
1310 }
1311
1312 return r;
1313}
1314
1315static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1316{
1317 struct kvm *kvm = vcpu->kvm;
1318
1319 switch (msr) {
1320 case HV_X64_MSR_GUEST_OS_ID:
1321 kvm->arch.hv_guest_os_id = data;
1322 /* setting guest os id to zero disables hypercall page */
1323 if (!kvm->arch.hv_guest_os_id)
1324 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1325 break;
1326 case HV_X64_MSR_HYPERCALL: {
1327 u64 gfn;
1328 unsigned long addr;
1329 u8 instructions[4];
1330
1331 /* if guest os id is not set hypercall should remain disabled */
1332 if (!kvm->arch.hv_guest_os_id)
1333 break;
1334 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1335 kvm->arch.hv_hypercall = data;
1336 break;
1337 }
1338 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1339 addr = gfn_to_hva(kvm, gfn);
1340 if (kvm_is_error_hva(addr))
1341 return 1;
1342 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1343 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1344 if (copy_to_user((void __user *)addr, instructions, 4))
1345 return 1;
1346 kvm->arch.hv_hypercall = data;
1347 break;
1348 }
1349 default:
1350 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1351 "data 0x%llx\n", msr, data);
1352 return 1;
1353 }
1354 return 0;
1355}
1356
1357static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1358{
10388a07
GN		 1359 switch (msr) {
1360 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1361 unsigned long addr;
55cd8e5a 1362
10388a07
GN		 1363 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1364 vcpu->arch.hv_vapic = data;
1365 break;
1366 }
1367 addr = gfn_to_hva(vcpu->kvm, data >>
1368 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1369 if (kvm_is_error_hva(addr))
1370 return 1;
1371 if (clear_user((void __user *)addr, PAGE_SIZE))
1372 return 1;
1373 vcpu->arch.hv_vapic = data;
1374 break;
1375 }
1376 case HV_X64_MSR_EOI:
1377 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1378 case HV_X64_MSR_ICR:
1379 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1380 case HV_X64_MSR_TPR:
1381 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1382 default:
1383 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1384 "data 0x%llx\n", msr, data);
1385 return 1;
1386 }
1387
1388 return 0;
55cd8e5a
GN		 1389}
1390
15c4a640
CO		 1391int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1392{
1393 switch (msr) {
15c4a640 1394 case MSR_EFER:
b69e8cae 1395 return set_efer(vcpu, data);
8f1589d9
AP		 1396 case MSR_K7_HWCR:
1397 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1398 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1399 if (data != 0) {
1400 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1401 data);
1402 return 1;
1403 }
15c4a640 1404 break;
f7c6d140
AP		 1405 case MSR_FAM10H_MMIO_CONF_BASE:
1406 if (data != 0) {
1407 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1408 "0x%llx\n", data);
1409 return 1;
1410 }
15c4a640 1411 break;
c323c0e5 1412 case MSR_AMD64_NB_CFG:
c7ac679c 1413 break;
b5e2fec0
AG		 1414 case MSR_IA32_DEBUGCTLMSR:
1415 if (!data) {
1416 /* We support the non-activated case already */
1417 break;
1418 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1419 /* Values other than LBR and BTF are vendor-specific,
1420 thus reserved and should throw a #GP */
1421 return 1;
1422 }
1423 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1424 __func__, data);
1425 break;
15c4a640
CO		 1426 case MSR_IA32_UCODE_REV:
1427 case MSR_IA32_UCODE_WRITE:
61a6bd67 1428 case MSR_VM_HSAVE_PA:
6098ca93 1429 case MSR_AMD64_PATCH_LOADER:
15c4a640 1430 break;
9ba075a6
AK		 1431 case 0x200 ... 0x2ff:
1432 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1433 case MSR_IA32_APICBASE:
1434 kvm_set_apic_base(vcpu, data);
1435 break;
0105d1a5
GN		 1436 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1437 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1438 case MSR_IA32_MISC_ENABLE:
ad312c7c 1439 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1440 break;
11c6bffa 1441 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1442 case MSR_KVM_WALL_CLOCK:
1443 vcpu->kvm->arch.wall_clock = data;
1444 kvm_write_wall_clock(vcpu->kvm, data);
1445 break;
11c6bffa 1446 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1447 case MSR_KVM_SYSTEM_TIME: {
1448 if (vcpu->arch.time_page) {
1449 kvm_release_page_dirty(vcpu->arch.time_page);
1450 vcpu->arch.time_page = NULL;
1451 }
1452
1453 vcpu->arch.time = data;
1454
1455 /* we verify if the enable bit is set... */
1456 if (!(data & 1))
1457 break;
1458
1459 /* ...but clean it before doing the actual write */
1460 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1461
18068523
GOC		 1462 vcpu->arch.time_page =
1463 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1464
1465 if (is_error_page(vcpu->arch.time_page)) {
1466 kvm_release_page_clean(vcpu->arch.time_page);
1467 vcpu->arch.time_page = NULL;
1468 }
1469
c8076604 1470 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1471 break;
1472 }
890ca9ae
HY		 1473 case MSR_IA32_MCG_CTL:
1474 case MSR_IA32_MCG_STATUS:
1475 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1476 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1477
1478 /* Performance counters are not protected by a CPUID bit,
1479 * so we should check all of them in the generic path for the sake of
1480 * cross vendor migration.
1481 * Writing a zero into the event select MSRs disables them,
1482 * which we perfectly emulate ;-). Any other value should be at least
1483 * reported, some guests depend on them.
1484 */
1485 case MSR_P6_EVNTSEL0:
1486 case MSR_P6_EVNTSEL1:
1487 case MSR_K7_EVNTSEL0:
1488 case MSR_K7_EVNTSEL1:
1489 case MSR_K7_EVNTSEL2:
1490 case MSR_K7_EVNTSEL3:
1491 if (data != 0)
1492 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1493 "0x%x data 0x%llx\n", msr, data);
1494 break;
1495 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1496 * so we ignore writes to make it happy.
1497 */
1498 case MSR_P6_PERFCTR0:
1499 case MSR_P6_PERFCTR1:
1500 case MSR_K7_PERFCTR0:
1501 case MSR_K7_PERFCTR1:
1502 case MSR_K7_PERFCTR2:
1503 case MSR_K7_PERFCTR3:
1504 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1505 "0x%x data 0x%llx\n", msr, data);
1506 break;
84e0cefa
JS		 1507 case MSR_K7_CLK_CTL:
1508 /*
1509 * Ignore all writes to this no longer documented MSR.
1510 * Writes are only relevant for old K7 processors,
1511 * all pre-dating SVM, but a recommended workaround from
1512 * AMD for these chips. It is possible to speicify the
1513 * affected processor models on the command line, hence
1514 * the need to ignore the workaround.
1515 */
1516 break;
55cd8e5a
GN		 1517 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1518 if (kvm_hv_msr_partition_wide(msr)) {
1519 int r;
1520 mutex_lock(&vcpu->kvm->lock);
1521 r = set_msr_hyperv_pw(vcpu, msr, data);
1522 mutex_unlock(&vcpu->kvm->lock);
1523 return r;
1524 } else
1525 return set_msr_hyperv(vcpu, msr, data);
1526 break;
15c4a640 1527 default:
ffde22ac
ES		 1528 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1529 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1530 if (!ignore_msrs) {
1531 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1532 msr, data);
1533 return 1;
1534 } else {
1535 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1536 msr, data);
1537 break;
1538 }
15c4a640
CO		 1539 }
1540 return 0;
1541}
1542EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1543
1544
1545/*
1546 * Reads an msr value (of 'msr_index') into 'pdata'.
1547 * Returns 0 on success, non-0 otherwise.
1548 * Assumes vcpu_load() was already called.
1549 */
1550int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1551{
1552 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1553}
1554
9ba075a6
AK		 1555static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1556{
0bed3b56
SY		 1557 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1558
9ba075a6
AK		 1559 if (!msr_mtrr_valid(msr))
1560 return 1;
1561
0bed3b56
SY		 1562 if (msr == MSR_MTRRdefType)
1563 *pdata = vcpu->arch.mtrr_state.def_type +
1564 (vcpu->arch.mtrr_state.enabled << 10);
1565 else if (msr == MSR_MTRRfix64K_00000)
1566 *pdata = p[0];
1567 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1568 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1569 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1570 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1571 else if (msr == MSR_IA32_CR_PAT)
1572 *pdata = vcpu->arch.pat;
1573 else { /* Variable MTRRs */
1574 int idx, is_mtrr_mask;
1575 u64 *pt;
1576
1577 idx = (msr - 0x200) / 2;
1578 is_mtrr_mask = msr - 0x200 - 2 * idx;
1579 if (!is_mtrr_mask)
1580 pt =
1581 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1582 else
1583 pt =
1584 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1585 *pdata = *pt;
1586 }
1587
9ba075a6
AK		 1588 return 0;
1589}
1590
890ca9ae 1591static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1592{
1593 u64 data;
890ca9ae
HY		 1594 u64 mcg_cap = vcpu->arch.mcg_cap;
1595 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1596
1597 switch (msr) {
15c4a640
CO		 1598 case MSR_IA32_P5_MC_ADDR:
1599 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1600 data = 0;
1601 break;
15c4a640 1602 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1603 data = vcpu->arch.mcg_cap;
1604 break;
c7ac679c 1605 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1606 if (!(mcg_cap & MCG_CTL_P))
1607 return 1;
1608 data = vcpu->arch.mcg_ctl;
1609 break;
1610 case MSR_IA32_MCG_STATUS:
1611 data = vcpu->arch.mcg_status;
1612 break;
1613 default:
1614 if (msr >= MSR_IA32_MC0_CTL &&
1615 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1616 u32 offset = msr - MSR_IA32_MC0_CTL;
1617 data = vcpu->arch.mce_banks[offset];
1618 break;
1619 }
1620 return 1;
1621 }
1622 *pdata = data;
1623 return 0;
1624}
1625
55cd8e5a
GN		 1626static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1627{
1628 u64 data = 0;
1629 struct kvm *kvm = vcpu->kvm;
1630
1631 switch (msr) {
1632 case HV_X64_MSR_GUEST_OS_ID:
1633 data = kvm->arch.hv_guest_os_id;
1634 break;
1635 case HV_X64_MSR_HYPERCALL:
1636 data = kvm->arch.hv_hypercall;
1637 break;
1638 default:
1639 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1640 return 1;
1641 }
1642
1643 *pdata = data;
1644 return 0;
1645}
1646
1647static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1648{
1649 u64 data = 0;
1650
1651 switch (msr) {
1652 case HV_X64_MSR_VP_INDEX: {
1653 int r;
1654 struct kvm_vcpu *v;
1655 kvm_for_each_vcpu(r, v, vcpu->kvm)
1656 if (v == vcpu)
1657 data = r;
1658 break;
1659 }
10388a07
GN		 1660 case HV_X64_MSR_EOI:
1661 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1662 case HV_X64_MSR_ICR:
1663 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1664 case HV_X64_MSR_TPR:
1665 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1666 default:
1667 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1668 return 1;
1669 }
1670 *pdata = data;
1671 return 0;
1672}
1673
890ca9ae
HY		 1674int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1675{
1676 u64 data;
1677
1678 switch (msr) {
890ca9ae 1679 case MSR_IA32_PLATFORM_ID:
15c4a640 1680 case MSR_IA32_UCODE_REV:
15c4a640 1681 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1682 case MSR_IA32_DEBUGCTLMSR:
1683 case MSR_IA32_LASTBRANCHFROMIP:
1684 case MSR_IA32_LASTBRANCHTOIP:
1685 case MSR_IA32_LASTINTFROMIP:
1686 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1687 case MSR_K8_SYSCFG:
1688 case MSR_K7_HWCR:
61a6bd67 1689 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1690 case MSR_P6_PERFCTR0:
1691 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1692 case MSR_P6_EVNTSEL0:
1693 case MSR_P6_EVNTSEL1:
9e699624 1694 case MSR_K7_EVNTSEL0:
1f3ee616 1695 case MSR_K7_PERFCTR0:
1fdbd48c 1696 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1697 case MSR_AMD64_NB_CFG:
f7c6d140 1698 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1699 data = 0;
1700 break;
9ba075a6
AK		 1701 case MSR_MTRRcap:
1702 data = 0x500 | KVM_NR_VAR_MTRR;
1703 break;
1704 case 0x200 ... 0x2ff:
1705 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1706 case 0xcd: /* fsb frequency */
1707 data = 3;
1708 break;
7b914098
JS		 1709 /*
1710 * MSR_EBC_FREQUENCY_ID
1711 * Conservative value valid for even the basic CPU models.
1712 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1713 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1714 * and 266MHz for model 3, or 4. Set Core Clock
1715 * Frequency to System Bus Frequency Ratio to 1 (bits
1716 * 31:24) even though these are only valid for CPU
1717 * models > 2, however guests may end up dividing or
1718 * multiplying by zero otherwise.
1719 */
1720 case MSR_EBC_FREQUENCY_ID:
1721 data = 1 << 24;
1722 break;
15c4a640
CO		 1723 case MSR_IA32_APICBASE:
1724 data = kvm_get_apic_base(vcpu);
1725 break;
0105d1a5
GN		 1726 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1727 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1728 break;
15c4a640 1729 case MSR_IA32_MISC_ENABLE:
ad312c7c 1730 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1731 break;
847f0ad8
AG		 1732 case MSR_IA32_PERF_STATUS:
1733 /* TSC increment by tick */
1734 data = 1000ULL;
1735 /* CPU multiplier */
1736 data |= (((uint64_t)4ULL) << 40);
1737 break;
15c4a640 1738 case MSR_EFER:
f6801dff 1739 data = vcpu->arch.efer;
15c4a640 1740 break;
18068523 1741 case MSR_KVM_WALL_CLOCK:
11c6bffa 1742 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1743 data = vcpu->kvm->arch.wall_clock;
1744 break;
1745 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1746 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1747 data = vcpu->arch.time;
1748 break;
890ca9ae
HY		 1749 case MSR_IA32_P5_MC_ADDR:
1750 case MSR_IA32_P5_MC_TYPE:
1751 case MSR_IA32_MCG_CAP:
1752 case MSR_IA32_MCG_CTL:
1753 case MSR_IA32_MCG_STATUS:
1754 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1755 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1756 case MSR_K7_CLK_CTL:
1757 /*
1758 * Provide expected ramp-up count for K7. All other
1759 * are set to zero, indicating minimum divisors for
1760 * every field.
1761 *
1762 * This prevents guest kernels on AMD host with CPU
1763 * type 6, model 8 and higher from exploding due to
1764 * the rdmsr failing.
1765 */
1766 data = 0x20000000;
1767 break;
55cd8e5a
GN		 1768 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1769 if (kvm_hv_msr_partition_wide(msr)) {
1770 int r;
1771 mutex_lock(&vcpu->kvm->lock);
1772 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1773 mutex_unlock(&vcpu->kvm->lock);
1774 return r;
1775 } else
1776 return get_msr_hyperv(vcpu, msr, pdata);
1777 break;
15c4a640 1778 default:
ed85c068
AP		 1779 if (!ignore_msrs) {
1780 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1781 return 1;
1782 } else {
1783 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1784 data = 0;
1785 }
1786 break;
15c4a640
CO		 1787 }
1788 *pdata = data;
1789 return 0;
1790}
1791EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1792
313a3dc7
CO		 1793/*
1794 * Read or write a bunch of msrs. All parameters are kernel addresses.
1795 *
1796 * @return number of msrs set successfully.
1797 */
1798static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1799 struct kvm_msr_entry *entries,
1800 int (*do_msr)(struct kvm_vcpu *vcpu,
1801 unsigned index, u64 *data))
1802{
f656ce01 1803 int i, idx;
313a3dc7 1804
f656ce01 1805 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1806 for (i = 0; i < msrs->nmsrs; ++i)
1807 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1808 break;
f656ce01 1809 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1810
313a3dc7
CO		 1811 return i;
1812}
1813
1814/*
1815 * Read or write a bunch of msrs. Parameters are user addresses.
1816 *
1817 * @return number of msrs set successfully.
1818 */
1819static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1820 int (*do_msr)(struct kvm_vcpu *vcpu,
1821 unsigned index, u64 *data),
1822 int writeback)
1823{
1824 struct kvm_msrs msrs;
1825 struct kvm_msr_entry *entries;
1826 int r, n;
1827 unsigned size;
1828
1829 r = -EFAULT;
1830 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1831 goto out;
1832
1833 r = -E2BIG;
1834 if (msrs.nmsrs >= MAX_IO_MSRS)
1835 goto out;
1836
1837 r = -ENOMEM;
1838 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1839 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1840 if (!entries)
1841 goto out;
1842
1843 r = -EFAULT;
1844 if (copy_from_user(entries, user_msrs->entries, size))
1845 goto out_free;
1846
1847 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1848 if (r < 0)
1849 goto out_free;
1850
1851 r = -EFAULT;
1852 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1853 goto out_free;
1854
1855 r = n;
1856
1857out_free:
7a73c028 1858 kfree(entries);
313a3dc7
CO		 1859out:
1860 return r;
1861}
1862
018d00d2
ZX		 1863int kvm_dev_ioctl_check_extension(long ext)
1864{
1865 int r;
1866
1867 switch (ext) {
1868 case KVM_CAP_IRQCHIP:
1869 case KVM_CAP_HLT:
1870 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1871 case KVM_CAP_SET_TSS_ADDR:
07716717 1872 case KVM_CAP_EXT_CPUID:
c8076604 1873 case KVM_CAP_CLOCKSOURCE:
7837699f 1874 case KVM_CAP_PIT:
a28e4f5a 1875 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1876 case KVM_CAP_MP_STATE:
ed848624 1877 case KVM_CAP_SYNC_MMU:
52d939a0 1878 case KVM_CAP_REINJECT_CONTROL:
4925663a 1879 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1880 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1881 case KVM_CAP_IRQFD:
d34e6b17 1882 case KVM_CAP_IOEVENTFD:
c5ff41ce 1883 case KVM_CAP_PIT2:
e9f42757 1884 case KVM_CAP_PIT_STATE2:
b927a3ce 1885 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1886 case KVM_CAP_XEN_HVM:
afbcf7ab 1887 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1888 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1889 case KVM_CAP_HYPERV:
10388a07 1890 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1891 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1892 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1893 case KVM_CAP_DEBUGREGS:
d2be1651 1894 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1895 case KVM_CAP_XSAVE:
018d00d2
ZX		 1896 r = 1;
1897 break;
542472b5
LV		 1898 case KVM_CAP_COALESCED_MMIO:
1899 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1900 break;
774ead3a
AK		 1901 case KVM_CAP_VAPIC:
1902 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1903 break;
f725230a
AK		 1904 case KVM_CAP_NR_VCPUS:
1905 r = KVM_MAX_VCPUS;
1906 break;
a988b910
AK		 1907 case KVM_CAP_NR_MEMSLOTS:
1908 r = KVM_MEMORY_SLOTS;
1909 break;
a68a6a72
MT		 1910 case KVM_CAP_PV_MMU: /* obsolete */
1911 r = 0;
2f333bcb 1912 break;
62c476c7 1913 case KVM_CAP_IOMMU:
19de40a8 1914 r = iommu_found();
62c476c7 1915 break;
890ca9ae
HY		 1916 case KVM_CAP_MCE:
1917 r = KVM_MAX_MCE_BANKS;
1918 break;
2d5b5a66
SY		 1919 case KVM_CAP_XCRS:
1920 r = cpu_has_xsave;
1921 break;
018d00d2
ZX		 1922 default:
1923 r = 0;
1924 break;
1925 }
1926 return r;
1927
1928}
1929
043405e1
CO		 1930long kvm_arch_dev_ioctl(struct file *filp,
1931 unsigned int ioctl, unsigned long arg)
1932{
1933 void __user *argp = (void __user *)arg;
1934 long r;
1935
1936 switch (ioctl) {
1937 case KVM_GET_MSR_INDEX_LIST: {
1938 struct kvm_msr_list __user *user_msr_list = argp;
1939 struct kvm_msr_list msr_list;
1940 unsigned n;
1941
1942 r = -EFAULT;
1943 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1944 goto out;
1945 n = msr_list.nmsrs;
1946 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1947 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1948 goto out;
1949 r = -E2BIG;
e125e7b6 1950 if (n < msr_list.nmsrs)
043405e1
CO		 1951 goto out;
1952 r = -EFAULT;
1953 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1954 num_msrs_to_save * sizeof(u32)))
1955 goto out;
e125e7b6 1956 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1957 &emulated_msrs,
1958 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1959 goto out;
1960 r = 0;
1961 break;
1962 }
674eea0f
AK		 1963 case KVM_GET_SUPPORTED_CPUID: {
1964 struct kvm_cpuid2 __user *cpuid_arg = argp;
1965 struct kvm_cpuid2 cpuid;
1966
1967 r = -EFAULT;
1968 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1969 goto out;
1970 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1971 cpuid_arg->entries);
674eea0f
AK		 1972 if (r)
1973 goto out;
1974
1975 r = -EFAULT;
1976 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1977 goto out;
1978 r = 0;
1979 break;
1980 }
890ca9ae
HY		 1981 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1982 u64 mce_cap;
1983
1984 mce_cap = KVM_MCE_CAP_SUPPORTED;
1985 r = -EFAULT;
1986 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1987 goto out;
1988 r = 0;
1989 break;
1990 }
043405e1
CO		 1991 default:
1992 r = -EINVAL;
1993 }
1994out:
1995 return r;
1996}
1997
f5f48ee1
SY		 1998static void wbinvd_ipi(void *garbage)
1999{
2000 wbinvd();
2001}
2002
2003static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2004{
2005 return vcpu->kvm->arch.iommu_domain &&
2006 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2007}
2008
313a3dc7
CO		 2009void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2010{
f5f48ee1
SY		 2011 /* Address WBINVD may be executed by guest */
2012 if (need_emulate_wbinvd(vcpu)) {
2013 if (kvm_x86_ops->has_wbinvd_exit())
2014 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2015 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2016 smp_call_function_single(vcpu->cpu,
2017 wbinvd_ipi, NULL, 1);
2018 }
2019
313a3dc7 2020 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2021 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2022 /* Make sure TSC doesn't go backwards */
2023 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2024 native_read_tsc() - vcpu->arch.last_host_tsc;
2025 if (tsc_delta < 0)
2026 mark_tsc_unstable("KVM discovered backwards TSC");
2027 if (check_tsc_unstable())
2028 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
2029 kvm_migrate_timers(vcpu);
2030 vcpu->cpu = cpu;
2031 }
313a3dc7
CO		 2032}
2033
2034void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2035{
02daab21 2036 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2037 kvm_put_guest_fpu(vcpu);
e48672fa 2038 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2039}
2040
07716717 2041static int is_efer_nx(void)
313a3dc7 2042{
e286e86e 2043 unsigned long long efer = 0;
313a3dc7 2044
e286e86e 2045 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2046 return efer & EFER_NX;
2047}
2048
2049static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2050{
2051 int i;
2052 struct kvm_cpuid_entry2 *e, *entry;
2053
313a3dc7 2054 entry = NULL;
ad312c7c
ZX		 2055 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2056 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2057 if (e->function == 0x80000001) {
2058 entry = e;
2059 break;
2060 }
2061 }
07716717 2062 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2063 entry->edx &= ~(1 << 20);
2064 printk(KERN_INFO "kvm: guest NX capability removed\n");
2065 }
2066}
2067
07716717 2068/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2069static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2070 struct kvm_cpuid *cpuid,
2071 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2072{
2073 int r, i;
2074 struct kvm_cpuid_entry *cpuid_entries;
2075
2076 r = -E2BIG;
2077 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2078 goto out;
2079 r = -ENOMEM;
2080 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2081 if (!cpuid_entries)
2082 goto out;
2083 r = -EFAULT;
2084 if (copy_from_user(cpuid_entries, entries,
2085 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2086 goto out_free;
2087 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2088 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2089 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2090 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2091 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2092 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2093 vcpu->arch.cpuid_entries[i].index = 0;
2094 vcpu->arch.cpuid_entries[i].flags = 0;
2095 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2096 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2097 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2098 }
2099 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2100 cpuid_fix_nx_cap(vcpu);
2101 r = 0;
fc61b800 2102 kvm_apic_set_version(vcpu);
0e851880 2103 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2104 update_cpuid(vcpu);
07716717
DK		 2105
2106out_free:
2107 vfree(cpuid_entries);
2108out:
2109 return r;
2110}
2111
2112static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2113 struct kvm_cpuid2 *cpuid,
2114 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2115{
2116 int r;
2117
2118 r = -E2BIG;
2119 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2120 goto out;
2121 r = -EFAULT;
ad312c7c 2122 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2123 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2124 goto out;
ad312c7c 2125 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2126 kvm_apic_set_version(vcpu);
0e851880 2127 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2128 update_cpuid(vcpu);
313a3dc7
CO		 2129 return 0;
2130
2131out:
2132 return r;
2133}
2134
07716717 2135static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2136 struct kvm_cpuid2 *cpuid,
2137 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2138{
2139 int r;
2140
2141 r = -E2BIG;
ad312c7c 2142 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2143 goto out;
2144 r = -EFAULT;
ad312c7c 2145 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2146 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2147 goto out;
2148 return 0;
2149
2150out:
ad312c7c 2151 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2152 return r;
2153}
2154
07716717 2155static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2156 u32 index)
07716717
DK		 2157{
2158 entry->function = function;
2159 entry->index = index;
2160 cpuid_count(entry->function, entry->index,
19355475 2161 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2162 entry->flags = 0;
2163}
2164
7faa4ee1
AK		 2165#define F(x) bit(X86_FEATURE_##x)
2166
07716717
DK		 2167static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2168 u32 index, int *nent, int maxnent)
2169{
7faa4ee1 2170 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2171#ifdef CONFIG_X86_64
17cc3935
SY		 2172 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2173 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2174 unsigned f_lm = F(LM);
2175#else
17cc3935 2176 unsigned f_gbpages = 0;
7faa4ee1 2177 unsigned f_lm = 0;
07716717 2178#endif
4e47c7a6 2179 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2180
2181 /* cpuid 1.edx */
2182 const u32 kvm_supported_word0_x86_features =
2183 F(FPU) | F(VME) | F(DE) | F(PSE) |
2184 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2185 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2186 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2187 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2188 0 /* Reserved, DS, ACPI */ | F(MMX) |
2189 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2190 0 /* HTT, TM, Reserved, PBE */;
2191 /* cpuid 0x80000001.edx */
2192 const u32 kvm_supported_word1_x86_features =
2193 F(FPU) | F(VME) | F(DE) | F(PSE) |
2194 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2195 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2196 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2197 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2198 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2199 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2200 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2201 /* cpuid 1.ecx */
2202 const u32 kvm_supported_word4_x86_features =
6c3f6041 2203 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2204 0 /* DS-CPL, VMX, SMX, EST */ |
2205 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2206 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2207 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2208 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6c3f6041 2209 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
7faa4ee1 2210 /* cpuid 0x80000001.ecx */
07716717 2211 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 2212 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
2213 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2214 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
2215 0 /* SKINIT */ | 0 /* WDT */;
07716717 2216
19355475 2217 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2218 get_cpu();
2219 do_cpuid_1_ent(entry, function, index);
2220 ++*nent;
2221
2222 switch (function) {
2223 case 0:
2acf923e 2224 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2225 break;
2226 case 1:
2227 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2228 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2229 /* we support x2apic emulation even if host does not support
2230 * it since we emulate x2apic in software */
2231 entry->ecx |= F(X2APIC);
07716717
DK		 2232 break;
2233 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2234 * may return different values. This forces us to get_cpu() before
2235 * issuing the first command, and also to emulate this annoying behavior
2236 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2237 case 2: {
2238 int t, times = entry->eax & 0xff;
2239
2240 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2241 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2242 for (t = 1; t < times && *nent < maxnent; ++t) {
2243 do_cpuid_1_ent(&entry[t], function, 0);
2244 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2245 ++*nent;
2246 }
2247 break;
2248 }
2249 /* function 4 and 0xb have additional index. */
2250 case 4: {
14af3f3c 2251 int i, cache_type;
07716717
DK		 2252
2253 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2254 /* read more entries until cache_type is zero */
14af3f3c
HH		 2255 for (i = 1; *nent < maxnent; ++i) {
2256 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2257 if (!cache_type)
2258 break;
14af3f3c
HH		 2259 do_cpuid_1_ent(&entry[i], function, i);
2260 entry[i].flags |=
07716717
DK		 2261 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2262 ++*nent;
2263 }
2264 break;
2265 }
2266 case 0xb: {
14af3f3c 2267 int i, level_type;
07716717
DK		 2268
2269 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2270 /* read more entries until level_type is zero */
14af3f3c 2271 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2272 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2273 if (!level_type)
2274 break;
14af3f3c
HH		 2275 do_cpuid_1_ent(&entry[i], function, i);
2276 entry[i].flags |=
07716717
DK		 2277 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2278 ++*nent;
2279 }
2280 break;
2281 }
2acf923e
DC		 2282 case 0xd: {
2283 int i;
2284
2285 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2286 for (i = 1; *nent < maxnent; ++i) {
2287 if (entry[i - 1].eax == 0 && i != 2)
2288 break;
2289 do_cpuid_1_ent(&entry[i], function, i);
2290 entry[i].flags |=
2291 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2292 ++*nent;
2293 }
2294 break;
2295 }
84478c82
GC		 2296 case KVM_CPUID_SIGNATURE: {
2297 char signature[12] = "KVMKVMKVM\0\0";
2298 u32 *sigptr = (u32 *)signature;
2299 entry->eax = 0;
2300 entry->ebx = sigptr[0];
2301 entry->ecx = sigptr[1];
2302 entry->edx = sigptr[2];
2303 break;
2304 }
2305 case KVM_CPUID_FEATURES:
2306 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2307 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2308 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2309 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2310 entry->ebx = 0;
2311 entry->ecx = 0;
2312 entry->edx = 0;
2313 break;
07716717
DK		 2314 case 0x80000000:
2315 entry->eax = min(entry->eax, 0x8000001a);
2316 break;
2317 case 0x80000001:
2318 entry->edx &= kvm_supported_word1_x86_features;
2319 entry->ecx &= kvm_supported_word6_x86_features;
2320 break;
2321 }
d4330ef2
JR		 2322
2323 kvm_x86_ops->set_supported_cpuid(function, entry);
2324
07716717
DK		 2325 put_cpu();
2326}
2327
7faa4ee1
AK		 2328#undef F
2329
674eea0f 2330static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2331 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2332{
2333 struct kvm_cpuid_entry2 *cpuid_entries;
2334 int limit, nent = 0, r = -E2BIG;
2335 u32 func;
2336
2337 if (cpuid->nent < 1)
2338 goto out;
6a544355
AK		 2339 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2340 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2341 r = -ENOMEM;
2342 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2343 if (!cpuid_entries)
2344 goto out;
2345
2346 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2347 limit = cpuid_entries[0].eax;
2348 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2349 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2350 &nent, cpuid->nent);
07716717
DK		 2351 r = -E2BIG;
2352 if (nent >= cpuid->nent)
2353 goto out_free;
2354
2355 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2356 limit = cpuid_entries[nent - 1].eax;
2357 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2358 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2359 &nent, cpuid->nent);
84478c82
GC		 2360
2361
2362
2363 r = -E2BIG;
2364 if (nent >= cpuid->nent)
2365 goto out_free;
2366
2367 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2368 cpuid->nent);
2369
2370 r = -E2BIG;
2371 if (nent >= cpuid->nent)
2372 goto out_free;
2373
2374 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2375 cpuid->nent);
2376
cb007648
MM		 2377 r = -E2BIG;
2378 if (nent >= cpuid->nent)
2379 goto out_free;
2380
07716717
DK		 2381 r = -EFAULT;
2382 if (copy_to_user(entries, cpuid_entries,
19355475 2383 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2384 goto out_free;
2385 cpuid->nent = nent;
2386 r = 0;
2387
2388out_free:
2389 vfree(cpuid_entries);
2390out:
2391 return r;
2392}
2393
313a3dc7
CO		 2394static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2395 struct kvm_lapic_state *s)
2396{
ad312c7c 2397 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2398
2399 return 0;
2400}
2401
2402static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2403 struct kvm_lapic_state *s)
2404{
ad312c7c 2405 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2406 kvm_apic_post_state_restore(vcpu);
cb142eb7 2407 update_cr8_intercept(vcpu);
313a3dc7
CO		 2408
2409 return 0;
2410}
2411
f77bc6a4
ZX		 2412static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2413 struct kvm_interrupt *irq)
2414{
2415 if (irq->irq < 0 || irq->irq >= 256)
2416 return -EINVAL;
2417 if (irqchip_in_kernel(vcpu->kvm))
2418 return -ENXIO;
f77bc6a4 2419
66fd3f7f 2420 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4 2421
f77bc6a4
ZX		 2422 return 0;
2423}
2424
c4abb7c9
JK		 2425static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2426{
c4abb7c9 2427 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2428
2429 return 0;
2430}
2431
b209749f
AK		 2432static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2433 struct kvm_tpr_access_ctl *tac)
2434{
2435 if (tac->flags)
2436 return -EINVAL;
2437 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2438 return 0;
2439}
2440
890ca9ae
HY		 2441static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2442 u64 mcg_cap)
2443{
2444 int r;
2445 unsigned bank_num = mcg_cap & 0xff, bank;
2446
2447 r = -EINVAL;
a9e38c3e 2448 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2449 goto out;
2450 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2451 goto out;
2452 r = 0;
2453 vcpu->arch.mcg_cap = mcg_cap;
2454 /* Init IA32_MCG_CTL to all 1s */
2455 if (mcg_cap & MCG_CTL_P)
2456 vcpu->arch.mcg_ctl = ~(u64)0;
2457 /* Init IA32_MCi_CTL to all 1s */
2458 for (bank = 0; bank < bank_num; bank++)
2459 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2460out:
2461 return r;
2462}
2463
2464static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2465 struct kvm_x86_mce *mce)
2466{
2467 u64 mcg_cap = vcpu->arch.mcg_cap;
2468 unsigned bank_num = mcg_cap & 0xff;
2469 u64 *banks = vcpu->arch.mce_banks;
2470
2471 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2472 return -EINVAL;
2473 /*
2474 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2475 * reporting is disabled
2476 */
2477 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2478 vcpu->arch.mcg_ctl != ~(u64)0)
2479 return 0;
2480 banks += 4 * mce->bank;
2481 /*
2482 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2483 * reporting is disabled for the bank
2484 */
2485 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2486 return 0;
2487 if (mce->status & MCI_STATUS_UC) {
2488 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2489 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2490 printk(KERN_DEBUG "kvm: set_mce: "
2491 "injects mce exception while "
2492 "previous one is in progress!\n");
a8eeb04a 2493 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2494 return 0;
2495 }
2496 if (banks[1] & MCI_STATUS_VAL)
2497 mce->status |= MCI_STATUS_OVER;
2498 banks[2] = mce->addr;
2499 banks[3] = mce->misc;
2500 vcpu->arch.mcg_status = mce->mcg_status;
2501 banks[1] = mce->status;
2502 kvm_queue_exception(vcpu, MC_VECTOR);
2503 } else if (!(banks[1] & MCI_STATUS_VAL)
2504 || !(banks[1] & MCI_STATUS_UC)) {
2505 if (banks[1] & MCI_STATUS_VAL)
2506 mce->status |= MCI_STATUS_OVER;
2507 banks[2] = mce->addr;
2508 banks[3] = mce->misc;
2509 banks[1] = mce->status;
2510 } else
2511 banks[1] |= MCI_STATUS_OVER;
2512 return 0;
2513}
2514
3cfc3092
JK		 2515static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2516 struct kvm_vcpu_events *events)
2517{
03b82a30
JK		 2518 events->exception.injected =
2519 vcpu->arch.exception.pending &&
2520 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2521 events->exception.nr = vcpu->arch.exception.nr;
2522 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2523 events->exception.error_code = vcpu->arch.exception.error_code;
2524
03b82a30
JK		 2525 events->interrupt.injected =
2526 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2527 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2528 events->interrupt.soft = 0;
48005f64
JK		 2529 events->interrupt.shadow =
2530 kvm_x86_ops->get_interrupt_shadow(vcpu,
2531 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2532
2533 events->nmi.injected = vcpu->arch.nmi_injected;
2534 events->nmi.pending = vcpu->arch.nmi_pending;
2535 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2536
2537 events->sipi_vector = vcpu->arch.sipi_vector;
2538
dab4b911 2539 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2540 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2541 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2542}
2543
2544static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2545 struct kvm_vcpu_events *events)
2546{
dab4b911 2547 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2548 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2549 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2550 return -EINVAL;
2551
3cfc3092
JK		 2552 vcpu->arch.exception.pending = events->exception.injected;
2553 vcpu->arch.exception.nr = events->exception.nr;
2554 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2555 vcpu->arch.exception.error_code = events->exception.error_code;
2556
2557 vcpu->arch.interrupt.pending = events->interrupt.injected;
2558 vcpu->arch.interrupt.nr = events->interrupt.nr;
2559 vcpu->arch.interrupt.soft = events->interrupt.soft;
2560 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2561 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2562 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2563 kvm_x86_ops->set_interrupt_shadow(vcpu,
2564 events->interrupt.shadow);
3cfc3092
JK		 2565
2566 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2567 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2568 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2569 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2570
dab4b911
JK		 2571 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2572 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2573
3cfc3092
JK		 2574 return 0;
2575}
2576
a1efbe77
JK		 2577static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2578 struct kvm_debugregs *dbgregs)
2579{
a1efbe77
JK		 2580 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2581 dbgregs->dr6 = vcpu->arch.dr6;
2582 dbgregs->dr7 = vcpu->arch.dr7;
2583 dbgregs->flags = 0;
a1efbe77
JK		 2584}
2585
2586static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2587 struct kvm_debugregs *dbgregs)
2588{
2589 if (dbgregs->flags)
2590 return -EINVAL;
2591
a1efbe77
JK		 2592 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2593 vcpu->arch.dr6 = dbgregs->dr6;
2594 vcpu->arch.dr7 = dbgregs->dr7;
2595
a1efbe77
JK		 2596 return 0;
2597}
2598
2d5b5a66
SY		 2599static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2600 struct kvm_xsave *guest_xsave)
2601{
2602 if (cpu_has_xsave)
2603 memcpy(guest_xsave->region,
2604 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2605 xstate_size);
2d5b5a66
SY		 2606 else {
2607 memcpy(guest_xsave->region,
2608 &vcpu->arch.guest_fpu.state->fxsave,
2609 sizeof(struct i387_fxsave_struct));
2610 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2611 XSTATE_FPSSE;
2612 }
2613}
2614
2615static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2616 struct kvm_xsave *guest_xsave)
2617{
2618 u64 xstate_bv =
2619 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2620
2621 if (cpu_has_xsave)
2622 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2623 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2624 else {
2625 if (xstate_bv & ~XSTATE_FPSSE)
2626 return -EINVAL;
2627 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2628 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2629 }
2630 return 0;
2631}
2632
2633static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2634 struct kvm_xcrs *guest_xcrs)
2635{
2636 if (!cpu_has_xsave) {
2637 guest_xcrs->nr_xcrs = 0;
2638 return;
2639 }
2640
2641 guest_xcrs->nr_xcrs = 1;
2642 guest_xcrs->flags = 0;
2643 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2644 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2645}
2646
2647static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2648 struct kvm_xcrs *guest_xcrs)
2649{
2650 int i, r = 0;
2651
2652 if (!cpu_has_xsave)
2653 return -EINVAL;
2654
2655 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2656 return -EINVAL;
2657
2658 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2659 /* Only support XCR0 currently */
2660 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2661 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2662 guest_xcrs->xcrs[0].value);
2663 break;
2664 }
2665 if (r)
2666 r = -EINVAL;
2667 return r;
2668}
2669
313a3dc7
CO		 2670long kvm_arch_vcpu_ioctl(struct file *filp,
2671 unsigned int ioctl, unsigned long arg)
2672{
2673 struct kvm_vcpu *vcpu = filp->private_data;
2674 void __user *argp = (void __user *)arg;
2675 int r;
d1ac91d8
AK		 2676 union {
2677 struct kvm_lapic_state *lapic;
2678 struct kvm_xsave *xsave;
2679 struct kvm_xcrs *xcrs;
2680 void *buffer;
2681 } u;
2682
2683 u.buffer = NULL;
313a3dc7
CO		 2684 switch (ioctl) {
2685 case KVM_GET_LAPIC: {
2204ae3c
MT		 2686 r = -EINVAL;
2687 if (!vcpu->arch.apic)
2688 goto out;
d1ac91d8 2689 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2690
b772ff36 2691 r = -ENOMEM;
d1ac91d8 2692 if (!u.lapic)
b772ff36 2693 goto out;
d1ac91d8 2694 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2695 if (r)
2696 goto out;
2697 r = -EFAULT;
d1ac91d8 2698 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2699 goto out;
2700 r = 0;
2701 break;
2702 }
2703 case KVM_SET_LAPIC: {
2204ae3c
MT		 2704 r = -EINVAL;
2705 if (!vcpu->arch.apic)
2706 goto out;
d1ac91d8 2707 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2708 r = -ENOMEM;
d1ac91d8 2709 if (!u.lapic)
b772ff36 2710 goto out;
313a3dc7 2711 r = -EFAULT;
d1ac91d8 2712 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2713 goto out;
d1ac91d8 2714 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2715 if (r)
2716 goto out;
2717 r = 0;
2718 break;
2719 }
f77bc6a4
ZX		 2720 case KVM_INTERRUPT: {
2721 struct kvm_interrupt irq;
2722
2723 r = -EFAULT;
2724 if (copy_from_user(&irq, argp, sizeof irq))
2725 goto out;
2726 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2727 if (r)
2728 goto out;
2729 r = 0;
2730 break;
2731 }
c4abb7c9
JK		 2732 case KVM_NMI: {
2733 r = kvm_vcpu_ioctl_nmi(vcpu);
2734 if (r)
2735 goto out;
2736 r = 0;
2737 break;
2738 }
313a3dc7
CO		 2739 case KVM_SET_CPUID: {
2740 struct kvm_cpuid __user *cpuid_arg = argp;
2741 struct kvm_cpuid cpuid;
2742
2743 r = -EFAULT;
2744 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2745 goto out;
2746 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2747 if (r)
2748 goto out;
2749 break;
2750 }
07716717
DK		 2751 case KVM_SET_CPUID2: {
2752 struct kvm_cpuid2 __user *cpuid_arg = argp;
2753 struct kvm_cpuid2 cpuid;
2754
2755 r = -EFAULT;
2756 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2757 goto out;
2758 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2759 cpuid_arg->entries);
07716717
DK		 2760 if (r)
2761 goto out;
2762 break;
2763 }
2764 case KVM_GET_CPUID2: {
2765 struct kvm_cpuid2 __user *cpuid_arg = argp;
2766 struct kvm_cpuid2 cpuid;
2767
2768 r = -EFAULT;
2769 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2770 goto out;
2771 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2772 cpuid_arg->entries);
07716717
DK		 2773 if (r)
2774 goto out;
2775 r = -EFAULT;
2776 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2777 goto out;
2778 r = 0;
2779 break;
2780 }
313a3dc7
CO		 2781 case KVM_GET_MSRS:
2782 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2783 break;
2784 case KVM_SET_MSRS:
2785 r = msr_io(vcpu, argp, do_set_msr, 0);
2786 break;
b209749f
AK		 2787 case KVM_TPR_ACCESS_REPORTING: {
2788 struct kvm_tpr_access_ctl tac;
2789
2790 r = -EFAULT;
2791 if (copy_from_user(&tac, argp, sizeof tac))
2792 goto out;
2793 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2794 if (r)
2795 goto out;
2796 r = -EFAULT;
2797 if (copy_to_user(argp, &tac, sizeof tac))
2798 goto out;
2799 r = 0;
2800 break;
2801 };
b93463aa
AK		 2802 case KVM_SET_VAPIC_ADDR: {
2803 struct kvm_vapic_addr va;
2804
2805 r = -EINVAL;
2806 if (!irqchip_in_kernel(vcpu->kvm))
2807 goto out;
2808 r = -EFAULT;
2809 if (copy_from_user(&va, argp, sizeof va))
2810 goto out;
2811 r = 0;
2812 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2813 break;
2814 }
890ca9ae
HY		 2815 case KVM_X86_SETUP_MCE: {
2816 u64 mcg_cap;
2817
2818 r = -EFAULT;
2819 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2820 goto out;
2821 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2822 break;
2823 }
2824 case KVM_X86_SET_MCE: {
2825 struct kvm_x86_mce mce;
2826
2827 r = -EFAULT;
2828 if (copy_from_user(&mce, argp, sizeof mce))
2829 goto out;
2830 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2831 break;
2832 }
3cfc3092
JK		 2833 case KVM_GET_VCPU_EVENTS: {
2834 struct kvm_vcpu_events events;
2835
2836 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2837
2838 r = -EFAULT;
2839 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2840 break;
2841 r = 0;
2842 break;
2843 }
2844 case KVM_SET_VCPU_EVENTS: {
2845 struct kvm_vcpu_events events;
2846
2847 r = -EFAULT;
2848 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2849 break;
2850
2851 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2852 break;
2853 }
a1efbe77
JK		 2854 case KVM_GET_DEBUGREGS: {
2855 struct kvm_debugregs dbgregs;
2856
2857 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2858
2859 r = -EFAULT;
2860 if (copy_to_user(argp, &dbgregs,
2861 sizeof(struct kvm_debugregs)))
2862 break;
2863 r = 0;
2864 break;
2865 }
2866 case KVM_SET_DEBUGREGS: {
2867 struct kvm_debugregs dbgregs;
2868
2869 r = -EFAULT;
2870 if (copy_from_user(&dbgregs, argp,
2871 sizeof(struct kvm_debugregs)))
2872 break;
2873
2874 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2875 break;
2876 }
2d5b5a66 2877 case KVM_GET_XSAVE: {
d1ac91d8 2878 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2879 r = -ENOMEM;
d1ac91d8 2880 if (!u.xsave)
2d5b5a66
SY		 2881 break;
2882
d1ac91d8 2883 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2884
2885 r = -EFAULT;
d1ac91d8 2886 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2887 break;
2888 r = 0;
2889 break;
2890 }
2891 case KVM_SET_XSAVE: {
d1ac91d8 2892 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2893 r = -ENOMEM;
d1ac91d8 2894 if (!u.xsave)
2d5b5a66
SY		 2895 break;
2896
2897 r = -EFAULT;
d1ac91d8 2898 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2899 break;
2900
d1ac91d8 2901 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2902 break;
2903 }
2904 case KVM_GET_XCRS: {
d1ac91d8 2905 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2906 r = -ENOMEM;
d1ac91d8 2907 if (!u.xcrs)
2d5b5a66
SY		 2908 break;
2909
d1ac91d8 2910 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2911
2912 r = -EFAULT;
d1ac91d8 2913 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2914 sizeof(struct kvm_xcrs)))
2915 break;
2916 r = 0;
2917 break;
2918 }
2919 case KVM_SET_XCRS: {
d1ac91d8 2920 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2921 r = -ENOMEM;
d1ac91d8 2922 if (!u.xcrs)
2d5b5a66
SY		 2923 break;
2924
2925 r = -EFAULT;
d1ac91d8 2926 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2927 sizeof(struct kvm_xcrs)))
2928 break;
2929
d1ac91d8 2930 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2931 break;
2932 }
313a3dc7
CO		 2933 default:
2934 r = -EINVAL;
2935 }
2936out:
d1ac91d8 2937 kfree(u.buffer);
313a3dc7
CO		 2938 return r;
2939}
2940
1fe779f8
CO		 2941static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2942{
2943 int ret;
2944
2945 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2946 return -1;
2947 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2948 return ret;
2949}
2950
b927a3ce
SY		 2951static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2952 u64 ident_addr)
2953{
2954 kvm->arch.ept_identity_map_addr = ident_addr;
2955 return 0;
2956}
2957
1fe779f8
CO		 2958static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2959 u32 kvm_nr_mmu_pages)
2960{
2961 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2962 return -EINVAL;
2963
79fac95e 2964 mutex_lock(&kvm->slots_lock);
7c8a83b7 2965 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2966
2967 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2968 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2969
7c8a83b7 2970 spin_unlock(&kvm->mmu_lock);
79fac95e 2971 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2972 return 0;
2973}
2974
2975static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2976{
39de71ec 2977 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2978}
2979
1fe779f8
CO		 2980static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2981{
2982 int r;
2983
2984 r = 0;
2985 switch (chip->chip_id) {
2986 case KVM_IRQCHIP_PIC_MASTER:
2987 memcpy(&chip->chip.pic,
2988 &pic_irqchip(kvm)->pics[0],
2989 sizeof(struct kvm_pic_state));
2990 break;
2991 case KVM_IRQCHIP_PIC_SLAVE:
2992 memcpy(&chip->chip.pic,
2993 &pic_irqchip(kvm)->pics[1],
2994 sizeof(struct kvm_pic_state));
2995 break;
2996 case KVM_IRQCHIP_IOAPIC:
eba0226b 2997 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2998 break;
2999 default:
3000 r = -EINVAL;
3001 break;
3002 }
3003 return r;
3004}
3005
3006static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3007{
3008 int r;
3009
3010 r = 0;
3011 switch (chip->chip_id) {
3012 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 3013 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3014 memcpy(&pic_irqchip(kvm)->pics[0],
3015 &chip->chip.pic,
3016 sizeof(struct kvm_pic_state));
fa8273e9 3017 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3018 break;
3019 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 3020 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3021 memcpy(&pic_irqchip(kvm)->pics[1],
3022 &chip->chip.pic,
3023 sizeof(struct kvm_pic_state));
fa8273e9 3024 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3025 break;
3026 case KVM_IRQCHIP_IOAPIC:
eba0226b 3027 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3028 break;
3029 default:
3030 r = -EINVAL;
3031 break;
3032 }
3033 kvm_pic_update_irq(pic_irqchip(kvm));
3034 return r;
3035}
3036
e0f63cb9
SY		 3037static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3038{
3039 int r = 0;
3040
894a9c55 3041 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3042 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3043 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3044 return r;
3045}
3046
3047static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3048{
3049 int r = 0;
3050
894a9c55 3051 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3052 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3053 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3054 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3055 return r;
3056}
3057
3058static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3059{
3060 int r = 0;
3061
3062 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3063 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3064 sizeof(ps->channels));
3065 ps->flags = kvm->arch.vpit->pit_state.flags;
3066 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3067 return r;
3068}
3069
3070static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3071{
3072 int r = 0, start = 0;
3073 u32 prev_legacy, cur_legacy;
3074 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3075 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3076 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3077 if (!prev_legacy && cur_legacy)
3078 start = 1;
3079 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3080 sizeof(kvm->arch.vpit->pit_state.channels));
3081 kvm->arch.vpit->pit_state.flags = ps->flags;
3082 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3083 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3084 return r;
3085}
3086
52d939a0
MT		 3087static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3088 struct kvm_reinject_control *control)
3089{
3090 if (!kvm->arch.vpit)
3091 return -ENXIO;
894a9c55 3092 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3093 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3094 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3095 return 0;
3096}
3097
5bb064dc
ZX		 3098/*
3099 * Get (and clear) the dirty memory log for a memory slot.
3100 */
3101int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3102 struct kvm_dirty_log *log)
3103{
87bf6e7d 3104 int r, i;
5bb064dc 3105 struct kvm_memory_slot *memslot;
87bf6e7d 3106 unsigned long n;
b050b015 3107 unsigned long is_dirty = 0;
5bb064dc 3108
79fac95e 3109 mutex_lock(&kvm->slots_lock);
5bb064dc 3110
b050b015
MT		 3111 r = -EINVAL;
3112 if (log->slot >= KVM_MEMORY_SLOTS)
3113 goto out;
3114
3115 memslot = &kvm->memslots->memslots[log->slot];
3116 r = -ENOENT;
3117 if (!memslot->dirty_bitmap)
3118 goto out;
3119
87bf6e7d 3120 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3121
b050b015
MT		 3122 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3123 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3124
3125 /* If nothing is dirty, don't bother messing with page tables. */
3126 if (is_dirty) {
b050b015 3127 struct kvm_memslots *slots, *old_slots;
914ebccd 3128 unsigned long *dirty_bitmap;
b050b015 3129
7c8a83b7 3130 spin_lock(&kvm->mmu_lock);
5bb064dc 3131 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 3132 spin_unlock(&kvm->mmu_lock);
b050b015 3133
914ebccd
TY		 3134 r = -ENOMEM;
3135 dirty_bitmap = vmalloc(n);
3136 if (!dirty_bitmap)
3137 goto out;
3138 memset(dirty_bitmap, 0, n);
b050b015 3139
914ebccd
TY		 3140 r = -ENOMEM;
3141 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3142 if (!slots) {
3143 vfree(dirty_bitmap);
3144 goto out;
3145 }
b050b015
MT		 3146 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3147 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3148
3149 old_slots = kvm->memslots;
3150 rcu_assign_pointer(kvm->memslots, slots);
3151 synchronize_srcu_expedited(&kvm->srcu);
3152 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3153 kfree(old_slots);
914ebccd
TY		 3154
3155 r = -EFAULT;
3156 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3157 vfree(dirty_bitmap);
3158 goto out;
3159 }
3160 vfree(dirty_bitmap);
3161 } else {
3162 r = -EFAULT;
3163 if (clear_user(log->dirty_bitmap, n))
3164 goto out;
5bb064dc 3165 }
b050b015 3166
5bb064dc
ZX		 3167 r = 0;
3168out:
79fac95e 3169 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3170 return r;
3171}
3172
1fe779f8
CO		 3173long kvm_arch_vm_ioctl(struct file *filp,
3174 unsigned int ioctl, unsigned long arg)
3175{
3176 struct kvm *kvm = filp->private_data;
3177 void __user *argp = (void __user *)arg;
367e1319 3178 int r = -ENOTTY;
f0d66275
DH		 3179 /*
3180 * This union makes it completely explicit to gcc-3.x
3181 * that these two variables' stack usage should be
3182 * combined, not added together.
3183 */
3184 union {
3185 struct kvm_pit_state ps;
e9f42757 3186 struct kvm_pit_state2 ps2;
c5ff41ce 3187 struct kvm_pit_config pit_config;
f0d66275 3188 } u;
1fe779f8
CO		 3189
3190 switch (ioctl) {
3191 case KVM_SET_TSS_ADDR:
3192 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3193 if (r < 0)
3194 goto out;
3195 break;
b927a3ce
SY		 3196 case KVM_SET_IDENTITY_MAP_ADDR: {
3197 u64 ident_addr;
3198
3199 r = -EFAULT;
3200 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3201 goto out;
3202 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3203 if (r < 0)
3204 goto out;
3205 break;
3206 }
1fe779f8
CO		 3207 case KVM_SET_NR_MMU_PAGES:
3208 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3209 if (r)
3210 goto out;
3211 break;
3212 case KVM_GET_NR_MMU_PAGES:
3213 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3214 break;
3ddea128
MT		 3215 case KVM_CREATE_IRQCHIP: {
3216 struct kvm_pic *vpic;
3217
3218 mutex_lock(&kvm->lock);
3219 r = -EEXIST;
3220 if (kvm->arch.vpic)
3221 goto create_irqchip_unlock;
1fe779f8 3222 r = -ENOMEM;
3ddea128
MT		 3223 vpic = kvm_create_pic(kvm);
3224 if (vpic) {
1fe779f8
CO		 3225 r = kvm_ioapic_init(kvm);
3226 if (r) {
72bb2fcd
WY		 3227 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3228 &vpic->dev);
3ddea128
MT		 3229 kfree(vpic);
3230 goto create_irqchip_unlock;
1fe779f8
CO		 3231 }
3232 } else
3ddea128
MT		 3233 goto create_irqchip_unlock;
3234 smp_wmb();
3235 kvm->arch.vpic = vpic;
3236 smp_wmb();
399ec807
AK		 3237 r = kvm_setup_default_irq_routing(kvm);
3238 if (r) {
3ddea128 3239 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3240 kvm_ioapic_destroy(kvm);
3241 kvm_destroy_pic(kvm);
3ddea128 3242 mutex_unlock(&kvm->irq_lock);
399ec807 3243 }
3ddea128
MT		 3244 create_irqchip_unlock:
3245 mutex_unlock(&kvm->lock);
1fe779f8 3246 break;
3ddea128 3247 }
7837699f 3248 case KVM_CREATE_PIT:
c5ff41ce
JK		 3249 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3250 goto create_pit;
3251 case KVM_CREATE_PIT2:
3252 r = -EFAULT;
3253 if (copy_from_user(&u.pit_config, argp,
3254 sizeof(struct kvm_pit_config)))
3255 goto out;
3256 create_pit:
79fac95e 3257 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3258 r = -EEXIST;
3259 if (kvm->arch.vpit)
3260 goto create_pit_unlock;
7837699f 3261 r = -ENOMEM;
c5ff41ce 3262 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3263 if (kvm->arch.vpit)
3264 r = 0;
269e05e4 3265 create_pit_unlock:
79fac95e 3266 mutex_unlock(&kvm->slots_lock);
7837699f 3267 break;
4925663a 3268 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3269 case KVM_IRQ_LINE: {
3270 struct kvm_irq_level irq_event;
3271
3272 r = -EFAULT;
3273 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3274 goto out;
160d2f6c 3275 r = -ENXIO;
1fe779f8 3276 if (irqchip_in_kernel(kvm)) {
4925663a 3277 __s32 status;
4925663a
GN		 3278 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3279 irq_event.irq, irq_event.level);
4925663a 3280 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3281 r = -EFAULT;
4925663a
GN		 3282 irq_event.status = status;
3283 if (copy_to_user(argp, &irq_event,
3284 sizeof irq_event))
3285 goto out;
3286 }
1fe779f8
CO		 3287 r = 0;
3288 }
3289 break;
3290 }
3291 case KVM_GET_IRQCHIP: {
3292 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3293 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3294
f0d66275
DH		 3295 r = -ENOMEM;
3296 if (!chip)
1fe779f8 3297 goto out;
f0d66275
DH		 3298 r = -EFAULT;
3299 if (copy_from_user(chip, argp, sizeof *chip))
3300 goto get_irqchip_out;
1fe779f8
CO		 3301 r = -ENXIO;
3302 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3303 goto get_irqchip_out;
3304 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3305 if (r)
f0d66275 3306 goto get_irqchip_out;
1fe779f8 3307 r = -EFAULT;
f0d66275
DH		 3308 if (copy_to_user(argp, chip, sizeof *chip))
3309 goto get_irqchip_out;
1fe779f8 3310 r = 0;
f0d66275
DH		 3311 get_irqchip_out:
3312 kfree(chip);
3313 if (r)
3314 goto out;
1fe779f8
CO		 3315 break;
3316 }
3317 case KVM_SET_IRQCHIP: {
3318 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3319 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3320
f0d66275
DH		 3321 r = -ENOMEM;
3322 if (!chip)
1fe779f8 3323 goto out;
f0d66275
DH		 3324 r = -EFAULT;
3325 if (copy_from_user(chip, argp, sizeof *chip))
3326 goto set_irqchip_out;
1fe779f8
CO		 3327 r = -ENXIO;
3328 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3329 goto set_irqchip_out;
3330 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3331 if (r)
f0d66275 3332 goto set_irqchip_out;
1fe779f8 3333 r = 0;
f0d66275
DH		 3334 set_irqchip_out:
3335 kfree(chip);
3336 if (r)
3337 goto out;
1fe779f8
CO		 3338 break;
3339 }
e0f63cb9 3340 case KVM_GET_PIT: {
e0f63cb9 3341 r = -EFAULT;
f0d66275 3342 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3343 goto out;
3344 r = -ENXIO;
3345 if (!kvm->arch.vpit)
3346 goto out;
f0d66275 3347 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3348 if (r)
3349 goto out;
3350 r = -EFAULT;
f0d66275 3351 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3352 goto out;
3353 r = 0;
3354 break;
3355 }
3356 case KVM_SET_PIT: {
e0f63cb9 3357 r = -EFAULT;
f0d66275 3358 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3359 goto out;
3360 r = -ENXIO;
3361 if (!kvm->arch.vpit)
3362 goto out;
f0d66275 3363 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3364 if (r)
3365 goto out;
3366 r = 0;
3367 break;
3368 }
e9f42757
BK		 3369 case KVM_GET_PIT2: {
3370 r = -ENXIO;
3371 if (!kvm->arch.vpit)
3372 goto out;
3373 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3374 if (r)
3375 goto out;
3376 r = -EFAULT;
3377 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3378 goto out;
3379 r = 0;
3380 break;
3381 }
3382 case KVM_SET_PIT2: {
3383 r = -EFAULT;
3384 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3385 goto out;
3386 r = -ENXIO;
3387 if (!kvm->arch.vpit)
3388 goto out;
3389 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3390 if (r)
3391 goto out;
3392 r = 0;
3393 break;
3394 }
52d939a0
MT		 3395 case KVM_REINJECT_CONTROL: {
3396 struct kvm_reinject_control control;
3397 r = -EFAULT;
3398 if (copy_from_user(&control, argp, sizeof(control)))
3399 goto out;
3400 r = kvm_vm_ioctl_reinject(kvm, &control);
3401 if (r)
3402 goto out;
3403 r = 0;
3404 break;
3405 }
ffde22ac
ES		 3406 case KVM_XEN_HVM_CONFIG: {
3407 r = -EFAULT;
3408 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3409 sizeof(struct kvm_xen_hvm_config)))
3410 goto out;
3411 r = -EINVAL;
3412 if (kvm->arch.xen_hvm_config.flags)
3413 goto out;
3414 r = 0;
3415 break;
3416 }
afbcf7ab 3417 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3418 struct kvm_clock_data user_ns;
3419 u64 now_ns;
3420 s64 delta;
3421
3422 r = -EFAULT;
3423 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3424 goto out;
3425
3426 r = -EINVAL;
3427 if (user_ns.flags)
3428 goto out;
3429
3430 r = 0;
759379dd 3431 now_ns = get_kernel_ns();
afbcf7ab
GC		 3432 delta = user_ns.clock - now_ns;
3433 kvm->arch.kvmclock_offset = delta;
3434 break;
3435 }
3436 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3437 struct kvm_clock_data user_ns;
3438 u64 now_ns;
3439
759379dd 3440 now_ns = get_kernel_ns();
afbcf7ab
GC		 3441 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3442 user_ns.flags = 0;
3443
3444 r = -EFAULT;
3445 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3446 goto out;
3447 r = 0;
3448 break;
3449 }
3450
1fe779f8
CO		 3451 default:
3452 ;
3453 }
3454out:
3455 return r;
3456}
3457
a16b043c 3458static void kvm_init_msr_list(void)
043405e1
CO		 3459{
3460 u32 dummy[2];
3461 unsigned i, j;
3462
e3267cbb
GC		 3463 /* skip the first msrs in the list. KVM-specific */
3464 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3465 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3466 continue;
3467 if (j < i)
3468 msrs_to_save[j] = msrs_to_save[i];
3469 j++;
3470 }
3471 num_msrs_to_save = j;
3472}
3473
bda9020e
MT		 3474static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3475 const void *v)
bbd9b64e 3476{
bda9020e
MT		 3477 if (vcpu->arch.apic &&
3478 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3479 return 0;
bbd9b64e 3480
e93f8a0f 3481 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3482}
3483
bda9020e 3484static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3485{
bda9020e
MT		 3486 if (vcpu->arch.apic &&
3487 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3488 return 0;
bbd9b64e 3489
e93f8a0f 3490 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3491}
3492
2dafc6c2
GN		 3493static void kvm_set_segment(struct kvm_vcpu *vcpu,
3494 struct kvm_segment *var, int seg)
3495{
3496 kvm_x86_ops->set_segment(vcpu, var, seg);
3497}
3498
3499void kvm_get_segment(struct kvm_vcpu *vcpu,
3500 struct kvm_segment *var, int seg)
3501{
3502 kvm_x86_ops->get_segment(vcpu, var, seg);
3503}
3504
c30a358d
JR		 3505static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3506{
3507 return gpa;
3508}
3509
02f59dc9
JR		 3510static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3511{
3512 gpa_t t_gpa;
3513 u32 error;
3514
3515 BUG_ON(!mmu_is_nested(vcpu));
3516
3517 /* NPT walks are always user-walks */
3518 access |= PFERR_USER_MASK;
3519 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &error);
3520 if (t_gpa == UNMAPPED_GVA)
3521 vcpu->arch.fault.error_code |= PFERR_NESTED_MASK;
3522
3523 return t_gpa;
3524}
3525
1871c602
GN		 3526gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3527{
3528 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
14dfe855 3529 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3530}
3531
3532 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3533{
3534 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3535 access |= PFERR_FETCH_MASK;
14dfe855 3536 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3537}
3538
3539gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3540{
3541 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3542 access |= PFERR_WRITE_MASK;
14dfe855 3543 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3544}
3545
3546/* uses this to access any guest's mapped memory without checking CPL */
3547gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3548{
14dfe855 3549 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error);
1871c602
GN		 3550}
3551
3552static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3553 struct kvm_vcpu *vcpu, u32 access,
3554 u32 *error)
bbd9b64e
CO		 3555{
3556 void *data = val;
10589a46 3557 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3558
3559 while (bytes) {
14dfe855
JR		 3560 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3561 error);
bbd9b64e 3562 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3563 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3564 int ret;
3565
10589a46
MT		 3566 if (gpa == UNMAPPED_GVA) {
3567 r = X86EMUL_PROPAGATE_FAULT;
3568 goto out;
3569 }
77c2002e 3570 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3571 if (ret < 0) {
c3cd7ffa 3572 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3573 goto out;
3574 }
bbd9b64e 3575
77c2002e
IE		 3576 bytes -= toread;
3577 data += toread;
3578 addr += toread;
bbd9b64e 3579 }
10589a46 3580out:
10589a46 3581 return r;
bbd9b64e 3582}
77c2002e 3583
1871c602
GN		 3584/* used for instruction fetching */
3585static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3586 struct kvm_vcpu *vcpu, u32 *error)
3587{
3588 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3589 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3590 access | PFERR_FETCH_MASK, error);
3591}
3592
3593static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3594 struct kvm_vcpu *vcpu, u32 *error)
3595{
3596 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3597 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3598 error);
3599}
3600
3601static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3602 struct kvm_vcpu *vcpu, u32 *error)
3603{
3604 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3605}
3606
7972995b 3607static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3608 unsigned int bytes,
7972995b 3609 struct kvm_vcpu *vcpu,
2dafc6c2 3610 u32 *error)
77c2002e
IE		 3611{
3612 void *data = val;
3613 int r = X86EMUL_CONTINUE;
3614
3615 while (bytes) {
14dfe855
JR		 3616 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3617 PFERR_WRITE_MASK,
3618 error);
77c2002e
IE		 3619 unsigned offset = addr & (PAGE_SIZE-1);
3620 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3621 int ret;
3622
3623 if (gpa == UNMAPPED_GVA) {
3624 r = X86EMUL_PROPAGATE_FAULT;
3625 goto out;
3626 }
3627 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3628 if (ret < 0) {
c3cd7ffa 3629 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3630 goto out;
3631 }
3632
3633 bytes -= towrite;
3634 data += towrite;
3635 addr += towrite;
3636 }
3637out:
3638 return r;
3639}
3640
bbd9b64e
CO		 3641static int emulator_read_emulated(unsigned long addr,
3642 void *val,
3643 unsigned int bytes,
8fe681e9 3644 unsigned int *error_code,
bbd9b64e
CO		 3645 struct kvm_vcpu *vcpu)
3646{
bbd9b64e
CO		 3647 gpa_t gpa;
3648
3649 if (vcpu->mmio_read_completed) {
3650 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3651 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3652 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3653 vcpu->mmio_read_completed = 0;
3654 return X86EMUL_CONTINUE;
3655 }
3656
8fe681e9 3657 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3658
8fe681e9 3659 if (gpa == UNMAPPED_GVA)
1871c602 3660 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3661
3662 /* For APIC access vmexit */
3663 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3664 goto mmio;
3665
1871c602 3666 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3667 == X86EMUL_CONTINUE)
bbd9b64e 3668 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3669
3670mmio:
3671 /*
3672 * Is this MMIO handled locally?
3673 */
aec51dc4
AK		 3674 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3675 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3676 return X86EMUL_CONTINUE;
3677 }
aec51dc4
AK		 3678
3679 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3680
3681 vcpu->mmio_needed = 1;
411c35b7
GN		 3682 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3683 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3684 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3685 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3686
c3cd7ffa 3687 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3688}
3689
3200f405 3690int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3691 const void *val, int bytes)
bbd9b64e
CO		 3692{
3693 int ret;
3694
3695 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3696 if (ret < 0)
bbd9b64e 3697 return 0;
ad218f85 3698 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3699 return 1;
3700}
3701
3702static int emulator_write_emulated_onepage(unsigned long addr,
3703 const void *val,
3704 unsigned int bytes,
8fe681e9 3705 unsigned int *error_code,
bbd9b64e
CO		 3706 struct kvm_vcpu *vcpu)
3707{
10589a46
MT		 3708 gpa_t gpa;
3709
8fe681e9 3710 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3711
8fe681e9 3712 if (gpa == UNMAPPED_GVA)
bbd9b64e 3713 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3714
3715 /* For APIC access vmexit */
3716 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3717 goto mmio;
3718
3719 if (emulator_write_phys(vcpu, gpa, val, bytes))
3720 return X86EMUL_CONTINUE;
3721
3722mmio:
aec51dc4 3723 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3724 /*
3725 * Is this MMIO handled locally?
3726 */
bda9020e 3727 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3728 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3729
3730 vcpu->mmio_needed = 1;
411c35b7
GN		 3731 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3732 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3733 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3734 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3735 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3736
3737 return X86EMUL_CONTINUE;
3738}
3739
3740int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3741 const void *val,
3742 unsigned int bytes,
8fe681e9 3743 unsigned int *error_code,
8f6abd06 3744 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3745{
3746 /* Crossing a page boundary? */
3747 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3748 int rc, now;
3749
3750 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3751 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3752 vcpu);
bbd9b64e
CO		 3753 if (rc != X86EMUL_CONTINUE)
3754 return rc;
3755 addr += now;
3756 val += now;
3757 bytes -= now;
3758 }
8fe681e9
GN		 3759 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3760 vcpu);
bbd9b64e 3761}
bbd9b64e 3762
daea3e73
AK		 3763#define CMPXCHG_TYPE(t, ptr, old, new) \
3764 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3765
3766#ifdef CONFIG_X86_64
3767# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3768#else
3769# define CMPXCHG64(ptr, old, new) \
9749a6c0 3770 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3771#endif
3772
bbd9b64e
CO		 3773static int emulator_cmpxchg_emulated(unsigned long addr,
3774 const void *old,
3775 const void *new,
3776 unsigned int bytes,
8fe681e9 3777 unsigned int *error_code,
bbd9b64e
CO		 3778 struct kvm_vcpu *vcpu)
3779{
daea3e73
AK		 3780 gpa_t gpa;
3781 struct page *page;
3782 char *kaddr;
3783 bool exchanged;
2bacc55c 3784
daea3e73
AK		 3785 /* guests cmpxchg8b have to be emulated atomically */
3786 if (bytes > 8 || (bytes & (bytes - 1)))
3787 goto emul_write;
10589a46 3788
daea3e73 3789 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3790
daea3e73
AK		 3791 if (gpa == UNMAPPED_GVA ||
3792 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3793 goto emul_write;
2bacc55c 3794
daea3e73
AK		 3795 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3796 goto emul_write;
72dc67a6 3797
daea3e73 3798 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3799 if (is_error_page(page)) {
3800 kvm_release_page_clean(page);
3801 goto emul_write;
3802 }
72dc67a6 3803
daea3e73
AK		 3804 kaddr = kmap_atomic(page, KM_USER0);
3805 kaddr += offset_in_page(gpa);
3806 switch (bytes) {
3807 case 1:
3808 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3809 break;
3810 case 2:
3811 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3812 break;
3813 case 4:
3814 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3815 break;
3816 case 8:
3817 exchanged = CMPXCHG64(kaddr, old, new);
3818 break;
3819 default:
3820 BUG();
2bacc55c 3821 }
daea3e73
AK		 3822 kunmap_atomic(kaddr, KM_USER0);
3823 kvm_release_page_dirty(page);
3824
3825 if (!exchanged)
3826 return X86EMUL_CMPXCHG_FAILED;
3827
8f6abd06
GN		 3828 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3829
3830 return X86EMUL_CONTINUE;
4a5f48f6 3831
3200f405 3832emul_write:
daea3e73 3833 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3834
8fe681e9 3835 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3836}
3837
cf8f70bf
GN		 3838static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3839{
3840 /* TODO: String I/O for in kernel device */
3841 int r;
3842
3843 if (vcpu->arch.pio.in)
3844 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3845 vcpu->arch.pio.size, pd);
3846 else
3847 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3848 vcpu->arch.pio.port, vcpu->arch.pio.size,
3849 pd);
3850 return r;
3851}
3852
3853
3854static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3855 unsigned int count, struct kvm_vcpu *vcpu)
3856{
7972995b 3857 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3858 goto data_avail;
3859
c41a15dd 3860 trace_kvm_pio(0, port, size, 1);
cf8f70bf
GN		 3861
3862 vcpu->arch.pio.port = port;
3863 vcpu->arch.pio.in = 1;
7972995b 3864 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3865 vcpu->arch.pio.size = size;
3866
3867 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3868 data_avail:
3869 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3870 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3871 return 1;
3872 }
3873
3874 vcpu->run->exit_reason = KVM_EXIT_IO;
3875 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3876 vcpu->run->io.size = size;
3877 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3878 vcpu->run->io.count = count;
3879 vcpu->run->io.port = port;
3880
3881 return 0;
3882}
3883
3884static int emulator_pio_out_emulated(int size, unsigned short port,
3885 const void *val, unsigned int count,
3886 struct kvm_vcpu *vcpu)
3887{
c41a15dd 3888 trace_kvm_pio(1, port, size, 1);
cf8f70bf
GN		 3889
3890 vcpu->arch.pio.port = port;
3891 vcpu->arch.pio.in = 0;
7972995b 3892 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3893 vcpu->arch.pio.size = size;
3894
3895 memcpy(vcpu->arch.pio_data, val, size * count);
3896
3897 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3898 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3899 return 1;
3900 }
3901
3902 vcpu->run->exit_reason = KVM_EXIT_IO;
3903 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3904 vcpu->run->io.size = size;
3905 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3906 vcpu->run->io.count = count;
3907 vcpu->run->io.port = port;
3908
3909 return 0;
3910}
3911
bbd9b64e
CO		 3912static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3913{
3914 return kvm_x86_ops->get_segment_base(vcpu, seg);
3915}
3916
3917int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3918{
a7052897 3919 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3920 return X86EMUL_CONTINUE;
3921}
3922
f5f48ee1
SY		 3923int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3924{
3925 if (!need_emulate_wbinvd(vcpu))
3926 return X86EMUL_CONTINUE;
3927
3928 if (kvm_x86_ops->has_wbinvd_exit()) {
3929 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3930 wbinvd_ipi, NULL, 1);
3931 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3932 }
3933 wbinvd();
3934 return X86EMUL_CONTINUE;
3935}
3936EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3937
bbd9b64e
CO		 3938int emulate_clts(struct kvm_vcpu *vcpu)
3939{
4d4ec087 3940 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3941 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3942 return X86EMUL_CONTINUE;
3943}
3944
35aa5375 3945int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3946{
338dbc97 3947 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3948}
3949
35aa5375 3950int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3951{
338dbc97
GN		 3952
3953 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3954}
3955
52a46617 3956static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3957{
52a46617 3958 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3959}
3960
52a46617 3961static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3962{
52a46617
GN		 3963 unsigned long value;
3964
3965 switch (cr) {
3966 case 0:
3967 value = kvm_read_cr0(vcpu);
3968 break;
3969 case 2:
3970 value = vcpu->arch.cr2;
3971 break;
3972 case 3:
3973 value = vcpu->arch.cr3;
3974 break;
3975 case 4:
3976 value = kvm_read_cr4(vcpu);
3977 break;
3978 case 8:
3979 value = kvm_get_cr8(vcpu);
3980 break;
3981 default:
3982 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3983 return 0;
3984 }
3985
3986 return value;
3987}
3988
0f12244f 3989static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3990{
0f12244f
GN		 3991 int res = 0;
3992
52a46617
GN		 3993 switch (cr) {
3994 case 0:
49a9b07e 3995 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3996 break;
3997 case 2:
3998 vcpu->arch.cr2 = val;
3999 break;
4000 case 3:
2390218b 4001 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4002 break;
4003 case 4:
a83b29c6 4004 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4005 break;
4006 case 8:
0f12244f 4007 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 4008 break;
4009 default:
4010 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4011 res = -1;
52a46617 4012 }
0f12244f
GN		 4013
4014 return res;
52a46617
GN		 4015}
4016
9c537244
GN		 4017static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4018{
4019 return kvm_x86_ops->get_cpl(vcpu);
4020}
4021
2dafc6c2
GN		 4022static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4023{
4024 kvm_x86_ops->get_gdt(vcpu, dt);
4025}
4026
160ce1f1
MG		 4027static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4028{
4029 kvm_x86_ops->get_idt(vcpu, dt);
4030}
4031
5951c442
GN		 4032static unsigned long emulator_get_cached_segment_base(int seg,
4033 struct kvm_vcpu *vcpu)
4034{
4035 return get_segment_base(vcpu, seg);
4036}
4037
2dafc6c2
GN		 4038static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4039 struct kvm_vcpu *vcpu)
4040{
4041 struct kvm_segment var;
4042
4043 kvm_get_segment(vcpu, &var, seg);
4044
4045 if (var.unusable)
4046 return false;
4047
4048 if (var.g)
4049 var.limit >>= 12;
4050 set_desc_limit(desc, var.limit);
4051 set_desc_base(desc, (unsigned long)var.base);
4052 desc->type = var.type;
4053 desc->s = var.s;
4054 desc->dpl = var.dpl;
4055 desc->p = var.present;
4056 desc->avl = var.avl;
4057 desc->l = var.l;
4058 desc->d = var.db;
4059 desc->g = var.g;
4060
4061 return true;
4062}
4063
4064static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4065 struct kvm_vcpu *vcpu)
4066{
4067 struct kvm_segment var;
4068
4069 /* needed to preserve selector */
4070 kvm_get_segment(vcpu, &var, seg);
4071
4072 var.base = get_desc_base(desc);
4073 var.limit = get_desc_limit(desc);
4074 if (desc->g)
4075 var.limit = (var.limit << 12) | 0xfff;
4076 var.type = desc->type;
4077 var.present = desc->p;
4078 var.dpl = desc->dpl;
4079 var.db = desc->d;
4080 var.s = desc->s;
4081 var.l = desc->l;
4082 var.g = desc->g;
4083 var.avl = desc->avl;
4084 var.present = desc->p;
4085 var.unusable = !var.present;
4086 var.padding = 0;
4087
4088 kvm_set_segment(vcpu, &var, seg);
4089 return;
4090}
4091
4092static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4093{
4094 struct kvm_segment kvm_seg;
4095
4096 kvm_get_segment(vcpu, &kvm_seg, seg);
4097 return kvm_seg.selector;
4098}
4099
4100static void emulator_set_segment_selector(u16 sel, int seg,
4101 struct kvm_vcpu *vcpu)
4102{
4103 struct kvm_segment kvm_seg;
4104
4105 kvm_get_segment(vcpu, &kvm_seg, seg);
4106 kvm_seg.selector = sel;
4107 kvm_set_segment(vcpu, &kvm_seg, seg);
4108}
4109
14af3f3c 4110static struct x86_emulate_ops emulate_ops = {
1871c602 4111 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4112 .write_std = kvm_write_guest_virt_system,
1871c602 4113 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4114 .read_emulated = emulator_read_emulated,
4115 .write_emulated = emulator_write_emulated,
4116 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4117 .pio_in_emulated = emulator_pio_in_emulated,
4118 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4119 .get_cached_descriptor = emulator_get_cached_descriptor,
4120 .set_cached_descriptor = emulator_set_cached_descriptor,
4121 .get_segment_selector = emulator_get_segment_selector,
4122 .set_segment_selector = emulator_set_segment_selector,
5951c442 4123 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4124 .get_gdt = emulator_get_gdt,
160ce1f1 4125 .get_idt = emulator_get_idt,
52a46617
GN		 4126 .get_cr = emulator_get_cr,
4127 .set_cr = emulator_set_cr,
9c537244 4128 .cpl = emulator_get_cpl,
35aa5375
GN		 4129 .get_dr = emulator_get_dr,
4130 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4131 .set_msr = kvm_set_msr,
4132 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4133};
4134
5fdbf976
MT		 4135static void cache_all_regs(struct kvm_vcpu *vcpu)
4136{
4137 kvm_register_read(vcpu, VCPU_REGS_RAX);
4138 kvm_register_read(vcpu, VCPU_REGS_RSP);
4139 kvm_register_read(vcpu, VCPU_REGS_RIP);
4140 vcpu->arch.regs_dirty = ~0;
4141}
4142
95cb2295
GN		 4143static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4144{
4145 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4146 /*
4147 * an sti; sti; sequence only disable interrupts for the first
4148 * instruction. So, if the last instruction, be it emulated or
4149 * not, left the system with the INT_STI flag enabled, it
4150 * means that the last instruction is an sti. We should not
4151 * leave the flag on in this case. The same goes for mov ss
4152 */
4153 if (!(int_shadow & mask))
4154 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4155}
4156
54b8486f
GN		 4157static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4158{
4159 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4160 if (ctxt->exception == PF_VECTOR)
d4f8cf66 4161 kvm_propagate_fault(vcpu);
54b8486f
GN		 4162 else if (ctxt->error_code_valid)
4163 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4164 else
4165 kvm_queue_exception(vcpu, ctxt->exception);
4166}
4167
8ec4722d
MG		 4168static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4169{
4170 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4171 int cs_db, cs_l;
4172
4173 cache_all_regs(vcpu);
4174
4175 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4176
4177 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4178 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4179 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4180 vcpu->arch.emulate_ctxt.mode =
4181 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4182 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4183 ? X86EMUL_MODE_VM86 : cs_l
4184 ? X86EMUL_MODE_PROT64 : cs_db
4185 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4186 memset(c, 0, sizeof(struct decode_cache));
4187 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4188}
4189
6d77dbfc
GN		 4190static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4191{
6d77dbfc
GN		 4192 ++vcpu->stat.insn_emulation_fail;
4193 trace_kvm_emulate_insn_failed(vcpu);
4194 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4195 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4196 vcpu->run->internal.ndata = 0;
4197 kvm_queue_exception(vcpu, UD_VECTOR);
4198 return EMULATE_FAIL;
4199}
4200
a6f177ef
GN		 4201static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4202{
4203 gpa_t gpa;
4204
68be0803
GN		 4205 if (tdp_enabled)
4206 return false;
4207
a6f177ef
GN		 4208 /*
4209 * if emulation was due to access to shadowed page table
4210 * and it failed try to unshadow page and re-entetr the
4211 * guest to let CPU execute the instruction.
4212 */
4213 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4214 return true;
4215
4216 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4217
4218 if (gpa == UNMAPPED_GVA)
4219 return true; /* let cpu generate fault */
4220
4221 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4222 return true;
4223
4224 return false;
4225}
4226
bbd9b64e 4227int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4228 unsigned long cr2,
4229 u16 error_code,
571008da 4230 int emulation_type)
bbd9b64e 4231{
95cb2295 4232 int r;
4d2179e1 4233 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4234
26eef70c 4235 kvm_clear_exception_queue(vcpu);
ad312c7c 4236 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4237 /*
56e82318 4238 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4239 * instead of direct ->regs accesses, can save hundred cycles
4240 * on Intel for instructions that don't read/change RSP, for
4241 * for example.
4242 */
4243 cache_all_regs(vcpu);
bbd9b64e 4244
571008da 4245 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4246 init_emulate_ctxt(vcpu);
95cb2295 4247 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4248 vcpu->arch.emulate_ctxt.exception = -1;
4fc40f07 4249 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4250
9aabc88f 4251 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
d47f00a6
JR		 4252 if (r == X86EMUL_PROPAGATE_FAULT)
4253 goto done;
4254
e46479f8 4255 trace_kvm_emulate_insn_start(vcpu);
571008da 4256
0cb5762e
AP		 4257 /* Only allow emulation of specific instructions on #UD
4258 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4259 if (emulation_type & EMULTYPE_TRAP_UD) {
4260 if (!c->twobyte)
4261 return EMULATE_FAIL;
4262 switch (c->b) {
4263 case 0x01: /* VMMCALL */
4264 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4265 return EMULATE_FAIL;
4266 break;
4267 case 0x34: /* sysenter */
4268 case 0x35: /* sysexit */
4269 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4270 return EMULATE_FAIL;
4271 break;
4272 case 0x05: /* syscall */
4273 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4274 return EMULATE_FAIL;
4275 break;
4276 default:
4277 return EMULATE_FAIL;
4278 }
4279
4280 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4281 return EMULATE_FAIL;
4282 }
571008da 4283
f2b5756b 4284 ++vcpu->stat.insn_emulation;
bbd9b64e 4285 if (r) {
a6f177ef 4286 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4287 return EMULATE_DONE;
6d77dbfc
GN		 4288 if (emulation_type & EMULTYPE_SKIP)
4289 return EMULATE_FAIL;
4290 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4291 }
4292 }
4293
ba8afb6b
GN		 4294 if (emulation_type & EMULTYPE_SKIP) {
4295 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4296 return EMULATE_DONE;
4297 }
4298
4d2179e1
GN		 4299 /* this is needed for vmware backdor interface to work since it
4300 changes registers values during IO operation */
4301 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4302
5cd21917 4303restart:
9aabc88f 4304 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4305
d2ddd1c4 4306 if (r == EMULATION_FAILED) {
a6f177ef 4307 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4308 return EMULATE_DONE;
4309
6d77dbfc 4310 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4311 }
4312
d47f00a6 4313done:
d2ddd1c4 4314 if (vcpu->arch.emulate_ctxt.exception >= 0) {
54b8486f 4315 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4316 r = EMULATE_DONE;
4317 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4318 if (!vcpu->arch.pio.in)
4319 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4320 r = EMULATE_DO_MMIO;
4321 } else if (vcpu->mmio_needed) {
3457e419
GN		 4322 if (vcpu->mmio_is_write)
4323 vcpu->mmio_needed = 0;
e85d28f8 4324 r = EMULATE_DO_MMIO;
d2ddd1c4 4325 } else if (r == EMULATION_RESTART)
5cd21917 4326 goto restart;
d2ddd1c4
GN		 4327 else
4328 r = EMULATE_DONE;
f850e2e6 4329
e85d28f8
GN		 4330 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4331 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4332 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4333 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4334
4335 return r;
de7d789a 4336}
bbd9b64e 4337EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4338
cf8f70bf 4339int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4340{
cf8f70bf
GN		 4341 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4342 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4343 /* do not return to emulator after return from userspace */
7972995b 4344 vcpu->arch.pio.count = 0;
de7d789a
CO		 4345 return ret;
4346}
cf8f70bf 4347EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4348
8cfdc000
ZA		 4349static void tsc_bad(void *info)
4350{
4351 __get_cpu_var(cpu_tsc_khz) = 0;
4352}
4353
4354static void tsc_khz_changed(void *data)
c8076604 4355{
8cfdc000
ZA		 4356 struct cpufreq_freqs *freq = data;
4357 unsigned long khz = 0;
4358
4359 if (data)
4360 khz = freq->new;
4361 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4362 khz = cpufreq_quick_get(raw_smp_processor_id());
4363 if (!khz)
4364 khz = tsc_khz;
4365 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4366}
4367
c8076604
GH		 4368static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4369 void *data)
4370{
4371 struct cpufreq_freqs *freq = data;
4372 struct kvm *kvm;
4373 struct kvm_vcpu *vcpu;
4374 int i, send_ipi = 0;
4375
8cfdc000
ZA		 4376 /*
4377 * We allow guests to temporarily run on slowing clocks,
4378 * provided we notify them after, or to run on accelerating
4379 * clocks, provided we notify them before. Thus time never
4380 * goes backwards.
4381 *
4382 * However, we have a problem. We can't atomically update
4383 * the frequency of a given CPU from this function; it is
4384 * merely a notifier, which can be called from any CPU.
4385 * Changing the TSC frequency at arbitrary points in time
4386 * requires a recomputation of local variables related to
4387 * the TSC for each VCPU. We must flag these local variables
4388 * to be updated and be sure the update takes place with the
4389 * new frequency before any guests proceed.
4390 *
4391 * Unfortunately, the combination of hotplug CPU and frequency
4392 * change creates an intractable locking scenario; the order
4393 * of when these callouts happen is undefined with respect to
4394 * CPU hotplug, and they can race with each other. As such,
4395 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4396 * undefined; you can actually have a CPU frequency change take
4397 * place in between the computation of X and the setting of the
4398 * variable. To protect against this problem, all updates of
4399 * the per_cpu tsc_khz variable are done in an interrupt
4400 * protected IPI, and all callers wishing to update the value
4401 * must wait for a synchronous IPI to complete (which is trivial
4402 * if the caller is on the CPU already). This establishes the
4403 * necessary total order on variable updates.
4404 *
4405 * Note that because a guest time update may take place
4406 * anytime after the setting of the VCPU's request bit, the
4407 * correct TSC value must be set before the request. However,
4408 * to ensure the update actually makes it to any guest which
4409 * starts running in hardware virtualization between the set
4410 * and the acquisition of the spinlock, we must also ping the
4411 * CPU after setting the request bit.
4412 *
4413 */
4414
c8076604
GH		 4415 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4416 return 0;
4417 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4418 return 0;
8cfdc000
ZA		 4419
4420 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4421
4422 spin_lock(&kvm_lock);
4423 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4424 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4425 if (vcpu->cpu != freq->cpu)
4426 continue;
4427 if (!kvm_request_guest_time_update(vcpu))
4428 continue;
4429 if (vcpu->cpu != smp_processor_id())
8cfdc000 4430 send_ipi = 1;
c8076604
GH		 4431 }
4432 }
4433 spin_unlock(&kvm_lock);
4434
4435 if (freq->old < freq->new && send_ipi) {
4436 /*
4437 * We upscale the frequency. Must make the guest
4438 * doesn't see old kvmclock values while running with
4439 * the new frequency, otherwise we risk the guest sees
4440 * time go backwards.
4441 *
4442 * In case we update the frequency for another cpu
4443 * (which might be in guest context) send an interrupt
4444 * to kick the cpu out of guest context. Next time
4445 * guest context is entered kvmclock will be updated,
4446 * so the guest will not see stale values.
4447 */
8cfdc000 4448 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4449 }
4450 return 0;
4451}
4452
4453static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4454 .notifier_call = kvmclock_cpufreq_notifier
4455};
4456
4457static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4458 unsigned long action, void *hcpu)
4459{
4460 unsigned int cpu = (unsigned long)hcpu;
4461
4462 switch (action) {
4463 case CPU_ONLINE:
4464 case CPU_DOWN_FAILED:
4465 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4466 break;
4467 case CPU_DOWN_PREPARE:
4468 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4469 break;
4470 }
4471 return NOTIFY_OK;
4472}
4473
4474static struct notifier_block kvmclock_cpu_notifier_block = {
4475 .notifier_call = kvmclock_cpu_notifier,
4476 .priority = -INT_MAX
c8076604
GH		 4477};
4478
b820cc0c
ZA		 4479static void kvm_timer_init(void)
4480{
4481 int cpu;
4482
8cfdc000 4483 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4484 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4485 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4486 CPUFREQ_TRANSITION_NOTIFIER);
4487 }
8cfdc000
ZA		 4488 for_each_online_cpu(cpu)
4489 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4490}
4491
ff9d07a0
ZY		 4492static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4493
4494static int kvm_is_in_guest(void)
4495{
4496 return percpu_read(current_vcpu) != NULL;
4497}
4498
4499static int kvm_is_user_mode(void)
4500{
4501 int user_mode = 3;
dcf46b94 4502
ff9d07a0
ZY		 4503 if (percpu_read(current_vcpu))
4504 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4505
ff9d07a0
ZY		 4506 return user_mode != 0;
4507}
4508
4509static unsigned long kvm_get_guest_ip(void)
4510{
4511 unsigned long ip = 0;
dcf46b94 4512
ff9d07a0
ZY		 4513 if (percpu_read(current_vcpu))
4514 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4515
ff9d07a0
ZY		 4516 return ip;
4517}
4518
4519static struct perf_guest_info_callbacks kvm_guest_cbs = {
4520 .is_in_guest = kvm_is_in_guest,
4521 .is_user_mode = kvm_is_user_mode,
4522 .get_guest_ip = kvm_get_guest_ip,
4523};
4524
4525void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4526{
4527 percpu_write(current_vcpu, vcpu);
4528}
4529EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4530
4531void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4532{
4533 percpu_write(current_vcpu, NULL);
4534}
4535EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4536
f8c16bba 4537int kvm_arch_init(void *opaque)
043405e1 4538{
b820cc0c 4539 int r;
f8c16bba
ZX		 4540 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4541
f8c16bba
ZX		 4542 if (kvm_x86_ops) {
4543 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4544 r = -EEXIST;
4545 goto out;
f8c16bba
ZX		 4546 }
4547
4548 if (!ops->cpu_has_kvm_support()) {
4549 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4550 r = -EOPNOTSUPP;
4551 goto out;
f8c16bba
ZX		 4552 }
4553 if (ops->disabled_by_bios()) {
4554 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4555 r = -EOPNOTSUPP;
4556 goto out;
f8c16bba
ZX		 4557 }
4558
97db56ce
AK		 4559 r = kvm_mmu_module_init();
4560 if (r)
4561 goto out;
4562
4563 kvm_init_msr_list();
4564
f8c16bba 4565 kvm_x86_ops = ops;
56c6d28a 4566 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4567 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4568 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4569 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4570
b820cc0c 4571 kvm_timer_init();
c8076604 4572
ff9d07a0
ZY		 4573 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4574
2acf923e
DC		 4575 if (cpu_has_xsave)
4576 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4577
f8c16bba 4578 return 0;
56c6d28a
ZX		 4579
4580out:
56c6d28a 4581 return r;
043405e1 4582}
8776e519 4583
f8c16bba
ZX		 4584void kvm_arch_exit(void)
4585{
ff9d07a0
ZY		 4586 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4587
888d256e
JK		 4588 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4589 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4590 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4591 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4592 kvm_x86_ops = NULL;
56c6d28a
ZX		 4593 kvm_mmu_module_exit();
4594}
f8c16bba 4595
8776e519
HB		 4596int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4597{
4598 ++vcpu->stat.halt_exits;
4599 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4600 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4601 return 1;
4602 } else {
4603 vcpu->run->exit_reason = KVM_EXIT_HLT;
4604 return 0;
4605 }
4606}
4607EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4608
2f333bcb
MT		 4609static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4610 unsigned long a1)
4611{
4612 if (is_long_mode(vcpu))
4613 return a0;
4614 else
4615 return a0 | ((gpa_t)a1 << 32);
4616}
4617
55cd8e5a
GN		 4618int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4619{
4620 u64 param, ingpa, outgpa, ret;
4621 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4622 bool fast, longmode;
4623 int cs_db, cs_l;
4624
4625 /*
4626 * hypercall generates UD from non zero cpl and real mode
4627 * per HYPER-V spec
4628 */
3eeb3288 4629 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4630 kvm_queue_exception(vcpu, UD_VECTOR);
4631 return 0;
4632 }
4633
4634 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4635 longmode = is_long_mode(vcpu) && cs_l == 1;
4636
4637 if (!longmode) {
ccd46936
GN		 4638 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4639 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4640 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4641 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4642 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4643 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4644 }
4645#ifdef CONFIG_X86_64
4646 else {
4647 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4648 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4649 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4650 }
4651#endif
4652
4653 code = param & 0xffff;
4654 fast = (param >> 16) & 0x1;
4655 rep_cnt = (param >> 32) & 0xfff;
4656 rep_idx = (param >> 48) & 0xfff;
4657
4658 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4659
c25bc163
GN		 4660 switch (code) {
4661 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4662 kvm_vcpu_on_spin(vcpu);
4663 break;
4664 default:
4665 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4666 break;
4667 }
55cd8e5a
GN		 4668
4669 ret = res | (((u64)rep_done & 0xfff) << 32);
4670 if (longmode) {
4671 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4672 } else {
4673 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4674 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4675 }
4676
4677 return 1;
4678}
4679
8776e519
HB		 4680int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4681{
4682 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4683 int r = 1;
8776e519 4684
55cd8e5a
GN		 4685 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4686 return kvm_hv_hypercall(vcpu);
4687
5fdbf976
MT		 4688 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4689 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4690 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4691 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4692 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4693
229456fc 4694 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4695
8776e519
HB		 4696 if (!is_long_mode(vcpu)) {
4697 nr &= 0xFFFFFFFF;
4698 a0 &= 0xFFFFFFFF;
4699 a1 &= 0xFFFFFFFF;
4700 a2 &= 0xFFFFFFFF;
4701 a3 &= 0xFFFFFFFF;
4702 }
4703
07708c4a
JK		 4704 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4705 ret = -KVM_EPERM;
4706 goto out;
4707 }
4708
8776e519 4709 switch (nr) {
b93463aa
AK		 4710 case KVM_HC_VAPIC_POLL_IRQ:
4711 ret = 0;
4712 break;
2f333bcb
MT		 4713 case KVM_HC_MMU_OP:
4714 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4715 break;
8776e519
HB		 4716 default:
4717 ret = -KVM_ENOSYS;
4718 break;
4719 }
07708c4a 4720out:
5fdbf976 4721 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4722 ++vcpu->stat.hypercalls;
2f333bcb 4723 return r;
8776e519
HB		 4724}
4725EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4726
4727int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4728{
4729 char instruction[3];
5fdbf976 4730 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4731
8776e519
HB		 4732 /*
4733 * Blow out the MMU to ensure that no other VCPU has an active mapping
4734 * to ensure that the updated hypercall appears atomically across all
4735 * VCPUs.
4736 */
4737 kvm_mmu_zap_all(vcpu->kvm);
4738
8776e519 4739 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4740
8fe681e9 4741 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4742}
4743
8776e519
HB		 4744void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4745{
89a27f4d 4746 struct desc_ptr dt = { limit, base };
8776e519
HB		 4747
4748 kvm_x86_ops->set_gdt(vcpu, &dt);
4749}
4750
4751void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4752{
89a27f4d 4753 struct desc_ptr dt = { limit, base };
8776e519
HB		 4754
4755 kvm_x86_ops->set_idt(vcpu, &dt);
4756}
4757
07716717
DK		 4758static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4759{
ad312c7c
ZX		 4760 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4761 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4762
4763 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4764 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4765 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4766 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4767 if (ej->function == e->function) {
4768 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4769 return j;
4770 }
4771 }
4772 return 0; /* silence gcc, even though control never reaches here */
4773}
4774
4775/* find an entry with matching function, matching index (if needed), and that
4776 * should be read next (if it's stateful) */
4777static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4778 u32 function, u32 index)
4779{
4780 if (e->function != function)
4781 return 0;
4782 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4783 return 0;
4784 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4785 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4786 return 0;
4787 return 1;
4788}
4789
d8017474
AG		 4790struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4791 u32 function, u32 index)
8776e519
HB		 4792{
4793 int i;
d8017474 4794 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4795
ad312c7c 4796 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4797 struct kvm_cpuid_entry2 *e;
4798
ad312c7c 4799 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4800 if (is_matching_cpuid_entry(e, function, index)) {
4801 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4802 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4803 best = e;
4804 break;
4805 }
4806 /*
4807 * Both basic or both extended?
4808 */
4809 if (((e->function ^ function) & 0x80000000) == 0)
4810 if (!best || e->function > best->function)
4811 best = e;
4812 }
d8017474
AG		 4813 return best;
4814}
0e851880 4815EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4816
82725b20
DE		 4817int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4818{
4819 struct kvm_cpuid_entry2 *best;
4820
f7a71197
AK		 4821 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4822 if (!best || best->eax < 0x80000008)
4823 goto not_found;
82725b20
DE		 4824 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4825 if (best)
4826 return best->eax & 0xff;
f7a71197 4827not_found:
82725b20
DE		 4828 return 36;
4829}
4830
d8017474
AG		 4831void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4832{
4833 u32 function, index;
4834 struct kvm_cpuid_entry2 *best;
4835
4836 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4837 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4838 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4839 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4840 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4841 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4842 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4843 if (best) {
5fdbf976
MT		 4844 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4845 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4846 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4847 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4848 }
8776e519 4849 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4850 trace_kvm_cpuid(function,
4851 kvm_register_read(vcpu, VCPU_REGS_RAX),
4852 kvm_register_read(vcpu, VCPU_REGS_RBX),
4853 kvm_register_read(vcpu, VCPU_REGS_RCX),
4854 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4855}
4856EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4857
b6c7a5dc
HB		 4858/*
4859 * Check if userspace requested an interrupt window, and that the
4860 * interrupt window is open.
4861 *
4862 * No need to exit to userspace if we already have an interrupt queued.
4863 */
851ba692 4864static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4865{
8061823a 4866 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4867 vcpu->run->request_interrupt_window &&
5df56646 4868 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4869}
4870
851ba692 4871static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4872{
851ba692
AK		 4873 struct kvm_run *kvm_run = vcpu->run;
4874
91586a3b 4875 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4876 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4877 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4878 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4879 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4880 else
b6c7a5dc 4881 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4882 kvm_arch_interrupt_allowed(vcpu) &&
4883 !kvm_cpu_has_interrupt(vcpu) &&
4884 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4885}
4886
b93463aa
AK		 4887static void vapic_enter(struct kvm_vcpu *vcpu)
4888{
4889 struct kvm_lapic *apic = vcpu->arch.apic;
4890 struct page *page;
4891
4892 if (!apic || !apic->vapic_addr)
4893 return;
4894
4895 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4896
4897 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4898}
4899
4900static void vapic_exit(struct kvm_vcpu *vcpu)
4901{
4902 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4903 int idx;
b93463aa
AK		 4904
4905 if (!apic || !apic->vapic_addr)
4906 return;
4907
f656ce01 4908 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4909 kvm_release_page_dirty(apic->vapic_page);
4910 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4911 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4912}
4913
95ba8273
GN		 4914static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4915{
4916 int max_irr, tpr;
4917
4918 if (!kvm_x86_ops->update_cr8_intercept)
4919 return;
4920
88c808fd
AK		 4921 if (!vcpu->arch.apic)
4922 return;
4923
8db3baa2
GN		 4924 if (!vcpu->arch.apic->vapic_addr)
4925 max_irr = kvm_lapic_find_highest_irr(vcpu);
4926 else
4927 max_irr = -1;
95ba8273
GN		 4928
4929 if (max_irr != -1)
4930 max_irr >>= 4;
4931
4932 tpr = kvm_lapic_get_cr8(vcpu);
4933
4934 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4935}
4936
851ba692 4937static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4938{
4939 /* try to reinject previous events if any */
b59bb7bd 4940 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4941 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4942 vcpu->arch.exception.has_error_code,
4943 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4944 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4945 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4946 vcpu->arch.exception.error_code,
4947 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4948 return;
4949 }
4950
95ba8273
GN		 4951 if (vcpu->arch.nmi_injected) {
4952 kvm_x86_ops->set_nmi(vcpu);
4953 return;
4954 }
4955
4956 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4957 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4958 return;
4959 }
4960
4961 /* try to inject new event if pending */
4962 if (vcpu->arch.nmi_pending) {
4963 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4964 vcpu->arch.nmi_pending = false;
4965 vcpu->arch.nmi_injected = true;
4966 kvm_x86_ops->set_nmi(vcpu);
4967 }
4968 } else if (kvm_cpu_has_interrupt(vcpu)) {
4969 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4970 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4971 false);
4972 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4973 }
4974 }
4975}
4976
2acf923e
DC		 4977static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
4978{
4979 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
4980 !vcpu->guest_xcr0_loaded) {
4981 /* kvm_set_xcr() also depends on this */
4982 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
4983 vcpu->guest_xcr0_loaded = 1;
4984 }
4985}
4986
4987static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
4988{
4989 if (vcpu->guest_xcr0_loaded) {
4990 if (vcpu->arch.xcr0 != host_xcr0)
4991 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
4992 vcpu->guest_xcr0_loaded = 0;
4993 }
4994}
4995
851ba692 4996static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4997{
4998 int r;
6a8b1d13 4999 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5000 vcpu->run->request_interrupt_window;
b6c7a5dc 5001
3e007509 5002 if (vcpu->requests) {
a8eeb04a 5003 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5004 kvm_mmu_unload(vcpu);
a8eeb04a 5005 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5006 __kvm_migrate_timers(vcpu);
8cfdc000
ZA		 5007 if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu)) {
5008 r = kvm_write_guest_time(vcpu);
5009 if (unlikely(r))
5010 goto out;
5011 }
a8eeb04a 5012 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5013 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5014 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5015 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5016 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5017 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5018 r = 0;
5019 goto out;
5020 }
a8eeb04a 5021 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5022 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5023 r = 0;
5024 goto out;
5025 }
a8eeb04a 5026 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5027 vcpu->fpu_active = 0;
5028 kvm_x86_ops->fpu_deactivate(vcpu);
5029 }
2f52d58c 5030 }
b93463aa 5031
3e007509
AK		 5032 r = kvm_mmu_reload(vcpu);
5033 if (unlikely(r))
5034 goto out;
5035
b6c7a5dc
HB		 5036 preempt_disable();
5037
5038 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5039 if (vcpu->fpu_active)
5040 kvm_load_guest_fpu(vcpu);
2acf923e 5041 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5042
d94e1dc9
AK		 5043 atomic_set(&vcpu->guest_mode, 1);
5044 smp_wmb();
b6c7a5dc 5045
d94e1dc9 5046 local_irq_disable();
32f88400 5047
d94e1dc9
AK		 5048 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5049 || need_resched() || signal_pending(current)) {
5050 atomic_set(&vcpu->guest_mode, 0);
5051 smp_wmb();
6c142801
AK		 5052 local_irq_enable();
5053 preempt_enable();
5054 r = 1;
5055 goto out;
5056 }
5057
851ba692 5058 inject_pending_event(vcpu);
b6c7a5dc 5059
6a8b1d13
GN		 5060 /* enable NMI/IRQ window open exits if needed */
5061 if (vcpu->arch.nmi_pending)
5062 kvm_x86_ops->enable_nmi_window(vcpu);
5063 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5064 kvm_x86_ops->enable_irq_window(vcpu);
5065
95ba8273 5066 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 5067 update_cr8_intercept(vcpu);
5068 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 5069 }
b93463aa 5070
f656ce01 5071 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5072
b6c7a5dc
HB		 5073 kvm_guest_enter();
5074
42dbaa5a 5075 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5076 set_debugreg(0, 7);
5077 set_debugreg(vcpu->arch.eff_db[0], 0);
5078 set_debugreg(vcpu->arch.eff_db[1], 1);
5079 set_debugreg(vcpu->arch.eff_db[2], 2);
5080 set_debugreg(vcpu->arch.eff_db[3], 3);
5081 }
b6c7a5dc 5082
229456fc 5083 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5084 kvm_x86_ops->run(vcpu);
b6c7a5dc 5085
24f1e32c
FW		 5086 /*
5087 * If the guest has used debug registers, at least dr7
5088 * will be disabled while returning to the host.
5089 * If we don't have active breakpoints in the host, we don't
5090 * care about the messed up debug address registers. But if
5091 * we have some of them active, restore the old state.
5092 */
59d8eb53 5093 if (hw_breakpoint_active())
24f1e32c 5094 hw_breakpoint_restore();
42dbaa5a 5095
1d5f066e
ZA		 5096 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5097
d94e1dc9
AK		 5098 atomic_set(&vcpu->guest_mode, 0);
5099 smp_wmb();
b6c7a5dc
HB		 5100 local_irq_enable();
5101
5102 ++vcpu->stat.exits;
5103
5104 /*
5105 * We must have an instruction between local_irq_enable() and
5106 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5107 * the interrupt shadow. The stat.exits increment will do nicely.
5108 * But we need to prevent reordering, hence this barrier():
5109 */
5110 barrier();
5111
5112 kvm_guest_exit();
5113
5114 preempt_enable();
5115
f656ce01 5116 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5117
b6c7a5dc
HB		 5118 /*
5119 * Profile KVM exit RIPs:
5120 */
5121 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5122 unsigned long rip = kvm_rip_read(vcpu);
5123 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5124 }
5125
298101da 5126
b93463aa
AK		 5127 kvm_lapic_sync_from_vapic(vcpu);
5128
851ba692 5129 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5130out:
5131 return r;
5132}
b6c7a5dc 5133
09cec754 5134
851ba692 5135static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5136{
5137 int r;
f656ce01 5138 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5139
5140 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5141 pr_debug("vcpu %d received sipi with vector # %x\n",
5142 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5143 kvm_lapic_reset(vcpu);
5f179287 5144 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5145 if (r)
5146 return r;
5147 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5148 }
5149
f656ce01 5150 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5151 vapic_enter(vcpu);
5152
5153 r = 1;
5154 while (r > 0) {
af2152f5 5155 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 5156 r = vcpu_enter_guest(vcpu);
d7690175 5157 else {
f656ce01 5158 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5159 kvm_vcpu_block(vcpu);
f656ce01 5160 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5161 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5162 {
5163 switch(vcpu->arch.mp_state) {
5164 case KVM_MP_STATE_HALTED:
d7690175 5165 vcpu->arch.mp_state =
09cec754
GN		 5166 KVM_MP_STATE_RUNNABLE;
5167 case KVM_MP_STATE_RUNNABLE:
5168 break;
5169 case KVM_MP_STATE_SIPI_RECEIVED:
5170 default:
5171 r = -EINTR;
5172 break;
5173 }
5174 }
d7690175
MT		 5175 }
5176
09cec754
GN		 5177 if (r <= 0)
5178 break;
5179
5180 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5181 if (kvm_cpu_has_pending_timer(vcpu))
5182 kvm_inject_pending_timer_irqs(vcpu);
5183
851ba692 5184 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5185 r = -EINTR;
851ba692 5186 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5187 ++vcpu->stat.request_irq_exits;
5188 }
5189 if (signal_pending(current)) {
5190 r = -EINTR;
851ba692 5191 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5192 ++vcpu->stat.signal_exits;
5193 }
5194 if (need_resched()) {
f656ce01 5195 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5196 kvm_resched(vcpu);
f656ce01 5197 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5198 }
b6c7a5dc
HB		 5199 }
5200
f656ce01 5201 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5202
b93463aa
AK		 5203 vapic_exit(vcpu);
5204
b6c7a5dc
HB		 5205 return r;
5206}
5207
5208int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5209{
5210 int r;
5211 sigset_t sigsaved;
5212
ac9f6dc0
AK		 5213 if (vcpu->sigset_active)
5214 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5215
a4535290 5216 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5217 kvm_vcpu_block(vcpu);
d7690175 5218 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5219 r = -EAGAIN;
5220 goto out;
b6c7a5dc
HB		 5221 }
5222
b6c7a5dc
HB		 5223 /* re-sync apic's tpr */
5224 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5225 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5226
d2ddd1c4 5227 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5228 if (vcpu->mmio_needed) {
5229 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5230 vcpu->mmio_read_completed = 1;
5231 vcpu->mmio_needed = 0;
b6c7a5dc 5232 }
f656ce01 5233 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5234 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5235 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5236 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5237 r = 0;
5238 goto out;
5239 }
5240 }
5fdbf976
MT		 5241 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5242 kvm_register_write(vcpu, VCPU_REGS_RAX,
5243 kvm_run->hypercall.ret);
b6c7a5dc 5244
851ba692 5245 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5246
5247out:
f1d86e46 5248 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5249 if (vcpu->sigset_active)
5250 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5251
b6c7a5dc
HB		 5252 return r;
5253}
5254
5255int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5256{
5fdbf976
MT		 5257 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5258 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5259 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5260 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5261 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5262 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5263 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5264 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5265#ifdef CONFIG_X86_64
5fdbf976
MT		 5266 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5267 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5268 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5269 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5270 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5271 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5272 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5273 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5274#endif
5275
5fdbf976 5276 regs->rip = kvm_rip_read(vcpu);
91586a3b 5277 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5278
b6c7a5dc
HB		 5279 return 0;
5280}
5281
5282int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5283{
5fdbf976
MT		 5284 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5285 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5286 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5287 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5288 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5289 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5290 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5291 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5292#ifdef CONFIG_X86_64
5fdbf976
MT		 5293 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5294 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5295 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5296 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5297 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5298 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5299 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5300 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5301#endif
5302
5fdbf976 5303 kvm_rip_write(vcpu, regs->rip);
91586a3b 5304 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5305
b4f14abd
JK		 5306 vcpu->arch.exception.pending = false;
5307
b6c7a5dc
HB		 5308 return 0;
5309}
5310
b6c7a5dc
HB		 5311void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5312{
5313 struct kvm_segment cs;
5314
3e6e0aab 5315 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5316 *db = cs.db;
5317 *l = cs.l;
5318}
5319EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5320
5321int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5322 struct kvm_sregs *sregs)
5323{
89a27f4d 5324 struct desc_ptr dt;
b6c7a5dc 5325
3e6e0aab
GT		 5326 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5327 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5328 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5329 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5330 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5331 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5332
3e6e0aab
GT		 5333 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5334 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5335
5336 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5337 sregs->idt.limit = dt.size;
5338 sregs->idt.base = dt.address;
b6c7a5dc 5339 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5340 sregs->gdt.limit = dt.size;
5341 sregs->gdt.base = dt.address;
b6c7a5dc 5342
4d4ec087 5343 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5344 sregs->cr2 = vcpu->arch.cr2;
5345 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5346 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5347 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5348 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5349 sregs->apic_base = kvm_get_apic_base(vcpu);
5350
923c61bb 5351 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5352
36752c9b 5353 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5354 set_bit(vcpu->arch.interrupt.nr,
5355 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5356
b6c7a5dc
HB		 5357 return 0;
5358}
5359
62d9f0db
MT		 5360int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5361 struct kvm_mp_state *mp_state)
5362{
62d9f0db 5363 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5364 return 0;
5365}
5366
5367int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5368 struct kvm_mp_state *mp_state)
5369{
62d9f0db 5370 vcpu->arch.mp_state = mp_state->mp_state;
62d9f0db
MT		 5371 return 0;
5372}
5373
e269fb21
JK		 5374int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5375 bool has_error_code, u32 error_code)
b6c7a5dc 5376{
4d2179e1 5377 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5378 int ret;
e01c2426 5379
8ec4722d 5380 init_emulate_ctxt(vcpu);
c697518a 5381
9aabc88f 5382 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5383 tss_selector, reason, has_error_code,
5384 error_code);
c697518a 5385
c697518a 5386 if (ret)
19d04437 5387 return EMULATE_FAIL;
37817f29 5388
4d2179e1 5389 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5390 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437
GN		 5391 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
5392 return EMULATE_DONE;
37817f29
IE		 5393}
5394EXPORT_SYMBOL_GPL(kvm_task_switch);
5395
b6c7a5dc
HB		 5396int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5397 struct kvm_sregs *sregs)
5398{
5399 int mmu_reset_needed = 0;
923c61bb 5400 int pending_vec, max_bits;
89a27f4d 5401 struct desc_ptr dt;
b6c7a5dc 5402
89a27f4d
GN		 5403 dt.size = sregs->idt.limit;
5404 dt.address = sregs->idt.base;
b6c7a5dc 5405 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5406 dt.size = sregs->gdt.limit;
5407 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5408 kvm_x86_ops->set_gdt(vcpu, &dt);
5409
ad312c7c
ZX		 5410 vcpu->arch.cr2 = sregs->cr2;
5411 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5412 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5413
2d3ad1f4 5414 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5415
f6801dff 5416 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5417 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5418 kvm_set_apic_base(vcpu, sregs->apic_base);
5419
4d4ec087 5420 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5421 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5422 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5423
fc78f519 5424 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5425 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5426 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ff03a073 5427 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
7c93be44
MT		 5428 mmu_reset_needed = 1;
5429 }
b6c7a5dc
HB		 5430
5431 if (mmu_reset_needed)
5432 kvm_mmu_reset_context(vcpu);
5433
923c61bb
GN		 5434 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5435 pending_vec = find_first_bit(
5436 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5437 if (pending_vec < max_bits) {
66fd3f7f 5438 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5439 pr_debug("Set back pending irq %d\n", pending_vec);
5440 if (irqchip_in_kernel(vcpu->kvm))
5441 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5442 }
5443
3e6e0aab
GT		 5444 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5445 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5446 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5447 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5448 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5449 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5450
3e6e0aab
GT		 5451 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5452 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5453
5f0269f5
ME		 5454 update_cr8_intercept(vcpu);
5455
9c3e4aab 5456 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5457 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5458 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5459 !is_protmode(vcpu))
9c3e4aab
MT		 5460 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5461
b6c7a5dc
HB		 5462 return 0;
5463}
5464
d0bfb940
JK		 5465int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5466 struct kvm_guest_debug *dbg)
b6c7a5dc 5467{
355be0b9 5468 unsigned long rflags;
ae675ef0 5469 int i, r;
b6c7a5dc 5470
4f926bf2
JK		 5471 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5472 r = -EBUSY;
5473 if (vcpu->arch.exception.pending)
2122ff5e 5474 goto out;
4f926bf2
JK		 5475 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5476 kvm_queue_exception(vcpu, DB_VECTOR);
5477 else
5478 kvm_queue_exception(vcpu, BP_VECTOR);
5479 }
5480
91586a3b
JK		 5481 /*
5482 * Read rflags as long as potentially injected trace flags are still
5483 * filtered out.
5484 */
5485 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5486
5487 vcpu->guest_debug = dbg->control;
5488 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5489 vcpu->guest_debug = 0;
5490
5491 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5492 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5493 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5494 vcpu->arch.switch_db_regs =
5495 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5496 } else {
5497 for (i = 0; i < KVM_NR_DB_REGS; i++)
5498 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5499 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5500 }
5501
f92653ee
JK		 5502 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5503 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5504 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5505
91586a3b
JK		 5506 /*
5507 * Trigger an rflags update that will inject or remove the trace
5508 * flags.
5509 */
5510 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5511
355be0b9 5512 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5513
4f926bf2 5514 r = 0;
d0bfb940 5515
2122ff5e 5516out:
b6c7a5dc
HB		 5517
5518 return r;
5519}
5520
8b006791
ZX		 5521/*
5522 * Translate a guest virtual address to a guest physical address.
5523 */
5524int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5525 struct kvm_translation *tr)
5526{
5527 unsigned long vaddr = tr->linear_address;
5528 gpa_t gpa;
f656ce01 5529 int idx;
8b006791 5530
f656ce01 5531 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5532 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5533 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5534 tr->physical_address = gpa;
5535 tr->valid = gpa != UNMAPPED_GVA;
5536 tr->writeable = 1;
5537 tr->usermode = 0;
8b006791
ZX		 5538
5539 return 0;
5540}
5541
d0752060
HB		 5542int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5543{
98918833
SY		 5544 struct i387_fxsave_struct *fxsave =
5545 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5546
d0752060
HB		 5547 memcpy(fpu->fpr, fxsave->st_space, 128);
5548 fpu->fcw = fxsave->cwd;
5549 fpu->fsw = fxsave->swd;
5550 fpu->ftwx = fxsave->twd;
5551 fpu->last_opcode = fxsave->fop;
5552 fpu->last_ip = fxsave->rip;
5553 fpu->last_dp = fxsave->rdp;
5554 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5555
d0752060
HB		 5556 return 0;
5557}
5558
5559int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5560{
98918833
SY		 5561 struct i387_fxsave_struct *fxsave =
5562 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5563
d0752060
HB		 5564 memcpy(fxsave->st_space, fpu->fpr, 128);
5565 fxsave->cwd = fpu->fcw;
5566 fxsave->swd = fpu->fsw;
5567 fxsave->twd = fpu->ftwx;
5568 fxsave->fop = fpu->last_opcode;
5569 fxsave->rip = fpu->last_ip;
5570 fxsave->rdp = fpu->last_dp;
5571 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5572
d0752060
HB		 5573 return 0;
5574}
5575
10ab25cd 5576int fx_init(struct kvm_vcpu *vcpu)
d0752060 5577{
10ab25cd
JK		 5578 int err;
5579
5580 err = fpu_alloc(&vcpu->arch.guest_fpu);
5581 if (err)
5582 return err;
5583
98918833 5584 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5585
2acf923e
DC		 5586 /*
5587 * Ensure guest xcr0 is valid for loading
5588 */
5589 vcpu->arch.xcr0 = XSTATE_FP;
5590
ad312c7c 5591 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5592
5593 return 0;
d0752060
HB		 5594}
5595EXPORT_SYMBOL_GPL(fx_init);
5596
98918833
SY		 5597static void fx_free(struct kvm_vcpu *vcpu)
5598{
5599 fpu_free(&vcpu->arch.guest_fpu);
5600}
5601
d0752060
HB		 5602void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5603{
2608d7a1 5604 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5605 return;
5606
2acf923e
DC		 5607 /*
5608 * Restore all possible states in the guest,
5609 * and assume host would use all available bits.
5610 * Guest xcr0 would be loaded later.
5611 */
5612 kvm_put_guest_xcr0(vcpu);
d0752060 5613 vcpu->guest_fpu_loaded = 1;
7cf30855 5614 unlazy_fpu(current);
98918833 5615 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5616 trace_kvm_fpu(1);
d0752060 5617}
d0752060
HB		 5618
5619void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5620{
2acf923e
DC		 5621 kvm_put_guest_xcr0(vcpu);
5622
d0752060
HB		 5623 if (!vcpu->guest_fpu_loaded)
5624 return;
5625
5626 vcpu->guest_fpu_loaded = 0;
98918833 5627 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5628 ++vcpu->stat.fpu_reload;
a8eeb04a 5629 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5630 trace_kvm_fpu(0);
d0752060 5631}
e9b11c17
ZX		 5632
5633void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5634{
7f1ea208
JR		 5635 if (vcpu->arch.time_page) {
5636 kvm_release_page_dirty(vcpu->arch.time_page);
5637 vcpu->arch.time_page = NULL;
5638 }
5639
f5f48ee1 5640 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5641 fx_free(vcpu);
e9b11c17
ZX		 5642 kvm_x86_ops->vcpu_free(vcpu);
5643}
5644
5645struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5646 unsigned int id)
5647{
6755bae8
ZA		 5648 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5649 printk_once(KERN_WARNING
5650 "kvm: SMP vm created on host with unstable TSC; "
5651 "guest TSC will not be reliable\n");
26e5215f
AK		 5652 return kvm_x86_ops->vcpu_create(kvm, id);
5653}
e9b11c17 5654
26e5215f
AK		 5655int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5656{
5657 int r;
e9b11c17 5658
0bed3b56 5659 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5660 vcpu_load(vcpu);
5661 r = kvm_arch_vcpu_reset(vcpu);
5662 if (r == 0)
5663 r = kvm_mmu_setup(vcpu);
5664 vcpu_put(vcpu);
5665 if (r < 0)
5666 goto free_vcpu;
5667
26e5215f 5668 return 0;
e9b11c17
ZX		 5669free_vcpu:
5670 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5671 return r;
e9b11c17
ZX		 5672}
5673
d40ccc62 5674void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5675{
5676 vcpu_load(vcpu);
5677 kvm_mmu_unload(vcpu);
5678 vcpu_put(vcpu);
5679
98918833 5680 fx_free(vcpu);
e9b11c17
ZX		 5681 kvm_x86_ops->vcpu_free(vcpu);
5682}
5683
5684int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5685{
448fa4a9
JK		 5686 vcpu->arch.nmi_pending = false;
5687 vcpu->arch.nmi_injected = false;
5688
42dbaa5a
JK		 5689 vcpu->arch.switch_db_regs = 0;
5690 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5691 vcpu->arch.dr6 = DR6_FIXED_1;
5692 vcpu->arch.dr7 = DR7_FIXED_1;
5693
e9b11c17
ZX		 5694 return kvm_x86_ops->vcpu_reset(vcpu);
5695}
5696
10474ae8 5697int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5698{
ca84d1a2
ZA		 5699 struct kvm *kvm;
5700 struct kvm_vcpu *vcpu;
5701 int i;
5702
18863bdd 5703 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5704 list_for_each_entry(kvm, &vm_list, vm_list)
5705 kvm_for_each_vcpu(i, vcpu, kvm)
5706 if (vcpu->cpu == smp_processor_id())
5707 kvm_request_guest_time_update(vcpu);
10474ae8 5708 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5709}
5710
5711void kvm_arch_hardware_disable(void *garbage)
5712{
5713 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5714 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5715}
5716
5717int kvm_arch_hardware_setup(void)
5718{
5719 return kvm_x86_ops->hardware_setup();
5720}
5721
5722void kvm_arch_hardware_unsetup(void)
5723{
5724 kvm_x86_ops->hardware_unsetup();
5725}
5726
5727void kvm_arch_check_processor_compat(void *rtn)
5728{
5729 kvm_x86_ops->check_processor_compatibility(rtn);
5730}
5731
5732int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5733{
5734 struct page *page;
5735 struct kvm *kvm;
5736 int r;
5737
5738 BUG_ON(vcpu->kvm == NULL);
5739 kvm = vcpu->kvm;
5740
9aabc88f 5741 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5742 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5743 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5744 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5745 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5746 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5747 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5748 else
a4535290 5749 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5750
5751 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5752 if (!page) {
5753 r = -ENOMEM;
5754 goto fail;
5755 }
ad312c7c 5756 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5757
5758 r = kvm_mmu_create(vcpu);
5759 if (r < 0)
5760 goto fail_free_pio_data;
5761
5762 if (irqchip_in_kernel(kvm)) {
5763 r = kvm_create_lapic(vcpu);
5764 if (r < 0)
5765 goto fail_mmu_destroy;
5766 }
5767
890ca9ae
HY		 5768 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5769 GFP_KERNEL);
5770 if (!vcpu->arch.mce_banks) {
5771 r = -ENOMEM;
443c39bc 5772 goto fail_free_lapic;
890ca9ae
HY		 5773 }
5774 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5775
f5f48ee1
SY		 5776 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5777 goto fail_free_mce_banks;
5778
e9b11c17 5779 return 0;
f5f48ee1
SY		 5780fail_free_mce_banks:
5781 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5782fail_free_lapic:
5783 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5784fail_mmu_destroy:
5785 kvm_mmu_destroy(vcpu);
5786fail_free_pio_data:
ad312c7c 5787 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5788fail:
5789 return r;
5790}
5791
5792void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5793{
f656ce01
MT		 5794 int idx;
5795
36cb93fd 5796 kfree(vcpu->arch.mce_banks);
e9b11c17 5797 kvm_free_lapic(vcpu);
f656ce01 5798 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5799 kvm_mmu_destroy(vcpu);
f656ce01 5800 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5801 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5802}
d19a9cd2
ZX		 5803
5804struct kvm *kvm_arch_create_vm(void)
5805{
5806 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5807
5808 if (!kvm)
5809 return ERR_PTR(-ENOMEM);
5810
f05e70ac 5811 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5812 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5813
5550af4d
SY		 5814 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5815 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5816
99e3e30a
ZA		 5817 spin_lock_init(&kvm->arch.tsc_write_lock);
5818
d19a9cd2
ZX		 5819 return kvm;
5820}
5821
5822static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5823{
5824 vcpu_load(vcpu);
5825 kvm_mmu_unload(vcpu);
5826 vcpu_put(vcpu);
5827}
5828
5829static void kvm_free_vcpus(struct kvm *kvm)
5830{
5831 unsigned int i;
988a2cae 5832 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5833
5834 /*
5835 * Unpin any mmu pages first.
5836 */
988a2cae
GN		 5837 kvm_for_each_vcpu(i, vcpu, kvm)
5838 kvm_unload_vcpu_mmu(vcpu);
5839 kvm_for_each_vcpu(i, vcpu, kvm)
5840 kvm_arch_vcpu_free(vcpu);
5841
5842 mutex_lock(&kvm->lock);
5843 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5844 kvm->vcpus[i] = NULL;
d19a9cd2 5845
988a2cae
GN		 5846 atomic_set(&kvm->online_vcpus, 0);
5847 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5848}
5849
ad8ba2cd
SY		 5850void kvm_arch_sync_events(struct kvm *kvm)
5851{
ba4cef31 5852 kvm_free_all_assigned_devices(kvm);
aea924f6 5853 kvm_free_pit(kvm);
ad8ba2cd
SY		 5854}
5855
d19a9cd2
ZX		 5856void kvm_arch_destroy_vm(struct kvm *kvm)
5857{
6eb55818 5858 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5859 kfree(kvm->arch.vpic);
5860 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5861 kvm_free_vcpus(kvm);
5862 kvm_free_physmem(kvm);
3d45830c
AK		 5863 if (kvm->arch.apic_access_page)
5864 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5865 if (kvm->arch.ept_identity_pagetable)
5866 put_page(kvm->arch.ept_identity_pagetable);
64749204 5867 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5868 kfree(kvm);
5869}
0de10343 5870
f7784b8e
MT		 5871int kvm_arch_prepare_memory_region(struct kvm *kvm,
5872 struct kvm_memory_slot *memslot,
0de10343 5873 struct kvm_memory_slot old,
f7784b8e 5874 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5875 int user_alloc)
5876{
f7784b8e 5877 int npages = memslot->npages;
7ac77099
AK		 5878 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5879
5880 /* Prevent internal slot pages from being moved by fork()/COW. */
5881 if (memslot->id >= KVM_MEMORY_SLOTS)
5882 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5883
5884 /*To keep backward compatibility with older userspace,
5885 *x86 needs to hanlde !user_alloc case.
5886 */
5887 if (!user_alloc) {
5888 if (npages && !old.rmap) {
604b38ac
AA		 5889 unsigned long userspace_addr;
5890
72dc67a6 5891 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5892 userspace_addr = do_mmap(NULL, 0,
5893 npages * PAGE_SIZE,
5894 PROT_READ | PROT_WRITE,
7ac77099 5895 map_flags,
604b38ac 5896 0);
72dc67a6 5897 up_write(&current->mm->mmap_sem);
0de10343 5898
604b38ac
AA		 5899 if (IS_ERR((void *)userspace_addr))
5900 return PTR_ERR((void *)userspace_addr);
5901
604b38ac 5902 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5903 }
5904 }
5905
f7784b8e
MT		 5906
5907 return 0;
5908}
5909
5910void kvm_arch_commit_memory_region(struct kvm *kvm,
5911 struct kvm_userspace_memory_region *mem,
5912 struct kvm_memory_slot old,
5913 int user_alloc)
5914{
5915
5916 int npages = mem->memory_size >> PAGE_SHIFT;
5917
5918 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5919 int ret;
5920
5921 down_write(&current->mm->mmap_sem);
5922 ret = do_munmap(current->mm, old.userspace_addr,
5923 old.npages * PAGE_SIZE);
5924 up_write(&current->mm->mmap_sem);
5925 if (ret < 0)
5926 printk(KERN_WARNING
5927 "kvm_vm_ioctl_set_memory_region: "
5928 "failed to munmap memory\n");
5929 }
5930
7c8a83b7 5931 spin_lock(&kvm->mmu_lock);
f05e70ac 5932 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5933 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5934 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5935 }
5936
5937 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5938 spin_unlock(&kvm->mmu_lock);
0de10343 5939}
1d737c8a 5940
34d4cb8f
MT		 5941void kvm_arch_flush_shadow(struct kvm *kvm)
5942{
5943 kvm_mmu_zap_all(kvm);
8986ecc0 5944 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5945}
5946
1d737c8a
ZX		 5947int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5948{
a4535290 5949 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5950 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5951 || vcpu->arch.nmi_pending ||
5952 (kvm_arch_interrupt_allowed(vcpu) &&
5953 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5954}
5736199a 5955
5736199a
ZX		 5956void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5957{
32f88400
MT		 5958 int me;
5959 int cpu = vcpu->cpu;
5736199a
ZX		 5960
5961 if (waitqueue_active(&vcpu->wq)) {
5962 wake_up_interruptible(&vcpu->wq);
5963 ++vcpu->stat.halt_wakeup;
5964 }
32f88400
MT		 5965
5966 me = get_cpu();
5967 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5968 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5969 smp_send_reschedule(cpu);
e9571ed5 5970 put_cpu();
5736199a 5971}
78646121
GN		 5972
5973int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5974{
5975 return kvm_x86_ops->interrupt_allowed(vcpu);
5976}
229456fc 5977
f92653ee
JK		 5978bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5979{
5980 unsigned long current_rip = kvm_rip_read(vcpu) +
5981 get_segment_base(vcpu, VCPU_SREG_CS);
5982
5983 return current_rip == linear_rip;
5984}
5985EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5986
94fe45da
JK		 5987unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5988{
5989 unsigned long rflags;
5990
5991 rflags = kvm_x86_ops->get_rflags(vcpu);
5992 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5993 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5994 return rflags;
5995}
5996EXPORT_SYMBOL_GPL(kvm_get_rflags);
5997
5998void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5999{
6000 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6001 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6002 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 6003 kvm_x86_ops->set_rflags(vcpu, rflags);
6004}
6005EXPORT_SYMBOL_GPL(kvm_set_rflags);
6006
229456fc
MT		 6007EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6008EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6009EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6010EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6011EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6012EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6013EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6014EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6015EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6016EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6017EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6018EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)