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KVM: MMU: Introduce init_kvm_nested_mmu()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
221d059d 9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
1d5f066e 58#include <asm/pvclock.h>
217fc9cf 59#include <asm/div64.h>
043405e1 60
313a3dc7 61#define MAX_IO_MSRS 256
a03490ed
CO		 62#define CR0_RESERVED_BITS \
63 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
64 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
65 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
66#define CR4_RESERVED_BITS \
67 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
68 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
69 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 70 | X86_CR4_OSXSAVE \
a03490ed
CO		 71 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
72
73#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 74
75#define KVM_MAX_MCE_BANKS 32
76#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
84#else
85static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
86#endif
313a3dc7 87
ba1389b7
AK		 88#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
89#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 90
cb142eb7 91static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 92static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
93 struct kvm_cpuid_entry2 __user *entries);
94
97896d04 95struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 96EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 97
ed85c068
AP		 98int ignore_msrs = 0;
99module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
100
18863bdd
AK		 101#define KVM_NR_SHARED_MSRS 16
102
103struct kvm_shared_msrs_global {
104 int nr;
2bf78fa7 105 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 106};
107
108struct kvm_shared_msrs {
109 struct user_return_notifier urn;
110 bool registered;
2bf78fa7
SY		 111 struct kvm_shared_msr_values {
112 u64 host;
113 u64 curr;
114 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 115};
116
117static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
118static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
119
417bc304 120struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 121 { "pf_fixed", VCPU_STAT(pf_fixed) },
122 { "pf_guest", VCPU_STAT(pf_guest) },
123 { "tlb_flush", VCPU_STAT(tlb_flush) },
124 { "invlpg", VCPU_STAT(invlpg) },
125 { "exits", VCPU_STAT(exits) },
126 { "io_exits", VCPU_STAT(io_exits) },
127 { "mmio_exits", VCPU_STAT(mmio_exits) },
128 { "signal_exits", VCPU_STAT(signal_exits) },
129 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 130 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 131 { "halt_exits", VCPU_STAT(halt_exits) },
132 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 133 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 134 { "request_irq", VCPU_STAT(request_irq_exits) },
135 { "irq_exits", VCPU_STAT(irq_exits) },
136 { "host_state_reload", VCPU_STAT(host_state_reload) },
137 { "efer_reload", VCPU_STAT(efer_reload) },
138 { "fpu_reload", VCPU_STAT(fpu_reload) },
139 { "insn_emulation", VCPU_STAT(insn_emulation) },
140 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 141 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 142 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 143 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
144 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
145 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
146 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
147 { "mmu_flooded", VM_STAT(mmu_flooded) },
148 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 149 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 150 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 151 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 152 { "largepages", VM_STAT(lpages) },
417bc304
HB		 153 { NULL }
154};
155
2acf923e
DC		 156u64 __read_mostly host_xcr0;
157
158static inline u32 bit(int bitno)
159{
160 return 1 << (bitno & 31);
161}
162
18863bdd
AK		 163static void kvm_on_user_return(struct user_return_notifier *urn)
164{
165 unsigned slot;
18863bdd
AK		 166 struct kvm_shared_msrs *locals
167 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 168 struct kvm_shared_msr_values *values;
18863bdd
AK		 169
170 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 171 values = &locals->values[slot];
172 if (values->host != values->curr) {
173 wrmsrl(shared_msrs_global.msrs[slot], values->host);
174 values->curr = values->host;
18863bdd
AK		 175 }
176 }
177 locals->registered = false;
178 user_return_notifier_unregister(urn);
179}
180
2bf78fa7 181static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 182{
2bf78fa7 183 struct kvm_shared_msrs *smsr;
18863bdd
AK		 184 u64 value;
185
2bf78fa7
SY		 186 smsr = &__get_cpu_var(shared_msrs);
187 /* only read, and nobody should modify it at this time,
188 * so don't need lock */
189 if (slot >= shared_msrs_global.nr) {
190 printk(KERN_ERR "kvm: invalid MSR slot!");
191 return;
192 }
193 rdmsrl_safe(msr, &value);
194 smsr->values[slot].host = value;
195 smsr->values[slot].curr = value;
196}
197
198void kvm_define_shared_msr(unsigned slot, u32 msr)
199{
18863bdd
AK		 200 if (slot >= shared_msrs_global.nr)
201 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 202 shared_msrs_global.msrs[slot] = msr;
203 /* we need ensured the shared_msr_global have been updated */
204 smp_wmb();
18863bdd
AK		 205}
206EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
207
208static void kvm_shared_msr_cpu_online(void)
209{
210 unsigned i;
18863bdd
AK		 211
212 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 213 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 214}
215
d5696725 216void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 217{
218 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
219
2bf78fa7 220 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 221 return;
2bf78fa7
SY		 222 smsr->values[slot].curr = value;
223 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 224 if (!smsr->registered) {
225 smsr->urn.on_user_return = kvm_on_user_return;
226 user_return_notifier_register(&smsr->urn);
227 smsr->registered = true;
228 }
229}
230EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
231
3548bab5
AK		 232static void drop_user_return_notifiers(void *ignore)
233{
234 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
235
236 if (smsr->registered)
237 kvm_on_user_return(&smsr->urn);
238}
239
6866b83e
CO		 240u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
241{
242 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e 244 else
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e
CO		 246}
247EXPORT_SYMBOL_GPL(kvm_get_apic_base);
248
249void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
250{
251 /* TODO: reserve bits check */
252 if (irqchip_in_kernel(vcpu->kvm))
253 kvm_lapic_set_base(vcpu, data);
254 else
ad312c7c 255 vcpu->arch.apic_base = data;
6866b83e
CO		 256}
257EXPORT_SYMBOL_GPL(kvm_set_apic_base);
258
3fd28fce
ED		 259#define EXCPT_BENIGN 0
260#define EXCPT_CONTRIBUTORY 1
261#define EXCPT_PF 2
262
263static int exception_class(int vector)
264{
265 switch (vector) {
266 case PF_VECTOR:
267 return EXCPT_PF;
268 case DE_VECTOR:
269 case TS_VECTOR:
270 case NP_VECTOR:
271 case SS_VECTOR:
272 case GP_VECTOR:
273 return EXCPT_CONTRIBUTORY;
274 default:
275 break;
276 }
277 return EXCPT_BENIGN;
278}
279
280static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 281 unsigned nr, bool has_error, u32 error_code,
282 bool reinject)
3fd28fce
ED		 283{
284 u32 prev_nr;
285 int class1, class2;
286
287 if (!vcpu->arch.exception.pending) {
288 queue:
289 vcpu->arch.exception.pending = true;
290 vcpu->arch.exception.has_error_code = has_error;
291 vcpu->arch.exception.nr = nr;
292 vcpu->arch.exception.error_code = error_code;
3f0fd292 293 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 294 return;
295 }
296
297 /* to check exception */
298 prev_nr = vcpu->arch.exception.nr;
299 if (prev_nr == DF_VECTOR) {
300 /* triple fault -> shutdown */
a8eeb04a 301 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 302 return;
303 }
304 class1 = exception_class(prev_nr);
305 class2 = exception_class(nr);
306 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
307 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
308 /* generate double fault per SDM Table 5-5 */
309 vcpu->arch.exception.pending = true;
310 vcpu->arch.exception.has_error_code = true;
311 vcpu->arch.exception.nr = DF_VECTOR;
312 vcpu->arch.exception.error_code = 0;
313 } else
314 /* replace previous exception with a new one in a hope
315 that instruction re-execution will regenerate lost
316 exception */
317 goto queue;
318}
319
298101da
AK		 320void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
321{
ce7ddec4 322 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 323}
324EXPORT_SYMBOL_GPL(kvm_queue_exception);
325
ce7ddec4
JR		 326void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
327{
328 kvm_multiple_exception(vcpu, nr, false, 0, true);
329}
330EXPORT_SYMBOL_GPL(kvm_requeue_exception);
331
8df25a32 332void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
c3c91fee 333{
8df25a32
JR		 334 unsigned error_code = vcpu->arch.fault.error_code;
335
c3c91fee 336 ++vcpu->stat.pf_guest;
8df25a32 337 vcpu->arch.cr2 = vcpu->arch.fault.address;
c3c91fee
AK		 338 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
339}
340
3419ffc8
SY		 341void kvm_inject_nmi(struct kvm_vcpu *vcpu)
342{
343 vcpu->arch.nmi_pending = 1;
344}
345EXPORT_SYMBOL_GPL(kvm_inject_nmi);
346
298101da
AK		 347void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
348{
ce7ddec4 349 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 350}
351EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
352
ce7ddec4
JR		 353void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
354{
355 kvm_multiple_exception(vcpu, nr, true, error_code, true);
356}
357EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
358
0a79b009
AK		 359/*
360 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
361 * a #GP and return false.
362 */
363bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 364{
0a79b009
AK		 365 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
366 return true;
367 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
368 return false;
298101da 369}
0a79b009 370EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 371
ec92fe44
JR		 372/*
373 * This function will be used to read from the physical memory of the currently
374 * running guest. The difference to kvm_read_guest_page is that this function
375 * can read from guest physical or from the guest's guest physical memory.
376 */
377int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
378 gfn_t ngfn, void *data, int offset, int len,
379 u32 access)
380{
381 gfn_t real_gfn;
382 gpa_t ngpa;
383
384 ngpa = gfn_to_gpa(ngfn);
385 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
386 if (real_gfn == UNMAPPED_GVA)
387 return -EFAULT;
388
389 real_gfn = gpa_to_gfn(real_gfn);
390
391 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
392}
393EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
394
3d06b8bf
JR		 395int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
396 void *data, int offset, int len, u32 access)
397{
398 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
399 data, offset, len, access);
400}
401
a03490ed
CO		 402/*
403 * Load the pae pdptrs. Return true is they are all valid.
404 */
405int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
406{
407 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
408 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
409 int i;
410 int ret;
ad312c7c 411 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 412
3d06b8bf
JR		 413 ret = kvm_read_nested_guest_page(vcpu, pdpt_gfn, pdpte,
414 offset * sizeof(u64), sizeof(pdpte),
415 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 416 if (ret < 0) {
417 ret = 0;
418 goto out;
419 }
420 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 421 if (is_present_gpte(pdpte[i]) &&
20c466b5 422 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 423 ret = 0;
424 goto out;
425 }
426 }
427 ret = 1;
428
ad312c7c 429 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 430 __set_bit(VCPU_EXREG_PDPTR,
431 (unsigned long *)&vcpu->arch.regs_avail);
432 __set_bit(VCPU_EXREG_PDPTR,
433 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 434out:
a03490ed
CO		 435
436 return ret;
437}
cc4b6871 438EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 439
d835dfec
AK		 440static bool pdptrs_changed(struct kvm_vcpu *vcpu)
441{
ad312c7c 442 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec 443 bool changed = true;
3d06b8bf
JR		 444 int offset;
445 gfn_t gfn;
d835dfec
AK		 446 int r;
447
448 if (is_long_mode(vcpu) || !is_pae(vcpu))
449 return false;
450
6de4f3ad
AK		 451 if (!test_bit(VCPU_EXREG_PDPTR,
452 (unsigned long *)&vcpu->arch.regs_avail))
453 return true;
454
3d06b8bf
JR		 455 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
456 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
457 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
458 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 459 if (r < 0)
460 goto out;
ad312c7c 461 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 462out:
d835dfec
AK		 463
464 return changed;
465}
466
49a9b07e 467int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 468{
aad82703
SY		 469 unsigned long old_cr0 = kvm_read_cr0(vcpu);
470 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
471 X86_CR0_CD | X86_CR0_NW;
472
f9a48e6a
AK		 473 cr0 |= X86_CR0_ET;
474
ab344828 475#ifdef CONFIG_X86_64
0f12244f
GN		 476 if (cr0 & 0xffffffff00000000UL)
477 return 1;
ab344828
GN		 478#endif
479
480 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 481
0f12244f
GN		 482 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
483 return 1;
a03490ed 484
0f12244f
GN		 485 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
486 return 1;
a03490ed
CO		 487
488 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
489#ifdef CONFIG_X86_64
f6801dff 490 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 491 int cs_db, cs_l;
492
0f12244f
GN		 493 if (!is_pae(vcpu))
494 return 1;
a03490ed 495 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 496 if (cs_l)
497 return 1;
a03490ed
CO		 498 } else
499#endif
0f12244f
GN		 500 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3))
501 return 1;
a03490ed
CO		 502 }
503
504 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 505
aad82703
SY		 506 if ((cr0 ^ old_cr0) & update_bits)
507 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 508 return 0;
509}
2d3ad1f4 510EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 511
2d3ad1f4 512void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 513{
49a9b07e 514 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 515}
2d3ad1f4 516EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 517
2acf923e
DC		 518int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
519{
520 u64 xcr0;
521
522 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
523 if (index != XCR_XFEATURE_ENABLED_MASK)
524 return 1;
525 xcr0 = xcr;
526 if (kvm_x86_ops->get_cpl(vcpu) != 0)
527 return 1;
528 if (!(xcr0 & XSTATE_FP))
529 return 1;
530 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
531 return 1;
532 if (xcr0 & ~host_xcr0)
533 return 1;
534 vcpu->arch.xcr0 = xcr0;
535 vcpu->guest_xcr0_loaded = 0;
536 return 0;
537}
538
539int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
540{
541 if (__kvm_set_xcr(vcpu, index, xcr)) {
542 kvm_inject_gp(vcpu, 0);
543 return 1;
544 }
545 return 0;
546}
547EXPORT_SYMBOL_GPL(kvm_set_xcr);
548
549static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
550{
551 struct kvm_cpuid_entry2 *best;
552
553 best = kvm_find_cpuid_entry(vcpu, 1, 0);
554 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
555}
556
557static void update_cpuid(struct kvm_vcpu *vcpu)
558{
559 struct kvm_cpuid_entry2 *best;
560
561 best = kvm_find_cpuid_entry(vcpu, 1, 0);
562 if (!best)
563 return;
564
565 /* Update OSXSAVE bit */
566 if (cpu_has_xsave && best->function == 0x1) {
567 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
568 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
569 best->ecx |= bit(X86_FEATURE_OSXSAVE);
570 }
571}
572
a83b29c6 573int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 574{
fc78f519 575 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 576 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
577
0f12244f
GN		 578 if (cr4 & CR4_RESERVED_BITS)
579 return 1;
a03490ed 580
2acf923e
DC		 581 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
582 return 1;
583
a03490ed 584 if (is_long_mode(vcpu)) {
0f12244f
GN		 585 if (!(cr4 & X86_CR4_PAE))
586 return 1;
a2edf57f
AK		 587 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
588 && ((cr4 ^ old_cr4) & pdptr_bits)
0f12244f
GN		 589 && !load_pdptrs(vcpu, vcpu->arch.cr3))
590 return 1;
591
592 if (cr4 & X86_CR4_VMXE)
593 return 1;
a03490ed 594
a03490ed 595 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 596
aad82703
SY		 597 if ((cr4 ^ old_cr4) & pdptr_bits)
598 kvm_mmu_reset_context(vcpu);
0f12244f 599
2acf923e
DC		 600 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
601 update_cpuid(vcpu);
602
0f12244f
GN		 603 return 0;
604}
2d3ad1f4 605EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 606
2390218b 607int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 608{
ad312c7c 609 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 610 kvm_mmu_sync_roots(vcpu);
d835dfec 611 kvm_mmu_flush_tlb(vcpu);
0f12244f 612 return 0;
d835dfec
AK		 613 }
614
a03490ed 615 if (is_long_mode(vcpu)) {
0f12244f
GN		 616 if (cr3 & CR3_L_MODE_RESERVED_BITS)
617 return 1;
a03490ed
CO		 618 } else {
619 if (is_pae(vcpu)) {
0f12244f
GN		 620 if (cr3 & CR3_PAE_RESERVED_BITS)
621 return 1;
622 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3))
623 return 1;
a03490ed
CO		 624 }
625 /*
626 * We don't check reserved bits in nonpae mode, because
627 * this isn't enforced, and VMware depends on this.
628 */
629 }
630
a03490ed
CO		 631 /*
632 * Does the new cr3 value map to physical memory? (Note, we
633 * catch an invalid cr3 even in real-mode, because it would
634 * cause trouble later on when we turn on paging anyway.)
635 *
636 * A real CPU would silently accept an invalid cr3 and would
637 * attempt to use it - with largely undefined (and often hard
638 * to debug) behavior on the guest side.
639 */
640 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 641 return 1;
642 vcpu->arch.cr3 = cr3;
643 vcpu->arch.mmu.new_cr3(vcpu);
644 return 0;
645}
2d3ad1f4 646EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 647
0f12244f 648int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 649{
0f12244f
GN		 650 if (cr8 & CR8_RESERVED_BITS)
651 return 1;
a03490ed
CO		 652 if (irqchip_in_kernel(vcpu->kvm))
653 kvm_lapic_set_tpr(vcpu, cr8);
654 else
ad312c7c 655 vcpu->arch.cr8 = cr8;
0f12244f
GN		 656 return 0;
657}
658
659void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
660{
661 if (__kvm_set_cr8(vcpu, cr8))
662 kvm_inject_gp(vcpu, 0);
a03490ed 663}
2d3ad1f4 664EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 665
2d3ad1f4 666unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 667{
668 if (irqchip_in_kernel(vcpu->kvm))
669 return kvm_lapic_get_cr8(vcpu);
670 else
ad312c7c 671 return vcpu->arch.cr8;
a03490ed 672}
2d3ad1f4 673EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 674
338dbc97 675static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 676{
677 switch (dr) {
678 case 0 ... 3:
679 vcpu->arch.db[dr] = val;
680 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
681 vcpu->arch.eff_db[dr] = val;
682 break;
683 case 4:
338dbc97
GN		 684 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
685 return 1; /* #UD */
020df079
GN		 686 /* fall through */
687 case 6:
338dbc97
GN		 688 if (val & 0xffffffff00000000ULL)
689 return -1; /* #GP */
020df079
GN		 690 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
691 break;
692 case 5:
338dbc97
GN		 693 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
694 return 1; /* #UD */
020df079
GN		 695 /* fall through */
696 default: /* 7 */
338dbc97
GN		 697 if (val & 0xffffffff00000000ULL)
698 return -1; /* #GP */
020df079
GN		 699 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
700 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
701 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
702 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
703 }
704 break;
705 }
706
707 return 0;
708}
338dbc97
GN		 709
710int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
711{
712 int res;
713
714 res = __kvm_set_dr(vcpu, dr, val);
715 if (res > 0)
716 kvm_queue_exception(vcpu, UD_VECTOR);
717 else if (res < 0)
718 kvm_inject_gp(vcpu, 0);
719
720 return res;
721}
020df079
GN		 722EXPORT_SYMBOL_GPL(kvm_set_dr);
723
338dbc97 724static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 725{
726 switch (dr) {
727 case 0 ... 3:
728 *val = vcpu->arch.db[dr];
729 break;
730 case 4:
338dbc97 731 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 732 return 1;
020df079
GN		 733 /* fall through */
734 case 6:
735 *val = vcpu->arch.dr6;
736 break;
737 case 5:
338dbc97 738 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 739 return 1;
020df079
GN		 740 /* fall through */
741 default: /* 7 */
742 *val = vcpu->arch.dr7;
743 break;
744 }
745
746 return 0;
747}
338dbc97
GN		 748
749int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
750{
751 if (_kvm_get_dr(vcpu, dr, val)) {
752 kvm_queue_exception(vcpu, UD_VECTOR);
753 return 1;
754 }
755 return 0;
756}
020df079
GN		 757EXPORT_SYMBOL_GPL(kvm_get_dr);
758
043405e1
CO		 759/*
760 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
761 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
762 *
763 * This list is modified at module load time to reflect the
e3267cbb
GC		 764 * capabilities of the host cpu. This capabilities test skips MSRs that are
765 * kvm-specific. Those are put in the beginning of the list.
043405e1 766 */
e3267cbb 767
11c6bffa 768#define KVM_SAVE_MSRS_BEGIN 7
043405e1 769static u32 msrs_to_save[] = {
e3267cbb 770 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 771 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 772 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 773 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1 774 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 775 MSR_STAR,
043405e1
CO		 776#ifdef CONFIG_X86_64
777 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
778#endif
e90aa41e 779 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 780};
781
782static unsigned num_msrs_to_save;
783
784static u32 emulated_msrs[] = {
785 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 786 MSR_IA32_MCG_STATUS,
787 MSR_IA32_MCG_CTL,
043405e1
CO		 788};
789
b69e8cae 790static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 791{
aad82703
SY		 792 u64 old_efer = vcpu->arch.efer;
793
b69e8cae
RJ		 794 if (efer & efer_reserved_bits)
795 return 1;
15c4a640
CO		 796
797 if (is_paging(vcpu)
b69e8cae
RJ		 798 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
799 return 1;
15c4a640 800
1b2fd70c
AG		 801 if (efer & EFER_FFXSR) {
802 struct kvm_cpuid_entry2 *feat;
803
804 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 805 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
806 return 1;
1b2fd70c
AG		 807 }
808
d8017474
AG		 809 if (efer & EFER_SVME) {
810 struct kvm_cpuid_entry2 *feat;
811
812 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 813 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
814 return 1;
d8017474
AG		 815 }
816
15c4a640 817 efer &= ~EFER_LMA;
f6801dff 818 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 819
a3d204e2
SY		 820 kvm_x86_ops->set_efer(vcpu, efer);
821
9645bb56
AK		 822 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
823 kvm_mmu_reset_context(vcpu);
b69e8cae 824
aad82703
SY		 825 /* Update reserved bits */
826 if ((efer ^ old_efer) & EFER_NX)
827 kvm_mmu_reset_context(vcpu);
828
b69e8cae 829 return 0;
15c4a640
CO		 830}
831
f2b4b7dd
JR		 832void kvm_enable_efer_bits(u64 mask)
833{
834 efer_reserved_bits &= ~mask;
835}
836EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
837
838
15c4a640
CO		 839/*
840 * Writes msr value into into the appropriate "register".
841 * Returns 0 on success, non-0 otherwise.
842 * Assumes vcpu_load() was already called.
843 */
844int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
845{
846 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
847}
848
313a3dc7
CO		 849/*
850 * Adapt set_msr() to msr_io()'s calling convention
851 */
852static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
853{
854 return kvm_set_msr(vcpu, index, *data);
855}
856
18068523
GOC		 857static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
858{
9ed3c444
AK		 859 int version;
860 int r;
50d0a0f9 861 struct pvclock_wall_clock wc;
923de3cf 862 struct timespec boot;
18068523
GOC		 863
864 if (!wall_clock)
865 return;
866
9ed3c444
AK		 867 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
868 if (r)
869 return;
870
871 if (version & 1)
872 ++version; /* first time write, random junk */
873
874 ++version;
18068523 875
18068523
GOC		 876 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
877
50d0a0f9
GH		 878 /*
879 * The guest calculates current wall clock time by adding
880 * system time (updated by kvm_write_guest_time below) to the
881 * wall clock specified here. guest system time equals host
882 * system time for us, thus we must fill in host boot time here.
883 */
923de3cf 884 getboottime(&boot);
50d0a0f9
GH		 885
886 wc.sec = boot.tv_sec;
887 wc.nsec = boot.tv_nsec;
888 wc.version = version;
18068523
GOC		 889
890 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
891
892 version++;
893 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 894}
895
50d0a0f9
GH		 896static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
897{
898 uint32_t quotient, remainder;
899
900 /* Don't try to replace with do_div(), this one calculates
901 * "(dividend << 32) / divisor" */
902 __asm__ ( "divl %4"
903 : "=a" (quotient), "=d" (remainder)
904 : "0" (0), "1" (dividend), "r" (divisor) );
905 return quotient;
906}
907
908static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
909{
910 uint64_t nsecs = 1000000000LL;
911 int32_t shift = 0;
912 uint64_t tps64;
913 uint32_t tps32;
914
915 tps64 = tsc_khz * 1000LL;
916 while (tps64 > nsecs*2) {
917 tps64 >>= 1;
918 shift--;
919 }
920
921 tps32 = (uint32_t)tps64;
922 while (tps32 <= (uint32_t)nsecs) {
923 tps32 <<= 1;
924 shift++;
925 }
926
927 hv_clock->tsc_shift = shift;
928 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
929
930 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 931 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 932 hv_clock->tsc_to_system_mul);
933}
934
759379dd
ZA		 935static inline u64 get_kernel_ns(void)
936{
937 struct timespec ts;
938
939 WARN_ON(preemptible());
940 ktime_get_ts(&ts);
941 monotonic_to_bootbased(&ts);
942 return timespec_to_ns(&ts);
943}
944
c8076604
GH		 945static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
946
8cfdc000
ZA		 947static inline int kvm_tsc_changes_freq(void)
948{
949 int cpu = get_cpu();
950 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
951 cpufreq_quick_get(cpu) != 0;
952 put_cpu();
953 return ret;
954}
955
759379dd
ZA		 956static inline u64 nsec_to_cycles(u64 nsec)
957{
217fc9cf
AK		 958 u64 ret;
959
759379dd
ZA		 960 WARN_ON(preemptible());
961 if (kvm_tsc_changes_freq())
962 printk_once(KERN_WARNING
963 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 964 ret = nsec * __get_cpu_var(cpu_tsc_khz);
965 do_div(ret, USEC_PER_SEC);
966 return ret;
759379dd
ZA		 967}
968
99e3e30a
ZA		 969void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
970{
971 struct kvm *kvm = vcpu->kvm;
f38e098f 972 u64 offset, ns, elapsed;
99e3e30a 973 unsigned long flags;
46543ba4 974 s64 sdiff;
99e3e30a
ZA		 975
976 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
977 offset = data - native_read_tsc();
759379dd 978 ns = get_kernel_ns();
f38e098f 979 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 980 sdiff = data - kvm->arch.last_tsc_write;
981 if (sdiff < 0)
982 sdiff = -sdiff;
f38e098f
ZA		 983
984 /*
46543ba4 985 * Special case: close write to TSC within 5 seconds of
f38e098f 986 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 987 * The 5 seconds is to accomodate host load / swapping as
988 * well as any reset of TSC during the boot process.
f38e098f
ZA		 989 *
990 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 991 * or make a best guest using elapsed value.
f38e098f 992 */
46543ba4
ZA		 993 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
994 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 995 if (!check_tsc_unstable()) {
996 offset = kvm->arch.last_tsc_offset;
997 pr_debug("kvm: matched tsc offset for %llu\n", data);
998 } else {
759379dd
ZA		 999 u64 delta = nsec_to_cycles(elapsed);
1000 offset += delta;
1001 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1002 }
1003 ns = kvm->arch.last_tsc_nsec;
1004 }
1005 kvm->arch.last_tsc_nsec = ns;
1006 kvm->arch.last_tsc_write = data;
1007 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1008 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1009 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1010
1011 /* Reset of TSC must disable overshoot protection below */
1012 vcpu->arch.hv_clock.tsc_timestamp = 0;
1013}
1014EXPORT_SYMBOL_GPL(kvm_write_tsc);
1015
8cfdc000 1016static int kvm_write_guest_time(struct kvm_vcpu *v)
18068523 1017{
18068523
GOC		 1018 unsigned long flags;
1019 struct kvm_vcpu_arch *vcpu = &v->arch;
1020 void *shared_kaddr;
463656c0 1021 unsigned long this_tsc_khz;
1d5f066e
ZA		 1022 s64 kernel_ns, max_kernel_ns;
1023 u64 tsc_timestamp;
18068523
GOC		 1024
1025 if ((!vcpu->time_page))
8cfdc000 1026 return 0;
50d0a0f9 1027
18068523
GOC		 1028 /* Keep irq disabled to prevent changes to the clock */
1029 local_irq_save(flags);
1d5f066e 1030 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1031 kernel_ns = get_kernel_ns();
8cfdc000 1032 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523
GOC		 1033 local_irq_restore(flags);
1034
8cfdc000
ZA		 1035 if (unlikely(this_tsc_khz == 0)) {
1036 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
1037 return 1;
1038 }
18068523 1039
1d5f066e
ZA		 1040 /*
1041 * Time as measured by the TSC may go backwards when resetting the base
1042 * tsc_timestamp. The reason for this is that the TSC resolution is
1043 * higher than the resolution of the other clock scales. Thus, many
1044 * possible measurments of the TSC correspond to one measurement of any
1045 * other clock, and so a spread of values is possible. This is not a
1046 * problem for the computation of the nanosecond clock; with TSC rates
1047 * around 1GHZ, there can only be a few cycles which correspond to one
1048 * nanosecond value, and any path through this code will inevitably
1049 * take longer than that. However, with the kernel_ns value itself,
1050 * the precision may be much lower, down to HZ granularity. If the
1051 * first sampling of TSC against kernel_ns ends in the low part of the
1052 * range, and the second in the high end of the range, we can get:
1053 *
1054 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1055 *
1056 * As the sampling errors potentially range in the thousands of cycles,
1057 * it is possible such a time value has already been observed by the
1058 * guest. To protect against this, we must compute the system time as
1059 * observed by the guest and ensure the new system time is greater.
1060 */
1061 max_kernel_ns = 0;
1062 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1063 max_kernel_ns = vcpu->last_guest_tsc -
1064 vcpu->hv_clock.tsc_timestamp;
1065 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1066 vcpu->hv_clock.tsc_to_system_mul,
1067 vcpu->hv_clock.tsc_shift);
1068 max_kernel_ns += vcpu->last_kernel_ns;
1069 }
1070
e48672fa 1071 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
8cfdc000 1072 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
e48672fa 1073 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1074 }
1075
1d5f066e
ZA		 1076 if (max_kernel_ns > kernel_ns)
1077 kernel_ns = max_kernel_ns;
1078
8cfdc000 1079 /* With all the info we got, fill in the values */
1d5f066e 1080 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1081 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1082 vcpu->last_kernel_ns = kernel_ns;
371bcf64
GC		 1083 vcpu->hv_clock.flags = 0;
1084
18068523
GOC		 1085 /*
1086 * The interface expects us to write an even number signaling that the
1087 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1088 * state, we just increase by 2 at the end.
18068523 1089 */
50d0a0f9 1090 vcpu->hv_clock.version += 2;
18068523
GOC		 1091
1092 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1093
1094 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1095 sizeof(vcpu->hv_clock));
18068523
GOC		 1096
1097 kunmap_atomic(shared_kaddr, KM_USER0);
1098
1099 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1100 return 0;
18068523
GOC		 1101}
1102
c8076604
GH		 1103static int kvm_request_guest_time_update(struct kvm_vcpu *v)
1104{
1105 struct kvm_vcpu_arch *vcpu = &v->arch;
1106
1107 if (!vcpu->time_page)
1108 return 0;
a8eeb04a 1109 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
c8076604
GH		 1110 return 1;
1111}
1112
9ba075a6
AK		 1113static bool msr_mtrr_valid(unsigned msr)
1114{
1115 switch (msr) {
1116 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1117 case MSR_MTRRfix64K_00000:
1118 case MSR_MTRRfix16K_80000:
1119 case MSR_MTRRfix16K_A0000:
1120 case MSR_MTRRfix4K_C0000:
1121 case MSR_MTRRfix4K_C8000:
1122 case MSR_MTRRfix4K_D0000:
1123 case MSR_MTRRfix4K_D8000:
1124 case MSR_MTRRfix4K_E0000:
1125 case MSR_MTRRfix4K_E8000:
1126 case MSR_MTRRfix4K_F0000:
1127 case MSR_MTRRfix4K_F8000:
1128 case MSR_MTRRdefType:
1129 case MSR_IA32_CR_PAT:
1130 return true;
1131 case 0x2f8:
1132 return true;
1133 }
1134 return false;
1135}
1136
d6289b93
MT		 1137static bool valid_pat_type(unsigned t)
1138{
1139 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1140}
1141
1142static bool valid_mtrr_type(unsigned t)
1143{
1144 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1145}
1146
1147static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1148{
1149 int i;
1150
1151 if (!msr_mtrr_valid(msr))
1152 return false;
1153
1154 if (msr == MSR_IA32_CR_PAT) {
1155 for (i = 0; i < 8; i++)
1156 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1157 return false;
1158 return true;
1159 } else if (msr == MSR_MTRRdefType) {
1160 if (data & ~0xcff)
1161 return false;
1162 return valid_mtrr_type(data & 0xff);
1163 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1164 for (i = 0; i < 8 ; i++)
1165 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1166 return false;
1167 return true;
1168 }
1169
1170 /* variable MTRRs */
1171 return valid_mtrr_type(data & 0xff);
1172}
1173
9ba075a6
AK		 1174static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1175{
0bed3b56
SY		 1176 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1177
d6289b93 1178 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1179 return 1;
1180
0bed3b56
SY		 1181 if (msr == MSR_MTRRdefType) {
1182 vcpu->arch.mtrr_state.def_type = data;
1183 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1184 } else if (msr == MSR_MTRRfix64K_00000)
1185 p[0] = data;
1186 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1187 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1188 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1189 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1190 else if (msr == MSR_IA32_CR_PAT)
1191 vcpu->arch.pat = data;
1192 else { /* Variable MTRRs */
1193 int idx, is_mtrr_mask;
1194 u64 *pt;
1195
1196 idx = (msr - 0x200) / 2;
1197 is_mtrr_mask = msr - 0x200 - 2 * idx;
1198 if (!is_mtrr_mask)
1199 pt =
1200 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1201 else
1202 pt =
1203 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1204 *pt = data;
1205 }
1206
1207 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1208 return 0;
1209}
15c4a640 1210
890ca9ae 1211static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1212{
890ca9ae
HY		 1213 u64 mcg_cap = vcpu->arch.mcg_cap;
1214 unsigned bank_num = mcg_cap & 0xff;
1215
15c4a640 1216 switch (msr) {
15c4a640 1217 case MSR_IA32_MCG_STATUS:
890ca9ae 1218 vcpu->arch.mcg_status = data;
15c4a640 1219 break;
c7ac679c 1220 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1221 if (!(mcg_cap & MCG_CTL_P))
1222 return 1;
1223 if (data != 0 && data != ~(u64)0)
1224 return -1;
1225 vcpu->arch.mcg_ctl = data;
1226 break;
1227 default:
1228 if (msr >= MSR_IA32_MC0_CTL &&
1229 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1230 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1231 /* only 0 or all 1s can be written to IA32_MCi_CTL
1232 * some Linux kernels though clear bit 10 in bank 4 to
1233 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1234 * this to avoid an uncatched #GP in the guest
1235 */
890ca9ae 1236 if ((offset & 0x3) == 0 &&
114be429 1237 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1238 return -1;
1239 vcpu->arch.mce_banks[offset] = data;
1240 break;
1241 }
1242 return 1;
1243 }
1244 return 0;
1245}
1246
ffde22ac
ES		 1247static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1248{
1249 struct kvm *kvm = vcpu->kvm;
1250 int lm = is_long_mode(vcpu);
1251 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1252 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1253 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1254 : kvm->arch.xen_hvm_config.blob_size_32;
1255 u32 page_num = data & ~PAGE_MASK;
1256 u64 page_addr = data & PAGE_MASK;
1257 u8 *page;
1258 int r;
1259
1260 r = -E2BIG;
1261 if (page_num >= blob_size)
1262 goto out;
1263 r = -ENOMEM;
1264 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1265 if (!page)
1266 goto out;
1267 r = -EFAULT;
1268 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1269 goto out_free;
1270 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1271 goto out_free;
1272 r = 0;
1273out_free:
1274 kfree(page);
1275out:
1276 return r;
1277}
1278
55cd8e5a
GN		 1279static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1280{
1281 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1282}
1283
1284static bool kvm_hv_msr_partition_wide(u32 msr)
1285{
1286 bool r = false;
1287 switch (msr) {
1288 case HV_X64_MSR_GUEST_OS_ID:
1289 case HV_X64_MSR_HYPERCALL:
1290 r = true;
1291 break;
1292 }
1293
1294 return r;
1295}
1296
1297static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1298{
1299 struct kvm *kvm = vcpu->kvm;
1300
1301 switch (msr) {
1302 case HV_X64_MSR_GUEST_OS_ID:
1303 kvm->arch.hv_guest_os_id = data;
1304 /* setting guest os id to zero disables hypercall page */
1305 if (!kvm->arch.hv_guest_os_id)
1306 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1307 break;
1308 case HV_X64_MSR_HYPERCALL: {
1309 u64 gfn;
1310 unsigned long addr;
1311 u8 instructions[4];
1312
1313 /* if guest os id is not set hypercall should remain disabled */
1314 if (!kvm->arch.hv_guest_os_id)
1315 break;
1316 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1317 kvm->arch.hv_hypercall = data;
1318 break;
1319 }
1320 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1321 addr = gfn_to_hva(kvm, gfn);
1322 if (kvm_is_error_hva(addr))
1323 return 1;
1324 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1325 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1326 if (copy_to_user((void __user *)addr, instructions, 4))
1327 return 1;
1328 kvm->arch.hv_hypercall = data;
1329 break;
1330 }
1331 default:
1332 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1333 "data 0x%llx\n", msr, data);
1334 return 1;
1335 }
1336 return 0;
1337}
1338
1339static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1340{
10388a07
GN		 1341 switch (msr) {
1342 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1343 unsigned long addr;
55cd8e5a 1344
10388a07
GN		 1345 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1346 vcpu->arch.hv_vapic = data;
1347 break;
1348 }
1349 addr = gfn_to_hva(vcpu->kvm, data >>
1350 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1351 if (kvm_is_error_hva(addr))
1352 return 1;
1353 if (clear_user((void __user *)addr, PAGE_SIZE))
1354 return 1;
1355 vcpu->arch.hv_vapic = data;
1356 break;
1357 }
1358 case HV_X64_MSR_EOI:
1359 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1360 case HV_X64_MSR_ICR:
1361 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1362 case HV_X64_MSR_TPR:
1363 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1364 default:
1365 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1366 "data 0x%llx\n", msr, data);
1367 return 1;
1368 }
1369
1370 return 0;
55cd8e5a
GN		 1371}
1372
15c4a640
CO		 1373int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1374{
1375 switch (msr) {
15c4a640 1376 case MSR_EFER:
b69e8cae 1377 return set_efer(vcpu, data);
8f1589d9
AP		 1378 case MSR_K7_HWCR:
1379 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1380 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1381 if (data != 0) {
1382 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1383 data);
1384 return 1;
1385 }
15c4a640 1386 break;
f7c6d140
AP		 1387 case MSR_FAM10H_MMIO_CONF_BASE:
1388 if (data != 0) {
1389 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1390 "0x%llx\n", data);
1391 return 1;
1392 }
15c4a640 1393 break;
c323c0e5 1394 case MSR_AMD64_NB_CFG:
c7ac679c 1395 break;
b5e2fec0
AG		 1396 case MSR_IA32_DEBUGCTLMSR:
1397 if (!data) {
1398 /* We support the non-activated case already */
1399 break;
1400 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1401 /* Values other than LBR and BTF are vendor-specific,
1402 thus reserved and should throw a #GP */
1403 return 1;
1404 }
1405 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1406 __func__, data);
1407 break;
15c4a640
CO		 1408 case MSR_IA32_UCODE_REV:
1409 case MSR_IA32_UCODE_WRITE:
61a6bd67 1410 case MSR_VM_HSAVE_PA:
6098ca93 1411 case MSR_AMD64_PATCH_LOADER:
15c4a640 1412 break;
9ba075a6
AK		 1413 case 0x200 ... 0x2ff:
1414 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1415 case MSR_IA32_APICBASE:
1416 kvm_set_apic_base(vcpu, data);
1417 break;
0105d1a5
GN		 1418 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1419 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1420 case MSR_IA32_MISC_ENABLE:
ad312c7c 1421 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1422 break;
11c6bffa 1423 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1424 case MSR_KVM_WALL_CLOCK:
1425 vcpu->kvm->arch.wall_clock = data;
1426 kvm_write_wall_clock(vcpu->kvm, data);
1427 break;
11c6bffa 1428 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1429 case MSR_KVM_SYSTEM_TIME: {
1430 if (vcpu->arch.time_page) {
1431 kvm_release_page_dirty(vcpu->arch.time_page);
1432 vcpu->arch.time_page = NULL;
1433 }
1434
1435 vcpu->arch.time = data;
1436
1437 /* we verify if the enable bit is set... */
1438 if (!(data & 1))
1439 break;
1440
1441 /* ...but clean it before doing the actual write */
1442 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1443
18068523
GOC		 1444 vcpu->arch.time_page =
1445 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1446
1447 if (is_error_page(vcpu->arch.time_page)) {
1448 kvm_release_page_clean(vcpu->arch.time_page);
1449 vcpu->arch.time_page = NULL;
1450 }
1451
c8076604 1452 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1453 break;
1454 }
890ca9ae
HY		 1455 case MSR_IA32_MCG_CTL:
1456 case MSR_IA32_MCG_STATUS:
1457 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1458 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1459
1460 /* Performance counters are not protected by a CPUID bit,
1461 * so we should check all of them in the generic path for the sake of
1462 * cross vendor migration.
1463 * Writing a zero into the event select MSRs disables them,
1464 * which we perfectly emulate ;-). Any other value should be at least
1465 * reported, some guests depend on them.
1466 */
1467 case MSR_P6_EVNTSEL0:
1468 case MSR_P6_EVNTSEL1:
1469 case MSR_K7_EVNTSEL0:
1470 case MSR_K7_EVNTSEL1:
1471 case MSR_K7_EVNTSEL2:
1472 case MSR_K7_EVNTSEL3:
1473 if (data != 0)
1474 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1475 "0x%x data 0x%llx\n", msr, data);
1476 break;
1477 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1478 * so we ignore writes to make it happy.
1479 */
1480 case MSR_P6_PERFCTR0:
1481 case MSR_P6_PERFCTR1:
1482 case MSR_K7_PERFCTR0:
1483 case MSR_K7_PERFCTR1:
1484 case MSR_K7_PERFCTR2:
1485 case MSR_K7_PERFCTR3:
1486 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1487 "0x%x data 0x%llx\n", msr, data);
1488 break;
84e0cefa
JS		 1489 case MSR_K7_CLK_CTL:
1490 /*
1491 * Ignore all writes to this no longer documented MSR.
1492 * Writes are only relevant for old K7 processors,
1493 * all pre-dating SVM, but a recommended workaround from
1494 * AMD for these chips. It is possible to speicify the
1495 * affected processor models on the command line, hence
1496 * the need to ignore the workaround.
1497 */
1498 break;
55cd8e5a
GN		 1499 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1500 if (kvm_hv_msr_partition_wide(msr)) {
1501 int r;
1502 mutex_lock(&vcpu->kvm->lock);
1503 r = set_msr_hyperv_pw(vcpu, msr, data);
1504 mutex_unlock(&vcpu->kvm->lock);
1505 return r;
1506 } else
1507 return set_msr_hyperv(vcpu, msr, data);
1508 break;
15c4a640 1509 default:
ffde22ac
ES		 1510 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1511 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1512 if (!ignore_msrs) {
1513 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1514 msr, data);
1515 return 1;
1516 } else {
1517 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1518 msr, data);
1519 break;
1520 }
15c4a640
CO		 1521 }
1522 return 0;
1523}
1524EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1525
1526
1527/*
1528 * Reads an msr value (of 'msr_index') into 'pdata'.
1529 * Returns 0 on success, non-0 otherwise.
1530 * Assumes vcpu_load() was already called.
1531 */
1532int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1533{
1534 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1535}
1536
9ba075a6
AK		 1537static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1538{
0bed3b56
SY		 1539 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1540
9ba075a6
AK		 1541 if (!msr_mtrr_valid(msr))
1542 return 1;
1543
0bed3b56
SY		 1544 if (msr == MSR_MTRRdefType)
1545 *pdata = vcpu->arch.mtrr_state.def_type +
1546 (vcpu->arch.mtrr_state.enabled << 10);
1547 else if (msr == MSR_MTRRfix64K_00000)
1548 *pdata = p[0];
1549 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1550 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1551 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1552 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1553 else if (msr == MSR_IA32_CR_PAT)
1554 *pdata = vcpu->arch.pat;
1555 else { /* Variable MTRRs */
1556 int idx, is_mtrr_mask;
1557 u64 *pt;
1558
1559 idx = (msr - 0x200) / 2;
1560 is_mtrr_mask = msr - 0x200 - 2 * idx;
1561 if (!is_mtrr_mask)
1562 pt =
1563 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1564 else
1565 pt =
1566 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1567 *pdata = *pt;
1568 }
1569
9ba075a6
AK		 1570 return 0;
1571}
1572
890ca9ae 1573static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1574{
1575 u64 data;
890ca9ae
HY		 1576 u64 mcg_cap = vcpu->arch.mcg_cap;
1577 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1578
1579 switch (msr) {
15c4a640
CO		 1580 case MSR_IA32_P5_MC_ADDR:
1581 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1582 data = 0;
1583 break;
15c4a640 1584 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1585 data = vcpu->arch.mcg_cap;
1586 break;
c7ac679c 1587 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1588 if (!(mcg_cap & MCG_CTL_P))
1589 return 1;
1590 data = vcpu->arch.mcg_ctl;
1591 break;
1592 case MSR_IA32_MCG_STATUS:
1593 data = vcpu->arch.mcg_status;
1594 break;
1595 default:
1596 if (msr >= MSR_IA32_MC0_CTL &&
1597 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1598 u32 offset = msr - MSR_IA32_MC0_CTL;
1599 data = vcpu->arch.mce_banks[offset];
1600 break;
1601 }
1602 return 1;
1603 }
1604 *pdata = data;
1605 return 0;
1606}
1607
55cd8e5a
GN		 1608static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1609{
1610 u64 data = 0;
1611 struct kvm *kvm = vcpu->kvm;
1612
1613 switch (msr) {
1614 case HV_X64_MSR_GUEST_OS_ID:
1615 data = kvm->arch.hv_guest_os_id;
1616 break;
1617 case HV_X64_MSR_HYPERCALL:
1618 data = kvm->arch.hv_hypercall;
1619 break;
1620 default:
1621 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1622 return 1;
1623 }
1624
1625 *pdata = data;
1626 return 0;
1627}
1628
1629static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1630{
1631 u64 data = 0;
1632
1633 switch (msr) {
1634 case HV_X64_MSR_VP_INDEX: {
1635 int r;
1636 struct kvm_vcpu *v;
1637 kvm_for_each_vcpu(r, v, vcpu->kvm)
1638 if (v == vcpu)
1639 data = r;
1640 break;
1641 }
10388a07
GN		 1642 case HV_X64_MSR_EOI:
1643 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1644 case HV_X64_MSR_ICR:
1645 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1646 case HV_X64_MSR_TPR:
1647 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1648 default:
1649 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1650 return 1;
1651 }
1652 *pdata = data;
1653 return 0;
1654}
1655
890ca9ae
HY		 1656int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1657{
1658 u64 data;
1659
1660 switch (msr) {
890ca9ae 1661 case MSR_IA32_PLATFORM_ID:
15c4a640 1662 case MSR_IA32_UCODE_REV:
15c4a640 1663 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1664 case MSR_IA32_DEBUGCTLMSR:
1665 case MSR_IA32_LASTBRANCHFROMIP:
1666 case MSR_IA32_LASTBRANCHTOIP:
1667 case MSR_IA32_LASTINTFROMIP:
1668 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1669 case MSR_K8_SYSCFG:
1670 case MSR_K7_HWCR:
61a6bd67 1671 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1672 case MSR_P6_PERFCTR0:
1673 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1674 case MSR_P6_EVNTSEL0:
1675 case MSR_P6_EVNTSEL1:
9e699624 1676 case MSR_K7_EVNTSEL0:
1f3ee616 1677 case MSR_K7_PERFCTR0:
1fdbd48c 1678 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1679 case MSR_AMD64_NB_CFG:
f7c6d140 1680 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1681 data = 0;
1682 break;
9ba075a6
AK		 1683 case MSR_MTRRcap:
1684 data = 0x500 | KVM_NR_VAR_MTRR;
1685 break;
1686 case 0x200 ... 0x2ff:
1687 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1688 case 0xcd: /* fsb frequency */
1689 data = 3;
1690 break;
7b914098
JS		 1691 /*
1692 * MSR_EBC_FREQUENCY_ID
1693 * Conservative value valid for even the basic CPU models.
1694 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1695 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1696 * and 266MHz for model 3, or 4. Set Core Clock
1697 * Frequency to System Bus Frequency Ratio to 1 (bits
1698 * 31:24) even though these are only valid for CPU
1699 * models > 2, however guests may end up dividing or
1700 * multiplying by zero otherwise.
1701 */
1702 case MSR_EBC_FREQUENCY_ID:
1703 data = 1 << 24;
1704 break;
15c4a640
CO		 1705 case MSR_IA32_APICBASE:
1706 data = kvm_get_apic_base(vcpu);
1707 break;
0105d1a5
GN		 1708 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1709 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1710 break;
15c4a640 1711 case MSR_IA32_MISC_ENABLE:
ad312c7c 1712 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1713 break;
847f0ad8
AG		 1714 case MSR_IA32_PERF_STATUS:
1715 /* TSC increment by tick */
1716 data = 1000ULL;
1717 /* CPU multiplier */
1718 data |= (((uint64_t)4ULL) << 40);
1719 break;
15c4a640 1720 case MSR_EFER:
f6801dff 1721 data = vcpu->arch.efer;
15c4a640 1722 break;
18068523 1723 case MSR_KVM_WALL_CLOCK:
11c6bffa 1724 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1725 data = vcpu->kvm->arch.wall_clock;
1726 break;
1727 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1728 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1729 data = vcpu->arch.time;
1730 break;
890ca9ae
HY		 1731 case MSR_IA32_P5_MC_ADDR:
1732 case MSR_IA32_P5_MC_TYPE:
1733 case MSR_IA32_MCG_CAP:
1734 case MSR_IA32_MCG_CTL:
1735 case MSR_IA32_MCG_STATUS:
1736 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1737 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1738 case MSR_K7_CLK_CTL:
1739 /*
1740 * Provide expected ramp-up count for K7. All other
1741 * are set to zero, indicating minimum divisors for
1742 * every field.
1743 *
1744 * This prevents guest kernels on AMD host with CPU
1745 * type 6, model 8 and higher from exploding due to
1746 * the rdmsr failing.
1747 */
1748 data = 0x20000000;
1749 break;
55cd8e5a
GN		 1750 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1751 if (kvm_hv_msr_partition_wide(msr)) {
1752 int r;
1753 mutex_lock(&vcpu->kvm->lock);
1754 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1755 mutex_unlock(&vcpu->kvm->lock);
1756 return r;
1757 } else
1758 return get_msr_hyperv(vcpu, msr, pdata);
1759 break;
15c4a640 1760 default:
ed85c068
AP		 1761 if (!ignore_msrs) {
1762 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1763 return 1;
1764 } else {
1765 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1766 data = 0;
1767 }
1768 break;
15c4a640
CO		 1769 }
1770 *pdata = data;
1771 return 0;
1772}
1773EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1774
313a3dc7
CO		 1775/*
1776 * Read or write a bunch of msrs. All parameters are kernel addresses.
1777 *
1778 * @return number of msrs set successfully.
1779 */
1780static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1781 struct kvm_msr_entry *entries,
1782 int (*do_msr)(struct kvm_vcpu *vcpu,
1783 unsigned index, u64 *data))
1784{
f656ce01 1785 int i, idx;
313a3dc7 1786
f656ce01 1787 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1788 for (i = 0; i < msrs->nmsrs; ++i)
1789 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1790 break;
f656ce01 1791 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1792
313a3dc7
CO		 1793 return i;
1794}
1795
1796/*
1797 * Read or write a bunch of msrs. Parameters are user addresses.
1798 *
1799 * @return number of msrs set successfully.
1800 */
1801static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1802 int (*do_msr)(struct kvm_vcpu *vcpu,
1803 unsigned index, u64 *data),
1804 int writeback)
1805{
1806 struct kvm_msrs msrs;
1807 struct kvm_msr_entry *entries;
1808 int r, n;
1809 unsigned size;
1810
1811 r = -EFAULT;
1812 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1813 goto out;
1814
1815 r = -E2BIG;
1816 if (msrs.nmsrs >= MAX_IO_MSRS)
1817 goto out;
1818
1819 r = -ENOMEM;
1820 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1821 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1822 if (!entries)
1823 goto out;
1824
1825 r = -EFAULT;
1826 if (copy_from_user(entries, user_msrs->entries, size))
1827 goto out_free;
1828
1829 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1830 if (r < 0)
1831 goto out_free;
1832
1833 r = -EFAULT;
1834 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1835 goto out_free;
1836
1837 r = n;
1838
1839out_free:
7a73c028 1840 kfree(entries);
313a3dc7
CO		 1841out:
1842 return r;
1843}
1844
018d00d2
ZX		 1845int kvm_dev_ioctl_check_extension(long ext)
1846{
1847 int r;
1848
1849 switch (ext) {
1850 case KVM_CAP_IRQCHIP:
1851 case KVM_CAP_HLT:
1852 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1853 case KVM_CAP_SET_TSS_ADDR:
07716717 1854 case KVM_CAP_EXT_CPUID:
c8076604 1855 case KVM_CAP_CLOCKSOURCE:
7837699f 1856 case KVM_CAP_PIT:
a28e4f5a 1857 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1858 case KVM_CAP_MP_STATE:
ed848624 1859 case KVM_CAP_SYNC_MMU:
52d939a0 1860 case KVM_CAP_REINJECT_CONTROL:
4925663a 1861 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1862 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1863 case KVM_CAP_IRQFD:
d34e6b17 1864 case KVM_CAP_IOEVENTFD:
c5ff41ce 1865 case KVM_CAP_PIT2:
e9f42757 1866 case KVM_CAP_PIT_STATE2:
b927a3ce 1867 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1868 case KVM_CAP_XEN_HVM:
afbcf7ab 1869 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1870 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1871 case KVM_CAP_HYPERV:
10388a07 1872 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1873 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1874 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1875 case KVM_CAP_DEBUGREGS:
d2be1651 1876 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1877 case KVM_CAP_XSAVE:
018d00d2
ZX		 1878 r = 1;
1879 break;
542472b5
LV		 1880 case KVM_CAP_COALESCED_MMIO:
1881 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1882 break;
774ead3a
AK		 1883 case KVM_CAP_VAPIC:
1884 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1885 break;
f725230a
AK		 1886 case KVM_CAP_NR_VCPUS:
1887 r = KVM_MAX_VCPUS;
1888 break;
a988b910
AK		 1889 case KVM_CAP_NR_MEMSLOTS:
1890 r = KVM_MEMORY_SLOTS;
1891 break;
a68a6a72
MT		 1892 case KVM_CAP_PV_MMU: /* obsolete */
1893 r = 0;
2f333bcb 1894 break;
62c476c7 1895 case KVM_CAP_IOMMU:
19de40a8 1896 r = iommu_found();
62c476c7 1897 break;
890ca9ae
HY		 1898 case KVM_CAP_MCE:
1899 r = KVM_MAX_MCE_BANKS;
1900 break;
2d5b5a66
SY		 1901 case KVM_CAP_XCRS:
1902 r = cpu_has_xsave;
1903 break;
018d00d2
ZX		 1904 default:
1905 r = 0;
1906 break;
1907 }
1908 return r;
1909
1910}
1911
043405e1
CO		 1912long kvm_arch_dev_ioctl(struct file *filp,
1913 unsigned int ioctl, unsigned long arg)
1914{
1915 void __user *argp = (void __user *)arg;
1916 long r;
1917
1918 switch (ioctl) {
1919 case KVM_GET_MSR_INDEX_LIST: {
1920 struct kvm_msr_list __user *user_msr_list = argp;
1921 struct kvm_msr_list msr_list;
1922 unsigned n;
1923
1924 r = -EFAULT;
1925 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1926 goto out;
1927 n = msr_list.nmsrs;
1928 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1929 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1930 goto out;
1931 r = -E2BIG;
e125e7b6 1932 if (n < msr_list.nmsrs)
043405e1
CO		 1933 goto out;
1934 r = -EFAULT;
1935 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1936 num_msrs_to_save * sizeof(u32)))
1937 goto out;
e125e7b6 1938 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1939 &emulated_msrs,
1940 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1941 goto out;
1942 r = 0;
1943 break;
1944 }
674eea0f
AK		 1945 case KVM_GET_SUPPORTED_CPUID: {
1946 struct kvm_cpuid2 __user *cpuid_arg = argp;
1947 struct kvm_cpuid2 cpuid;
1948
1949 r = -EFAULT;
1950 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1951 goto out;
1952 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1953 cpuid_arg->entries);
674eea0f
AK		 1954 if (r)
1955 goto out;
1956
1957 r = -EFAULT;
1958 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1959 goto out;
1960 r = 0;
1961 break;
1962 }
890ca9ae
HY		 1963 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1964 u64 mce_cap;
1965
1966 mce_cap = KVM_MCE_CAP_SUPPORTED;
1967 r = -EFAULT;
1968 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1969 goto out;
1970 r = 0;
1971 break;
1972 }
043405e1
CO		 1973 default:
1974 r = -EINVAL;
1975 }
1976out:
1977 return r;
1978}
1979
f5f48ee1
SY		 1980static void wbinvd_ipi(void *garbage)
1981{
1982 wbinvd();
1983}
1984
1985static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
1986{
1987 return vcpu->kvm->arch.iommu_domain &&
1988 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
1989}
1990
313a3dc7
CO		 1991void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1992{
f5f48ee1
SY		 1993 /* Address WBINVD may be executed by guest */
1994 if (need_emulate_wbinvd(vcpu)) {
1995 if (kvm_x86_ops->has_wbinvd_exit())
1996 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
1997 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
1998 smp_call_function_single(vcpu->cpu,
1999 wbinvd_ipi, NULL, 1);
2000 }
2001
313a3dc7 2002 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2003 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2004 /* Make sure TSC doesn't go backwards */
2005 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2006 native_read_tsc() - vcpu->arch.last_host_tsc;
2007 if (tsc_delta < 0)
2008 mark_tsc_unstable("KVM discovered backwards TSC");
2009 if (check_tsc_unstable())
2010 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
2011 kvm_migrate_timers(vcpu);
2012 vcpu->cpu = cpu;
2013 }
313a3dc7
CO		 2014}
2015
2016void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2017{
02daab21 2018 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2019 kvm_put_guest_fpu(vcpu);
e48672fa 2020 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2021}
2022
07716717 2023static int is_efer_nx(void)
313a3dc7 2024{
e286e86e 2025 unsigned long long efer = 0;
313a3dc7 2026
e286e86e 2027 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2028 return efer & EFER_NX;
2029}
2030
2031static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2032{
2033 int i;
2034 struct kvm_cpuid_entry2 *e, *entry;
2035
313a3dc7 2036 entry = NULL;
ad312c7c
ZX		 2037 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2038 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2039 if (e->function == 0x80000001) {
2040 entry = e;
2041 break;
2042 }
2043 }
07716717 2044 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2045 entry->edx &= ~(1 << 20);
2046 printk(KERN_INFO "kvm: guest NX capability removed\n");
2047 }
2048}
2049
07716717 2050/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2051static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2052 struct kvm_cpuid *cpuid,
2053 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2054{
2055 int r, i;
2056 struct kvm_cpuid_entry *cpuid_entries;
2057
2058 r = -E2BIG;
2059 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2060 goto out;
2061 r = -ENOMEM;
2062 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2063 if (!cpuid_entries)
2064 goto out;
2065 r = -EFAULT;
2066 if (copy_from_user(cpuid_entries, entries,
2067 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2068 goto out_free;
2069 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2070 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2071 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2072 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2073 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2074 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2075 vcpu->arch.cpuid_entries[i].index = 0;
2076 vcpu->arch.cpuid_entries[i].flags = 0;
2077 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2078 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2079 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2080 }
2081 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2082 cpuid_fix_nx_cap(vcpu);
2083 r = 0;
fc61b800 2084 kvm_apic_set_version(vcpu);
0e851880 2085 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2086 update_cpuid(vcpu);
07716717
DK		 2087
2088out_free:
2089 vfree(cpuid_entries);
2090out:
2091 return r;
2092}
2093
2094static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2095 struct kvm_cpuid2 *cpuid,
2096 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2097{
2098 int r;
2099
2100 r = -E2BIG;
2101 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2102 goto out;
2103 r = -EFAULT;
ad312c7c 2104 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2105 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2106 goto out;
ad312c7c 2107 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2108 kvm_apic_set_version(vcpu);
0e851880 2109 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2110 update_cpuid(vcpu);
313a3dc7
CO		 2111 return 0;
2112
2113out:
2114 return r;
2115}
2116
07716717 2117static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2118 struct kvm_cpuid2 *cpuid,
2119 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2120{
2121 int r;
2122
2123 r = -E2BIG;
ad312c7c 2124 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2125 goto out;
2126 r = -EFAULT;
ad312c7c 2127 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2128 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2129 goto out;
2130 return 0;
2131
2132out:
ad312c7c 2133 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2134 return r;
2135}
2136
07716717 2137static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2138 u32 index)
07716717
DK		 2139{
2140 entry->function = function;
2141 entry->index = index;
2142 cpuid_count(entry->function, entry->index,
19355475 2143 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2144 entry->flags = 0;
2145}
2146
7faa4ee1
AK		 2147#define F(x) bit(X86_FEATURE_##x)
2148
07716717
DK		 2149static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2150 u32 index, int *nent, int maxnent)
2151{
7faa4ee1 2152 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2153#ifdef CONFIG_X86_64
17cc3935
SY		 2154 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2155 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2156 unsigned f_lm = F(LM);
2157#else
17cc3935 2158 unsigned f_gbpages = 0;
7faa4ee1 2159 unsigned f_lm = 0;
07716717 2160#endif
4e47c7a6 2161 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2162
2163 /* cpuid 1.edx */
2164 const u32 kvm_supported_word0_x86_features =
2165 F(FPU) | F(VME) | F(DE) | F(PSE) |
2166 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2167 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2168 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2169 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2170 0 /* Reserved, DS, ACPI */ | F(MMX) |
2171 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2172 0 /* HTT, TM, Reserved, PBE */;
2173 /* cpuid 0x80000001.edx */
2174 const u32 kvm_supported_word1_x86_features =
2175 F(FPU) | F(VME) | F(DE) | F(PSE) |
2176 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2177 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2178 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2179 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2180 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2181 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2182 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2183 /* cpuid 1.ecx */
2184 const u32 kvm_supported_word4_x86_features =
6c3f6041 2185 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2186 0 /* DS-CPL, VMX, SMX, EST */ |
2187 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2188 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2189 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2190 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6c3f6041 2191 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
7faa4ee1 2192 /* cpuid 0x80000001.ecx */
07716717 2193 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 2194 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
2195 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2196 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
2197 0 /* SKINIT */ | 0 /* WDT */;
07716717 2198
19355475 2199 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2200 get_cpu();
2201 do_cpuid_1_ent(entry, function, index);
2202 ++*nent;
2203
2204 switch (function) {
2205 case 0:
2acf923e 2206 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2207 break;
2208 case 1:
2209 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2210 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2211 /* we support x2apic emulation even if host does not support
2212 * it since we emulate x2apic in software */
2213 entry->ecx |= F(X2APIC);
07716717
DK		 2214 break;
2215 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2216 * may return different values. This forces us to get_cpu() before
2217 * issuing the first command, and also to emulate this annoying behavior
2218 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2219 case 2: {
2220 int t, times = entry->eax & 0xff;
2221
2222 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2223 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2224 for (t = 1; t < times && *nent < maxnent; ++t) {
2225 do_cpuid_1_ent(&entry[t], function, 0);
2226 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2227 ++*nent;
2228 }
2229 break;
2230 }
2231 /* function 4 and 0xb have additional index. */
2232 case 4: {
14af3f3c 2233 int i, cache_type;
07716717
DK		 2234
2235 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2236 /* read more entries until cache_type is zero */
14af3f3c
HH		 2237 for (i = 1; *nent < maxnent; ++i) {
2238 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2239 if (!cache_type)
2240 break;
14af3f3c
HH		 2241 do_cpuid_1_ent(&entry[i], function, i);
2242 entry[i].flags |=
07716717
DK		 2243 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2244 ++*nent;
2245 }
2246 break;
2247 }
2248 case 0xb: {
14af3f3c 2249 int i, level_type;
07716717
DK		 2250
2251 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2252 /* read more entries until level_type is zero */
14af3f3c 2253 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2254 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2255 if (!level_type)
2256 break;
14af3f3c
HH		 2257 do_cpuid_1_ent(&entry[i], function, i);
2258 entry[i].flags |=
07716717
DK		 2259 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2260 ++*nent;
2261 }
2262 break;
2263 }
2acf923e
DC		 2264 case 0xd: {
2265 int i;
2266
2267 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2268 for (i = 1; *nent < maxnent; ++i) {
2269 if (entry[i - 1].eax == 0 && i != 2)
2270 break;
2271 do_cpuid_1_ent(&entry[i], function, i);
2272 entry[i].flags |=
2273 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2274 ++*nent;
2275 }
2276 break;
2277 }
84478c82
GC		 2278 case KVM_CPUID_SIGNATURE: {
2279 char signature[12] = "KVMKVMKVM\0\0";
2280 u32 *sigptr = (u32 *)signature;
2281 entry->eax = 0;
2282 entry->ebx = sigptr[0];
2283 entry->ecx = sigptr[1];
2284 entry->edx = sigptr[2];
2285 break;
2286 }
2287 case KVM_CPUID_FEATURES:
2288 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2289 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2290 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2291 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2292 entry->ebx = 0;
2293 entry->ecx = 0;
2294 entry->edx = 0;
2295 break;
07716717
DK		 2296 case 0x80000000:
2297 entry->eax = min(entry->eax, 0x8000001a);
2298 break;
2299 case 0x80000001:
2300 entry->edx &= kvm_supported_word1_x86_features;
2301 entry->ecx &= kvm_supported_word6_x86_features;
2302 break;
2303 }
d4330ef2
JR		 2304
2305 kvm_x86_ops->set_supported_cpuid(function, entry);
2306
07716717
DK		 2307 put_cpu();
2308}
2309
7faa4ee1
AK		 2310#undef F
2311
674eea0f 2312static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2313 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2314{
2315 struct kvm_cpuid_entry2 *cpuid_entries;
2316 int limit, nent = 0, r = -E2BIG;
2317 u32 func;
2318
2319 if (cpuid->nent < 1)
2320 goto out;
6a544355
AK		 2321 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2322 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2323 r = -ENOMEM;
2324 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2325 if (!cpuid_entries)
2326 goto out;
2327
2328 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2329 limit = cpuid_entries[0].eax;
2330 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2331 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2332 &nent, cpuid->nent);
07716717
DK		 2333 r = -E2BIG;
2334 if (nent >= cpuid->nent)
2335 goto out_free;
2336
2337 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2338 limit = cpuid_entries[nent - 1].eax;
2339 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2340 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2341 &nent, cpuid->nent);
84478c82
GC		 2342
2343
2344
2345 r = -E2BIG;
2346 if (nent >= cpuid->nent)
2347 goto out_free;
2348
2349 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2350 cpuid->nent);
2351
2352 r = -E2BIG;
2353 if (nent >= cpuid->nent)
2354 goto out_free;
2355
2356 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2357 cpuid->nent);
2358
cb007648
MM		 2359 r = -E2BIG;
2360 if (nent >= cpuid->nent)
2361 goto out_free;
2362
07716717
DK		 2363 r = -EFAULT;
2364 if (copy_to_user(entries, cpuid_entries,
19355475 2365 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2366 goto out_free;
2367 cpuid->nent = nent;
2368 r = 0;
2369
2370out_free:
2371 vfree(cpuid_entries);
2372out:
2373 return r;
2374}
2375
313a3dc7
CO		 2376static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2377 struct kvm_lapic_state *s)
2378{
ad312c7c 2379 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2380
2381 return 0;
2382}
2383
2384static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2385 struct kvm_lapic_state *s)
2386{
ad312c7c 2387 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2388 kvm_apic_post_state_restore(vcpu);
cb142eb7 2389 update_cr8_intercept(vcpu);
313a3dc7
CO		 2390
2391 return 0;
2392}
2393
f77bc6a4
ZX		 2394static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2395 struct kvm_interrupt *irq)
2396{
2397 if (irq->irq < 0 || irq->irq >= 256)
2398 return -EINVAL;
2399 if (irqchip_in_kernel(vcpu->kvm))
2400 return -ENXIO;
f77bc6a4 2401
66fd3f7f 2402 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4 2403
f77bc6a4
ZX		 2404 return 0;
2405}
2406
c4abb7c9
JK		 2407static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2408{
c4abb7c9 2409 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2410
2411 return 0;
2412}
2413
b209749f
AK		 2414static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2415 struct kvm_tpr_access_ctl *tac)
2416{
2417 if (tac->flags)
2418 return -EINVAL;
2419 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2420 return 0;
2421}
2422
890ca9ae
HY		 2423static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2424 u64 mcg_cap)
2425{
2426 int r;
2427 unsigned bank_num = mcg_cap & 0xff, bank;
2428
2429 r = -EINVAL;
a9e38c3e 2430 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2431 goto out;
2432 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2433 goto out;
2434 r = 0;
2435 vcpu->arch.mcg_cap = mcg_cap;
2436 /* Init IA32_MCG_CTL to all 1s */
2437 if (mcg_cap & MCG_CTL_P)
2438 vcpu->arch.mcg_ctl = ~(u64)0;
2439 /* Init IA32_MCi_CTL to all 1s */
2440 for (bank = 0; bank < bank_num; bank++)
2441 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2442out:
2443 return r;
2444}
2445
2446static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2447 struct kvm_x86_mce *mce)
2448{
2449 u64 mcg_cap = vcpu->arch.mcg_cap;
2450 unsigned bank_num = mcg_cap & 0xff;
2451 u64 *banks = vcpu->arch.mce_banks;
2452
2453 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2454 return -EINVAL;
2455 /*
2456 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2457 * reporting is disabled
2458 */
2459 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2460 vcpu->arch.mcg_ctl != ~(u64)0)
2461 return 0;
2462 banks += 4 * mce->bank;
2463 /*
2464 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2465 * reporting is disabled for the bank
2466 */
2467 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2468 return 0;
2469 if (mce->status & MCI_STATUS_UC) {
2470 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2471 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2472 printk(KERN_DEBUG "kvm: set_mce: "
2473 "injects mce exception while "
2474 "previous one is in progress!\n");
a8eeb04a 2475 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2476 return 0;
2477 }
2478 if (banks[1] & MCI_STATUS_VAL)
2479 mce->status |= MCI_STATUS_OVER;
2480 banks[2] = mce->addr;
2481 banks[3] = mce->misc;
2482 vcpu->arch.mcg_status = mce->mcg_status;
2483 banks[1] = mce->status;
2484 kvm_queue_exception(vcpu, MC_VECTOR);
2485 } else if (!(banks[1] & MCI_STATUS_VAL)
2486 || !(banks[1] & MCI_STATUS_UC)) {
2487 if (banks[1] & MCI_STATUS_VAL)
2488 mce->status |= MCI_STATUS_OVER;
2489 banks[2] = mce->addr;
2490 banks[3] = mce->misc;
2491 banks[1] = mce->status;
2492 } else
2493 banks[1] |= MCI_STATUS_OVER;
2494 return 0;
2495}
2496
3cfc3092
JK		 2497static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2498 struct kvm_vcpu_events *events)
2499{
03b82a30
JK		 2500 events->exception.injected =
2501 vcpu->arch.exception.pending &&
2502 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2503 events->exception.nr = vcpu->arch.exception.nr;
2504 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2505 events->exception.error_code = vcpu->arch.exception.error_code;
2506
03b82a30
JK		 2507 events->interrupt.injected =
2508 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2509 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2510 events->interrupt.soft = 0;
48005f64
JK		 2511 events->interrupt.shadow =
2512 kvm_x86_ops->get_interrupt_shadow(vcpu,
2513 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2514
2515 events->nmi.injected = vcpu->arch.nmi_injected;
2516 events->nmi.pending = vcpu->arch.nmi_pending;
2517 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2518
2519 events->sipi_vector = vcpu->arch.sipi_vector;
2520
dab4b911 2521 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2522 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2523 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2524}
2525
2526static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2527 struct kvm_vcpu_events *events)
2528{
dab4b911 2529 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2530 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2531 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2532 return -EINVAL;
2533
3cfc3092
JK		 2534 vcpu->arch.exception.pending = events->exception.injected;
2535 vcpu->arch.exception.nr = events->exception.nr;
2536 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2537 vcpu->arch.exception.error_code = events->exception.error_code;
2538
2539 vcpu->arch.interrupt.pending = events->interrupt.injected;
2540 vcpu->arch.interrupt.nr = events->interrupt.nr;
2541 vcpu->arch.interrupt.soft = events->interrupt.soft;
2542 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2543 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2544 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2545 kvm_x86_ops->set_interrupt_shadow(vcpu,
2546 events->interrupt.shadow);
3cfc3092
JK		 2547
2548 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2549 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2550 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2551 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2552
dab4b911
JK		 2553 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2554 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2555
3cfc3092
JK		 2556 return 0;
2557}
2558
a1efbe77
JK		 2559static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2560 struct kvm_debugregs *dbgregs)
2561{
a1efbe77
JK		 2562 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2563 dbgregs->dr6 = vcpu->arch.dr6;
2564 dbgregs->dr7 = vcpu->arch.dr7;
2565 dbgregs->flags = 0;
a1efbe77
JK		 2566}
2567
2568static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2569 struct kvm_debugregs *dbgregs)
2570{
2571 if (dbgregs->flags)
2572 return -EINVAL;
2573
a1efbe77
JK		 2574 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2575 vcpu->arch.dr6 = dbgregs->dr6;
2576 vcpu->arch.dr7 = dbgregs->dr7;
2577
a1efbe77
JK		 2578 return 0;
2579}
2580
2d5b5a66
SY		 2581static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2582 struct kvm_xsave *guest_xsave)
2583{
2584 if (cpu_has_xsave)
2585 memcpy(guest_xsave->region,
2586 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2587 xstate_size);
2d5b5a66
SY		 2588 else {
2589 memcpy(guest_xsave->region,
2590 &vcpu->arch.guest_fpu.state->fxsave,
2591 sizeof(struct i387_fxsave_struct));
2592 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2593 XSTATE_FPSSE;
2594 }
2595}
2596
2597static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2598 struct kvm_xsave *guest_xsave)
2599{
2600 u64 xstate_bv =
2601 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2602
2603 if (cpu_has_xsave)
2604 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2605 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2606 else {
2607 if (xstate_bv & ~XSTATE_FPSSE)
2608 return -EINVAL;
2609 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2610 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2611 }
2612 return 0;
2613}
2614
2615static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2616 struct kvm_xcrs *guest_xcrs)
2617{
2618 if (!cpu_has_xsave) {
2619 guest_xcrs->nr_xcrs = 0;
2620 return;
2621 }
2622
2623 guest_xcrs->nr_xcrs = 1;
2624 guest_xcrs->flags = 0;
2625 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2626 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2627}
2628
2629static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2630 struct kvm_xcrs *guest_xcrs)
2631{
2632 int i, r = 0;
2633
2634 if (!cpu_has_xsave)
2635 return -EINVAL;
2636
2637 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2638 return -EINVAL;
2639
2640 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2641 /* Only support XCR0 currently */
2642 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2643 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2644 guest_xcrs->xcrs[0].value);
2645 break;
2646 }
2647 if (r)
2648 r = -EINVAL;
2649 return r;
2650}
2651
313a3dc7
CO		 2652long kvm_arch_vcpu_ioctl(struct file *filp,
2653 unsigned int ioctl, unsigned long arg)
2654{
2655 struct kvm_vcpu *vcpu = filp->private_data;
2656 void __user *argp = (void __user *)arg;
2657 int r;
d1ac91d8
AK		 2658 union {
2659 struct kvm_lapic_state *lapic;
2660 struct kvm_xsave *xsave;
2661 struct kvm_xcrs *xcrs;
2662 void *buffer;
2663 } u;
2664
2665 u.buffer = NULL;
313a3dc7
CO		 2666 switch (ioctl) {
2667 case KVM_GET_LAPIC: {
2204ae3c
MT		 2668 r = -EINVAL;
2669 if (!vcpu->arch.apic)
2670 goto out;
d1ac91d8 2671 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2672
b772ff36 2673 r = -ENOMEM;
d1ac91d8 2674 if (!u.lapic)
b772ff36 2675 goto out;
d1ac91d8 2676 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2677 if (r)
2678 goto out;
2679 r = -EFAULT;
d1ac91d8 2680 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2681 goto out;
2682 r = 0;
2683 break;
2684 }
2685 case KVM_SET_LAPIC: {
2204ae3c
MT		 2686 r = -EINVAL;
2687 if (!vcpu->arch.apic)
2688 goto out;
d1ac91d8 2689 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2690 r = -ENOMEM;
d1ac91d8 2691 if (!u.lapic)
b772ff36 2692 goto out;
313a3dc7 2693 r = -EFAULT;
d1ac91d8 2694 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2695 goto out;
d1ac91d8 2696 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2697 if (r)
2698 goto out;
2699 r = 0;
2700 break;
2701 }
f77bc6a4
ZX		 2702 case KVM_INTERRUPT: {
2703 struct kvm_interrupt irq;
2704
2705 r = -EFAULT;
2706 if (copy_from_user(&irq, argp, sizeof irq))
2707 goto out;
2708 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2709 if (r)
2710 goto out;
2711 r = 0;
2712 break;
2713 }
c4abb7c9
JK		 2714 case KVM_NMI: {
2715 r = kvm_vcpu_ioctl_nmi(vcpu);
2716 if (r)
2717 goto out;
2718 r = 0;
2719 break;
2720 }
313a3dc7
CO		 2721 case KVM_SET_CPUID: {
2722 struct kvm_cpuid __user *cpuid_arg = argp;
2723 struct kvm_cpuid cpuid;
2724
2725 r = -EFAULT;
2726 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2727 goto out;
2728 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2729 if (r)
2730 goto out;
2731 break;
2732 }
07716717
DK		 2733 case KVM_SET_CPUID2: {
2734 struct kvm_cpuid2 __user *cpuid_arg = argp;
2735 struct kvm_cpuid2 cpuid;
2736
2737 r = -EFAULT;
2738 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2739 goto out;
2740 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2741 cpuid_arg->entries);
07716717
DK		 2742 if (r)
2743 goto out;
2744 break;
2745 }
2746 case KVM_GET_CPUID2: {
2747 struct kvm_cpuid2 __user *cpuid_arg = argp;
2748 struct kvm_cpuid2 cpuid;
2749
2750 r = -EFAULT;
2751 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2752 goto out;
2753 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2754 cpuid_arg->entries);
07716717
DK		 2755 if (r)
2756 goto out;
2757 r = -EFAULT;
2758 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2759 goto out;
2760 r = 0;
2761 break;
2762 }
313a3dc7
CO		 2763 case KVM_GET_MSRS:
2764 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2765 break;
2766 case KVM_SET_MSRS:
2767 r = msr_io(vcpu, argp, do_set_msr, 0);
2768 break;
b209749f
AK		 2769 case KVM_TPR_ACCESS_REPORTING: {
2770 struct kvm_tpr_access_ctl tac;
2771
2772 r = -EFAULT;
2773 if (copy_from_user(&tac, argp, sizeof tac))
2774 goto out;
2775 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2776 if (r)
2777 goto out;
2778 r = -EFAULT;
2779 if (copy_to_user(argp, &tac, sizeof tac))
2780 goto out;
2781 r = 0;
2782 break;
2783 };
b93463aa
AK		 2784 case KVM_SET_VAPIC_ADDR: {
2785 struct kvm_vapic_addr va;
2786
2787 r = -EINVAL;
2788 if (!irqchip_in_kernel(vcpu->kvm))
2789 goto out;
2790 r = -EFAULT;
2791 if (copy_from_user(&va, argp, sizeof va))
2792 goto out;
2793 r = 0;
2794 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2795 break;
2796 }
890ca9ae
HY		 2797 case KVM_X86_SETUP_MCE: {
2798 u64 mcg_cap;
2799
2800 r = -EFAULT;
2801 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2802 goto out;
2803 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2804 break;
2805 }
2806 case KVM_X86_SET_MCE: {
2807 struct kvm_x86_mce mce;
2808
2809 r = -EFAULT;
2810 if (copy_from_user(&mce, argp, sizeof mce))
2811 goto out;
2812 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2813 break;
2814 }
3cfc3092
JK		 2815 case KVM_GET_VCPU_EVENTS: {
2816 struct kvm_vcpu_events events;
2817
2818 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2819
2820 r = -EFAULT;
2821 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2822 break;
2823 r = 0;
2824 break;
2825 }
2826 case KVM_SET_VCPU_EVENTS: {
2827 struct kvm_vcpu_events events;
2828
2829 r = -EFAULT;
2830 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2831 break;
2832
2833 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2834 break;
2835 }
a1efbe77
JK		 2836 case KVM_GET_DEBUGREGS: {
2837 struct kvm_debugregs dbgregs;
2838
2839 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2840
2841 r = -EFAULT;
2842 if (copy_to_user(argp, &dbgregs,
2843 sizeof(struct kvm_debugregs)))
2844 break;
2845 r = 0;
2846 break;
2847 }
2848 case KVM_SET_DEBUGREGS: {
2849 struct kvm_debugregs dbgregs;
2850
2851 r = -EFAULT;
2852 if (copy_from_user(&dbgregs, argp,
2853 sizeof(struct kvm_debugregs)))
2854 break;
2855
2856 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2857 break;
2858 }
2d5b5a66 2859 case KVM_GET_XSAVE: {
d1ac91d8 2860 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2861 r = -ENOMEM;
d1ac91d8 2862 if (!u.xsave)
2d5b5a66
SY		 2863 break;
2864
d1ac91d8 2865 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2866
2867 r = -EFAULT;
d1ac91d8 2868 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2869 break;
2870 r = 0;
2871 break;
2872 }
2873 case KVM_SET_XSAVE: {
d1ac91d8 2874 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2875 r = -ENOMEM;
d1ac91d8 2876 if (!u.xsave)
2d5b5a66
SY		 2877 break;
2878
2879 r = -EFAULT;
d1ac91d8 2880 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2881 break;
2882
d1ac91d8 2883 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2884 break;
2885 }
2886 case KVM_GET_XCRS: {
d1ac91d8 2887 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2888 r = -ENOMEM;
d1ac91d8 2889 if (!u.xcrs)
2d5b5a66
SY		 2890 break;
2891
d1ac91d8 2892 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2893
2894 r = -EFAULT;
d1ac91d8 2895 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2896 sizeof(struct kvm_xcrs)))
2897 break;
2898 r = 0;
2899 break;
2900 }
2901 case KVM_SET_XCRS: {
d1ac91d8 2902 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2903 r = -ENOMEM;
d1ac91d8 2904 if (!u.xcrs)
2d5b5a66
SY		 2905 break;
2906
2907 r = -EFAULT;
d1ac91d8 2908 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2909 sizeof(struct kvm_xcrs)))
2910 break;
2911
d1ac91d8 2912 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2913 break;
2914 }
313a3dc7
CO		 2915 default:
2916 r = -EINVAL;
2917 }
2918out:
d1ac91d8 2919 kfree(u.buffer);
313a3dc7
CO		 2920 return r;
2921}
2922
1fe779f8
CO		 2923static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2924{
2925 int ret;
2926
2927 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2928 return -1;
2929 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2930 return ret;
2931}
2932
b927a3ce
SY		 2933static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2934 u64 ident_addr)
2935{
2936 kvm->arch.ept_identity_map_addr = ident_addr;
2937 return 0;
2938}
2939
1fe779f8
CO		 2940static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2941 u32 kvm_nr_mmu_pages)
2942{
2943 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2944 return -EINVAL;
2945
79fac95e 2946 mutex_lock(&kvm->slots_lock);
7c8a83b7 2947 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2948
2949 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2950 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2951
7c8a83b7 2952 spin_unlock(&kvm->mmu_lock);
79fac95e 2953 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2954 return 0;
2955}
2956
2957static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2958{
39de71ec 2959 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2960}
2961
1fe779f8
CO		 2962static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2963{
2964 int r;
2965
2966 r = 0;
2967 switch (chip->chip_id) {
2968 case KVM_IRQCHIP_PIC_MASTER:
2969 memcpy(&chip->chip.pic,
2970 &pic_irqchip(kvm)->pics[0],
2971 sizeof(struct kvm_pic_state));
2972 break;
2973 case KVM_IRQCHIP_PIC_SLAVE:
2974 memcpy(&chip->chip.pic,
2975 &pic_irqchip(kvm)->pics[1],
2976 sizeof(struct kvm_pic_state));
2977 break;
2978 case KVM_IRQCHIP_IOAPIC:
eba0226b 2979 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2980 break;
2981 default:
2982 r = -EINVAL;
2983 break;
2984 }
2985 return r;
2986}
2987
2988static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2989{
2990 int r;
2991
2992 r = 0;
2993 switch (chip->chip_id) {
2994 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2995 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2996 memcpy(&pic_irqchip(kvm)->pics[0],
2997 &chip->chip.pic,
2998 sizeof(struct kvm_pic_state));
fa8273e9 2999 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3000 break;
3001 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 3002 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3003 memcpy(&pic_irqchip(kvm)->pics[1],
3004 &chip->chip.pic,
3005 sizeof(struct kvm_pic_state));
fa8273e9 3006 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3007 break;
3008 case KVM_IRQCHIP_IOAPIC:
eba0226b 3009 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3010 break;
3011 default:
3012 r = -EINVAL;
3013 break;
3014 }
3015 kvm_pic_update_irq(pic_irqchip(kvm));
3016 return r;
3017}
3018
e0f63cb9
SY		 3019static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3020{
3021 int r = 0;
3022
894a9c55 3023 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3024 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3025 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3026 return r;
3027}
3028
3029static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3030{
3031 int r = 0;
3032
894a9c55 3033 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3034 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3035 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3036 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3037 return r;
3038}
3039
3040static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3041{
3042 int r = 0;
3043
3044 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3045 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3046 sizeof(ps->channels));
3047 ps->flags = kvm->arch.vpit->pit_state.flags;
3048 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3049 return r;
3050}
3051
3052static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3053{
3054 int r = 0, start = 0;
3055 u32 prev_legacy, cur_legacy;
3056 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3057 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3058 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3059 if (!prev_legacy && cur_legacy)
3060 start = 1;
3061 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3062 sizeof(kvm->arch.vpit->pit_state.channels));
3063 kvm->arch.vpit->pit_state.flags = ps->flags;
3064 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3065 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3066 return r;
3067}
3068
52d939a0
MT		 3069static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3070 struct kvm_reinject_control *control)
3071{
3072 if (!kvm->arch.vpit)
3073 return -ENXIO;
894a9c55 3074 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3075 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3076 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3077 return 0;
3078}
3079
5bb064dc
ZX		 3080/*
3081 * Get (and clear) the dirty memory log for a memory slot.
3082 */
3083int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3084 struct kvm_dirty_log *log)
3085{
87bf6e7d 3086 int r, i;
5bb064dc 3087 struct kvm_memory_slot *memslot;
87bf6e7d 3088 unsigned long n;
b050b015 3089 unsigned long is_dirty = 0;
5bb064dc 3090
79fac95e 3091 mutex_lock(&kvm->slots_lock);
5bb064dc 3092
b050b015
MT		 3093 r = -EINVAL;
3094 if (log->slot >= KVM_MEMORY_SLOTS)
3095 goto out;
3096
3097 memslot = &kvm->memslots->memslots[log->slot];
3098 r = -ENOENT;
3099 if (!memslot->dirty_bitmap)
3100 goto out;
3101
87bf6e7d 3102 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3103
b050b015
MT		 3104 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3105 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3106
3107 /* If nothing is dirty, don't bother messing with page tables. */
3108 if (is_dirty) {
b050b015 3109 struct kvm_memslots *slots, *old_slots;
914ebccd 3110 unsigned long *dirty_bitmap;
b050b015 3111
7c8a83b7 3112 spin_lock(&kvm->mmu_lock);
5bb064dc 3113 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 3114 spin_unlock(&kvm->mmu_lock);
b050b015 3115
914ebccd
TY		 3116 r = -ENOMEM;
3117 dirty_bitmap = vmalloc(n);
3118 if (!dirty_bitmap)
3119 goto out;
3120 memset(dirty_bitmap, 0, n);
b050b015 3121
914ebccd
TY		 3122 r = -ENOMEM;
3123 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3124 if (!slots) {
3125 vfree(dirty_bitmap);
3126 goto out;
3127 }
b050b015
MT		 3128 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3129 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3130
3131 old_slots = kvm->memslots;
3132 rcu_assign_pointer(kvm->memslots, slots);
3133 synchronize_srcu_expedited(&kvm->srcu);
3134 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3135 kfree(old_slots);
914ebccd
TY		 3136
3137 r = -EFAULT;
3138 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3139 vfree(dirty_bitmap);
3140 goto out;
3141 }
3142 vfree(dirty_bitmap);
3143 } else {
3144 r = -EFAULT;
3145 if (clear_user(log->dirty_bitmap, n))
3146 goto out;
5bb064dc 3147 }
b050b015 3148
5bb064dc
ZX		 3149 r = 0;
3150out:
79fac95e 3151 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3152 return r;
3153}
3154
1fe779f8
CO		 3155long kvm_arch_vm_ioctl(struct file *filp,
3156 unsigned int ioctl, unsigned long arg)
3157{
3158 struct kvm *kvm = filp->private_data;
3159 void __user *argp = (void __user *)arg;
367e1319 3160 int r = -ENOTTY;
f0d66275
DH		 3161 /*
3162 * This union makes it completely explicit to gcc-3.x
3163 * that these two variables' stack usage should be
3164 * combined, not added together.
3165 */
3166 union {
3167 struct kvm_pit_state ps;
e9f42757 3168 struct kvm_pit_state2 ps2;
c5ff41ce 3169 struct kvm_pit_config pit_config;
f0d66275 3170 } u;
1fe779f8
CO		 3171
3172 switch (ioctl) {
3173 case KVM_SET_TSS_ADDR:
3174 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3175 if (r < 0)
3176 goto out;
3177 break;
b927a3ce
SY		 3178 case KVM_SET_IDENTITY_MAP_ADDR: {
3179 u64 ident_addr;
3180
3181 r = -EFAULT;
3182 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3183 goto out;
3184 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3185 if (r < 0)
3186 goto out;
3187 break;
3188 }
1fe779f8
CO		 3189 case KVM_SET_NR_MMU_PAGES:
3190 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3191 if (r)
3192 goto out;
3193 break;
3194 case KVM_GET_NR_MMU_PAGES:
3195 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3196 break;
3ddea128
MT		 3197 case KVM_CREATE_IRQCHIP: {
3198 struct kvm_pic *vpic;
3199
3200 mutex_lock(&kvm->lock);
3201 r = -EEXIST;
3202 if (kvm->arch.vpic)
3203 goto create_irqchip_unlock;
1fe779f8 3204 r = -ENOMEM;
3ddea128
MT		 3205 vpic = kvm_create_pic(kvm);
3206 if (vpic) {
1fe779f8
CO		 3207 r = kvm_ioapic_init(kvm);
3208 if (r) {
72bb2fcd
WY		 3209 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3210 &vpic->dev);
3ddea128
MT		 3211 kfree(vpic);
3212 goto create_irqchip_unlock;
1fe779f8
CO		 3213 }
3214 } else
3ddea128
MT		 3215 goto create_irqchip_unlock;
3216 smp_wmb();
3217 kvm->arch.vpic = vpic;
3218 smp_wmb();
399ec807
AK		 3219 r = kvm_setup_default_irq_routing(kvm);
3220 if (r) {
3ddea128 3221 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3222 kvm_ioapic_destroy(kvm);
3223 kvm_destroy_pic(kvm);
3ddea128 3224 mutex_unlock(&kvm->irq_lock);
399ec807 3225 }
3ddea128
MT		 3226 create_irqchip_unlock:
3227 mutex_unlock(&kvm->lock);
1fe779f8 3228 break;
3ddea128 3229 }
7837699f 3230 case KVM_CREATE_PIT:
c5ff41ce
JK		 3231 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3232 goto create_pit;
3233 case KVM_CREATE_PIT2:
3234 r = -EFAULT;
3235 if (copy_from_user(&u.pit_config, argp,
3236 sizeof(struct kvm_pit_config)))
3237 goto out;
3238 create_pit:
79fac95e 3239 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3240 r = -EEXIST;
3241 if (kvm->arch.vpit)
3242 goto create_pit_unlock;
7837699f 3243 r = -ENOMEM;
c5ff41ce 3244 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3245 if (kvm->arch.vpit)
3246 r = 0;
269e05e4 3247 create_pit_unlock:
79fac95e 3248 mutex_unlock(&kvm->slots_lock);
7837699f 3249 break;
4925663a 3250 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3251 case KVM_IRQ_LINE: {
3252 struct kvm_irq_level irq_event;
3253
3254 r = -EFAULT;
3255 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3256 goto out;
160d2f6c 3257 r = -ENXIO;
1fe779f8 3258 if (irqchip_in_kernel(kvm)) {
4925663a 3259 __s32 status;
4925663a
GN		 3260 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3261 irq_event.irq, irq_event.level);
4925663a 3262 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3263 r = -EFAULT;
4925663a
GN		 3264 irq_event.status = status;
3265 if (copy_to_user(argp, &irq_event,
3266 sizeof irq_event))
3267 goto out;
3268 }
1fe779f8
CO		 3269 r = 0;
3270 }
3271 break;
3272 }
3273 case KVM_GET_IRQCHIP: {
3274 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3275 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3276
f0d66275
DH		 3277 r = -ENOMEM;
3278 if (!chip)
1fe779f8 3279 goto out;
f0d66275
DH		 3280 r = -EFAULT;
3281 if (copy_from_user(chip, argp, sizeof *chip))
3282 goto get_irqchip_out;
1fe779f8
CO		 3283 r = -ENXIO;
3284 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3285 goto get_irqchip_out;
3286 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3287 if (r)
f0d66275 3288 goto get_irqchip_out;
1fe779f8 3289 r = -EFAULT;
f0d66275
DH		 3290 if (copy_to_user(argp, chip, sizeof *chip))
3291 goto get_irqchip_out;
1fe779f8 3292 r = 0;
f0d66275
DH		 3293 get_irqchip_out:
3294 kfree(chip);
3295 if (r)
3296 goto out;
1fe779f8
CO		 3297 break;
3298 }
3299 case KVM_SET_IRQCHIP: {
3300 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3301 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3302
f0d66275
DH		 3303 r = -ENOMEM;
3304 if (!chip)
1fe779f8 3305 goto out;
f0d66275
DH		 3306 r = -EFAULT;
3307 if (copy_from_user(chip, argp, sizeof *chip))
3308 goto set_irqchip_out;
1fe779f8
CO		 3309 r = -ENXIO;
3310 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3311 goto set_irqchip_out;
3312 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3313 if (r)
f0d66275 3314 goto set_irqchip_out;
1fe779f8 3315 r = 0;
f0d66275
DH		 3316 set_irqchip_out:
3317 kfree(chip);
3318 if (r)
3319 goto out;
1fe779f8
CO		 3320 break;
3321 }
e0f63cb9 3322 case KVM_GET_PIT: {
e0f63cb9 3323 r = -EFAULT;
f0d66275 3324 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3325 goto out;
3326 r = -ENXIO;
3327 if (!kvm->arch.vpit)
3328 goto out;
f0d66275 3329 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3330 if (r)
3331 goto out;
3332 r = -EFAULT;
f0d66275 3333 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3334 goto out;
3335 r = 0;
3336 break;
3337 }
3338 case KVM_SET_PIT: {
e0f63cb9 3339 r = -EFAULT;
f0d66275 3340 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3341 goto out;
3342 r = -ENXIO;
3343 if (!kvm->arch.vpit)
3344 goto out;
f0d66275 3345 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3346 if (r)
3347 goto out;
3348 r = 0;
3349 break;
3350 }
e9f42757
BK		 3351 case KVM_GET_PIT2: {
3352 r = -ENXIO;
3353 if (!kvm->arch.vpit)
3354 goto out;
3355 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3356 if (r)
3357 goto out;
3358 r = -EFAULT;
3359 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3360 goto out;
3361 r = 0;
3362 break;
3363 }
3364 case KVM_SET_PIT2: {
3365 r = -EFAULT;
3366 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3367 goto out;
3368 r = -ENXIO;
3369 if (!kvm->arch.vpit)
3370 goto out;
3371 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3372 if (r)
3373 goto out;
3374 r = 0;
3375 break;
3376 }
52d939a0
MT		 3377 case KVM_REINJECT_CONTROL: {
3378 struct kvm_reinject_control control;
3379 r = -EFAULT;
3380 if (copy_from_user(&control, argp, sizeof(control)))
3381 goto out;
3382 r = kvm_vm_ioctl_reinject(kvm, &control);
3383 if (r)
3384 goto out;
3385 r = 0;
3386 break;
3387 }
ffde22ac
ES		 3388 case KVM_XEN_HVM_CONFIG: {
3389 r = -EFAULT;
3390 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3391 sizeof(struct kvm_xen_hvm_config)))
3392 goto out;
3393 r = -EINVAL;
3394 if (kvm->arch.xen_hvm_config.flags)
3395 goto out;
3396 r = 0;
3397 break;
3398 }
afbcf7ab 3399 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3400 struct kvm_clock_data user_ns;
3401 u64 now_ns;
3402 s64 delta;
3403
3404 r = -EFAULT;
3405 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3406 goto out;
3407
3408 r = -EINVAL;
3409 if (user_ns.flags)
3410 goto out;
3411
3412 r = 0;
759379dd 3413 now_ns = get_kernel_ns();
afbcf7ab
GC		 3414 delta = user_ns.clock - now_ns;
3415 kvm->arch.kvmclock_offset = delta;
3416 break;
3417 }
3418 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3419 struct kvm_clock_data user_ns;
3420 u64 now_ns;
3421
759379dd 3422 now_ns = get_kernel_ns();
afbcf7ab
GC		 3423 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3424 user_ns.flags = 0;
3425
3426 r = -EFAULT;
3427 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3428 goto out;
3429 r = 0;
3430 break;
3431 }
3432
1fe779f8
CO		 3433 default:
3434 ;
3435 }
3436out:
3437 return r;
3438}
3439
a16b043c 3440static void kvm_init_msr_list(void)
043405e1
CO		 3441{
3442 u32 dummy[2];
3443 unsigned i, j;
3444
e3267cbb
GC		 3445 /* skip the first msrs in the list. KVM-specific */
3446 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3447 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3448 continue;
3449 if (j < i)
3450 msrs_to_save[j] = msrs_to_save[i];
3451 j++;
3452 }
3453 num_msrs_to_save = j;
3454}
3455
bda9020e
MT		 3456static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3457 const void *v)
bbd9b64e 3458{
bda9020e
MT		 3459 if (vcpu->arch.apic &&
3460 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3461 return 0;
bbd9b64e 3462
e93f8a0f 3463 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3464}
3465
bda9020e 3466static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3467{
bda9020e
MT		 3468 if (vcpu->arch.apic &&
3469 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3470 return 0;
bbd9b64e 3471
e93f8a0f 3472 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3473}
3474
2dafc6c2
GN		 3475static void kvm_set_segment(struct kvm_vcpu *vcpu,
3476 struct kvm_segment *var, int seg)
3477{
3478 kvm_x86_ops->set_segment(vcpu, var, seg);
3479}
3480
3481void kvm_get_segment(struct kvm_vcpu *vcpu,
3482 struct kvm_segment *var, int seg)
3483{
3484 kvm_x86_ops->get_segment(vcpu, var, seg);
3485}
3486
c30a358d
JR		 3487static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3488{
3489 return gpa;
3490}
3491
02f59dc9
JR		 3492static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3493{
3494 gpa_t t_gpa;
3495 u32 error;
3496
3497 BUG_ON(!mmu_is_nested(vcpu));
3498
3499 /* NPT walks are always user-walks */
3500 access |= PFERR_USER_MASK;
3501 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &error);
3502 if (t_gpa == UNMAPPED_GVA)
3503 vcpu->arch.fault.error_code |= PFERR_NESTED_MASK;
3504
3505 return t_gpa;
3506}
3507
1871c602
GN		 3508gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3509{
3510 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
14dfe855 3511 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3512}
3513
3514 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3515{
3516 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3517 access |= PFERR_FETCH_MASK;
14dfe855 3518 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3519}
3520
3521gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3522{
3523 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3524 access |= PFERR_WRITE_MASK;
14dfe855 3525 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3526}
3527
3528/* uses this to access any guest's mapped memory without checking CPL */
3529gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3530{
14dfe855 3531 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error);
1871c602
GN		 3532}
3533
3534static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3535 struct kvm_vcpu *vcpu, u32 access,
3536 u32 *error)
bbd9b64e
CO		 3537{
3538 void *data = val;
10589a46 3539 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3540
3541 while (bytes) {
14dfe855
JR		 3542 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3543 error);
bbd9b64e 3544 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3545 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3546 int ret;
3547
10589a46
MT		 3548 if (gpa == UNMAPPED_GVA) {
3549 r = X86EMUL_PROPAGATE_FAULT;
3550 goto out;
3551 }
77c2002e 3552 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3553 if (ret < 0) {
c3cd7ffa 3554 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3555 goto out;
3556 }
bbd9b64e 3557
77c2002e
IE		 3558 bytes -= toread;
3559 data += toread;
3560 addr += toread;
bbd9b64e 3561 }
10589a46 3562out:
10589a46 3563 return r;
bbd9b64e 3564}
77c2002e 3565
1871c602
GN		 3566/* used for instruction fetching */
3567static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3568 struct kvm_vcpu *vcpu, u32 *error)
3569{
3570 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3571 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3572 access | PFERR_FETCH_MASK, error);
3573}
3574
3575static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3576 struct kvm_vcpu *vcpu, u32 *error)
3577{
3578 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3579 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3580 error);
3581}
3582
3583static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3584 struct kvm_vcpu *vcpu, u32 *error)
3585{
3586 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3587}
3588
7972995b 3589static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3590 unsigned int bytes,
7972995b 3591 struct kvm_vcpu *vcpu,
2dafc6c2 3592 u32 *error)
77c2002e
IE		 3593{
3594 void *data = val;
3595 int r = X86EMUL_CONTINUE;
3596
3597 while (bytes) {
14dfe855
JR		 3598 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3599 PFERR_WRITE_MASK,
3600 error);
77c2002e
IE		 3601 unsigned offset = addr & (PAGE_SIZE-1);
3602 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3603 int ret;
3604
3605 if (gpa == UNMAPPED_GVA) {
3606 r = X86EMUL_PROPAGATE_FAULT;
3607 goto out;
3608 }
3609 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3610 if (ret < 0) {
c3cd7ffa 3611 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3612 goto out;
3613 }
3614
3615 bytes -= towrite;
3616 data += towrite;
3617 addr += towrite;
3618 }
3619out:
3620 return r;
3621}
3622
bbd9b64e
CO		 3623static int emulator_read_emulated(unsigned long addr,
3624 void *val,
3625 unsigned int bytes,
8fe681e9 3626 unsigned int *error_code,
bbd9b64e
CO		 3627 struct kvm_vcpu *vcpu)
3628{
bbd9b64e
CO		 3629 gpa_t gpa;
3630
3631 if (vcpu->mmio_read_completed) {
3632 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3633 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3634 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3635 vcpu->mmio_read_completed = 0;
3636 return X86EMUL_CONTINUE;
3637 }
3638
8fe681e9 3639 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3640
8fe681e9 3641 if (gpa == UNMAPPED_GVA)
1871c602 3642 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3643
3644 /* For APIC access vmexit */
3645 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3646 goto mmio;
3647
1871c602 3648 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3649 == X86EMUL_CONTINUE)
bbd9b64e 3650 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3651
3652mmio:
3653 /*
3654 * Is this MMIO handled locally?
3655 */
aec51dc4
AK		 3656 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3657 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3658 return X86EMUL_CONTINUE;
3659 }
aec51dc4
AK		 3660
3661 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3662
3663 vcpu->mmio_needed = 1;
411c35b7
GN		 3664 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3665 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3666 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3667 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3668
c3cd7ffa 3669 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3670}
3671
3200f405 3672int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3673 const void *val, int bytes)
bbd9b64e
CO		 3674{
3675 int ret;
3676
3677 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3678 if (ret < 0)
bbd9b64e 3679 return 0;
ad218f85 3680 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3681 return 1;
3682}
3683
3684static int emulator_write_emulated_onepage(unsigned long addr,
3685 const void *val,
3686 unsigned int bytes,
8fe681e9 3687 unsigned int *error_code,
bbd9b64e
CO		 3688 struct kvm_vcpu *vcpu)
3689{
10589a46
MT		 3690 gpa_t gpa;
3691
8fe681e9 3692 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3693
8fe681e9 3694 if (gpa == UNMAPPED_GVA)
bbd9b64e 3695 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3696
3697 /* For APIC access vmexit */
3698 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3699 goto mmio;
3700
3701 if (emulator_write_phys(vcpu, gpa, val, bytes))
3702 return X86EMUL_CONTINUE;
3703
3704mmio:
aec51dc4 3705 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3706 /*
3707 * Is this MMIO handled locally?
3708 */
bda9020e 3709 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3710 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3711
3712 vcpu->mmio_needed = 1;
411c35b7
GN		 3713 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3714 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3715 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3716 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3717 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3718
3719 return X86EMUL_CONTINUE;
3720}
3721
3722int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3723 const void *val,
3724 unsigned int bytes,
8fe681e9 3725 unsigned int *error_code,
8f6abd06 3726 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3727{
3728 /* Crossing a page boundary? */
3729 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3730 int rc, now;
3731
3732 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3733 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3734 vcpu);
bbd9b64e
CO		 3735 if (rc != X86EMUL_CONTINUE)
3736 return rc;
3737 addr += now;
3738 val += now;
3739 bytes -= now;
3740 }
8fe681e9
GN		 3741 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3742 vcpu);
bbd9b64e 3743}
bbd9b64e 3744
daea3e73
AK		 3745#define CMPXCHG_TYPE(t, ptr, old, new) \
3746 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3747
3748#ifdef CONFIG_X86_64
3749# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3750#else
3751# define CMPXCHG64(ptr, old, new) \
9749a6c0 3752 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3753#endif
3754
bbd9b64e
CO		 3755static int emulator_cmpxchg_emulated(unsigned long addr,
3756 const void *old,
3757 const void *new,
3758 unsigned int bytes,
8fe681e9 3759 unsigned int *error_code,
bbd9b64e
CO		 3760 struct kvm_vcpu *vcpu)
3761{
daea3e73
AK		 3762 gpa_t gpa;
3763 struct page *page;
3764 char *kaddr;
3765 bool exchanged;
2bacc55c 3766
daea3e73
AK		 3767 /* guests cmpxchg8b have to be emulated atomically */
3768 if (bytes > 8 || (bytes & (bytes - 1)))
3769 goto emul_write;
10589a46 3770
daea3e73 3771 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3772
daea3e73
AK		 3773 if (gpa == UNMAPPED_GVA ||
3774 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3775 goto emul_write;
2bacc55c 3776
daea3e73
AK		 3777 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3778 goto emul_write;
72dc67a6 3779
daea3e73 3780 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3781 if (is_error_page(page)) {
3782 kvm_release_page_clean(page);
3783 goto emul_write;
3784 }
72dc67a6 3785
daea3e73
AK		 3786 kaddr = kmap_atomic(page, KM_USER0);
3787 kaddr += offset_in_page(gpa);
3788 switch (bytes) {
3789 case 1:
3790 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3791 break;
3792 case 2:
3793 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3794 break;
3795 case 4:
3796 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3797 break;
3798 case 8:
3799 exchanged = CMPXCHG64(kaddr, old, new);
3800 break;
3801 default:
3802 BUG();
2bacc55c 3803 }
daea3e73
AK		 3804 kunmap_atomic(kaddr, KM_USER0);
3805 kvm_release_page_dirty(page);
3806
3807 if (!exchanged)
3808 return X86EMUL_CMPXCHG_FAILED;
3809
8f6abd06
GN		 3810 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3811
3812 return X86EMUL_CONTINUE;
4a5f48f6 3813
3200f405 3814emul_write:
daea3e73 3815 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3816
8fe681e9 3817 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3818}
3819
cf8f70bf
GN		 3820static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3821{
3822 /* TODO: String I/O for in kernel device */
3823 int r;
3824
3825 if (vcpu->arch.pio.in)
3826 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3827 vcpu->arch.pio.size, pd);
3828 else
3829 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3830 vcpu->arch.pio.port, vcpu->arch.pio.size,
3831 pd);
3832 return r;
3833}
3834
3835
3836static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3837 unsigned int count, struct kvm_vcpu *vcpu)
3838{
7972995b 3839 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3840 goto data_avail;
3841
c41a15dd 3842 trace_kvm_pio(0, port, size, 1);
cf8f70bf
GN		 3843
3844 vcpu->arch.pio.port = port;
3845 vcpu->arch.pio.in = 1;
7972995b 3846 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3847 vcpu->arch.pio.size = size;
3848
3849 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3850 data_avail:
3851 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3852 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3853 return 1;
3854 }
3855
3856 vcpu->run->exit_reason = KVM_EXIT_IO;
3857 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3858 vcpu->run->io.size = size;
3859 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3860 vcpu->run->io.count = count;
3861 vcpu->run->io.port = port;
3862
3863 return 0;
3864}
3865
3866static int emulator_pio_out_emulated(int size, unsigned short port,
3867 const void *val, unsigned int count,
3868 struct kvm_vcpu *vcpu)
3869{
c41a15dd 3870 trace_kvm_pio(1, port, size, 1);
cf8f70bf
GN		 3871
3872 vcpu->arch.pio.port = port;
3873 vcpu->arch.pio.in = 0;
7972995b 3874 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3875 vcpu->arch.pio.size = size;
3876
3877 memcpy(vcpu->arch.pio_data, val, size * count);
3878
3879 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3880 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3881 return 1;
3882 }
3883
3884 vcpu->run->exit_reason = KVM_EXIT_IO;
3885 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3886 vcpu->run->io.size = size;
3887 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3888 vcpu->run->io.count = count;
3889 vcpu->run->io.port = port;
3890
3891 return 0;
3892}
3893
bbd9b64e
CO		 3894static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3895{
3896 return kvm_x86_ops->get_segment_base(vcpu, seg);
3897}
3898
3899int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3900{
a7052897 3901 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3902 return X86EMUL_CONTINUE;
3903}
3904
f5f48ee1
SY		 3905int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3906{
3907 if (!need_emulate_wbinvd(vcpu))
3908 return X86EMUL_CONTINUE;
3909
3910 if (kvm_x86_ops->has_wbinvd_exit()) {
3911 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3912 wbinvd_ipi, NULL, 1);
3913 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3914 }
3915 wbinvd();
3916 return X86EMUL_CONTINUE;
3917}
3918EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3919
bbd9b64e
CO		 3920int emulate_clts(struct kvm_vcpu *vcpu)
3921{
4d4ec087 3922 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3923 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3924 return X86EMUL_CONTINUE;
3925}
3926
35aa5375 3927int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3928{
338dbc97 3929 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3930}
3931
35aa5375 3932int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3933{
338dbc97
GN		 3934
3935 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3936}
3937
52a46617 3938static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3939{
52a46617 3940 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3941}
3942
52a46617 3943static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3944{
52a46617
GN		 3945 unsigned long value;
3946
3947 switch (cr) {
3948 case 0:
3949 value = kvm_read_cr0(vcpu);
3950 break;
3951 case 2:
3952 value = vcpu->arch.cr2;
3953 break;
3954 case 3:
3955 value = vcpu->arch.cr3;
3956 break;
3957 case 4:
3958 value = kvm_read_cr4(vcpu);
3959 break;
3960 case 8:
3961 value = kvm_get_cr8(vcpu);
3962 break;
3963 default:
3964 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3965 return 0;
3966 }
3967
3968 return value;
3969}
3970
0f12244f 3971static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3972{
0f12244f
GN		 3973 int res = 0;
3974
52a46617
GN		 3975 switch (cr) {
3976 case 0:
49a9b07e 3977 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3978 break;
3979 case 2:
3980 vcpu->arch.cr2 = val;
3981 break;
3982 case 3:
2390218b 3983 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 3984 break;
3985 case 4:
a83b29c6 3986 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 3987 break;
3988 case 8:
0f12244f 3989 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 3990 break;
3991 default:
3992 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 3993 res = -1;
52a46617 3994 }
0f12244f
GN		 3995
3996 return res;
52a46617
GN		 3997}
3998
9c537244
GN		 3999static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4000{
4001 return kvm_x86_ops->get_cpl(vcpu);
4002}
4003
2dafc6c2
GN		 4004static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4005{
4006 kvm_x86_ops->get_gdt(vcpu, dt);
4007}
4008
160ce1f1
MG		 4009static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4010{
4011 kvm_x86_ops->get_idt(vcpu, dt);
4012}
4013
5951c442
GN		 4014static unsigned long emulator_get_cached_segment_base(int seg,
4015 struct kvm_vcpu *vcpu)
4016{
4017 return get_segment_base(vcpu, seg);
4018}
4019
2dafc6c2
GN		 4020static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4021 struct kvm_vcpu *vcpu)
4022{
4023 struct kvm_segment var;
4024
4025 kvm_get_segment(vcpu, &var, seg);
4026
4027 if (var.unusable)
4028 return false;
4029
4030 if (var.g)
4031 var.limit >>= 12;
4032 set_desc_limit(desc, var.limit);
4033 set_desc_base(desc, (unsigned long)var.base);
4034 desc->type = var.type;
4035 desc->s = var.s;
4036 desc->dpl = var.dpl;
4037 desc->p = var.present;
4038 desc->avl = var.avl;
4039 desc->l = var.l;
4040 desc->d = var.db;
4041 desc->g = var.g;
4042
4043 return true;
4044}
4045
4046static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4047 struct kvm_vcpu *vcpu)
4048{
4049 struct kvm_segment var;
4050
4051 /* needed to preserve selector */
4052 kvm_get_segment(vcpu, &var, seg);
4053
4054 var.base = get_desc_base(desc);
4055 var.limit = get_desc_limit(desc);
4056 if (desc->g)
4057 var.limit = (var.limit << 12) | 0xfff;
4058 var.type = desc->type;
4059 var.present = desc->p;
4060 var.dpl = desc->dpl;
4061 var.db = desc->d;
4062 var.s = desc->s;
4063 var.l = desc->l;
4064 var.g = desc->g;
4065 var.avl = desc->avl;
4066 var.present = desc->p;
4067 var.unusable = !var.present;
4068 var.padding = 0;
4069
4070 kvm_set_segment(vcpu, &var, seg);
4071 return;
4072}
4073
4074static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4075{
4076 struct kvm_segment kvm_seg;
4077
4078 kvm_get_segment(vcpu, &kvm_seg, seg);
4079 return kvm_seg.selector;
4080}
4081
4082static void emulator_set_segment_selector(u16 sel, int seg,
4083 struct kvm_vcpu *vcpu)
4084{
4085 struct kvm_segment kvm_seg;
4086
4087 kvm_get_segment(vcpu, &kvm_seg, seg);
4088 kvm_seg.selector = sel;
4089 kvm_set_segment(vcpu, &kvm_seg, seg);
4090}
4091
14af3f3c 4092static struct x86_emulate_ops emulate_ops = {
1871c602 4093 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4094 .write_std = kvm_write_guest_virt_system,
1871c602 4095 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4096 .read_emulated = emulator_read_emulated,
4097 .write_emulated = emulator_write_emulated,
4098 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4099 .pio_in_emulated = emulator_pio_in_emulated,
4100 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4101 .get_cached_descriptor = emulator_get_cached_descriptor,
4102 .set_cached_descriptor = emulator_set_cached_descriptor,
4103 .get_segment_selector = emulator_get_segment_selector,
4104 .set_segment_selector = emulator_set_segment_selector,
5951c442 4105 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4106 .get_gdt = emulator_get_gdt,
160ce1f1 4107 .get_idt = emulator_get_idt,
52a46617
GN		 4108 .get_cr = emulator_get_cr,
4109 .set_cr = emulator_set_cr,
9c537244 4110 .cpl = emulator_get_cpl,
35aa5375
GN		 4111 .get_dr = emulator_get_dr,
4112 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4113 .set_msr = kvm_set_msr,
4114 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4115};
4116
5fdbf976
MT		 4117static void cache_all_regs(struct kvm_vcpu *vcpu)
4118{
4119 kvm_register_read(vcpu, VCPU_REGS_RAX);
4120 kvm_register_read(vcpu, VCPU_REGS_RSP);
4121 kvm_register_read(vcpu, VCPU_REGS_RIP);
4122 vcpu->arch.regs_dirty = ~0;
4123}
4124
95cb2295
GN		 4125static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4126{
4127 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4128 /*
4129 * an sti; sti; sequence only disable interrupts for the first
4130 * instruction. So, if the last instruction, be it emulated or
4131 * not, left the system with the INT_STI flag enabled, it
4132 * means that the last instruction is an sti. We should not
4133 * leave the flag on in this case. The same goes for mov ss
4134 */
4135 if (!(int_shadow & mask))
4136 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4137}
4138
54b8486f
GN		 4139static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4140{
4141 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4142 if (ctxt->exception == PF_VECTOR)
8df25a32 4143 kvm_inject_page_fault(vcpu);
54b8486f
GN		 4144 else if (ctxt->error_code_valid)
4145 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4146 else
4147 kvm_queue_exception(vcpu, ctxt->exception);
4148}
4149
8ec4722d
MG		 4150static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4151{
4152 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4153 int cs_db, cs_l;
4154
4155 cache_all_regs(vcpu);
4156
4157 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4158
4159 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4160 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4161 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4162 vcpu->arch.emulate_ctxt.mode =
4163 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4164 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4165 ? X86EMUL_MODE_VM86 : cs_l
4166 ? X86EMUL_MODE_PROT64 : cs_db
4167 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4168 memset(c, 0, sizeof(struct decode_cache));
4169 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4170}
4171
6d77dbfc
GN		 4172static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4173{
6d77dbfc
GN		 4174 ++vcpu->stat.insn_emulation_fail;
4175 trace_kvm_emulate_insn_failed(vcpu);
4176 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4177 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4178 vcpu->run->internal.ndata = 0;
4179 kvm_queue_exception(vcpu, UD_VECTOR);
4180 return EMULATE_FAIL;
4181}
4182
a6f177ef
GN		 4183static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4184{
4185 gpa_t gpa;
4186
68be0803
GN		 4187 if (tdp_enabled)
4188 return false;
4189
a6f177ef
GN		 4190 /*
4191 * if emulation was due to access to shadowed page table
4192 * and it failed try to unshadow page and re-entetr the
4193 * guest to let CPU execute the instruction.
4194 */
4195 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4196 return true;
4197
4198 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4199
4200 if (gpa == UNMAPPED_GVA)
4201 return true; /* let cpu generate fault */
4202
4203 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4204 return true;
4205
4206 return false;
4207}
4208
bbd9b64e 4209int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4210 unsigned long cr2,
4211 u16 error_code,
571008da 4212 int emulation_type)
bbd9b64e 4213{
95cb2295 4214 int r;
4d2179e1 4215 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4216
26eef70c 4217 kvm_clear_exception_queue(vcpu);
ad312c7c 4218 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4219 /*
56e82318 4220 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4221 * instead of direct ->regs accesses, can save hundred cycles
4222 * on Intel for instructions that don't read/change RSP, for
4223 * for example.
4224 */
4225 cache_all_regs(vcpu);
bbd9b64e 4226
571008da 4227 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4228 init_emulate_ctxt(vcpu);
95cb2295 4229 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4230 vcpu->arch.emulate_ctxt.exception = -1;
4fc40f07 4231 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4232
9aabc88f 4233 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
e46479f8 4234 trace_kvm_emulate_insn_start(vcpu);
571008da 4235
0cb5762e
AP		 4236 /* Only allow emulation of specific instructions on #UD
4237 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4238 if (emulation_type & EMULTYPE_TRAP_UD) {
4239 if (!c->twobyte)
4240 return EMULATE_FAIL;
4241 switch (c->b) {
4242 case 0x01: /* VMMCALL */
4243 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4244 return EMULATE_FAIL;
4245 break;
4246 case 0x34: /* sysenter */
4247 case 0x35: /* sysexit */
4248 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4249 return EMULATE_FAIL;
4250 break;
4251 case 0x05: /* syscall */
4252 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4253 return EMULATE_FAIL;
4254 break;
4255 default:
4256 return EMULATE_FAIL;
4257 }
4258
4259 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4260 return EMULATE_FAIL;
4261 }
571008da 4262
f2b5756b 4263 ++vcpu->stat.insn_emulation;
bbd9b64e 4264 if (r) {
a6f177ef 4265 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4266 return EMULATE_DONE;
6d77dbfc
GN		 4267 if (emulation_type & EMULTYPE_SKIP)
4268 return EMULATE_FAIL;
4269 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4270 }
4271 }
4272
ba8afb6b
GN		 4273 if (emulation_type & EMULTYPE_SKIP) {
4274 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4275 return EMULATE_DONE;
4276 }
4277
4d2179e1
GN		 4278 /* this is needed for vmware backdor interface to work since it
4279 changes registers values during IO operation */
4280 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4281
5cd21917 4282restart:
9aabc88f 4283 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4284
d2ddd1c4 4285 if (r == EMULATION_FAILED) {
a6f177ef 4286 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4287 return EMULATE_DONE;
4288
6d77dbfc 4289 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4290 }
4291
d2ddd1c4 4292 if (vcpu->arch.emulate_ctxt.exception >= 0) {
54b8486f 4293 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4294 r = EMULATE_DONE;
4295 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4296 if (!vcpu->arch.pio.in)
4297 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4298 r = EMULATE_DO_MMIO;
4299 } else if (vcpu->mmio_needed) {
3457e419
GN		 4300 if (vcpu->mmio_is_write)
4301 vcpu->mmio_needed = 0;
e85d28f8 4302 r = EMULATE_DO_MMIO;
d2ddd1c4 4303 } else if (r == EMULATION_RESTART)
5cd21917 4304 goto restart;
d2ddd1c4
GN		 4305 else
4306 r = EMULATE_DONE;
f850e2e6 4307
e85d28f8
GN		 4308 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4309 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4310 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4311 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4312
4313 return r;
de7d789a 4314}
bbd9b64e 4315EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4316
cf8f70bf 4317int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4318{
cf8f70bf
GN		 4319 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4320 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4321 /* do not return to emulator after return from userspace */
7972995b 4322 vcpu->arch.pio.count = 0;
de7d789a
CO		 4323 return ret;
4324}
cf8f70bf 4325EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4326
8cfdc000
ZA		 4327static void tsc_bad(void *info)
4328{
4329 __get_cpu_var(cpu_tsc_khz) = 0;
4330}
4331
4332static void tsc_khz_changed(void *data)
c8076604 4333{
8cfdc000
ZA		 4334 struct cpufreq_freqs *freq = data;
4335 unsigned long khz = 0;
4336
4337 if (data)
4338 khz = freq->new;
4339 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4340 khz = cpufreq_quick_get(raw_smp_processor_id());
4341 if (!khz)
4342 khz = tsc_khz;
4343 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4344}
4345
c8076604
GH		 4346static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4347 void *data)
4348{
4349 struct cpufreq_freqs *freq = data;
4350 struct kvm *kvm;
4351 struct kvm_vcpu *vcpu;
4352 int i, send_ipi = 0;
4353
8cfdc000
ZA		 4354 /*
4355 * We allow guests to temporarily run on slowing clocks,
4356 * provided we notify them after, or to run on accelerating
4357 * clocks, provided we notify them before. Thus time never
4358 * goes backwards.
4359 *
4360 * However, we have a problem. We can't atomically update
4361 * the frequency of a given CPU from this function; it is
4362 * merely a notifier, which can be called from any CPU.
4363 * Changing the TSC frequency at arbitrary points in time
4364 * requires a recomputation of local variables related to
4365 * the TSC for each VCPU. We must flag these local variables
4366 * to be updated and be sure the update takes place with the
4367 * new frequency before any guests proceed.
4368 *
4369 * Unfortunately, the combination of hotplug CPU and frequency
4370 * change creates an intractable locking scenario; the order
4371 * of when these callouts happen is undefined with respect to
4372 * CPU hotplug, and they can race with each other. As such,
4373 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4374 * undefined; you can actually have a CPU frequency change take
4375 * place in between the computation of X and the setting of the
4376 * variable. To protect against this problem, all updates of
4377 * the per_cpu tsc_khz variable are done in an interrupt
4378 * protected IPI, and all callers wishing to update the value
4379 * must wait for a synchronous IPI to complete (which is trivial
4380 * if the caller is on the CPU already). This establishes the
4381 * necessary total order on variable updates.
4382 *
4383 * Note that because a guest time update may take place
4384 * anytime after the setting of the VCPU's request bit, the
4385 * correct TSC value must be set before the request. However,
4386 * to ensure the update actually makes it to any guest which
4387 * starts running in hardware virtualization between the set
4388 * and the acquisition of the spinlock, we must also ping the
4389 * CPU after setting the request bit.
4390 *
4391 */
4392
c8076604
GH		 4393 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4394 return 0;
4395 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4396 return 0;
8cfdc000
ZA		 4397
4398 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4399
4400 spin_lock(&kvm_lock);
4401 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4402 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4403 if (vcpu->cpu != freq->cpu)
4404 continue;
4405 if (!kvm_request_guest_time_update(vcpu))
4406 continue;
4407 if (vcpu->cpu != smp_processor_id())
8cfdc000 4408 send_ipi = 1;
c8076604
GH		 4409 }
4410 }
4411 spin_unlock(&kvm_lock);
4412
4413 if (freq->old < freq->new && send_ipi) {
4414 /*
4415 * We upscale the frequency. Must make the guest
4416 * doesn't see old kvmclock values while running with
4417 * the new frequency, otherwise we risk the guest sees
4418 * time go backwards.
4419 *
4420 * In case we update the frequency for another cpu
4421 * (which might be in guest context) send an interrupt
4422 * to kick the cpu out of guest context. Next time
4423 * guest context is entered kvmclock will be updated,
4424 * so the guest will not see stale values.
4425 */
8cfdc000 4426 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4427 }
4428 return 0;
4429}
4430
4431static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4432 .notifier_call = kvmclock_cpufreq_notifier
4433};
4434
4435static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4436 unsigned long action, void *hcpu)
4437{
4438 unsigned int cpu = (unsigned long)hcpu;
4439
4440 switch (action) {
4441 case CPU_ONLINE:
4442 case CPU_DOWN_FAILED:
4443 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4444 break;
4445 case CPU_DOWN_PREPARE:
4446 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4447 break;
4448 }
4449 return NOTIFY_OK;
4450}
4451
4452static struct notifier_block kvmclock_cpu_notifier_block = {
4453 .notifier_call = kvmclock_cpu_notifier,
4454 .priority = -INT_MAX
c8076604
GH		 4455};
4456
b820cc0c
ZA		 4457static void kvm_timer_init(void)
4458{
4459 int cpu;
4460
8cfdc000 4461 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4462 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4463 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4464 CPUFREQ_TRANSITION_NOTIFIER);
4465 }
8cfdc000
ZA		 4466 for_each_online_cpu(cpu)
4467 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4468}
4469
ff9d07a0
ZY		 4470static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4471
4472static int kvm_is_in_guest(void)
4473{
4474 return percpu_read(current_vcpu) != NULL;
4475}
4476
4477static int kvm_is_user_mode(void)
4478{
4479 int user_mode = 3;
dcf46b94 4480
ff9d07a0
ZY		 4481 if (percpu_read(current_vcpu))
4482 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4483
ff9d07a0
ZY		 4484 return user_mode != 0;
4485}
4486
4487static unsigned long kvm_get_guest_ip(void)
4488{
4489 unsigned long ip = 0;
dcf46b94 4490
ff9d07a0
ZY		 4491 if (percpu_read(current_vcpu))
4492 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4493
ff9d07a0
ZY		 4494 return ip;
4495}
4496
4497static struct perf_guest_info_callbacks kvm_guest_cbs = {
4498 .is_in_guest = kvm_is_in_guest,
4499 .is_user_mode = kvm_is_user_mode,
4500 .get_guest_ip = kvm_get_guest_ip,
4501};
4502
4503void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4504{
4505 percpu_write(current_vcpu, vcpu);
4506}
4507EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4508
4509void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4510{
4511 percpu_write(current_vcpu, NULL);
4512}
4513EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4514
f8c16bba 4515int kvm_arch_init(void *opaque)
043405e1 4516{
b820cc0c 4517 int r;
f8c16bba
ZX		 4518 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4519
f8c16bba
ZX		 4520 if (kvm_x86_ops) {
4521 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4522 r = -EEXIST;
4523 goto out;
f8c16bba
ZX		 4524 }
4525
4526 if (!ops->cpu_has_kvm_support()) {
4527 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4528 r = -EOPNOTSUPP;
4529 goto out;
f8c16bba
ZX		 4530 }
4531 if (ops->disabled_by_bios()) {
4532 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4533 r = -EOPNOTSUPP;
4534 goto out;
f8c16bba
ZX		 4535 }
4536
97db56ce
AK		 4537 r = kvm_mmu_module_init();
4538 if (r)
4539 goto out;
4540
4541 kvm_init_msr_list();
4542
f8c16bba 4543 kvm_x86_ops = ops;
56c6d28a 4544 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4545 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4546 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4547 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4548
b820cc0c 4549 kvm_timer_init();
c8076604 4550
ff9d07a0
ZY		 4551 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4552
2acf923e
DC		 4553 if (cpu_has_xsave)
4554 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4555
f8c16bba 4556 return 0;
56c6d28a
ZX		 4557
4558out:
56c6d28a 4559 return r;
043405e1 4560}
8776e519 4561
f8c16bba
ZX		 4562void kvm_arch_exit(void)
4563{
ff9d07a0
ZY		 4564 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4565
888d256e
JK		 4566 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4567 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4568 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4569 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4570 kvm_x86_ops = NULL;
56c6d28a
ZX		 4571 kvm_mmu_module_exit();
4572}
f8c16bba 4573
8776e519
HB		 4574int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4575{
4576 ++vcpu->stat.halt_exits;
4577 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4578 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4579 return 1;
4580 } else {
4581 vcpu->run->exit_reason = KVM_EXIT_HLT;
4582 return 0;
4583 }
4584}
4585EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4586
2f333bcb
MT		 4587static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4588 unsigned long a1)
4589{
4590 if (is_long_mode(vcpu))
4591 return a0;
4592 else
4593 return a0 | ((gpa_t)a1 << 32);
4594}
4595
55cd8e5a
GN		 4596int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4597{
4598 u64 param, ingpa, outgpa, ret;
4599 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4600 bool fast, longmode;
4601 int cs_db, cs_l;
4602
4603 /*
4604 * hypercall generates UD from non zero cpl and real mode
4605 * per HYPER-V spec
4606 */
3eeb3288 4607 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4608 kvm_queue_exception(vcpu, UD_VECTOR);
4609 return 0;
4610 }
4611
4612 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4613 longmode = is_long_mode(vcpu) && cs_l == 1;
4614
4615 if (!longmode) {
ccd46936
GN		 4616 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4617 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4618 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4619 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4620 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4621 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4622 }
4623#ifdef CONFIG_X86_64
4624 else {
4625 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4626 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4627 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4628 }
4629#endif
4630
4631 code = param & 0xffff;
4632 fast = (param >> 16) & 0x1;
4633 rep_cnt = (param >> 32) & 0xfff;
4634 rep_idx = (param >> 48) & 0xfff;
4635
4636 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4637
c25bc163
GN		 4638 switch (code) {
4639 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4640 kvm_vcpu_on_spin(vcpu);
4641 break;
4642 default:
4643 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4644 break;
4645 }
55cd8e5a
GN		 4646
4647 ret = res | (((u64)rep_done & 0xfff) << 32);
4648 if (longmode) {
4649 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4650 } else {
4651 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4652 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4653 }
4654
4655 return 1;
4656}
4657
8776e519
HB		 4658int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4659{
4660 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4661 int r = 1;
8776e519 4662
55cd8e5a
GN		 4663 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4664 return kvm_hv_hypercall(vcpu);
4665
5fdbf976
MT		 4666 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4667 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4668 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4669 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4670 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4671
229456fc 4672 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4673
8776e519
HB		 4674 if (!is_long_mode(vcpu)) {
4675 nr &= 0xFFFFFFFF;
4676 a0 &= 0xFFFFFFFF;
4677 a1 &= 0xFFFFFFFF;
4678 a2 &= 0xFFFFFFFF;
4679 a3 &= 0xFFFFFFFF;
4680 }
4681
07708c4a
JK		 4682 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4683 ret = -KVM_EPERM;
4684 goto out;
4685 }
4686
8776e519 4687 switch (nr) {
b93463aa
AK		 4688 case KVM_HC_VAPIC_POLL_IRQ:
4689 ret = 0;
4690 break;
2f333bcb
MT		 4691 case KVM_HC_MMU_OP:
4692 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4693 break;
8776e519
HB		 4694 default:
4695 ret = -KVM_ENOSYS;
4696 break;
4697 }
07708c4a 4698out:
5fdbf976 4699 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4700 ++vcpu->stat.hypercalls;
2f333bcb 4701 return r;
8776e519
HB		 4702}
4703EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4704
4705int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4706{
4707 char instruction[3];
5fdbf976 4708 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4709
8776e519
HB		 4710 /*
4711 * Blow out the MMU to ensure that no other VCPU has an active mapping
4712 * to ensure that the updated hypercall appears atomically across all
4713 * VCPUs.
4714 */
4715 kvm_mmu_zap_all(vcpu->kvm);
4716
8776e519 4717 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4718
8fe681e9 4719 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4720}
4721
8776e519
HB		 4722void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4723{
89a27f4d 4724 struct desc_ptr dt = { limit, base };
8776e519
HB		 4725
4726 kvm_x86_ops->set_gdt(vcpu, &dt);
4727}
4728
4729void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4730{
89a27f4d 4731 struct desc_ptr dt = { limit, base };
8776e519
HB		 4732
4733 kvm_x86_ops->set_idt(vcpu, &dt);
4734}
4735
07716717
DK		 4736static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4737{
ad312c7c
ZX		 4738 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4739 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4740
4741 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4742 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4743 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4744 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4745 if (ej->function == e->function) {
4746 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4747 return j;
4748 }
4749 }
4750 return 0; /* silence gcc, even though control never reaches here */
4751}
4752
4753/* find an entry with matching function, matching index (if needed), and that
4754 * should be read next (if it's stateful) */
4755static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4756 u32 function, u32 index)
4757{
4758 if (e->function != function)
4759 return 0;
4760 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4761 return 0;
4762 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4763 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4764 return 0;
4765 return 1;
4766}
4767
d8017474
AG		 4768struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4769 u32 function, u32 index)
8776e519
HB		 4770{
4771 int i;
d8017474 4772 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4773
ad312c7c 4774 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4775 struct kvm_cpuid_entry2 *e;
4776
ad312c7c 4777 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4778 if (is_matching_cpuid_entry(e, function, index)) {
4779 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4780 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4781 best = e;
4782 break;
4783 }
4784 /*
4785 * Both basic or both extended?
4786 */
4787 if (((e->function ^ function) & 0x80000000) == 0)
4788 if (!best || e->function > best->function)
4789 best = e;
4790 }
d8017474
AG		 4791 return best;
4792}
0e851880 4793EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4794
82725b20
DE		 4795int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4796{
4797 struct kvm_cpuid_entry2 *best;
4798
f7a71197
AK		 4799 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4800 if (!best || best->eax < 0x80000008)
4801 goto not_found;
82725b20
DE		 4802 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4803 if (best)
4804 return best->eax & 0xff;
f7a71197 4805not_found:
82725b20
DE		 4806 return 36;
4807}
4808
d8017474
AG		 4809void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4810{
4811 u32 function, index;
4812 struct kvm_cpuid_entry2 *best;
4813
4814 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4815 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4816 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4817 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4818 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4819 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4820 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4821 if (best) {
5fdbf976
MT		 4822 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4823 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4824 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4825 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4826 }
8776e519 4827 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4828 trace_kvm_cpuid(function,
4829 kvm_register_read(vcpu, VCPU_REGS_RAX),
4830 kvm_register_read(vcpu, VCPU_REGS_RBX),
4831 kvm_register_read(vcpu, VCPU_REGS_RCX),
4832 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4833}
4834EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4835
b6c7a5dc
HB		 4836/*
4837 * Check if userspace requested an interrupt window, and that the
4838 * interrupt window is open.
4839 *
4840 * No need to exit to userspace if we already have an interrupt queued.
4841 */
851ba692 4842static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4843{
8061823a 4844 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4845 vcpu->run->request_interrupt_window &&
5df56646 4846 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4847}
4848
851ba692 4849static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4850{
851ba692
AK		 4851 struct kvm_run *kvm_run = vcpu->run;
4852
91586a3b 4853 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4854 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4855 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4856 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4857 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4858 else
b6c7a5dc 4859 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4860 kvm_arch_interrupt_allowed(vcpu) &&
4861 !kvm_cpu_has_interrupt(vcpu) &&
4862 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4863}
4864
b93463aa
AK		 4865static void vapic_enter(struct kvm_vcpu *vcpu)
4866{
4867 struct kvm_lapic *apic = vcpu->arch.apic;
4868 struct page *page;
4869
4870 if (!apic || !apic->vapic_addr)
4871 return;
4872
4873 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4874
4875 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4876}
4877
4878static void vapic_exit(struct kvm_vcpu *vcpu)
4879{
4880 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4881 int idx;
b93463aa
AK		 4882
4883 if (!apic || !apic->vapic_addr)
4884 return;
4885
f656ce01 4886 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4887 kvm_release_page_dirty(apic->vapic_page);
4888 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4889 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4890}
4891
95ba8273
GN		 4892static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4893{
4894 int max_irr, tpr;
4895
4896 if (!kvm_x86_ops->update_cr8_intercept)
4897 return;
4898
88c808fd
AK		 4899 if (!vcpu->arch.apic)
4900 return;
4901
8db3baa2
GN		 4902 if (!vcpu->arch.apic->vapic_addr)
4903 max_irr = kvm_lapic_find_highest_irr(vcpu);
4904 else
4905 max_irr = -1;
95ba8273
GN		 4906
4907 if (max_irr != -1)
4908 max_irr >>= 4;
4909
4910 tpr = kvm_lapic_get_cr8(vcpu);
4911
4912 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4913}
4914
851ba692 4915static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4916{
4917 /* try to reinject previous events if any */
b59bb7bd 4918 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4919 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4920 vcpu->arch.exception.has_error_code,
4921 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4922 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4923 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4924 vcpu->arch.exception.error_code,
4925 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4926 return;
4927 }
4928
95ba8273
GN		 4929 if (vcpu->arch.nmi_injected) {
4930 kvm_x86_ops->set_nmi(vcpu);
4931 return;
4932 }
4933
4934 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4935 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4936 return;
4937 }
4938
4939 /* try to inject new event if pending */
4940 if (vcpu->arch.nmi_pending) {
4941 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4942 vcpu->arch.nmi_pending = false;
4943 vcpu->arch.nmi_injected = true;
4944 kvm_x86_ops->set_nmi(vcpu);
4945 }
4946 } else if (kvm_cpu_has_interrupt(vcpu)) {
4947 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4948 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4949 false);
4950 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4951 }
4952 }
4953}
4954
2acf923e
DC		 4955static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
4956{
4957 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
4958 !vcpu->guest_xcr0_loaded) {
4959 /* kvm_set_xcr() also depends on this */
4960 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
4961 vcpu->guest_xcr0_loaded = 1;
4962 }
4963}
4964
4965static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
4966{
4967 if (vcpu->guest_xcr0_loaded) {
4968 if (vcpu->arch.xcr0 != host_xcr0)
4969 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
4970 vcpu->guest_xcr0_loaded = 0;
4971 }
4972}
4973
851ba692 4974static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4975{
4976 int r;
6a8b1d13 4977 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4978 vcpu->run->request_interrupt_window;
b6c7a5dc 4979
3e007509 4980 if (vcpu->requests) {
a8eeb04a 4981 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 4982 kvm_mmu_unload(vcpu);
a8eeb04a 4983 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 4984 __kvm_migrate_timers(vcpu);
8cfdc000
ZA		 4985 if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu)) {
4986 r = kvm_write_guest_time(vcpu);
4987 if (unlikely(r))
4988 goto out;
4989 }
a8eeb04a 4990 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 4991 kvm_mmu_sync_roots(vcpu);
a8eeb04a 4992 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 4993 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 4994 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 4995 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4996 r = 0;
4997 goto out;
4998 }
a8eeb04a 4999 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5000 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5001 r = 0;
5002 goto out;
5003 }
a8eeb04a 5004 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5005 vcpu->fpu_active = 0;
5006 kvm_x86_ops->fpu_deactivate(vcpu);
5007 }
2f52d58c 5008 }
b93463aa 5009
3e007509
AK		 5010 r = kvm_mmu_reload(vcpu);
5011 if (unlikely(r))
5012 goto out;
5013
b6c7a5dc
HB		 5014 preempt_disable();
5015
5016 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5017 if (vcpu->fpu_active)
5018 kvm_load_guest_fpu(vcpu);
2acf923e 5019 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5020
d94e1dc9
AK		 5021 atomic_set(&vcpu->guest_mode, 1);
5022 smp_wmb();
b6c7a5dc 5023
d94e1dc9 5024 local_irq_disable();
32f88400 5025
d94e1dc9
AK		 5026 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5027 || need_resched() || signal_pending(current)) {
5028 atomic_set(&vcpu->guest_mode, 0);
5029 smp_wmb();
6c142801
AK		 5030 local_irq_enable();
5031 preempt_enable();
5032 r = 1;
5033 goto out;
5034 }
5035
851ba692 5036 inject_pending_event(vcpu);
b6c7a5dc 5037
6a8b1d13
GN		 5038 /* enable NMI/IRQ window open exits if needed */
5039 if (vcpu->arch.nmi_pending)
5040 kvm_x86_ops->enable_nmi_window(vcpu);
5041 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5042 kvm_x86_ops->enable_irq_window(vcpu);
5043
95ba8273 5044 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 5045 update_cr8_intercept(vcpu);
5046 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 5047 }
b93463aa 5048
f656ce01 5049 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5050
b6c7a5dc
HB		 5051 kvm_guest_enter();
5052
42dbaa5a 5053 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5054 set_debugreg(0, 7);
5055 set_debugreg(vcpu->arch.eff_db[0], 0);
5056 set_debugreg(vcpu->arch.eff_db[1], 1);
5057 set_debugreg(vcpu->arch.eff_db[2], 2);
5058 set_debugreg(vcpu->arch.eff_db[3], 3);
5059 }
b6c7a5dc 5060
229456fc 5061 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5062 kvm_x86_ops->run(vcpu);
b6c7a5dc 5063
24f1e32c
FW		 5064 /*
5065 * If the guest has used debug registers, at least dr7
5066 * will be disabled while returning to the host.
5067 * If we don't have active breakpoints in the host, we don't
5068 * care about the messed up debug address registers. But if
5069 * we have some of them active, restore the old state.
5070 */
59d8eb53 5071 if (hw_breakpoint_active())
24f1e32c 5072 hw_breakpoint_restore();
42dbaa5a 5073
1d5f066e
ZA		 5074 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5075
d94e1dc9
AK		 5076 atomic_set(&vcpu->guest_mode, 0);
5077 smp_wmb();
b6c7a5dc
HB		 5078 local_irq_enable();
5079
5080 ++vcpu->stat.exits;
5081
5082 /*
5083 * We must have an instruction between local_irq_enable() and
5084 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5085 * the interrupt shadow. The stat.exits increment will do nicely.
5086 * But we need to prevent reordering, hence this barrier():
5087 */
5088 barrier();
5089
5090 kvm_guest_exit();
5091
5092 preempt_enable();
5093
f656ce01 5094 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5095
b6c7a5dc
HB		 5096 /*
5097 * Profile KVM exit RIPs:
5098 */
5099 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5100 unsigned long rip = kvm_rip_read(vcpu);
5101 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5102 }
5103
298101da 5104
b93463aa
AK		 5105 kvm_lapic_sync_from_vapic(vcpu);
5106
851ba692 5107 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5108out:
5109 return r;
5110}
b6c7a5dc 5111
09cec754 5112
851ba692 5113static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5114{
5115 int r;
f656ce01 5116 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5117
5118 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5119 pr_debug("vcpu %d received sipi with vector # %x\n",
5120 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5121 kvm_lapic_reset(vcpu);
5f179287 5122 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5123 if (r)
5124 return r;
5125 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5126 }
5127
f656ce01 5128 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5129 vapic_enter(vcpu);
5130
5131 r = 1;
5132 while (r > 0) {
af2152f5 5133 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 5134 r = vcpu_enter_guest(vcpu);
d7690175 5135 else {
f656ce01 5136 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5137 kvm_vcpu_block(vcpu);
f656ce01 5138 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5139 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5140 {
5141 switch(vcpu->arch.mp_state) {
5142 case KVM_MP_STATE_HALTED:
d7690175 5143 vcpu->arch.mp_state =
09cec754
GN		 5144 KVM_MP_STATE_RUNNABLE;
5145 case KVM_MP_STATE_RUNNABLE:
5146 break;
5147 case KVM_MP_STATE_SIPI_RECEIVED:
5148 default:
5149 r = -EINTR;
5150 break;
5151 }
5152 }
d7690175
MT		 5153 }
5154
09cec754
GN		 5155 if (r <= 0)
5156 break;
5157
5158 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5159 if (kvm_cpu_has_pending_timer(vcpu))
5160 kvm_inject_pending_timer_irqs(vcpu);
5161
851ba692 5162 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5163 r = -EINTR;
851ba692 5164 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5165 ++vcpu->stat.request_irq_exits;
5166 }
5167 if (signal_pending(current)) {
5168 r = -EINTR;
851ba692 5169 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5170 ++vcpu->stat.signal_exits;
5171 }
5172 if (need_resched()) {
f656ce01 5173 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5174 kvm_resched(vcpu);
f656ce01 5175 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5176 }
b6c7a5dc
HB		 5177 }
5178
f656ce01 5179 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5180
b93463aa
AK		 5181 vapic_exit(vcpu);
5182
b6c7a5dc
HB		 5183 return r;
5184}
5185
5186int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5187{
5188 int r;
5189 sigset_t sigsaved;
5190
ac9f6dc0
AK		 5191 if (vcpu->sigset_active)
5192 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5193
a4535290 5194 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5195 kvm_vcpu_block(vcpu);
d7690175 5196 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5197 r = -EAGAIN;
5198 goto out;
b6c7a5dc
HB		 5199 }
5200
b6c7a5dc
HB		 5201 /* re-sync apic's tpr */
5202 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5203 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5204
d2ddd1c4 5205 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5206 if (vcpu->mmio_needed) {
5207 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5208 vcpu->mmio_read_completed = 1;
5209 vcpu->mmio_needed = 0;
b6c7a5dc 5210 }
f656ce01 5211 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5212 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5213 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5214 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5215 r = 0;
5216 goto out;
5217 }
5218 }
5fdbf976
MT		 5219 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5220 kvm_register_write(vcpu, VCPU_REGS_RAX,
5221 kvm_run->hypercall.ret);
b6c7a5dc 5222
851ba692 5223 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5224
5225out:
f1d86e46 5226 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5227 if (vcpu->sigset_active)
5228 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5229
b6c7a5dc
HB		 5230 return r;
5231}
5232
5233int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5234{
5fdbf976
MT		 5235 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5236 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5237 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5238 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5239 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5240 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5241 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5242 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5243#ifdef CONFIG_X86_64
5fdbf976
MT		 5244 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5245 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5246 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5247 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5248 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5249 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5250 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5251 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5252#endif
5253
5fdbf976 5254 regs->rip = kvm_rip_read(vcpu);
91586a3b 5255 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5256
b6c7a5dc
HB		 5257 return 0;
5258}
5259
5260int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5261{
5fdbf976
MT		 5262 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5263 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5264 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5265 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5266 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5267 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5268 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5269 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5270#ifdef CONFIG_X86_64
5fdbf976
MT		 5271 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5272 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5273 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5274 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5275 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5276 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5277 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5278 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5279#endif
5280
5fdbf976 5281 kvm_rip_write(vcpu, regs->rip);
91586a3b 5282 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5283
b4f14abd
JK		 5284 vcpu->arch.exception.pending = false;
5285
b6c7a5dc
HB		 5286 return 0;
5287}
5288
b6c7a5dc
HB		 5289void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5290{
5291 struct kvm_segment cs;
5292
3e6e0aab 5293 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5294 *db = cs.db;
5295 *l = cs.l;
5296}
5297EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5298
5299int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5300 struct kvm_sregs *sregs)
5301{
89a27f4d 5302 struct desc_ptr dt;
b6c7a5dc 5303
3e6e0aab
GT		 5304 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5305 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5306 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5307 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5308 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5309 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5310
3e6e0aab
GT		 5311 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5312 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5313
5314 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5315 sregs->idt.limit = dt.size;
5316 sregs->idt.base = dt.address;
b6c7a5dc 5317 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5318 sregs->gdt.limit = dt.size;
5319 sregs->gdt.base = dt.address;
b6c7a5dc 5320
4d4ec087 5321 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5322 sregs->cr2 = vcpu->arch.cr2;
5323 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5324 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5325 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5326 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5327 sregs->apic_base = kvm_get_apic_base(vcpu);
5328
923c61bb 5329 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5330
36752c9b 5331 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5332 set_bit(vcpu->arch.interrupt.nr,
5333 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5334
b6c7a5dc
HB		 5335 return 0;
5336}
5337
62d9f0db
MT		 5338int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5339 struct kvm_mp_state *mp_state)
5340{
62d9f0db 5341 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5342 return 0;
5343}
5344
5345int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5346 struct kvm_mp_state *mp_state)
5347{
62d9f0db 5348 vcpu->arch.mp_state = mp_state->mp_state;
62d9f0db
MT		 5349 return 0;
5350}
5351
e269fb21
JK		 5352int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5353 bool has_error_code, u32 error_code)
b6c7a5dc 5354{
4d2179e1 5355 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5356 int ret;
e01c2426 5357
8ec4722d 5358 init_emulate_ctxt(vcpu);
c697518a 5359
9aabc88f 5360 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5361 tss_selector, reason, has_error_code,
5362 error_code);
c697518a 5363
c697518a 5364 if (ret)
19d04437 5365 return EMULATE_FAIL;
37817f29 5366
4d2179e1 5367 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5368 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437
GN		 5369 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
5370 return EMULATE_DONE;
37817f29
IE		 5371}
5372EXPORT_SYMBOL_GPL(kvm_task_switch);
5373
b6c7a5dc
HB		 5374int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5375 struct kvm_sregs *sregs)
5376{
5377 int mmu_reset_needed = 0;
923c61bb 5378 int pending_vec, max_bits;
89a27f4d 5379 struct desc_ptr dt;
b6c7a5dc 5380
89a27f4d
GN		 5381 dt.size = sregs->idt.limit;
5382 dt.address = sregs->idt.base;
b6c7a5dc 5383 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5384 dt.size = sregs->gdt.limit;
5385 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5386 kvm_x86_ops->set_gdt(vcpu, &dt);
5387
ad312c7c
ZX		 5388 vcpu->arch.cr2 = sregs->cr2;
5389 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5390 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5391
2d3ad1f4 5392 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5393
f6801dff 5394 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5395 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5396 kvm_set_apic_base(vcpu, sregs->apic_base);
5397
4d4ec087 5398 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5399 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5400 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5401
fc78f519 5402 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5403 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5404 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5405 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5406 mmu_reset_needed = 1;
5407 }
b6c7a5dc
HB		 5408
5409 if (mmu_reset_needed)
5410 kvm_mmu_reset_context(vcpu);
5411
923c61bb
GN		 5412 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5413 pending_vec = find_first_bit(
5414 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5415 if (pending_vec < max_bits) {
66fd3f7f 5416 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5417 pr_debug("Set back pending irq %d\n", pending_vec);
5418 if (irqchip_in_kernel(vcpu->kvm))
5419 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5420 }
5421
3e6e0aab
GT		 5422 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5423 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5424 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5425 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5426 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5427 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5428
3e6e0aab
GT		 5429 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5430 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5431
5f0269f5
ME		 5432 update_cr8_intercept(vcpu);
5433
9c3e4aab 5434 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5435 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5436 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5437 !is_protmode(vcpu))
9c3e4aab
MT		 5438 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5439
b6c7a5dc
HB		 5440 return 0;
5441}
5442
d0bfb940
JK		 5443int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5444 struct kvm_guest_debug *dbg)
b6c7a5dc 5445{
355be0b9 5446 unsigned long rflags;
ae675ef0 5447 int i, r;
b6c7a5dc 5448
4f926bf2
JK		 5449 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5450 r = -EBUSY;
5451 if (vcpu->arch.exception.pending)
2122ff5e 5452 goto out;
4f926bf2
JK		 5453 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5454 kvm_queue_exception(vcpu, DB_VECTOR);
5455 else
5456 kvm_queue_exception(vcpu, BP_VECTOR);
5457 }
5458
91586a3b
JK		 5459 /*
5460 * Read rflags as long as potentially injected trace flags are still
5461 * filtered out.
5462 */
5463 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5464
5465 vcpu->guest_debug = dbg->control;
5466 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5467 vcpu->guest_debug = 0;
5468
5469 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5470 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5471 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5472 vcpu->arch.switch_db_regs =
5473 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5474 } else {
5475 for (i = 0; i < KVM_NR_DB_REGS; i++)
5476 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5477 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5478 }
5479
f92653ee
JK		 5480 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5481 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5482 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5483
91586a3b
JK		 5484 /*
5485 * Trigger an rflags update that will inject or remove the trace
5486 * flags.
5487 */
5488 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5489
355be0b9 5490 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5491
4f926bf2 5492 r = 0;
d0bfb940 5493
2122ff5e 5494out:
b6c7a5dc
HB		 5495
5496 return r;
5497}
5498
8b006791
ZX		 5499/*
5500 * Translate a guest virtual address to a guest physical address.
5501 */
5502int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5503 struct kvm_translation *tr)
5504{
5505 unsigned long vaddr = tr->linear_address;
5506 gpa_t gpa;
f656ce01 5507 int idx;
8b006791 5508
f656ce01 5509 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5510 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5511 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5512 tr->physical_address = gpa;
5513 tr->valid = gpa != UNMAPPED_GVA;
5514 tr->writeable = 1;
5515 tr->usermode = 0;
8b006791
ZX		 5516
5517 return 0;
5518}
5519
d0752060
HB		 5520int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5521{
98918833
SY		 5522 struct i387_fxsave_struct *fxsave =
5523 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5524
d0752060
HB		 5525 memcpy(fpu->fpr, fxsave->st_space, 128);
5526 fpu->fcw = fxsave->cwd;
5527 fpu->fsw = fxsave->swd;
5528 fpu->ftwx = fxsave->twd;
5529 fpu->last_opcode = fxsave->fop;
5530 fpu->last_ip = fxsave->rip;
5531 fpu->last_dp = fxsave->rdp;
5532 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5533
d0752060
HB		 5534 return 0;
5535}
5536
5537int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5538{
98918833
SY		 5539 struct i387_fxsave_struct *fxsave =
5540 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5541
d0752060
HB		 5542 memcpy(fxsave->st_space, fpu->fpr, 128);
5543 fxsave->cwd = fpu->fcw;
5544 fxsave->swd = fpu->fsw;
5545 fxsave->twd = fpu->ftwx;
5546 fxsave->fop = fpu->last_opcode;
5547 fxsave->rip = fpu->last_ip;
5548 fxsave->rdp = fpu->last_dp;
5549 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5550
d0752060
HB		 5551 return 0;
5552}
5553
10ab25cd 5554int fx_init(struct kvm_vcpu *vcpu)
d0752060 5555{
10ab25cd
JK		 5556 int err;
5557
5558 err = fpu_alloc(&vcpu->arch.guest_fpu);
5559 if (err)
5560 return err;
5561
98918833 5562 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5563
2acf923e
DC		 5564 /*
5565 * Ensure guest xcr0 is valid for loading
5566 */
5567 vcpu->arch.xcr0 = XSTATE_FP;
5568
ad312c7c 5569 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5570
5571 return 0;
d0752060
HB		 5572}
5573EXPORT_SYMBOL_GPL(fx_init);
5574
98918833
SY		 5575static void fx_free(struct kvm_vcpu *vcpu)
5576{
5577 fpu_free(&vcpu->arch.guest_fpu);
5578}
5579
d0752060
HB		 5580void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5581{
2608d7a1 5582 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5583 return;
5584
2acf923e
DC		 5585 /*
5586 * Restore all possible states in the guest,
5587 * and assume host would use all available bits.
5588 * Guest xcr0 would be loaded later.
5589 */
5590 kvm_put_guest_xcr0(vcpu);
d0752060 5591 vcpu->guest_fpu_loaded = 1;
7cf30855 5592 unlazy_fpu(current);
98918833 5593 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5594 trace_kvm_fpu(1);
d0752060 5595}
d0752060
HB		 5596
5597void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5598{
2acf923e
DC		 5599 kvm_put_guest_xcr0(vcpu);
5600
d0752060
HB		 5601 if (!vcpu->guest_fpu_loaded)
5602 return;
5603
5604 vcpu->guest_fpu_loaded = 0;
98918833 5605 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5606 ++vcpu->stat.fpu_reload;
a8eeb04a 5607 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5608 trace_kvm_fpu(0);
d0752060 5609}
e9b11c17
ZX		 5610
5611void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5612{
7f1ea208
JR		 5613 if (vcpu->arch.time_page) {
5614 kvm_release_page_dirty(vcpu->arch.time_page);
5615 vcpu->arch.time_page = NULL;
5616 }
5617
f5f48ee1 5618 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5619 fx_free(vcpu);
e9b11c17
ZX		 5620 kvm_x86_ops->vcpu_free(vcpu);
5621}
5622
5623struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5624 unsigned int id)
5625{
6755bae8
ZA		 5626 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5627 printk_once(KERN_WARNING
5628 "kvm: SMP vm created on host with unstable TSC; "
5629 "guest TSC will not be reliable\n");
26e5215f
AK		 5630 return kvm_x86_ops->vcpu_create(kvm, id);
5631}
e9b11c17 5632
26e5215f
AK		 5633int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5634{
5635 int r;
e9b11c17 5636
0bed3b56 5637 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5638 vcpu_load(vcpu);
5639 r = kvm_arch_vcpu_reset(vcpu);
5640 if (r == 0)
5641 r = kvm_mmu_setup(vcpu);
5642 vcpu_put(vcpu);
5643 if (r < 0)
5644 goto free_vcpu;
5645
26e5215f 5646 return 0;
e9b11c17
ZX		 5647free_vcpu:
5648 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5649 return r;
e9b11c17
ZX		 5650}
5651
d40ccc62 5652void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5653{
5654 vcpu_load(vcpu);
5655 kvm_mmu_unload(vcpu);
5656 vcpu_put(vcpu);
5657
98918833 5658 fx_free(vcpu);
e9b11c17
ZX		 5659 kvm_x86_ops->vcpu_free(vcpu);
5660}
5661
5662int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5663{
448fa4a9
JK		 5664 vcpu->arch.nmi_pending = false;
5665 vcpu->arch.nmi_injected = false;
5666
42dbaa5a
JK		 5667 vcpu->arch.switch_db_regs = 0;
5668 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5669 vcpu->arch.dr6 = DR6_FIXED_1;
5670 vcpu->arch.dr7 = DR7_FIXED_1;
5671
e9b11c17
ZX		 5672 return kvm_x86_ops->vcpu_reset(vcpu);
5673}
5674
10474ae8 5675int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5676{
ca84d1a2
ZA		 5677 struct kvm *kvm;
5678 struct kvm_vcpu *vcpu;
5679 int i;
5680
18863bdd 5681 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5682 list_for_each_entry(kvm, &vm_list, vm_list)
5683 kvm_for_each_vcpu(i, vcpu, kvm)
5684 if (vcpu->cpu == smp_processor_id())
5685 kvm_request_guest_time_update(vcpu);
10474ae8 5686 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5687}
5688
5689void kvm_arch_hardware_disable(void *garbage)
5690{
5691 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5692 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5693}
5694
5695int kvm_arch_hardware_setup(void)
5696{
5697 return kvm_x86_ops->hardware_setup();
5698}
5699
5700void kvm_arch_hardware_unsetup(void)
5701{
5702 kvm_x86_ops->hardware_unsetup();
5703}
5704
5705void kvm_arch_check_processor_compat(void *rtn)
5706{
5707 kvm_x86_ops->check_processor_compatibility(rtn);
5708}
5709
5710int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5711{
5712 struct page *page;
5713 struct kvm *kvm;
5714 int r;
5715
5716 BUG_ON(vcpu->kvm == NULL);
5717 kvm = vcpu->kvm;
5718
9aabc88f 5719 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5720 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5721 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5722 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5723 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5724 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5725 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5726 else
a4535290 5727 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5728
5729 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5730 if (!page) {
5731 r = -ENOMEM;
5732 goto fail;
5733 }
ad312c7c 5734 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5735
5736 r = kvm_mmu_create(vcpu);
5737 if (r < 0)
5738 goto fail_free_pio_data;
5739
5740 if (irqchip_in_kernel(kvm)) {
5741 r = kvm_create_lapic(vcpu);
5742 if (r < 0)
5743 goto fail_mmu_destroy;
5744 }
5745
890ca9ae
HY		 5746 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5747 GFP_KERNEL);
5748 if (!vcpu->arch.mce_banks) {
5749 r = -ENOMEM;
443c39bc 5750 goto fail_free_lapic;
890ca9ae
HY		 5751 }
5752 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5753
f5f48ee1
SY		 5754 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5755 goto fail_free_mce_banks;
5756
e9b11c17 5757 return 0;
f5f48ee1
SY		 5758fail_free_mce_banks:
5759 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5760fail_free_lapic:
5761 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5762fail_mmu_destroy:
5763 kvm_mmu_destroy(vcpu);
5764fail_free_pio_data:
ad312c7c 5765 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5766fail:
5767 return r;
5768}
5769
5770void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5771{
f656ce01
MT		 5772 int idx;
5773
36cb93fd 5774 kfree(vcpu->arch.mce_banks);
e9b11c17 5775 kvm_free_lapic(vcpu);
f656ce01 5776 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5777 kvm_mmu_destroy(vcpu);
f656ce01 5778 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5779 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5780}
d19a9cd2
ZX		 5781
5782struct kvm *kvm_arch_create_vm(void)
5783{
5784 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5785
5786 if (!kvm)
5787 return ERR_PTR(-ENOMEM);
5788
f05e70ac 5789 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5790 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5791
5550af4d
SY		 5792 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5793 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5794
99e3e30a
ZA		 5795 spin_lock_init(&kvm->arch.tsc_write_lock);
5796
d19a9cd2
ZX		 5797 return kvm;
5798}
5799
5800static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5801{
5802 vcpu_load(vcpu);
5803 kvm_mmu_unload(vcpu);
5804 vcpu_put(vcpu);
5805}
5806
5807static void kvm_free_vcpus(struct kvm *kvm)
5808{
5809 unsigned int i;
988a2cae 5810 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5811
5812 /*
5813 * Unpin any mmu pages first.
5814 */
988a2cae
GN		 5815 kvm_for_each_vcpu(i, vcpu, kvm)
5816 kvm_unload_vcpu_mmu(vcpu);
5817 kvm_for_each_vcpu(i, vcpu, kvm)
5818 kvm_arch_vcpu_free(vcpu);
5819
5820 mutex_lock(&kvm->lock);
5821 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5822 kvm->vcpus[i] = NULL;
d19a9cd2 5823
988a2cae
GN		 5824 atomic_set(&kvm->online_vcpus, 0);
5825 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5826}
5827
ad8ba2cd
SY		 5828void kvm_arch_sync_events(struct kvm *kvm)
5829{
ba4cef31 5830 kvm_free_all_assigned_devices(kvm);
aea924f6 5831 kvm_free_pit(kvm);
ad8ba2cd
SY		 5832}
5833
d19a9cd2
ZX		 5834void kvm_arch_destroy_vm(struct kvm *kvm)
5835{
6eb55818 5836 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5837 kfree(kvm->arch.vpic);
5838 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5839 kvm_free_vcpus(kvm);
5840 kvm_free_physmem(kvm);
3d45830c
AK		 5841 if (kvm->arch.apic_access_page)
5842 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5843 if (kvm->arch.ept_identity_pagetable)
5844 put_page(kvm->arch.ept_identity_pagetable);
64749204 5845 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5846 kfree(kvm);
5847}
0de10343 5848
f7784b8e
MT		 5849int kvm_arch_prepare_memory_region(struct kvm *kvm,
5850 struct kvm_memory_slot *memslot,
0de10343 5851 struct kvm_memory_slot old,
f7784b8e 5852 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5853 int user_alloc)
5854{
f7784b8e 5855 int npages = memslot->npages;
7ac77099
AK		 5856 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5857
5858 /* Prevent internal slot pages from being moved by fork()/COW. */
5859 if (memslot->id >= KVM_MEMORY_SLOTS)
5860 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5861
5862 /*To keep backward compatibility with older userspace,
5863 *x86 needs to hanlde !user_alloc case.
5864 */
5865 if (!user_alloc) {
5866 if (npages && !old.rmap) {
604b38ac
AA		 5867 unsigned long userspace_addr;
5868
72dc67a6 5869 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5870 userspace_addr = do_mmap(NULL, 0,
5871 npages * PAGE_SIZE,
5872 PROT_READ | PROT_WRITE,
7ac77099 5873 map_flags,
604b38ac 5874 0);
72dc67a6 5875 up_write(&current->mm->mmap_sem);
0de10343 5876
604b38ac
AA		 5877 if (IS_ERR((void *)userspace_addr))
5878 return PTR_ERR((void *)userspace_addr);
5879
604b38ac 5880 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5881 }
5882 }
5883
f7784b8e
MT		 5884
5885 return 0;
5886}
5887
5888void kvm_arch_commit_memory_region(struct kvm *kvm,
5889 struct kvm_userspace_memory_region *mem,
5890 struct kvm_memory_slot old,
5891 int user_alloc)
5892{
5893
5894 int npages = mem->memory_size >> PAGE_SHIFT;
5895
5896 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5897 int ret;
5898
5899 down_write(&current->mm->mmap_sem);
5900 ret = do_munmap(current->mm, old.userspace_addr,
5901 old.npages * PAGE_SIZE);
5902 up_write(&current->mm->mmap_sem);
5903 if (ret < 0)
5904 printk(KERN_WARNING
5905 "kvm_vm_ioctl_set_memory_region: "
5906 "failed to munmap memory\n");
5907 }
5908
7c8a83b7 5909 spin_lock(&kvm->mmu_lock);
f05e70ac 5910 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5911 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5912 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5913 }
5914
5915 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5916 spin_unlock(&kvm->mmu_lock);
0de10343 5917}
1d737c8a 5918
34d4cb8f
MT		 5919void kvm_arch_flush_shadow(struct kvm *kvm)
5920{
5921 kvm_mmu_zap_all(kvm);
8986ecc0 5922 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5923}
5924
1d737c8a
ZX		 5925int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5926{
a4535290 5927 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5928 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5929 || vcpu->arch.nmi_pending ||
5930 (kvm_arch_interrupt_allowed(vcpu) &&
5931 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5932}
5736199a 5933
5736199a
ZX		 5934void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5935{
32f88400
MT		 5936 int me;
5937 int cpu = vcpu->cpu;
5736199a
ZX		 5938
5939 if (waitqueue_active(&vcpu->wq)) {
5940 wake_up_interruptible(&vcpu->wq);
5941 ++vcpu->stat.halt_wakeup;
5942 }
32f88400
MT		 5943
5944 me = get_cpu();
5945 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5946 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5947 smp_send_reschedule(cpu);
e9571ed5 5948 put_cpu();
5736199a 5949}
78646121
GN		 5950
5951int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5952{
5953 return kvm_x86_ops->interrupt_allowed(vcpu);
5954}
229456fc 5955
f92653ee
JK		 5956bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5957{
5958 unsigned long current_rip = kvm_rip_read(vcpu) +
5959 get_segment_base(vcpu, VCPU_SREG_CS);
5960
5961 return current_rip == linear_rip;
5962}
5963EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5964
94fe45da
JK		 5965unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5966{
5967 unsigned long rflags;
5968
5969 rflags = kvm_x86_ops->get_rflags(vcpu);
5970 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5971 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5972 return rflags;
5973}
5974EXPORT_SYMBOL_GPL(kvm_get_rflags);
5975
5976void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5977{
5978 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5979 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5980 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5981 kvm_x86_ops->set_rflags(vcpu, rflags);
5982}
5983EXPORT_SYMBOL_GPL(kvm_set_rflags);
5984
229456fc
MT		 5985EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5986EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5987EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5988EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5989EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5990EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5991EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5992EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5993EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5994EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5995EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5996EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)