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KVM: VMX: Prepare an identity page table for EPT in real mode
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
6aa8b732 19#include "vmx.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
e495606d 29
6aa8b732 30#include <asm/io.h>
3b3be0d1 31#include <asm/desc.h>
6aa8b732 32
6aa8b732
AK		 33MODULE_AUTHOR("Qumranet");
34MODULE_LICENSE("GPL");
35
c7addb90
AK		 36static int bypass_guest_pf = 1;
37module_param(bypass_guest_pf, bool, 0);
38
2384d2b3
SY		 39static int enable_vpid = 1;
40module_param(enable_vpid, bool, 0);
41
4c9fc8ef
AK		 42static int flexpriority_enabled = 1;
43module_param(flexpriority_enabled, bool, 0);
44
d56f546d
SY		 45static int enable_ept;
46module_param(enable_ept, bool, 0);
47
a2fa3e9f
GH		 48struct vmcs {
49 u32 revision_id;
50 u32 abort;
51 char data[0];
52};
53
54struct vcpu_vmx {
fb3f0f51 55 struct kvm_vcpu vcpu;
a2fa3e9f 56 int launched;
29bd8a78 57 u8 fail;
1155f76a 58 u32 idt_vectoring_info;
a2fa3e9f
GH		 59 struct kvm_msr_entry *guest_msrs;
60 struct kvm_msr_entry *host_msrs;
61 int nmsrs;
62 int save_nmsrs;
63 int msr_offset_efer;
64#ifdef CONFIG_X86_64
65 int msr_offset_kernel_gs_base;
66#endif
67 struct vmcs *vmcs;
68 struct {
69 int loaded;
70 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 71 int gs_ldt_reload_needed;
72 int fs_reload_needed;
51c6cf66 73 int guest_efer_loaded;
d77c26fc 74 } host_state;
9c8cba37
AK		 75 struct {
76 struct {
77 bool pending;
78 u8 vector;
79 unsigned rip;
80 } irq;
81 } rmode;
2384d2b3 82 int vpid;
a2fa3e9f
GH		 83};
84
85static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
86{
fb3f0f51 87 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 88}
89
b7ebfb05 90static int init_rmode(struct kvm *kvm);
75880a01 91
6aa8b732
AK		 92static DEFINE_PER_CPU(struct vmcs *, vmxarea);
93static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
94
fdef3ad1
HQ		 95static struct page *vmx_io_bitmap_a;
96static struct page *vmx_io_bitmap_b;
25c5f225 97static struct page *vmx_msr_bitmap;
fdef3ad1 98
2384d2b3
SY		 99static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
100static DEFINE_SPINLOCK(vmx_vpid_lock);
101
1c3d14fe 102static struct vmcs_config {
6aa8b732
AK		 103 int size;
104 int order;
105 u32 revision_id;
1c3d14fe
YS		 106 u32 pin_based_exec_ctrl;
107 u32 cpu_based_exec_ctrl;
f78e0e2e 108 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 109 u32 vmexit_ctrl;
110 u32 vmentry_ctrl;
111} vmcs_config;
6aa8b732 112
d56f546d
SY		 113struct vmx_capability {
114 u32 ept;
115 u32 vpid;
116} vmx_capability;
117
6aa8b732
AK		 118#define VMX_SEGMENT_FIELD(seg) \
119 [VCPU_SREG_##seg] = { \
120 .selector = GUEST_##seg##_SELECTOR, \
121 .base = GUEST_##seg##_BASE, \
122 .limit = GUEST_##seg##_LIMIT, \
123 .ar_bytes = GUEST_##seg##_AR_BYTES, \
124 }
125
126static struct kvm_vmx_segment_field {
127 unsigned selector;
128 unsigned base;
129 unsigned limit;
130 unsigned ar_bytes;
131} kvm_vmx_segment_fields[] = {
132 VMX_SEGMENT_FIELD(CS),
133 VMX_SEGMENT_FIELD(DS),
134 VMX_SEGMENT_FIELD(ES),
135 VMX_SEGMENT_FIELD(FS),
136 VMX_SEGMENT_FIELD(GS),
137 VMX_SEGMENT_FIELD(SS),
138 VMX_SEGMENT_FIELD(TR),
139 VMX_SEGMENT_FIELD(LDTR),
140};
141
4d56c8a7
AK		 142/*
143 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
144 * away by decrementing the array size.
145 */
6aa8b732 146static const u32 vmx_msr_index[] = {
05b3e0c2 147#ifdef CONFIG_X86_64
6aa8b732
AK		 148 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
149#endif
150 MSR_EFER, MSR_K6_STAR,
151};
9d8f549d 152#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 153
a2fa3e9f
GH		 154static void load_msrs(struct kvm_msr_entry *e, int n)
155{
156 int i;
157
158 for (i = 0; i < n; ++i)
159 wrmsrl(e[i].index, e[i].data);
160}
161
162static void save_msrs(struct kvm_msr_entry *e, int n)
163{
164 int i;
165
166 for (i = 0; i < n; ++i)
167 rdmsrl(e[i].index, e[i].data);
168}
169
6aa8b732
AK		 170static inline int is_page_fault(u32 intr_info)
171{
172 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
173 INTR_INFO_VALID_MASK)) ==
174 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
175}
176
2ab455cc
AL		 177static inline int is_no_device(u32 intr_info)
178{
179 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
180 INTR_INFO_VALID_MASK)) ==
181 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
182}
183
7aa81cc0
AL		 184static inline int is_invalid_opcode(u32 intr_info)
185{
186 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
187 INTR_INFO_VALID_MASK)) ==
188 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
189}
190
6aa8b732
AK		 191static inline int is_external_interrupt(u32 intr_info)
192{
193 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
194 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
195}
196
25c5f225
SY		 197static inline int cpu_has_vmx_msr_bitmap(void)
198{
199 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
200}
201
6e5d865c
YS		 202static inline int cpu_has_vmx_tpr_shadow(void)
203{
204 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
205}
206
207static inline int vm_need_tpr_shadow(struct kvm *kvm)
208{
209 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
210}
211
f78e0e2e
SY		 212static inline int cpu_has_secondary_exec_ctrls(void)
213{
214 return (vmcs_config.cpu_based_exec_ctrl &
215 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
216}
217
774ead3a 218static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 219{
4c9fc8ef
AK		 220 return flexpriority_enabled
221 && (vmcs_config.cpu_based_2nd_exec_ctrl &
222 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
f78e0e2e
SY		 223}
224
d56f546d
SY		 225static inline int cpu_has_vmx_invept_individual_addr(void)
226{
227 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
228}
229
230static inline int cpu_has_vmx_invept_context(void)
231{
232 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
233}
234
235static inline int cpu_has_vmx_invept_global(void)
236{
237 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
238}
239
240static inline int cpu_has_vmx_ept(void)
241{
242 return (vmcs_config.cpu_based_2nd_exec_ctrl &
243 SECONDARY_EXEC_ENABLE_EPT);
244}
245
246static inline int vm_need_ept(void)
247{
248 return (cpu_has_vmx_ept() && enable_ept);
249}
250
f78e0e2e
SY		 251static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
252{
253 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
254 (irqchip_in_kernel(kvm)));
255}
256
2384d2b3
SY		 257static inline int cpu_has_vmx_vpid(void)
258{
259 return (vmcs_config.cpu_based_2nd_exec_ctrl &
260 SECONDARY_EXEC_ENABLE_VPID);
261}
262
8b9cf98c 263static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 264{
265 int i;
266
a2fa3e9f
GH		 267 for (i = 0; i < vmx->nmsrs; ++i)
268 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 269 return i;
270 return -1;
271}
272
2384d2b3
SY		 273static inline void __invvpid(int ext, u16 vpid, gva_t gva)
274{
275 struct {
276 u64 vpid : 16;
277 u64 rsvd : 48;
278 u64 gva;
279 } operand = { vpid, 0, gva };
280
281 asm volatile (ASM_VMX_INVVPID
282 /* CF==1 or ZF==1 --> rc = -1 */
283 "; ja 1f ; ud2 ; 1:"
284 : : "a"(&operand), "c"(ext) : "cc", "memory");
285}
286
8b9cf98c 287static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 288{
289 int i;
290
8b9cf98c 291 i = __find_msr_index(vmx, msr);
a75beee6 292 if (i >= 0)
a2fa3e9f 293 return &vmx->guest_msrs[i];
8b6d44c7 294 return NULL;
7725f0ba
AK		 295}
296
6aa8b732
AK		 297static void vmcs_clear(struct vmcs *vmcs)
298{
299 u64 phys_addr = __pa(vmcs);
300 u8 error;
301
302 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
303 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
304 : "cc", "memory");
305 if (error)
306 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
307 vmcs, phys_addr);
308}
309
310static void __vcpu_clear(void *arg)
311{
8b9cf98c 312 struct vcpu_vmx *vmx = arg;
d3b2c338 313 int cpu = raw_smp_processor_id();
6aa8b732 314
8b9cf98c 315 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 316 vmcs_clear(vmx->vmcs);
317 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 318 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 319 rdtscll(vmx->vcpu.arch.host_tsc);
6aa8b732
AK		 320}
321
8b9cf98c 322static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 323{
eae5ecb5
AK		 324 if (vmx->vcpu.cpu == -1)
325 return;
f566e09f 326 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
8b9cf98c 327 vmx->launched = 0;
8d0be2b3
AK		 328}
329
2384d2b3
SY		 330static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
331{
332 if (vmx->vpid == 0)
333 return;
334
335 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
336}
337
6aa8b732
AK		 338static unsigned long vmcs_readl(unsigned long field)
339{
340 unsigned long value;
341
342 asm volatile (ASM_VMX_VMREAD_RDX_RAX
343 : "=a"(value) : "d"(field) : "cc");
344 return value;
345}
346
347static u16 vmcs_read16(unsigned long field)
348{
349 return vmcs_readl(field);
350}
351
352static u32 vmcs_read32(unsigned long field)
353{
354 return vmcs_readl(field);
355}
356
357static u64 vmcs_read64(unsigned long field)
358{
05b3e0c2 359#ifdef CONFIG_X86_64
6aa8b732
AK		 360 return vmcs_readl(field);
361#else
362 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
363#endif
364}
365
e52de1b8
AK		 366static noinline void vmwrite_error(unsigned long field, unsigned long value)
367{
368 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
369 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
370 dump_stack();
371}
372
6aa8b732
AK		 373static void vmcs_writel(unsigned long field, unsigned long value)
374{
375 u8 error;
376
377 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
d77c26fc 378 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 379 if (unlikely(error))
380 vmwrite_error(field, value);
6aa8b732
AK		 381}
382
383static void vmcs_write16(unsigned long field, u16 value)
384{
385 vmcs_writel(field, value);
386}
387
388static void vmcs_write32(unsigned long field, u32 value)
389{
390 vmcs_writel(field, value);
391}
392
393static void vmcs_write64(unsigned long field, u64 value)
394{
05b3e0c2 395#ifdef CONFIG_X86_64
6aa8b732
AK		 396 vmcs_writel(field, value);
397#else
398 vmcs_writel(field, value);
399 asm volatile ("");
400 vmcs_writel(field+1, value >> 32);
401#endif
402}
403
2ab455cc
AL		 404static void vmcs_clear_bits(unsigned long field, u32 mask)
405{
406 vmcs_writel(field, vmcs_readl(field) & ~mask);
407}
408
409static void vmcs_set_bits(unsigned long field, u32 mask)
410{
411 vmcs_writel(field, vmcs_readl(field) | mask);
412}
413
abd3f2d6
AK		 414static void update_exception_bitmap(struct kvm_vcpu *vcpu)
415{
416 u32 eb;
417
7aa81cc0 418 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 419 if (!vcpu->fpu_active)
420 eb |= 1u << NM_VECTOR;
421 if (vcpu->guest_debug.enabled)
422 eb |= 1u << 1;
ad312c7c 423 if (vcpu->arch.rmode.active)
abd3f2d6
AK		 424 eb = ~0;
425 vmcs_write32(EXCEPTION_BITMAP, eb);
426}
427
33ed6329
AK		 428static void reload_tss(void)
429{
33ed6329
AK		 430 /*
431 * VT restores TR but not its size. Useless.
432 */
433 struct descriptor_table gdt;
a5f61300 434 struct desc_struct *descs;
33ed6329
AK		 435
436 get_gdt(&gdt);
437 descs = (void *)gdt.base;
438 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
439 load_TR_desc();
33ed6329
AK		 440}
441
8b9cf98c 442static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 443{
a2fa3e9f 444 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 445 u64 host_efer = vmx->host_msrs[efer_offset].data;
446 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
447 u64 ignore_bits;
448
449 if (efer_offset < 0)
450 return;
451 /*
452 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
453 * outside long mode
454 */
455 ignore_bits = EFER_NX | EFER_SCE;
456#ifdef CONFIG_X86_64
457 ignore_bits |= EFER_LMA | EFER_LME;
458 /* SCE is meaningful only in long mode on Intel */
459 if (guest_efer & EFER_LMA)
460 ignore_bits &= ~(u64)EFER_SCE;
461#endif
462 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
463 return;
2cc51560 464
51c6cf66
AK		 465 vmx->host_state.guest_efer_loaded = 1;
466 guest_efer &= ~ignore_bits;
467 guest_efer |= host_efer & ignore_bits;
468 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 469 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 470}
471
51c6cf66
AK		 472static void reload_host_efer(struct vcpu_vmx *vmx)
473{
474 if (vmx->host_state.guest_efer_loaded) {
475 vmx->host_state.guest_efer_loaded = 0;
476 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
477 }
478}
479
04d2cc77 480static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 481{
04d2cc77
AK		 482 struct vcpu_vmx *vmx = to_vmx(vcpu);
483
a2fa3e9f 484 if (vmx->host_state.loaded)
33ed6329
AK		 485 return;
486
a2fa3e9f 487 vmx->host_state.loaded = 1;
33ed6329
AK		 488 /*
489 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
490 * allow segment selectors with cpl > 0 or ti == 1.
491 */
a2fa3e9f 492 vmx->host_state.ldt_sel = read_ldt();
152d3f2f 493 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
a2fa3e9f 494 vmx->host_state.fs_sel = read_fs();
152d3f2f 495 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 496 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 497 vmx->host_state.fs_reload_needed = 0;
498 } else {
33ed6329 499 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 500 vmx->host_state.fs_reload_needed = 1;
33ed6329 501 }
a2fa3e9f
GH		 502 vmx->host_state.gs_sel = read_gs();
503 if (!(vmx->host_state.gs_sel & 7))
504 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 505 else {
506 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 507 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 508 }
509
510#ifdef CONFIG_X86_64
511 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
512 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
513#else
a2fa3e9f
GH		 514 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
515 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 516#endif
707c0874
AK		 517
518#ifdef CONFIG_X86_64
d77c26fc 519 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 520 save_msrs(vmx->host_msrs +
521 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 522
707c0874 523#endif
a2fa3e9f 524 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 525 load_transition_efer(vmx);
33ed6329
AK		 526}
527
8b9cf98c 528static void vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 529{
15ad7146 530 unsigned long flags;
33ed6329 531
a2fa3e9f 532 if (!vmx->host_state.loaded)
33ed6329
AK		 533 return;
534
e1beb1d3 535 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 536 vmx->host_state.loaded = 0;
152d3f2f 537 if (vmx->host_state.fs_reload_needed)
a2fa3e9f 538 load_fs(vmx->host_state.fs_sel);
152d3f2f
LV		 539 if (vmx->host_state.gs_ldt_reload_needed) {
540 load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 541 /*
542 * If we have to reload gs, we must take care to
543 * preserve our gs base.
544 */
15ad7146 545 local_irq_save(flags);
a2fa3e9f 546 load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 547#ifdef CONFIG_X86_64
548 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
549#endif
15ad7146 550 local_irq_restore(flags);
33ed6329 551 }
152d3f2f 552 reload_tss();
a2fa3e9f
GH		 553 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
554 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 555 reload_host_efer(vmx);
33ed6329
AK		 556}
557
6aa8b732
AK		 558/*
559 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
560 * vcpu mutex is already taken.
561 */
15ad7146 562static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 563{
a2fa3e9f
GH		 564 struct vcpu_vmx *vmx = to_vmx(vcpu);
565 u64 phys_addr = __pa(vmx->vmcs);
019960ae 566 u64 tsc_this, delta, new_offset;
6aa8b732 567
a3d7f85f 568 if (vcpu->cpu != cpu) {
8b9cf98c 569 vcpu_clear(vmx);
a3d7f85f 570 kvm_migrate_apic_timer(vcpu);
2384d2b3 571 vpid_sync_vcpu_all(vmx);
a3d7f85f 572 }
6aa8b732 573
a2fa3e9f 574 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 575 u8 error;
576
a2fa3e9f 577 per_cpu(current_vmcs, cpu) = vmx->vmcs;
6aa8b732
AK		 578 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
579 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
580 : "cc");
581 if (error)
582 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 583 vmx->vmcs, phys_addr);
6aa8b732
AK		 584 }
585
586 if (vcpu->cpu != cpu) {
587 struct descriptor_table dt;
588 unsigned long sysenter_esp;
589
590 vcpu->cpu = cpu;
591 /*
592 * Linux uses per-cpu TSS and GDT, so set these when switching
593 * processors.
594 */
595 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
596 get_gdt(&dt);
597 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
598
599 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
600 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 601
602 /*
603 * Make sure the time stamp counter is monotonous.
604 */
605 rdtscll(tsc_this);
019960ae
AK		 606 if (tsc_this < vcpu->arch.host_tsc) {
607 delta = vcpu->arch.host_tsc - tsc_this;
608 new_offset = vmcs_read64(TSC_OFFSET) + delta;
609 vmcs_write64(TSC_OFFSET, new_offset);
610 }
6aa8b732 611 }
6aa8b732
AK		 612}
613
614static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
615{
8b9cf98c 616 vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 617}
618
5fd86fcf
AK		 619static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
620{
621 if (vcpu->fpu_active)
622 return;
623 vcpu->fpu_active = 1;
707d92fa 624 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 625 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 626 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 627 update_exception_bitmap(vcpu);
628}
629
630static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
631{
632 if (!vcpu->fpu_active)
633 return;
634 vcpu->fpu_active = 0;
707d92fa 635 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 636 update_exception_bitmap(vcpu);
637}
638
774c47f1
AK		 639static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
640{
8b9cf98c 641 vcpu_clear(to_vmx(vcpu));
774c47f1
AK		 642}
643
6aa8b732
AK		 644static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
645{
646 return vmcs_readl(GUEST_RFLAGS);
647}
648
649static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
650{
ad312c7c 651 if (vcpu->arch.rmode.active)
053de044 652 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 653 vmcs_writel(GUEST_RFLAGS, rflags);
654}
655
656static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
657{
658 unsigned long rip;
659 u32 interruptibility;
660
661 rip = vmcs_readl(GUEST_RIP);
662 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
663 vmcs_writel(GUEST_RIP, rip);
664
665 /*
666 * We emulated an instruction, so temporary interrupt blocking
667 * should be removed, if set.
668 */
669 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
670 if (interruptibility & 3)
671 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
672 interruptibility & ~3);
ad312c7c 673 vcpu->arch.interrupt_window_open = 1;
6aa8b732
AK		 674}
675
298101da
AK		 676static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
677 bool has_error_code, u32 error_code)
678{
679 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
680 nr | INTR_TYPE_EXCEPTION
2e11384c 681 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
298101da
AK		 682 | INTR_INFO_VALID_MASK);
683 if (has_error_code)
684 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
685}
686
687static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
688{
689 struct vcpu_vmx *vmx = to_vmx(vcpu);
690
691 return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
692}
693
a75beee6
ED		 694/*
695 * Swap MSR entry in host/guest MSR entry array.
696 */
54e11fa1 697#ifdef CONFIG_X86_64
8b9cf98c 698static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 699{
a2fa3e9f
GH		 700 struct kvm_msr_entry tmp;
701
702 tmp = vmx->guest_msrs[to];
703 vmx->guest_msrs[to] = vmx->guest_msrs[from];
704 vmx->guest_msrs[from] = tmp;
705 tmp = vmx->host_msrs[to];
706 vmx->host_msrs[to] = vmx->host_msrs[from];
707 vmx->host_msrs[from] = tmp;
a75beee6 708}
54e11fa1 709#endif
a75beee6 710
e38aea3e
AK		 711/*
712 * Set up the vmcs to automatically save and restore system
713 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
714 * mode, as fiddling with msrs is very expensive.
715 */
8b9cf98c 716static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 717{
2cc51560 718 int save_nmsrs;
e38aea3e 719
33f9c505 720 vmx_load_host_state(vmx);
a75beee6
ED		 721 save_nmsrs = 0;
722#ifdef CONFIG_X86_64
8b9cf98c 723 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 724 int index;
725
8b9cf98c 726 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 727 if (index >= 0)
8b9cf98c
RR		 728 move_msr_up(vmx, index, save_nmsrs++);
729 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 730 if (index >= 0)
8b9cf98c
RR		 731 move_msr_up(vmx, index, save_nmsrs++);
732 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 733 if (index >= 0)
8b9cf98c
RR		 734 move_msr_up(vmx, index, save_nmsrs++);
735 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 736 if (index >= 0)
8b9cf98c 737 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 738 /*
739 * MSR_K6_STAR is only needed on long mode guests, and only
740 * if efer.sce is enabled.
741 */
8b9cf98c 742 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 743 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 744 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 745 }
746#endif
a2fa3e9f 747 vmx->save_nmsrs = save_nmsrs;
e38aea3e 748
4d56c8a7 749#ifdef CONFIG_X86_64
a2fa3e9f 750 vmx->msr_offset_kernel_gs_base =
8b9cf98c 751 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 752#endif
8b9cf98c 753 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 754}
755
6aa8b732
AK		 756/*
757 * reads and returns guest's timestamp counter "register"
758 * guest_tsc = host_tsc + tsc_offset -- 21.3
759 */
760static u64 guest_read_tsc(void)
761{
762 u64 host_tsc, tsc_offset;
763
764 rdtscll(host_tsc);
765 tsc_offset = vmcs_read64(TSC_OFFSET);
766 return host_tsc + tsc_offset;
767}
768
769/*
770 * writes 'guest_tsc' into guest's timestamp counter "register"
771 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
772 */
773static void guest_write_tsc(u64 guest_tsc)
774{
775 u64 host_tsc;
776
777 rdtscll(host_tsc);
778 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
779}
780
6aa8b732
AK		 781/*
782 * Reads an msr value (of 'msr_index') into 'pdata'.
783 * Returns 0 on success, non-0 otherwise.
784 * Assumes vcpu_load() was already called.
785 */
786static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
787{
788 u64 data;
a2fa3e9f 789 struct kvm_msr_entry *msr;
6aa8b732
AK		 790
791 if (!pdata) {
792 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
793 return -EINVAL;
794 }
795
796 switch (msr_index) {
05b3e0c2 797#ifdef CONFIG_X86_64
6aa8b732
AK		 798 case MSR_FS_BASE:
799 data = vmcs_readl(GUEST_FS_BASE);
800 break;
801 case MSR_GS_BASE:
802 data = vmcs_readl(GUEST_GS_BASE);
803 break;
804 case MSR_EFER:
3bab1f5d 805 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 806#endif
807 case MSR_IA32_TIME_STAMP_COUNTER:
808 data = guest_read_tsc();
809 break;
810 case MSR_IA32_SYSENTER_CS:
811 data = vmcs_read32(GUEST_SYSENTER_CS);
812 break;
813 case MSR_IA32_SYSENTER_EIP:
f5b42c33 814 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 815 break;
816 case MSR_IA32_SYSENTER_ESP:
f5b42c33 817 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 818 break;
6aa8b732 819 default:
8b9cf98c 820 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 821 if (msr) {
822 data = msr->data;
823 break;
6aa8b732 824 }
3bab1f5d 825 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 826 }
827
828 *pdata = data;
829 return 0;
830}
831
832/*
833 * Writes msr value into into the appropriate "register".
834 * Returns 0 on success, non-0 otherwise.
835 * Assumes vcpu_load() was already called.
836 */
837static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
838{
a2fa3e9f
GH		 839 struct vcpu_vmx *vmx = to_vmx(vcpu);
840 struct kvm_msr_entry *msr;
2cc51560
ED		 841 int ret = 0;
842
6aa8b732 843 switch (msr_index) {
05b3e0c2 844#ifdef CONFIG_X86_64
3bab1f5d 845 case MSR_EFER:
2cc51560 846 ret = kvm_set_msr_common(vcpu, msr_index, data);
51c6cf66
AK		 847 if (vmx->host_state.loaded) {
848 reload_host_efer(vmx);
8b9cf98c 849 load_transition_efer(vmx);
51c6cf66 850 }
2cc51560 851 break;
6aa8b732
AK		 852 case MSR_FS_BASE:
853 vmcs_writel(GUEST_FS_BASE, data);
854 break;
855 case MSR_GS_BASE:
856 vmcs_writel(GUEST_GS_BASE, data);
857 break;
858#endif
859 case MSR_IA32_SYSENTER_CS:
860 vmcs_write32(GUEST_SYSENTER_CS, data);
861 break;
862 case MSR_IA32_SYSENTER_EIP:
f5b42c33 863 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 864 break;
865 case MSR_IA32_SYSENTER_ESP:
f5b42c33 866 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 867 break;
d27d4aca 868 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 869 guest_write_tsc(data);
870 break;
6aa8b732 871 default:
8b9cf98c 872 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 873 if (msr) {
874 msr->data = data;
a2fa3e9f
GH		 875 if (vmx->host_state.loaded)
876 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
3bab1f5d 877 break;
6aa8b732 878 }
2cc51560 879 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 880 }
881
2cc51560 882 return ret;
6aa8b732
AK		 883}
884
885/*
886 * Sync the rsp and rip registers into the vcpu structure. This allows
ad312c7c 887 * registers to be accessed by indexing vcpu->arch.regs.
6aa8b732
AK		 888 */
889static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
890{
ad312c7c
ZX		 891 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
892 vcpu->arch.rip = vmcs_readl(GUEST_RIP);
6aa8b732
AK		 893}
894
895/*
896 * Syncs rsp and rip back into the vmcs. Should be called after possible
897 * modification.
898 */
899static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
900{
ad312c7c
ZX		 901 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
902 vmcs_writel(GUEST_RIP, vcpu->arch.rip);
6aa8b732
AK		 903}
904
905static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
906{
907 unsigned long dr7 = 0x400;
6aa8b732
AK		 908 int old_singlestep;
909
6aa8b732
AK		 910 old_singlestep = vcpu->guest_debug.singlestep;
911
912 vcpu->guest_debug.enabled = dbg->enabled;
913 if (vcpu->guest_debug.enabled) {
914 int i;
915
916 dr7 |= 0x200; /* exact */
917 for (i = 0; i < 4; ++i) {
918 if (!dbg->breakpoints[i].enabled)
919 continue;
920 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
921 dr7 |= 2 << (i*2); /* global enable */
922 dr7 |= 0 << (i*4+16); /* execution breakpoint */
923 }
924
6aa8b732 925 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 926 } else
6aa8b732 927 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 928
929 if (old_singlestep && !vcpu->guest_debug.singlestep) {
930 unsigned long flags;
931
932 flags = vmcs_readl(GUEST_RFLAGS);
933 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
934 vmcs_writel(GUEST_RFLAGS, flags);
935 }
936
abd3f2d6 937 update_exception_bitmap(vcpu);
6aa8b732
AK		 938 vmcs_writel(GUEST_DR7, dr7);
939
940 return 0;
941}
942
2a8067f1
ED		 943static int vmx_get_irq(struct kvm_vcpu *vcpu)
944{
1155f76a 945 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a8067f1
ED		 946 u32 idtv_info_field;
947
1155f76a 948 idtv_info_field = vmx->idt_vectoring_info;
2a8067f1
ED		 949 if (idtv_info_field & INTR_INFO_VALID_MASK) {
950 if (is_external_interrupt(idtv_info_field))
951 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
952 else
d77c26fc 953 printk(KERN_DEBUG "pending exception: not handled yet\n");
2a8067f1
ED		 954 }
955 return -1;
956}
957
6aa8b732
AK		 958static __init int cpu_has_kvm_support(void)
959{
960 unsigned long ecx = cpuid_ecx(1);
961 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
962}
963
964static __init int vmx_disabled_by_bios(void)
965{
966 u64 msr;
967
968 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
62b3ffb8
YS		 969 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
970 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
971 == MSR_IA32_FEATURE_CONTROL_LOCKED;
972 /* locked but not enabled */
6aa8b732
AK		 973}
974
774c47f1 975static void hardware_enable(void *garbage)
6aa8b732
AK		 976{
977 int cpu = raw_smp_processor_id();
978 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
979 u64 old;
980
981 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
62b3ffb8
YS		 982 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
983 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
984 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
985 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 986 /* enable and lock */
62b3ffb8
YS		 987 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
988 MSR_IA32_FEATURE_CONTROL_LOCKED |
989 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 990 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
6aa8b732
AK		 991 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
992 : "memory", "cc");
993}
994
995static void hardware_disable(void *garbage)
996{
997 asm volatile (ASM_VMX_VMXOFF : : : "cc");
998}
999
1c3d14fe 1000static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1001 u32 msr, u32 *result)
1c3d14fe
YS		 1002{
1003 u32 vmx_msr_low, vmx_msr_high;
1004 u32 ctl = ctl_min | ctl_opt;
1005
1006 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1007
1008 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1009 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1010
1011 /* Ensure minimum (required) set of control bits are supported. */
1012 if (ctl_min & ~ctl)
002c7f7c 1013 return -EIO;
1c3d14fe
YS		 1014
1015 *result = ctl;
1016 return 0;
1017}
1018
002c7f7c 1019static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1020{
1021 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1022 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1023 u32 _pin_based_exec_control = 0;
1024 u32 _cpu_based_exec_control = 0;
f78e0e2e 1025 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1026 u32 _vmexit_control = 0;
1027 u32 _vmentry_control = 0;
1028
1029 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1030 opt = 0;
1031 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1032 &_pin_based_exec_control) < 0)
002c7f7c 1033 return -EIO;
1c3d14fe
YS		 1034
1035 min = CPU_BASED_HLT_EXITING |
1036#ifdef CONFIG_X86_64
1037 CPU_BASED_CR8_LOAD_EXITING |
1038 CPU_BASED_CR8_STORE_EXITING |
1039#endif
d56f546d
SY		 1040 CPU_BASED_CR3_LOAD_EXITING |
1041 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1042 CPU_BASED_USE_IO_BITMAPS |
1043 CPU_BASED_MOV_DR_EXITING |
1044 CPU_BASED_USE_TSC_OFFSETING;
f78e0e2e 1045 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1046 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1047 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1048 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1049 &_cpu_based_exec_control) < 0)
002c7f7c 1050 return -EIO;
6e5d865c
YS		 1051#ifdef CONFIG_X86_64
1052 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1053 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1054 ~CPU_BASED_CR8_STORE_EXITING;
1055#endif
f78e0e2e 1056 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1057 min2 = 0;
1058 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1059 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d
SY		 1060 SECONDARY_EXEC_ENABLE_VPID |
1061 SECONDARY_EXEC_ENABLE_EPT;
1062 if (adjust_vmx_controls(min2, opt2,
1063 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1064 &_cpu_based_2nd_exec_control) < 0)
1065 return -EIO;
1066 }
1067#ifndef CONFIG_X86_64
1068 if (!(_cpu_based_2nd_exec_control &
1069 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1070 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1071#endif
d56f546d
SY		 1072 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1073 /* CR3 accesses don't need to cause VM Exits when EPT enabled */
1074 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1075 CPU_BASED_CR3_STORE_EXITING);
1076 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1077 &_cpu_based_exec_control) < 0)
1078 return -EIO;
1079 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1080 vmx_capability.ept, vmx_capability.vpid);
1081 }
1c3d14fe
YS		 1082
1083 min = 0;
1084#ifdef CONFIG_X86_64
1085 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1086#endif
1087 opt = 0;
1088 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1089 &_vmexit_control) < 0)
002c7f7c 1090 return -EIO;
1c3d14fe
YS		 1091
1092 min = opt = 0;
1093 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1094 &_vmentry_control) < 0)
002c7f7c 1095 return -EIO;
6aa8b732 1096
c68876fd 1097 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1098
1099 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1100 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1101 return -EIO;
1c3d14fe
YS		 1102
1103#ifdef CONFIG_X86_64
1104 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1105 if (vmx_msr_high & (1u<<16))
002c7f7c 1106 return -EIO;
1c3d14fe
YS		 1107#endif
1108
1109 /* Require Write-Back (WB) memory type for VMCS accesses. */
1110 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1111 return -EIO;
1c3d14fe 1112
002c7f7c
YS		 1113 vmcs_conf->size = vmx_msr_high & 0x1fff;
1114 vmcs_conf->order = get_order(vmcs_config.size);
1115 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1116
002c7f7c
YS		 1117 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1118 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1119 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1120 vmcs_conf->vmexit_ctrl = _vmexit_control;
1121 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1122
1123 return 0;
c68876fd 1124}
6aa8b732
AK		 1125
1126static struct vmcs *alloc_vmcs_cpu(int cpu)
1127{
1128 int node = cpu_to_node(cpu);
1129 struct page *pages;
1130 struct vmcs *vmcs;
1131
1c3d14fe 1132 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1133 if (!pages)
1134 return NULL;
1135 vmcs = page_address(pages);
1c3d14fe
YS		 1136 memset(vmcs, 0, vmcs_config.size);
1137 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1138 return vmcs;
1139}
1140
1141static struct vmcs *alloc_vmcs(void)
1142{
d3b2c338 1143 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1144}
1145
1146static void free_vmcs(struct vmcs *vmcs)
1147{
1c3d14fe 1148 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1149}
1150
39959588 1151static void free_kvm_area(void)
6aa8b732
AK		 1152{
1153 int cpu;
1154
1155 for_each_online_cpu(cpu)
1156 free_vmcs(per_cpu(vmxarea, cpu));
1157}
1158
6aa8b732
AK		 1159static __init int alloc_kvm_area(void)
1160{
1161 int cpu;
1162
1163 for_each_online_cpu(cpu) {
1164 struct vmcs *vmcs;
1165
1166 vmcs = alloc_vmcs_cpu(cpu);
1167 if (!vmcs) {
1168 free_kvm_area();
1169 return -ENOMEM;
1170 }
1171
1172 per_cpu(vmxarea, cpu) = vmcs;
1173 }
1174 return 0;
1175}
1176
1177static __init int hardware_setup(void)
1178{
002c7f7c
YS		 1179 if (setup_vmcs_config(&vmcs_config) < 0)
1180 return -EIO;
50a37eb4
JR		 1181
1182 if (boot_cpu_has(X86_FEATURE_NX))
1183 kvm_enable_efer_bits(EFER_NX);
1184
6aa8b732
AK		 1185 return alloc_kvm_area();
1186}
1187
1188static __exit void hardware_unsetup(void)
1189{
1190 free_kvm_area();
1191}
1192
6aa8b732
AK		 1193static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1194{
1195 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1196
6af11b9e 1197 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1198 vmcs_write16(sf->selector, save->selector);
1199 vmcs_writel(sf->base, save->base);
1200 vmcs_write32(sf->limit, save->limit);
1201 vmcs_write32(sf->ar_bytes, save->ar);
1202 } else {
1203 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1204 << AR_DPL_SHIFT;
1205 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1206 }
1207}
1208
1209static void enter_pmode(struct kvm_vcpu *vcpu)
1210{
1211 unsigned long flags;
1212
ad312c7c 1213 vcpu->arch.rmode.active = 0;
6aa8b732 1214
ad312c7c
ZX		 1215 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1216 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1217 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
6aa8b732
AK		 1218
1219 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1220 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
ad312c7c 1221 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1222 vmcs_writel(GUEST_RFLAGS, flags);
1223
66aee91a
RR		 1224 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1225 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1226
1227 update_exception_bitmap(vcpu);
1228
ad312c7c
ZX		 1229 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1230 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1231 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1232 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
6aa8b732
AK		 1233
1234 vmcs_write16(GUEST_SS_SELECTOR, 0);
1235 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1236
1237 vmcs_write16(GUEST_CS_SELECTOR,
1238 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1239 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1240}
1241
d77c26fc 1242static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1243{
bfc6d222 1244 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1245 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1246 kvm->memslots[0].npages - 3;
1247 return base_gfn << PAGE_SHIFT;
1248 }
bfc6d222 1249 return kvm->arch.tss_addr;
6aa8b732
AK		 1250}
1251
1252static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1253{
1254 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1255
1256 save->selector = vmcs_read16(sf->selector);
1257 save->base = vmcs_readl(sf->base);
1258 save->limit = vmcs_read32(sf->limit);
1259 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1260 vmcs_write16(sf->selector, save->base >> 4);
1261 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1262 vmcs_write32(sf->limit, 0xffff);
1263 vmcs_write32(sf->ar_bytes, 0xf3);
1264}
1265
1266static void enter_rmode(struct kvm_vcpu *vcpu)
1267{
1268 unsigned long flags;
1269
ad312c7c 1270 vcpu->arch.rmode.active = 1;
6aa8b732 1271
ad312c7c 1272 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1273 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1274
ad312c7c 1275 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1276 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1277
ad312c7c 1278 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1279 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1280
1281 flags = vmcs_readl(GUEST_RFLAGS);
ad312c7c
ZX		 1282 vcpu->arch.rmode.save_iopl
1283 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1284
053de044 1285 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1286
1287 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1288 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1289 update_exception_bitmap(vcpu);
1290
1291 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1292 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1293 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1294
1295 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1296 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1297 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1298 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1299 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1300
ad312c7c
ZX		 1301 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1302 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1303 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1304 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
75880a01 1305
8668a3c4 1306 kvm_mmu_reset_context(vcpu);
b7ebfb05 1307 init_rmode(vcpu->kvm);
6aa8b732
AK		 1308}
1309
05b3e0c2 1310#ifdef CONFIG_X86_64
6aa8b732
AK		 1311
1312static void enter_lmode(struct kvm_vcpu *vcpu)
1313{
1314 u32 guest_tr_ar;
1315
1316 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1317 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1318 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1319 __func__);
6aa8b732
AK		 1320 vmcs_write32(GUEST_TR_AR_BYTES,
1321 (guest_tr_ar & ~AR_TYPE_MASK)
1322 | AR_TYPE_BUSY_64_TSS);
1323 }
1324
ad312c7c 1325 vcpu->arch.shadow_efer |= EFER_LMA;
6aa8b732 1326
8b9cf98c 1327 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1328 vmcs_write32(VM_ENTRY_CONTROLS,
1329 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1330 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1331}
1332
1333static void exit_lmode(struct kvm_vcpu *vcpu)
1334{
ad312c7c 1335 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1336
1337 vmcs_write32(VM_ENTRY_CONTROLS,
1338 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1339 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1340}
1341
1342#endif
1343
2384d2b3
SY		 1344static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1345{
1346 vpid_sync_vcpu_all(to_vmx(vcpu));
1347}
1348
25c4c276 1349static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1350{
ad312c7c
ZX		 1351 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1352 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1353}
1354
6aa8b732
AK		 1355static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1356{
5fd86fcf
AK		 1357 vmx_fpu_deactivate(vcpu);
1358
ad312c7c 1359 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1360 enter_pmode(vcpu);
1361
ad312c7c 1362 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1363 enter_rmode(vcpu);
1364
05b3e0c2 1365#ifdef CONFIG_X86_64
ad312c7c 1366 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1367 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1368 enter_lmode(vcpu);
707d92fa 1369 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1370 exit_lmode(vcpu);
1371 }
1372#endif
1373
1374 vmcs_writel(CR0_READ_SHADOW, cr0);
1375 vmcs_writel(GUEST_CR0,
1376 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
ad312c7c 1377 vcpu->arch.cr0 = cr0;
5fd86fcf 1378
707d92fa 1379 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1380 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1381}
1382
6aa8b732
AK		 1383static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1384{
2384d2b3 1385 vmx_flush_tlb(vcpu);
6aa8b732 1386 vmcs_writel(GUEST_CR3, cr3);
ad312c7c 1387 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1388 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1389}
1390
1391static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1392{
1393 vmcs_writel(CR4_READ_SHADOW, cr4);
ad312c7c 1394 vmcs_writel(GUEST_CR4, cr4 | (vcpu->arch.rmode.active ?
6aa8b732 1395 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
ad312c7c 1396 vcpu->arch.cr4 = cr4;
6aa8b732
AK		 1397}
1398
6aa8b732
AK		 1399static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1400{
8b9cf98c
RR		 1401 struct vcpu_vmx *vmx = to_vmx(vcpu);
1402 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732 1403
ad312c7c 1404 vcpu->arch.shadow_efer = efer;
9f62e19a
JR		 1405 if (!msr)
1406 return;
6aa8b732
AK		 1407 if (efer & EFER_LMA) {
1408 vmcs_write32(VM_ENTRY_CONTROLS,
1409 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1410 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1411 msr->data = efer;
1412
1413 } else {
1414 vmcs_write32(VM_ENTRY_CONTROLS,
1415 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1416 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1417
1418 msr->data = efer & ~EFER_LME;
1419 }
8b9cf98c 1420 setup_msrs(vmx);
6aa8b732
AK		 1421}
1422
6aa8b732
AK		 1423static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1424{
1425 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1426
1427 return vmcs_readl(sf->base);
1428}
1429
1430static void vmx_get_segment(struct kvm_vcpu *vcpu,
1431 struct kvm_segment *var, int seg)
1432{
1433 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1434 u32 ar;
1435
1436 var->base = vmcs_readl(sf->base);
1437 var->limit = vmcs_read32(sf->limit);
1438 var->selector = vmcs_read16(sf->selector);
1439 ar = vmcs_read32(sf->ar_bytes);
1440 if (ar & AR_UNUSABLE_MASK)
1441 ar = 0;
1442 var->type = ar & 15;
1443 var->s = (ar >> 4) & 1;
1444 var->dpl = (ar >> 5) & 3;
1445 var->present = (ar >> 7) & 1;
1446 var->avl = (ar >> 12) & 1;
1447 var->l = (ar >> 13) & 1;
1448 var->db = (ar >> 14) & 1;
1449 var->g = (ar >> 15) & 1;
1450 var->unusable = (ar >> 16) & 1;
1451}
1452
2e4d2653
IE		 1453static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1454{
1455 struct kvm_segment kvm_seg;
1456
1457 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1458 return 0;
1459
1460 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1461 return 3;
1462
1463 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1464 return kvm_seg.selector & 3;
1465}
1466
653e3108 1467static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1468{
6aa8b732
AK		 1469 u32 ar;
1470
653e3108 1471 if (var->unusable)
6aa8b732
AK		 1472 ar = 1 << 16;
1473 else {
1474 ar = var->type & 15;
1475 ar |= (var->s & 1) << 4;
1476 ar |= (var->dpl & 3) << 5;
1477 ar |= (var->present & 1) << 7;
1478 ar |= (var->avl & 1) << 12;
1479 ar |= (var->l & 1) << 13;
1480 ar |= (var->db & 1) << 14;
1481 ar |= (var->g & 1) << 15;
1482 }
f7fbf1fd
UL		 1483 if (ar == 0) /* a 0 value means unusable */
1484 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1485
1486 return ar;
1487}
1488
1489static void vmx_set_segment(struct kvm_vcpu *vcpu,
1490 struct kvm_segment *var, int seg)
1491{
1492 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1493 u32 ar;
1494
ad312c7c
ZX		 1495 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1496 vcpu->arch.rmode.tr.selector = var->selector;
1497 vcpu->arch.rmode.tr.base = var->base;
1498 vcpu->arch.rmode.tr.limit = var->limit;
1499 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1500 return;
1501 }
1502 vmcs_writel(sf->base, var->base);
1503 vmcs_write32(sf->limit, var->limit);
1504 vmcs_write16(sf->selector, var->selector);
ad312c7c 1505 if (vcpu->arch.rmode.active && var->s) {
653e3108
AK		 1506 /*
1507 * Hack real-mode segments into vm86 compatibility.
1508 */
1509 if (var->base == 0xffff0000 && var->selector == 0xf000)
1510 vmcs_writel(sf->base, 0xf0000);
1511 ar = 0xf3;
1512 } else
1513 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1514 vmcs_write32(sf->ar_bytes, ar);
1515}
1516
6aa8b732
AK		 1517static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1518{
1519 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1520
1521 *db = (ar >> 14) & 1;
1522 *l = (ar >> 13) & 1;
1523}
1524
1525static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1526{
1527 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1528 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1529}
1530
1531static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1532{
1533 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1534 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1535}
1536
1537static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1538{
1539 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1540 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1541}
1542
1543static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1544{
1545 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1546 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1547}
1548
d77c26fc 1549static int init_rmode_tss(struct kvm *kvm)
6aa8b732 1550{
6aa8b732 1551 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 1552 u16 data = 0;
10589a46 1553 int ret = 0;
195aefde 1554 int r;
6aa8b732 1555
195aefde
IE		 1556 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1557 if (r < 0)
10589a46 1558 goto out;
195aefde
IE		 1559 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1560 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1561 if (r < 0)
10589a46 1562 goto out;
195aefde
IE		 1563 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1564 if (r < 0)
10589a46 1565 goto out;
195aefde
IE		 1566 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1567 if (r < 0)
10589a46 1568 goto out;
195aefde 1569 data = ~0;
10589a46
MT		 1570 r = kvm_write_guest_page(kvm, fn, &data,
1571 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1572 sizeof(u8));
195aefde 1573 if (r < 0)
10589a46
MT		 1574 goto out;
1575
1576 ret = 1;
1577out:
10589a46 1578 return ret;
6aa8b732
AK		 1579}
1580
b7ebfb05
SY		 1581static int init_rmode_identity_map(struct kvm *kvm)
1582{
1583 int i, r, ret;
1584 pfn_t identity_map_pfn;
1585 u32 tmp;
1586
1587 if (!vm_need_ept())
1588 return 1;
1589 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1590 printk(KERN_ERR "EPT: identity-mapping pagetable "
1591 "haven't been allocated!\n");
1592 return 0;
1593 }
1594 if (likely(kvm->arch.ept_identity_pagetable_done))
1595 return 1;
1596 ret = 0;
1597 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1598 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1599 if (r < 0)
1600 goto out;
1601 /* Set up identity-mapping pagetable for EPT in real mode */
1602 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1603 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1604 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1605 r = kvm_write_guest_page(kvm, identity_map_pfn,
1606 &tmp, i * sizeof(tmp), sizeof(tmp));
1607 if (r < 0)
1608 goto out;
1609 }
1610 kvm->arch.ept_identity_pagetable_done = true;
1611 ret = 1;
1612out:
1613 return ret;
1614}
1615
6aa8b732
AK		 1616static void seg_setup(int seg)
1617{
1618 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1619
1620 vmcs_write16(sf->selector, 0);
1621 vmcs_writel(sf->base, 0);
1622 vmcs_write32(sf->limit, 0xffff);
1623 vmcs_write32(sf->ar_bytes, 0x93);
1624}
1625
f78e0e2e
SY		 1626static int alloc_apic_access_page(struct kvm *kvm)
1627{
1628 struct kvm_userspace_memory_region kvm_userspace_mem;
1629 int r = 0;
1630
72dc67a6 1631 down_write(&kvm->slots_lock);
bfc6d222 1632 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 1633 goto out;
1634 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1635 kvm_userspace_mem.flags = 0;
1636 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1637 kvm_userspace_mem.memory_size = PAGE_SIZE;
1638 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1639 if (r)
1640 goto out;
72dc67a6
IE		 1641
1642 down_read(&current->mm->mmap_sem);
bfc6d222 1643 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
72dc67a6 1644 up_read(&current->mm->mmap_sem);
f78e0e2e 1645out:
72dc67a6 1646 up_write(&kvm->slots_lock);
f78e0e2e
SY		 1647 return r;
1648}
1649
b7ebfb05
SY		 1650static int alloc_identity_pagetable(struct kvm *kvm)
1651{
1652 struct kvm_userspace_memory_region kvm_userspace_mem;
1653 int r = 0;
1654
1655 down_write(&kvm->slots_lock);
1656 if (kvm->arch.ept_identity_pagetable)
1657 goto out;
1658 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
1659 kvm_userspace_mem.flags = 0;
1660 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1661 kvm_userspace_mem.memory_size = PAGE_SIZE;
1662 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1663 if (r)
1664 goto out;
1665
1666 down_read(&current->mm->mmap_sem);
1667 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
1668 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
1669 up_read(&current->mm->mmap_sem);
1670out:
1671 up_write(&kvm->slots_lock);
1672 return r;
1673}
1674
2384d2b3
SY		 1675static void allocate_vpid(struct vcpu_vmx *vmx)
1676{
1677 int vpid;
1678
1679 vmx->vpid = 0;
1680 if (!enable_vpid || !cpu_has_vmx_vpid())
1681 return;
1682 spin_lock(&vmx_vpid_lock);
1683 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
1684 if (vpid < VMX_NR_VPIDS) {
1685 vmx->vpid = vpid;
1686 __set_bit(vpid, vmx_vpid_bitmap);
1687 }
1688 spin_unlock(&vmx_vpid_lock);
1689}
1690
25c5f225
SY		 1691void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
1692{
1693 void *va;
1694
1695 if (!cpu_has_vmx_msr_bitmap())
1696 return;
1697
1698 /*
1699 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
1700 * have the write-low and read-high bitmap offsets the wrong way round.
1701 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
1702 */
1703 va = kmap(msr_bitmap);
1704 if (msr <= 0x1fff) {
1705 __clear_bit(msr, va + 0x000); /* read-low */
1706 __clear_bit(msr, va + 0x800); /* write-low */
1707 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1708 msr &= 0x1fff;
1709 __clear_bit(msr, va + 0x400); /* read-high */
1710 __clear_bit(msr, va + 0xc00); /* write-high */
1711 }
1712 kunmap(msr_bitmap);
1713}
1714
6aa8b732
AK		 1715/*
1716 * Sets up the vmcs for emulated real mode.
1717 */
8b9cf98c 1718static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732
AK		 1719{
1720 u32 host_sysenter_cs;
1721 u32 junk;
1722 unsigned long a;
1723 struct descriptor_table dt;
1724 int i;
cd2276a7 1725 unsigned long kvm_vmx_return;
6e5d865c 1726 u32 exec_control;
6aa8b732 1727
6aa8b732 1728 /* I/O */
fdef3ad1
HQ		 1729 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1730 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732 1731
25c5f225
SY		 1732 if (cpu_has_vmx_msr_bitmap())
1733 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
1734
6aa8b732
AK		 1735 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1736
6aa8b732 1737 /* Control */
1c3d14fe
YS		 1738 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1739 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 1740
1741 exec_control = vmcs_config.cpu_based_exec_ctrl;
1742 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1743 exec_control &= ~CPU_BASED_TPR_SHADOW;
1744#ifdef CONFIG_X86_64
1745 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1746 CPU_BASED_CR8_LOAD_EXITING;
1747#endif
1748 }
d56f546d
SY		 1749 if (!vm_need_ept())
1750 exec_control |= CPU_BASED_CR3_STORE_EXITING |
1751 CPU_BASED_CR3_LOAD_EXITING;
6e5d865c 1752 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 1753
83ff3b9d
SY		 1754 if (cpu_has_secondary_exec_ctrls()) {
1755 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1756 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1757 exec_control &=
1758 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 1759 if (vmx->vpid == 0)
1760 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
d56f546d
SY		 1761 if (!vm_need_ept())
1762 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
83ff3b9d
SY		 1763 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1764 }
f78e0e2e 1765
c7addb90
AK		 1766 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1767 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 1768 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1769
1770 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1771 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1772 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1773
1774 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1775 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1776 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1777 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1778 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1779 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1780#ifdef CONFIG_X86_64
6aa8b732
AK		 1781 rdmsrl(MSR_FS_BASE, a);
1782 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1783 rdmsrl(MSR_GS_BASE, a);
1784 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1785#else
1786 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1787 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1788#endif
1789
1790 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1791
1792 get_idt(&dt);
1793 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1794
d77c26fc 1795 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 1796 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 1797 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1798 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1799 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 1800
1801 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1802 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1803 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1804 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1805 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1806 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1807
6aa8b732
AK		 1808 for (i = 0; i < NR_VMX_MSR; ++i) {
1809 u32 index = vmx_msr_index[i];
1810 u32 data_low, data_high;
1811 u64 data;
a2fa3e9f 1812 int j = vmx->nmsrs;
6aa8b732
AK		 1813
1814 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1815 continue;
432bd6cb
AK		 1816 if (wrmsr_safe(index, data_low, data_high) < 0)
1817 continue;
6aa8b732 1818 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 1819 vmx->host_msrs[j].index = index;
1820 vmx->host_msrs[j].reserved = 0;
1821 vmx->host_msrs[j].data = data;
1822 vmx->guest_msrs[j] = vmx->host_msrs[j];
1823 ++vmx->nmsrs;
6aa8b732 1824 }
6aa8b732 1825
1c3d14fe 1826 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 1827
1828 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 1829 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1830
e00c8cf2
AK		 1831 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1832 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1833
f78e0e2e 1834
e00c8cf2
AK		 1835 return 0;
1836}
1837
b7ebfb05
SY		 1838static int init_rmode(struct kvm *kvm)
1839{
1840 if (!init_rmode_tss(kvm))
1841 return 0;
1842 if (!init_rmode_identity_map(kvm))
1843 return 0;
1844 return 1;
1845}
1846
e00c8cf2
AK		 1847static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1848{
1849 struct vcpu_vmx *vmx = to_vmx(vcpu);
1850 u64 msr;
1851 int ret;
1852
3200f405 1853 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 1854 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 1855 ret = -ENOMEM;
1856 goto out;
1857 }
1858
ad312c7c 1859 vmx->vcpu.arch.rmode.active = 0;
e00c8cf2 1860
ad312c7c 1861 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 1862 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2
AK		 1863 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1864 if (vmx->vcpu.vcpu_id == 0)
1865 msr |= MSR_IA32_APICBASE_BSP;
1866 kvm_set_apic_base(&vmx->vcpu, msr);
1867
1868 fx_init(&vmx->vcpu);
1869
1870 /*
1871 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1872 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1873 */
1874 if (vmx->vcpu.vcpu_id == 0) {
1875 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1876 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1877 } else {
ad312c7c
ZX		 1878 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
1879 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2
AK		 1880 }
1881 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1882 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1883
1884 seg_setup(VCPU_SREG_DS);
1885 seg_setup(VCPU_SREG_ES);
1886 seg_setup(VCPU_SREG_FS);
1887 seg_setup(VCPU_SREG_GS);
1888 seg_setup(VCPU_SREG_SS);
1889
1890 vmcs_write16(GUEST_TR_SELECTOR, 0);
1891 vmcs_writel(GUEST_TR_BASE, 0);
1892 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1893 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1894
1895 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1896 vmcs_writel(GUEST_LDTR_BASE, 0);
1897 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1898 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1899
1900 vmcs_write32(GUEST_SYSENTER_CS, 0);
1901 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1902 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1903
1904 vmcs_writel(GUEST_RFLAGS, 0x02);
1905 if (vmx->vcpu.vcpu_id == 0)
1906 vmcs_writel(GUEST_RIP, 0xfff0);
1907 else
1908 vmcs_writel(GUEST_RIP, 0);
1909 vmcs_writel(GUEST_RSP, 0);
1910
1911 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1912 vmcs_writel(GUEST_DR7, 0x400);
1913
1914 vmcs_writel(GUEST_GDTR_BASE, 0);
1915 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1916
1917 vmcs_writel(GUEST_IDTR_BASE, 0);
1918 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1919
1920 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1921 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1922 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1923
1924 guest_write_tsc(0);
1925
1926 /* Special registers */
1927 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1928
1929 setup_msrs(vmx);
1930
6aa8b732
AK		 1931 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1932
f78e0e2e
SY		 1933 if (cpu_has_vmx_tpr_shadow()) {
1934 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1935 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1936 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 1937 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 1938 vmcs_write32(TPR_THRESHOLD, 0);
1939 }
1940
1941 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1942 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 1943 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 1944
2384d2b3
SY		 1945 if (vmx->vpid != 0)
1946 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
1947
ad312c7c
ZX		 1948 vmx->vcpu.arch.cr0 = 0x60000010;
1949 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 1950 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 1951 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 1952 vmx_fpu_activate(&vmx->vcpu);
1953 update_exception_bitmap(&vmx->vcpu);
6aa8b732 1954
2384d2b3
SY		 1955 vpid_sync_vcpu_all(vmx);
1956
3200f405 1957 ret = 0;
6aa8b732 1958
6aa8b732 1959out:
3200f405 1960 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 1961 return ret;
1962}
1963
85f455f7
ED		 1964static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1965{
9c8cba37
AK		 1966 struct vcpu_vmx *vmx = to_vmx(vcpu);
1967
2714d1d3
FEL		 1968 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
1969
ad312c7c 1970 if (vcpu->arch.rmode.active) {
9c8cba37
AK		 1971 vmx->rmode.irq.pending = true;
1972 vmx->rmode.irq.vector = irq;
1973 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
9c5623e3
AK		 1974 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1975 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1976 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
9c8cba37 1977 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
85f455f7
ED		 1978 return;
1979 }
1980 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1981 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1982}
1983
6aa8b732
AK		 1984static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1985{
ad312c7c
ZX		 1986 int word_index = __ffs(vcpu->arch.irq_summary);
1987 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
6aa8b732
AK		 1988 int irq = word_index * BITS_PER_LONG + bit_index;
1989
ad312c7c
ZX		 1990 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1991 if (!vcpu->arch.irq_pending[word_index])
1992 clear_bit(word_index, &vcpu->arch.irq_summary);
85f455f7 1993 vmx_inject_irq(vcpu, irq);
6aa8b732
AK		 1994}
1995
c1150d8c
DL		 1996
1997static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1998 struct kvm_run *kvm_run)
6aa8b732 1999{
c1150d8c
DL		 2000 u32 cpu_based_vm_exec_control;
2001
ad312c7c 2002 vcpu->arch.interrupt_window_open =
c1150d8c
DL		 2003 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2004 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2005
ad312c7c
ZX		 2006 if (vcpu->arch.interrupt_window_open &&
2007 vcpu->arch.irq_summary &&
c1150d8c 2008 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 2009 /*
c1150d8c 2010 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 2011 */
2012 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 2013
2014 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
ad312c7c
ZX		 2015 if (!vcpu->arch.interrupt_window_open &&
2016 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 2017 /*
2018 * Interrupts blocked. Wait for unblock.
2019 */
c1150d8c
DL		 2020 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2021 else
2022 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2023 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 2024}
2025
cbc94022
IE		 2026static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2027{
2028 int ret;
2029 struct kvm_userspace_memory_region tss_mem = {
2030 .slot = 8,
2031 .guest_phys_addr = addr,
2032 .memory_size = PAGE_SIZE * 3,
2033 .flags = 0,
2034 };
2035
2036 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2037 if (ret)
2038 return ret;
bfc6d222 2039 kvm->arch.tss_addr = addr;
cbc94022
IE		 2040 return 0;
2041}
2042
6aa8b732
AK		 2043static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2044{
2045 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2046
2047 set_debugreg(dbg->bp[0], 0);
2048 set_debugreg(dbg->bp[1], 1);
2049 set_debugreg(dbg->bp[2], 2);
2050 set_debugreg(dbg->bp[3], 3);
2051
2052 if (dbg->singlestep) {
2053 unsigned long flags;
2054
2055 flags = vmcs_readl(GUEST_RFLAGS);
2056 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2057 vmcs_writel(GUEST_RFLAGS, flags);
2058 }
2059}
2060
2061static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2062 int vec, u32 err_code)
2063{
ad312c7c 2064 if (!vcpu->arch.rmode.active)
6aa8b732
AK		 2065 return 0;
2066
b3f37707
NK		 2067 /*
2068 * Instruction with address size override prefix opcode 0x67
2069 * Cause the #SS fault with 0 error code in VM86 mode.
2070 */
2071 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 2072 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732
AK		 2073 return 1;
2074 return 0;
2075}
2076
2077static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2078{
1155f76a 2079 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 2080 u32 intr_info, error_code;
2081 unsigned long cr2, rip;
2082 u32 vect_info;
2083 enum emulation_result er;
2084
1155f76a 2085 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2086 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2087
2088 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 2089 !is_page_fault(intr_info))
6aa8b732 2090 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 2091 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 2092
85f455f7 2093 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732 2094 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
ad312c7c
ZX		 2095 set_bit(irq, vcpu->arch.irq_pending);
2096 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
6aa8b732
AK		 2097 }
2098
1b6269db
AK		 2099 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2100 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2101
2102 if (is_no_device(intr_info)) {
5fd86fcf 2103 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2104 return 1;
2105 }
2106
7aa81cc0 2107 if (is_invalid_opcode(intr_info)) {
571008da 2108 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2109 if (er != EMULATE_DONE)
7ee5d940 2110 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2111 return 1;
2112 }
2113
6aa8b732
AK		 2114 error_code = 0;
2115 rip = vmcs_readl(GUEST_RIP);
2e11384c 2116 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2117 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2118 if (is_page_fault(intr_info)) {
2119 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2714d1d3
FEL		 2120 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2121 (u32)((u64)cr2 >> 32), handler);
3067714c 2122 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2123 }
2124
ad312c7c 2125 if (vcpu->arch.rmode.active &&
6aa8b732 2126 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2127 error_code)) {
ad312c7c
ZX		 2128 if (vcpu->arch.halt_request) {
2129 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2130 return kvm_emulate_halt(vcpu);
2131 }
6aa8b732 2132 return 1;
72d6e5a0 2133 }
6aa8b732 2134
d77c26fc
MD		 2135 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2136 (INTR_TYPE_EXCEPTION | 1)) {
6aa8b732
AK		 2137 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2138 return 0;
2139 }
2140 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2141 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2142 kvm_run->ex.error_code = error_code;
2143 return 0;
2144}
2145
2146static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2147 struct kvm_run *kvm_run)
2148{
1165f5fe 2149 ++vcpu->stat.irq_exits;
2714d1d3 2150 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
6aa8b732
AK		 2151 return 1;
2152}
2153
988ad74f
AK		 2154static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2155{
2156 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2157 return 0;
2158}
6aa8b732 2159
6aa8b732
AK		 2160static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2161{
bfdaab09 2162 unsigned long exit_qualification;
039576c0
AK		 2163 int size, down, in, string, rep;
2164 unsigned port;
6aa8b732 2165
1165f5fe 2166 ++vcpu->stat.io_exits;
bfdaab09 2167 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2168 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2169
2170 if (string) {
3427318f
LV		 2171 if (emulate_instruction(vcpu,
2172 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2173 return 0;
2174 return 1;
2175 }
2176
2177 size = (exit_qualification & 7) + 1;
2178 in = (exit_qualification & 8) != 0;
039576c0 2179 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 2180 rep = (exit_qualification & 32) != 0;
2181 port = exit_qualification >> 16;
e70669ab 2182
3090dd73 2183 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 2184}
2185
102d8325
IM		 2186static void
2187vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2188{
2189 /*
2190 * Patch in the VMCALL instruction:
2191 */
2192 hypercall[0] = 0x0f;
2193 hypercall[1] = 0x01;
2194 hypercall[2] = 0xc1;
102d8325
IM		 2195}
2196
6aa8b732
AK		 2197static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2198{
bfdaab09 2199 unsigned long exit_qualification;
6aa8b732
AK		 2200 int cr;
2201 int reg;
2202
bfdaab09 2203 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2204 cr = exit_qualification & 15;
2205 reg = (exit_qualification >> 8) & 15;
2206 switch ((exit_qualification >> 4) & 3) {
2207 case 0: /* mov to cr */
2714d1d3
FEL		 2208 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)vcpu->arch.regs[reg],
2209 (u32)((u64)vcpu->arch.regs[reg] >> 32), handler);
6aa8b732
AK		 2210 switch (cr) {
2211 case 0:
2212 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2213 kvm_set_cr0(vcpu, vcpu->arch.regs[reg]);
6aa8b732
AK		 2214 skip_emulated_instruction(vcpu);
2215 return 1;
2216 case 3:
2217 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2218 kvm_set_cr3(vcpu, vcpu->arch.regs[reg]);
6aa8b732
AK		 2219 skip_emulated_instruction(vcpu);
2220 return 1;
2221 case 4:
2222 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2223 kvm_set_cr4(vcpu, vcpu->arch.regs[reg]);
6aa8b732
AK		 2224 skip_emulated_instruction(vcpu);
2225 return 1;
2226 case 8:
2227 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2228 kvm_set_cr8(vcpu, vcpu->arch.regs[reg]);
6aa8b732 2229 skip_emulated_instruction(vcpu);
e5314067
AK		 2230 if (irqchip_in_kernel(vcpu->kvm))
2231 return 1;
253abdee
YS		 2232 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2233 return 0;
6aa8b732
AK		 2234 };
2235 break;
25c4c276
AL		 2236 case 2: /* clts */
2237 vcpu_load_rsp_rip(vcpu);
5fd86fcf 2238 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2239 vcpu->arch.cr0 &= ~X86_CR0_TS;
2240 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2241 vmx_fpu_activate(vcpu);
2714d1d3 2242 KVMTRACE_0D(CLTS, vcpu, handler);
25c4c276
AL		 2243 skip_emulated_instruction(vcpu);
2244 return 1;
6aa8b732
AK		 2245 case 1: /*mov from cr*/
2246 switch (cr) {
2247 case 3:
2248 vcpu_load_rsp_rip(vcpu);
ad312c7c 2249 vcpu->arch.regs[reg] = vcpu->arch.cr3;
6aa8b732 2250 vcpu_put_rsp_rip(vcpu);
2714d1d3
FEL		 2251 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2252 (u32)vcpu->arch.regs[reg],
2253 (u32)((u64)vcpu->arch.regs[reg] >> 32),
2254 handler);
6aa8b732
AK		 2255 skip_emulated_instruction(vcpu);
2256 return 1;
2257 case 8:
6aa8b732 2258 vcpu_load_rsp_rip(vcpu);
2d3ad1f4 2259 vcpu->arch.regs[reg] = kvm_get_cr8(vcpu);
6aa8b732 2260 vcpu_put_rsp_rip(vcpu);
2714d1d3
FEL		 2261 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2262 (u32)vcpu->arch.regs[reg], handler);
6aa8b732
AK		 2263 skip_emulated_instruction(vcpu);
2264 return 1;
2265 }
2266 break;
2267 case 3: /* lmsw */
2d3ad1f4 2268 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2269
2270 skip_emulated_instruction(vcpu);
2271 return 1;
2272 default:
2273 break;
2274 }
2275 kvm_run->exit_reason = 0;
f0242478 2276 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2277 (int)(exit_qualification >> 4) & 3, cr);
2278 return 0;
2279}
2280
2281static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2282{
bfdaab09 2283 unsigned long exit_qualification;
6aa8b732
AK		 2284 unsigned long val;
2285 int dr, reg;
2286
2287 /*
2288 * FIXME: this code assumes the host is debugging the guest.
2289 * need to deal with guest debugging itself too.
2290 */
bfdaab09 2291 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2292 dr = exit_qualification & 7;
2293 reg = (exit_qualification >> 8) & 15;
2294 vcpu_load_rsp_rip(vcpu);
2295 if (exit_qualification & 16) {
2296 /* mov from dr */
2297 switch (dr) {
2298 case 6:
2299 val = 0xffff0ff0;
2300 break;
2301 case 7:
2302 val = 0x400;
2303 break;
2304 default:
2305 val = 0;
2306 }
ad312c7c 2307 vcpu->arch.regs[reg] = val;
2714d1d3 2308 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
6aa8b732
AK		 2309 } else {
2310 /* mov to dr */
2311 }
2312 vcpu_put_rsp_rip(vcpu);
2313 skip_emulated_instruction(vcpu);
2314 return 1;
2315}
2316
2317static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2318{
06465c5a
AK		 2319 kvm_emulate_cpuid(vcpu);
2320 return 1;
6aa8b732
AK		 2321}
2322
2323static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2324{
ad312c7c 2325 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2326 u64 data;
2327
2328 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 2329 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2330 return 1;
2331 }
2332
2714d1d3
FEL		 2333 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2334 handler);
2335
6aa8b732 2336 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 2337 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2338 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 2339 skip_emulated_instruction(vcpu);
2340 return 1;
2341}
2342
2343static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2344{
ad312c7c
ZX		 2345 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2346 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2347 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 2348
2714d1d3
FEL		 2349 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2350 handler);
2351
6aa8b732 2352 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 2353 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2354 return 1;
2355 }
2356
2357 skip_emulated_instruction(vcpu);
2358 return 1;
2359}
2360
6e5d865c
YS		 2361static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2362 struct kvm_run *kvm_run)
2363{
2364 return 1;
2365}
2366
6aa8b732
AK		 2367static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2368 struct kvm_run *kvm_run)
2369{
85f455f7
ED		 2370 u32 cpu_based_vm_exec_control;
2371
2372 /* clear pending irq */
2373 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2374 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2375 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3
FEL		 2376
2377 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2378
c1150d8c
DL		 2379 /*
2380 * If the user space waits to inject interrupts, exit as soon as
2381 * possible
2382 */
2383 if (kvm_run->request_interrupt_window &&
ad312c7c 2384 !vcpu->arch.irq_summary) {
c1150d8c 2385 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 2386 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 2387 return 0;
2388 }
6aa8b732
AK		 2389 return 1;
2390}
2391
2392static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2393{
2394 skip_emulated_instruction(vcpu);
d3bef15f 2395 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2396}
2397
c21415e8
IM		 2398static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2399{
510043da 2400 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2401 kvm_emulate_hypercall(vcpu);
2402 return 1;
c21415e8
IM		 2403}
2404
e5edaa01
ED		 2405static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2406{
2407 skip_emulated_instruction(vcpu);
2408 /* TODO: Add support for VT-d/pass-through device */
2409 return 1;
2410}
2411
f78e0e2e
SY		 2412static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2413{
2414 u64 exit_qualification;
2415 enum emulation_result er;
2416 unsigned long offset;
2417
2418 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2419 offset = exit_qualification & 0xffful;
2420
2714d1d3
FEL		 2421 KVMTRACE_1D(APIC_ACCESS, vcpu, (u32)offset, handler);
2422
f78e0e2e
SY		 2423 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2424
2425 if (er != EMULATE_DONE) {
2426 printk(KERN_ERR
2427 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2428 offset);
2429 return -ENOTSUPP;
2430 }
2431 return 1;
2432}
2433
37817f29
IE		 2434static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2435{
2436 unsigned long exit_qualification;
2437 u16 tss_selector;
2438 int reason;
2439
2440 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2441
2442 reason = (u32)exit_qualification >> 30;
2443 tss_selector = exit_qualification;
2444
2445 return kvm_task_switch(vcpu, tss_selector, reason);
2446}
2447
6aa8b732
AK		 2448/*
2449 * The exit handlers return 1 if the exit was handled fully and guest execution
2450 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2451 * to be done to userspace and return 0.
2452 */
2453static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2454 struct kvm_run *kvm_run) = {
2455 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2456 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 2457 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 2458 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 2459 [EXIT_REASON_CR_ACCESS] = handle_cr,
2460 [EXIT_REASON_DR_ACCESS] = handle_dr,
2461 [EXIT_REASON_CPUID] = handle_cpuid,
2462 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2463 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2464 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2465 [EXIT_REASON_HLT] = handle_halt,
c21415e8 2466 [EXIT_REASON_VMCALL] = handle_vmcall,
f78e0e2e
SY		 2467 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
2468 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 2469 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 2470 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
6aa8b732
AK		 2471};
2472
2473static const int kvm_vmx_max_exit_handlers =
50a3485c 2474 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 2475
2476/*
2477 * The guest has exited. See if we can fix it or if we need userspace
2478 * assistance.
2479 */
2480static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2481{
6aa8b732 2482 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78 2483 struct vcpu_vmx *vmx = to_vmx(vcpu);
1155f76a 2484 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 2485
2714d1d3
FEL		 2486 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)vmcs_readl(GUEST_RIP),
2487 (u32)((u64)vmcs_readl(GUEST_RIP) >> 32), entryexit);
2488
29bd8a78
AK		 2489 if (unlikely(vmx->fail)) {
2490 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2491 kvm_run->fail_entry.hardware_entry_failure_reason
2492 = vmcs_read32(VM_INSTRUCTION_ERROR);
2493 return 0;
2494 }
6aa8b732 2495
d77c26fc
MD		 2496 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2497 exit_reason != EXIT_REASON_EXCEPTION_NMI)
6aa8b732 2498 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
b8688d51 2499 "exit reason is 0x%x\n", __func__, exit_reason);
6aa8b732
AK		 2500 if (exit_reason < kvm_vmx_max_exit_handlers
2501 && kvm_vmx_exit_handlers[exit_reason])
2502 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2503 else {
2504 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2505 kvm_run->hw.hardware_exit_reason = exit_reason;
2506 }
2507 return 0;
2508}
2509
6e5d865c
YS		 2510static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2511{
2512 int max_irr, tpr;
2513
2514 if (!vm_need_tpr_shadow(vcpu->kvm))
2515 return;
2516
2517 if (!kvm_lapic_enabled(vcpu) ||
2518 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2519 vmcs_write32(TPR_THRESHOLD, 0);
2520 return;
2521 }
2522
2523 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2524 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2525}
2526
85f455f7
ED		 2527static void enable_irq_window(struct kvm_vcpu *vcpu)
2528{
2529 u32 cpu_based_vm_exec_control;
2530
2531 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2532 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2533 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2534}
2535
2536static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2537{
1155f76a 2538 struct vcpu_vmx *vmx = to_vmx(vcpu);
85f455f7
ED		 2539 u32 idtv_info_field, intr_info_field;
2540 int has_ext_irq, interrupt_window_open;
1b9778da 2541 int vector;
85f455f7 2542
6e5d865c
YS		 2543 update_tpr_threshold(vcpu);
2544
85f455f7
ED		 2545 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2546 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
1155f76a 2547 idtv_info_field = vmx->idt_vectoring_info;
85f455f7
ED		 2548 if (intr_info_field & INTR_INFO_VALID_MASK) {
2549 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2550 /* TODO: fault when IDT_Vectoring */
9584bf2c
RH		 2551 if (printk_ratelimit())
2552 printk(KERN_ERR "Fault when IDT_Vectoring\n");
85f455f7
ED		 2553 }
2554 if (has_ext_irq)
2555 enable_irq_window(vcpu);
2556 return;
2557 }
2558 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
9c8cba37
AK		 2559 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2560 == INTR_TYPE_EXT_INTR
ad312c7c 2561 && vcpu->arch.rmode.active) {
9c8cba37
AK		 2562 u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2563
2564 vmx_inject_irq(vcpu, vect);
2565 if (unlikely(has_ext_irq))
2566 enable_irq_window(vcpu);
2567 return;
2568 }
2569
2714d1d3
FEL		 2570 KVMTRACE_1D(REDELIVER_EVT, vcpu, idtv_info_field, handler);
2571
85f455f7
ED		 2572 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2573 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2574 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2575
2e11384c 2576 if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK))
85f455f7
ED		 2577 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2578 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2579 if (unlikely(has_ext_irq))
2580 enable_irq_window(vcpu);
2581 return;
2582 }
2583 if (!has_ext_irq)
2584 return;
2585 interrupt_window_open =
2586 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2587 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1b9778da
ED		 2588 if (interrupt_window_open) {
2589 vector = kvm_cpu_get_interrupt(vcpu);
2590 vmx_inject_irq(vcpu, vector);
2591 kvm_timer_intr_post(vcpu, vector);
2592 } else
85f455f7
ED		 2593 enable_irq_window(vcpu);
2594}
2595
9c8cba37
AK		 2596/*
2597 * Failure to inject an interrupt should give us the information
2598 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
2599 * when fetching the interrupt redirection bitmap in the real-mode
2600 * tss, this doesn't happen. So we do it ourselves.
2601 */
2602static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2603{
2604 vmx->rmode.irq.pending = 0;
2605 if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2606 return;
2607 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2608 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2609 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2610 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2611 return;
2612 }
2613 vmx->idt_vectoring_info =
2614 VECTORING_INFO_VALID_MASK
2615 | INTR_TYPE_EXT_INTR
2616 | vmx->rmode.irq.vector;
2617}
2618
04d2cc77 2619static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2620{
a2fa3e9f 2621 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 2622 u32 intr_info;
e6adf283
AK		 2623
2624 /*
2625 * Loading guest fpu may have cleared host cr0.ts
2626 */
2627 vmcs_writel(HOST_CR0, read_cr0());
2628
d77c26fc 2629 asm(
6aa8b732 2630 /* Store host registers */
05b3e0c2 2631#ifdef CONFIG_X86_64
c2036300 2632 "push %%rdx; push %%rbp;"
6aa8b732 2633 "push %%rcx \n\t"
6aa8b732 2634#else
ff593e5a
LV		 2635 "push %%edx; push %%ebp;"
2636 "push %%ecx \n\t"
6aa8b732 2637#endif
c2036300 2638 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
6aa8b732 2639 /* Check if vmlaunch of vmresume is needed */
e08aa78a 2640 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 2641 /* Load guest registers. Don't clobber flags. */
05b3e0c2 2642#ifdef CONFIG_X86_64
e08aa78a 2643 "mov %c[cr2](%0), %%rax \n\t"
6aa8b732 2644 "mov %%rax, %%cr2 \n\t"
e08aa78a
AK		 2645 "mov %c[rax](%0), %%rax \n\t"
2646 "mov %c[rbx](%0), %%rbx \n\t"
2647 "mov %c[rdx](%0), %%rdx \n\t"
2648 "mov %c[rsi](%0), %%rsi \n\t"
2649 "mov %c[rdi](%0), %%rdi \n\t"
2650 "mov %c[rbp](%0), %%rbp \n\t"
2651 "mov %c[r8](%0), %%r8 \n\t"
2652 "mov %c[r9](%0), %%r9 \n\t"
2653 "mov %c[r10](%0), %%r10 \n\t"
2654 "mov %c[r11](%0), %%r11 \n\t"
2655 "mov %c[r12](%0), %%r12 \n\t"
2656 "mov %c[r13](%0), %%r13 \n\t"
2657 "mov %c[r14](%0), %%r14 \n\t"
2658 "mov %c[r15](%0), %%r15 \n\t"
2659 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
6aa8b732 2660#else
e08aa78a 2661 "mov %c[cr2](%0), %%eax \n\t"
6aa8b732 2662 "mov %%eax, %%cr2 \n\t"
e08aa78a
AK		 2663 "mov %c[rax](%0), %%eax \n\t"
2664 "mov %c[rbx](%0), %%ebx \n\t"
2665 "mov %c[rdx](%0), %%edx \n\t"
2666 "mov %c[rsi](%0), %%esi \n\t"
2667 "mov %c[rdi](%0), %%edi \n\t"
2668 "mov %c[rbp](%0), %%ebp \n\t"
2669 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
6aa8b732
AK		 2670#endif
2671 /* Enter guest mode */
cd2276a7 2672 "jne .Llaunched \n\t"
6aa8b732 2673 ASM_VMX_VMLAUNCH "\n\t"
cd2276a7
AK		 2674 "jmp .Lkvm_vmx_return \n\t"
2675 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2676 ".Lkvm_vmx_return: "
6aa8b732 2677 /* Save guest registers, load host registers, keep flags */
05b3e0c2 2678#ifdef CONFIG_X86_64
e08aa78a
AK		 2679 "xchg %0, (%%rsp) \n\t"
2680 "mov %%rax, %c[rax](%0) \n\t"
2681 "mov %%rbx, %c[rbx](%0) \n\t"
2682 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2683 "mov %%rdx, %c[rdx](%0) \n\t"
2684 "mov %%rsi, %c[rsi](%0) \n\t"
2685 "mov %%rdi, %c[rdi](%0) \n\t"
2686 "mov %%rbp, %c[rbp](%0) \n\t"
2687 "mov %%r8, %c[r8](%0) \n\t"
2688 "mov %%r9, %c[r9](%0) \n\t"
2689 "mov %%r10, %c[r10](%0) \n\t"
2690 "mov %%r11, %c[r11](%0) \n\t"
2691 "mov %%r12, %c[r12](%0) \n\t"
2692 "mov %%r13, %c[r13](%0) \n\t"
2693 "mov %%r14, %c[r14](%0) \n\t"
2694 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 2695 "mov %%cr2, %%rax \n\t"
e08aa78a 2696 "mov %%rax, %c[cr2](%0) \n\t"
6aa8b732 2697
e08aa78a 2698 "pop %%rbp; pop %%rbp; pop %%rdx \n\t"
6aa8b732 2699#else
e08aa78a
AK		 2700 "xchg %0, (%%esp) \n\t"
2701 "mov %%eax, %c[rax](%0) \n\t"
2702 "mov %%ebx, %c[rbx](%0) \n\t"
2703 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2704 "mov %%edx, %c[rdx](%0) \n\t"
2705 "mov %%esi, %c[rsi](%0) \n\t"
2706 "mov %%edi, %c[rdi](%0) \n\t"
2707 "mov %%ebp, %c[rbp](%0) \n\t"
6aa8b732 2708 "mov %%cr2, %%eax \n\t"
e08aa78a 2709 "mov %%eax, %c[cr2](%0) \n\t"
6aa8b732 2710
e08aa78a 2711 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
6aa8b732 2712#endif
e08aa78a
AK		 2713 "setbe %c[fail](%0) \n\t"
2714 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2715 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2716 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
ad312c7c
ZX		 2717 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
2718 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
2719 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
2720 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
2721 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
2722 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
2723 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 2724#ifdef CONFIG_X86_64
ad312c7c
ZX		 2725 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
2726 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
2727 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
2728 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
2729 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
2730 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
2731 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
2732 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 2733#endif
ad312c7c 2734 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300
LV		 2735 : "cc", "memory"
2736#ifdef CONFIG_X86_64
2737 , "rbx", "rdi", "rsi"
2738 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
ff593e5a
LV		 2739#else
2740 , "ebx", "edi", "rsi"
c2036300
LV		 2741#endif
2742 );
6aa8b732 2743
1155f76a 2744 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 2745 if (vmx->rmode.irq.pending)
2746 fixup_rmode_irq(vmx);
1155f76a 2747
ad312c7c 2748 vcpu->arch.interrupt_window_open =
d77c26fc 2749 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2750
d77c26fc 2751 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 2752 vmx->launched = 1;
1b6269db
AK		 2753
2754 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2755
2756 /* We need to handle NMIs before interrupts are enabled */
2714d1d3
FEL		 2757 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
2758 KVMTRACE_0D(NMI, vcpu, handler);
1b6269db 2759 asm("int $2");
2714d1d3 2760 }
6aa8b732
AK		 2761}
2762
6aa8b732
AK		 2763static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2764{
a2fa3e9f
GH		 2765 struct vcpu_vmx *vmx = to_vmx(vcpu);
2766
2767 if (vmx->vmcs) {
8b9cf98c 2768 on_each_cpu(__vcpu_clear, vmx, 0, 1);
a2fa3e9f
GH		 2769 free_vmcs(vmx->vmcs);
2770 vmx->vmcs = NULL;
6aa8b732
AK		 2771 }
2772}
2773
2774static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2775{
fb3f0f51
RR		 2776 struct vcpu_vmx *vmx = to_vmx(vcpu);
2777
2384d2b3
SY		 2778 spin_lock(&vmx_vpid_lock);
2779 if (vmx->vpid != 0)
2780 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2781 spin_unlock(&vmx_vpid_lock);
6aa8b732 2782 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 2783 kfree(vmx->host_msrs);
2784 kfree(vmx->guest_msrs);
2785 kvm_vcpu_uninit(vcpu);
a4770347 2786 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 2787}
2788
fb3f0f51 2789static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 2790{
fb3f0f51 2791 int err;
c16f862d 2792 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 2793 int cpu;
6aa8b732 2794
a2fa3e9f 2795 if (!vmx)
fb3f0f51
RR		 2796 return ERR_PTR(-ENOMEM);
2797
2384d2b3
SY		 2798 allocate_vpid(vmx);
2799
fb3f0f51
RR		 2800 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2801 if (err)
2802 goto free_vcpu;
965b58a5 2803
a2fa3e9f 2804 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 2805 if (!vmx->guest_msrs) {
2806 err = -ENOMEM;
2807 goto uninit_vcpu;
2808 }
965b58a5 2809
a2fa3e9f
GH		 2810 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2811 if (!vmx->host_msrs)
fb3f0f51 2812 goto free_guest_msrs;
965b58a5 2813
a2fa3e9f
GH		 2814 vmx->vmcs = alloc_vmcs();
2815 if (!vmx->vmcs)
fb3f0f51 2816 goto free_msrs;
a2fa3e9f
GH		 2817
2818 vmcs_clear(vmx->vmcs);
2819
15ad7146
AK		 2820 cpu = get_cpu();
2821 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 2822 err = vmx_vcpu_setup(vmx);
fb3f0f51 2823 vmx_vcpu_put(&vmx->vcpu);
15ad7146 2824 put_cpu();
fb3f0f51
RR		 2825 if (err)
2826 goto free_vmcs;
5e4a0b3c
MT		 2827 if (vm_need_virtualize_apic_accesses(kvm))
2828 if (alloc_apic_access_page(kvm) != 0)
2829 goto free_vmcs;
fb3f0f51 2830
b7ebfb05
SY		 2831 if (vm_need_ept())
2832 if (alloc_identity_pagetable(kvm) != 0)
2833 goto free_vmcs;
2834
fb3f0f51
RR		 2835 return &vmx->vcpu;
2836
2837free_vmcs:
2838 free_vmcs(vmx->vmcs);
2839free_msrs:
2840 kfree(vmx->host_msrs);
2841free_guest_msrs:
2842 kfree(vmx->guest_msrs);
2843uninit_vcpu:
2844 kvm_vcpu_uninit(&vmx->vcpu);
2845free_vcpu:
a4770347 2846 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 2847 return ERR_PTR(err);
6aa8b732
AK		 2848}
2849
002c7f7c
YS		 2850static void __init vmx_check_processor_compat(void *rtn)
2851{
2852 struct vmcs_config vmcs_conf;
2853
2854 *(int *)rtn = 0;
2855 if (setup_vmcs_config(&vmcs_conf) < 0)
2856 *(int *)rtn = -EIO;
2857 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2858 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2859 smp_processor_id());
2860 *(int *)rtn = -EIO;
2861 }
2862}
2863
67253af5
SY		 2864static int get_ept_level(void)
2865{
2866 return VMX_EPT_DEFAULT_GAW + 1;
2867}
2868
cbdd1bea 2869static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 2870 .cpu_has_kvm_support = cpu_has_kvm_support,
2871 .disabled_by_bios = vmx_disabled_by_bios,
2872 .hardware_setup = hardware_setup,
2873 .hardware_unsetup = hardware_unsetup,
002c7f7c 2874 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 2875 .hardware_enable = hardware_enable,
2876 .hardware_disable = hardware_disable,
774ead3a 2877 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
6aa8b732
AK		 2878
2879 .vcpu_create = vmx_create_vcpu,
2880 .vcpu_free = vmx_free_vcpu,
04d2cc77 2881 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 2882
04d2cc77 2883 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 2884 .vcpu_load = vmx_vcpu_load,
2885 .vcpu_put = vmx_vcpu_put,
774c47f1 2886 .vcpu_decache = vmx_vcpu_decache,
6aa8b732
AK		 2887
2888 .set_guest_debug = set_guest_debug,
04d2cc77 2889 .guest_debug_pre = kvm_guest_debug_pre,
6aa8b732
AK		 2890 .get_msr = vmx_get_msr,
2891 .set_msr = vmx_set_msr,
2892 .get_segment_base = vmx_get_segment_base,
2893 .get_segment = vmx_get_segment,
2894 .set_segment = vmx_set_segment,
2e4d2653 2895 .get_cpl = vmx_get_cpl,
6aa8b732 2896 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 2897 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 2898 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 2899 .set_cr3 = vmx_set_cr3,
2900 .set_cr4 = vmx_set_cr4,
6aa8b732 2901 .set_efer = vmx_set_efer,
6aa8b732
AK		 2902 .get_idt = vmx_get_idt,
2903 .set_idt = vmx_set_idt,
2904 .get_gdt = vmx_get_gdt,
2905 .set_gdt = vmx_set_gdt,
2906 .cache_regs = vcpu_load_rsp_rip,
2907 .decache_regs = vcpu_put_rsp_rip,
2908 .get_rflags = vmx_get_rflags,
2909 .set_rflags = vmx_set_rflags,
2910
2911 .tlb_flush = vmx_flush_tlb,
6aa8b732 2912
6aa8b732 2913 .run = vmx_vcpu_run,
04d2cc77 2914 .handle_exit = kvm_handle_exit,
6aa8b732 2915 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 2916 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 2917 .get_irq = vmx_get_irq,
2918 .set_irq = vmx_inject_irq,
298101da
AK		 2919 .queue_exception = vmx_queue_exception,
2920 .exception_injected = vmx_exception_injected,
04d2cc77
AK		 2921 .inject_pending_irq = vmx_intr_assist,
2922 .inject_pending_vectors = do_interrupt_requests,
cbc94022
IE		 2923
2924 .set_tss_addr = vmx_set_tss_addr,
67253af5 2925 .get_tdp_level = get_ept_level,
6aa8b732
AK		 2926};
2927
2928static int __init vmx_init(void)
2929{
25c5f225 2930 void *va;
fdef3ad1
HQ		 2931 int r;
2932
2933 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2934 if (!vmx_io_bitmap_a)
2935 return -ENOMEM;
2936
2937 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2938 if (!vmx_io_bitmap_b) {
2939 r = -ENOMEM;
2940 goto out;
2941 }
2942
25c5f225
SY		 2943 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2944 if (!vmx_msr_bitmap) {
2945 r = -ENOMEM;
2946 goto out1;
2947 }
2948
fdef3ad1
HQ		 2949 /*
2950 * Allow direct access to the PC debug port (it is often used for I/O
2951 * delays, but the vmexits simply slow things down).
2952 */
25c5f225
SY		 2953 va = kmap(vmx_io_bitmap_a);
2954 memset(va, 0xff, PAGE_SIZE);
2955 clear_bit(0x80, va);
cd0536d7 2956 kunmap(vmx_io_bitmap_a);
fdef3ad1 2957
25c5f225
SY		 2958 va = kmap(vmx_io_bitmap_b);
2959 memset(va, 0xff, PAGE_SIZE);
cd0536d7 2960 kunmap(vmx_io_bitmap_b);
fdef3ad1 2961
25c5f225
SY		 2962 va = kmap(vmx_msr_bitmap);
2963 memset(va, 0xff, PAGE_SIZE);
2964 kunmap(vmx_msr_bitmap);
2965
2384d2b3
SY		 2966 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
2967
cb498ea2 2968 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 2969 if (r)
25c5f225
SY		 2970 goto out2;
2971
2972 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
2973 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
2974 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
2975 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
2976 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
fdef3ad1 2977
c7addb90
AK		 2978 if (bypass_guest_pf)
2979 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2980
fdef3ad1
HQ		 2981 return 0;
2982
25c5f225
SY		 2983out2:
2984 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 2985out1:
2986 __free_page(vmx_io_bitmap_b);
2987out:
2988 __free_page(vmx_io_bitmap_a);
2989 return r;
6aa8b732
AK		 2990}
2991
2992static void __exit vmx_exit(void)
2993{
25c5f225 2994 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 2995 __free_page(vmx_io_bitmap_b);
2996 __free_page(vmx_io_bitmap_a);
2997
cb498ea2 2998 kvm_exit();
6aa8b732
AK		 2999}
3000
3001module_init(vmx_init)
3002module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)