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KVM: Limit vcpu mmap size to one page on non-x86
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
6aa8b732 19#include "vmx.h"
e495606d 20#include "segment_descriptor.h"
1d737c8a 21#include "mmu.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e495606d 30
6aa8b732 31#include <asm/io.h>
3b3be0d1 32#include <asm/desc.h>
6aa8b732 33
6aa8b732
AK		 34MODULE_AUTHOR("Qumranet");
35MODULE_LICENSE("GPL");
36
c7addb90
AK		 37static int bypass_guest_pf = 1;
38module_param(bypass_guest_pf, bool, 0);
39
a2fa3e9f
GH		 40struct vmcs {
41 u32 revision_id;
42 u32 abort;
43 char data[0];
44};
45
46struct vcpu_vmx {
fb3f0f51 47 struct kvm_vcpu vcpu;
a2fa3e9f 48 int launched;
29bd8a78 49 u8 fail;
1155f76a 50 u32 idt_vectoring_info;
a2fa3e9f
GH		 51 struct kvm_msr_entry *guest_msrs;
52 struct kvm_msr_entry *host_msrs;
53 int nmsrs;
54 int save_nmsrs;
55 int msr_offset_efer;
56#ifdef CONFIG_X86_64
57 int msr_offset_kernel_gs_base;
58#endif
59 struct vmcs *vmcs;
60 struct {
61 int loaded;
62 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 63 int gs_ldt_reload_needed;
64 int fs_reload_needed;
51c6cf66 65 int guest_efer_loaded;
d77c26fc 66 } host_state;
9c8cba37
AK		 67 struct {
68 struct {
69 bool pending;
70 u8 vector;
71 unsigned rip;
72 } irq;
73 } rmode;
a2fa3e9f
GH		 74};
75
76static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
77{
fb3f0f51 78 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 79}
80
75880a01
AK		 81static int init_rmode_tss(struct kvm *kvm);
82
6aa8b732
AK		 83static DEFINE_PER_CPU(struct vmcs *, vmxarea);
84static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
85
fdef3ad1
HQ		 86static struct page *vmx_io_bitmap_a;
87static struct page *vmx_io_bitmap_b;
88
1c3d14fe 89static struct vmcs_config {
6aa8b732
AK		 90 int size;
91 int order;
92 u32 revision_id;
1c3d14fe
YS		 93 u32 pin_based_exec_ctrl;
94 u32 cpu_based_exec_ctrl;
f78e0e2e 95 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 96 u32 vmexit_ctrl;
97 u32 vmentry_ctrl;
98} vmcs_config;
6aa8b732
AK		 99
100#define VMX_SEGMENT_FIELD(seg) \
101 [VCPU_SREG_##seg] = { \
102 .selector = GUEST_##seg##_SELECTOR, \
103 .base = GUEST_##seg##_BASE, \
104 .limit = GUEST_##seg##_LIMIT, \
105 .ar_bytes = GUEST_##seg##_AR_BYTES, \
106 }
107
108static struct kvm_vmx_segment_field {
109 unsigned selector;
110 unsigned base;
111 unsigned limit;
112 unsigned ar_bytes;
113} kvm_vmx_segment_fields[] = {
114 VMX_SEGMENT_FIELD(CS),
115 VMX_SEGMENT_FIELD(DS),
116 VMX_SEGMENT_FIELD(ES),
117 VMX_SEGMENT_FIELD(FS),
118 VMX_SEGMENT_FIELD(GS),
119 VMX_SEGMENT_FIELD(SS),
120 VMX_SEGMENT_FIELD(TR),
121 VMX_SEGMENT_FIELD(LDTR),
122};
123
4d56c8a7
AK		 124/*
125 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
126 * away by decrementing the array size.
127 */
6aa8b732 128static const u32 vmx_msr_index[] = {
05b3e0c2 129#ifdef CONFIG_X86_64
6aa8b732
AK		 130 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
131#endif
132 MSR_EFER, MSR_K6_STAR,
133};
9d8f549d 134#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 135
a2fa3e9f
GH		 136static void load_msrs(struct kvm_msr_entry *e, int n)
137{
138 int i;
139
140 for (i = 0; i < n; ++i)
141 wrmsrl(e[i].index, e[i].data);
142}
143
144static void save_msrs(struct kvm_msr_entry *e, int n)
145{
146 int i;
147
148 for (i = 0; i < n; ++i)
149 rdmsrl(e[i].index, e[i].data);
150}
151
6aa8b732
AK		 152static inline int is_page_fault(u32 intr_info)
153{
154 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
155 INTR_INFO_VALID_MASK)) ==
156 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
157}
158
2ab455cc
AL		 159static inline int is_no_device(u32 intr_info)
160{
161 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
162 INTR_INFO_VALID_MASK)) ==
163 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
164}
165
7aa81cc0
AL		 166static inline int is_invalid_opcode(u32 intr_info)
167{
168 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
169 INTR_INFO_VALID_MASK)) ==
170 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
171}
172
6aa8b732
AK		 173static inline int is_external_interrupt(u32 intr_info)
174{
175 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
176 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
177}
178
6e5d865c
YS		 179static inline int cpu_has_vmx_tpr_shadow(void)
180{
181 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
182}
183
184static inline int vm_need_tpr_shadow(struct kvm *kvm)
185{
186 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
187}
188
f78e0e2e
SY		 189static inline int cpu_has_secondary_exec_ctrls(void)
190{
191 return (vmcs_config.cpu_based_exec_ctrl &
192 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
193}
194
774ead3a 195static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e
SY		 196{
197 return (vmcs_config.cpu_based_2nd_exec_ctrl &
198 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
199}
200
201static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
202{
203 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
204 (irqchip_in_kernel(kvm)));
205}
206
8b9cf98c 207static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 208{
209 int i;
210
a2fa3e9f
GH		 211 for (i = 0; i < vmx->nmsrs; ++i)
212 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 213 return i;
214 return -1;
215}
216
8b9cf98c 217static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 218{
219 int i;
220
8b9cf98c 221 i = __find_msr_index(vmx, msr);
a75beee6 222 if (i >= 0)
a2fa3e9f 223 return &vmx->guest_msrs[i];
8b6d44c7 224 return NULL;
7725f0ba
AK		 225}
226
6aa8b732
AK		 227static void vmcs_clear(struct vmcs *vmcs)
228{
229 u64 phys_addr = __pa(vmcs);
230 u8 error;
231
232 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
233 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
234 : "cc", "memory");
235 if (error)
236 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
237 vmcs, phys_addr);
238}
239
240static void __vcpu_clear(void *arg)
241{
8b9cf98c 242 struct vcpu_vmx *vmx = arg;
d3b2c338 243 int cpu = raw_smp_processor_id();
6aa8b732 244
8b9cf98c 245 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 246 vmcs_clear(vmx->vmcs);
247 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 248 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 249 rdtscll(vmx->vcpu.arch.host_tsc);
6aa8b732
AK		 250}
251
8b9cf98c 252static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 253{
eae5ecb5
AK		 254 if (vmx->vcpu.cpu == -1)
255 return;
f566e09f 256 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
8b9cf98c 257 vmx->launched = 0;
8d0be2b3
AK		 258}
259
6aa8b732
AK		 260static unsigned long vmcs_readl(unsigned long field)
261{
262 unsigned long value;
263
264 asm volatile (ASM_VMX_VMREAD_RDX_RAX
265 : "=a"(value) : "d"(field) : "cc");
266 return value;
267}
268
269static u16 vmcs_read16(unsigned long field)
270{
271 return vmcs_readl(field);
272}
273
274static u32 vmcs_read32(unsigned long field)
275{
276 return vmcs_readl(field);
277}
278
279static u64 vmcs_read64(unsigned long field)
280{
05b3e0c2 281#ifdef CONFIG_X86_64
6aa8b732
AK		 282 return vmcs_readl(field);
283#else
284 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
285#endif
286}
287
e52de1b8
AK		 288static noinline void vmwrite_error(unsigned long field, unsigned long value)
289{
290 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
291 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
292 dump_stack();
293}
294
6aa8b732
AK		 295static void vmcs_writel(unsigned long field, unsigned long value)
296{
297 u8 error;
298
299 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
d77c26fc 300 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 301 if (unlikely(error))
302 vmwrite_error(field, value);
6aa8b732
AK		 303}
304
305static void vmcs_write16(unsigned long field, u16 value)
306{
307 vmcs_writel(field, value);
308}
309
310static void vmcs_write32(unsigned long field, u32 value)
311{
312 vmcs_writel(field, value);
313}
314
315static void vmcs_write64(unsigned long field, u64 value)
316{
05b3e0c2 317#ifdef CONFIG_X86_64
6aa8b732
AK		 318 vmcs_writel(field, value);
319#else
320 vmcs_writel(field, value);
321 asm volatile ("");
322 vmcs_writel(field+1, value >> 32);
323#endif
324}
325
2ab455cc
AL		 326static void vmcs_clear_bits(unsigned long field, u32 mask)
327{
328 vmcs_writel(field, vmcs_readl(field) & ~mask);
329}
330
331static void vmcs_set_bits(unsigned long field, u32 mask)
332{
333 vmcs_writel(field, vmcs_readl(field) | mask);
334}
335
abd3f2d6
AK		 336static void update_exception_bitmap(struct kvm_vcpu *vcpu)
337{
338 u32 eb;
339
7aa81cc0 340 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 341 if (!vcpu->fpu_active)
342 eb |= 1u << NM_VECTOR;
343 if (vcpu->guest_debug.enabled)
344 eb |= 1u << 1;
ad312c7c 345 if (vcpu->arch.rmode.active)
abd3f2d6
AK		 346 eb = ~0;
347 vmcs_write32(EXCEPTION_BITMAP, eb);
348}
349
33ed6329
AK		 350static void reload_tss(void)
351{
33ed6329
AK		 352 /*
353 * VT restores TR but not its size. Useless.
354 */
355 struct descriptor_table gdt;
356 struct segment_descriptor *descs;
357
358 get_gdt(&gdt);
359 descs = (void *)gdt.base;
360 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
361 load_TR_desc();
33ed6329
AK		 362}
363
8b9cf98c 364static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 365{
a2fa3e9f 366 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 367 u64 host_efer = vmx->host_msrs[efer_offset].data;
368 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
369 u64 ignore_bits;
370
371 if (efer_offset < 0)
372 return;
373 /*
374 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
375 * outside long mode
376 */
377 ignore_bits = EFER_NX | EFER_SCE;
378#ifdef CONFIG_X86_64
379 ignore_bits |= EFER_LMA | EFER_LME;
380 /* SCE is meaningful only in long mode on Intel */
381 if (guest_efer & EFER_LMA)
382 ignore_bits &= ~(u64)EFER_SCE;
383#endif
384 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
385 return;
2cc51560 386
51c6cf66
AK		 387 vmx->host_state.guest_efer_loaded = 1;
388 guest_efer &= ~ignore_bits;
389 guest_efer |= host_efer & ignore_bits;
390 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 391 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 392}
393
51c6cf66
AK		 394static void reload_host_efer(struct vcpu_vmx *vmx)
395{
396 if (vmx->host_state.guest_efer_loaded) {
397 vmx->host_state.guest_efer_loaded = 0;
398 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
399 }
400}
401
04d2cc77 402static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 403{
04d2cc77
AK		 404 struct vcpu_vmx *vmx = to_vmx(vcpu);
405
a2fa3e9f 406 if (vmx->host_state.loaded)
33ed6329
AK		 407 return;
408
a2fa3e9f 409 vmx->host_state.loaded = 1;
33ed6329
AK		 410 /*
411 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
412 * allow segment selectors with cpl > 0 or ti == 1.
413 */
a2fa3e9f 414 vmx->host_state.ldt_sel = read_ldt();
152d3f2f 415 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
a2fa3e9f 416 vmx->host_state.fs_sel = read_fs();
152d3f2f 417 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 418 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 419 vmx->host_state.fs_reload_needed = 0;
420 } else {
33ed6329 421 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 422 vmx->host_state.fs_reload_needed = 1;
33ed6329 423 }
a2fa3e9f
GH		 424 vmx->host_state.gs_sel = read_gs();
425 if (!(vmx->host_state.gs_sel & 7))
426 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 427 else {
428 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 429 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 430 }
431
432#ifdef CONFIG_X86_64
433 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
434 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
435#else
a2fa3e9f
GH		 436 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
437 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 438#endif
707c0874
AK		 439
440#ifdef CONFIG_X86_64
d77c26fc 441 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 442 save_msrs(vmx->host_msrs +
443 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 444
707c0874 445#endif
a2fa3e9f 446 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 447 load_transition_efer(vmx);
33ed6329
AK		 448}
449
8b9cf98c 450static void vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 451{
15ad7146 452 unsigned long flags;
33ed6329 453
a2fa3e9f 454 if (!vmx->host_state.loaded)
33ed6329
AK		 455 return;
456
e1beb1d3 457 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 458 vmx->host_state.loaded = 0;
152d3f2f 459 if (vmx->host_state.fs_reload_needed)
a2fa3e9f 460 load_fs(vmx->host_state.fs_sel);
152d3f2f
LV		 461 if (vmx->host_state.gs_ldt_reload_needed) {
462 load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 463 /*
464 * If we have to reload gs, we must take care to
465 * preserve our gs base.
466 */
15ad7146 467 local_irq_save(flags);
a2fa3e9f 468 load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 469#ifdef CONFIG_X86_64
470 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
471#endif
15ad7146 472 local_irq_restore(flags);
33ed6329 473 }
152d3f2f 474 reload_tss();
a2fa3e9f
GH		 475 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
476 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 477 reload_host_efer(vmx);
33ed6329
AK		 478}
479
6aa8b732
AK		 480/*
481 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
482 * vcpu mutex is already taken.
483 */
15ad7146 484static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 485{
a2fa3e9f
GH		 486 struct vcpu_vmx *vmx = to_vmx(vcpu);
487 u64 phys_addr = __pa(vmx->vmcs);
7700270e 488 u64 tsc_this, delta;
6aa8b732 489
a3d7f85f 490 if (vcpu->cpu != cpu) {
8b9cf98c 491 vcpu_clear(vmx);
a3d7f85f
ED		 492 kvm_migrate_apic_timer(vcpu);
493 }
6aa8b732 494
a2fa3e9f 495 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 496 u8 error;
497
a2fa3e9f 498 per_cpu(current_vmcs, cpu) = vmx->vmcs;
6aa8b732
AK		 499 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
500 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
501 : "cc");
502 if (error)
503 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 504 vmx->vmcs, phys_addr);
6aa8b732
AK		 505 }
506
507 if (vcpu->cpu != cpu) {
508 struct descriptor_table dt;
509 unsigned long sysenter_esp;
510
511 vcpu->cpu = cpu;
512 /*
513 * Linux uses per-cpu TSS and GDT, so set these when switching
514 * processors.
515 */
516 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
517 get_gdt(&dt);
518 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
519
520 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
521 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 522
523 /*
524 * Make sure the time stamp counter is monotonous.
525 */
526 rdtscll(tsc_this);
ad312c7c 527 delta = vcpu->arch.host_tsc - tsc_this;
7700270e 528 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
6aa8b732 529 }
6aa8b732
AK		 530}
531
532static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
533{
8b9cf98c 534 vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 535}
536
5fd86fcf
AK		 537static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
538{
539 if (vcpu->fpu_active)
540 return;
541 vcpu->fpu_active = 1;
707d92fa 542 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 543 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 544 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 545 update_exception_bitmap(vcpu);
546}
547
548static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
549{
550 if (!vcpu->fpu_active)
551 return;
552 vcpu->fpu_active = 0;
707d92fa 553 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 554 update_exception_bitmap(vcpu);
555}
556
774c47f1
AK		 557static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
558{
8b9cf98c 559 vcpu_clear(to_vmx(vcpu));
774c47f1
AK		 560}
561
6aa8b732
AK		 562static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
563{
564 return vmcs_readl(GUEST_RFLAGS);
565}
566
567static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
568{
ad312c7c 569 if (vcpu->arch.rmode.active)
053de044 570 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 571 vmcs_writel(GUEST_RFLAGS, rflags);
572}
573
574static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
575{
576 unsigned long rip;
577 u32 interruptibility;
578
579 rip = vmcs_readl(GUEST_RIP);
580 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
581 vmcs_writel(GUEST_RIP, rip);
582
583 /*
584 * We emulated an instruction, so temporary interrupt blocking
585 * should be removed, if set.
586 */
587 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
588 if (interruptibility & 3)
589 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
590 interruptibility & ~3);
ad312c7c 591 vcpu->arch.interrupt_window_open = 1;
6aa8b732
AK		 592}
593
298101da
AK		 594static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
595 bool has_error_code, u32 error_code)
596{
597 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
598 nr | INTR_TYPE_EXCEPTION
599 | (has_error_code ? INTR_INFO_DELIEVER_CODE_MASK : 0)
600 | INTR_INFO_VALID_MASK);
601 if (has_error_code)
602 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
603}
604
605static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
606{
607 struct vcpu_vmx *vmx = to_vmx(vcpu);
608
609 return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
610}
611
a75beee6
ED		 612/*
613 * Swap MSR entry in host/guest MSR entry array.
614 */
54e11fa1 615#ifdef CONFIG_X86_64
8b9cf98c 616static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 617{
a2fa3e9f
GH		 618 struct kvm_msr_entry tmp;
619
620 tmp = vmx->guest_msrs[to];
621 vmx->guest_msrs[to] = vmx->guest_msrs[from];
622 vmx->guest_msrs[from] = tmp;
623 tmp = vmx->host_msrs[to];
624 vmx->host_msrs[to] = vmx->host_msrs[from];
625 vmx->host_msrs[from] = tmp;
a75beee6 626}
54e11fa1 627#endif
a75beee6 628
e38aea3e
AK		 629/*
630 * Set up the vmcs to automatically save and restore system
631 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
632 * mode, as fiddling with msrs is very expensive.
633 */
8b9cf98c 634static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 635{
2cc51560 636 int save_nmsrs;
e38aea3e 637
33f9c505 638 vmx_load_host_state(vmx);
a75beee6
ED		 639 save_nmsrs = 0;
640#ifdef CONFIG_X86_64
8b9cf98c 641 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 642 int index;
643
8b9cf98c 644 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 645 if (index >= 0)
8b9cf98c
RR		 646 move_msr_up(vmx, index, save_nmsrs++);
647 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 648 if (index >= 0)
8b9cf98c
RR		 649 move_msr_up(vmx, index, save_nmsrs++);
650 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 651 if (index >= 0)
8b9cf98c
RR		 652 move_msr_up(vmx, index, save_nmsrs++);
653 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 654 if (index >= 0)
8b9cf98c 655 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 656 /*
657 * MSR_K6_STAR is only needed on long mode guests, and only
658 * if efer.sce is enabled.
659 */
8b9cf98c 660 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 661 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 662 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 663 }
664#endif
a2fa3e9f 665 vmx->save_nmsrs = save_nmsrs;
e38aea3e 666
4d56c8a7 667#ifdef CONFIG_X86_64
a2fa3e9f 668 vmx->msr_offset_kernel_gs_base =
8b9cf98c 669 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 670#endif
8b9cf98c 671 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 672}
673
6aa8b732
AK		 674/*
675 * reads and returns guest's timestamp counter "register"
676 * guest_tsc = host_tsc + tsc_offset -- 21.3
677 */
678static u64 guest_read_tsc(void)
679{
680 u64 host_tsc, tsc_offset;
681
682 rdtscll(host_tsc);
683 tsc_offset = vmcs_read64(TSC_OFFSET);
684 return host_tsc + tsc_offset;
685}
686
687/*
688 * writes 'guest_tsc' into guest's timestamp counter "register"
689 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
690 */
691static void guest_write_tsc(u64 guest_tsc)
692{
693 u64 host_tsc;
694
695 rdtscll(host_tsc);
696 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
697}
698
6aa8b732
AK		 699/*
700 * Reads an msr value (of 'msr_index') into 'pdata'.
701 * Returns 0 on success, non-0 otherwise.
702 * Assumes vcpu_load() was already called.
703 */
704static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
705{
706 u64 data;
a2fa3e9f 707 struct kvm_msr_entry *msr;
6aa8b732
AK		 708
709 if (!pdata) {
710 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
711 return -EINVAL;
712 }
713
714 switch (msr_index) {
05b3e0c2 715#ifdef CONFIG_X86_64
6aa8b732
AK		 716 case MSR_FS_BASE:
717 data = vmcs_readl(GUEST_FS_BASE);
718 break;
719 case MSR_GS_BASE:
720 data = vmcs_readl(GUEST_GS_BASE);
721 break;
722 case MSR_EFER:
3bab1f5d 723 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 724#endif
725 case MSR_IA32_TIME_STAMP_COUNTER:
726 data = guest_read_tsc();
727 break;
728 case MSR_IA32_SYSENTER_CS:
729 data = vmcs_read32(GUEST_SYSENTER_CS);
730 break;
731 case MSR_IA32_SYSENTER_EIP:
f5b42c33 732 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 733 break;
734 case MSR_IA32_SYSENTER_ESP:
f5b42c33 735 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 736 break;
6aa8b732 737 default:
8b9cf98c 738 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 739 if (msr) {
740 data = msr->data;
741 break;
6aa8b732 742 }
3bab1f5d 743 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 744 }
745
746 *pdata = data;
747 return 0;
748}
749
750/*
751 * Writes msr value into into the appropriate "register".
752 * Returns 0 on success, non-0 otherwise.
753 * Assumes vcpu_load() was already called.
754 */
755static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
756{
a2fa3e9f
GH		 757 struct vcpu_vmx *vmx = to_vmx(vcpu);
758 struct kvm_msr_entry *msr;
2cc51560
ED		 759 int ret = 0;
760
6aa8b732 761 switch (msr_index) {
05b3e0c2 762#ifdef CONFIG_X86_64
3bab1f5d 763 case MSR_EFER:
2cc51560 764 ret = kvm_set_msr_common(vcpu, msr_index, data);
51c6cf66
AK		 765 if (vmx->host_state.loaded) {
766 reload_host_efer(vmx);
8b9cf98c 767 load_transition_efer(vmx);
51c6cf66 768 }
2cc51560 769 break;
6aa8b732
AK		 770 case MSR_FS_BASE:
771 vmcs_writel(GUEST_FS_BASE, data);
772 break;
773 case MSR_GS_BASE:
774 vmcs_writel(GUEST_GS_BASE, data);
775 break;
776#endif
777 case MSR_IA32_SYSENTER_CS:
778 vmcs_write32(GUEST_SYSENTER_CS, data);
779 break;
780 case MSR_IA32_SYSENTER_EIP:
f5b42c33 781 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 782 break;
783 case MSR_IA32_SYSENTER_ESP:
f5b42c33 784 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 785 break;
d27d4aca 786 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 787 guest_write_tsc(data);
788 break;
6aa8b732 789 default:
8b9cf98c 790 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 791 if (msr) {
792 msr->data = data;
a2fa3e9f
GH		 793 if (vmx->host_state.loaded)
794 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
3bab1f5d 795 break;
6aa8b732 796 }
2cc51560 797 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 798 }
799
2cc51560 800 return ret;
6aa8b732
AK		 801}
802
803/*
804 * Sync the rsp and rip registers into the vcpu structure. This allows
ad312c7c 805 * registers to be accessed by indexing vcpu->arch.regs.
6aa8b732
AK		 806 */
807static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
808{
ad312c7c
ZX		 809 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
810 vcpu->arch.rip = vmcs_readl(GUEST_RIP);
6aa8b732
AK		 811}
812
813/*
814 * Syncs rsp and rip back into the vmcs. Should be called after possible
815 * modification.
816 */
817static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
818{
ad312c7c
ZX		 819 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
820 vmcs_writel(GUEST_RIP, vcpu->arch.rip);
6aa8b732
AK		 821}
822
823static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
824{
825 unsigned long dr7 = 0x400;
6aa8b732
AK		 826 int old_singlestep;
827
6aa8b732
AK		 828 old_singlestep = vcpu->guest_debug.singlestep;
829
830 vcpu->guest_debug.enabled = dbg->enabled;
831 if (vcpu->guest_debug.enabled) {
832 int i;
833
834 dr7 |= 0x200; /* exact */
835 for (i = 0; i < 4; ++i) {
836 if (!dbg->breakpoints[i].enabled)
837 continue;
838 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
839 dr7 |= 2 << (i*2); /* global enable */
840 dr7 |= 0 << (i*4+16); /* execution breakpoint */
841 }
842
6aa8b732 843 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 844 } else
6aa8b732 845 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 846
847 if (old_singlestep && !vcpu->guest_debug.singlestep) {
848 unsigned long flags;
849
850 flags = vmcs_readl(GUEST_RFLAGS);
851 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
852 vmcs_writel(GUEST_RFLAGS, flags);
853 }
854
abd3f2d6 855 update_exception_bitmap(vcpu);
6aa8b732
AK		 856 vmcs_writel(GUEST_DR7, dr7);
857
858 return 0;
859}
860
2a8067f1
ED		 861static int vmx_get_irq(struct kvm_vcpu *vcpu)
862{
1155f76a 863 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a8067f1
ED		 864 u32 idtv_info_field;
865
1155f76a 866 idtv_info_field = vmx->idt_vectoring_info;
2a8067f1
ED		 867 if (idtv_info_field & INTR_INFO_VALID_MASK) {
868 if (is_external_interrupt(idtv_info_field))
869 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
870 else
d77c26fc 871 printk(KERN_DEBUG "pending exception: not handled yet\n");
2a8067f1
ED		 872 }
873 return -1;
874}
875
6aa8b732
AK		 876static __init int cpu_has_kvm_support(void)
877{
878 unsigned long ecx = cpuid_ecx(1);
879 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
880}
881
882static __init int vmx_disabled_by_bios(void)
883{
884 u64 msr;
885
886 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
62b3ffb8
YS		 887 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
888 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
889 == MSR_IA32_FEATURE_CONTROL_LOCKED;
890 /* locked but not enabled */
6aa8b732
AK		 891}
892
774c47f1 893static void hardware_enable(void *garbage)
6aa8b732
AK		 894{
895 int cpu = raw_smp_processor_id();
896 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
897 u64 old;
898
899 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
62b3ffb8
YS		 900 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
901 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
902 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
903 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 904 /* enable and lock */
62b3ffb8
YS		 905 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
906 MSR_IA32_FEATURE_CONTROL_LOCKED |
907 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 908 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
6aa8b732
AK		 909 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
910 : "memory", "cc");
911}
912
913static void hardware_disable(void *garbage)
914{
915 asm volatile (ASM_VMX_VMXOFF : : : "cc");
916}
917
1c3d14fe 918static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 919 u32 msr, u32 *result)
1c3d14fe
YS		 920{
921 u32 vmx_msr_low, vmx_msr_high;
922 u32 ctl = ctl_min | ctl_opt;
923
924 rdmsr(msr, vmx_msr_low, vmx_msr_high);
925
926 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
927 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
928
929 /* Ensure minimum (required) set of control bits are supported. */
930 if (ctl_min & ~ctl)
002c7f7c 931 return -EIO;
1c3d14fe
YS		 932
933 *result = ctl;
934 return 0;
935}
936
002c7f7c 937static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 938{
939 u32 vmx_msr_low, vmx_msr_high;
1c3d14fe
YS		 940 u32 min, opt;
941 u32 _pin_based_exec_control = 0;
942 u32 _cpu_based_exec_control = 0;
f78e0e2e 943 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 944 u32 _vmexit_control = 0;
945 u32 _vmentry_control = 0;
946
947 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
948 opt = 0;
949 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
950 &_pin_based_exec_control) < 0)
002c7f7c 951 return -EIO;
1c3d14fe
YS		 952
953 min = CPU_BASED_HLT_EXITING |
954#ifdef CONFIG_X86_64
955 CPU_BASED_CR8_LOAD_EXITING |
956 CPU_BASED_CR8_STORE_EXITING |
957#endif
958 CPU_BASED_USE_IO_BITMAPS |
959 CPU_BASED_MOV_DR_EXITING |
960 CPU_BASED_USE_TSC_OFFSETING;
f78e0e2e
SY		 961 opt = CPU_BASED_TPR_SHADOW |
962 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 963 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
964 &_cpu_based_exec_control) < 0)
002c7f7c 965 return -EIO;
6e5d865c
YS		 966#ifdef CONFIG_X86_64
967 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
968 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
969 ~CPU_BASED_CR8_STORE_EXITING;
970#endif
f78e0e2e
SY		 971 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
972 min = 0;
e5edaa01
ED		 973 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
974 SECONDARY_EXEC_WBINVD_EXITING;
f78e0e2e
SY		 975 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
976 &_cpu_based_2nd_exec_control) < 0)
977 return -EIO;
978 }
979#ifndef CONFIG_X86_64
980 if (!(_cpu_based_2nd_exec_control &
981 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
982 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
983#endif
1c3d14fe
YS		 984
985 min = 0;
986#ifdef CONFIG_X86_64
987 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
988#endif
989 opt = 0;
990 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
991 &_vmexit_control) < 0)
002c7f7c 992 return -EIO;
1c3d14fe
YS		 993
994 min = opt = 0;
995 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
996 &_vmentry_control) < 0)
002c7f7c 997 return -EIO;
6aa8b732 998
c68876fd 999 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1000
1001 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1002 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1003 return -EIO;
1c3d14fe
YS		 1004
1005#ifdef CONFIG_X86_64
1006 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1007 if (vmx_msr_high & (1u<<16))
002c7f7c 1008 return -EIO;
1c3d14fe
YS		 1009#endif
1010
1011 /* Require Write-Back (WB) memory type for VMCS accesses. */
1012 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1013 return -EIO;
1c3d14fe 1014
002c7f7c
YS		 1015 vmcs_conf->size = vmx_msr_high & 0x1fff;
1016 vmcs_conf->order = get_order(vmcs_config.size);
1017 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1018
002c7f7c
YS		 1019 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1020 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1021 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1022 vmcs_conf->vmexit_ctrl = _vmexit_control;
1023 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1024
1025 return 0;
c68876fd 1026}
6aa8b732
AK		 1027
1028static struct vmcs *alloc_vmcs_cpu(int cpu)
1029{
1030 int node = cpu_to_node(cpu);
1031 struct page *pages;
1032 struct vmcs *vmcs;
1033
1c3d14fe 1034 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1035 if (!pages)
1036 return NULL;
1037 vmcs = page_address(pages);
1c3d14fe
YS		 1038 memset(vmcs, 0, vmcs_config.size);
1039 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1040 return vmcs;
1041}
1042
1043static struct vmcs *alloc_vmcs(void)
1044{
d3b2c338 1045 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1046}
1047
1048static void free_vmcs(struct vmcs *vmcs)
1049{
1c3d14fe 1050 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1051}
1052
39959588 1053static void free_kvm_area(void)
6aa8b732
AK		 1054{
1055 int cpu;
1056
1057 for_each_online_cpu(cpu)
1058 free_vmcs(per_cpu(vmxarea, cpu));
1059}
1060
6aa8b732
AK		 1061static __init int alloc_kvm_area(void)
1062{
1063 int cpu;
1064
1065 for_each_online_cpu(cpu) {
1066 struct vmcs *vmcs;
1067
1068 vmcs = alloc_vmcs_cpu(cpu);
1069 if (!vmcs) {
1070 free_kvm_area();
1071 return -ENOMEM;
1072 }
1073
1074 per_cpu(vmxarea, cpu) = vmcs;
1075 }
1076 return 0;
1077}
1078
1079static __init int hardware_setup(void)
1080{
002c7f7c
YS		 1081 if (setup_vmcs_config(&vmcs_config) < 0)
1082 return -EIO;
6aa8b732
AK		 1083 return alloc_kvm_area();
1084}
1085
1086static __exit void hardware_unsetup(void)
1087{
1088 free_kvm_area();
1089}
1090
6aa8b732
AK		 1091static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1092{
1093 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1094
6af11b9e 1095 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1096 vmcs_write16(sf->selector, save->selector);
1097 vmcs_writel(sf->base, save->base);
1098 vmcs_write32(sf->limit, save->limit);
1099 vmcs_write32(sf->ar_bytes, save->ar);
1100 } else {
1101 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1102 << AR_DPL_SHIFT;
1103 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1104 }
1105}
1106
1107static void enter_pmode(struct kvm_vcpu *vcpu)
1108{
1109 unsigned long flags;
1110
ad312c7c 1111 vcpu->arch.rmode.active = 0;
6aa8b732 1112
ad312c7c
ZX		 1113 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1114 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1115 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
6aa8b732
AK		 1116
1117 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1118 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
ad312c7c 1119 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1120 vmcs_writel(GUEST_RFLAGS, flags);
1121
66aee91a
RR		 1122 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1123 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1124
1125 update_exception_bitmap(vcpu);
1126
ad312c7c
ZX		 1127 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1128 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1129 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1130 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
6aa8b732
AK		 1131
1132 vmcs_write16(GUEST_SS_SELECTOR, 0);
1133 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1134
1135 vmcs_write16(GUEST_CS_SELECTOR,
1136 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1137 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1138}
1139
d77c26fc 1140static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1141{
bfc6d222 1142 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1143 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1144 kvm->memslots[0].npages - 3;
1145 return base_gfn << PAGE_SHIFT;
1146 }
bfc6d222 1147 return kvm->arch.tss_addr;
6aa8b732
AK		 1148}
1149
1150static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1151{
1152 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1153
1154 save->selector = vmcs_read16(sf->selector);
1155 save->base = vmcs_readl(sf->base);
1156 save->limit = vmcs_read32(sf->limit);
1157 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1158 vmcs_write16(sf->selector, save->base >> 4);
1159 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1160 vmcs_write32(sf->limit, 0xffff);
1161 vmcs_write32(sf->ar_bytes, 0xf3);
1162}
1163
1164static void enter_rmode(struct kvm_vcpu *vcpu)
1165{
1166 unsigned long flags;
1167
ad312c7c 1168 vcpu->arch.rmode.active = 1;
6aa8b732 1169
ad312c7c 1170 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1171 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1172
ad312c7c 1173 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1174 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1175
ad312c7c 1176 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1177 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1178
1179 flags = vmcs_readl(GUEST_RFLAGS);
ad312c7c
ZX		 1180 vcpu->arch.rmode.save_iopl
1181 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1182
053de044 1183 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1184
1185 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1186 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1187 update_exception_bitmap(vcpu);
1188
1189 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1190 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1191 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1192
1193 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1194 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1195 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1196 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1197 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1198
ad312c7c
ZX		 1199 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1200 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1201 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1202 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
75880a01 1203
8668a3c4 1204 kvm_mmu_reset_context(vcpu);
75880a01 1205 init_rmode_tss(vcpu->kvm);
6aa8b732
AK		 1206}
1207
05b3e0c2 1208#ifdef CONFIG_X86_64
6aa8b732
AK		 1209
1210static void enter_lmode(struct kvm_vcpu *vcpu)
1211{
1212 u32 guest_tr_ar;
1213
1214 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1215 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1216 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1217 __FUNCTION__);
1218 vmcs_write32(GUEST_TR_AR_BYTES,
1219 (guest_tr_ar & ~AR_TYPE_MASK)
1220 | AR_TYPE_BUSY_64_TSS);
1221 }
1222
ad312c7c 1223 vcpu->arch.shadow_efer |= EFER_LMA;
6aa8b732 1224
8b9cf98c 1225 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1226 vmcs_write32(VM_ENTRY_CONTROLS,
1227 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1228 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1229}
1230
1231static void exit_lmode(struct kvm_vcpu *vcpu)
1232{
ad312c7c 1233 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1234
1235 vmcs_write32(VM_ENTRY_CONTROLS,
1236 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1237 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1238}
1239
1240#endif
1241
25c4c276 1242static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1243{
ad312c7c
ZX		 1244 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1245 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1246}
1247
6aa8b732
AK		 1248static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1249{
5fd86fcf
AK		 1250 vmx_fpu_deactivate(vcpu);
1251
ad312c7c 1252 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1253 enter_pmode(vcpu);
1254
ad312c7c 1255 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1256 enter_rmode(vcpu);
1257
05b3e0c2 1258#ifdef CONFIG_X86_64
ad312c7c 1259 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1260 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1261 enter_lmode(vcpu);
707d92fa 1262 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1263 exit_lmode(vcpu);
1264 }
1265#endif
1266
1267 vmcs_writel(CR0_READ_SHADOW, cr0);
1268 vmcs_writel(GUEST_CR0,
1269 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
ad312c7c 1270 vcpu->arch.cr0 = cr0;
5fd86fcf 1271
707d92fa 1272 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1273 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1274}
1275
6aa8b732
AK		 1276static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1277{
1278 vmcs_writel(GUEST_CR3, cr3);
ad312c7c 1279 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1280 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1281}
1282
1283static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1284{
1285 vmcs_writel(CR4_READ_SHADOW, cr4);
ad312c7c 1286 vmcs_writel(GUEST_CR4, cr4 | (vcpu->arch.rmode.active ?
6aa8b732 1287 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
ad312c7c 1288 vcpu->arch.cr4 = cr4;
6aa8b732
AK		 1289}
1290
05b3e0c2 1291#ifdef CONFIG_X86_64
6aa8b732
AK		 1292
1293static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1294{
8b9cf98c
RR		 1295 struct vcpu_vmx *vmx = to_vmx(vcpu);
1296 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732 1297
ad312c7c 1298 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 1299 if (efer & EFER_LMA) {
1300 vmcs_write32(VM_ENTRY_CONTROLS,
1301 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1302 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1303 msr->data = efer;
1304
1305 } else {
1306 vmcs_write32(VM_ENTRY_CONTROLS,
1307 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1308 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1309
1310 msr->data = efer & ~EFER_LME;
1311 }
8b9cf98c 1312 setup_msrs(vmx);
6aa8b732
AK		 1313}
1314
1315#endif
1316
1317static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1318{
1319 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1320
1321 return vmcs_readl(sf->base);
1322}
1323
1324static void vmx_get_segment(struct kvm_vcpu *vcpu,
1325 struct kvm_segment *var, int seg)
1326{
1327 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1328 u32 ar;
1329
1330 var->base = vmcs_readl(sf->base);
1331 var->limit = vmcs_read32(sf->limit);
1332 var->selector = vmcs_read16(sf->selector);
1333 ar = vmcs_read32(sf->ar_bytes);
1334 if (ar & AR_UNUSABLE_MASK)
1335 ar = 0;
1336 var->type = ar & 15;
1337 var->s = (ar >> 4) & 1;
1338 var->dpl = (ar >> 5) & 3;
1339 var->present = (ar >> 7) & 1;
1340 var->avl = (ar >> 12) & 1;
1341 var->l = (ar >> 13) & 1;
1342 var->db = (ar >> 14) & 1;
1343 var->g = (ar >> 15) & 1;
1344 var->unusable = (ar >> 16) & 1;
1345}
1346
653e3108 1347static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1348{
6aa8b732
AK		 1349 u32 ar;
1350
653e3108 1351 if (var->unusable)
6aa8b732
AK		 1352 ar = 1 << 16;
1353 else {
1354 ar = var->type & 15;
1355 ar |= (var->s & 1) << 4;
1356 ar |= (var->dpl & 3) << 5;
1357 ar |= (var->present & 1) << 7;
1358 ar |= (var->avl & 1) << 12;
1359 ar |= (var->l & 1) << 13;
1360 ar |= (var->db & 1) << 14;
1361 ar |= (var->g & 1) << 15;
1362 }
f7fbf1fd
UL		 1363 if (ar == 0) /* a 0 value means unusable */
1364 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1365
1366 return ar;
1367}
1368
1369static void vmx_set_segment(struct kvm_vcpu *vcpu,
1370 struct kvm_segment *var, int seg)
1371{
1372 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1373 u32 ar;
1374
ad312c7c
ZX		 1375 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1376 vcpu->arch.rmode.tr.selector = var->selector;
1377 vcpu->arch.rmode.tr.base = var->base;
1378 vcpu->arch.rmode.tr.limit = var->limit;
1379 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1380 return;
1381 }
1382 vmcs_writel(sf->base, var->base);
1383 vmcs_write32(sf->limit, var->limit);
1384 vmcs_write16(sf->selector, var->selector);
ad312c7c 1385 if (vcpu->arch.rmode.active && var->s) {
653e3108
AK		 1386 /*
1387 * Hack real-mode segments into vm86 compatibility.
1388 */
1389 if (var->base == 0xffff0000 && var->selector == 0xf000)
1390 vmcs_writel(sf->base, 0xf0000);
1391 ar = 0xf3;
1392 } else
1393 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1394 vmcs_write32(sf->ar_bytes, ar);
1395}
1396
6aa8b732
AK		 1397static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1398{
1399 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1400
1401 *db = (ar >> 14) & 1;
1402 *l = (ar >> 13) & 1;
1403}
1404
1405static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1406{
1407 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1408 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1409}
1410
1411static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1412{
1413 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1414 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1415}
1416
1417static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1418{
1419 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1420 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1421}
1422
1423static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1424{
1425 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1426 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1427}
1428
d77c26fc 1429static int init_rmode_tss(struct kvm *kvm)
6aa8b732 1430{
6aa8b732 1431 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 1432 u16 data = 0;
10589a46 1433 int ret = 0;
195aefde 1434 int r;
6aa8b732 1435
707a18a5 1436 down_read(&kvm->slots_lock);
195aefde
IE		 1437 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1438 if (r < 0)
10589a46 1439 goto out;
195aefde
IE		 1440 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1441 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1442 if (r < 0)
10589a46 1443 goto out;
195aefde
IE		 1444 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1445 if (r < 0)
10589a46 1446 goto out;
195aefde
IE		 1447 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1448 if (r < 0)
10589a46 1449 goto out;
195aefde 1450 data = ~0;
10589a46
MT		 1451 r = kvm_write_guest_page(kvm, fn, &data,
1452 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1453 sizeof(u8));
195aefde 1454 if (r < 0)
10589a46
MT		 1455 goto out;
1456
1457 ret = 1;
1458out:
707a18a5 1459 up_read(&kvm->slots_lock);
10589a46 1460 return ret;
6aa8b732
AK		 1461}
1462
6aa8b732
AK		 1463static void seg_setup(int seg)
1464{
1465 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1466
1467 vmcs_write16(sf->selector, 0);
1468 vmcs_writel(sf->base, 0);
1469 vmcs_write32(sf->limit, 0xffff);
1470 vmcs_write32(sf->ar_bytes, 0x93);
1471}
1472
f78e0e2e
SY		 1473static int alloc_apic_access_page(struct kvm *kvm)
1474{
1475 struct kvm_userspace_memory_region kvm_userspace_mem;
1476 int r = 0;
1477
72dc67a6 1478 down_write(&kvm->slots_lock);
bfc6d222 1479 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 1480 goto out;
1481 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1482 kvm_userspace_mem.flags = 0;
1483 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1484 kvm_userspace_mem.memory_size = PAGE_SIZE;
1485 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1486 if (r)
1487 goto out;
72dc67a6
IE		 1488
1489 down_read(&current->mm->mmap_sem);
bfc6d222 1490 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
72dc67a6 1491 up_read(&current->mm->mmap_sem);
f78e0e2e 1492out:
72dc67a6 1493 up_write(&kvm->slots_lock);
f78e0e2e
SY		 1494 return r;
1495}
1496
6aa8b732
AK		 1497/*
1498 * Sets up the vmcs for emulated real mode.
1499 */
8b9cf98c 1500static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732
AK		 1501{
1502 u32 host_sysenter_cs;
1503 u32 junk;
1504 unsigned long a;
1505 struct descriptor_table dt;
1506 int i;
cd2276a7 1507 unsigned long kvm_vmx_return;
6e5d865c 1508 u32 exec_control;
6aa8b732 1509
6aa8b732 1510 /* I/O */
fdef3ad1
HQ		 1511 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1512 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732 1513
6aa8b732
AK		 1514 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1515
6aa8b732 1516 /* Control */
1c3d14fe
YS		 1517 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1518 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 1519
1520 exec_control = vmcs_config.cpu_based_exec_ctrl;
1521 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1522 exec_control &= ~CPU_BASED_TPR_SHADOW;
1523#ifdef CONFIG_X86_64
1524 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1525 CPU_BASED_CR8_LOAD_EXITING;
1526#endif
1527 }
1528 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 1529
83ff3b9d
SY		 1530 if (cpu_has_secondary_exec_ctrls()) {
1531 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1532 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1533 exec_control &=
1534 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1535 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1536 }
f78e0e2e 1537
c7addb90
AK		 1538 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1539 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 1540 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1541
1542 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1543 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1544 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1545
1546 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1547 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1548 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1549 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1550 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1551 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1552#ifdef CONFIG_X86_64
6aa8b732
AK		 1553 rdmsrl(MSR_FS_BASE, a);
1554 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1555 rdmsrl(MSR_GS_BASE, a);
1556 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1557#else
1558 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1559 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1560#endif
1561
1562 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1563
1564 get_idt(&dt);
1565 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1566
d77c26fc 1567 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 1568 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 1569 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1570 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1571 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 1572
1573 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1574 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1575 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1576 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1577 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1578 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1579
6aa8b732
AK		 1580 for (i = 0; i < NR_VMX_MSR; ++i) {
1581 u32 index = vmx_msr_index[i];
1582 u32 data_low, data_high;
1583 u64 data;
a2fa3e9f 1584 int j = vmx->nmsrs;
6aa8b732
AK		 1585
1586 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1587 continue;
432bd6cb
AK		 1588 if (wrmsr_safe(index, data_low, data_high) < 0)
1589 continue;
6aa8b732 1590 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 1591 vmx->host_msrs[j].index = index;
1592 vmx->host_msrs[j].reserved = 0;
1593 vmx->host_msrs[j].data = data;
1594 vmx->guest_msrs[j] = vmx->host_msrs[j];
1595 ++vmx->nmsrs;
6aa8b732 1596 }
6aa8b732 1597
1c3d14fe 1598 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 1599
1600 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 1601 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1602
e00c8cf2
AK		 1603 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1604 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1605
f78e0e2e 1606
e00c8cf2
AK		 1607 return 0;
1608}
1609
1610static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1611{
1612 struct vcpu_vmx *vmx = to_vmx(vcpu);
1613 u64 msr;
1614 int ret;
1615
1616 if (!init_rmode_tss(vmx->vcpu.kvm)) {
1617 ret = -ENOMEM;
1618 goto out;
1619 }
1620
ad312c7c 1621 vmx->vcpu.arch.rmode.active = 0;
e00c8cf2 1622
ad312c7c 1623 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
e00c8cf2
AK		 1624 set_cr8(&vmx->vcpu, 0);
1625 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1626 if (vmx->vcpu.vcpu_id == 0)
1627 msr |= MSR_IA32_APICBASE_BSP;
1628 kvm_set_apic_base(&vmx->vcpu, msr);
1629
1630 fx_init(&vmx->vcpu);
1631
1632 /*
1633 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1634 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1635 */
1636 if (vmx->vcpu.vcpu_id == 0) {
1637 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1638 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1639 } else {
ad312c7c
ZX		 1640 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
1641 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2
AK		 1642 }
1643 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1644 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1645
1646 seg_setup(VCPU_SREG_DS);
1647 seg_setup(VCPU_SREG_ES);
1648 seg_setup(VCPU_SREG_FS);
1649 seg_setup(VCPU_SREG_GS);
1650 seg_setup(VCPU_SREG_SS);
1651
1652 vmcs_write16(GUEST_TR_SELECTOR, 0);
1653 vmcs_writel(GUEST_TR_BASE, 0);
1654 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1655 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1656
1657 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1658 vmcs_writel(GUEST_LDTR_BASE, 0);
1659 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1660 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1661
1662 vmcs_write32(GUEST_SYSENTER_CS, 0);
1663 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1664 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1665
1666 vmcs_writel(GUEST_RFLAGS, 0x02);
1667 if (vmx->vcpu.vcpu_id == 0)
1668 vmcs_writel(GUEST_RIP, 0xfff0);
1669 else
1670 vmcs_writel(GUEST_RIP, 0);
1671 vmcs_writel(GUEST_RSP, 0);
1672
1673 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1674 vmcs_writel(GUEST_DR7, 0x400);
1675
1676 vmcs_writel(GUEST_GDTR_BASE, 0);
1677 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1678
1679 vmcs_writel(GUEST_IDTR_BASE, 0);
1680 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1681
1682 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1683 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1684 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1685
1686 guest_write_tsc(0);
1687
1688 /* Special registers */
1689 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1690
1691 setup_msrs(vmx);
1692
6aa8b732
AK		 1693 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1694
f78e0e2e
SY		 1695 if (cpu_has_vmx_tpr_shadow()) {
1696 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1697 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1698 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 1699 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 1700 vmcs_write32(TPR_THRESHOLD, 0);
1701 }
1702
1703 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1704 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 1705 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 1706
ad312c7c
ZX		 1707 vmx->vcpu.arch.cr0 = 0x60000010;
1708 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 1709 vmx_set_cr4(&vmx->vcpu, 0);
05b3e0c2 1710#ifdef CONFIG_X86_64
8b9cf98c 1711 vmx_set_efer(&vmx->vcpu, 0);
6aa8b732 1712#endif
8b9cf98c
RR		 1713 vmx_fpu_activate(&vmx->vcpu);
1714 update_exception_bitmap(&vmx->vcpu);
6aa8b732
AK		 1715
1716 return 0;
1717
6aa8b732
AK		 1718out:
1719 return ret;
1720}
1721
85f455f7
ED		 1722static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1723{
9c8cba37
AK		 1724 struct vcpu_vmx *vmx = to_vmx(vcpu);
1725
ad312c7c 1726 if (vcpu->arch.rmode.active) {
9c8cba37
AK		 1727 vmx->rmode.irq.pending = true;
1728 vmx->rmode.irq.vector = irq;
1729 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
9c5623e3
AK		 1730 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1731 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1732 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
9c8cba37 1733 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
85f455f7
ED		 1734 return;
1735 }
1736 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1737 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1738}
1739
6aa8b732
AK		 1740static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1741{
ad312c7c
ZX		 1742 int word_index = __ffs(vcpu->arch.irq_summary);
1743 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
6aa8b732
AK		 1744 int irq = word_index * BITS_PER_LONG + bit_index;
1745
ad312c7c
ZX		 1746 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1747 if (!vcpu->arch.irq_pending[word_index])
1748 clear_bit(word_index, &vcpu->arch.irq_summary);
85f455f7 1749 vmx_inject_irq(vcpu, irq);
6aa8b732
AK		 1750}
1751
c1150d8c
DL		 1752
1753static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1754 struct kvm_run *kvm_run)
6aa8b732 1755{
c1150d8c
DL		 1756 u32 cpu_based_vm_exec_control;
1757
ad312c7c 1758 vcpu->arch.interrupt_window_open =
c1150d8c
DL		 1759 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1760 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1761
ad312c7c
ZX		 1762 if (vcpu->arch.interrupt_window_open &&
1763 vcpu->arch.irq_summary &&
c1150d8c 1764 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 1765 /*
c1150d8c 1766 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 1767 */
1768 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 1769
1770 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
ad312c7c
ZX		 1771 if (!vcpu->arch.interrupt_window_open &&
1772 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 1773 /*
1774 * Interrupts blocked. Wait for unblock.
1775 */
c1150d8c
DL		 1776 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1777 else
1778 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1779 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 1780}
1781
cbc94022
IE		 1782static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1783{
1784 int ret;
1785 struct kvm_userspace_memory_region tss_mem = {
1786 .slot = 8,
1787 .guest_phys_addr = addr,
1788 .memory_size = PAGE_SIZE * 3,
1789 .flags = 0,
1790 };
1791
1792 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1793 if (ret)
1794 return ret;
bfc6d222 1795 kvm->arch.tss_addr = addr;
cbc94022
IE		 1796 return 0;
1797}
1798
6aa8b732
AK		 1799static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1800{
1801 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1802
1803 set_debugreg(dbg->bp[0], 0);
1804 set_debugreg(dbg->bp[1], 1);
1805 set_debugreg(dbg->bp[2], 2);
1806 set_debugreg(dbg->bp[3], 3);
1807
1808 if (dbg->singlestep) {
1809 unsigned long flags;
1810
1811 flags = vmcs_readl(GUEST_RFLAGS);
1812 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1813 vmcs_writel(GUEST_RFLAGS, flags);
1814 }
1815}
1816
1817static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1818 int vec, u32 err_code)
1819{
ad312c7c 1820 if (!vcpu->arch.rmode.active)
6aa8b732
AK		 1821 return 0;
1822
b3f37707
NK		 1823 /*
1824 * Instruction with address size override prefix opcode 0x67
1825 * Cause the #SS fault with 0 error code in VM86 mode.
1826 */
1827 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 1828 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732
AK		 1829 return 1;
1830 return 0;
1831}
1832
1833static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1834{
1155f76a 1835 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 1836 u32 intr_info, error_code;
1837 unsigned long cr2, rip;
1838 u32 vect_info;
1839 enum emulation_result er;
1840
1155f76a 1841 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 1842 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1843
1844 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 1845 !is_page_fault(intr_info))
6aa8b732
AK		 1846 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1847 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
6aa8b732 1848
85f455f7 1849 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732 1850 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
ad312c7c
ZX		 1851 set_bit(irq, vcpu->arch.irq_pending);
1852 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
6aa8b732
AK		 1853 }
1854
1b6269db
AK		 1855 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1856 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 1857
1858 if (is_no_device(intr_info)) {
5fd86fcf 1859 vmx_fpu_activate(vcpu);
2ab455cc
AL		 1860 return 1;
1861 }
1862
7aa81cc0 1863 if (is_invalid_opcode(intr_info)) {
571008da 1864 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1865 if (er != EMULATE_DONE)
7ee5d940 1866 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 1867 return 1;
1868 }
1869
6aa8b732
AK		 1870 error_code = 0;
1871 rip = vmcs_readl(GUEST_RIP);
1872 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1873 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1874 if (is_page_fault(intr_info)) {
1875 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3067714c 1876 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 1877 }
1878
ad312c7c 1879 if (vcpu->arch.rmode.active &&
6aa8b732 1880 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 1881 error_code)) {
ad312c7c
ZX		 1882 if (vcpu->arch.halt_request) {
1883 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 1884 return kvm_emulate_halt(vcpu);
1885 }
6aa8b732 1886 return 1;
72d6e5a0 1887 }
6aa8b732 1888
d77c26fc
MD		 1889 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1890 (INTR_TYPE_EXCEPTION | 1)) {
6aa8b732
AK		 1891 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1892 return 0;
1893 }
1894 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1895 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1896 kvm_run->ex.error_code = error_code;
1897 return 0;
1898}
1899
1900static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1901 struct kvm_run *kvm_run)
1902{
1165f5fe 1903 ++vcpu->stat.irq_exits;
6aa8b732
AK		 1904 return 1;
1905}
1906
988ad74f
AK		 1907static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1908{
1909 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1910 return 0;
1911}
6aa8b732 1912
6aa8b732
AK		 1913static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1914{
bfdaab09 1915 unsigned long exit_qualification;
039576c0
AK		 1916 int size, down, in, string, rep;
1917 unsigned port;
6aa8b732 1918
1165f5fe 1919 ++vcpu->stat.io_exits;
bfdaab09 1920 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 1921 string = (exit_qualification & 16) != 0;
e70669ab
LV		 1922
1923 if (string) {
3427318f
LV		 1924 if (emulate_instruction(vcpu,
1925 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1926 return 0;
1927 return 1;
1928 }
1929
1930 size = (exit_qualification & 7) + 1;
1931 in = (exit_qualification & 8) != 0;
039576c0 1932 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 1933 rep = (exit_qualification & 32) != 0;
1934 port = exit_qualification >> 16;
e70669ab 1935
3090dd73 1936 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1937}
1938
102d8325
IM		 1939static void
1940vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1941{
1942 /*
1943 * Patch in the VMCALL instruction:
1944 */
1945 hypercall[0] = 0x0f;
1946 hypercall[1] = 0x01;
1947 hypercall[2] = 0xc1;
102d8325
IM		 1948}
1949
6aa8b732
AK		 1950static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1951{
bfdaab09 1952 unsigned long exit_qualification;
6aa8b732
AK		 1953 int cr;
1954 int reg;
1955
bfdaab09 1956 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 1957 cr = exit_qualification & 15;
1958 reg = (exit_qualification >> 8) & 15;
1959 switch ((exit_qualification >> 4) & 3) {
1960 case 0: /* mov to cr */
1961 switch (cr) {
1962 case 0:
1963 vcpu_load_rsp_rip(vcpu);
ad312c7c 1964 set_cr0(vcpu, vcpu->arch.regs[reg]);
6aa8b732
AK		 1965 skip_emulated_instruction(vcpu);
1966 return 1;
1967 case 3:
1968 vcpu_load_rsp_rip(vcpu);
ad312c7c 1969 set_cr3(vcpu, vcpu->arch.regs[reg]);
6aa8b732
AK		 1970 skip_emulated_instruction(vcpu);
1971 return 1;
1972 case 4:
1973 vcpu_load_rsp_rip(vcpu);
ad312c7c 1974 set_cr4(vcpu, vcpu->arch.regs[reg]);
6aa8b732
AK		 1975 skip_emulated_instruction(vcpu);
1976 return 1;
1977 case 8:
1978 vcpu_load_rsp_rip(vcpu);
ad312c7c 1979 set_cr8(vcpu, vcpu->arch.regs[reg]);
6aa8b732 1980 skip_emulated_instruction(vcpu);
e5314067
AK		 1981 if (irqchip_in_kernel(vcpu->kvm))
1982 return 1;
253abdee
YS		 1983 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1984 return 0;
6aa8b732
AK		 1985 };
1986 break;
25c4c276
AL		 1987 case 2: /* clts */
1988 vcpu_load_rsp_rip(vcpu);
5fd86fcf 1989 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 1990 vcpu->arch.cr0 &= ~X86_CR0_TS;
1991 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 1992 vmx_fpu_activate(vcpu);
25c4c276
AL		 1993 skip_emulated_instruction(vcpu);
1994 return 1;
6aa8b732
AK		 1995 case 1: /*mov from cr*/
1996 switch (cr) {
1997 case 3:
1998 vcpu_load_rsp_rip(vcpu);
ad312c7c 1999 vcpu->arch.regs[reg] = vcpu->arch.cr3;
6aa8b732
AK		 2000 vcpu_put_rsp_rip(vcpu);
2001 skip_emulated_instruction(vcpu);
2002 return 1;
2003 case 8:
6aa8b732 2004 vcpu_load_rsp_rip(vcpu);
ad312c7c 2005 vcpu->arch.regs[reg] = get_cr8(vcpu);
6aa8b732
AK		 2006 vcpu_put_rsp_rip(vcpu);
2007 skip_emulated_instruction(vcpu);
2008 return 1;
2009 }
2010 break;
2011 case 3: /* lmsw */
2012 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2013
2014 skip_emulated_instruction(vcpu);
2015 return 1;
2016 default:
2017 break;
2018 }
2019 kvm_run->exit_reason = 0;
f0242478 2020 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2021 (int)(exit_qualification >> 4) & 3, cr);
2022 return 0;
2023}
2024
2025static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2026{
bfdaab09 2027 unsigned long exit_qualification;
6aa8b732
AK		 2028 unsigned long val;
2029 int dr, reg;
2030
2031 /*
2032 * FIXME: this code assumes the host is debugging the guest.
2033 * need to deal with guest debugging itself too.
2034 */
bfdaab09 2035 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2036 dr = exit_qualification & 7;
2037 reg = (exit_qualification >> 8) & 15;
2038 vcpu_load_rsp_rip(vcpu);
2039 if (exit_qualification & 16) {
2040 /* mov from dr */
2041 switch (dr) {
2042 case 6:
2043 val = 0xffff0ff0;
2044 break;
2045 case 7:
2046 val = 0x400;
2047 break;
2048 default:
2049 val = 0;
2050 }
ad312c7c 2051 vcpu->arch.regs[reg] = val;
6aa8b732
AK		 2052 } else {
2053 /* mov to dr */
2054 }
2055 vcpu_put_rsp_rip(vcpu);
2056 skip_emulated_instruction(vcpu);
2057 return 1;
2058}
2059
2060static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2061{
06465c5a
AK		 2062 kvm_emulate_cpuid(vcpu);
2063 return 1;
6aa8b732
AK		 2064}
2065
2066static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2067{
ad312c7c 2068 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2069 u64 data;
2070
2071 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 2072 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2073 return 1;
2074 }
2075
2076 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 2077 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2078 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 2079 skip_emulated_instruction(vcpu);
2080 return 1;
2081}
2082
2083static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2084{
ad312c7c
ZX		 2085 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2086 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2087 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 2088
2089 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 2090 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2091 return 1;
2092 }
2093
2094 skip_emulated_instruction(vcpu);
2095 return 1;
2096}
2097
6e5d865c
YS		 2098static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2099 struct kvm_run *kvm_run)
2100{
2101 return 1;
2102}
2103
6aa8b732
AK		 2104static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2105 struct kvm_run *kvm_run)
2106{
85f455f7
ED		 2107 u32 cpu_based_vm_exec_control;
2108
2109 /* clear pending irq */
2110 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2111 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2112 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
c1150d8c
DL		 2113 /*
2114 * If the user space waits to inject interrupts, exit as soon as
2115 * possible
2116 */
2117 if (kvm_run->request_interrupt_window &&
ad312c7c 2118 !vcpu->arch.irq_summary) {
c1150d8c 2119 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 2120 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 2121 return 0;
2122 }
6aa8b732
AK		 2123 return 1;
2124}
2125
2126static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2127{
2128 skip_emulated_instruction(vcpu);
d3bef15f 2129 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2130}
2131
c21415e8
IM		 2132static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2133{
510043da 2134 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2135 kvm_emulate_hypercall(vcpu);
2136 return 1;
c21415e8
IM		 2137}
2138
e5edaa01
ED		 2139static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2140{
2141 skip_emulated_instruction(vcpu);
2142 /* TODO: Add support for VT-d/pass-through device */
2143 return 1;
2144}
2145
f78e0e2e
SY		 2146static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2147{
2148 u64 exit_qualification;
2149 enum emulation_result er;
2150 unsigned long offset;
2151
2152 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2153 offset = exit_qualification & 0xffful;
2154
2155 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2156
2157 if (er != EMULATE_DONE) {
2158 printk(KERN_ERR
2159 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2160 offset);
2161 return -ENOTSUPP;
2162 }
2163 return 1;
2164}
2165
6aa8b732
AK		 2166/*
2167 * The exit handlers return 1 if the exit was handled fully and guest execution
2168 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2169 * to be done to userspace and return 0.
2170 */
2171static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2172 struct kvm_run *kvm_run) = {
2173 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2174 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 2175 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 2176 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 2177 [EXIT_REASON_CR_ACCESS] = handle_cr,
2178 [EXIT_REASON_DR_ACCESS] = handle_dr,
2179 [EXIT_REASON_CPUID] = handle_cpuid,
2180 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2181 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2182 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2183 [EXIT_REASON_HLT] = handle_halt,
c21415e8 2184 [EXIT_REASON_VMCALL] = handle_vmcall,
f78e0e2e
SY		 2185 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
2186 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 2187 [EXIT_REASON_WBINVD] = handle_wbinvd,
6aa8b732
AK		 2188};
2189
2190static const int kvm_vmx_max_exit_handlers =
50a3485c 2191 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 2192
2193/*
2194 * The guest has exited. See if we can fix it or if we need userspace
2195 * assistance.
2196 */
2197static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2198{
6aa8b732 2199 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78 2200 struct vcpu_vmx *vmx = to_vmx(vcpu);
1155f76a 2201 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78
AK		 2202
2203 if (unlikely(vmx->fail)) {
2204 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2205 kvm_run->fail_entry.hardware_entry_failure_reason
2206 = vmcs_read32(VM_INSTRUCTION_ERROR);
2207 return 0;
2208 }
6aa8b732 2209
d77c26fc
MD		 2210 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2211 exit_reason != EXIT_REASON_EXCEPTION_NMI)
6aa8b732
AK		 2212 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2213 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
6aa8b732
AK		 2214 if (exit_reason < kvm_vmx_max_exit_handlers
2215 && kvm_vmx_exit_handlers[exit_reason])
2216 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2217 else {
2218 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2219 kvm_run->hw.hardware_exit_reason = exit_reason;
2220 }
2221 return 0;
2222}
2223
d9e368d6
AK		 2224static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2225{
d9e368d6
AK		 2226}
2227
6e5d865c
YS		 2228static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2229{
2230 int max_irr, tpr;
2231
2232 if (!vm_need_tpr_shadow(vcpu->kvm))
2233 return;
2234
2235 if (!kvm_lapic_enabled(vcpu) ||
2236 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2237 vmcs_write32(TPR_THRESHOLD, 0);
2238 return;
2239 }
2240
2241 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2242 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2243}
2244
85f455f7
ED		 2245static void enable_irq_window(struct kvm_vcpu *vcpu)
2246{
2247 u32 cpu_based_vm_exec_control;
2248
2249 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2250 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2251 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2252}
2253
2254static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2255{
1155f76a 2256 struct vcpu_vmx *vmx = to_vmx(vcpu);
85f455f7
ED		 2257 u32 idtv_info_field, intr_info_field;
2258 int has_ext_irq, interrupt_window_open;
1b9778da 2259 int vector;
85f455f7 2260
6e5d865c
YS		 2261 update_tpr_threshold(vcpu);
2262
85f455f7
ED		 2263 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2264 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
1155f76a 2265 idtv_info_field = vmx->idt_vectoring_info;
85f455f7
ED		 2266 if (intr_info_field & INTR_INFO_VALID_MASK) {
2267 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2268 /* TODO: fault when IDT_Vectoring */
9584bf2c
RH		 2269 if (printk_ratelimit())
2270 printk(KERN_ERR "Fault when IDT_Vectoring\n");
85f455f7
ED		 2271 }
2272 if (has_ext_irq)
2273 enable_irq_window(vcpu);
2274 return;
2275 }
2276 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
9c8cba37
AK		 2277 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2278 == INTR_TYPE_EXT_INTR
ad312c7c 2279 && vcpu->arch.rmode.active) {
9c8cba37
AK		 2280 u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2281
2282 vmx_inject_irq(vcpu, vect);
2283 if (unlikely(has_ext_irq))
2284 enable_irq_window(vcpu);
2285 return;
2286 }
2287
85f455f7
ED		 2288 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2289 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2290 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2291
2292 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2293 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2294 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2295 if (unlikely(has_ext_irq))
2296 enable_irq_window(vcpu);
2297 return;
2298 }
2299 if (!has_ext_irq)
2300 return;
2301 interrupt_window_open =
2302 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2303 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1b9778da
ED		 2304 if (interrupt_window_open) {
2305 vector = kvm_cpu_get_interrupt(vcpu);
2306 vmx_inject_irq(vcpu, vector);
2307 kvm_timer_intr_post(vcpu, vector);
2308 } else
85f455f7
ED		 2309 enable_irq_window(vcpu);
2310}
2311
9c8cba37
AK		 2312/*
2313 * Failure to inject an interrupt should give us the information
2314 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
2315 * when fetching the interrupt redirection bitmap in the real-mode
2316 * tss, this doesn't happen. So we do it ourselves.
2317 */
2318static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2319{
2320 vmx->rmode.irq.pending = 0;
2321 if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2322 return;
2323 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2324 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2325 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2326 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2327 return;
2328 }
2329 vmx->idt_vectoring_info =
2330 VECTORING_INFO_VALID_MASK
2331 | INTR_TYPE_EXT_INTR
2332 | vmx->rmode.irq.vector;
2333}
2334
04d2cc77 2335static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2336{
a2fa3e9f 2337 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 2338 u32 intr_info;
e6adf283
AK		 2339
2340 /*
2341 * Loading guest fpu may have cleared host cr0.ts
2342 */
2343 vmcs_writel(HOST_CR0, read_cr0());
2344
d77c26fc 2345 asm(
6aa8b732 2346 /* Store host registers */
05b3e0c2 2347#ifdef CONFIG_X86_64
c2036300 2348 "push %%rdx; push %%rbp;"
6aa8b732 2349 "push %%rcx \n\t"
6aa8b732 2350#else
ff593e5a
LV		 2351 "push %%edx; push %%ebp;"
2352 "push %%ecx \n\t"
6aa8b732 2353#endif
c2036300 2354 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
6aa8b732 2355 /* Check if vmlaunch of vmresume is needed */
e08aa78a 2356 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 2357 /* Load guest registers. Don't clobber flags. */
05b3e0c2 2358#ifdef CONFIG_X86_64
e08aa78a 2359 "mov %c[cr2](%0), %%rax \n\t"
6aa8b732 2360 "mov %%rax, %%cr2 \n\t"
e08aa78a
AK		 2361 "mov %c[rax](%0), %%rax \n\t"
2362 "mov %c[rbx](%0), %%rbx \n\t"
2363 "mov %c[rdx](%0), %%rdx \n\t"
2364 "mov %c[rsi](%0), %%rsi \n\t"
2365 "mov %c[rdi](%0), %%rdi \n\t"
2366 "mov %c[rbp](%0), %%rbp \n\t"
2367 "mov %c[r8](%0), %%r8 \n\t"
2368 "mov %c[r9](%0), %%r9 \n\t"
2369 "mov %c[r10](%0), %%r10 \n\t"
2370 "mov %c[r11](%0), %%r11 \n\t"
2371 "mov %c[r12](%0), %%r12 \n\t"
2372 "mov %c[r13](%0), %%r13 \n\t"
2373 "mov %c[r14](%0), %%r14 \n\t"
2374 "mov %c[r15](%0), %%r15 \n\t"
2375 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
6aa8b732 2376#else
e08aa78a 2377 "mov %c[cr2](%0), %%eax \n\t"
6aa8b732 2378 "mov %%eax, %%cr2 \n\t"
e08aa78a
AK		 2379 "mov %c[rax](%0), %%eax \n\t"
2380 "mov %c[rbx](%0), %%ebx \n\t"
2381 "mov %c[rdx](%0), %%edx \n\t"
2382 "mov %c[rsi](%0), %%esi \n\t"
2383 "mov %c[rdi](%0), %%edi \n\t"
2384 "mov %c[rbp](%0), %%ebp \n\t"
2385 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
6aa8b732
AK		 2386#endif
2387 /* Enter guest mode */
cd2276a7 2388 "jne .Llaunched \n\t"
6aa8b732 2389 ASM_VMX_VMLAUNCH "\n\t"
cd2276a7
AK		 2390 "jmp .Lkvm_vmx_return \n\t"
2391 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2392 ".Lkvm_vmx_return: "
6aa8b732 2393 /* Save guest registers, load host registers, keep flags */
05b3e0c2 2394#ifdef CONFIG_X86_64
e08aa78a
AK		 2395 "xchg %0, (%%rsp) \n\t"
2396 "mov %%rax, %c[rax](%0) \n\t"
2397 "mov %%rbx, %c[rbx](%0) \n\t"
2398 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2399 "mov %%rdx, %c[rdx](%0) \n\t"
2400 "mov %%rsi, %c[rsi](%0) \n\t"
2401 "mov %%rdi, %c[rdi](%0) \n\t"
2402 "mov %%rbp, %c[rbp](%0) \n\t"
2403 "mov %%r8, %c[r8](%0) \n\t"
2404 "mov %%r9, %c[r9](%0) \n\t"
2405 "mov %%r10, %c[r10](%0) \n\t"
2406 "mov %%r11, %c[r11](%0) \n\t"
2407 "mov %%r12, %c[r12](%0) \n\t"
2408 "mov %%r13, %c[r13](%0) \n\t"
2409 "mov %%r14, %c[r14](%0) \n\t"
2410 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 2411 "mov %%cr2, %%rax \n\t"
e08aa78a 2412 "mov %%rax, %c[cr2](%0) \n\t"
6aa8b732 2413
e08aa78a 2414 "pop %%rbp; pop %%rbp; pop %%rdx \n\t"
6aa8b732 2415#else
e08aa78a
AK		 2416 "xchg %0, (%%esp) \n\t"
2417 "mov %%eax, %c[rax](%0) \n\t"
2418 "mov %%ebx, %c[rbx](%0) \n\t"
2419 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2420 "mov %%edx, %c[rdx](%0) \n\t"
2421 "mov %%esi, %c[rsi](%0) \n\t"
2422 "mov %%edi, %c[rdi](%0) \n\t"
2423 "mov %%ebp, %c[rbp](%0) \n\t"
6aa8b732 2424 "mov %%cr2, %%eax \n\t"
e08aa78a 2425 "mov %%eax, %c[cr2](%0) \n\t"
6aa8b732 2426
e08aa78a 2427 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
6aa8b732 2428#endif
e08aa78a
AK		 2429 "setbe %c[fail](%0) \n\t"
2430 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2431 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2432 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
ad312c7c
ZX		 2433 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
2434 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
2435 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
2436 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
2437 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
2438 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
2439 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 2440#ifdef CONFIG_X86_64
ad312c7c
ZX		 2441 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
2442 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
2443 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
2444 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
2445 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
2446 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
2447 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
2448 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 2449#endif
ad312c7c 2450 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300
LV		 2451 : "cc", "memory"
2452#ifdef CONFIG_X86_64
2453 , "rbx", "rdi", "rsi"
2454 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
ff593e5a
LV		 2455#else
2456 , "ebx", "edi", "rsi"
c2036300
LV		 2457#endif
2458 );
6aa8b732 2459
1155f76a 2460 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 2461 if (vmx->rmode.irq.pending)
2462 fixup_rmode_irq(vmx);
1155f76a 2463
ad312c7c 2464 vcpu->arch.interrupt_window_open =
d77c26fc 2465 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2466
d77c26fc 2467 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 2468 vmx->launched = 1;
1b6269db
AK		 2469
2470 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2471
2472 /* We need to handle NMIs before interrupts are enabled */
2473 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2474 asm("int $2");
6aa8b732
AK		 2475}
2476
6aa8b732
AK		 2477static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2478{
a2fa3e9f
GH		 2479 struct vcpu_vmx *vmx = to_vmx(vcpu);
2480
2481 if (vmx->vmcs) {
8b9cf98c 2482 on_each_cpu(__vcpu_clear, vmx, 0, 1);
a2fa3e9f
GH		 2483 free_vmcs(vmx->vmcs);
2484 vmx->vmcs = NULL;
6aa8b732
AK		 2485 }
2486}
2487
2488static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2489{
fb3f0f51
RR		 2490 struct vcpu_vmx *vmx = to_vmx(vcpu);
2491
6aa8b732 2492 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 2493 kfree(vmx->host_msrs);
2494 kfree(vmx->guest_msrs);
2495 kvm_vcpu_uninit(vcpu);
a4770347 2496 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 2497}
2498
fb3f0f51 2499static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 2500{
fb3f0f51 2501 int err;
c16f862d 2502 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 2503 int cpu;
6aa8b732 2504
a2fa3e9f 2505 if (!vmx)
fb3f0f51
RR		 2506 return ERR_PTR(-ENOMEM);
2507
2508 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2509 if (err)
2510 goto free_vcpu;
965b58a5 2511
a2fa3e9f 2512 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 2513 if (!vmx->guest_msrs) {
2514 err = -ENOMEM;
2515 goto uninit_vcpu;
2516 }
965b58a5 2517
a2fa3e9f
GH		 2518 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2519 if (!vmx->host_msrs)
fb3f0f51 2520 goto free_guest_msrs;
965b58a5 2521
a2fa3e9f
GH		 2522 vmx->vmcs = alloc_vmcs();
2523 if (!vmx->vmcs)
fb3f0f51 2524 goto free_msrs;
a2fa3e9f
GH		 2525
2526 vmcs_clear(vmx->vmcs);
2527
15ad7146
AK		 2528 cpu = get_cpu();
2529 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 2530 err = vmx_vcpu_setup(vmx);
fb3f0f51 2531 vmx_vcpu_put(&vmx->vcpu);
15ad7146 2532 put_cpu();
fb3f0f51
RR		 2533 if (err)
2534 goto free_vmcs;
5e4a0b3c
MT		 2535 if (vm_need_virtualize_apic_accesses(kvm))
2536 if (alloc_apic_access_page(kvm) != 0)
2537 goto free_vmcs;
fb3f0f51
RR		 2538
2539 return &vmx->vcpu;
2540
2541free_vmcs:
2542 free_vmcs(vmx->vmcs);
2543free_msrs:
2544 kfree(vmx->host_msrs);
2545free_guest_msrs:
2546 kfree(vmx->guest_msrs);
2547uninit_vcpu:
2548 kvm_vcpu_uninit(&vmx->vcpu);
2549free_vcpu:
a4770347 2550 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 2551 return ERR_PTR(err);
6aa8b732
AK		 2552}
2553
002c7f7c
YS		 2554static void __init vmx_check_processor_compat(void *rtn)
2555{
2556 struct vmcs_config vmcs_conf;
2557
2558 *(int *)rtn = 0;
2559 if (setup_vmcs_config(&vmcs_conf) < 0)
2560 *(int *)rtn = -EIO;
2561 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2562 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2563 smp_processor_id());
2564 *(int *)rtn = -EIO;
2565 }
2566}
2567
cbdd1bea 2568static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 2569 .cpu_has_kvm_support = cpu_has_kvm_support,
2570 .disabled_by_bios = vmx_disabled_by_bios,
2571 .hardware_setup = hardware_setup,
2572 .hardware_unsetup = hardware_unsetup,
002c7f7c 2573 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 2574 .hardware_enable = hardware_enable,
2575 .hardware_disable = hardware_disable,
774ead3a 2576 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
6aa8b732
AK		 2577
2578 .vcpu_create = vmx_create_vcpu,
2579 .vcpu_free = vmx_free_vcpu,
04d2cc77 2580 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 2581
04d2cc77 2582 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 2583 .vcpu_load = vmx_vcpu_load,
2584 .vcpu_put = vmx_vcpu_put,
774c47f1 2585 .vcpu_decache = vmx_vcpu_decache,
6aa8b732
AK		 2586
2587 .set_guest_debug = set_guest_debug,
04d2cc77 2588 .guest_debug_pre = kvm_guest_debug_pre,
6aa8b732
AK		 2589 .get_msr = vmx_get_msr,
2590 .set_msr = vmx_set_msr,
2591 .get_segment_base = vmx_get_segment_base,
2592 .get_segment = vmx_get_segment,
2593 .set_segment = vmx_set_segment,
6aa8b732 2594 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 2595 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 2596 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 2597 .set_cr3 = vmx_set_cr3,
2598 .set_cr4 = vmx_set_cr4,
05b3e0c2 2599#ifdef CONFIG_X86_64
6aa8b732
AK		 2600 .set_efer = vmx_set_efer,
2601#endif
2602 .get_idt = vmx_get_idt,
2603 .set_idt = vmx_set_idt,
2604 .get_gdt = vmx_get_gdt,
2605 .set_gdt = vmx_set_gdt,
2606 .cache_regs = vcpu_load_rsp_rip,
2607 .decache_regs = vcpu_put_rsp_rip,
2608 .get_rflags = vmx_get_rflags,
2609 .set_rflags = vmx_set_rflags,
2610
2611 .tlb_flush = vmx_flush_tlb,
6aa8b732 2612
6aa8b732 2613 .run = vmx_vcpu_run,
04d2cc77 2614 .handle_exit = kvm_handle_exit,
6aa8b732 2615 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 2616 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 2617 .get_irq = vmx_get_irq,
2618 .set_irq = vmx_inject_irq,
298101da
AK		 2619 .queue_exception = vmx_queue_exception,
2620 .exception_injected = vmx_exception_injected,
04d2cc77
AK		 2621 .inject_pending_irq = vmx_intr_assist,
2622 .inject_pending_vectors = do_interrupt_requests,
cbc94022
IE		 2623
2624 .set_tss_addr = vmx_set_tss_addr,
6aa8b732
AK		 2625};
2626
2627static int __init vmx_init(void)
2628{
fdef3ad1
HQ		 2629 void *iova;
2630 int r;
2631
2632 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2633 if (!vmx_io_bitmap_a)
2634 return -ENOMEM;
2635
2636 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2637 if (!vmx_io_bitmap_b) {
2638 r = -ENOMEM;
2639 goto out;
2640 }
2641
2642 /*
2643 * Allow direct access to the PC debug port (it is often used for I/O
2644 * delays, but the vmexits simply slow things down).
2645 */
2646 iova = kmap(vmx_io_bitmap_a);
2647 memset(iova, 0xff, PAGE_SIZE);
2648 clear_bit(0x80, iova);
cd0536d7 2649 kunmap(vmx_io_bitmap_a);
fdef3ad1
HQ		 2650
2651 iova = kmap(vmx_io_bitmap_b);
2652 memset(iova, 0xff, PAGE_SIZE);
cd0536d7 2653 kunmap(vmx_io_bitmap_b);
fdef3ad1 2654
cb498ea2 2655 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1
HQ		 2656 if (r)
2657 goto out1;
2658
c7addb90
AK		 2659 if (bypass_guest_pf)
2660 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2661
fdef3ad1
HQ		 2662 return 0;
2663
2664out1:
2665 __free_page(vmx_io_bitmap_b);
2666out:
2667 __free_page(vmx_io_bitmap_a);
2668 return r;
6aa8b732
AK		 2669}
2670
2671static void __exit vmx_exit(void)
2672{
fdef3ad1
HQ		 2673 __free_page(vmx_io_bitmap_b);
2674 __free_page(vmx_io_bitmap_a);
2675
cb498ea2 2676 kvm_exit();
6aa8b732
AK		 2677}
2678
2679module_init(vmx_init)
2680module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)