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KVM: Move performance counter MSR access interception to generic x86 path
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
5fdbf976 28#include "kvm_cache_regs.h"
35920a35 29#include "x86.h"
e495606d 30
6aa8b732 31#include <asm/io.h>
3b3be0d1 32#include <asm/desc.h>
13673a90 33#include <asm/vmx.h>
6210e37b 34#include <asm/virtext.h>
a0861c02 35#include <asm/mce.h>
6aa8b732 36
4ecac3fd
AK		 37#define __ex(x) __kvm_handle_fault_on_reboot(x)
38
6aa8b732
AK		 39MODULE_AUTHOR("Qumranet");
40MODULE_LICENSE("GPL");
41
4462d21a 42static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 43module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 44
4462d21a 45static int __read_mostly enable_vpid = 1;
736caefe 46module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 47
4462d21a 48static int __read_mostly flexpriority_enabled = 1;
736caefe 49module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 50
4462d21a 51static int __read_mostly enable_ept = 1;
736caefe 52module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 53
3a624e29
NK		 54static int __read_mostly enable_unrestricted_guest = 1;
55module_param_named(unrestricted_guest,
56 enable_unrestricted_guest, bool, S_IRUGO);
57
4462d21a 58static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 59module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 60
a2fa3e9f
GH		 61struct vmcs {
62 u32 revision_id;
63 u32 abort;
64 char data[0];
65};
66
67struct vcpu_vmx {
fb3f0f51 68 struct kvm_vcpu vcpu;
543e4243 69 struct list_head local_vcpus_link;
313dbd49 70 unsigned long host_rsp;
a2fa3e9f 71 int launched;
29bd8a78 72 u8 fail;
1155f76a 73 u32 idt_vectoring_info;
a2fa3e9f
GH		 74 struct kvm_msr_entry *guest_msrs;
75 struct kvm_msr_entry *host_msrs;
76 int nmsrs;
77 int save_nmsrs;
78 int msr_offset_efer;
79#ifdef CONFIG_X86_64
80 int msr_offset_kernel_gs_base;
81#endif
82 struct vmcs *vmcs;
83 struct {
84 int loaded;
85 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 86 int gs_ldt_reload_needed;
87 int fs_reload_needed;
51c6cf66 88 int guest_efer_loaded;
d77c26fc 89 } host_state;
9c8cba37 90 struct {
7ffd92c5
AK		 91 int vm86_active;
92 u8 save_iopl;
93 struct kvm_save_segment {
94 u16 selector;
95 unsigned long base;
96 u32 limit;
97 u32 ar;
98 } tr, es, ds, fs, gs;
9c8cba37
AK		 99 struct {
100 bool pending;
101 u8 vector;
102 unsigned rip;
103 } irq;
104 } rmode;
2384d2b3 105 int vpid;
04fa4d32 106 bool emulation_required;
8b3079a5 107 enum emulation_result invalid_state_emulation_result;
3b86cd99
JK		 108
109 /* Support for vnmi-less CPUs */
110 int soft_vnmi_blocked;
111 ktime_t entry_time;
112 s64 vnmi_blocked_time;
a0861c02 113 u32 exit_reason;
a2fa3e9f
GH		 114};
115
116static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
117{
fb3f0f51 118 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 119}
120
b7ebfb05 121static int init_rmode(struct kvm *kvm);
4e1096d2 122static u64 construct_eptp(unsigned long root_hpa);
75880a01 123
6aa8b732
AK		 124static DEFINE_PER_CPU(struct vmcs *, vmxarea);
125static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 126static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 127
3e7c73e9
AK		 128static unsigned long *vmx_io_bitmap_a;
129static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 130static unsigned long *vmx_msr_bitmap_legacy;
131static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 132
2384d2b3
SY		 133static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
134static DEFINE_SPINLOCK(vmx_vpid_lock);
135
1c3d14fe 136static struct vmcs_config {
6aa8b732
AK		 137 int size;
138 int order;
139 u32 revision_id;
1c3d14fe
YS		 140 u32 pin_based_exec_ctrl;
141 u32 cpu_based_exec_ctrl;
f78e0e2e 142 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 143 u32 vmexit_ctrl;
144 u32 vmentry_ctrl;
145} vmcs_config;
6aa8b732 146
efff9e53 147static struct vmx_capability {
d56f546d
SY		 148 u32 ept;
149 u32 vpid;
150} vmx_capability;
151
6aa8b732
AK		 152#define VMX_SEGMENT_FIELD(seg) \
153 [VCPU_SREG_##seg] = { \
154 .selector = GUEST_##seg##_SELECTOR, \
155 .base = GUEST_##seg##_BASE, \
156 .limit = GUEST_##seg##_LIMIT, \
157 .ar_bytes = GUEST_##seg##_AR_BYTES, \
158 }
159
160static struct kvm_vmx_segment_field {
161 unsigned selector;
162 unsigned base;
163 unsigned limit;
164 unsigned ar_bytes;
165} kvm_vmx_segment_fields[] = {
166 VMX_SEGMENT_FIELD(CS),
167 VMX_SEGMENT_FIELD(DS),
168 VMX_SEGMENT_FIELD(ES),
169 VMX_SEGMENT_FIELD(FS),
170 VMX_SEGMENT_FIELD(GS),
171 VMX_SEGMENT_FIELD(SS),
172 VMX_SEGMENT_FIELD(TR),
173 VMX_SEGMENT_FIELD(LDTR),
174};
175
6de4f3ad
AK		 176static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
177
4d56c8a7
AK		 178/*
179 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
180 * away by decrementing the array size.
181 */
6aa8b732 182static const u32 vmx_msr_index[] = {
05b3e0c2 183#ifdef CONFIG_X86_64
6aa8b732
AK		 184 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
185#endif
186 MSR_EFER, MSR_K6_STAR,
187};
9d8f549d 188#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 189
a2fa3e9f
GH		 190static void load_msrs(struct kvm_msr_entry *e, int n)
191{
192 int i;
193
194 for (i = 0; i < n; ++i)
195 wrmsrl(e[i].index, e[i].data);
196}
197
198static void save_msrs(struct kvm_msr_entry *e, int n)
199{
200 int i;
201
202 for (i = 0; i < n; ++i)
203 rdmsrl(e[i].index, e[i].data);
204}
205
6aa8b732
AK		 206static inline int is_page_fault(u32 intr_info)
207{
208 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
209 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 210 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 211}
212
2ab455cc
AL		 213static inline int is_no_device(u32 intr_info)
214{
215 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
216 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 217 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 218}
219
7aa81cc0
AL		 220static inline int is_invalid_opcode(u32 intr_info)
221{
222 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
223 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 224 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 225}
226
6aa8b732
AK		 227static inline int is_external_interrupt(u32 intr_info)
228{
229 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
230 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
231}
232
a0861c02
AK		 233static inline int is_machine_check(u32 intr_info)
234{
235 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
236 INTR_INFO_VALID_MASK)) ==
237 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
238}
239
25c5f225
SY		 240static inline int cpu_has_vmx_msr_bitmap(void)
241{
04547156 242 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 243}
244
6e5d865c
YS		 245static inline int cpu_has_vmx_tpr_shadow(void)
246{
04547156 247 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 248}
249
250static inline int vm_need_tpr_shadow(struct kvm *kvm)
251{
04547156 252 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 253}
254
f78e0e2e
SY		 255static inline int cpu_has_secondary_exec_ctrls(void)
256{
04547156
SY		 257 return vmcs_config.cpu_based_exec_ctrl &
258 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 259}
260
774ead3a 261static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 262{
04547156
SY		 263 return vmcs_config.cpu_based_2nd_exec_ctrl &
264 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
265}
266
267static inline bool cpu_has_vmx_flexpriority(void)
268{
269 return cpu_has_vmx_tpr_shadow() &&
270 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 271}
272
d56f546d
SY		 273static inline int cpu_has_vmx_invept_individual_addr(void)
274{
04547156 275 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 276}
277
278static inline int cpu_has_vmx_invept_context(void)
279{
04547156 280 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 281}
282
283static inline int cpu_has_vmx_invept_global(void)
284{
04547156 285 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 286}
287
288static inline int cpu_has_vmx_ept(void)
289{
04547156
SY		 290 return vmcs_config.cpu_based_2nd_exec_ctrl &
291 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 292}
293
3a624e29
NK		 294static inline int cpu_has_vmx_unrestricted_guest(void)
295{
296 return vmcs_config.cpu_based_2nd_exec_ctrl &
297 SECONDARY_EXEC_UNRESTRICTED_GUEST;
298}
299
f78e0e2e
SY		 300static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
301{
04547156
SY		 302 return flexpriority_enabled &&
303 (cpu_has_vmx_virtualize_apic_accesses()) &&
304 (irqchip_in_kernel(kvm));
f78e0e2e
SY		 305}
306
2384d2b3
SY		 307static inline int cpu_has_vmx_vpid(void)
308{
04547156
SY		 309 return vmcs_config.cpu_based_2nd_exec_ctrl &
310 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 311}
312
f08864b4
SY		 313static inline int cpu_has_virtual_nmis(void)
314{
315 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
316}
317
04547156
SY		 318static inline bool report_flexpriority(void)
319{
320 return flexpriority_enabled;
321}
322
8b9cf98c 323static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 324{
325 int i;
326
a2fa3e9f
GH		 327 for (i = 0; i < vmx->nmsrs; ++i)
328 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 329 return i;
330 return -1;
331}
332
2384d2b3
SY		 333static inline void __invvpid(int ext, u16 vpid, gva_t gva)
334{
335 struct {
336 u64 vpid : 16;
337 u64 rsvd : 48;
338 u64 gva;
339 } operand = { vpid, 0, gva };
340
4ecac3fd 341 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 342 /* CF==1 or ZF==1 --> rc = -1 */
343 "; ja 1f ; ud2 ; 1:"
344 : : "a"(&operand), "c"(ext) : "cc", "memory");
345}
346
1439442c
SY		 347static inline void __invept(int ext, u64 eptp, gpa_t gpa)
348{
349 struct {
350 u64 eptp, gpa;
351 } operand = {eptp, gpa};
352
4ecac3fd 353 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 354 /* CF==1 or ZF==1 --> rc = -1 */
355 "; ja 1f ; ud2 ; 1:\n"
356 : : "a" (&operand), "c" (ext) : "cc", "memory");
357}
358
8b9cf98c 359static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 360{
361 int i;
362
8b9cf98c 363 i = __find_msr_index(vmx, msr);
a75beee6 364 if (i >= 0)
a2fa3e9f 365 return &vmx->guest_msrs[i];
8b6d44c7 366 return NULL;
7725f0ba
AK		 367}
368
6aa8b732
AK		 369static void vmcs_clear(struct vmcs *vmcs)
370{
371 u64 phys_addr = __pa(vmcs);
372 u8 error;
373
4ecac3fd 374 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 375 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
376 : "cc", "memory");
377 if (error)
378 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
379 vmcs, phys_addr);
380}
381
382static void __vcpu_clear(void *arg)
383{
8b9cf98c 384 struct vcpu_vmx *vmx = arg;
d3b2c338 385 int cpu = raw_smp_processor_id();
6aa8b732 386
8b9cf98c 387 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 388 vmcs_clear(vmx->vmcs);
389 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 390 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 391 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 392 list_del(&vmx->local_vcpus_link);
393 vmx->vcpu.cpu = -1;
394 vmx->launched = 0;
6aa8b732
AK		 395}
396
8b9cf98c 397static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 398{
eae5ecb5
AK		 399 if (vmx->vcpu.cpu == -1)
400 return;
8691e5a8 401 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 402}
403
2384d2b3
SY		 404static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
405{
406 if (vmx->vpid == 0)
407 return;
408
409 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
410}
411
1439442c
SY		 412static inline void ept_sync_global(void)
413{
414 if (cpu_has_vmx_invept_global())
415 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
416}
417
418static inline void ept_sync_context(u64 eptp)
419{
089d034e 420 if (enable_ept) {
1439442c
SY		 421 if (cpu_has_vmx_invept_context())
422 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
423 else
424 ept_sync_global();
425 }
426}
427
428static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
429{
089d034e 430 if (enable_ept) {
1439442c
SY		 431 if (cpu_has_vmx_invept_individual_addr())
432 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
433 eptp, gpa);
434 else
435 ept_sync_context(eptp);
436 }
437}
438
6aa8b732
AK		 439static unsigned long vmcs_readl(unsigned long field)
440{
441 unsigned long value;
442
4ecac3fd 443 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 444 : "=a"(value) : "d"(field) : "cc");
445 return value;
446}
447
448static u16 vmcs_read16(unsigned long field)
449{
450 return vmcs_readl(field);
451}
452
453static u32 vmcs_read32(unsigned long field)
454{
455 return vmcs_readl(field);
456}
457
458static u64 vmcs_read64(unsigned long field)
459{
05b3e0c2 460#ifdef CONFIG_X86_64
6aa8b732
AK		 461 return vmcs_readl(field);
462#else
463 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
464#endif
465}
466
e52de1b8
AK		 467static noinline void vmwrite_error(unsigned long field, unsigned long value)
468{
469 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
470 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
471 dump_stack();
472}
473
6aa8b732
AK		 474static void vmcs_writel(unsigned long field, unsigned long value)
475{
476 u8 error;
477
4ecac3fd 478 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 479 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 480 if (unlikely(error))
481 vmwrite_error(field, value);
6aa8b732
AK		 482}
483
484static void vmcs_write16(unsigned long field, u16 value)
485{
486 vmcs_writel(field, value);
487}
488
489static void vmcs_write32(unsigned long field, u32 value)
490{
491 vmcs_writel(field, value);
492}
493
494static void vmcs_write64(unsigned long field, u64 value)
495{
6aa8b732 496 vmcs_writel(field, value);
7682f2d0 497#ifndef CONFIG_X86_64
6aa8b732
AK		 498 asm volatile ("");
499 vmcs_writel(field+1, value >> 32);
500#endif
501}
502
2ab455cc
AL		 503static void vmcs_clear_bits(unsigned long field, u32 mask)
504{
505 vmcs_writel(field, vmcs_readl(field) & ~mask);
506}
507
508static void vmcs_set_bits(unsigned long field, u32 mask)
509{
510 vmcs_writel(field, vmcs_readl(field) | mask);
511}
512
abd3f2d6
AK		 513static void update_exception_bitmap(struct kvm_vcpu *vcpu)
514{
515 u32 eb;
516
a0861c02 517 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
abd3f2d6
AK		 518 if (!vcpu->fpu_active)
519 eb |= 1u << NM_VECTOR;
d0bfb940
JK		 520 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
521 if (vcpu->guest_debug &
522 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
523 eb |= 1u << DB_VECTOR;
524 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
525 eb |= 1u << BP_VECTOR;
526 }
7ffd92c5 527 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 528 eb = ~0;
089d034e 529 if (enable_ept)
1439442c 530 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 531 vmcs_write32(EXCEPTION_BITMAP, eb);
532}
533
33ed6329
AK		 534static void reload_tss(void)
535{
33ed6329
AK		 536 /*
537 * VT restores TR but not its size. Useless.
538 */
539 struct descriptor_table gdt;
a5f61300 540 struct desc_struct *descs;
33ed6329 541
d6e88aec 542 kvm_get_gdt(&gdt);
33ed6329
AK		 543 descs = (void *)gdt.base;
544 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
545 load_TR_desc();
33ed6329
AK		 546}
547
8b9cf98c 548static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 549{
a2fa3e9f 550 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 551 u64 host_efer = vmx->host_msrs[efer_offset].data;
552 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
553 u64 ignore_bits;
554
555 if (efer_offset < 0)
556 return;
557 /*
558 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
559 * outside long mode
560 */
561 ignore_bits = EFER_NX | EFER_SCE;
562#ifdef CONFIG_X86_64
563 ignore_bits |= EFER_LMA | EFER_LME;
564 /* SCE is meaningful only in long mode on Intel */
565 if (guest_efer & EFER_LMA)
566 ignore_bits &= ~(u64)EFER_SCE;
567#endif
568 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
569 return;
2cc51560 570
51c6cf66
AK		 571 vmx->host_state.guest_efer_loaded = 1;
572 guest_efer &= ~ignore_bits;
573 guest_efer |= host_efer & ignore_bits;
574 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 575 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 576}
577
51c6cf66
AK		 578static void reload_host_efer(struct vcpu_vmx *vmx)
579{
580 if (vmx->host_state.guest_efer_loaded) {
581 vmx->host_state.guest_efer_loaded = 0;
582 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
583 }
584}
585
04d2cc77 586static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 587{
04d2cc77
AK		 588 struct vcpu_vmx *vmx = to_vmx(vcpu);
589
a2fa3e9f 590 if (vmx->host_state.loaded)
33ed6329
AK		 591 return;
592
a2fa3e9f 593 vmx->host_state.loaded = 1;
33ed6329
AK		 594 /*
595 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
596 * allow segment selectors with cpl > 0 or ti == 1.
597 */
d6e88aec 598 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 599 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 600 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 601 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 602 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 603 vmx->host_state.fs_reload_needed = 0;
604 } else {
33ed6329 605 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 606 vmx->host_state.fs_reload_needed = 1;
33ed6329 607 }
d6e88aec 608 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 609 if (!(vmx->host_state.gs_sel & 7))
610 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 611 else {
612 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 613 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 614 }
615
616#ifdef CONFIG_X86_64
617 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
618 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
619#else
a2fa3e9f
GH		 620 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
621 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 622#endif
707c0874
AK		 623
624#ifdef CONFIG_X86_64
d77c26fc 625 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 626 save_msrs(vmx->host_msrs +
627 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 628
707c0874 629#endif
a2fa3e9f 630 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 631 load_transition_efer(vmx);
33ed6329
AK		 632}
633
a9b21b62 634static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 635{
15ad7146 636 unsigned long flags;
33ed6329 637
a2fa3e9f 638 if (!vmx->host_state.loaded)
33ed6329
AK		 639 return;
640
e1beb1d3 641 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 642 vmx->host_state.loaded = 0;
152d3f2f 643 if (vmx->host_state.fs_reload_needed)
d6e88aec 644 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 645 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 646 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 647 /*
648 * If we have to reload gs, we must take care to
649 * preserve our gs base.
650 */
15ad7146 651 local_irq_save(flags);
d6e88aec 652 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 653#ifdef CONFIG_X86_64
654 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
655#endif
15ad7146 656 local_irq_restore(flags);
33ed6329 657 }
152d3f2f 658 reload_tss();
a2fa3e9f
GH		 659 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
660 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 661 reload_host_efer(vmx);
33ed6329
AK		 662}
663
a9b21b62
AK		 664static void vmx_load_host_state(struct vcpu_vmx *vmx)
665{
666 preempt_disable();
667 __vmx_load_host_state(vmx);
668 preempt_enable();
669}
670
6aa8b732
AK		 671/*
672 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
673 * vcpu mutex is already taken.
674 */
15ad7146 675static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 676{
a2fa3e9f
GH		 677 struct vcpu_vmx *vmx = to_vmx(vcpu);
678 u64 phys_addr = __pa(vmx->vmcs);
019960ae 679 u64 tsc_this, delta, new_offset;
6aa8b732 680
a3d7f85f 681 if (vcpu->cpu != cpu) {
8b9cf98c 682 vcpu_clear(vmx);
2f599714 683 kvm_migrate_timers(vcpu);
2384d2b3 684 vpid_sync_vcpu_all(vmx);
543e4243
AK		 685 local_irq_disable();
686 list_add(&vmx->local_vcpus_link,
687 &per_cpu(vcpus_on_cpu, cpu));
688 local_irq_enable();
a3d7f85f 689 }
6aa8b732 690
a2fa3e9f 691 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 692 u8 error;
693
a2fa3e9f 694 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 695 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 696 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
697 : "cc");
698 if (error)
699 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 700 vmx->vmcs, phys_addr);
6aa8b732
AK		 701 }
702
703 if (vcpu->cpu != cpu) {
704 struct descriptor_table dt;
705 unsigned long sysenter_esp;
706
707 vcpu->cpu = cpu;
708 /*
709 * Linux uses per-cpu TSS and GDT, so set these when switching
710 * processors.
711 */
d6e88aec
AK		 712 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
713 kvm_get_gdt(&dt);
6aa8b732
AK		 714 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
715
716 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
717 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 718
719 /*
720 * Make sure the time stamp counter is monotonous.
721 */
722 rdtscll(tsc_this);
019960ae
AK		 723 if (tsc_this < vcpu->arch.host_tsc) {
724 delta = vcpu->arch.host_tsc - tsc_this;
725 new_offset = vmcs_read64(TSC_OFFSET) + delta;
726 vmcs_write64(TSC_OFFSET, new_offset);
727 }
6aa8b732 728 }
6aa8b732
AK		 729}
730
731static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
732{
a9b21b62 733 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 734}
735
5fd86fcf
AK		 736static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
737{
738 if (vcpu->fpu_active)
739 return;
740 vcpu->fpu_active = 1;
707d92fa 741 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 742 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 743 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 744 update_exception_bitmap(vcpu);
745}
746
747static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
748{
749 if (!vcpu->fpu_active)
750 return;
751 vcpu->fpu_active = 0;
707d92fa 752 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 753 update_exception_bitmap(vcpu);
754}
755
6aa8b732
AK		 756static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
757{
758 return vmcs_readl(GUEST_RFLAGS);
759}
760
761static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
762{
7ffd92c5 763 if (to_vmx(vcpu)->rmode.vm86_active)
053de044 764 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 765 vmcs_writel(GUEST_RFLAGS, rflags);
766}
767
2809f5d2
GC		 768static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
769{
770 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
771 int ret = 0;
772
773 if (interruptibility & GUEST_INTR_STATE_STI)
774 ret |= X86_SHADOW_INT_STI;
775 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
776 ret |= X86_SHADOW_INT_MOV_SS;
777
778 return ret & mask;
779}
780
781static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
782{
783 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
784 u32 interruptibility = interruptibility_old;
785
786 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
787
788 if (mask & X86_SHADOW_INT_MOV_SS)
789 interruptibility |= GUEST_INTR_STATE_MOV_SS;
790 if (mask & X86_SHADOW_INT_STI)
791 interruptibility |= GUEST_INTR_STATE_STI;
792
793 if ((interruptibility != interruptibility_old))
794 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
795}
796
6aa8b732
AK		 797static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
798{
799 unsigned long rip;
6aa8b732 800
5fdbf976 801 rip = kvm_rip_read(vcpu);
6aa8b732 802 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 803 kvm_rip_write(vcpu, rip);
6aa8b732 804
2809f5d2
GC		 805 /* skipping an emulated instruction also counts */
806 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 807}
808
298101da
AK		 809static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
810 bool has_error_code, u32 error_code)
811{
77ab6db0 812 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 813 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 814
8ab2d2e2 815 if (has_error_code) {
77ab6db0 816 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 817 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
818 }
77ab6db0 819
7ffd92c5 820 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 821 vmx->rmode.irq.pending = true;
822 vmx->rmode.irq.vector = nr;
823 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 824 if (kvm_exception_is_soft(nr))
825 vmx->rmode.irq.rip +=
826 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 827 intr_info |= INTR_TYPE_SOFT_INTR;
828 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 829 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
830 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
831 return;
832 }
833
66fd3f7f
GN		 834 if (kvm_exception_is_soft(nr)) {
835 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
836 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 837 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
838 } else
839 intr_info |= INTR_TYPE_HARD_EXCEPTION;
840
841 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 842}
843
a75beee6
ED		 844/*
845 * Swap MSR entry in host/guest MSR entry array.
846 */
54e11fa1 847#ifdef CONFIG_X86_64
8b9cf98c 848static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 849{
a2fa3e9f
GH		 850 struct kvm_msr_entry tmp;
851
852 tmp = vmx->guest_msrs[to];
853 vmx->guest_msrs[to] = vmx->guest_msrs[from];
854 vmx->guest_msrs[from] = tmp;
855 tmp = vmx->host_msrs[to];
856 vmx->host_msrs[to] = vmx->host_msrs[from];
857 vmx->host_msrs[from] = tmp;
a75beee6 858}
54e11fa1 859#endif
a75beee6 860
e38aea3e
AK		 861/*
862 * Set up the vmcs to automatically save and restore system
863 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
864 * mode, as fiddling with msrs is very expensive.
865 */
8b9cf98c 866static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 867{
2cc51560 868 int save_nmsrs;
5897297b 869 unsigned long *msr_bitmap;
e38aea3e 870
33f9c505 871 vmx_load_host_state(vmx);
a75beee6
ED		 872 save_nmsrs = 0;
873#ifdef CONFIG_X86_64
8b9cf98c 874 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 875 int index;
876
8b9cf98c 877 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 878 if (index >= 0)
8b9cf98c
RR		 879 move_msr_up(vmx, index, save_nmsrs++);
880 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 881 if (index >= 0)
8b9cf98c
RR		 882 move_msr_up(vmx, index, save_nmsrs++);
883 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 884 if (index >= 0)
8b9cf98c
RR		 885 move_msr_up(vmx, index, save_nmsrs++);
886 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 887 if (index >= 0)
8b9cf98c 888 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 889 /*
890 * MSR_K6_STAR is only needed on long mode guests, and only
891 * if efer.sce is enabled.
892 */
8b9cf98c 893 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 894 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 895 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 896 }
897#endif
a2fa3e9f 898 vmx->save_nmsrs = save_nmsrs;
e38aea3e 899
4d56c8a7 900#ifdef CONFIG_X86_64
a2fa3e9f 901 vmx->msr_offset_kernel_gs_base =
8b9cf98c 902 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 903#endif
8b9cf98c 904 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
5897297b
AK		 905
906 if (cpu_has_vmx_msr_bitmap()) {
907 if (is_long_mode(&vmx->vcpu))
908 msr_bitmap = vmx_msr_bitmap_longmode;
909 else
910 msr_bitmap = vmx_msr_bitmap_legacy;
911
912 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
913 }
e38aea3e
AK		 914}
915
6aa8b732
AK		 916/*
917 * reads and returns guest's timestamp counter "register"
918 * guest_tsc = host_tsc + tsc_offset -- 21.3
919 */
920static u64 guest_read_tsc(void)
921{
922 u64 host_tsc, tsc_offset;
923
924 rdtscll(host_tsc);
925 tsc_offset = vmcs_read64(TSC_OFFSET);
926 return host_tsc + tsc_offset;
927}
928
929/*
930 * writes 'guest_tsc' into guest's timestamp counter "register"
931 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
932 */
53f658b3 933static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 934{
6aa8b732
AK		 935 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
936}
937
6aa8b732
AK		 938/*
939 * Reads an msr value (of 'msr_index') into 'pdata'.
940 * Returns 0 on success, non-0 otherwise.
941 * Assumes vcpu_load() was already called.
942 */
943static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
944{
945 u64 data;
a2fa3e9f 946 struct kvm_msr_entry *msr;
6aa8b732
AK		 947
948 if (!pdata) {
949 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
950 return -EINVAL;
951 }
952
953 switch (msr_index) {
05b3e0c2 954#ifdef CONFIG_X86_64
6aa8b732
AK		 955 case MSR_FS_BASE:
956 data = vmcs_readl(GUEST_FS_BASE);
957 break;
958 case MSR_GS_BASE:
959 data = vmcs_readl(GUEST_GS_BASE);
960 break;
961 case MSR_EFER:
3bab1f5d 962 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732 963#endif
af24a4e4 964 case MSR_IA32_TSC:
6aa8b732
AK		 965 data = guest_read_tsc();
966 break;
967 case MSR_IA32_SYSENTER_CS:
968 data = vmcs_read32(GUEST_SYSENTER_CS);
969 break;
970 case MSR_IA32_SYSENTER_EIP:
f5b42c33 971 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 972 break;
973 case MSR_IA32_SYSENTER_ESP:
f5b42c33 974 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 975 break;
6aa8b732 976 default:
516a1a7e 977 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 978 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 979 if (msr) {
980 data = msr->data;
981 break;
6aa8b732 982 }
3bab1f5d 983 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 984 }
985
986 *pdata = data;
987 return 0;
988}
989
990/*
991 * Writes msr value into into the appropriate "register".
992 * Returns 0 on success, non-0 otherwise.
993 * Assumes vcpu_load() was already called.
994 */
995static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
996{
a2fa3e9f
GH		 997 struct vcpu_vmx *vmx = to_vmx(vcpu);
998 struct kvm_msr_entry *msr;
53f658b3 999 u64 host_tsc;
2cc51560
ED		 1000 int ret = 0;
1001
6aa8b732 1002 switch (msr_index) {
3bab1f5d 1003 case MSR_EFER:
a9b21b62 1004 vmx_load_host_state(vmx);
2cc51560 1005 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1006 break;
16175a79 1007#ifdef CONFIG_X86_64
6aa8b732
AK		 1008 case MSR_FS_BASE:
1009 vmcs_writel(GUEST_FS_BASE, data);
1010 break;
1011 case MSR_GS_BASE:
1012 vmcs_writel(GUEST_GS_BASE, data);
1013 break;
1014#endif
1015 case MSR_IA32_SYSENTER_CS:
1016 vmcs_write32(GUEST_SYSENTER_CS, data);
1017 break;
1018 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1019 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1020 break;
1021 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1022 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1023 break;
af24a4e4 1024 case MSR_IA32_TSC:
53f658b3
MT		 1025 rdtscll(host_tsc);
1026 guest_write_tsc(data, host_tsc);
6aa8b732 1027 break;
468d472f
SY		 1028 case MSR_IA32_CR_PAT:
1029 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1030 vmcs_write64(GUEST_IA32_PAT, data);
1031 vcpu->arch.pat = data;
1032 break;
1033 }
1034 /* Otherwise falls through to kvm_set_msr_common */
6aa8b732 1035 default:
a9b21b62 1036 vmx_load_host_state(vmx);
8b9cf98c 1037 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 1038 if (msr) {
1039 msr->data = data;
1040 break;
6aa8b732 1041 }
2cc51560 1042 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1043 }
1044
2cc51560 1045 return ret;
6aa8b732
AK		 1046}
1047
5fdbf976 1048static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1049{
5fdbf976
MT		 1050 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1051 switch (reg) {
1052 case VCPU_REGS_RSP:
1053 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1054 break;
1055 case VCPU_REGS_RIP:
1056 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1057 break;
6de4f3ad
AK		 1058 case VCPU_EXREG_PDPTR:
1059 if (enable_ept)
1060 ept_save_pdptrs(vcpu);
1061 break;
5fdbf976
MT		 1062 default:
1063 break;
1064 }
6aa8b732
AK		 1065}
1066
d0bfb940 1067static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1068{
d0bfb940
JK		 1069 int old_debug = vcpu->guest_debug;
1070 unsigned long flags;
6aa8b732 1071
d0bfb940
JK		 1072 vcpu->guest_debug = dbg->control;
1073 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1074 vcpu->guest_debug = 0;
6aa8b732 1075
ae675ef0
JK		 1076 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1077 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1078 else
1079 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1080
d0bfb940
JK		 1081 flags = vmcs_readl(GUEST_RFLAGS);
1082 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1083 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1084 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
6aa8b732 1085 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
d0bfb940 1086 vmcs_writel(GUEST_RFLAGS, flags);
6aa8b732 1087
abd3f2d6 1088 update_exception_bitmap(vcpu);
6aa8b732
AK		 1089
1090 return 0;
1091}
1092
1093static __init int cpu_has_kvm_support(void)
1094{
6210e37b 1095 return cpu_has_vmx();
6aa8b732
AK		 1096}
1097
1098static __init int vmx_disabled_by_bios(void)
1099{
1100 u64 msr;
1101
1102 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1103 return (msr & (FEATURE_CONTROL_LOCKED |
1104 FEATURE_CONTROL_VMXON_ENABLED))
1105 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1106 /* locked but not enabled */
6aa8b732
AK		 1107}
1108
774c47f1 1109static void hardware_enable(void *garbage)
6aa8b732
AK		 1110{
1111 int cpu = raw_smp_processor_id();
1112 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1113 u64 old;
1114
543e4243 1115 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1116 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1117 if ((old & (FEATURE_CONTROL_LOCKED |
1118 FEATURE_CONTROL_VMXON_ENABLED))
1119 != (FEATURE_CONTROL_LOCKED |
1120 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1121 /* enable and lock */
62b3ffb8 1122 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1123 FEATURE_CONTROL_LOCKED |
1124 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1125 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1126 asm volatile (ASM_VMX_VMXON_RAX
1127 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1128 : "memory", "cc");
1129}
1130
543e4243
AK		 1131static void vmclear_local_vcpus(void)
1132{
1133 int cpu = raw_smp_processor_id();
1134 struct vcpu_vmx *vmx, *n;
1135
1136 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1137 local_vcpus_link)
1138 __vcpu_clear(vmx);
1139}
1140
710ff4a8
EH		 1141
1142/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1143 * tricks.
1144 */
1145static void kvm_cpu_vmxoff(void)
6aa8b732 1146{
4ecac3fd 1147 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1148 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1149}
1150
710ff4a8
EH		 1151static void hardware_disable(void *garbage)
1152{
1153 vmclear_local_vcpus();
1154 kvm_cpu_vmxoff();
1155}
1156
1c3d14fe 1157static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1158 u32 msr, u32 *result)
1c3d14fe
YS		 1159{
1160 u32 vmx_msr_low, vmx_msr_high;
1161 u32 ctl = ctl_min | ctl_opt;
1162
1163 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1164
1165 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1166 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1167
1168 /* Ensure minimum (required) set of control bits are supported. */
1169 if (ctl_min & ~ctl)
002c7f7c 1170 return -EIO;
1c3d14fe
YS		 1171
1172 *result = ctl;
1173 return 0;
1174}
1175
002c7f7c 1176static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1177{
1178 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1179 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1180 u32 _pin_based_exec_control = 0;
1181 u32 _cpu_based_exec_control = 0;
f78e0e2e 1182 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1183 u32 _vmexit_control = 0;
1184 u32 _vmentry_control = 0;
1185
1186 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1187 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1188 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1189 &_pin_based_exec_control) < 0)
002c7f7c 1190 return -EIO;
1c3d14fe
YS		 1191
1192 min = CPU_BASED_HLT_EXITING |
1193#ifdef CONFIG_X86_64
1194 CPU_BASED_CR8_LOAD_EXITING |
1195 CPU_BASED_CR8_STORE_EXITING |
1196#endif
d56f546d
SY		 1197 CPU_BASED_CR3_LOAD_EXITING |
1198 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1199 CPU_BASED_USE_IO_BITMAPS |
1200 CPU_BASED_MOV_DR_EXITING |
a7052897
MT		 1201 CPU_BASED_USE_TSC_OFFSETING |
1202 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1203 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1204 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1205 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1206 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1207 &_cpu_based_exec_control) < 0)
002c7f7c 1208 return -EIO;
6e5d865c
YS		 1209#ifdef CONFIG_X86_64
1210 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1211 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1212 ~CPU_BASED_CR8_STORE_EXITING;
1213#endif
f78e0e2e 1214 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1215 min2 = 0;
1216 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1217 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1218 SECONDARY_EXEC_ENABLE_VPID |
3a624e29
NK		 1219 SECONDARY_EXEC_ENABLE_EPT |
1220 SECONDARY_EXEC_UNRESTRICTED_GUEST;
d56f546d
SY		 1221 if (adjust_vmx_controls(min2, opt2,
1222 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1223 &_cpu_based_2nd_exec_control) < 0)
1224 return -EIO;
1225 }
1226#ifndef CONFIG_X86_64
1227 if (!(_cpu_based_2nd_exec_control &
1228 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1229 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1230#endif
d56f546d 1231 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1232 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1233 enabled */
d56f546d 1234 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
a7052897
MT		 1235 CPU_BASED_CR3_STORE_EXITING |
1236 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1237 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1238 &_cpu_based_exec_control) < 0)
1239 return -EIO;
1240 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1241 vmx_capability.ept, vmx_capability.vpid);
1242 }
1c3d14fe
YS		 1243
1244 min = 0;
1245#ifdef CONFIG_X86_64
1246 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1247#endif
468d472f 1248 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1249 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1250 &_vmexit_control) < 0)
002c7f7c 1251 return -EIO;
1c3d14fe 1252
468d472f
SY		 1253 min = 0;
1254 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1255 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1256 &_vmentry_control) < 0)
002c7f7c 1257 return -EIO;
6aa8b732 1258
c68876fd 1259 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1260
1261 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1262 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1263 return -EIO;
1c3d14fe
YS		 1264
1265#ifdef CONFIG_X86_64
1266 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1267 if (vmx_msr_high & (1u<<16))
002c7f7c 1268 return -EIO;
1c3d14fe
YS		 1269#endif
1270
1271 /* Require Write-Back (WB) memory type for VMCS accesses. */
1272 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1273 return -EIO;
1c3d14fe 1274
002c7f7c
YS		 1275 vmcs_conf->size = vmx_msr_high & 0x1fff;
1276 vmcs_conf->order = get_order(vmcs_config.size);
1277 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1278
002c7f7c
YS		 1279 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1280 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1281 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1282 vmcs_conf->vmexit_ctrl = _vmexit_control;
1283 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1284
1285 return 0;
c68876fd 1286}
6aa8b732
AK		 1287
1288static struct vmcs *alloc_vmcs_cpu(int cpu)
1289{
1290 int node = cpu_to_node(cpu);
1291 struct page *pages;
1292 struct vmcs *vmcs;
1293
6484eb3e 1294 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1295 if (!pages)
1296 return NULL;
1297 vmcs = page_address(pages);
1c3d14fe
YS		 1298 memset(vmcs, 0, vmcs_config.size);
1299 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1300 return vmcs;
1301}
1302
1303static struct vmcs *alloc_vmcs(void)
1304{
d3b2c338 1305 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1306}
1307
1308static void free_vmcs(struct vmcs *vmcs)
1309{
1c3d14fe 1310 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1311}
1312
39959588 1313static void free_kvm_area(void)
6aa8b732
AK		 1314{
1315 int cpu;
1316
1317 for_each_online_cpu(cpu)
1318 free_vmcs(per_cpu(vmxarea, cpu));
1319}
1320
6aa8b732
AK		 1321static __init int alloc_kvm_area(void)
1322{
1323 int cpu;
1324
1325 for_each_online_cpu(cpu) {
1326 struct vmcs *vmcs;
1327
1328 vmcs = alloc_vmcs_cpu(cpu);
1329 if (!vmcs) {
1330 free_kvm_area();
1331 return -ENOMEM;
1332 }
1333
1334 per_cpu(vmxarea, cpu) = vmcs;
1335 }
1336 return 0;
1337}
1338
1339static __init int hardware_setup(void)
1340{
002c7f7c
YS		 1341 if (setup_vmcs_config(&vmcs_config) < 0)
1342 return -EIO;
50a37eb4
JR		 1343
1344 if (boot_cpu_has(X86_FEATURE_NX))
1345 kvm_enable_efer_bits(EFER_NX);
1346
93ba03c2
SY		 1347 if (!cpu_has_vmx_vpid())
1348 enable_vpid = 0;
1349
3a624e29 1350 if (!cpu_has_vmx_ept()) {
93ba03c2 1351 enable_ept = 0;
3a624e29
NK		 1352 enable_unrestricted_guest = 0;
1353 }
1354
1355 if (!cpu_has_vmx_unrestricted_guest())
1356 enable_unrestricted_guest = 0;
93ba03c2
SY		 1357
1358 if (!cpu_has_vmx_flexpriority())
1359 flexpriority_enabled = 0;
1360
95ba8273
GN		 1361 if (!cpu_has_vmx_tpr_shadow())
1362 kvm_x86_ops->update_cr8_intercept = NULL;
1363
6aa8b732
AK		 1364 return alloc_kvm_area();
1365}
1366
1367static __exit void hardware_unsetup(void)
1368{
1369 free_kvm_area();
1370}
1371
6aa8b732
AK		 1372static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1373{
1374 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1375
6af11b9e 1376 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1377 vmcs_write16(sf->selector, save->selector);
1378 vmcs_writel(sf->base, save->base);
1379 vmcs_write32(sf->limit, save->limit);
1380 vmcs_write32(sf->ar_bytes, save->ar);
1381 } else {
1382 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1383 << AR_DPL_SHIFT;
1384 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1385 }
1386}
1387
1388static void enter_pmode(struct kvm_vcpu *vcpu)
1389{
1390 unsigned long flags;
a89a8fb9 1391 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1392
a89a8fb9 1393 vmx->emulation_required = 1;
7ffd92c5 1394 vmx->rmode.vm86_active = 0;
6aa8b732 1395
7ffd92c5
AK		 1396 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1397 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1398 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1399
1400 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1401 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
7ffd92c5 1402 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1403 vmcs_writel(GUEST_RFLAGS, flags);
1404
66aee91a
RR		 1405 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1406 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1407
1408 update_exception_bitmap(vcpu);
1409
a89a8fb9
MG		 1410 if (emulate_invalid_guest_state)
1411 return;
1412
7ffd92c5
AK		 1413 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1414 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1415 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1416 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1417
1418 vmcs_write16(GUEST_SS_SELECTOR, 0);
1419 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1420
1421 vmcs_write16(GUEST_CS_SELECTOR,
1422 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1423 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1424}
1425
d77c26fc 1426static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1427{
bfc6d222 1428 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1429 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1430 kvm->memslots[0].npages - 3;
1431 return base_gfn << PAGE_SHIFT;
1432 }
bfc6d222 1433 return kvm->arch.tss_addr;
6aa8b732
AK		 1434}
1435
1436static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1437{
1438 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1439
1440 save->selector = vmcs_read16(sf->selector);
1441 save->base = vmcs_readl(sf->base);
1442 save->limit = vmcs_read32(sf->limit);
1443 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1444 vmcs_write16(sf->selector, save->base >> 4);
1445 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1446 vmcs_write32(sf->limit, 0xffff);
1447 vmcs_write32(sf->ar_bytes, 0xf3);
1448}
1449
1450static void enter_rmode(struct kvm_vcpu *vcpu)
1451{
1452 unsigned long flags;
a89a8fb9 1453 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1454
3a624e29
NK		 1455 if (enable_unrestricted_guest)
1456 return;
1457
a89a8fb9 1458 vmx->emulation_required = 1;
7ffd92c5 1459 vmx->rmode.vm86_active = 1;
6aa8b732 1460
7ffd92c5 1461 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1462 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1463
7ffd92c5 1464 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1465 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1466
7ffd92c5 1467 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1468 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1469
1470 flags = vmcs_readl(GUEST_RFLAGS);
7ffd92c5 1471 vmx->rmode.save_iopl
ad312c7c 1472 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1473
053de044 1474 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1475
1476 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1477 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1478 update_exception_bitmap(vcpu);
1479
a89a8fb9
MG		 1480 if (emulate_invalid_guest_state)
1481 goto continue_rmode;
1482
6aa8b732
AK		 1483 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1484 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1485 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1486
1487 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1488 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1489 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1490 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1491 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1492
7ffd92c5
AK		 1493 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1494 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1495 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1496 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1497
a89a8fb9 1498continue_rmode:
8668a3c4 1499 kvm_mmu_reset_context(vcpu);
b7ebfb05 1500 init_rmode(vcpu->kvm);
6aa8b732
AK		 1501}
1502
401d10de
AS		 1503static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1504{
1505 struct vcpu_vmx *vmx = to_vmx(vcpu);
1506 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1507
1508 vcpu->arch.shadow_efer = efer;
1509 if (!msr)
1510 return;
1511 if (efer & EFER_LMA) {
1512 vmcs_write32(VM_ENTRY_CONTROLS,
1513 vmcs_read32(VM_ENTRY_CONTROLS) |
1514 VM_ENTRY_IA32E_MODE);
1515 msr->data = efer;
1516 } else {
1517 vmcs_write32(VM_ENTRY_CONTROLS,
1518 vmcs_read32(VM_ENTRY_CONTROLS) &
1519 ~VM_ENTRY_IA32E_MODE);
1520
1521 msr->data = efer & ~EFER_LME;
1522 }
1523 setup_msrs(vmx);
1524}
1525
05b3e0c2 1526#ifdef CONFIG_X86_64
6aa8b732
AK		 1527
1528static void enter_lmode(struct kvm_vcpu *vcpu)
1529{
1530 u32 guest_tr_ar;
1531
1532 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1533 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1534 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1535 __func__);
6aa8b732
AK		 1536 vmcs_write32(GUEST_TR_AR_BYTES,
1537 (guest_tr_ar & ~AR_TYPE_MASK)
1538 | AR_TYPE_BUSY_64_TSS);
1539 }
ad312c7c 1540 vcpu->arch.shadow_efer |= EFER_LMA;
401d10de 1541 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
6aa8b732
AK		 1542}
1543
1544static void exit_lmode(struct kvm_vcpu *vcpu)
1545{
ad312c7c 1546 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1547
1548 vmcs_write32(VM_ENTRY_CONTROLS,
1549 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1550 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1551}
1552
1553#endif
1554
2384d2b3
SY		 1555static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1556{
1557 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1558 if (enable_ept)
4e1096d2 1559 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1560}
1561
25c4c276 1562static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1563{
ad312c7c
ZX		 1564 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1565 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1566}
1567
1439442c
SY		 1568static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1569{
6de4f3ad
AK		 1570 if (!test_bit(VCPU_EXREG_PDPTR,
1571 (unsigned long *)&vcpu->arch.regs_dirty))
1572 return;
1573
1439442c 1574 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1575 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1576 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1577 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1578 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1579 }
1580}
1581
8f5d549f
AK		 1582static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1583{
1584 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1585 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1586 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1587 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1588 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1589 }
6de4f3ad
AK		 1590
1591 __set_bit(VCPU_EXREG_PDPTR,
1592 (unsigned long *)&vcpu->arch.regs_avail);
1593 __set_bit(VCPU_EXREG_PDPTR,
1594 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1595}
1596
1439442c
SY		 1597static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1598
1599static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1600 unsigned long cr0,
1601 struct kvm_vcpu *vcpu)
1602{
1603 if (!(cr0 & X86_CR0_PG)) {
1604 /* From paging/starting to nonpaging */
1605 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1606 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1607 (CPU_BASED_CR3_LOAD_EXITING |
1608 CPU_BASED_CR3_STORE_EXITING));
1609 vcpu->arch.cr0 = cr0;
1610 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1439442c
SY		 1611 *hw_cr0 &= ~X86_CR0_WP;
1612 } else if (!is_paging(vcpu)) {
1613 /* From nonpaging to paging */
1614 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1615 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1616 ~(CPU_BASED_CR3_LOAD_EXITING |
1617 CPU_BASED_CR3_STORE_EXITING));
1618 vcpu->arch.cr0 = cr0;
1619 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1620 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1621 *hw_cr0 &= ~X86_CR0_WP;
1622 }
1623}
1624
1625static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1626 struct kvm_vcpu *vcpu)
1627{
1628 if (!is_paging(vcpu)) {
1629 *hw_cr4 &= ~X86_CR4_PAE;
1630 *hw_cr4 |= X86_CR4_PSE;
1631 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1632 *hw_cr4 &= ~X86_CR4_PAE;
1633}
1634
6aa8b732
AK		 1635static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1636{
7ffd92c5 1637 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1638 unsigned long hw_cr0;
1639
1640 if (enable_unrestricted_guest)
1641 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1642 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1643 else
1644 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1645
5fd86fcf
AK		 1646 vmx_fpu_deactivate(vcpu);
1647
7ffd92c5 1648 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1649 enter_pmode(vcpu);
1650
7ffd92c5 1651 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1652 enter_rmode(vcpu);
1653
05b3e0c2 1654#ifdef CONFIG_X86_64
ad312c7c 1655 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1656 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1657 enter_lmode(vcpu);
707d92fa 1658 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1659 exit_lmode(vcpu);
1660 }
1661#endif
1662
089d034e 1663 if (enable_ept)
1439442c
SY		 1664 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1665
6aa8b732 1666 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1667 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1668 vcpu->arch.cr0 = cr0;
5fd86fcf 1669
707d92fa 1670 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1671 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1672}
1673
1439442c
SY		 1674static u64 construct_eptp(unsigned long root_hpa)
1675{
1676 u64 eptp;
1677
1678 /* TODO write the value reading from MSR */
1679 eptp = VMX_EPT_DEFAULT_MT |
1680 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1681 eptp |= (root_hpa & PAGE_MASK);
1682
1683 return eptp;
1684}
1685
6aa8b732
AK		 1686static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1687{
1439442c
SY		 1688 unsigned long guest_cr3;
1689 u64 eptp;
1690
1691 guest_cr3 = cr3;
089d034e 1692 if (enable_ept) {
1439442c
SY		 1693 eptp = construct_eptp(cr3);
1694 vmcs_write64(EPT_POINTER, eptp);
1439442c
SY		 1695 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1696 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1697 }
1698
2384d2b3 1699 vmx_flush_tlb(vcpu);
1439442c 1700 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1701 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1702 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1703}
1704
1705static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1706{
7ffd92c5 1707 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1708 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1709
ad312c7c 1710 vcpu->arch.cr4 = cr4;
089d034e 1711 if (enable_ept)
1439442c
SY		 1712 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1713
1714 vmcs_writel(CR4_READ_SHADOW, cr4);
1715 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1716}
1717
6aa8b732
AK		 1718static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1719{
1720 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1721
1722 return vmcs_readl(sf->base);
1723}
1724
1725static void vmx_get_segment(struct kvm_vcpu *vcpu,
1726 struct kvm_segment *var, int seg)
1727{
1728 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1729 u32 ar;
1730
1731 var->base = vmcs_readl(sf->base);
1732 var->limit = vmcs_read32(sf->limit);
1733 var->selector = vmcs_read16(sf->selector);
1734 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1735 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1736 ar = 0;
1737 var->type = ar & 15;
1738 var->s = (ar >> 4) & 1;
1739 var->dpl = (ar >> 5) & 3;
1740 var->present = (ar >> 7) & 1;
1741 var->avl = (ar >> 12) & 1;
1742 var->l = (ar >> 13) & 1;
1743 var->db = (ar >> 14) & 1;
1744 var->g = (ar >> 15) & 1;
1745 var->unusable = (ar >> 16) & 1;
1746}
1747
2e4d2653
IE		 1748static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1749{
1750 struct kvm_segment kvm_seg;
1751
1752 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1753 return 0;
1754
1755 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1756 return 3;
1757
1758 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1759 return kvm_seg.selector & 3;
1760}
1761
653e3108 1762static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1763{
6aa8b732
AK		 1764 u32 ar;
1765
653e3108 1766 if (var->unusable)
6aa8b732
AK		 1767 ar = 1 << 16;
1768 else {
1769 ar = var->type & 15;
1770 ar |= (var->s & 1) << 4;
1771 ar |= (var->dpl & 3) << 5;
1772 ar |= (var->present & 1) << 7;
1773 ar |= (var->avl & 1) << 12;
1774 ar |= (var->l & 1) << 13;
1775 ar |= (var->db & 1) << 14;
1776 ar |= (var->g & 1) << 15;
1777 }
f7fbf1fd
UL		 1778 if (ar == 0) /* a 0 value means unusable */
1779 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1780
1781 return ar;
1782}
1783
1784static void vmx_set_segment(struct kvm_vcpu *vcpu,
1785 struct kvm_segment *var, int seg)
1786{
7ffd92c5 1787 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 1788 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1789 u32 ar;
1790
7ffd92c5
AK		 1791 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1792 vmx->rmode.tr.selector = var->selector;
1793 vmx->rmode.tr.base = var->base;
1794 vmx->rmode.tr.limit = var->limit;
1795 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1796 return;
1797 }
1798 vmcs_writel(sf->base, var->base);
1799 vmcs_write32(sf->limit, var->limit);
1800 vmcs_write16(sf->selector, var->selector);
7ffd92c5 1801 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 1802 /*
1803 * Hack real-mode segments into vm86 compatibility.
1804 */
1805 if (var->base == 0xffff0000 && var->selector == 0xf000)
1806 vmcs_writel(sf->base, 0xf0000);
1807 ar = 0xf3;
1808 } else
1809 ar = vmx_segment_access_rights(var);
3a624e29
NK		 1810
1811 /*
1812 * Fix the "Accessed" bit in AR field of segment registers for older
1813 * qemu binaries.
1814 * IA32 arch specifies that at the time of processor reset the
1815 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1816 * is setting it to 0 in the usedland code. This causes invalid guest
1817 * state vmexit when "unrestricted guest" mode is turned on.
1818 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1819 * tree. Newer qemu binaries with that qemu fix would not need this
1820 * kvm hack.
1821 */
1822 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1823 ar |= 0x1; /* Accessed */
1824
6aa8b732
AK		 1825 vmcs_write32(sf->ar_bytes, ar);
1826}
1827
6aa8b732
AK		 1828static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1829{
1830 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1831
1832 *db = (ar >> 14) & 1;
1833 *l = (ar >> 13) & 1;
1834}
1835
1836static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1837{
1838 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1839 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1840}
1841
1842static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1843{
1844 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1845 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1846}
1847
1848static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1849{
1850 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1851 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1852}
1853
1854static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1855{
1856 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1857 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1858}
1859
648dfaa7
MG		 1860static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1861{
1862 struct kvm_segment var;
1863 u32 ar;
1864
1865 vmx_get_segment(vcpu, &var, seg);
1866 ar = vmx_segment_access_rights(&var);
1867
1868 if (var.base != (var.selector << 4))
1869 return false;
1870 if (var.limit != 0xffff)
1871 return false;
1872 if (ar != 0xf3)
1873 return false;
1874
1875 return true;
1876}
1877
1878static bool code_segment_valid(struct kvm_vcpu *vcpu)
1879{
1880 struct kvm_segment cs;
1881 unsigned int cs_rpl;
1882
1883 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1884 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1885
1872a3f4
AK		 1886 if (cs.unusable)
1887 return false;
648dfaa7
MG		 1888 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1889 return false;
1890 if (!cs.s)
1891 return false;
1872a3f4 1892 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1893 if (cs.dpl > cs_rpl)
1894 return false;
1872a3f4 1895 } else {
648dfaa7
MG		 1896 if (cs.dpl != cs_rpl)
1897 return false;
1898 }
1899 if (!cs.present)
1900 return false;
1901
1902 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1903 return true;
1904}
1905
1906static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1907{
1908 struct kvm_segment ss;
1909 unsigned int ss_rpl;
1910
1911 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1912 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1913
1872a3f4
AK		 1914 if (ss.unusable)
1915 return true;
1916 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 1917 return false;
1918 if (!ss.s)
1919 return false;
1920 if (ss.dpl != ss_rpl) /* DPL != RPL */
1921 return false;
1922 if (!ss.present)
1923 return false;
1924
1925 return true;
1926}
1927
1928static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1929{
1930 struct kvm_segment var;
1931 unsigned int rpl;
1932
1933 vmx_get_segment(vcpu, &var, seg);
1934 rpl = var.selector & SELECTOR_RPL_MASK;
1935
1872a3f4
AK		 1936 if (var.unusable)
1937 return true;
648dfaa7
MG		 1938 if (!var.s)
1939 return false;
1940 if (!var.present)
1941 return false;
1942 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1943 if (var.dpl < rpl) /* DPL < RPL */
1944 return false;
1945 }
1946
1947 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1948 * rights flags
1949 */
1950 return true;
1951}
1952
1953static bool tr_valid(struct kvm_vcpu *vcpu)
1954{
1955 struct kvm_segment tr;
1956
1957 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1958
1872a3f4
AK		 1959 if (tr.unusable)
1960 return false;
648dfaa7
MG		 1961 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1962 return false;
1872a3f4 1963 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 1964 return false;
1965 if (!tr.present)
1966 return false;
1967
1968 return true;
1969}
1970
1971static bool ldtr_valid(struct kvm_vcpu *vcpu)
1972{
1973 struct kvm_segment ldtr;
1974
1975 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1976
1872a3f4
AK		 1977 if (ldtr.unusable)
1978 return true;
648dfaa7
MG		 1979 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1980 return false;
1981 if (ldtr.type != 2)
1982 return false;
1983 if (!ldtr.present)
1984 return false;
1985
1986 return true;
1987}
1988
1989static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1990{
1991 struct kvm_segment cs, ss;
1992
1993 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1994 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1995
1996 return ((cs.selector & SELECTOR_RPL_MASK) ==
1997 (ss.selector & SELECTOR_RPL_MASK));
1998}
1999
2000/*
2001 * Check if guest state is valid. Returns true if valid, false if
2002 * not.
2003 * We assume that registers are always usable
2004 */
2005static bool guest_state_valid(struct kvm_vcpu *vcpu)
2006{
2007 /* real mode guest state checks */
2008 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2009 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2010 return false;
2011 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2012 return false;
2013 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2014 return false;
2015 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2016 return false;
2017 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2018 return false;
2019 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2020 return false;
2021 } else {
2022 /* protected mode guest state checks */
2023 if (!cs_ss_rpl_check(vcpu))
2024 return false;
2025 if (!code_segment_valid(vcpu))
2026 return false;
2027 if (!stack_segment_valid(vcpu))
2028 return false;
2029 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2030 return false;
2031 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2032 return false;
2033 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2034 return false;
2035 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2036 return false;
2037 if (!tr_valid(vcpu))
2038 return false;
2039 if (!ldtr_valid(vcpu))
2040 return false;
2041 }
2042 /* TODO:
2043 * - Add checks on RIP
2044 * - Add checks on RFLAGS
2045 */
2046
2047 return true;
2048}
2049
d77c26fc 2050static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2051{
6aa8b732 2052 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2053 u16 data = 0;
10589a46 2054 int ret = 0;
195aefde 2055 int r;
6aa8b732 2056
195aefde
IE		 2057 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2058 if (r < 0)
10589a46 2059 goto out;
195aefde 2060 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2061 r = kvm_write_guest_page(kvm, fn++, &data,
2062 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2063 if (r < 0)
10589a46 2064 goto out;
195aefde
IE		 2065 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2066 if (r < 0)
10589a46 2067 goto out;
195aefde
IE		 2068 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2069 if (r < 0)
10589a46 2070 goto out;
195aefde 2071 data = ~0;
10589a46
MT		 2072 r = kvm_write_guest_page(kvm, fn, &data,
2073 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2074 sizeof(u8));
195aefde 2075 if (r < 0)
10589a46
MT		 2076 goto out;
2077
2078 ret = 1;
2079out:
10589a46 2080 return ret;
6aa8b732
AK		 2081}
2082
b7ebfb05
SY		 2083static int init_rmode_identity_map(struct kvm *kvm)
2084{
2085 int i, r, ret;
2086 pfn_t identity_map_pfn;
2087 u32 tmp;
2088
089d034e 2089 if (!enable_ept)
b7ebfb05
SY		 2090 return 1;
2091 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2092 printk(KERN_ERR "EPT: identity-mapping pagetable "
2093 "haven't been allocated!\n");
2094 return 0;
2095 }
2096 if (likely(kvm->arch.ept_identity_pagetable_done))
2097 return 1;
2098 ret = 0;
2099 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2100 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2101 if (r < 0)
2102 goto out;
2103 /* Set up identity-mapping pagetable for EPT in real mode */
2104 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2105 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2106 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2107 r = kvm_write_guest_page(kvm, identity_map_pfn,
2108 &tmp, i * sizeof(tmp), sizeof(tmp));
2109 if (r < 0)
2110 goto out;
2111 }
2112 kvm->arch.ept_identity_pagetable_done = true;
2113 ret = 1;
2114out:
2115 return ret;
2116}
2117
6aa8b732
AK		 2118static void seg_setup(int seg)
2119{
2120 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2121 unsigned int ar;
6aa8b732
AK		 2122
2123 vmcs_write16(sf->selector, 0);
2124 vmcs_writel(sf->base, 0);
2125 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2126 if (enable_unrestricted_guest) {
2127 ar = 0x93;
2128 if (seg == VCPU_SREG_CS)
2129 ar |= 0x08; /* code segment */
2130 } else
2131 ar = 0xf3;
2132
2133 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2134}
2135
f78e0e2e
SY		 2136static int alloc_apic_access_page(struct kvm *kvm)
2137{
2138 struct kvm_userspace_memory_region kvm_userspace_mem;
2139 int r = 0;
2140
72dc67a6 2141 down_write(&kvm->slots_lock);
bfc6d222 2142 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2143 goto out;
2144 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2145 kvm_userspace_mem.flags = 0;
2146 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2147 kvm_userspace_mem.memory_size = PAGE_SIZE;
2148 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2149 if (r)
2150 goto out;
72dc67a6 2151
bfc6d222 2152 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2153out:
72dc67a6 2154 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2155 return r;
2156}
2157
b7ebfb05
SY		 2158static int alloc_identity_pagetable(struct kvm *kvm)
2159{
2160 struct kvm_userspace_memory_region kvm_userspace_mem;
2161 int r = 0;
2162
2163 down_write(&kvm->slots_lock);
2164 if (kvm->arch.ept_identity_pagetable)
2165 goto out;
2166 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2167 kvm_userspace_mem.flags = 0;
2168 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2169 kvm_userspace_mem.memory_size = PAGE_SIZE;
2170 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2171 if (r)
2172 goto out;
2173
b7ebfb05
SY		 2174 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2175 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
b7ebfb05
SY		 2176out:
2177 up_write(&kvm->slots_lock);
2178 return r;
2179}
2180
2384d2b3
SY		 2181static void allocate_vpid(struct vcpu_vmx *vmx)
2182{
2183 int vpid;
2184
2185 vmx->vpid = 0;
919818ab 2186 if (!enable_vpid)
2384d2b3
SY		 2187 return;
2188 spin_lock(&vmx_vpid_lock);
2189 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2190 if (vpid < VMX_NR_VPIDS) {
2191 vmx->vpid = vpid;
2192 __set_bit(vpid, vmx_vpid_bitmap);
2193 }
2194 spin_unlock(&vmx_vpid_lock);
2195}
2196
5897297b 2197static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2198{
3e7c73e9 2199 int f = sizeof(unsigned long);
25c5f225
SY		 2200
2201 if (!cpu_has_vmx_msr_bitmap())
2202 return;
2203
2204 /*
2205 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2206 * have the write-low and read-high bitmap offsets the wrong way round.
2207 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2208 */
25c5f225 2209 if (msr <= 0x1fff) {
3e7c73e9
AK		 2210 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2211 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2212 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2213 msr &= 0x1fff;
3e7c73e9
AK		 2214 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2215 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2216 }
25c5f225
SY		 2217}
2218
5897297b
AK		 2219static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2220{
2221 if (!longmode_only)
2222 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2223 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2224}
2225
6aa8b732
AK		 2226/*
2227 * Sets up the vmcs for emulated real mode.
2228 */
8b9cf98c 2229static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2230{
468d472f 2231 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2232 u32 junk;
53f658b3 2233 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2234 unsigned long a;
2235 struct descriptor_table dt;
2236 int i;
cd2276a7 2237 unsigned long kvm_vmx_return;
6e5d865c 2238 u32 exec_control;
6aa8b732 2239
6aa8b732 2240 /* I/O */
3e7c73e9
AK		 2241 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2242 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2243
25c5f225 2244 if (cpu_has_vmx_msr_bitmap())
5897297b 2245 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2246
6aa8b732
AK		 2247 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2248
6aa8b732 2249 /* Control */
1c3d14fe
YS		 2250 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2251 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2252
2253 exec_control = vmcs_config.cpu_based_exec_ctrl;
2254 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2255 exec_control &= ~CPU_BASED_TPR_SHADOW;
2256#ifdef CONFIG_X86_64
2257 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2258 CPU_BASED_CR8_LOAD_EXITING;
2259#endif
2260 }
089d034e 2261 if (!enable_ept)
d56f546d 2262 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2263 CPU_BASED_CR3_LOAD_EXITING |
2264 CPU_BASED_INVLPG_EXITING;
6e5d865c 2265 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2266
83ff3b9d
SY		 2267 if (cpu_has_secondary_exec_ctrls()) {
2268 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2269 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2270 exec_control &=
2271 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2272 if (vmx->vpid == 0)
2273 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
089d034e 2274 if (!enable_ept)
d56f546d 2275 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3a624e29
NK		 2276 if (!enable_unrestricted_guest)
2277 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
83ff3b9d
SY		 2278 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2279 }
f78e0e2e 2280
c7addb90
AK		 2281 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2282 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2283 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2284
2285 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2286 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2287 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2288
2289 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2290 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2291 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2292 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2293 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2294 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2295#ifdef CONFIG_X86_64
6aa8b732
AK		 2296 rdmsrl(MSR_FS_BASE, a);
2297 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2298 rdmsrl(MSR_GS_BASE, a);
2299 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2300#else
2301 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2302 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2303#endif
2304
2305 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2306
d6e88aec 2307 kvm_get_idt(&dt);
6aa8b732
AK		 2308 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2309
d77c26fc 2310 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2311 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2312 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2313 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2314 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2315
2316 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2317 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2318 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2319 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2320 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2321 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2322
468d472f
SY		 2323 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2324 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2325 host_pat = msr_low | ((u64) msr_high << 32);
2326 vmcs_write64(HOST_IA32_PAT, host_pat);
2327 }
2328 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2329 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2330 host_pat = msr_low | ((u64) msr_high << 32);
2331 /* Write the default value follow host pat */
2332 vmcs_write64(GUEST_IA32_PAT, host_pat);
2333 /* Keep arch.pat sync with GUEST_IA32_PAT */
2334 vmx->vcpu.arch.pat = host_pat;
2335 }
2336
6aa8b732
AK		 2337 for (i = 0; i < NR_VMX_MSR; ++i) {
2338 u32 index = vmx_msr_index[i];
2339 u32 data_low, data_high;
2340 u64 data;
a2fa3e9f 2341 int j = vmx->nmsrs;
6aa8b732
AK		 2342
2343 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2344 continue;
432bd6cb
AK		 2345 if (wrmsr_safe(index, data_low, data_high) < 0)
2346 continue;
6aa8b732 2347 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 2348 vmx->host_msrs[j].index = index;
2349 vmx->host_msrs[j].reserved = 0;
2350 vmx->host_msrs[j].data = data;
2351 vmx->guest_msrs[j] = vmx->host_msrs[j];
2352 ++vmx->nmsrs;
6aa8b732 2353 }
6aa8b732 2354
1c3d14fe 2355 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2356
2357 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2358 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2359
e00c8cf2
AK		 2360 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2361 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2362
53f658b3
MT		 2363 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2364 rdtscll(tsc_this);
2365 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2366 tsc_base = tsc_this;
2367
2368 guest_write_tsc(0, tsc_base);
f78e0e2e 2369
e00c8cf2
AK		 2370 return 0;
2371}
2372
b7ebfb05
SY		 2373static int init_rmode(struct kvm *kvm)
2374{
2375 if (!init_rmode_tss(kvm))
2376 return 0;
2377 if (!init_rmode_identity_map(kvm))
2378 return 0;
2379 return 1;
2380}
2381
e00c8cf2
AK		 2382static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2383{
2384 struct vcpu_vmx *vmx = to_vmx(vcpu);
2385 u64 msr;
2386 int ret;
2387
5fdbf976 2388 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2389 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2390 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2391 ret = -ENOMEM;
2392 goto out;
2393 }
2394
7ffd92c5 2395 vmx->rmode.vm86_active = 0;
e00c8cf2 2396
3b86cd99
JK		 2397 vmx->soft_vnmi_blocked = 0;
2398
ad312c7c 2399 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2400 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2401 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2402 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2403 msr |= MSR_IA32_APICBASE_BSP;
2404 kvm_set_apic_base(&vmx->vcpu, msr);
2405
2406 fx_init(&vmx->vcpu);
2407
5706be0d 2408 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2409 /*
2410 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2411 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2412 */
c5af89b6 2413 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2414 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2415 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2416 } else {
ad312c7c
ZX		 2417 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2418 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2419 }
e00c8cf2
AK		 2420
2421 seg_setup(VCPU_SREG_DS);
2422 seg_setup(VCPU_SREG_ES);
2423 seg_setup(VCPU_SREG_FS);
2424 seg_setup(VCPU_SREG_GS);
2425 seg_setup(VCPU_SREG_SS);
2426
2427 vmcs_write16(GUEST_TR_SELECTOR, 0);
2428 vmcs_writel(GUEST_TR_BASE, 0);
2429 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2430 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2431
2432 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2433 vmcs_writel(GUEST_LDTR_BASE, 0);
2434 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2435 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2436
2437 vmcs_write32(GUEST_SYSENTER_CS, 0);
2438 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2439 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2440
2441 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2442 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2443 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2444 else
5fdbf976
MT		 2445 kvm_rip_write(vcpu, 0);
2446 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2447
e00c8cf2
AK		 2448 vmcs_writel(GUEST_DR7, 0x400);
2449
2450 vmcs_writel(GUEST_GDTR_BASE, 0);
2451 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2452
2453 vmcs_writel(GUEST_IDTR_BASE, 0);
2454 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2455
2456 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2457 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2458 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2459
e00c8cf2
AK		 2460 /* Special registers */
2461 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2462
2463 setup_msrs(vmx);
2464
6aa8b732
AK		 2465 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2466
f78e0e2e
SY		 2467 if (cpu_has_vmx_tpr_shadow()) {
2468 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2469 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2470 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2471 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2472 vmcs_write32(TPR_THRESHOLD, 0);
2473 }
2474
2475 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2476 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2477 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2478
2384d2b3
SY		 2479 if (vmx->vpid != 0)
2480 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2481
ad312c7c
ZX		 2482 vmx->vcpu.arch.cr0 = 0x60000010;
2483 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2484 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2485 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2486 vmx_fpu_activate(&vmx->vcpu);
2487 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2488
2384d2b3
SY		 2489 vpid_sync_vcpu_all(vmx);
2490
3200f405 2491 ret = 0;
6aa8b732 2492
a89a8fb9
MG		 2493 /* HACK: Don't enable emulation on guest boot/reset */
2494 vmx->emulation_required = 0;
2495
6aa8b732 2496out:
3200f405 2497 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2498 return ret;
2499}
2500
3b86cd99
JK		 2501static void enable_irq_window(struct kvm_vcpu *vcpu)
2502{
2503 u32 cpu_based_vm_exec_control;
2504
2505 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2506 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2507 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2508}
2509
2510static void enable_nmi_window(struct kvm_vcpu *vcpu)
2511{
2512 u32 cpu_based_vm_exec_control;
2513
2514 if (!cpu_has_virtual_nmis()) {
2515 enable_irq_window(vcpu);
2516 return;
2517 }
2518
2519 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2520 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2521 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2522}
2523
66fd3f7f 2524static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2525{
9c8cba37 2526 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2527 uint32_t intr;
2528 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2529
2714d1d3
FEL		 2530 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2531
fa89a817 2532 ++vcpu->stat.irq_injections;
7ffd92c5 2533 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2534 vmx->rmode.irq.pending = true;
2535 vmx->rmode.irq.vector = irq;
5fdbf976 2536 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2537 if (vcpu->arch.interrupt.soft)
2538 vmx->rmode.irq.rip +=
2539 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2540 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2541 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2542 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2543 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2544 return;
2545 }
66fd3f7f
GN		 2546 intr = irq | INTR_INFO_VALID_MASK;
2547 if (vcpu->arch.interrupt.soft) {
2548 intr |= INTR_TYPE_SOFT_INTR;
2549 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2550 vmx->vcpu.arch.event_exit_inst_len);
2551 } else
2552 intr |= INTR_TYPE_EXT_INTR;
2553 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2554}
2555
f08864b4
SY		 2556static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2557{
66a5a347
JK		 2558 struct vcpu_vmx *vmx = to_vmx(vcpu);
2559
3b86cd99
JK		 2560 if (!cpu_has_virtual_nmis()) {
2561 /*
2562 * Tracking the NMI-blocked state in software is built upon
2563 * finding the next open IRQ window. This, in turn, depends on
2564 * well-behaving guests: They have to keep IRQs disabled at
2565 * least as long as the NMI handler runs. Otherwise we may
2566 * cause NMI nesting, maybe breaking the guest. But as this is
2567 * highly unlikely, we can live with the residual risk.
2568 */
2569 vmx->soft_vnmi_blocked = 1;
2570 vmx->vnmi_blocked_time = 0;
2571 }
2572
487b391d 2573 ++vcpu->stat.nmi_injections;
7ffd92c5 2574 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2575 vmx->rmode.irq.pending = true;
2576 vmx->rmode.irq.vector = NMI_VECTOR;
2577 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2578 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2579 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2580 INTR_INFO_VALID_MASK);
2581 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2582 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2583 return;
2584 }
f08864b4
SY		 2585 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2586 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2587}
2588
c4282df9 2589static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2590{
3b86cd99 2591 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2592 return 0;
33f089ca 2593
c4282df9
GN		 2594 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2595 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2596 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2597}
2598
78646121
GN		 2599static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2600{
c4282df9
GN		 2601 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2602 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2603 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2604}
2605
cbc94022
IE		 2606static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2607{
2608 int ret;
2609 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2610 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2611 .guest_phys_addr = addr,
2612 .memory_size = PAGE_SIZE * 3,
2613 .flags = 0,
2614 };
2615
2616 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2617 if (ret)
2618 return ret;
bfc6d222 2619 kvm->arch.tss_addr = addr;
cbc94022
IE		 2620 return 0;
2621}
2622
6aa8b732
AK		 2623static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2624 int vec, u32 err_code)
2625{
b3f37707
NK		 2626 /*
2627 * Instruction with address size override prefix opcode 0x67
2628 * Cause the #SS fault with 0 error code in VM86 mode.
2629 */
2630 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 2631 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2632 return 1;
77ab6db0
JK		 2633 /*
2634 * Forward all other exceptions that are valid in real mode.
2635 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2636 * the required debugging infrastructure rework.
2637 */
2638 switch (vec) {
77ab6db0 2639 case DB_VECTOR:
d0bfb940
JK		 2640 if (vcpu->guest_debug &
2641 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2642 return 0;
2643 kvm_queue_exception(vcpu, vec);
2644 return 1;
77ab6db0 2645 case BP_VECTOR:
d0bfb940
JK		 2646 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2647 return 0;
2648 /* fall through */
2649 case DE_VECTOR:
77ab6db0
JK		 2650 case OF_VECTOR:
2651 case BR_VECTOR:
2652 case UD_VECTOR:
2653 case DF_VECTOR:
2654 case SS_VECTOR:
2655 case GP_VECTOR:
2656 case MF_VECTOR:
2657 kvm_queue_exception(vcpu, vec);
2658 return 1;
2659 }
6aa8b732
AK		 2660 return 0;
2661}
2662
a0861c02
AK		 2663/*
2664 * Trigger machine check on the host. We assume all the MSRs are already set up
2665 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2666 * We pass a fake environment to the machine check handler because we want
2667 * the guest to be always treated like user space, no matter what context
2668 * it used internally.
2669 */
2670static void kvm_machine_check(void)
2671{
2672#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2673 struct pt_regs regs = {
2674 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2675 .flags = X86_EFLAGS_IF,
2676 };
2677
2678 do_machine_check(&regs, 0);
2679#endif
2680}
2681
2682static int handle_machine_check(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2683{
2684 /* already handled by vcpu_run */
2685 return 1;
2686}
2687
6aa8b732
AK		 2688static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2689{
1155f76a 2690 struct vcpu_vmx *vmx = to_vmx(vcpu);
d0bfb940 2691 u32 intr_info, ex_no, error_code;
42dbaa5a 2692 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2693 u32 vect_info;
2694 enum emulation_result er;
2695
1155f76a 2696 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2697 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2698
a0861c02
AK		 2699 if (is_machine_check(intr_info))
2700 return handle_machine_check(vcpu, kvm_run);
2701
6aa8b732 2702 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 2703 !is_page_fault(intr_info))
6aa8b732 2704 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 2705 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 2706
e4a41889 2707 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2708 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2709
2710 if (is_no_device(intr_info)) {
5fd86fcf 2711 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2712 return 1;
2713 }
2714
7aa81cc0 2715 if (is_invalid_opcode(intr_info)) {
571008da 2716 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2717 if (er != EMULATE_DONE)
7ee5d940 2718 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2719 return 1;
2720 }
2721
6aa8b732 2722 error_code = 0;
5fdbf976 2723 rip = kvm_rip_read(vcpu);
2e11384c 2724 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2725 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2726 if (is_page_fault(intr_info)) {
1439442c 2727 /* EPT won't cause page fault directly */
089d034e 2728 if (enable_ept)
1439442c 2729 BUG();
6aa8b732 2730 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2714d1d3
FEL		 2731 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2732 (u32)((u64)cr2 >> 32), handler);
3298b75c 2733 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2734 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2735 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2736 }
2737
7ffd92c5 2738 if (vmx->rmode.vm86_active &&
6aa8b732 2739 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2740 error_code)) {
ad312c7c
ZX		 2741 if (vcpu->arch.halt_request) {
2742 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2743 return kvm_emulate_halt(vcpu);
2744 }
6aa8b732 2745 return 1;
72d6e5a0 2746 }
6aa8b732 2747
d0bfb940 2748 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2749 switch (ex_no) {
2750 case DB_VECTOR:
2751 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2752 if (!(vcpu->guest_debug &
2753 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2754 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2755 kvm_queue_exception(vcpu, DB_VECTOR);
2756 return 1;
2757 }
2758 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2759 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2760 /* fall through */
2761 case BP_VECTOR:
6aa8b732 2762 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2763 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2764 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2765 break;
2766 default:
d0bfb940
JK		 2767 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2768 kvm_run->ex.exception = ex_no;
2769 kvm_run->ex.error_code = error_code;
42dbaa5a 2770 break;
6aa8b732 2771 }
6aa8b732
AK		 2772 return 0;
2773}
2774
2775static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2776 struct kvm_run *kvm_run)
2777{
1165f5fe 2778 ++vcpu->stat.irq_exits;
2714d1d3 2779 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
6aa8b732
AK		 2780 return 1;
2781}
2782
988ad74f
AK		 2783static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2784{
2785 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2786 return 0;
2787}
6aa8b732 2788
6aa8b732
AK		 2789static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2790{
bfdaab09 2791 unsigned long exit_qualification;
34c33d16 2792 int size, in, string;
039576c0 2793 unsigned port;
6aa8b732 2794
1165f5fe 2795 ++vcpu->stat.io_exits;
bfdaab09 2796 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2797 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2798
2799 if (string) {
3427318f
LV		 2800 if (emulate_instruction(vcpu,
2801 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2802 return 0;
2803 return 1;
2804 }
2805
2806 size = (exit_qualification & 7) + 1;
2807 in = (exit_qualification & 8) != 0;
039576c0 2808 port = exit_qualification >> 16;
e70669ab 2809
e93f36bc 2810 skip_emulated_instruction(vcpu);
3090dd73 2811 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 2812}
2813
102d8325
IM		 2814static void
2815vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2816{
2817 /*
2818 * Patch in the VMCALL instruction:
2819 */
2820 hypercall[0] = 0x0f;
2821 hypercall[1] = 0x01;
2822 hypercall[2] = 0xc1;
102d8325
IM		 2823}
2824
6aa8b732
AK		 2825static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2826{
bfdaab09 2827 unsigned long exit_qualification;
6aa8b732
AK		 2828 int cr;
2829 int reg;
2830
bfdaab09 2831 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2832 cr = exit_qualification & 15;
2833 reg = (exit_qualification >> 8) & 15;
2834 switch ((exit_qualification >> 4) & 3) {
2835 case 0: /* mov to cr */
5fdbf976
MT		 2836 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2837 (u32)kvm_register_read(vcpu, reg),
2838 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2839 handler);
6aa8b732
AK		 2840 switch (cr) {
2841 case 0:
5fdbf976 2842 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2843 skip_emulated_instruction(vcpu);
2844 return 1;
2845 case 3:
5fdbf976 2846 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2847 skip_emulated_instruction(vcpu);
2848 return 1;
2849 case 4:
5fdbf976 2850 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2851 skip_emulated_instruction(vcpu);
2852 return 1;
0a5fff19
GN		 2853 case 8: {
2854 u8 cr8_prev = kvm_get_cr8(vcpu);
2855 u8 cr8 = kvm_register_read(vcpu, reg);
2856 kvm_set_cr8(vcpu, cr8);
2857 skip_emulated_instruction(vcpu);
2858 if (irqchip_in_kernel(vcpu->kvm))
2859 return 1;
2860 if (cr8_prev <= cr8)
2861 return 1;
2862 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2863 return 0;
2864 }
6aa8b732
AK		 2865 };
2866 break;
25c4c276 2867 case 2: /* clts */
5fd86fcf 2868 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2869 vcpu->arch.cr0 &= ~X86_CR0_TS;
2870 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2871 vmx_fpu_activate(vcpu);
2714d1d3 2872 KVMTRACE_0D(CLTS, vcpu, handler);
25c4c276
AL		 2873 skip_emulated_instruction(vcpu);
2874 return 1;
6aa8b732
AK		 2875 case 1: /*mov from cr*/
2876 switch (cr) {
2877 case 3:
5fdbf976 2878 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2714d1d3 2879 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
5fdbf976
MT		 2880 (u32)kvm_register_read(vcpu, reg),
2881 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2714d1d3 2882 handler);
6aa8b732
AK		 2883 skip_emulated_instruction(vcpu);
2884 return 1;
2885 case 8:
5fdbf976 2886 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2714d1d3 2887 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
5fdbf976 2888 (u32)kvm_register_read(vcpu, reg), handler);
6aa8b732
AK		 2889 skip_emulated_instruction(vcpu);
2890 return 1;
2891 }
2892 break;
2893 case 3: /* lmsw */
2d3ad1f4 2894 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2895
2896 skip_emulated_instruction(vcpu);
2897 return 1;
2898 default:
2899 break;
2900 }
2901 kvm_run->exit_reason = 0;
f0242478 2902 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2903 (int)(exit_qualification >> 4) & 3, cr);
2904 return 0;
2905}
2906
2907static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2908{
bfdaab09 2909 unsigned long exit_qualification;
6aa8b732
AK		 2910 unsigned long val;
2911 int dr, reg;
2912
42dbaa5a
JK		 2913 dr = vmcs_readl(GUEST_DR7);
2914 if (dr & DR7_GD) {
2915 /*
2916 * As the vm-exit takes precedence over the debug trap, we
2917 * need to emulate the latter, either for the host or the
2918 * guest debugging itself.
2919 */
2920 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2921 kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2922 kvm_run->debug.arch.dr7 = dr;
2923 kvm_run->debug.arch.pc =
2924 vmcs_readl(GUEST_CS_BASE) +
2925 vmcs_readl(GUEST_RIP);
2926 kvm_run->debug.arch.exception = DB_VECTOR;
2927 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2928 return 0;
2929 } else {
2930 vcpu->arch.dr7 &= ~DR7_GD;
2931 vcpu->arch.dr6 |= DR6_BD;
2932 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2933 kvm_queue_exception(vcpu, DB_VECTOR);
2934 return 1;
2935 }
2936 }
2937
bfdaab09 2938 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 2939 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2940 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2941 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 2942 switch (dr) {
42dbaa5a
JK		 2943 case 0 ... 3:
2944 val = vcpu->arch.db[dr];
2945 break;
6aa8b732 2946 case 6:
42dbaa5a 2947 val = vcpu->arch.dr6;
6aa8b732
AK		 2948 break;
2949 case 7:
42dbaa5a 2950 val = vcpu->arch.dr7;
6aa8b732
AK		 2951 break;
2952 default:
2953 val = 0;
2954 }
5fdbf976 2955 kvm_register_write(vcpu, reg, val);
2714d1d3 2956 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
6aa8b732 2957 } else {
42dbaa5a
JK		 2958 val = vcpu->arch.regs[reg];
2959 switch (dr) {
2960 case 0 ... 3:
2961 vcpu->arch.db[dr] = val;
2962 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2963 vcpu->arch.eff_db[dr] = val;
2964 break;
2965 case 4 ... 5:
2966 if (vcpu->arch.cr4 & X86_CR4_DE)
2967 kvm_queue_exception(vcpu, UD_VECTOR);
2968 break;
2969 case 6:
2970 if (val & 0xffffffff00000000ULL) {
2971 kvm_queue_exception(vcpu, GP_VECTOR);
2972 break;
2973 }
2974 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2975 break;
2976 case 7:
2977 if (val & 0xffffffff00000000ULL) {
2978 kvm_queue_exception(vcpu, GP_VECTOR);
2979 break;
2980 }
2981 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2982 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2983 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2984 vcpu->arch.switch_db_regs =
2985 (val & DR7_BP_EN_MASK);
2986 }
2987 break;
2988 }
2989 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
6aa8b732 2990 }
6aa8b732
AK		 2991 skip_emulated_instruction(vcpu);
2992 return 1;
2993}
2994
2995static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2996{
06465c5a
AK		 2997 kvm_emulate_cpuid(vcpu);
2998 return 1;
6aa8b732
AK		 2999}
3000
3001static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3002{
ad312c7c 3003 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3004 u64 data;
3005
3006 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 3007 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3008 return 1;
3009 }
3010
2714d1d3
FEL		 3011 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
3012 handler);
3013
6aa8b732 3014 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3015 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3016 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3017 skip_emulated_instruction(vcpu);
3018 return 1;
3019}
3020
3021static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3022{
ad312c7c
ZX		 3023 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3024 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3025 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 3026
2714d1d3
FEL		 3027 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
3028 handler);
3029
6aa8b732 3030 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 3031 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3032 return 1;
3033 }
3034
3035 skip_emulated_instruction(vcpu);
3036 return 1;
3037}
3038
6e5d865c
YS		 3039static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
3040 struct kvm_run *kvm_run)
3041{
3042 return 1;
3043}
3044
6aa8b732
AK		 3045static int handle_interrupt_window(struct kvm_vcpu *vcpu,
3046 struct kvm_run *kvm_run)
3047{
85f455f7
ED		 3048 u32 cpu_based_vm_exec_control;
3049
3050 /* clear pending irq */
3051 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3052 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3053 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3
FEL		 3054
3055 KVMTRACE_0D(PEND_INTR, vcpu, handler);
a26bf12a 3056 ++vcpu->stat.irq_window_exits;
2714d1d3 3057
c1150d8c
DL		 3058 /*
3059 * If the user space waits to inject interrupts, exit as soon as
3060 * possible
3061 */
8061823a
GN		 3062 if (!irqchip_in_kernel(vcpu->kvm) &&
3063 kvm_run->request_interrupt_window &&
3064 !kvm_cpu_has_interrupt(vcpu)) {
c1150d8c 3065 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3066 return 0;
3067 }
6aa8b732
AK		 3068 return 1;
3069}
3070
3071static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3072{
3073 skip_emulated_instruction(vcpu);
d3bef15f 3074 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3075}
3076
c21415e8
IM		 3077static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3078{
510043da 3079 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3080 kvm_emulate_hypercall(vcpu);
3081 return 1;
c21415e8
IM		 3082}
3083
e3c7cb6a
AK		 3084static int handle_vmx_insn(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3085{
3086 kvm_queue_exception(vcpu, UD_VECTOR);
3087 return 1;
3088}
3089
a7052897
MT		 3090static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3091{
f9c617f6 3092 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3093
3094 kvm_mmu_invlpg(vcpu, exit_qualification);
3095 skip_emulated_instruction(vcpu);
3096 return 1;
3097}
3098
e5edaa01
ED		 3099static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3100{
3101 skip_emulated_instruction(vcpu);
3102 /* TODO: Add support for VT-d/pass-through device */
3103 return 1;
3104}
3105
f78e0e2e
SY		 3106static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3107{
f9c617f6 3108 unsigned long exit_qualification;
f78e0e2e
SY		 3109 enum emulation_result er;
3110 unsigned long offset;
3111
f9c617f6 3112 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 3113 offset = exit_qualification & 0xffful;
3114
3115 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3116
3117 if (er != EMULATE_DONE) {
3118 printk(KERN_ERR
3119 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3120 offset);
3121 return -ENOTSUPP;
3122 }
3123 return 1;
3124}
3125
37817f29
IE		 3126static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3127{
60637aac 3128 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 3129 unsigned long exit_qualification;
3130 u16 tss_selector;
64a7ec06
GN		 3131 int reason, type, idt_v;
3132
3133 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3134 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3135
3136 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3137
3138 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3139 if (reason == TASK_SWITCH_GATE && idt_v) {
3140 switch (type) {
3141 case INTR_TYPE_NMI_INTR:
3142 vcpu->arch.nmi_injected = false;
3143 if (cpu_has_virtual_nmis())
3144 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3145 GUEST_INTR_STATE_NMI);
3146 break;
3147 case INTR_TYPE_EXT_INTR:
66fd3f7f 3148 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3149 kvm_clear_interrupt_queue(vcpu);
3150 break;
3151 case INTR_TYPE_HARD_EXCEPTION:
3152 case INTR_TYPE_SOFT_EXCEPTION:
3153 kvm_clear_exception_queue(vcpu);
3154 break;
3155 default:
3156 break;
3157 }
60637aac 3158 }
37817f29
IE		 3159 tss_selector = exit_qualification;
3160
64a7ec06
GN		 3161 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3162 type != INTR_TYPE_EXT_INTR &&
3163 type != INTR_TYPE_NMI_INTR))
3164 skip_emulated_instruction(vcpu);
3165
42dbaa5a
JK		 3166 if (!kvm_task_switch(vcpu, tss_selector, reason))
3167 return 0;
3168
3169 /* clear all local breakpoint enable flags */
3170 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3171
3172 /*
3173 * TODO: What about debug traps on tss switch?
3174 * Are we supposed to inject them and update dr6?
3175 */
3176
3177 return 1;
37817f29
IE		 3178}
3179
1439442c
SY		 3180static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3181{
f9c617f6 3182 unsigned long exit_qualification;
1439442c 3183 gpa_t gpa;
1439442c 3184 int gla_validity;
1439442c 3185
f9c617f6 3186 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3187
3188 if (exit_qualification & (1 << 6)) {
3189 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3190 return -ENOTSUPP;
3191 }
3192
3193 gla_validity = (exit_qualification >> 7) & 0x3;
3194 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3195 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3196 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3197 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3198 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3199 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3200 (long unsigned int)exit_qualification);
3201 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
596ae895
AK		 3202 kvm_run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3203 return 0;
1439442c
SY		 3204 }
3205
3206 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
49cd7d22 3207 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3208}
3209
f08864b4
SY		 3210static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3211{
3212 u32 cpu_based_vm_exec_control;
3213
3214 /* clear pending NMI */
3215 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3216 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3217 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3218 ++vcpu->stat.nmi_window_exits;
3219
3220 return 1;
3221}
3222
ea953ef0
MG		 3223static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3224 struct kvm_run *kvm_run)
3225{
8b3079a5
AK		 3226 struct vcpu_vmx *vmx = to_vmx(vcpu);
3227 enum emulation_result err = EMULATE_DONE;
ea953ef0 3228
ea953ef0 3229 local_irq_enable();
34f0c1ad 3230 preempt_enable();
ea953ef0
MG		 3231
3232 while (!guest_state_valid(vcpu)) {
3233 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3234
1d5a4d9b
GT		 3235 if (err == EMULATE_DO_MMIO)
3236 break;
3237
3238 if (err != EMULATE_DONE) {
3239 kvm_report_emulation_failure(vcpu, "emulation failure");
263799a3 3240 break;
ea953ef0
MG		 3241 }
3242
3243 if (signal_pending(current))
3244 break;
3245 if (need_resched())
3246 schedule();
3247 }
3248
ea953ef0 3249 preempt_disable();
34f0c1ad 3250 local_irq_disable();
8b3079a5
AK		 3251
3252 vmx->invalid_state_emulation_result = err;
ea953ef0
MG		 3253}
3254
6aa8b732
AK		 3255/*
3256 * The exit handlers return 1 if the exit was handled fully and guest execution
3257 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3258 * to be done to userspace and return 0.
3259 */
3260static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3261 struct kvm_run *kvm_run) = {
3262 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3263 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3264 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3265 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3266 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3267 [EXIT_REASON_CR_ACCESS] = handle_cr,
3268 [EXIT_REASON_DR_ACCESS] = handle_dr,
3269 [EXIT_REASON_CPUID] = handle_cpuid,
3270 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3271 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3272 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3273 [EXIT_REASON_HLT] = handle_halt,
a7052897 3274 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3275 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3276 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3277 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3278 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3279 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3280 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3281 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3282 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3283 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3284 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3285 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3286 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3287 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3288 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
1439442c 3289 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
a0861c02 3290 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
6aa8b732
AK		 3291};
3292
3293static const int kvm_vmx_max_exit_handlers =
50a3485c 3294 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3295
3296/*
3297 * The guest has exited. See if we can fix it or if we need userspace
3298 * assistance.
3299 */
6062d012 3300static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 3301{
29bd8a78 3302 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3303 u32 exit_reason = vmx->exit_reason;
1155f76a 3304 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3305
5fdbf976
MT		 3306 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3307 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
2714d1d3 3308
1d5a4d9b
GT		 3309 /* If we need to emulate an MMIO from handle_invalid_guest_state
3310 * we just return 0 */
10f32d84
AK		 3311 if (vmx->emulation_required && emulate_invalid_guest_state) {
3312 if (guest_state_valid(vcpu))
3313 vmx->emulation_required = 0;
8b3079a5 3314 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
10f32d84 3315 }
1d5a4d9b 3316
1439442c
SY		 3317 /* Access CR3 don't cause VMExit in paging mode, so we need
3318 * to sync with guest real CR3. */
6de4f3ad 3319 if (enable_ept && is_paging(vcpu))
1439442c 3320 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3321
29bd8a78
AK		 3322 if (unlikely(vmx->fail)) {
3323 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3324 kvm_run->fail_entry.hardware_entry_failure_reason
3325 = vmcs_read32(VM_INSTRUCTION_ERROR);
3326 return 0;
3327 }
6aa8b732 3328
d77c26fc 3329 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3330 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3331 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3332 exit_reason != EXIT_REASON_TASK_SWITCH))
3333 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3334 "(0x%x) and exit reason is 0x%x\n",
3335 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3336
3337 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3338 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3339 vmx->soft_vnmi_blocked = 0;
3b86cd99 3340 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3341 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3342 /*
3343 * This CPU don't support us in finding the end of an
3344 * NMI-blocked window if the guest runs with IRQs
3345 * disabled. So we pull the trigger after 1 s of
3346 * futile waiting, but inform the user about this.
3347 */
3348 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3349 "state on VCPU %d after 1 s timeout\n",
3350 __func__, vcpu->vcpu_id);
3351 vmx->soft_vnmi_blocked = 0;
3b86cd99 3352 }
3b86cd99
JK		 3353 }
3354
6aa8b732
AK		 3355 if (exit_reason < kvm_vmx_max_exit_handlers
3356 && kvm_vmx_exit_handlers[exit_reason])
3357 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3358 else {
3359 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3360 kvm_run->hw.hardware_exit_reason = exit_reason;
3361 }
3362 return 0;
3363}
3364
95ba8273 3365static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3366{
95ba8273 3367 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3368 vmcs_write32(TPR_THRESHOLD, 0);
3369 return;
3370 }
3371
95ba8273 3372 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3373}
3374
cf393f75
AK		 3375static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3376{
3377 u32 exit_intr_info;
7b4a25cb 3378 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3379 bool unblock_nmi;
3380 u8 vector;
668f612f
AK		 3381 int type;
3382 bool idtv_info_valid;
cf393f75
AK		 3383
3384 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3385
a0861c02
AK		 3386 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3387
3388 /* Handle machine checks before interrupts are enabled */
3389 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3390 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3391 && is_machine_check(exit_intr_info)))
3392 kvm_machine_check();
3393
20f65983
GN		 3394 /* We need to handle NMIs before interrupts are enabled */
3395 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3396 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3397 KVMTRACE_0D(NMI, &vmx->vcpu, handler);
3398 asm("int $2");
3399 }
3400
3401 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3402
cf393f75
AK		 3403 if (cpu_has_virtual_nmis()) {
3404 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3405 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3406 /*
7b4a25cb 3407 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3408 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3409 * a guest IRET fault.
7b4a25cb
GN		 3410 * SDM 3: 23.2.2 (September 2008)
3411 * Bit 12 is undefined in any of the following cases:
3412 * If the VM exit sets the valid bit in the IDT-vectoring
3413 * information field.
3414 * If the VM exit is due to a double fault.
cf393f75 3415 */
7b4a25cb
GN		 3416 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3417 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3418 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3419 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3420 } else if (unlikely(vmx->soft_vnmi_blocked))
3421 vmx->vnmi_blocked_time +=
3422 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3423
37b96e98
GN		 3424 vmx->vcpu.arch.nmi_injected = false;
3425 kvm_clear_exception_queue(&vmx->vcpu);
3426 kvm_clear_interrupt_queue(&vmx->vcpu);
3427
3428 if (!idtv_info_valid)
3429 return;
3430
668f612f
AK		 3431 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3432 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3433
64a7ec06 3434 switch (type) {
37b96e98
GN		 3435 case INTR_TYPE_NMI_INTR:
3436 vmx->vcpu.arch.nmi_injected = true;
668f612f 3437 /*
7b4a25cb 3438 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3439 * Clear bit "block by NMI" before VM entry if a NMI
3440 * delivery faulted.
668f612f 3441 */
37b96e98
GN		 3442 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3443 GUEST_INTR_STATE_NMI);
3444 break;
37b96e98 3445 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3446 vmx->vcpu.arch.event_exit_inst_len =
3447 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3448 /* fall through */
3449 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3450 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3451 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3452 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3453 } else
3454 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3455 break;
66fd3f7f
GN		 3456 case INTR_TYPE_SOFT_INTR:
3457 vmx->vcpu.arch.event_exit_inst_len =
3458 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3459 /* fall through */
37b96e98 3460 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3461 kvm_queue_interrupt(&vmx->vcpu, vector,
3462 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3463 break;
3464 default:
3465 break;
f7d9238f 3466 }
cf393f75
AK		 3467}
3468
9c8cba37
AK		 3469/*
3470 * Failure to inject an interrupt should give us the information
3471 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3472 * when fetching the interrupt redirection bitmap in the real-mode
3473 * tss, this doesn't happen. So we do it ourselves.
3474 */
3475static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3476{
3477 vmx->rmode.irq.pending = 0;
5fdbf976 3478 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3479 return;
5fdbf976 3480 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3481 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3482 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3483 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3484 return;
3485 }
3486 vmx->idt_vectoring_info =
3487 VECTORING_INFO_VALID_MASK
3488 | INTR_TYPE_EXT_INTR
3489 | vmx->rmode.irq.vector;
3490}
3491
c801949d
AK		 3492#ifdef CONFIG_X86_64
3493#define R "r"
3494#define Q "q"
3495#else
3496#define R "e"
3497#define Q "l"
3498#endif
3499
04d2cc77 3500static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 3501{
a2fa3e9f 3502 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3503
8f5d549f
AK		 3504 if (enable_ept && is_paging(vcpu)) {
3505 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3506 ept_load_pdptrs(vcpu);
3507 }
3b86cd99
JK		 3508 /* Record the guest's net vcpu time for enforced NMI injections. */
3509 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3510 vmx->entry_time = ktime_get();
3511
a89a8fb9
MG		 3512 /* Handle invalid guest state instead of entering VMX */
3513 if (vmx->emulation_required && emulate_invalid_guest_state) {
3514 handle_invalid_guest_state(vcpu, kvm_run);
3515 return;
3516 }
3517
5fdbf976
MT		 3518 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3519 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3520 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3521 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3522
787ff736
GN		 3523 /* When single-stepping over STI and MOV SS, we must clear the
3524 * corresponding interruptibility bits in the guest state. Otherwise
3525 * vmentry fails as it then expects bit 14 (BS) in pending debug
3526 * exceptions being set, but that's not correct for the guest debugging
3527 * case. */
3528 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3529 vmx_set_interrupt_shadow(vcpu, 0);
3530
e6adf283
AK		 3531 /*
3532 * Loading guest fpu may have cleared host cr0.ts
3533 */
3534 vmcs_writel(HOST_CR0, read_cr0());
3535
42dbaa5a
JK		 3536 set_debugreg(vcpu->arch.dr6, 6);
3537
d77c26fc 3538 asm(
6aa8b732 3539 /* Store host registers */
c801949d
AK		 3540 "push %%"R"dx; push %%"R"bp;"
3541 "push %%"R"cx \n\t"
313dbd49
AK		 3542 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3543 "je 1f \n\t"
3544 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3545 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3546 "1: \n\t"
6aa8b732 3547 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3548 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3549 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3550 "mov %c[cr2](%0), %%"R"ax \n\t"
3551 "mov %%"R"ax, %%cr2 \n\t"
3552 "mov %c[rax](%0), %%"R"ax \n\t"
3553 "mov %c[rbx](%0), %%"R"bx \n\t"
3554 "mov %c[rdx](%0), %%"R"dx \n\t"
3555 "mov %c[rsi](%0), %%"R"si \n\t"
3556 "mov %c[rdi](%0), %%"R"di \n\t"
3557 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3558#ifdef CONFIG_X86_64
e08aa78a
AK		 3559 "mov %c[r8](%0), %%r8 \n\t"
3560 "mov %c[r9](%0), %%r9 \n\t"
3561 "mov %c[r10](%0), %%r10 \n\t"
3562 "mov %c[r11](%0), %%r11 \n\t"
3563 "mov %c[r12](%0), %%r12 \n\t"
3564 "mov %c[r13](%0), %%r13 \n\t"
3565 "mov %c[r14](%0), %%r14 \n\t"
3566 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3567#endif
c801949d
AK		 3568 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3569
6aa8b732 3570 /* Enter guest mode */
cd2276a7 3571 "jne .Llaunched \n\t"
4ecac3fd 3572 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3573 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3574 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3575 ".Lkvm_vmx_return: "
6aa8b732 3576 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3577 "xchg %0, (%%"R"sp) \n\t"
3578 "mov %%"R"ax, %c[rax](%0) \n\t"
3579 "mov %%"R"bx, %c[rbx](%0) \n\t"
3580 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3581 "mov %%"R"dx, %c[rdx](%0) \n\t"
3582 "mov %%"R"si, %c[rsi](%0) \n\t"
3583 "mov %%"R"di, %c[rdi](%0) \n\t"
3584 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3585#ifdef CONFIG_X86_64
e08aa78a
AK		 3586 "mov %%r8, %c[r8](%0) \n\t"
3587 "mov %%r9, %c[r9](%0) \n\t"
3588 "mov %%r10, %c[r10](%0) \n\t"
3589 "mov %%r11, %c[r11](%0) \n\t"
3590 "mov %%r12, %c[r12](%0) \n\t"
3591 "mov %%r13, %c[r13](%0) \n\t"
3592 "mov %%r14, %c[r14](%0) \n\t"
3593 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3594#endif
c801949d
AK		 3595 "mov %%cr2, %%"R"ax \n\t"
3596 "mov %%"R"ax, %c[cr2](%0) \n\t"
3597
3598 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3599 "setbe %c[fail](%0) \n\t"
3600 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3601 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3602 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3603 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3604 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3605 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3606 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3607 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3608 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3609 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3610 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3611#ifdef CONFIG_X86_64
ad312c7c
ZX		 3612 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3613 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3614 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3615 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3616 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3617 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3618 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3619 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3620#endif
ad312c7c 3621 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3622 : "cc", "memory"
c801949d 3623 , R"bx", R"di", R"si"
c2036300 3624#ifdef CONFIG_X86_64
c2036300
LV		 3625 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3626#endif
3627 );
6aa8b732 3628
6de4f3ad
AK		 3629 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3630 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3631 vcpu->arch.regs_dirty = 0;
3632
42dbaa5a
JK		 3633 get_debugreg(vcpu->arch.dr6, 6);
3634
1155f76a 3635 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3636 if (vmx->rmode.irq.pending)
3637 fixup_rmode_irq(vmx);
1155f76a 3638
d77c26fc 3639 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3640 vmx->launched = 1;
1b6269db 3641
cf393f75 3642 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3643}
3644
c801949d
AK		 3645#undef R
3646#undef Q
3647
6aa8b732
AK		 3648static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3649{
a2fa3e9f
GH		 3650 struct vcpu_vmx *vmx = to_vmx(vcpu);
3651
3652 if (vmx->vmcs) {
543e4243 3653 vcpu_clear(vmx);
a2fa3e9f
GH		 3654 free_vmcs(vmx->vmcs);
3655 vmx->vmcs = NULL;
6aa8b732
AK		 3656 }
3657}
3658
3659static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3660{
fb3f0f51
RR		 3661 struct vcpu_vmx *vmx = to_vmx(vcpu);
3662
2384d2b3
SY		 3663 spin_lock(&vmx_vpid_lock);
3664 if (vmx->vpid != 0)
3665 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3666 spin_unlock(&vmx_vpid_lock);
6aa8b732 3667 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3668 kfree(vmx->host_msrs);
3669 kfree(vmx->guest_msrs);
3670 kvm_vcpu_uninit(vcpu);
a4770347 3671 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3672}
3673
fb3f0f51 3674static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3675{
fb3f0f51 3676 int err;
c16f862d 3677 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3678 int cpu;
6aa8b732 3679
a2fa3e9f 3680 if (!vmx)
fb3f0f51
RR		 3681 return ERR_PTR(-ENOMEM);
3682
2384d2b3
SY		 3683 allocate_vpid(vmx);
3684
fb3f0f51
RR		 3685 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3686 if (err)
3687 goto free_vcpu;
965b58a5 3688
a2fa3e9f 3689 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3690 if (!vmx->guest_msrs) {
3691 err = -ENOMEM;
3692 goto uninit_vcpu;
3693 }
965b58a5 3694
a2fa3e9f
GH		 3695 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3696 if (!vmx->host_msrs)
fb3f0f51 3697 goto free_guest_msrs;
965b58a5 3698
a2fa3e9f
GH		 3699 vmx->vmcs = alloc_vmcs();
3700 if (!vmx->vmcs)
fb3f0f51 3701 goto free_msrs;
a2fa3e9f
GH		 3702
3703 vmcs_clear(vmx->vmcs);
3704
15ad7146
AK		 3705 cpu = get_cpu();
3706 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3707 err = vmx_vcpu_setup(vmx);
fb3f0f51 3708 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3709 put_cpu();
fb3f0f51
RR		 3710 if (err)
3711 goto free_vmcs;
5e4a0b3c
MT		 3712 if (vm_need_virtualize_apic_accesses(kvm))
3713 if (alloc_apic_access_page(kvm) != 0)
3714 goto free_vmcs;
fb3f0f51 3715
089d034e 3716 if (enable_ept)
b7ebfb05
SY		 3717 if (alloc_identity_pagetable(kvm) != 0)
3718 goto free_vmcs;
3719
fb3f0f51
RR		 3720 return &vmx->vcpu;
3721
3722free_vmcs:
3723 free_vmcs(vmx->vmcs);
3724free_msrs:
3725 kfree(vmx->host_msrs);
3726free_guest_msrs:
3727 kfree(vmx->guest_msrs);
3728uninit_vcpu:
3729 kvm_vcpu_uninit(&vmx->vcpu);
3730free_vcpu:
a4770347 3731 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3732 return ERR_PTR(err);
6aa8b732
AK		 3733}
3734
002c7f7c
YS		 3735static void __init vmx_check_processor_compat(void *rtn)
3736{
3737 struct vmcs_config vmcs_conf;
3738
3739 *(int *)rtn = 0;
3740 if (setup_vmcs_config(&vmcs_conf) < 0)
3741 *(int *)rtn = -EIO;
3742 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3743 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3744 smp_processor_id());
3745 *(int *)rtn = -EIO;
3746 }
3747}
3748
67253af5
SY		 3749static int get_ept_level(void)
3750{
3751 return VMX_EPT_DEFAULT_GAW + 1;
3752}
3753
4b12f0de 3754static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 3755{
4b12f0de
SY		 3756 u64 ret;
3757
522c68c4
SY		 3758 /* For VT-d and EPT combination
3759 * 1. MMIO: always map as UC
3760 * 2. EPT with VT-d:
3761 * a. VT-d without snooping control feature: can't guarantee the
3762 * result, try to trust guest.
3763 * b. VT-d with snooping control feature: snooping control feature of
3764 * VT-d engine can guarantee the cache correctness. Just set it
3765 * to WB to keep consistent with host. So the same as item 3.
3766 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3767 * consistent with host MTRR
3768 */
4b12f0de
SY		 3769 if (is_mmio)
3770 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 3771 else if (vcpu->kvm->arch.iommu_domain &&
3772 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3773 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3774 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 3775 else
522c68c4
SY		 3776 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3777 | VMX_EPT_IGMT_BIT;
4b12f0de
SY		 3778
3779 return ret;
64d4d521
SY		 3780}
3781
cbdd1bea 3782static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3783 .cpu_has_kvm_support = cpu_has_kvm_support,
3784 .disabled_by_bios = vmx_disabled_by_bios,
3785 .hardware_setup = hardware_setup,
3786 .hardware_unsetup = hardware_unsetup,
002c7f7c 3787 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3788 .hardware_enable = hardware_enable,
3789 .hardware_disable = hardware_disable,
04547156 3790 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 3791
3792 .vcpu_create = vmx_create_vcpu,
3793 .vcpu_free = vmx_free_vcpu,
04d2cc77 3794 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3795
04d2cc77 3796 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3797 .vcpu_load = vmx_vcpu_load,
3798 .vcpu_put = vmx_vcpu_put,
3799
3800 .set_guest_debug = set_guest_debug,
3801 .get_msr = vmx_get_msr,
3802 .set_msr = vmx_set_msr,
3803 .get_segment_base = vmx_get_segment_base,
3804 .get_segment = vmx_get_segment,
3805 .set_segment = vmx_set_segment,
2e4d2653 3806 .get_cpl = vmx_get_cpl,
6aa8b732 3807 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3808 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3809 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3810 .set_cr3 = vmx_set_cr3,
3811 .set_cr4 = vmx_set_cr4,
6aa8b732 3812 .set_efer = vmx_set_efer,
6aa8b732
AK		 3813 .get_idt = vmx_get_idt,
3814 .set_idt = vmx_set_idt,
3815 .get_gdt = vmx_get_gdt,
3816 .set_gdt = vmx_set_gdt,
5fdbf976 3817 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 3818 .get_rflags = vmx_get_rflags,
3819 .set_rflags = vmx_set_rflags,
3820
3821 .tlb_flush = vmx_flush_tlb,
6aa8b732 3822
6aa8b732 3823 .run = vmx_vcpu_run,
6062d012 3824 .handle_exit = vmx_handle_exit,
6aa8b732 3825 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3826 .set_interrupt_shadow = vmx_set_interrupt_shadow,
3827 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 3828 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 3829 .set_irq = vmx_inject_irq,
95ba8273 3830 .set_nmi = vmx_inject_nmi,
298101da 3831 .queue_exception = vmx_queue_exception,
78646121 3832 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273
GN		 3833 .nmi_allowed = vmx_nmi_allowed,
3834 .enable_nmi_window = enable_nmi_window,
3835 .enable_irq_window = enable_irq_window,
3836 .update_cr8_intercept = update_cr8_intercept,
95ba8273 3837
cbc94022 3838 .set_tss_addr = vmx_set_tss_addr,
67253af5 3839 .get_tdp_level = get_ept_level,
4b12f0de 3840 .get_mt_mask = vmx_get_mt_mask,
6aa8b732
AK		 3841};
3842
3843static int __init vmx_init(void)
3844{
fdef3ad1
HQ		 3845 int r;
3846
3e7c73e9 3847 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 3848 if (!vmx_io_bitmap_a)
3849 return -ENOMEM;
3850
3e7c73e9 3851 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 3852 if (!vmx_io_bitmap_b) {
3853 r = -ENOMEM;
3854 goto out;
3855 }
3856
5897297b
AK		 3857 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3858 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 3859 r = -ENOMEM;
3860 goto out1;
3861 }
3862
5897297b
AK		 3863 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
3864 if (!vmx_msr_bitmap_longmode) {
3865 r = -ENOMEM;
3866 goto out2;
3867 }
3868
fdef3ad1
HQ		 3869 /*
3870 * Allow direct access to the PC debug port (it is often used for I/O
3871 * delays, but the vmexits simply slow things down).
3872 */
3e7c73e9
AK		 3873 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
3874 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 3875
3e7c73e9 3876 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 3877
5897297b
AK		 3878 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
3879 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 3880
2384d2b3
SY		 3881 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3882
cb498ea2 3883 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 3884 if (r)
5897297b 3885 goto out3;
25c5f225 3886
5897297b
AK		 3887 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
3888 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
3889 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
3890 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
3891 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
3892 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 3893
089d034e 3894 if (enable_ept) {
1439442c 3895 bypass_guest_pf = 0;
5fdbcb9d 3896 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 3897 VMX_EPT_WRITABLE_MASK);
534e38b4 3898 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 3899 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 3900 kvm_enable_tdp();
3901 } else
3902 kvm_disable_tdp();
1439442c 3903
c7addb90
AK		 3904 if (bypass_guest_pf)
3905 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3906
1439442c
SY		 3907 ept_sync_global();
3908
fdef3ad1
HQ		 3909 return 0;
3910
5897297b
AK		 3911out3:
3912 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 3913out2:
5897297b 3914 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 3915out1:
3e7c73e9 3916 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 3917out:
3e7c73e9 3918 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 3919 return r;
6aa8b732
AK		 3920}
3921
3922static void __exit vmx_exit(void)
3923{
5897297b
AK		 3924 free_page((unsigned long)vmx_msr_bitmap_legacy);
3925 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 3926 free_page((unsigned long)vmx_io_bitmap_b);
3927 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 3928
cb498ea2 3929 kvm_exit();
6aa8b732
AK		 3930}
3931
3932module_init(vmx_init)
3933module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)