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KVM: Improve MTRR structure
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
6aa8b732 19#include "vmx.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
5fdbf976 29#include "kvm_cache_regs.h"
35920a35 30#include "x86.h"
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
6aa8b732 34
4ecac3fd
AK		 35#define __ex(x) __kvm_handle_fault_on_reboot(x)
36
6aa8b732
AK		 37MODULE_AUTHOR("Qumranet");
38MODULE_LICENSE("GPL");
39
c7addb90
AK		 40static int bypass_guest_pf = 1;
41module_param(bypass_guest_pf, bool, 0);
42
2384d2b3
SY		 43static int enable_vpid = 1;
44module_param(enable_vpid, bool, 0);
45
4c9fc8ef
AK		 46static int flexpriority_enabled = 1;
47module_param(flexpriority_enabled, bool, 0);
48
1439442c 49static int enable_ept = 1;
d56f546d
SY		 50module_param(enable_ept, bool, 0);
51
04fa4d32
MG		 52static int emulate_invalid_guest_state = 0;
53module_param(emulate_invalid_guest_state, bool, 0);
54
a2fa3e9f
GH		 55struct vmcs {
56 u32 revision_id;
57 u32 abort;
58 char data[0];
59};
60
61struct vcpu_vmx {
fb3f0f51 62 struct kvm_vcpu vcpu;
543e4243 63 struct list_head local_vcpus_link;
313dbd49 64 unsigned long host_rsp;
a2fa3e9f 65 int launched;
29bd8a78 66 u8 fail;
1155f76a 67 u32 idt_vectoring_info;
a2fa3e9f
GH		 68 struct kvm_msr_entry *guest_msrs;
69 struct kvm_msr_entry *host_msrs;
70 int nmsrs;
71 int save_nmsrs;
72 int msr_offset_efer;
73#ifdef CONFIG_X86_64
74 int msr_offset_kernel_gs_base;
75#endif
76 struct vmcs *vmcs;
77 struct {
78 int loaded;
79 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 80 int gs_ldt_reload_needed;
81 int fs_reload_needed;
51c6cf66 82 int guest_efer_loaded;
d77c26fc 83 } host_state;
9c8cba37
AK		 84 struct {
85 struct {
86 bool pending;
87 u8 vector;
88 unsigned rip;
89 } irq;
90 } rmode;
2384d2b3 91 int vpid;
04fa4d32 92 bool emulation_required;
3b86cd99
JK		 93
94 /* Support for vnmi-less CPUs */
95 int soft_vnmi_blocked;
96 ktime_t entry_time;
97 s64 vnmi_blocked_time;
a2fa3e9f
GH		 98};
99
100static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
101{
fb3f0f51 102 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 103}
104
b7ebfb05 105static int init_rmode(struct kvm *kvm);
4e1096d2 106static u64 construct_eptp(unsigned long root_hpa);
75880a01 107
6aa8b732
AK		 108static DEFINE_PER_CPU(struct vmcs *, vmxarea);
109static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 110static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 111
fdef3ad1
HQ		 112static struct page *vmx_io_bitmap_a;
113static struct page *vmx_io_bitmap_b;
25c5f225 114static struct page *vmx_msr_bitmap;
fdef3ad1 115
2384d2b3
SY		 116static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
117static DEFINE_SPINLOCK(vmx_vpid_lock);
118
1c3d14fe 119static struct vmcs_config {
6aa8b732
AK		 120 int size;
121 int order;
122 u32 revision_id;
1c3d14fe
YS		 123 u32 pin_based_exec_ctrl;
124 u32 cpu_based_exec_ctrl;
f78e0e2e 125 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 126 u32 vmexit_ctrl;
127 u32 vmentry_ctrl;
128} vmcs_config;
6aa8b732 129
d56f546d
SY		 130struct vmx_capability {
131 u32 ept;
132 u32 vpid;
133} vmx_capability;
134
6aa8b732
AK		 135#define VMX_SEGMENT_FIELD(seg) \
136 [VCPU_SREG_##seg] = { \
137 .selector = GUEST_##seg##_SELECTOR, \
138 .base = GUEST_##seg##_BASE, \
139 .limit = GUEST_##seg##_LIMIT, \
140 .ar_bytes = GUEST_##seg##_AR_BYTES, \
141 }
142
143static struct kvm_vmx_segment_field {
144 unsigned selector;
145 unsigned base;
146 unsigned limit;
147 unsigned ar_bytes;
148} kvm_vmx_segment_fields[] = {
149 VMX_SEGMENT_FIELD(CS),
150 VMX_SEGMENT_FIELD(DS),
151 VMX_SEGMENT_FIELD(ES),
152 VMX_SEGMENT_FIELD(FS),
153 VMX_SEGMENT_FIELD(GS),
154 VMX_SEGMENT_FIELD(SS),
155 VMX_SEGMENT_FIELD(TR),
156 VMX_SEGMENT_FIELD(LDTR),
157};
158
4d56c8a7
AK		 159/*
160 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
161 * away by decrementing the array size.
162 */
6aa8b732 163static const u32 vmx_msr_index[] = {
05b3e0c2 164#ifdef CONFIG_X86_64
6aa8b732
AK		 165 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
166#endif
167 MSR_EFER, MSR_K6_STAR,
168};
9d8f549d 169#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 170
a2fa3e9f
GH		 171static void load_msrs(struct kvm_msr_entry *e, int n)
172{
173 int i;
174
175 for (i = 0; i < n; ++i)
176 wrmsrl(e[i].index, e[i].data);
177}
178
179static void save_msrs(struct kvm_msr_entry *e, int n)
180{
181 int i;
182
183 for (i = 0; i < n; ++i)
184 rdmsrl(e[i].index, e[i].data);
185}
186
6aa8b732
AK		 187static inline int is_page_fault(u32 intr_info)
188{
189 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
190 INTR_INFO_VALID_MASK)) ==
191 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
192}
193
2ab455cc
AL		 194static inline int is_no_device(u32 intr_info)
195{
196 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
197 INTR_INFO_VALID_MASK)) ==
198 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
199}
200
7aa81cc0
AL		 201static inline int is_invalid_opcode(u32 intr_info)
202{
203 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
204 INTR_INFO_VALID_MASK)) ==
205 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
206}
207
6aa8b732
AK		 208static inline int is_external_interrupt(u32 intr_info)
209{
210 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
211 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
212}
213
25c5f225
SY		 214static inline int cpu_has_vmx_msr_bitmap(void)
215{
216 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
217}
218
6e5d865c
YS		 219static inline int cpu_has_vmx_tpr_shadow(void)
220{
221 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
222}
223
224static inline int vm_need_tpr_shadow(struct kvm *kvm)
225{
226 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
227}
228
f78e0e2e
SY		 229static inline int cpu_has_secondary_exec_ctrls(void)
230{
231 return (vmcs_config.cpu_based_exec_ctrl &
232 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
233}
234
774ead3a 235static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 236{
4c9fc8ef
AK		 237 return flexpriority_enabled
238 && (vmcs_config.cpu_based_2nd_exec_ctrl &
239 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
f78e0e2e
SY		 240}
241
d56f546d
SY		 242static inline int cpu_has_vmx_invept_individual_addr(void)
243{
244 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
245}
246
247static inline int cpu_has_vmx_invept_context(void)
248{
249 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
250}
251
252static inline int cpu_has_vmx_invept_global(void)
253{
254 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
255}
256
257static inline int cpu_has_vmx_ept(void)
258{
259 return (vmcs_config.cpu_based_2nd_exec_ctrl &
260 SECONDARY_EXEC_ENABLE_EPT);
261}
262
263static inline int vm_need_ept(void)
264{
265 return (cpu_has_vmx_ept() && enable_ept);
266}
267
f78e0e2e
SY		 268static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
269{
270 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
271 (irqchip_in_kernel(kvm)));
272}
273
2384d2b3
SY		 274static inline int cpu_has_vmx_vpid(void)
275{
276 return (vmcs_config.cpu_based_2nd_exec_ctrl &
277 SECONDARY_EXEC_ENABLE_VPID);
278}
279
f08864b4
SY		 280static inline int cpu_has_virtual_nmis(void)
281{
282 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
283}
284
8b9cf98c 285static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 286{
287 int i;
288
a2fa3e9f
GH		 289 for (i = 0; i < vmx->nmsrs; ++i)
290 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 291 return i;
292 return -1;
293}
294
2384d2b3
SY		 295static inline void __invvpid(int ext, u16 vpid, gva_t gva)
296{
297 struct {
298 u64 vpid : 16;
299 u64 rsvd : 48;
300 u64 gva;
301 } operand = { vpid, 0, gva };
302
4ecac3fd 303 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 304 /* CF==1 or ZF==1 --> rc = -1 */
305 "; ja 1f ; ud2 ; 1:"
306 : : "a"(&operand), "c"(ext) : "cc", "memory");
307}
308
1439442c
SY		 309static inline void __invept(int ext, u64 eptp, gpa_t gpa)
310{
311 struct {
312 u64 eptp, gpa;
313 } operand = {eptp, gpa};
314
4ecac3fd 315 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 316 /* CF==1 or ZF==1 --> rc = -1 */
317 "; ja 1f ; ud2 ; 1:\n"
318 : : "a" (&operand), "c" (ext) : "cc", "memory");
319}
320
8b9cf98c 321static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 322{
323 int i;
324
8b9cf98c 325 i = __find_msr_index(vmx, msr);
a75beee6 326 if (i >= 0)
a2fa3e9f 327 return &vmx->guest_msrs[i];
8b6d44c7 328 return NULL;
7725f0ba
AK		 329}
330
6aa8b732
AK		 331static void vmcs_clear(struct vmcs *vmcs)
332{
333 u64 phys_addr = __pa(vmcs);
334 u8 error;
335
4ecac3fd 336 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 337 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
338 : "cc", "memory");
339 if (error)
340 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
341 vmcs, phys_addr);
342}
343
344static void __vcpu_clear(void *arg)
345{
8b9cf98c 346 struct vcpu_vmx *vmx = arg;
d3b2c338 347 int cpu = raw_smp_processor_id();
6aa8b732 348
8b9cf98c 349 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 350 vmcs_clear(vmx->vmcs);
351 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 352 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 353 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 354 list_del(&vmx->local_vcpus_link);
355 vmx->vcpu.cpu = -1;
356 vmx->launched = 0;
6aa8b732
AK		 357}
358
8b9cf98c 359static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 360{
eae5ecb5
AK		 361 if (vmx->vcpu.cpu == -1)
362 return;
8691e5a8 363 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 364}
365
2384d2b3
SY		 366static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
367{
368 if (vmx->vpid == 0)
369 return;
370
371 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
372}
373
1439442c
SY		 374static inline void ept_sync_global(void)
375{
376 if (cpu_has_vmx_invept_global())
377 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
378}
379
380static inline void ept_sync_context(u64 eptp)
381{
382 if (vm_need_ept()) {
383 if (cpu_has_vmx_invept_context())
384 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
385 else
386 ept_sync_global();
387 }
388}
389
390static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
391{
392 if (vm_need_ept()) {
393 if (cpu_has_vmx_invept_individual_addr())
394 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
395 eptp, gpa);
396 else
397 ept_sync_context(eptp);
398 }
399}
400
6aa8b732
AK		 401static unsigned long vmcs_readl(unsigned long field)
402{
403 unsigned long value;
404
4ecac3fd 405 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 406 : "=a"(value) : "d"(field) : "cc");
407 return value;
408}
409
410static u16 vmcs_read16(unsigned long field)
411{
412 return vmcs_readl(field);
413}
414
415static u32 vmcs_read32(unsigned long field)
416{
417 return vmcs_readl(field);
418}
419
420static u64 vmcs_read64(unsigned long field)
421{
05b3e0c2 422#ifdef CONFIG_X86_64
6aa8b732
AK		 423 return vmcs_readl(field);
424#else
425 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
426#endif
427}
428
e52de1b8
AK		 429static noinline void vmwrite_error(unsigned long field, unsigned long value)
430{
431 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
432 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
433 dump_stack();
434}
435
6aa8b732
AK		 436static void vmcs_writel(unsigned long field, unsigned long value)
437{
438 u8 error;
439
4ecac3fd 440 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 441 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 442 if (unlikely(error))
443 vmwrite_error(field, value);
6aa8b732
AK		 444}
445
446static void vmcs_write16(unsigned long field, u16 value)
447{
448 vmcs_writel(field, value);
449}
450
451static void vmcs_write32(unsigned long field, u32 value)
452{
453 vmcs_writel(field, value);
454}
455
456static void vmcs_write64(unsigned long field, u64 value)
457{
6aa8b732 458 vmcs_writel(field, value);
7682f2d0 459#ifndef CONFIG_X86_64
6aa8b732
AK		 460 asm volatile ("");
461 vmcs_writel(field+1, value >> 32);
462#endif
463}
464
2ab455cc
AL		 465static void vmcs_clear_bits(unsigned long field, u32 mask)
466{
467 vmcs_writel(field, vmcs_readl(field) & ~mask);
468}
469
470static void vmcs_set_bits(unsigned long field, u32 mask)
471{
472 vmcs_writel(field, vmcs_readl(field) | mask);
473}
474
abd3f2d6
AK		 475static void update_exception_bitmap(struct kvm_vcpu *vcpu)
476{
477 u32 eb;
478
7aa81cc0 479 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 480 if (!vcpu->fpu_active)
481 eb |= 1u << NM_VECTOR;
482 if (vcpu->guest_debug.enabled)
19bd8afd 483 eb |= 1u << DB_VECTOR;
ad312c7c 484 if (vcpu->arch.rmode.active)
abd3f2d6 485 eb = ~0;
1439442c
SY		 486 if (vm_need_ept())
487 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 488 vmcs_write32(EXCEPTION_BITMAP, eb);
489}
490
33ed6329
AK		 491static void reload_tss(void)
492{
33ed6329
AK		 493 /*
494 * VT restores TR but not its size. Useless.
495 */
496 struct descriptor_table gdt;
a5f61300 497 struct desc_struct *descs;
33ed6329 498
d6e88aec 499 kvm_get_gdt(&gdt);
33ed6329
AK		 500 descs = (void *)gdt.base;
501 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
502 load_TR_desc();
33ed6329
AK		 503}
504
8b9cf98c 505static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 506{
a2fa3e9f 507 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 508 u64 host_efer = vmx->host_msrs[efer_offset].data;
509 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
510 u64 ignore_bits;
511
512 if (efer_offset < 0)
513 return;
514 /*
515 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
516 * outside long mode
517 */
518 ignore_bits = EFER_NX | EFER_SCE;
519#ifdef CONFIG_X86_64
520 ignore_bits |= EFER_LMA | EFER_LME;
521 /* SCE is meaningful only in long mode on Intel */
522 if (guest_efer & EFER_LMA)
523 ignore_bits &= ~(u64)EFER_SCE;
524#endif
525 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
526 return;
2cc51560 527
51c6cf66
AK		 528 vmx->host_state.guest_efer_loaded = 1;
529 guest_efer &= ~ignore_bits;
530 guest_efer |= host_efer & ignore_bits;
531 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 532 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 533}
534
51c6cf66
AK		 535static void reload_host_efer(struct vcpu_vmx *vmx)
536{
537 if (vmx->host_state.guest_efer_loaded) {
538 vmx->host_state.guest_efer_loaded = 0;
539 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
540 }
541}
542
04d2cc77 543static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 544{
04d2cc77
AK		 545 struct vcpu_vmx *vmx = to_vmx(vcpu);
546
a2fa3e9f 547 if (vmx->host_state.loaded)
33ed6329
AK		 548 return;
549
a2fa3e9f 550 vmx->host_state.loaded = 1;
33ed6329
AK		 551 /*
552 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
553 * allow segment selectors with cpl > 0 or ti == 1.
554 */
d6e88aec 555 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 556 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 557 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 558 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 559 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 560 vmx->host_state.fs_reload_needed = 0;
561 } else {
33ed6329 562 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 563 vmx->host_state.fs_reload_needed = 1;
33ed6329 564 }
d6e88aec 565 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 566 if (!(vmx->host_state.gs_sel & 7))
567 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 568 else {
569 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 570 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 571 }
572
573#ifdef CONFIG_X86_64
574 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
575 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
576#else
a2fa3e9f
GH		 577 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
578 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 579#endif
707c0874
AK		 580
581#ifdef CONFIG_X86_64
d77c26fc 582 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 583 save_msrs(vmx->host_msrs +
584 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 585
707c0874 586#endif
a2fa3e9f 587 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 588 load_transition_efer(vmx);
33ed6329
AK		 589}
590
a9b21b62 591static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 592{
15ad7146 593 unsigned long flags;
33ed6329 594
a2fa3e9f 595 if (!vmx->host_state.loaded)
33ed6329
AK		 596 return;
597
e1beb1d3 598 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 599 vmx->host_state.loaded = 0;
152d3f2f 600 if (vmx->host_state.fs_reload_needed)
d6e88aec 601 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 602 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 603 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 604 /*
605 * If we have to reload gs, we must take care to
606 * preserve our gs base.
607 */
15ad7146 608 local_irq_save(flags);
d6e88aec 609 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 610#ifdef CONFIG_X86_64
611 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
612#endif
15ad7146 613 local_irq_restore(flags);
33ed6329 614 }
152d3f2f 615 reload_tss();
a2fa3e9f
GH		 616 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
617 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 618 reload_host_efer(vmx);
33ed6329
AK		 619}
620
a9b21b62
AK		 621static void vmx_load_host_state(struct vcpu_vmx *vmx)
622{
623 preempt_disable();
624 __vmx_load_host_state(vmx);
625 preempt_enable();
626}
627
6aa8b732
AK		 628/*
629 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
630 * vcpu mutex is already taken.
631 */
15ad7146 632static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 633{
a2fa3e9f
GH		 634 struct vcpu_vmx *vmx = to_vmx(vcpu);
635 u64 phys_addr = __pa(vmx->vmcs);
019960ae 636 u64 tsc_this, delta, new_offset;
6aa8b732 637
a3d7f85f 638 if (vcpu->cpu != cpu) {
8b9cf98c 639 vcpu_clear(vmx);
2f599714 640 kvm_migrate_timers(vcpu);
2384d2b3 641 vpid_sync_vcpu_all(vmx);
543e4243
AK		 642 local_irq_disable();
643 list_add(&vmx->local_vcpus_link,
644 &per_cpu(vcpus_on_cpu, cpu));
645 local_irq_enable();
a3d7f85f 646 }
6aa8b732 647
a2fa3e9f 648 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 649 u8 error;
650
a2fa3e9f 651 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 652 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 653 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
654 : "cc");
655 if (error)
656 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 657 vmx->vmcs, phys_addr);
6aa8b732
AK		 658 }
659
660 if (vcpu->cpu != cpu) {
661 struct descriptor_table dt;
662 unsigned long sysenter_esp;
663
664 vcpu->cpu = cpu;
665 /*
666 * Linux uses per-cpu TSS and GDT, so set these when switching
667 * processors.
668 */
d6e88aec
AK		 669 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
670 kvm_get_gdt(&dt);
6aa8b732
AK		 671 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
672
673 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
674 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 675
676 /*
677 * Make sure the time stamp counter is monotonous.
678 */
679 rdtscll(tsc_this);
019960ae
AK		 680 if (tsc_this < vcpu->arch.host_tsc) {
681 delta = vcpu->arch.host_tsc - tsc_this;
682 new_offset = vmcs_read64(TSC_OFFSET) + delta;
683 vmcs_write64(TSC_OFFSET, new_offset);
684 }
6aa8b732 685 }
6aa8b732
AK		 686}
687
688static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
689{
a9b21b62 690 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 691}
692
5fd86fcf
AK		 693static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
694{
695 if (vcpu->fpu_active)
696 return;
697 vcpu->fpu_active = 1;
707d92fa 698 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 699 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 700 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 701 update_exception_bitmap(vcpu);
702}
703
704static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
705{
706 if (!vcpu->fpu_active)
707 return;
708 vcpu->fpu_active = 0;
707d92fa 709 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 710 update_exception_bitmap(vcpu);
711}
712
6aa8b732
AK		 713static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
714{
715 return vmcs_readl(GUEST_RFLAGS);
716}
717
718static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
719{
ad312c7c 720 if (vcpu->arch.rmode.active)
053de044 721 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 722 vmcs_writel(GUEST_RFLAGS, rflags);
723}
724
725static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
726{
727 unsigned long rip;
728 u32 interruptibility;
729
5fdbf976 730 rip = kvm_rip_read(vcpu);
6aa8b732 731 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 732 kvm_rip_write(vcpu, rip);
6aa8b732
AK		 733
734 /*
735 * We emulated an instruction, so temporary interrupt blocking
736 * should be removed, if set.
737 */
738 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
739 if (interruptibility & 3)
740 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
741 interruptibility & ~3);
ad312c7c 742 vcpu->arch.interrupt_window_open = 1;
6aa8b732
AK		 743}
744
298101da
AK		 745static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
746 bool has_error_code, u32 error_code)
747{
77ab6db0
JK		 748 struct vcpu_vmx *vmx = to_vmx(vcpu);
749
750 if (has_error_code)
751 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
752
753 if (vcpu->arch.rmode.active) {
754 vmx->rmode.irq.pending = true;
755 vmx->rmode.irq.vector = nr;
756 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
757 if (nr == BP_VECTOR)
758 vmx->rmode.irq.rip++;
759 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
760 nr | INTR_TYPE_SOFT_INTR
761 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
762 | INTR_INFO_VALID_MASK);
763 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
764 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
765 return;
766 }
767
298101da
AK		 768 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
769 nr | INTR_TYPE_EXCEPTION
2e11384c 770 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
298101da 771 | INTR_INFO_VALID_MASK);
298101da
AK		 772}
773
774static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
775{
35920a35 776 return false;
298101da
AK		 777}
778
a75beee6
ED		 779/*
780 * Swap MSR entry in host/guest MSR entry array.
781 */
54e11fa1 782#ifdef CONFIG_X86_64
8b9cf98c 783static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 784{
a2fa3e9f
GH		 785 struct kvm_msr_entry tmp;
786
787 tmp = vmx->guest_msrs[to];
788 vmx->guest_msrs[to] = vmx->guest_msrs[from];
789 vmx->guest_msrs[from] = tmp;
790 tmp = vmx->host_msrs[to];
791 vmx->host_msrs[to] = vmx->host_msrs[from];
792 vmx->host_msrs[from] = tmp;
a75beee6 793}
54e11fa1 794#endif
a75beee6 795
e38aea3e
AK		 796/*
797 * Set up the vmcs to automatically save and restore system
798 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
799 * mode, as fiddling with msrs is very expensive.
800 */
8b9cf98c 801static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 802{
2cc51560 803 int save_nmsrs;
e38aea3e 804
33f9c505 805 vmx_load_host_state(vmx);
a75beee6
ED		 806 save_nmsrs = 0;
807#ifdef CONFIG_X86_64
8b9cf98c 808 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 809 int index;
810
8b9cf98c 811 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 812 if (index >= 0)
8b9cf98c
RR		 813 move_msr_up(vmx, index, save_nmsrs++);
814 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 815 if (index >= 0)
8b9cf98c
RR		 816 move_msr_up(vmx, index, save_nmsrs++);
817 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 818 if (index >= 0)
8b9cf98c
RR		 819 move_msr_up(vmx, index, save_nmsrs++);
820 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 821 if (index >= 0)
8b9cf98c 822 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 823 /*
824 * MSR_K6_STAR is only needed on long mode guests, and only
825 * if efer.sce is enabled.
826 */
8b9cf98c 827 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 828 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 829 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 830 }
831#endif
a2fa3e9f 832 vmx->save_nmsrs = save_nmsrs;
e38aea3e 833
4d56c8a7 834#ifdef CONFIG_X86_64
a2fa3e9f 835 vmx->msr_offset_kernel_gs_base =
8b9cf98c 836 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 837#endif
8b9cf98c 838 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 839}
840
6aa8b732
AK		 841/*
842 * reads and returns guest's timestamp counter "register"
843 * guest_tsc = host_tsc + tsc_offset -- 21.3
844 */
845static u64 guest_read_tsc(void)
846{
847 u64 host_tsc, tsc_offset;
848
849 rdtscll(host_tsc);
850 tsc_offset = vmcs_read64(TSC_OFFSET);
851 return host_tsc + tsc_offset;
852}
853
854/*
855 * writes 'guest_tsc' into guest's timestamp counter "register"
856 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
857 */
858static void guest_write_tsc(u64 guest_tsc)
859{
860 u64 host_tsc;
861
862 rdtscll(host_tsc);
863 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
864}
865
6aa8b732
AK		 866/*
867 * Reads an msr value (of 'msr_index') into 'pdata'.
868 * Returns 0 on success, non-0 otherwise.
869 * Assumes vcpu_load() was already called.
870 */
871static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
872{
873 u64 data;
a2fa3e9f 874 struct kvm_msr_entry *msr;
6aa8b732
AK		 875
876 if (!pdata) {
877 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
878 return -EINVAL;
879 }
880
881 switch (msr_index) {
05b3e0c2 882#ifdef CONFIG_X86_64
6aa8b732
AK		 883 case MSR_FS_BASE:
884 data = vmcs_readl(GUEST_FS_BASE);
885 break;
886 case MSR_GS_BASE:
887 data = vmcs_readl(GUEST_GS_BASE);
888 break;
889 case MSR_EFER:
3bab1f5d 890 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 891#endif
892 case MSR_IA32_TIME_STAMP_COUNTER:
893 data = guest_read_tsc();
894 break;
895 case MSR_IA32_SYSENTER_CS:
896 data = vmcs_read32(GUEST_SYSENTER_CS);
897 break;
898 case MSR_IA32_SYSENTER_EIP:
f5b42c33 899 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 900 break;
901 case MSR_IA32_SYSENTER_ESP:
f5b42c33 902 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 903 break;
6aa8b732 904 default:
8b9cf98c 905 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 906 if (msr) {
907 data = msr->data;
908 break;
6aa8b732 909 }
3bab1f5d 910 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 911 }
912
913 *pdata = data;
914 return 0;
915}
916
917/*
918 * Writes msr value into into the appropriate "register".
919 * Returns 0 on success, non-0 otherwise.
920 * Assumes vcpu_load() was already called.
921 */
922static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
923{
a2fa3e9f
GH		 924 struct vcpu_vmx *vmx = to_vmx(vcpu);
925 struct kvm_msr_entry *msr;
2cc51560
ED		 926 int ret = 0;
927
6aa8b732 928 switch (msr_index) {
05b3e0c2 929#ifdef CONFIG_X86_64
3bab1f5d 930 case MSR_EFER:
a9b21b62 931 vmx_load_host_state(vmx);
2cc51560 932 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 933 break;
6aa8b732
AK		 934 case MSR_FS_BASE:
935 vmcs_writel(GUEST_FS_BASE, data);
936 break;
937 case MSR_GS_BASE:
938 vmcs_writel(GUEST_GS_BASE, data);
939 break;
940#endif
941 case MSR_IA32_SYSENTER_CS:
942 vmcs_write32(GUEST_SYSENTER_CS, data);
943 break;
944 case MSR_IA32_SYSENTER_EIP:
f5b42c33 945 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 946 break;
947 case MSR_IA32_SYSENTER_ESP:
f5b42c33 948 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 949 break;
d27d4aca 950 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732 951 guest_write_tsc(data);
efa67e0d
CL		 952 break;
953 case MSR_P6_PERFCTR0:
954 case MSR_P6_PERFCTR1:
955 case MSR_P6_EVNTSEL0:
956 case MSR_P6_EVNTSEL1:
957 /*
958 * Just discard all writes to the performance counters; this
959 * should keep both older linux and windows 64-bit guests
960 * happy
961 */
962 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
963
6aa8b732 964 break;
6aa8b732 965 default:
a9b21b62 966 vmx_load_host_state(vmx);
8b9cf98c 967 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 968 if (msr) {
969 msr->data = data;
970 break;
6aa8b732 971 }
2cc51560 972 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 973 }
974
2cc51560 975 return ret;
6aa8b732
AK		 976}
977
5fdbf976 978static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 979{
5fdbf976
MT		 980 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
981 switch (reg) {
982 case VCPU_REGS_RSP:
983 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
984 break;
985 case VCPU_REGS_RIP:
986 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
987 break;
988 default:
989 break;
990 }
6aa8b732
AK		 991}
992
993static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
994{
995 unsigned long dr7 = 0x400;
6aa8b732
AK		 996 int old_singlestep;
997
6aa8b732
AK		 998 old_singlestep = vcpu->guest_debug.singlestep;
999
1000 vcpu->guest_debug.enabled = dbg->enabled;
1001 if (vcpu->guest_debug.enabled) {
1002 int i;
1003
1004 dr7 |= 0x200; /* exact */
1005 for (i = 0; i < 4; ++i) {
1006 if (!dbg->breakpoints[i].enabled)
1007 continue;
1008 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
1009 dr7 |= 2 << (i*2); /* global enable */
1010 dr7 |= 0 << (i*4+16); /* execution breakpoint */
1011 }
1012
6aa8b732 1013 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 1014 } else
6aa8b732 1015 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 1016
1017 if (old_singlestep && !vcpu->guest_debug.singlestep) {
1018 unsigned long flags;
1019
1020 flags = vmcs_readl(GUEST_RFLAGS);
1021 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1022 vmcs_writel(GUEST_RFLAGS, flags);
1023 }
1024
abd3f2d6 1025 update_exception_bitmap(vcpu);
6aa8b732
AK		 1026 vmcs_writel(GUEST_DR7, dr7);
1027
1028 return 0;
1029}
1030
2a8067f1
ED		 1031static int vmx_get_irq(struct kvm_vcpu *vcpu)
1032{
f7d9238f
AK		 1033 if (!vcpu->arch.interrupt.pending)
1034 return -1;
1035 return vcpu->arch.interrupt.nr;
2a8067f1
ED		 1036}
1037
6aa8b732
AK		 1038static __init int cpu_has_kvm_support(void)
1039{
1040 unsigned long ecx = cpuid_ecx(1);
1041 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
1042}
1043
1044static __init int vmx_disabled_by_bios(void)
1045{
1046 u64 msr;
1047
1048 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1049 return (msr & (FEATURE_CONTROL_LOCKED |
1050 FEATURE_CONTROL_VMXON_ENABLED))
1051 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1052 /* locked but not enabled */
6aa8b732
AK		 1053}
1054
774c47f1 1055static void hardware_enable(void *garbage)
6aa8b732
AK		 1056{
1057 int cpu = raw_smp_processor_id();
1058 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1059 u64 old;
1060
543e4243 1061 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1062 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1063 if ((old & (FEATURE_CONTROL_LOCKED |
1064 FEATURE_CONTROL_VMXON_ENABLED))
1065 != (FEATURE_CONTROL_LOCKED |
1066 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1067 /* enable and lock */
62b3ffb8 1068 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1069 FEATURE_CONTROL_LOCKED |
1070 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1071 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1072 asm volatile (ASM_VMX_VMXON_RAX
1073 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1074 : "memory", "cc");
1075}
1076
543e4243
AK		 1077static void vmclear_local_vcpus(void)
1078{
1079 int cpu = raw_smp_processor_id();
1080 struct vcpu_vmx *vmx, *n;
1081
1082 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1083 local_vcpus_link)
1084 __vcpu_clear(vmx);
1085}
1086
6aa8b732
AK		 1087static void hardware_disable(void *garbage)
1088{
543e4243 1089 vmclear_local_vcpus();
4ecac3fd 1090 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1091 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1092}
1093
1c3d14fe 1094static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1095 u32 msr, u32 *result)
1c3d14fe
YS		 1096{
1097 u32 vmx_msr_low, vmx_msr_high;
1098 u32 ctl = ctl_min | ctl_opt;
1099
1100 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1101
1102 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1103 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1104
1105 /* Ensure minimum (required) set of control bits are supported. */
1106 if (ctl_min & ~ctl)
002c7f7c 1107 return -EIO;
1c3d14fe
YS		 1108
1109 *result = ctl;
1110 return 0;
1111}
1112
002c7f7c 1113static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1114{
1115 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1116 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1117 u32 _pin_based_exec_control = 0;
1118 u32 _cpu_based_exec_control = 0;
f78e0e2e 1119 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1120 u32 _vmexit_control = 0;
1121 u32 _vmentry_control = 0;
1122
1123 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1124 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1125 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1126 &_pin_based_exec_control) < 0)
002c7f7c 1127 return -EIO;
1c3d14fe
YS		 1128
1129 min = CPU_BASED_HLT_EXITING |
1130#ifdef CONFIG_X86_64
1131 CPU_BASED_CR8_LOAD_EXITING |
1132 CPU_BASED_CR8_STORE_EXITING |
1133#endif
d56f546d
SY		 1134 CPU_BASED_CR3_LOAD_EXITING |
1135 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1136 CPU_BASED_USE_IO_BITMAPS |
1137 CPU_BASED_MOV_DR_EXITING |
a7052897
MT		 1138 CPU_BASED_USE_TSC_OFFSETING |
1139 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1140 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1141 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1142 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1143 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1144 &_cpu_based_exec_control) < 0)
002c7f7c 1145 return -EIO;
6e5d865c
YS		 1146#ifdef CONFIG_X86_64
1147 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1148 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1149 ~CPU_BASED_CR8_STORE_EXITING;
1150#endif
f78e0e2e 1151 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1152 min2 = 0;
1153 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1154 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d
SY		 1155 SECONDARY_EXEC_ENABLE_VPID |
1156 SECONDARY_EXEC_ENABLE_EPT;
1157 if (adjust_vmx_controls(min2, opt2,
1158 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1159 &_cpu_based_2nd_exec_control) < 0)
1160 return -EIO;
1161 }
1162#ifndef CONFIG_X86_64
1163 if (!(_cpu_based_2nd_exec_control &
1164 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1165 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1166#endif
d56f546d 1167 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1168 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1169 enabled */
d56f546d 1170 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
a7052897
MT		 1171 CPU_BASED_CR3_STORE_EXITING |
1172 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1173 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1174 &_cpu_based_exec_control) < 0)
1175 return -EIO;
1176 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1177 vmx_capability.ept, vmx_capability.vpid);
1178 }
1c3d14fe
YS		 1179
1180 min = 0;
1181#ifdef CONFIG_X86_64
1182 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1183#endif
1184 opt = 0;
1185 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1186 &_vmexit_control) < 0)
002c7f7c 1187 return -EIO;
1c3d14fe
YS		 1188
1189 min = opt = 0;
1190 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1191 &_vmentry_control) < 0)
002c7f7c 1192 return -EIO;
6aa8b732 1193
c68876fd 1194 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1195
1196 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1197 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1198 return -EIO;
1c3d14fe
YS		 1199
1200#ifdef CONFIG_X86_64
1201 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1202 if (vmx_msr_high & (1u<<16))
002c7f7c 1203 return -EIO;
1c3d14fe
YS		 1204#endif
1205
1206 /* Require Write-Back (WB) memory type for VMCS accesses. */
1207 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1208 return -EIO;
1c3d14fe 1209
002c7f7c
YS		 1210 vmcs_conf->size = vmx_msr_high & 0x1fff;
1211 vmcs_conf->order = get_order(vmcs_config.size);
1212 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1213
002c7f7c
YS		 1214 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1215 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1216 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1217 vmcs_conf->vmexit_ctrl = _vmexit_control;
1218 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1219
1220 return 0;
c68876fd 1221}
6aa8b732
AK		 1222
1223static struct vmcs *alloc_vmcs_cpu(int cpu)
1224{
1225 int node = cpu_to_node(cpu);
1226 struct page *pages;
1227 struct vmcs *vmcs;
1228
1c3d14fe 1229 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1230 if (!pages)
1231 return NULL;
1232 vmcs = page_address(pages);
1c3d14fe
YS		 1233 memset(vmcs, 0, vmcs_config.size);
1234 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1235 return vmcs;
1236}
1237
1238static struct vmcs *alloc_vmcs(void)
1239{
d3b2c338 1240 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1241}
1242
1243static void free_vmcs(struct vmcs *vmcs)
1244{
1c3d14fe 1245 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1246}
1247
39959588 1248static void free_kvm_area(void)
6aa8b732
AK		 1249{
1250 int cpu;
1251
1252 for_each_online_cpu(cpu)
1253 free_vmcs(per_cpu(vmxarea, cpu));
1254}
1255
6aa8b732
AK		 1256static __init int alloc_kvm_area(void)
1257{
1258 int cpu;
1259
1260 for_each_online_cpu(cpu) {
1261 struct vmcs *vmcs;
1262
1263 vmcs = alloc_vmcs_cpu(cpu);
1264 if (!vmcs) {
1265 free_kvm_area();
1266 return -ENOMEM;
1267 }
1268
1269 per_cpu(vmxarea, cpu) = vmcs;
1270 }
1271 return 0;
1272}
1273
1274static __init int hardware_setup(void)
1275{
002c7f7c
YS		 1276 if (setup_vmcs_config(&vmcs_config) < 0)
1277 return -EIO;
50a37eb4
JR		 1278
1279 if (boot_cpu_has(X86_FEATURE_NX))
1280 kvm_enable_efer_bits(EFER_NX);
1281
6aa8b732
AK		 1282 return alloc_kvm_area();
1283}
1284
1285static __exit void hardware_unsetup(void)
1286{
1287 free_kvm_area();
1288}
1289
6aa8b732
AK		 1290static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1291{
1292 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1293
6af11b9e 1294 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1295 vmcs_write16(sf->selector, save->selector);
1296 vmcs_writel(sf->base, save->base);
1297 vmcs_write32(sf->limit, save->limit);
1298 vmcs_write32(sf->ar_bytes, save->ar);
1299 } else {
1300 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1301 << AR_DPL_SHIFT;
1302 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1303 }
1304}
1305
1306static void enter_pmode(struct kvm_vcpu *vcpu)
1307{
1308 unsigned long flags;
a89a8fb9 1309 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1310
a89a8fb9 1311 vmx->emulation_required = 1;
ad312c7c 1312 vcpu->arch.rmode.active = 0;
6aa8b732 1313
ad312c7c
ZX		 1314 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1315 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1316 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
6aa8b732
AK		 1317
1318 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1319 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
ad312c7c 1320 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1321 vmcs_writel(GUEST_RFLAGS, flags);
1322
66aee91a
RR		 1323 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1324 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1325
1326 update_exception_bitmap(vcpu);
1327
a89a8fb9
MG		 1328 if (emulate_invalid_guest_state)
1329 return;
1330
ad312c7c
ZX		 1331 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1332 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1333 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1334 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
6aa8b732
AK		 1335
1336 vmcs_write16(GUEST_SS_SELECTOR, 0);
1337 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1338
1339 vmcs_write16(GUEST_CS_SELECTOR,
1340 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1341 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1342}
1343
d77c26fc 1344static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1345{
bfc6d222 1346 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1347 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1348 kvm->memslots[0].npages - 3;
1349 return base_gfn << PAGE_SHIFT;
1350 }
bfc6d222 1351 return kvm->arch.tss_addr;
6aa8b732
AK		 1352}
1353
1354static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1355{
1356 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1357
1358 save->selector = vmcs_read16(sf->selector);
1359 save->base = vmcs_readl(sf->base);
1360 save->limit = vmcs_read32(sf->limit);
1361 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1362 vmcs_write16(sf->selector, save->base >> 4);
1363 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1364 vmcs_write32(sf->limit, 0xffff);
1365 vmcs_write32(sf->ar_bytes, 0xf3);
1366}
1367
1368static void enter_rmode(struct kvm_vcpu *vcpu)
1369{
1370 unsigned long flags;
a89a8fb9 1371 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1372
a89a8fb9 1373 vmx->emulation_required = 1;
ad312c7c 1374 vcpu->arch.rmode.active = 1;
6aa8b732 1375
ad312c7c 1376 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1377 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1378
ad312c7c 1379 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1380 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1381
ad312c7c 1382 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1383 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1384
1385 flags = vmcs_readl(GUEST_RFLAGS);
ad312c7c
ZX		 1386 vcpu->arch.rmode.save_iopl
1387 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1388
053de044 1389 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1390
1391 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1392 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1393 update_exception_bitmap(vcpu);
1394
a89a8fb9
MG		 1395 if (emulate_invalid_guest_state)
1396 goto continue_rmode;
1397
6aa8b732
AK		 1398 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1399 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1400 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1401
1402 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1403 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1404 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1405 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1406 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1407
ad312c7c
ZX		 1408 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1409 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1410 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1411 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
75880a01 1412
a89a8fb9 1413continue_rmode:
8668a3c4 1414 kvm_mmu_reset_context(vcpu);
b7ebfb05 1415 init_rmode(vcpu->kvm);
6aa8b732
AK		 1416}
1417
05b3e0c2 1418#ifdef CONFIG_X86_64
6aa8b732
AK		 1419
1420static void enter_lmode(struct kvm_vcpu *vcpu)
1421{
1422 u32 guest_tr_ar;
1423
1424 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1425 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1426 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1427 __func__);
6aa8b732
AK		 1428 vmcs_write32(GUEST_TR_AR_BYTES,
1429 (guest_tr_ar & ~AR_TYPE_MASK)
1430 | AR_TYPE_BUSY_64_TSS);
1431 }
1432
ad312c7c 1433 vcpu->arch.shadow_efer |= EFER_LMA;
6aa8b732 1434
8b9cf98c 1435 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1436 vmcs_write32(VM_ENTRY_CONTROLS,
1437 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1438 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1439}
1440
1441static void exit_lmode(struct kvm_vcpu *vcpu)
1442{
ad312c7c 1443 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1444
1445 vmcs_write32(VM_ENTRY_CONTROLS,
1446 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1447 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1448}
1449
1450#endif
1451
2384d2b3
SY		 1452static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1453{
1454 vpid_sync_vcpu_all(to_vmx(vcpu));
4e1096d2
SY		 1455 if (vm_need_ept())
1456 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1457}
1458
25c4c276 1459static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1460{
ad312c7c
ZX		 1461 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1462 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1463}
1464
1439442c
SY		 1465static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1466{
1467 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1468 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1469 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1470 return;
1471 }
1472 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1473 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1474 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1475 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1476 }
1477}
1478
1479static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1480
1481static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1482 unsigned long cr0,
1483 struct kvm_vcpu *vcpu)
1484{
1485 if (!(cr0 & X86_CR0_PG)) {
1486 /* From paging/starting to nonpaging */
1487 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1488 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1489 (CPU_BASED_CR3_LOAD_EXITING |
1490 CPU_BASED_CR3_STORE_EXITING));
1491 vcpu->arch.cr0 = cr0;
1492 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1493 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1494 *hw_cr0 &= ~X86_CR0_WP;
1495 } else if (!is_paging(vcpu)) {
1496 /* From nonpaging to paging */
1497 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1498 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1499 ~(CPU_BASED_CR3_LOAD_EXITING |
1500 CPU_BASED_CR3_STORE_EXITING));
1501 vcpu->arch.cr0 = cr0;
1502 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1503 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1504 *hw_cr0 &= ~X86_CR0_WP;
1505 }
1506}
1507
1508static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1509 struct kvm_vcpu *vcpu)
1510{
1511 if (!is_paging(vcpu)) {
1512 *hw_cr4 &= ~X86_CR4_PAE;
1513 *hw_cr4 |= X86_CR4_PSE;
1514 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1515 *hw_cr4 &= ~X86_CR4_PAE;
1516}
1517
6aa8b732
AK		 1518static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1519{
1439442c
SY		 1520 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1521 KVM_VM_CR0_ALWAYS_ON;
1522
5fd86fcf
AK		 1523 vmx_fpu_deactivate(vcpu);
1524
ad312c7c 1525 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1526 enter_pmode(vcpu);
1527
ad312c7c 1528 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1529 enter_rmode(vcpu);
1530
05b3e0c2 1531#ifdef CONFIG_X86_64
ad312c7c 1532 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1533 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1534 enter_lmode(vcpu);
707d92fa 1535 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1536 exit_lmode(vcpu);
1537 }
1538#endif
1539
1439442c
SY		 1540 if (vm_need_ept())
1541 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1542
6aa8b732 1543 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1544 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1545 vcpu->arch.cr0 = cr0;
5fd86fcf 1546
707d92fa 1547 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1548 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1549}
1550
1439442c
SY		 1551static u64 construct_eptp(unsigned long root_hpa)
1552{
1553 u64 eptp;
1554
1555 /* TODO write the value reading from MSR */
1556 eptp = VMX_EPT_DEFAULT_MT |
1557 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1558 eptp |= (root_hpa & PAGE_MASK);
1559
1560 return eptp;
1561}
1562
6aa8b732
AK		 1563static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1564{
1439442c
SY		 1565 unsigned long guest_cr3;
1566 u64 eptp;
1567
1568 guest_cr3 = cr3;
1569 if (vm_need_ept()) {
1570 eptp = construct_eptp(cr3);
1571 vmcs_write64(EPT_POINTER, eptp);
1572 ept_sync_context(eptp);
1573 ept_load_pdptrs(vcpu);
1574 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1575 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1576 }
1577
2384d2b3 1578 vmx_flush_tlb(vcpu);
1439442c 1579 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1580 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1581 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1582}
1583
1584static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1585{
1439442c
SY		 1586 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1587 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1588
ad312c7c 1589 vcpu->arch.cr4 = cr4;
1439442c
SY		 1590 if (vm_need_ept())
1591 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1592
1593 vmcs_writel(CR4_READ_SHADOW, cr4);
1594 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1595}
1596
6aa8b732
AK		 1597static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1598{
8b9cf98c
RR		 1599 struct vcpu_vmx *vmx = to_vmx(vcpu);
1600 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732 1601
ad312c7c 1602 vcpu->arch.shadow_efer = efer;
9f62e19a
JR		 1603 if (!msr)
1604 return;
6aa8b732
AK		 1605 if (efer & EFER_LMA) {
1606 vmcs_write32(VM_ENTRY_CONTROLS,
1607 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1608 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1609 msr->data = efer;
1610
1611 } else {
1612 vmcs_write32(VM_ENTRY_CONTROLS,
1613 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1614 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1615
1616 msr->data = efer & ~EFER_LME;
1617 }
8b9cf98c 1618 setup_msrs(vmx);
6aa8b732
AK		 1619}
1620
6aa8b732
AK		 1621static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1622{
1623 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1624
1625 return vmcs_readl(sf->base);
1626}
1627
1628static void vmx_get_segment(struct kvm_vcpu *vcpu,
1629 struct kvm_segment *var, int seg)
1630{
1631 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1632 u32 ar;
1633
1634 var->base = vmcs_readl(sf->base);
1635 var->limit = vmcs_read32(sf->limit);
1636 var->selector = vmcs_read16(sf->selector);
1637 ar = vmcs_read32(sf->ar_bytes);
1638 if (ar & AR_UNUSABLE_MASK)
1639 ar = 0;
1640 var->type = ar & 15;
1641 var->s = (ar >> 4) & 1;
1642 var->dpl = (ar >> 5) & 3;
1643 var->present = (ar >> 7) & 1;
1644 var->avl = (ar >> 12) & 1;
1645 var->l = (ar >> 13) & 1;
1646 var->db = (ar >> 14) & 1;
1647 var->g = (ar >> 15) & 1;
1648 var->unusable = (ar >> 16) & 1;
1649}
1650
2e4d2653
IE		 1651static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1652{
1653 struct kvm_segment kvm_seg;
1654
1655 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1656 return 0;
1657
1658 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1659 return 3;
1660
1661 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1662 return kvm_seg.selector & 3;
1663}
1664
653e3108 1665static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1666{
6aa8b732
AK		 1667 u32 ar;
1668
653e3108 1669 if (var->unusable)
6aa8b732
AK		 1670 ar = 1 << 16;
1671 else {
1672 ar = var->type & 15;
1673 ar |= (var->s & 1) << 4;
1674 ar |= (var->dpl & 3) << 5;
1675 ar |= (var->present & 1) << 7;
1676 ar |= (var->avl & 1) << 12;
1677 ar |= (var->l & 1) << 13;
1678 ar |= (var->db & 1) << 14;
1679 ar |= (var->g & 1) << 15;
1680 }
f7fbf1fd
UL		 1681 if (ar == 0) /* a 0 value means unusable */
1682 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1683
1684 return ar;
1685}
1686
1687static void vmx_set_segment(struct kvm_vcpu *vcpu,
1688 struct kvm_segment *var, int seg)
1689{
1690 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1691 u32 ar;
1692
ad312c7c
ZX		 1693 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1694 vcpu->arch.rmode.tr.selector = var->selector;
1695 vcpu->arch.rmode.tr.base = var->base;
1696 vcpu->arch.rmode.tr.limit = var->limit;
1697 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1698 return;
1699 }
1700 vmcs_writel(sf->base, var->base);
1701 vmcs_write32(sf->limit, var->limit);
1702 vmcs_write16(sf->selector, var->selector);
ad312c7c 1703 if (vcpu->arch.rmode.active && var->s) {
653e3108
AK		 1704 /*
1705 * Hack real-mode segments into vm86 compatibility.
1706 */
1707 if (var->base == 0xffff0000 && var->selector == 0xf000)
1708 vmcs_writel(sf->base, 0xf0000);
1709 ar = 0xf3;
1710 } else
1711 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1712 vmcs_write32(sf->ar_bytes, ar);
1713}
1714
6aa8b732
AK		 1715static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1716{
1717 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1718
1719 *db = (ar >> 14) & 1;
1720 *l = (ar >> 13) & 1;
1721}
1722
1723static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1724{
1725 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1726 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1727}
1728
1729static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1730{
1731 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1732 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1733}
1734
1735static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1736{
1737 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1738 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1739}
1740
1741static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1742{
1743 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1744 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1745}
1746
648dfaa7
MG		 1747static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1748{
1749 struct kvm_segment var;
1750 u32 ar;
1751
1752 vmx_get_segment(vcpu, &var, seg);
1753 ar = vmx_segment_access_rights(&var);
1754
1755 if (var.base != (var.selector << 4))
1756 return false;
1757 if (var.limit != 0xffff)
1758 return false;
1759 if (ar != 0xf3)
1760 return false;
1761
1762 return true;
1763}
1764
1765static bool code_segment_valid(struct kvm_vcpu *vcpu)
1766{
1767 struct kvm_segment cs;
1768 unsigned int cs_rpl;
1769
1770 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1771 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1772
1773 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1774 return false;
1775 if (!cs.s)
1776 return false;
1777 if (!(~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK))) {
1778 if (cs.dpl > cs_rpl)
1779 return false;
1780 } else if (cs.type & AR_TYPE_CODE_MASK) {
1781 if (cs.dpl != cs_rpl)
1782 return false;
1783 }
1784 if (!cs.present)
1785 return false;
1786
1787 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1788 return true;
1789}
1790
1791static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1792{
1793 struct kvm_segment ss;
1794 unsigned int ss_rpl;
1795
1796 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1797 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1798
1799 if ((ss.type != 3) || (ss.type != 7))
1800 return false;
1801 if (!ss.s)
1802 return false;
1803 if (ss.dpl != ss_rpl) /* DPL != RPL */
1804 return false;
1805 if (!ss.present)
1806 return false;
1807
1808 return true;
1809}
1810
1811static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1812{
1813 struct kvm_segment var;
1814 unsigned int rpl;
1815
1816 vmx_get_segment(vcpu, &var, seg);
1817 rpl = var.selector & SELECTOR_RPL_MASK;
1818
1819 if (!var.s)
1820 return false;
1821 if (!var.present)
1822 return false;
1823 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1824 if (var.dpl < rpl) /* DPL < RPL */
1825 return false;
1826 }
1827
1828 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1829 * rights flags
1830 */
1831 return true;
1832}
1833
1834static bool tr_valid(struct kvm_vcpu *vcpu)
1835{
1836 struct kvm_segment tr;
1837
1838 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1839
1840 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1841 return false;
1842 if ((tr.type != 3) || (tr.type != 11)) /* TODO: Check if guest is in IA32e mode */
1843 return false;
1844 if (!tr.present)
1845 return false;
1846
1847 return true;
1848}
1849
1850static bool ldtr_valid(struct kvm_vcpu *vcpu)
1851{
1852 struct kvm_segment ldtr;
1853
1854 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1855
1856 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1857 return false;
1858 if (ldtr.type != 2)
1859 return false;
1860 if (!ldtr.present)
1861 return false;
1862
1863 return true;
1864}
1865
1866static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1867{
1868 struct kvm_segment cs, ss;
1869
1870 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1871 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1872
1873 return ((cs.selector & SELECTOR_RPL_MASK) ==
1874 (ss.selector & SELECTOR_RPL_MASK));
1875}
1876
1877/*
1878 * Check if guest state is valid. Returns true if valid, false if
1879 * not.
1880 * We assume that registers are always usable
1881 */
1882static bool guest_state_valid(struct kvm_vcpu *vcpu)
1883{
1884 /* real mode guest state checks */
1885 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1886 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1887 return false;
1888 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1889 return false;
1890 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1891 return false;
1892 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1893 return false;
1894 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1895 return false;
1896 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1897 return false;
1898 } else {
1899 /* protected mode guest state checks */
1900 if (!cs_ss_rpl_check(vcpu))
1901 return false;
1902 if (!code_segment_valid(vcpu))
1903 return false;
1904 if (!stack_segment_valid(vcpu))
1905 return false;
1906 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1907 return false;
1908 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1909 return false;
1910 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1911 return false;
1912 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1913 return false;
1914 if (!tr_valid(vcpu))
1915 return false;
1916 if (!ldtr_valid(vcpu))
1917 return false;
1918 }
1919 /* TODO:
1920 * - Add checks on RIP
1921 * - Add checks on RFLAGS
1922 */
1923
1924 return true;
1925}
1926
d77c26fc 1927static int init_rmode_tss(struct kvm *kvm)
6aa8b732 1928{
6aa8b732 1929 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 1930 u16 data = 0;
10589a46 1931 int ret = 0;
195aefde 1932 int r;
6aa8b732 1933
195aefde
IE		 1934 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1935 if (r < 0)
10589a46 1936 goto out;
195aefde 1937 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 1938 r = kvm_write_guest_page(kvm, fn++, &data,
1939 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 1940 if (r < 0)
10589a46 1941 goto out;
195aefde
IE		 1942 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1943 if (r < 0)
10589a46 1944 goto out;
195aefde
IE		 1945 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1946 if (r < 0)
10589a46 1947 goto out;
195aefde 1948 data = ~0;
10589a46
MT		 1949 r = kvm_write_guest_page(kvm, fn, &data,
1950 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1951 sizeof(u8));
195aefde 1952 if (r < 0)
10589a46
MT		 1953 goto out;
1954
1955 ret = 1;
1956out:
10589a46 1957 return ret;
6aa8b732
AK		 1958}
1959
b7ebfb05
SY		 1960static int init_rmode_identity_map(struct kvm *kvm)
1961{
1962 int i, r, ret;
1963 pfn_t identity_map_pfn;
1964 u32 tmp;
1965
1966 if (!vm_need_ept())
1967 return 1;
1968 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1969 printk(KERN_ERR "EPT: identity-mapping pagetable "
1970 "haven't been allocated!\n");
1971 return 0;
1972 }
1973 if (likely(kvm->arch.ept_identity_pagetable_done))
1974 return 1;
1975 ret = 0;
1976 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1977 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1978 if (r < 0)
1979 goto out;
1980 /* Set up identity-mapping pagetable for EPT in real mode */
1981 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1982 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1983 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1984 r = kvm_write_guest_page(kvm, identity_map_pfn,
1985 &tmp, i * sizeof(tmp), sizeof(tmp));
1986 if (r < 0)
1987 goto out;
1988 }
1989 kvm->arch.ept_identity_pagetable_done = true;
1990 ret = 1;
1991out:
1992 return ret;
1993}
1994
6aa8b732
AK		 1995static void seg_setup(int seg)
1996{
1997 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1998
1999 vmcs_write16(sf->selector, 0);
2000 vmcs_writel(sf->base, 0);
2001 vmcs_write32(sf->limit, 0xffff);
a16b20da 2002 vmcs_write32(sf->ar_bytes, 0xf3);
6aa8b732
AK		 2003}
2004
f78e0e2e
SY		 2005static int alloc_apic_access_page(struct kvm *kvm)
2006{
2007 struct kvm_userspace_memory_region kvm_userspace_mem;
2008 int r = 0;
2009
72dc67a6 2010 down_write(&kvm->slots_lock);
bfc6d222 2011 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2012 goto out;
2013 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2014 kvm_userspace_mem.flags = 0;
2015 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2016 kvm_userspace_mem.memory_size = PAGE_SIZE;
2017 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2018 if (r)
2019 goto out;
72dc67a6 2020
bfc6d222 2021 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2022out:
72dc67a6 2023 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2024 return r;
2025}
2026
b7ebfb05
SY		 2027static int alloc_identity_pagetable(struct kvm *kvm)
2028{
2029 struct kvm_userspace_memory_region kvm_userspace_mem;
2030 int r = 0;
2031
2032 down_write(&kvm->slots_lock);
2033 if (kvm->arch.ept_identity_pagetable)
2034 goto out;
2035 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2036 kvm_userspace_mem.flags = 0;
2037 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2038 kvm_userspace_mem.memory_size = PAGE_SIZE;
2039 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2040 if (r)
2041 goto out;
2042
b7ebfb05
SY		 2043 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2044 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
b7ebfb05
SY		 2045out:
2046 up_write(&kvm->slots_lock);
2047 return r;
2048}
2049
2384d2b3
SY		 2050static void allocate_vpid(struct vcpu_vmx *vmx)
2051{
2052 int vpid;
2053
2054 vmx->vpid = 0;
2055 if (!enable_vpid || !cpu_has_vmx_vpid())
2056 return;
2057 spin_lock(&vmx_vpid_lock);
2058 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2059 if (vpid < VMX_NR_VPIDS) {
2060 vmx->vpid = vpid;
2061 __set_bit(vpid, vmx_vpid_bitmap);
2062 }
2063 spin_unlock(&vmx_vpid_lock);
2064}
2065
8b2cf73c 2066static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
25c5f225
SY		 2067{
2068 void *va;
2069
2070 if (!cpu_has_vmx_msr_bitmap())
2071 return;
2072
2073 /*
2074 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2075 * have the write-low and read-high bitmap offsets the wrong way round.
2076 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2077 */
2078 va = kmap(msr_bitmap);
2079 if (msr <= 0x1fff) {
2080 __clear_bit(msr, va + 0x000); /* read-low */
2081 __clear_bit(msr, va + 0x800); /* write-low */
2082 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2083 msr &= 0x1fff;
2084 __clear_bit(msr, va + 0x400); /* read-high */
2085 __clear_bit(msr, va + 0xc00); /* write-high */
2086 }
2087 kunmap(msr_bitmap);
2088}
2089
6aa8b732
AK		 2090/*
2091 * Sets up the vmcs for emulated real mode.
2092 */
8b9cf98c 2093static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732
AK		 2094{
2095 u32 host_sysenter_cs;
2096 u32 junk;
2097 unsigned long a;
2098 struct descriptor_table dt;
2099 int i;
cd2276a7 2100 unsigned long kvm_vmx_return;
6e5d865c 2101 u32 exec_control;
6aa8b732 2102
6aa8b732 2103 /* I/O */
fdef3ad1
HQ		 2104 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2105 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732 2106
25c5f225
SY		 2107 if (cpu_has_vmx_msr_bitmap())
2108 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2109
6aa8b732
AK		 2110 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2111
6aa8b732 2112 /* Control */
1c3d14fe
YS		 2113 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2114 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2115
2116 exec_control = vmcs_config.cpu_based_exec_ctrl;
2117 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2118 exec_control &= ~CPU_BASED_TPR_SHADOW;
2119#ifdef CONFIG_X86_64
2120 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2121 CPU_BASED_CR8_LOAD_EXITING;
2122#endif
2123 }
d56f546d
SY		 2124 if (!vm_need_ept())
2125 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2126 CPU_BASED_CR3_LOAD_EXITING |
2127 CPU_BASED_INVLPG_EXITING;
6e5d865c 2128 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2129
83ff3b9d
SY		 2130 if (cpu_has_secondary_exec_ctrls()) {
2131 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2132 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2133 exec_control &=
2134 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2135 if (vmx->vpid == 0)
2136 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
d56f546d
SY		 2137 if (!vm_need_ept())
2138 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
83ff3b9d
SY		 2139 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2140 }
f78e0e2e 2141
c7addb90
AK		 2142 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2143 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2144 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2145
2146 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2147 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2148 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2149
2150 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2151 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2152 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2153 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2154 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2155 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2156#ifdef CONFIG_X86_64
6aa8b732
AK		 2157 rdmsrl(MSR_FS_BASE, a);
2158 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2159 rdmsrl(MSR_GS_BASE, a);
2160 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2161#else
2162 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2163 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2164#endif
2165
2166 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2167
d6e88aec 2168 kvm_get_idt(&dt);
6aa8b732
AK		 2169 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2170
d77c26fc 2171 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2172 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2173 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2174 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2175 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2176
2177 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2178 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2179 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2180 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2181 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2182 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2183
6aa8b732
AK		 2184 for (i = 0; i < NR_VMX_MSR; ++i) {
2185 u32 index = vmx_msr_index[i];
2186 u32 data_low, data_high;
2187 u64 data;
a2fa3e9f 2188 int j = vmx->nmsrs;
6aa8b732
AK		 2189
2190 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2191 continue;
432bd6cb
AK		 2192 if (wrmsr_safe(index, data_low, data_high) < 0)
2193 continue;
6aa8b732 2194 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 2195 vmx->host_msrs[j].index = index;
2196 vmx->host_msrs[j].reserved = 0;
2197 vmx->host_msrs[j].data = data;
2198 vmx->guest_msrs[j] = vmx->host_msrs[j];
2199 ++vmx->nmsrs;
6aa8b732 2200 }
6aa8b732 2201
1c3d14fe 2202 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2203
2204 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2205 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2206
e00c8cf2
AK		 2207 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2208 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2209
f78e0e2e 2210
e00c8cf2
AK		 2211 return 0;
2212}
2213
b7ebfb05
SY		 2214static int init_rmode(struct kvm *kvm)
2215{
2216 if (!init_rmode_tss(kvm))
2217 return 0;
2218 if (!init_rmode_identity_map(kvm))
2219 return 0;
2220 return 1;
2221}
2222
e00c8cf2
AK		 2223static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2224{
2225 struct vcpu_vmx *vmx = to_vmx(vcpu);
2226 u64 msr;
2227 int ret;
2228
5fdbf976 2229 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2230 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2231 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2232 ret = -ENOMEM;
2233 goto out;
2234 }
2235
ad312c7c 2236 vmx->vcpu.arch.rmode.active = 0;
e00c8cf2 2237
3b86cd99
JK		 2238 vmx->soft_vnmi_blocked = 0;
2239
ad312c7c 2240 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2241 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2
AK		 2242 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2243 if (vmx->vcpu.vcpu_id == 0)
2244 msr |= MSR_IA32_APICBASE_BSP;
2245 kvm_set_apic_base(&vmx->vcpu, msr);
2246
2247 fx_init(&vmx->vcpu);
2248
5706be0d 2249 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2250 /*
2251 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2252 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2253 */
2254 if (vmx->vcpu.vcpu_id == 0) {
2255 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2256 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2257 } else {
ad312c7c
ZX		 2258 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2259 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2260 }
e00c8cf2
AK		 2261
2262 seg_setup(VCPU_SREG_DS);
2263 seg_setup(VCPU_SREG_ES);
2264 seg_setup(VCPU_SREG_FS);
2265 seg_setup(VCPU_SREG_GS);
2266 seg_setup(VCPU_SREG_SS);
2267
2268 vmcs_write16(GUEST_TR_SELECTOR, 0);
2269 vmcs_writel(GUEST_TR_BASE, 0);
2270 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2271 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2272
2273 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2274 vmcs_writel(GUEST_LDTR_BASE, 0);
2275 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2276 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2277
2278 vmcs_write32(GUEST_SYSENTER_CS, 0);
2279 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2280 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2281
2282 vmcs_writel(GUEST_RFLAGS, 0x02);
2283 if (vmx->vcpu.vcpu_id == 0)
5fdbf976 2284 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2285 else
5fdbf976
MT		 2286 kvm_rip_write(vcpu, 0);
2287 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2
AK		 2288
2289 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2290 vmcs_writel(GUEST_DR7, 0x400);
2291
2292 vmcs_writel(GUEST_GDTR_BASE, 0);
2293 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2294
2295 vmcs_writel(GUEST_IDTR_BASE, 0);
2296 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2297
2298 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2299 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2300 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2301
2302 guest_write_tsc(0);
2303
2304 /* Special registers */
2305 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2306
2307 setup_msrs(vmx);
2308
6aa8b732
AK		 2309 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2310
f78e0e2e
SY		 2311 if (cpu_has_vmx_tpr_shadow()) {
2312 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2313 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2314 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2315 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2316 vmcs_write32(TPR_THRESHOLD, 0);
2317 }
2318
2319 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2320 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2321 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2322
2384d2b3
SY		 2323 if (vmx->vpid != 0)
2324 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2325
ad312c7c
ZX		 2326 vmx->vcpu.arch.cr0 = 0x60000010;
2327 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2328 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2329 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2330 vmx_fpu_activate(&vmx->vcpu);
2331 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2332
2384d2b3
SY		 2333 vpid_sync_vcpu_all(vmx);
2334
3200f405 2335 ret = 0;
6aa8b732 2336
a89a8fb9
MG		 2337 /* HACK: Don't enable emulation on guest boot/reset */
2338 vmx->emulation_required = 0;
2339
6aa8b732 2340out:
3200f405 2341 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2342 return ret;
2343}
2344
3b86cd99
JK		 2345static void enable_irq_window(struct kvm_vcpu *vcpu)
2346{
2347 u32 cpu_based_vm_exec_control;
2348
2349 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2350 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2351 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2352}
2353
2354static void enable_nmi_window(struct kvm_vcpu *vcpu)
2355{
2356 u32 cpu_based_vm_exec_control;
2357
2358 if (!cpu_has_virtual_nmis()) {
2359 enable_irq_window(vcpu);
2360 return;
2361 }
2362
2363 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2364 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2365 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2366}
2367
85f455f7
ED		 2368static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2369{
9c8cba37
AK		 2370 struct vcpu_vmx *vmx = to_vmx(vcpu);
2371
2714d1d3
FEL		 2372 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2373
fa89a817 2374 ++vcpu->stat.irq_injections;
ad312c7c 2375 if (vcpu->arch.rmode.active) {
9c8cba37
AK		 2376 vmx->rmode.irq.pending = true;
2377 vmx->rmode.irq.vector = irq;
5fdbf976 2378 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
9c5623e3
AK		 2379 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2380 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2381 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2382 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2383 return;
2384 }
2385 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2386 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2387}
2388
f08864b4
SY		 2389static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2390{
66a5a347
JK		 2391 struct vcpu_vmx *vmx = to_vmx(vcpu);
2392
3b86cd99
JK		 2393 if (!cpu_has_virtual_nmis()) {
2394 /*
2395 * Tracking the NMI-blocked state in software is built upon
2396 * finding the next open IRQ window. This, in turn, depends on
2397 * well-behaving guests: They have to keep IRQs disabled at
2398 * least as long as the NMI handler runs. Otherwise we may
2399 * cause NMI nesting, maybe breaking the guest. But as this is
2400 * highly unlikely, we can live with the residual risk.
2401 */
2402 vmx->soft_vnmi_blocked = 1;
2403 vmx->vnmi_blocked_time = 0;
2404 }
2405
487b391d 2406 ++vcpu->stat.nmi_injections;
66a5a347
JK		 2407 if (vcpu->arch.rmode.active) {
2408 vmx->rmode.irq.pending = true;
2409 vmx->rmode.irq.vector = NMI_VECTOR;
2410 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2411 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2412 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2413 INTR_INFO_VALID_MASK);
2414 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2415 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2416 return;
2417 }
f08864b4
SY		 2418 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2419 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2420}
2421
33f089ca
JK		 2422static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2423{
2424 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2425
2426 vcpu->arch.nmi_window_open =
2427 !(guest_intr & (GUEST_INTR_STATE_STI |
2428 GUEST_INTR_STATE_MOV_SS |
2429 GUEST_INTR_STATE_NMI));
3b86cd99
JK		 2430 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2431 vcpu->arch.nmi_window_open = 0;
33f089ca
JK		 2432
2433 vcpu->arch.interrupt_window_open =
2434 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2435 !(guest_intr & (GUEST_INTR_STATE_STI |
2436 GUEST_INTR_STATE_MOV_SS)));
2437}
2438
6aa8b732
AK		 2439static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2440{
ad312c7c
ZX		 2441 int word_index = __ffs(vcpu->arch.irq_summary);
2442 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
6aa8b732
AK		 2443 int irq = word_index * BITS_PER_LONG + bit_index;
2444
ad312c7c
ZX		 2445 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2446 if (!vcpu->arch.irq_pending[word_index])
2447 clear_bit(word_index, &vcpu->arch.irq_summary);
ecfc79c7 2448 kvm_queue_interrupt(vcpu, irq);
6aa8b732
AK		 2449}
2450
f460ee43
JK		 2451static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2452 struct kvm_run *kvm_run)
2453{
2454 vmx_update_window_states(vcpu);
2455
3b86cd99
JK		 2456 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2457 if (vcpu->arch.nmi_window_open) {
2458 vcpu->arch.nmi_pending = false;
2459 vcpu->arch.nmi_injected = true;
2460 } else {
2461 enable_nmi_window(vcpu);
487b391d
JK		 2462 return;
2463 }
3b86cd99
JK		 2464 }
2465 if (vcpu->arch.nmi_injected) {
2466 vmx_inject_nmi(vcpu);
2467 if (vcpu->arch.nmi_pending || kvm_run->request_nmi_window)
487b391d 2468 enable_nmi_window(vcpu);
3b86cd99
JK		 2469 else if (vcpu->arch.irq_summary
2470 || kvm_run->request_interrupt_window)
2471 enable_irq_window(vcpu);
2472 return;
487b391d 2473 }
3b86cd99
JK		 2474 if (!vcpu->arch.nmi_window_open || kvm_run->request_nmi_window)
2475 enable_nmi_window(vcpu);
487b391d 2476
f460ee43
JK		 2477 if (vcpu->arch.interrupt_window_open) {
2478 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2479 kvm_do_inject_irq(vcpu);
2480
2481 if (vcpu->arch.interrupt.pending)
2482 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2483 }
ad312c7c
ZX		 2484 if (!vcpu->arch.interrupt_window_open &&
2485 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
f460ee43 2486 enable_irq_window(vcpu);
6aa8b732
AK		 2487}
2488
cbc94022
IE		 2489static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2490{
2491 int ret;
2492 struct kvm_userspace_memory_region tss_mem = {
2493 .slot = 8,
2494 .guest_phys_addr = addr,
2495 .memory_size = PAGE_SIZE * 3,
2496 .flags = 0,
2497 };
2498
2499 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2500 if (ret)
2501 return ret;
bfc6d222 2502 kvm->arch.tss_addr = addr;
cbc94022
IE		 2503 return 0;
2504}
2505
6aa8b732
AK		 2506static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2507{
2508 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2509
2510 set_debugreg(dbg->bp[0], 0);
2511 set_debugreg(dbg->bp[1], 1);
2512 set_debugreg(dbg->bp[2], 2);
2513 set_debugreg(dbg->bp[3], 3);
2514
2515 if (dbg->singlestep) {
2516 unsigned long flags;
2517
2518 flags = vmcs_readl(GUEST_RFLAGS);
2519 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2520 vmcs_writel(GUEST_RFLAGS, flags);
2521 }
2522}
2523
2524static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2525 int vec, u32 err_code)
2526{
b3f37707
NK		 2527 /*
2528 * Instruction with address size override prefix opcode 0x67
2529 * Cause the #SS fault with 0 error code in VM86 mode.
2530 */
2531 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 2532 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2533 return 1;
77ab6db0
JK		 2534 /*
2535 * Forward all other exceptions that are valid in real mode.
2536 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2537 * the required debugging infrastructure rework.
2538 */
2539 switch (vec) {
2540 case DE_VECTOR:
2541 case DB_VECTOR:
2542 case BP_VECTOR:
2543 case OF_VECTOR:
2544 case BR_VECTOR:
2545 case UD_VECTOR:
2546 case DF_VECTOR:
2547 case SS_VECTOR:
2548 case GP_VECTOR:
2549 case MF_VECTOR:
2550 kvm_queue_exception(vcpu, vec);
2551 return 1;
2552 }
6aa8b732
AK		 2553 return 0;
2554}
2555
2556static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2557{
1155f76a 2558 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 2559 u32 intr_info, error_code;
2560 unsigned long cr2, rip;
2561 u32 vect_info;
2562 enum emulation_result er;
2563
1155f76a 2564 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2565 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2566
2567 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 2568 !is_page_fault(intr_info))
6aa8b732 2569 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 2570 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 2571
85f455f7 2572 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732 2573 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
ad312c7c
ZX		 2574 set_bit(irq, vcpu->arch.irq_pending);
2575 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
6aa8b732
AK		 2576 }
2577
e4a41889 2578 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2579 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2580
2581 if (is_no_device(intr_info)) {
5fd86fcf 2582 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2583 return 1;
2584 }
2585
7aa81cc0 2586 if (is_invalid_opcode(intr_info)) {
571008da 2587 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2588 if (er != EMULATE_DONE)
7ee5d940 2589 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2590 return 1;
2591 }
2592
6aa8b732 2593 error_code = 0;
5fdbf976 2594 rip = kvm_rip_read(vcpu);
2e11384c 2595 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2596 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2597 if (is_page_fault(intr_info)) {
1439442c
SY		 2598 /* EPT won't cause page fault directly */
2599 if (vm_need_ept())
2600 BUG();
6aa8b732 2601 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2714d1d3
FEL		 2602 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2603 (u32)((u64)cr2 >> 32), handler);
f7d9238f 2604 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
577bdc49 2605 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2606 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2607 }
2608
ad312c7c 2609 if (vcpu->arch.rmode.active &&
6aa8b732 2610 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2611 error_code)) {
ad312c7c
ZX		 2612 if (vcpu->arch.halt_request) {
2613 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2614 return kvm_emulate_halt(vcpu);
2615 }
6aa8b732 2616 return 1;
72d6e5a0 2617 }
6aa8b732 2618
d77c26fc
MD		 2619 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2620 (INTR_TYPE_EXCEPTION | 1)) {
6aa8b732
AK		 2621 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2622 return 0;
2623 }
2624 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2625 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2626 kvm_run->ex.error_code = error_code;
2627 return 0;
2628}
2629
2630static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2631 struct kvm_run *kvm_run)
2632{
1165f5fe 2633 ++vcpu->stat.irq_exits;
2714d1d3 2634 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
6aa8b732
AK		 2635 return 1;
2636}
2637
988ad74f
AK		 2638static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2639{
2640 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2641 return 0;
2642}
6aa8b732 2643
6aa8b732
AK		 2644static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2645{
bfdaab09 2646 unsigned long exit_qualification;
039576c0
AK		 2647 int size, down, in, string, rep;
2648 unsigned port;
6aa8b732 2649
1165f5fe 2650 ++vcpu->stat.io_exits;
bfdaab09 2651 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2652 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2653
2654 if (string) {
3427318f
LV		 2655 if (emulate_instruction(vcpu,
2656 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2657 return 0;
2658 return 1;
2659 }
2660
2661 size = (exit_qualification & 7) + 1;
2662 in = (exit_qualification & 8) != 0;
039576c0 2663 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 2664 rep = (exit_qualification & 32) != 0;
2665 port = exit_qualification >> 16;
e70669ab 2666
3090dd73 2667 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 2668}
2669
102d8325
IM		 2670static void
2671vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2672{
2673 /*
2674 * Patch in the VMCALL instruction:
2675 */
2676 hypercall[0] = 0x0f;
2677 hypercall[1] = 0x01;
2678 hypercall[2] = 0xc1;
102d8325
IM		 2679}
2680
6aa8b732
AK		 2681static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2682{
bfdaab09 2683 unsigned long exit_qualification;
6aa8b732
AK		 2684 int cr;
2685 int reg;
2686
bfdaab09 2687 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2688 cr = exit_qualification & 15;
2689 reg = (exit_qualification >> 8) & 15;
2690 switch ((exit_qualification >> 4) & 3) {
2691 case 0: /* mov to cr */
5fdbf976
MT		 2692 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2693 (u32)kvm_register_read(vcpu, reg),
2694 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2695 handler);
6aa8b732
AK		 2696 switch (cr) {
2697 case 0:
5fdbf976 2698 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2699 skip_emulated_instruction(vcpu);
2700 return 1;
2701 case 3:
5fdbf976 2702 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2703 skip_emulated_instruction(vcpu);
2704 return 1;
2705 case 4:
5fdbf976 2706 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2707 skip_emulated_instruction(vcpu);
2708 return 1;
2709 case 8:
5fdbf976 2710 kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
6aa8b732 2711 skip_emulated_instruction(vcpu);
e5314067
AK		 2712 if (irqchip_in_kernel(vcpu->kvm))
2713 return 1;
253abdee
YS		 2714 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2715 return 0;
6aa8b732
AK		 2716 };
2717 break;
25c4c276 2718 case 2: /* clts */
5fd86fcf 2719 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2720 vcpu->arch.cr0 &= ~X86_CR0_TS;
2721 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2722 vmx_fpu_activate(vcpu);
2714d1d3 2723 KVMTRACE_0D(CLTS, vcpu, handler);
25c4c276
AL		 2724 skip_emulated_instruction(vcpu);
2725 return 1;
6aa8b732
AK		 2726 case 1: /*mov from cr*/
2727 switch (cr) {
2728 case 3:
5fdbf976 2729 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2714d1d3 2730 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
5fdbf976
MT		 2731 (u32)kvm_register_read(vcpu, reg),
2732 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2714d1d3 2733 handler);
6aa8b732
AK		 2734 skip_emulated_instruction(vcpu);
2735 return 1;
2736 case 8:
5fdbf976 2737 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2714d1d3 2738 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
5fdbf976 2739 (u32)kvm_register_read(vcpu, reg), handler);
6aa8b732
AK		 2740 skip_emulated_instruction(vcpu);
2741 return 1;
2742 }
2743 break;
2744 case 3: /* lmsw */
2d3ad1f4 2745 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2746
2747 skip_emulated_instruction(vcpu);
2748 return 1;
2749 default:
2750 break;
2751 }
2752 kvm_run->exit_reason = 0;
f0242478 2753 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2754 (int)(exit_qualification >> 4) & 3, cr);
2755 return 0;
2756}
2757
2758static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2759{
bfdaab09 2760 unsigned long exit_qualification;
6aa8b732
AK		 2761 unsigned long val;
2762 int dr, reg;
2763
2764 /*
2765 * FIXME: this code assumes the host is debugging the guest.
2766 * need to deal with guest debugging itself too.
2767 */
bfdaab09 2768 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2769 dr = exit_qualification & 7;
2770 reg = (exit_qualification >> 8) & 15;
6aa8b732
AK		 2771 if (exit_qualification & 16) {
2772 /* mov from dr */
2773 switch (dr) {
2774 case 6:
2775 val = 0xffff0ff0;
2776 break;
2777 case 7:
2778 val = 0x400;
2779 break;
2780 default:
2781 val = 0;
2782 }
5fdbf976 2783 kvm_register_write(vcpu, reg, val);
2714d1d3 2784 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
6aa8b732
AK		 2785 } else {
2786 /* mov to dr */
2787 }
6aa8b732
AK		 2788 skip_emulated_instruction(vcpu);
2789 return 1;
2790}
2791
2792static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2793{
06465c5a
AK		 2794 kvm_emulate_cpuid(vcpu);
2795 return 1;
6aa8b732
AK		 2796}
2797
2798static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2799{
ad312c7c 2800 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2801 u64 data;
2802
2803 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 2804 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2805 return 1;
2806 }
2807
2714d1d3
FEL		 2808 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2809 handler);
2810
6aa8b732 2811 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 2812 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2813 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 2814 skip_emulated_instruction(vcpu);
2815 return 1;
2816}
2817
2818static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2819{
ad312c7c
ZX		 2820 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2821 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2822 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 2823
2714d1d3
FEL		 2824 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2825 handler);
2826
6aa8b732 2827 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 2828 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2829 return 1;
2830 }
2831
2832 skip_emulated_instruction(vcpu);
2833 return 1;
2834}
2835
6e5d865c
YS		 2836static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2837 struct kvm_run *kvm_run)
2838{
2839 return 1;
2840}
2841
6aa8b732
AK		 2842static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2843 struct kvm_run *kvm_run)
2844{
85f455f7
ED		 2845 u32 cpu_based_vm_exec_control;
2846
2847 /* clear pending irq */
2848 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2849 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2850 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3
FEL		 2851
2852 KVMTRACE_0D(PEND_INTR, vcpu, handler);
a26bf12a 2853 ++vcpu->stat.irq_window_exits;
2714d1d3 2854
c1150d8c
DL		 2855 /*
2856 * If the user space waits to inject interrupts, exit as soon as
2857 * possible
2858 */
2859 if (kvm_run->request_interrupt_window &&
ad312c7c 2860 !vcpu->arch.irq_summary) {
c1150d8c 2861 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 2862 return 0;
2863 }
6aa8b732
AK		 2864 return 1;
2865}
2866
2867static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2868{
2869 skip_emulated_instruction(vcpu);
d3bef15f 2870 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2871}
2872
c21415e8
IM		 2873static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2874{
510043da 2875 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2876 kvm_emulate_hypercall(vcpu);
2877 return 1;
c21415e8
IM		 2878}
2879
a7052897
MT		 2880static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2881{
2882 u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2883
2884 kvm_mmu_invlpg(vcpu, exit_qualification);
2885 skip_emulated_instruction(vcpu);
2886 return 1;
2887}
2888
e5edaa01
ED		 2889static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2890{
2891 skip_emulated_instruction(vcpu);
2892 /* TODO: Add support for VT-d/pass-through device */
2893 return 1;
2894}
2895
f78e0e2e
SY		 2896static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2897{
2898 u64 exit_qualification;
2899 enum emulation_result er;
2900 unsigned long offset;
2901
2902 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2903 offset = exit_qualification & 0xffful;
2904
2905 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2906
2907 if (er != EMULATE_DONE) {
2908 printk(KERN_ERR
2909 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2910 offset);
2911 return -ENOTSUPP;
2912 }
2913 return 1;
2914}
2915
37817f29
IE		 2916static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2917{
60637aac 2918 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 2919 unsigned long exit_qualification;
2920 u16 tss_selector;
2921 int reason;
2922
2923 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2924
2925 reason = (u32)exit_qualification >> 30;
60637aac
JK		 2926 if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
2927 (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
2928 (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
2929 == INTR_TYPE_NMI_INTR) {
2930 vcpu->arch.nmi_injected = false;
2931 if (cpu_has_virtual_nmis())
2932 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2933 GUEST_INTR_STATE_NMI);
2934 }
37817f29
IE		 2935 tss_selector = exit_qualification;
2936
2937 return kvm_task_switch(vcpu, tss_selector, reason);
2938}
2939
1439442c
SY		 2940static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2941{
2942 u64 exit_qualification;
2943 enum emulation_result er;
2944 gpa_t gpa;
2945 unsigned long hva;
2946 int gla_validity;
2947 int r;
2948
2949 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2950
2951 if (exit_qualification & (1 << 6)) {
2952 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2953 return -ENOTSUPP;
2954 }
2955
2956 gla_validity = (exit_qualification >> 7) & 0x3;
2957 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2958 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2959 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2960 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2961 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2962 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2963 (long unsigned int)exit_qualification);
2964 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2965 kvm_run->hw.hardware_exit_reason = 0;
2966 return -ENOTSUPP;
2967 }
2968
2969 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2970 hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2971 if (!kvm_is_error_hva(hva)) {
2972 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2973 if (r < 0) {
2974 printk(KERN_ERR "EPT: Not enough memory!\n");
2975 return -ENOMEM;
2976 }
2977 return 1;
2978 } else {
2979 /* must be MMIO */
2980 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2981
2982 if (er == EMULATE_FAIL) {
2983 printk(KERN_ERR
2984 "EPT: Fail to handle EPT violation vmexit!er is %d\n",
2985 er);
2986 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2987 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2988 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2989 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2990 (long unsigned int)exit_qualification);
2991 return -ENOTSUPP;
2992 } else if (er == EMULATE_DO_MMIO)
2993 return 0;
2994 }
2995 return 1;
2996}
2997
f08864b4
SY		 2998static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2999{
3000 u32 cpu_based_vm_exec_control;
3001
3002 /* clear pending NMI */
3003 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3004 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3005 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3006 ++vcpu->stat.nmi_window_exits;
3007
487b391d
JK		 3008 /*
3009 * If the user space waits to inject a NMI, exit as soon as possible
3010 */
3011 if (kvm_run->request_nmi_window && !vcpu->arch.nmi_pending) {
3012 kvm_run->exit_reason = KVM_EXIT_NMI_WINDOW_OPEN;
3013 return 0;
3014 }
3015
f08864b4
SY		 3016 return 1;
3017}
3018
ea953ef0
MG		 3019static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3020 struct kvm_run *kvm_run)
3021{
3022 struct vcpu_vmx *vmx = to_vmx(vcpu);
3023 int err;
3024
3025 preempt_enable();
3026 local_irq_enable();
3027
3028 while (!guest_state_valid(vcpu)) {
3029 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3030
3031 switch (err) {
3032 case EMULATE_DONE:
3033 break;
3034 case EMULATE_DO_MMIO:
3035 kvm_report_emulation_failure(vcpu, "mmio");
3036 /* TODO: Handle MMIO */
3037 return;
3038 default:
3039 kvm_report_emulation_failure(vcpu, "emulation failure");
3040 return;
3041 }
3042
3043 if (signal_pending(current))
3044 break;
3045 if (need_resched())
3046 schedule();
3047 }
3048
3049 local_irq_disable();
3050 preempt_disable();
3051
3052 /* Guest state should be valid now, no more emulation should be needed */
3053 vmx->emulation_required = 0;
3054}
3055
6aa8b732
AK		 3056/*
3057 * The exit handlers return 1 if the exit was handled fully and guest execution
3058 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3059 * to be done to userspace and return 0.
3060 */
3061static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3062 struct kvm_run *kvm_run) = {
3063 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3064 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3065 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3066 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3067 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3068 [EXIT_REASON_CR_ACCESS] = handle_cr,
3069 [EXIT_REASON_DR_ACCESS] = handle_dr,
3070 [EXIT_REASON_CPUID] = handle_cpuid,
3071 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3072 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3073 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3074 [EXIT_REASON_HLT] = handle_halt,
a7052897 3075 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3076 [EXIT_REASON_VMCALL] = handle_vmcall,
f78e0e2e
SY		 3077 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3078 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3079 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3080 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
1439442c 3081 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6aa8b732
AK		 3082};
3083
3084static const int kvm_vmx_max_exit_handlers =
50a3485c 3085 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3086
3087/*
3088 * The guest has exited. See if we can fix it or if we need userspace
3089 * assistance.
3090 */
3091static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3092{
6aa8b732 3093 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78 3094 struct vcpu_vmx *vmx = to_vmx(vcpu);
1155f76a 3095 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3096
5fdbf976
MT		 3097 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3098 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
2714d1d3 3099
1439442c
SY		 3100 /* Access CR3 don't cause VMExit in paging mode, so we need
3101 * to sync with guest real CR3. */
3102 if (vm_need_ept() && is_paging(vcpu)) {
3103 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3104 ept_load_pdptrs(vcpu);
3105 }
3106
29bd8a78
AK		 3107 if (unlikely(vmx->fail)) {
3108 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3109 kvm_run->fail_entry.hardware_entry_failure_reason
3110 = vmcs_read32(VM_INSTRUCTION_ERROR);
3111 return 0;
3112 }
6aa8b732 3113
d77c26fc 3114 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3115 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3116 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3117 exit_reason != EXIT_REASON_TASK_SWITCH))
3118 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3119 "(0x%x) and exit reason is 0x%x\n",
3120 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3121
3122 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3123 if (vcpu->arch.interrupt_window_open) {
3124 vmx->soft_vnmi_blocked = 0;
3125 vcpu->arch.nmi_window_open = 1;
3126 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3127 (kvm_run->request_nmi_window || vcpu->arch.nmi_pending)) {
3128 /*
3129 * This CPU don't support us in finding the end of an
3130 * NMI-blocked window if the guest runs with IRQs
3131 * disabled. So we pull the trigger after 1 s of
3132 * futile waiting, but inform the user about this.
3133 */
3134 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3135 "state on VCPU %d after 1 s timeout\n",
3136 __func__, vcpu->vcpu_id);
3137 vmx->soft_vnmi_blocked = 0;
3138 vmx->vcpu.arch.nmi_window_open = 1;
3139 }
3140
3141 /*
3142 * If the user space waits to inject an NNI, exit ASAP
3143 */
3144 if (vcpu->arch.nmi_window_open && kvm_run->request_nmi_window
3145 && !vcpu->arch.nmi_pending) {
3146 kvm_run->exit_reason = KVM_EXIT_NMI_WINDOW_OPEN;
3147 ++vcpu->stat.nmi_window_exits;
3148 return 0;
3149 }
3150 }
3151
6aa8b732
AK		 3152 if (exit_reason < kvm_vmx_max_exit_handlers
3153 && kvm_vmx_exit_handlers[exit_reason])
3154 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3155 else {
3156 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3157 kvm_run->hw.hardware_exit_reason = exit_reason;
3158 }
3159 return 0;
3160}
3161
6e5d865c
YS		 3162static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3163{
3164 int max_irr, tpr;
3165
3166 if (!vm_need_tpr_shadow(vcpu->kvm))
3167 return;
3168
3169 if (!kvm_lapic_enabled(vcpu) ||
3170 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3171 vmcs_write32(TPR_THRESHOLD, 0);
3172 return;
3173 }
3174
3175 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3176 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3177}
3178
cf393f75
AK		 3179static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3180{
3181 u32 exit_intr_info;
668f612f 3182 u32 idt_vectoring_info;
cf393f75
AK		 3183 bool unblock_nmi;
3184 u8 vector;
668f612f
AK		 3185 int type;
3186 bool idtv_info_valid;
35920a35 3187 u32 error;
cf393f75
AK		 3188
3189 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3190 if (cpu_has_virtual_nmis()) {
3191 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3192 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3193 /*
3194 * SDM 3: 25.7.1.2
3195 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3196 * a guest IRET fault.
3197 */
3198 if (unblock_nmi && vector != DF_VECTOR)
3199 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3200 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3201 } else if (unlikely(vmx->soft_vnmi_blocked))
3202 vmx->vnmi_blocked_time +=
3203 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f
AK		 3204
3205 idt_vectoring_info = vmx->idt_vectoring_info;
3206 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3207 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3208 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3209 if (vmx->vcpu.arch.nmi_injected) {
3210 /*
3211 * SDM 3: 25.7.1.2
3212 * Clear bit "block by NMI" before VM entry if a NMI delivery
3213 * faulted.
3214 */
3215 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3216 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3217 GUEST_INTR_STATE_NMI);
3218 else
3219 vmx->vcpu.arch.nmi_injected = false;
3220 }
35920a35
AK		 3221 kvm_clear_exception_queue(&vmx->vcpu);
3222 if (idtv_info_valid && type == INTR_TYPE_EXCEPTION) {
3223 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3224 error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3225 kvm_queue_exception_e(&vmx->vcpu, vector, error);
3226 } else
3227 kvm_queue_exception(&vmx->vcpu, vector);
3228 vmx->idt_vectoring_info = 0;
3229 }
f7d9238f
AK		 3230 kvm_clear_interrupt_queue(&vmx->vcpu);
3231 if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3232 kvm_queue_interrupt(&vmx->vcpu, vector);
3233 vmx->idt_vectoring_info = 0;
3234 }
cf393f75
AK		 3235}
3236
85f455f7
ED		 3237static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3238{
6e5d865c
YS		 3239 update_tpr_threshold(vcpu);
3240
33f089ca
JK		 3241 vmx_update_window_states(vcpu);
3242
3b86cd99
JK		 3243 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3244 if (vcpu->arch.interrupt.pending) {
3245 enable_nmi_window(vcpu);
3246 } else if (vcpu->arch.nmi_window_open) {
3247 vcpu->arch.nmi_pending = false;
3248 vcpu->arch.nmi_injected = true;
3249 } else {
3250 enable_nmi_window(vcpu);
f08864b4
SY		 3251 return;
3252 }
f08864b4 3253 }
3b86cd99
JK		 3254 if (vcpu->arch.nmi_injected) {
3255 vmx_inject_nmi(vcpu);
3256 if (vcpu->arch.nmi_pending)
3257 enable_nmi_window(vcpu);
3258 else if (kvm_cpu_has_interrupt(vcpu))
3259 enable_irq_window(vcpu);
3260 return;
3261 }
f7d9238f 3262 if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
33f089ca 3263 if (vcpu->arch.interrupt_window_open)
f7d9238f
AK		 3264 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3265 else
3266 enable_irq_window(vcpu);
3267 }
3268 if (vcpu->arch.interrupt.pending) {
3269 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3270 kvm_timer_intr_post(vcpu, vcpu->arch.interrupt.nr);
3271 }
85f455f7
ED		 3272}
3273
9c8cba37
AK		 3274/*
3275 * Failure to inject an interrupt should give us the information
3276 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3277 * when fetching the interrupt redirection bitmap in the real-mode
3278 * tss, this doesn't happen. So we do it ourselves.
3279 */
3280static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3281{
3282 vmx->rmode.irq.pending = 0;
5fdbf976 3283 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3284 return;
5fdbf976 3285 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3286 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3287 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3288 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3289 return;
3290 }
3291 vmx->idt_vectoring_info =
3292 VECTORING_INFO_VALID_MASK
3293 | INTR_TYPE_EXT_INTR
3294 | vmx->rmode.irq.vector;
3295}
3296
c801949d
AK		 3297#ifdef CONFIG_X86_64
3298#define R "r"
3299#define Q "q"
3300#else
3301#define R "e"
3302#define Q "l"
3303#endif
3304
04d2cc77 3305static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 3306{
a2fa3e9f 3307 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 3308 u32 intr_info;
e6adf283 3309
3b86cd99
JK		 3310 /* Record the guest's net vcpu time for enforced NMI injections. */
3311 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3312 vmx->entry_time = ktime_get();
3313
a89a8fb9
MG		 3314 /* Handle invalid guest state instead of entering VMX */
3315 if (vmx->emulation_required && emulate_invalid_guest_state) {
3316 handle_invalid_guest_state(vcpu, kvm_run);
3317 return;
3318 }
3319
5fdbf976
MT		 3320 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3321 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3322 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3323 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3324
e6adf283
AK		 3325 /*
3326 * Loading guest fpu may have cleared host cr0.ts
3327 */
3328 vmcs_writel(HOST_CR0, read_cr0());
3329
d77c26fc 3330 asm(
6aa8b732 3331 /* Store host registers */
c801949d
AK		 3332 "push %%"R"dx; push %%"R"bp;"
3333 "push %%"R"cx \n\t"
313dbd49
AK		 3334 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3335 "je 1f \n\t"
3336 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3337 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3338 "1: \n\t"
6aa8b732 3339 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3340 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3341 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3342 "mov %c[cr2](%0), %%"R"ax \n\t"
3343 "mov %%"R"ax, %%cr2 \n\t"
3344 "mov %c[rax](%0), %%"R"ax \n\t"
3345 "mov %c[rbx](%0), %%"R"bx \n\t"
3346 "mov %c[rdx](%0), %%"R"dx \n\t"
3347 "mov %c[rsi](%0), %%"R"si \n\t"
3348 "mov %c[rdi](%0), %%"R"di \n\t"
3349 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3350#ifdef CONFIG_X86_64
e08aa78a
AK		 3351 "mov %c[r8](%0), %%r8 \n\t"
3352 "mov %c[r9](%0), %%r9 \n\t"
3353 "mov %c[r10](%0), %%r10 \n\t"
3354 "mov %c[r11](%0), %%r11 \n\t"
3355 "mov %c[r12](%0), %%r12 \n\t"
3356 "mov %c[r13](%0), %%r13 \n\t"
3357 "mov %c[r14](%0), %%r14 \n\t"
3358 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3359#endif
c801949d
AK		 3360 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3361
6aa8b732 3362 /* Enter guest mode */
cd2276a7 3363 "jne .Llaunched \n\t"
4ecac3fd 3364 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3365 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3366 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3367 ".Lkvm_vmx_return: "
6aa8b732 3368 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3369 "xchg %0, (%%"R"sp) \n\t"
3370 "mov %%"R"ax, %c[rax](%0) \n\t"
3371 "mov %%"R"bx, %c[rbx](%0) \n\t"
3372 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3373 "mov %%"R"dx, %c[rdx](%0) \n\t"
3374 "mov %%"R"si, %c[rsi](%0) \n\t"
3375 "mov %%"R"di, %c[rdi](%0) \n\t"
3376 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3377#ifdef CONFIG_X86_64
e08aa78a
AK		 3378 "mov %%r8, %c[r8](%0) \n\t"
3379 "mov %%r9, %c[r9](%0) \n\t"
3380 "mov %%r10, %c[r10](%0) \n\t"
3381 "mov %%r11, %c[r11](%0) \n\t"
3382 "mov %%r12, %c[r12](%0) \n\t"
3383 "mov %%r13, %c[r13](%0) \n\t"
3384 "mov %%r14, %c[r14](%0) \n\t"
3385 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3386#endif
c801949d
AK		 3387 "mov %%cr2, %%"R"ax \n\t"
3388 "mov %%"R"ax, %c[cr2](%0) \n\t"
3389
3390 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3391 "setbe %c[fail](%0) \n\t"
3392 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3393 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3394 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3395 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3396 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3397 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3398 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3399 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3400 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3401 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3402 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3403#ifdef CONFIG_X86_64
ad312c7c
ZX		 3404 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3405 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3406 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3407 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3408 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3409 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3410 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3411 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3412#endif
ad312c7c 3413 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3414 : "cc", "memory"
c801949d 3415 , R"bx", R"di", R"si"
c2036300 3416#ifdef CONFIG_X86_64
c2036300
LV		 3417 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3418#endif
3419 );
6aa8b732 3420
5fdbf976
MT		 3421 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3422 vcpu->arch.regs_dirty = 0;
3423
1155f76a 3424 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3425 if (vmx->rmode.irq.pending)
3426 fixup_rmode_irq(vmx);
1155f76a 3427
33f089ca 3428 vmx_update_window_states(vcpu);
6aa8b732 3429
d77c26fc 3430 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3431 vmx->launched = 1;
1b6269db
AK		 3432
3433 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3434
3435 /* We need to handle NMIs before interrupts are enabled */
e4a41889 3436 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
f08864b4 3437 (intr_info & INTR_INFO_VALID_MASK)) {
2714d1d3 3438 KVMTRACE_0D(NMI, vcpu, handler);
1b6269db 3439 asm("int $2");
2714d1d3 3440 }
cf393f75
AK		 3441
3442 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3443}
3444
c801949d
AK		 3445#undef R
3446#undef Q
3447
6aa8b732
AK		 3448static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3449{
a2fa3e9f
GH		 3450 struct vcpu_vmx *vmx = to_vmx(vcpu);
3451
3452 if (vmx->vmcs) {
543e4243 3453 vcpu_clear(vmx);
a2fa3e9f
GH		 3454 free_vmcs(vmx->vmcs);
3455 vmx->vmcs = NULL;
6aa8b732
AK		 3456 }
3457}
3458
3459static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3460{
fb3f0f51
RR		 3461 struct vcpu_vmx *vmx = to_vmx(vcpu);
3462
2384d2b3
SY		 3463 spin_lock(&vmx_vpid_lock);
3464 if (vmx->vpid != 0)
3465 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3466 spin_unlock(&vmx_vpid_lock);
6aa8b732 3467 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3468 kfree(vmx->host_msrs);
3469 kfree(vmx->guest_msrs);
3470 kvm_vcpu_uninit(vcpu);
a4770347 3471 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3472}
3473
fb3f0f51 3474static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3475{
fb3f0f51 3476 int err;
c16f862d 3477 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3478 int cpu;
6aa8b732 3479
a2fa3e9f 3480 if (!vmx)
fb3f0f51
RR		 3481 return ERR_PTR(-ENOMEM);
3482
2384d2b3
SY		 3483 allocate_vpid(vmx);
3484
fb3f0f51
RR		 3485 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3486 if (err)
3487 goto free_vcpu;
965b58a5 3488
a2fa3e9f 3489 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3490 if (!vmx->guest_msrs) {
3491 err = -ENOMEM;
3492 goto uninit_vcpu;
3493 }
965b58a5 3494
a2fa3e9f
GH		 3495 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3496 if (!vmx->host_msrs)
fb3f0f51 3497 goto free_guest_msrs;
965b58a5 3498
a2fa3e9f
GH		 3499 vmx->vmcs = alloc_vmcs();
3500 if (!vmx->vmcs)
fb3f0f51 3501 goto free_msrs;
a2fa3e9f
GH		 3502
3503 vmcs_clear(vmx->vmcs);
3504
15ad7146
AK		 3505 cpu = get_cpu();
3506 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3507 err = vmx_vcpu_setup(vmx);
fb3f0f51 3508 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3509 put_cpu();
fb3f0f51
RR		 3510 if (err)
3511 goto free_vmcs;
5e4a0b3c
MT		 3512 if (vm_need_virtualize_apic_accesses(kvm))
3513 if (alloc_apic_access_page(kvm) != 0)
3514 goto free_vmcs;
fb3f0f51 3515
b7ebfb05
SY		 3516 if (vm_need_ept())
3517 if (alloc_identity_pagetable(kvm) != 0)
3518 goto free_vmcs;
3519
fb3f0f51
RR		 3520 return &vmx->vcpu;
3521
3522free_vmcs:
3523 free_vmcs(vmx->vmcs);
3524free_msrs:
3525 kfree(vmx->host_msrs);
3526free_guest_msrs:
3527 kfree(vmx->guest_msrs);
3528uninit_vcpu:
3529 kvm_vcpu_uninit(&vmx->vcpu);
3530free_vcpu:
a4770347 3531 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3532 return ERR_PTR(err);
6aa8b732
AK		 3533}
3534
002c7f7c
YS		 3535static void __init vmx_check_processor_compat(void *rtn)
3536{
3537 struct vmcs_config vmcs_conf;
3538
3539 *(int *)rtn = 0;
3540 if (setup_vmcs_config(&vmcs_conf) < 0)
3541 *(int *)rtn = -EIO;
3542 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3543 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3544 smp_processor_id());
3545 *(int *)rtn = -EIO;
3546 }
3547}
3548
67253af5
SY		 3549static int get_ept_level(void)
3550{
3551 return VMX_EPT_DEFAULT_GAW + 1;
3552}
3553
cbdd1bea 3554static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3555 .cpu_has_kvm_support = cpu_has_kvm_support,
3556 .disabled_by_bios = vmx_disabled_by_bios,
3557 .hardware_setup = hardware_setup,
3558 .hardware_unsetup = hardware_unsetup,
002c7f7c 3559 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3560 .hardware_enable = hardware_enable,
3561 .hardware_disable = hardware_disable,
774ead3a 3562 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
6aa8b732
AK		 3563
3564 .vcpu_create = vmx_create_vcpu,
3565 .vcpu_free = vmx_free_vcpu,
04d2cc77 3566 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3567
04d2cc77 3568 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3569 .vcpu_load = vmx_vcpu_load,
3570 .vcpu_put = vmx_vcpu_put,
3571
3572 .set_guest_debug = set_guest_debug,
04d2cc77 3573 .guest_debug_pre = kvm_guest_debug_pre,
6aa8b732
AK		 3574 .get_msr = vmx_get_msr,
3575 .set_msr = vmx_set_msr,
3576 .get_segment_base = vmx_get_segment_base,
3577 .get_segment = vmx_get_segment,
3578 .set_segment = vmx_set_segment,
2e4d2653 3579 .get_cpl = vmx_get_cpl,
6aa8b732 3580 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3581 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3582 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3583 .set_cr3 = vmx_set_cr3,
3584 .set_cr4 = vmx_set_cr4,
6aa8b732 3585 .set_efer = vmx_set_efer,
6aa8b732
AK		 3586 .get_idt = vmx_get_idt,
3587 .set_idt = vmx_set_idt,
3588 .get_gdt = vmx_get_gdt,
3589 .set_gdt = vmx_set_gdt,
5fdbf976 3590 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 3591 .get_rflags = vmx_get_rflags,
3592 .set_rflags = vmx_set_rflags,
3593
3594 .tlb_flush = vmx_flush_tlb,
6aa8b732 3595
6aa8b732 3596 .run = vmx_vcpu_run,
04d2cc77 3597 .handle_exit = kvm_handle_exit,
6aa8b732 3598 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 3599 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 3600 .get_irq = vmx_get_irq,
3601 .set_irq = vmx_inject_irq,
298101da
AK		 3602 .queue_exception = vmx_queue_exception,
3603 .exception_injected = vmx_exception_injected,
04d2cc77
AK		 3604 .inject_pending_irq = vmx_intr_assist,
3605 .inject_pending_vectors = do_interrupt_requests,
cbc94022
IE		 3606
3607 .set_tss_addr = vmx_set_tss_addr,
67253af5 3608 .get_tdp_level = get_ept_level,
6aa8b732
AK		 3609};
3610
3611static int __init vmx_init(void)
3612{
25c5f225 3613 void *va;
fdef3ad1
HQ		 3614 int r;
3615
3616 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3617 if (!vmx_io_bitmap_a)
3618 return -ENOMEM;
3619
3620 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3621 if (!vmx_io_bitmap_b) {
3622 r = -ENOMEM;
3623 goto out;
3624 }
3625
25c5f225
SY		 3626 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3627 if (!vmx_msr_bitmap) {
3628 r = -ENOMEM;
3629 goto out1;
3630 }
3631
fdef3ad1
HQ		 3632 /*
3633 * Allow direct access to the PC debug port (it is often used for I/O
3634 * delays, but the vmexits simply slow things down).
3635 */
25c5f225
SY		 3636 va = kmap(vmx_io_bitmap_a);
3637 memset(va, 0xff, PAGE_SIZE);
3638 clear_bit(0x80, va);
cd0536d7 3639 kunmap(vmx_io_bitmap_a);
fdef3ad1 3640
25c5f225
SY		 3641 va = kmap(vmx_io_bitmap_b);
3642 memset(va, 0xff, PAGE_SIZE);
cd0536d7 3643 kunmap(vmx_io_bitmap_b);
fdef3ad1 3644
25c5f225
SY		 3645 va = kmap(vmx_msr_bitmap);
3646 memset(va, 0xff, PAGE_SIZE);
3647 kunmap(vmx_msr_bitmap);
3648
2384d2b3
SY		 3649 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3650
cb498ea2 3651 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 3652 if (r)
25c5f225
SY		 3653 goto out2;
3654
3655 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3656 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3657 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3658 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3659 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
fdef3ad1 3660
5fdbcb9d 3661 if (vm_need_ept()) {
1439442c 3662 bypass_guest_pf = 0;
5fdbcb9d
SY		 3663 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3664 VMX_EPT_WRITABLE_MASK |
928d4bf7
SY		 3665 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT |
3666 VMX_EPT_IGMT_BIT);
534e38b4 3667 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
5fdbcb9d
SY		 3668 VMX_EPT_EXECUTABLE_MASK);
3669 kvm_enable_tdp();
3670 } else
3671 kvm_disable_tdp();
1439442c 3672
c7addb90
AK		 3673 if (bypass_guest_pf)
3674 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3675
1439442c
SY		 3676 ept_sync_global();
3677
fdef3ad1
HQ		 3678 return 0;
3679
25c5f225
SY		 3680out2:
3681 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 3682out1:
3683 __free_page(vmx_io_bitmap_b);
3684out:
3685 __free_page(vmx_io_bitmap_a);
3686 return r;
6aa8b732
AK		 3687}
3688
3689static void __exit vmx_exit(void)
3690{
25c5f225 3691 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 3692 __free_page(vmx_io_bitmap_b);
3693 __free_page(vmx_io_bitmap_a);
3694
cb498ea2 3695 kvm_exit();
6aa8b732
AK		 3696}
3697
3698module_init(vmx_init)
3699module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)