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Merge tag 'v3.10.105' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / megaraid / megaraid_sas.h
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c4a3e0a5 1/*
3f1530c1 2 * Linux MegaRAID driver for SAS based RAID controllers
c4a3e0a5 3 *
ae59057b 4 * Copyright (c) 2003-2012 LSI Corporation.
c4a3e0a5 5 *
3f1530c1
AR		 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
c4a3e0a5 10 *
3f1530c1
AR		 11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
c4a3e0a5 15 *
3f1530c1
AR		 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * FILE: megaraid_sas.h
21 *
22 * Authors: LSI Corporation
23 *
24 * Send feedback to: <megaraidlinux@lsi.com>
25 *
26 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
27 * ATTN: Linuxraid
c4a3e0a5
BS		 28 */
29
30#ifndef LSI_MEGARAID_SAS_H
31#define LSI_MEGARAID_SAS_H
32
a69b74d3 33/*
c4a3e0a5
BS		 34 * MegaRAID SAS Driver meta data
35 */
5eca4a67
AR		 36#define MEGASAS_VERSION "06.506.00.00-rc1"
37#define MEGASAS_RELDATE "Feb. 9, 2013"
38#define MEGASAS_EXT_VERSION "Sat. Feb. 9 17:00:00 PDT 2013"
0e98936c
SP		 39
40/*
41 * Device IDs
42 */
43#define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
af7a5647 44#define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
0e98936c 45#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
6610a6b3
YB		 46#define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
47#define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
87911122
YB		 48#define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
49#define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
9c915a8c 50#define PCI_DEVICE_ID_LSI_FUSION 0x005b
36807e67 51#define PCI_DEVICE_ID_LSI_INVADER 0x005d
0e98936c 52
c4a3e0a5
BS		 53/*
54 * =====================================
55 * MegaRAID SAS MFI firmware definitions
56 * =====================================
57 */
58
59/*
60 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
61 * protocol between the software and firmware. Commands are issued using
62 * "message frames"
63 */
64
a69b74d3 65/*
c4a3e0a5
BS		 66 * FW posts its state in upper 4 bits of outbound_msg_0 register
67 */
68#define MFI_STATE_MASK 0xF0000000
69#define MFI_STATE_UNDEFINED 0x00000000
70#define MFI_STATE_BB_INIT 0x10000000
71#define MFI_STATE_FW_INIT 0x40000000
72#define MFI_STATE_WAIT_HANDSHAKE 0x60000000
73#define MFI_STATE_FW_INIT_2 0x70000000
74#define MFI_STATE_DEVICE_SCAN 0x80000000
e3bbff9f 75#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
c4a3e0a5
BS		 76#define MFI_STATE_FLUSH_CACHE 0xA0000000
77#define MFI_STATE_READY 0xB0000000
78#define MFI_STATE_OPERATIONAL 0xC0000000
79#define MFI_STATE_FAULT 0xF0000000
7e70e733
AR		 80#define MFI_RESET_REQUIRED 0x00000001
81#define MFI_RESET_ADAPTER 0x00000002
c4a3e0a5
BS		 82#define MEGAMFI_FRAME_SIZE 64
83
a69b74d3 84/*
c4a3e0a5
BS		 85 * During FW init, clear pending cmds & reset state using inbound_msg_0
86 *
87 * ABORT : Abort all pending cmds
88 * READY : Move from OPERATIONAL to READY state; discard queue info
89 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
90 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
e3bbff9f
SP		 91 * HOTPLUG : Resume from Hotplug
92 * MFI_STOP_ADP : Send signal to FW to stop processing
c4a3e0a5 93 */
39a98554 94#define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
95#define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
96#define DIAG_WRITE_ENABLE (0x00000080)
97#define DIAG_RESET_ADAPTER (0x00000004)
98
99#define MFI_ADP_RESET 0x00000040
e3bbff9f 100#define MFI_INIT_ABORT 0x00000001
c4a3e0a5
BS		 101#define MFI_INIT_READY 0x00000002
102#define MFI_INIT_MFIMODE 0x00000004
103#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
e3bbff9f
SP		 104#define MFI_INIT_HOTPLUG 0x00000010
105#define MFI_STOP_ADP 0x00000020
106#define MFI_RESET_FLAGS MFI_INIT_READY| \
107 MFI_INIT_MFIMODE| \
108 MFI_INIT_ABORT
c4a3e0a5 109
a69b74d3 110/*
c4a3e0a5
BS		 111 * MFI frame flags
112 */
113#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
114#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
115#define MFI_FRAME_SGL32 0x0000
116#define MFI_FRAME_SGL64 0x0002
117#define MFI_FRAME_SENSE32 0x0000
118#define MFI_FRAME_SENSE64 0x0004
119#define MFI_FRAME_DIR_NONE 0x0000
120#define MFI_FRAME_DIR_WRITE 0x0008
121#define MFI_FRAME_DIR_READ 0x0010
122#define MFI_FRAME_DIR_BOTH 0x0018
f4c9a131 123#define MFI_FRAME_IEEE 0x0020
c4a3e0a5 124
a69b74d3 125/*
c4a3e0a5
BS		 126 * Definition for cmd_status
127 */
128#define MFI_CMD_STATUS_POLL_MODE 0xFF
129
a69b74d3 130/*
c4a3e0a5
BS		 131 * MFI command opcodes
132 */
133#define MFI_CMD_INIT 0x00
134#define MFI_CMD_LD_READ 0x01
135#define MFI_CMD_LD_WRITE 0x02
136#define MFI_CMD_LD_SCSI_IO 0x03
137#define MFI_CMD_PD_SCSI_IO 0x04
138#define MFI_CMD_DCMD 0x05
139#define MFI_CMD_ABORT 0x06
140#define MFI_CMD_SMP 0x07
141#define MFI_CMD_STP 0x08
e5f93a36 142#define MFI_CMD_INVALID 0xff
c4a3e0a5
BS		 143
144#define MR_DCMD_CTRL_GET_INFO 0x01010000
bdc6fb8d 145#define MR_DCMD_LD_GET_LIST 0x03010000
c4a3e0a5
BS		 146
147#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
148#define MR_FLUSH_CTRL_CACHE 0x01
149#define MR_FLUSH_DISK_CACHE 0x02
150
151#define MR_DCMD_CTRL_SHUTDOWN 0x01050000
31ea7088 152#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
c4a3e0a5
BS		 153#define MR_ENABLE_DRIVE_SPINDOWN 0x01
154
155#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
156#define MR_DCMD_CTRL_EVENT_GET 0x01040300
157#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
158#define MR_DCMD_LD_GET_PROPERTIES 0x03030000
159
160#define MR_DCMD_CLUSTER 0x08000000
161#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
162#define MR_DCMD_CLUSTER_RESET_LD 0x08010200
81e403ce 163#define MR_DCMD_PD_LIST_QUERY 0x02010100
c4a3e0a5 164
a69b74d3 165/*
c4a3e0a5
BS		 166 * MFI command completion codes
167 */
168enum MFI_STAT {
169 MFI_STAT_OK = 0x00,
170 MFI_STAT_INVALID_CMD = 0x01,
171 MFI_STAT_INVALID_DCMD = 0x02,
172 MFI_STAT_INVALID_PARAMETER = 0x03,
173 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
174 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
175 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
176 MFI_STAT_APP_IN_USE = 0x07,
177 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
178 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
179 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
180 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
181 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
182 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
183 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
184 MFI_STAT_FLASH_BUSY = 0x0f,
185 MFI_STAT_FLASH_ERROR = 0x10,
186 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
187 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
188 MFI_STAT_FLASH_NOT_OPEN = 0x13,
189 MFI_STAT_FLASH_NOT_STARTED = 0x14,
190 MFI_STAT_FLUSH_FAILED = 0x15,
191 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
192 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
193 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
194 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
195 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
196 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
197 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
198 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
199 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
200 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
201 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
202 MFI_STAT_MFC_HW_ERROR = 0x21,
203 MFI_STAT_NO_HW_PRESENT = 0x22,
204 MFI_STAT_NOT_FOUND = 0x23,
205 MFI_STAT_NOT_IN_ENCL = 0x24,
206 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
207 MFI_STAT_PD_TYPE_WRONG = 0x26,
208 MFI_STAT_PR_DISABLED = 0x27,
209 MFI_STAT_ROW_INDEX_INVALID = 0x28,
210 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
211 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
212 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
213 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
214 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
215 MFI_STAT_SCSI_IO_FAILED = 0x2e,
216 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
217 MFI_STAT_SHUTDOWN_FAILED = 0x30,
218 MFI_STAT_TIME_NOT_SET = 0x31,
219 MFI_STAT_WRONG_STATE = 0x32,
220 MFI_STAT_LD_OFFLINE = 0x33,
221 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
222 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
223 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
224 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
225 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
36807e67 226 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
c4a3e0a5
BS		 227
228 MFI_STAT_INVALID_STATUS = 0xFF
229};
230
231/*
232 * Number of mailbox bytes in DCMD message frame
233 */
234#define MFI_MBOX_SIZE 12
235
236enum MR_EVT_CLASS {
237
238 MR_EVT_CLASS_DEBUG = -2,
239 MR_EVT_CLASS_PROGRESS = -1,
240 MR_EVT_CLASS_INFO = 0,
241 MR_EVT_CLASS_WARNING = 1,
242 MR_EVT_CLASS_CRITICAL = 2,
243 MR_EVT_CLASS_FATAL = 3,
244 MR_EVT_CLASS_DEAD = 4,
245
246};
247
248enum MR_EVT_LOCALE {
249
250 MR_EVT_LOCALE_LD = 0x0001,
251 MR_EVT_LOCALE_PD = 0x0002,
252 MR_EVT_LOCALE_ENCL = 0x0004,
253 MR_EVT_LOCALE_BBU = 0x0008,
254 MR_EVT_LOCALE_SAS = 0x0010,
255 MR_EVT_LOCALE_CTRL = 0x0020,
256 MR_EVT_LOCALE_CONFIG = 0x0040,
257 MR_EVT_LOCALE_CLUSTER = 0x0080,
258 MR_EVT_LOCALE_ALL = 0xffff,
259
260};
261
262enum MR_EVT_ARGS {
263
264 MR_EVT_ARGS_NONE,
265 MR_EVT_ARGS_CDB_SENSE,
266 MR_EVT_ARGS_LD,
267 MR_EVT_ARGS_LD_COUNT,
268 MR_EVT_ARGS_LD_LBA,
269 MR_EVT_ARGS_LD_OWNER,
270 MR_EVT_ARGS_LD_LBA_PD_LBA,
271 MR_EVT_ARGS_LD_PROG,
272 MR_EVT_ARGS_LD_STATE,
273 MR_EVT_ARGS_LD_STRIP,
274 MR_EVT_ARGS_PD,
275 MR_EVT_ARGS_PD_ERR,
276 MR_EVT_ARGS_PD_LBA,
277 MR_EVT_ARGS_PD_LBA_LD,
278 MR_EVT_ARGS_PD_PROG,
279 MR_EVT_ARGS_PD_STATE,
280 MR_EVT_ARGS_PCI,
281 MR_EVT_ARGS_RATE,
282 MR_EVT_ARGS_STR,
283 MR_EVT_ARGS_TIME,
284 MR_EVT_ARGS_ECC,
81e403ce
YB		 285 MR_EVT_ARGS_LD_PROP,
286 MR_EVT_ARGS_PD_SPARE,
287 MR_EVT_ARGS_PD_INDEX,
288 MR_EVT_ARGS_DIAG_PASS,
289 MR_EVT_ARGS_DIAG_FAIL,
290 MR_EVT_ARGS_PD_LBA_LBA,
291 MR_EVT_ARGS_PORT_PHY,
292 MR_EVT_ARGS_PD_MISSING,
293 MR_EVT_ARGS_PD_ADDRESS,
294 MR_EVT_ARGS_BITMAP,
295 MR_EVT_ARGS_CONNECTOR,
296 MR_EVT_ARGS_PD_PD,
297 MR_EVT_ARGS_PD_FRU,
298 MR_EVT_ARGS_PD_PATHINFO,
299 MR_EVT_ARGS_PD_POWER_STATE,
300 MR_EVT_ARGS_GENERIC,
301};
c4a3e0a5 302
64896131 303
304#define SGE_BUFFER_SIZE 4096
81e403ce
YB		 305/*
306 * define constants for device list query options
307 */
308enum MR_PD_QUERY_TYPE {
309 MR_PD_QUERY_TYPE_ALL = 0,
310 MR_PD_QUERY_TYPE_STATE = 1,
311 MR_PD_QUERY_TYPE_POWER_STATE = 2,
312 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
313 MR_PD_QUERY_TYPE_SPEED = 4,
314 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
c4a3e0a5
BS		 315};
316
7e8a75f4
YB		 317#define MR_EVT_CFG_CLEARED 0x0004
318#define MR_EVT_LD_STATE_CHANGE 0x0051
319#define MR_EVT_PD_INSERTED 0x005b
320#define MR_EVT_PD_REMOVED 0x0070
321#define MR_EVT_LD_CREATED 0x008a
322#define MR_EVT_LD_DELETED 0x008b
323#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
324#define MR_EVT_LD_OFFLINE 0x00fc
325#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
326#define MAX_LOGICAL_DRIVES 64
327
81e403ce
YB		 328enum MR_PD_STATE {
329 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
330 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
331 MR_PD_STATE_HOT_SPARE = 0x02,
332 MR_PD_STATE_OFFLINE = 0x10,
333 MR_PD_STATE_FAILED = 0x11,
334 MR_PD_STATE_REBUILD = 0x14,
335 MR_PD_STATE_ONLINE = 0x18,
336 MR_PD_STATE_COPYBACK = 0x20,
337 MR_PD_STATE_SYSTEM = 0x40,
338 };
339
340
341 /*
342 * defines the physical drive address structure
343 */
344struct MR_PD_ADDRESS {
345 u16 deviceId;
346 u16 enclDeviceId;
347
348 union {
349 struct {
350 u8 enclIndex;
351 u8 slotNumber;
352 } mrPdAddress;
353 struct {
354 u8 enclPosition;
355 u8 enclConnectorIndex;
356 } mrEnclAddress;
357 };
358 u8 scsiDevType;
359 union {
360 u8 connectedPortBitmap;
361 u8 connectedPortNumbers;
362 };
363 u64 sasAddr[2];
364} __packed;
365
366/*
367 * defines the physical drive list structure
368 */
369struct MR_PD_LIST {
370 u32 size;
371 u32 count;
372 struct MR_PD_ADDRESS addr[1];
373} __packed;
374
375struct megasas_pd_list {
376 u16 tid;
377 u8 driveType;
378 u8 driveState;
379} __packed;
380
bdc6fb8d
YB		 381 /*
382 * defines the logical drive reference structure
383 */
384union MR_LD_REF {
385 struct {
386 u8 targetId;
387 u8 reserved;
388 u16 seqNum;
389 };
390 u32 ref;
391} __packed;
392
393/*
394 * defines the logical drive list structure
395 */
396struct MR_LD_LIST {
397 u32 ldCount;
398 u32 reserved;
399 struct {
400 union MR_LD_REF ref;
401 u8 state;
402 u8 reserved[3];
403 u64 size;
404 } ldList[MAX_LOGICAL_DRIVES];
405} __packed;
406
c4a3e0a5
BS		 407/*
408 * SAS controller properties
409 */
410struct megasas_ctrl_prop {
411
412 u16 seq_num;
413 u16 pred_fail_poll_interval;
414 u16 intr_throttle_count;
415 u16 intr_throttle_timeouts;
416 u8 rebuild_rate;
417 u8 patrol_read_rate;
418 u8 bgi_rate;
419 u8 cc_rate;
420 u8 recon_rate;
421 u8 cache_flush_interval;
422 u8 spinup_drv_count;
423 u8 spinup_delay;
424 u8 cluster_enable;
425 u8 coercion_mode;
426 u8 alarm_enable;
427 u8 disable_auto_rebuild;
428 u8 disable_battery_warn;
429 u8 ecc_bucket_size;
430 u16 ecc_bucket_leak_rate;
431 u8 restore_hotspare_on_insertion;
432 u8 expose_encl_devices;
39a98554 433 u8 maintainPdFailHistory;
434 u8 disallowHostRequestReordering;
435 u8 abortCCOnError;
436 u8 loadBalanceMode;
437 u8 disableAutoDetectBackplane;
438
439 u8 snapVDSpace;
440
441 /*
442 * Add properties that can be controlled by
443 * a bit in the following structure.
444 */
39a98554 445 struct {
446 u32 copyBackDisabled : 1;
447 u32 SMARTerEnabled : 1;
448 u32 prCorrectUnconfiguredAreas : 1;
449 u32 useFdeOnly : 1;
450 u32 disableNCQ : 1;
451 u32 SSDSMARTerEnabled : 1;
452 u32 SSDPatrolReadEnabled : 1;
453 u32 enableSpinDownUnconfigured : 1;
454 u32 autoEnhancedImport : 1;
455 u32 enableSecretKeyControl : 1;
456 u32 disableOnlineCtrlReset : 1;
457 u32 allowBootWithPinnedCache : 1;
458 u32 disableSpinDownHS : 1;
459 u32 enableJBOD : 1;
460 u32 reserved :18;
461 } OnOffProperties;
462 u8 autoSnapVDSpace;
463 u8 viewSpace;
464 u16 spinDownTime;
465 u8 reserved[24];
81e403ce 466} __packed;
c4a3e0a5
BS		 467
468/*
469 * SAS controller information
470 */
471struct megasas_ctrl_info {
472
473 /*
474 * PCI device information
475 */
476 struct {
477
478 u16 vendor_id;
479 u16 device_id;
480 u16 sub_vendor_id;
481 u16 sub_device_id;
482 u8 reserved[24];
483
484 } __attribute__ ((packed)) pci;
485
486 /*
487 * Host interface information
488 */
489 struct {
490
491 u8 PCIX:1;
492 u8 PCIE:1;
493 u8 iSCSI:1;
494 u8 SAS_3G:1;
495 u8 reserved_0:4;
496 u8 reserved_1[6];
497 u8 port_count;
498 u64 port_addr[8];
499
500 } __attribute__ ((packed)) host_interface;
501
502 /*
503 * Device (backend) interface information
504 */
505 struct {
506
507 u8 SPI:1;
508 u8 SAS_3G:1;
509 u8 SATA_1_5G:1;
510 u8 SATA_3G:1;
511 u8 reserved_0:4;
512 u8 reserved_1[6];
513 u8 port_count;
514 u64 port_addr[8];
515
516 } __attribute__ ((packed)) device_interface;
517
518 /*
519 * List of components residing in flash. All str are null terminated
520 */
521 u32 image_check_word;
522 u32 image_component_count;
523
524 struct {
525
526 char name[8];
527 char version[32];
528 char build_date[16];
529 char built_time[16];
530
531 } __attribute__ ((packed)) image_component[8];
532
533 /*
534 * List of flash components that have been flashed on the card, but
535 * are not in use, pending reset of the adapter. This list will be
536 * empty if a flash operation has not occurred. All stings are null
537 * terminated
538 */
539 u32 pending_image_component_count;
540
541 struct {
542
543 char name[8];
544 char version[32];
545 char build_date[16];
546 char build_time[16];
547
548 } __attribute__ ((packed)) pending_image_component[8];
549
550 u8 max_arms;
551 u8 max_spans;
552 u8 max_arrays;
553 u8 max_lds;
554
555 char product_name[80];
556 char serial_no[32];
557
558 /*
559 * Other physical/controller/operation information. Indicates the
560 * presence of the hardware
561 */
562 struct {
563
564 u32 bbu:1;
565 u32 alarm:1;
566 u32 nvram:1;
567 u32 uart:1;
568 u32 reserved:28;
569
570 } __attribute__ ((packed)) hw_present;
571
572 u32 current_fw_time;
573
574 /*
575 * Maximum data transfer sizes
576 */
577 u16 max_concurrent_cmds;
578 u16 max_sge_count;
579 u32 max_request_size;
580
581 /*
582 * Logical and physical device counts
583 */
584 u16 ld_present_count;
585 u16 ld_degraded_count;
586 u16 ld_offline_count;
587
588 u16 pd_present_count;
589 u16 pd_disk_present_count;
590 u16 pd_disk_pred_failure_count;
591 u16 pd_disk_failed_count;
592
593 /*
594 * Memory size information
595 */
596 u16 nvram_size;
597 u16 memory_size;
598 u16 flash_size;
599
600 /*
601 * Error counters
602 */
603 u16 mem_correctable_error_count;
604 u16 mem_uncorrectable_error_count;
605
606 /*
607 * Cluster information
608 */
609 u8 cluster_permitted;
610 u8 cluster_active;
611
612 /*
613 * Additional max data transfer sizes
614 */
615 u16 max_strips_per_io;
616
617 /*
618 * Controller capabilities structures
619 */
620 struct {
621
622 u32 raid_level_0:1;
623 u32 raid_level_1:1;
624 u32 raid_level_5:1;
625 u32 raid_level_1E:1;
626 u32 raid_level_6:1;
627 u32 reserved:27;
628
629 } __attribute__ ((packed)) raid_levels;
630
631 struct {
632
633 u32 rbld_rate:1;
634 u32 cc_rate:1;
635 u32 bgi_rate:1;
636 u32 recon_rate:1;
637 u32 patrol_rate:1;
638 u32 alarm_control:1;
639 u32 cluster_supported:1;
640 u32 bbu:1;
641 u32 spanning_allowed:1;
642 u32 dedicated_hotspares:1;
643 u32 revertible_hotspares:1;
644 u32 foreign_config_import:1;
645 u32 self_diagnostic:1;
646 u32 mixed_redundancy_arr:1;
647 u32 global_hot_spares:1;
648 u32 reserved:17;
649
650 } __attribute__ ((packed)) adapter_operations;
651
652 struct {
653
654 u32 read_policy:1;
655 u32 write_policy:1;
656 u32 io_policy:1;
657 u32 access_policy:1;
658 u32 disk_cache_policy:1;
659 u32 reserved:27;
660
661 } __attribute__ ((packed)) ld_operations;
662
663 struct {
664
665 u8 min;
666 u8 max;
667 u8 reserved[2];
668
669 } __attribute__ ((packed)) stripe_sz_ops;
670
671 struct {
672
673 u32 force_online:1;
674 u32 force_offline:1;
675 u32 force_rebuild:1;
676 u32 reserved:29;
677
678 } __attribute__ ((packed)) pd_operations;
679
680 struct {
681
682 u32 ctrl_supports_sas:1;
683 u32 ctrl_supports_sata:1;
684 u32 allow_mix_in_encl:1;
685 u32 allow_mix_in_ld:1;
686 u32 allow_sata_in_cluster:1;
687 u32 reserved:27;
688
689 } __attribute__ ((packed)) pd_mix_support;
690
691 /*
692 * Define ECC single-bit-error bucket information
693 */
694 u8 ecc_bucket_count;
695 u8 reserved_2[11];
696
697 /*
698 * Include the controller properties (changeable items)
699 */
700 struct megasas_ctrl_prop properties;
701
702 /*
703 * Define FW pkg version (set in envt v'bles on OEM basis)
704 */
705 char package_version[0x60];
706
707 u8 pad[0x800 - 0x6a0];
708
81e403ce 709} __packed;
c4a3e0a5
BS		 710
711/*
712 * ===============================
713 * MegaRAID SAS driver definitions
714 * ===============================
715 */
716#define MEGASAS_MAX_PD_CHANNELS 2
717#define MEGASAS_MAX_LD_CHANNELS 2
718#define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
719 MEGASAS_MAX_LD_CHANNELS)
720#define MEGASAS_MAX_DEV_PER_CHANNEL 128
721#define MEGASAS_DEFAULT_INIT_ID -1
722#define MEGASAS_MAX_LUN 8
723#define MEGASAS_MAX_LD 64
6bf579a3 724#define MEGASAS_DEFAULT_CMD_PER_LUN 256
81e403ce
YB		 725#define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
726 MEGASAS_MAX_DEV_PER_CHANNEL)
bdc6fb8d
YB		 727#define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
728 MEGASAS_MAX_DEV_PER_CHANNEL)
c4a3e0a5 729
1fd10685 730#define MEGASAS_MAX_SECTORS (2*1024)
42a8d2b3 731#define MEGASAS_MAX_SECTORS_IEEE (2*128)
658dcedb
SP		 732#define MEGASAS_DBG_LVL 1
733
05e9ebbe
SP		 734#define MEGASAS_FW_BUSY 1
735
d532dbe2 736/* Frame Type */
737#define IO_FRAME 0
738#define PTHRU_FRAME 1
739
c4a3e0a5
BS		 740/*
741 * When SCSI mid-layer calls driver's reset routine, driver waits for
742 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
743 * that the driver cannot _actually_ abort or reset pending commands. While
744 * it is waiting for the commands to complete, it prints a diagnostic message
745 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
746 */
747#define MEGASAS_RESET_WAIT_TIME 180
2a3681e5 748#define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
c4a3e0a5 749#define MEGASAS_RESET_NOTICE_INTERVAL 5
c4a3e0a5 750#define MEGASAS_IOCTL_CMD 0
05e9ebbe 751#define MEGASAS_DEFAULT_CMD_TIMEOUT 90
c5daa6a9 752#define MEGASAS_THROTTLE_QUEUE_DEPTH 16
c4a3e0a5
BS		 753
754/*
755 * FW reports the maximum of number of commands that it can accept (maximum
756 * commands that can be outstanding) at any time. The driver must report a
757 * lower number to the mid layer because it can issue a few internal commands
758 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
759 * is shown below
760 */
761#define MEGASAS_INT_CMDS 32
7bebf5c7 762#define MEGASAS_SKINNY_INT_CMDS 5
c4a3e0a5 763
c8e858fe 764#define MEGASAS_MAX_MSIX_QUEUES 16
c4a3e0a5
BS		 765/*
766 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
767 * SGLs based on the size of dma_addr_t
768 */
769#define IS_DMA64 (sizeof(dma_addr_t) == 8)
770
39a98554 771#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
772
773#define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
774#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
775#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
776
c4a3e0a5 777#define MFI_OB_INTR_STATUS_MASK 0x00000002
14faea9f 778#define MFI_POLL_TIMEOUT_SECS 60
c4a3e0a5 779
f9876f0b 780#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
6610a6b3
YB		 781#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
782#define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
87911122
YB		 783#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
784#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
0e98936c 785
39a98554 786#define MFI_1068_PCSR_OFFSET 0x84
787#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
788#define MFI_1068_FW_READY 0xDDDD0000
0e98936c
SP		 789/*
790* register set for both 1068 and 1078 controllers
791* structure extended for 1078 registers
792*/
f9876f0b 793
c4a3e0a5 794struct megasas_register_set {
9c915a8c
AR		 795 u32 doorbell; /*0000h*/
796 u32 fusion_seq_offset; /*0004h*/
797 u32 fusion_host_diag; /*0008h*/
798 u32 reserved_01; /*000Ch*/
c4a3e0a5 799
f9876f0b
SP		 800 u32 inbound_msg_0; /*0010h*/
801 u32 inbound_msg_1; /*0014h*/
802 u32 outbound_msg_0; /*0018h*/
803 u32 outbound_msg_1; /*001Ch*/
c4a3e0a5 804
f9876f0b
SP		 805 u32 inbound_doorbell; /*0020h*/
806 u32 inbound_intr_status; /*0024h*/
807 u32 inbound_intr_mask; /*0028h*/
c4a3e0a5 808
f9876f0b
SP		 809 u32 outbound_doorbell; /*002Ch*/
810 u32 outbound_intr_status; /*0030h*/
811 u32 outbound_intr_mask; /*0034h*/
c4a3e0a5 812
f9876f0b 813 u32 reserved_1[2]; /*0038h*/
c4a3e0a5 814
f9876f0b
SP		 815 u32 inbound_queue_port; /*0040h*/
816 u32 outbound_queue_port; /*0044h*/
c4a3e0a5 817
9c915a8c
AR		 818 u32 reserved_2[9]; /*0048h*/
819 u32 reply_post_host_index; /*006Ch*/
820 u32 reserved_2_2[12]; /*0070h*/
c4a3e0a5 821
f9876f0b 822 u32 outbound_doorbell_clear; /*00A0h*/
c4a3e0a5 823
f9876f0b
SP		 824 u32 reserved_3[3]; /*00A4h*/
825
826 u32 outbound_scratch_pad ; /*00B0h*/
9c915a8c 827 u32 outbound_scratch_pad_2; /*00B4h*/
f9876f0b 828
9c915a8c 829 u32 reserved_4[2]; /*00B8h*/
f9876f0b
SP		 830
831 u32 inbound_low_queue_port ; /*00C0h*/
832
833 u32 inbound_high_queue_port ; /*00C4h*/
834
835 u32 reserved_5; /*00C8h*/
39a98554 836 u32 res_6[11]; /*CCh*/
837 u32 host_diag;
838 u32 seq_offset;
839 u32 index_registers[807]; /*00CCh*/
c4a3e0a5
BS		 840} __attribute__ ((packed));
841
842struct megasas_sge32 {
843
844 u32 phys_addr;
845 u32 length;
846
847} __attribute__ ((packed));
848
849struct megasas_sge64 {
850
851 u64 phys_addr;
852 u32 length;
853
854} __attribute__ ((packed));
855
f4c9a131
YB		 856struct megasas_sge_skinny {
857 u64 phys_addr;
858 u32 length;
859 u32 flag;
860} __packed;
861
c4a3e0a5
BS		 862union megasas_sgl {
863
864 struct megasas_sge32 sge32[1];
865 struct megasas_sge64 sge64[1];
f4c9a131 866 struct megasas_sge_skinny sge_skinny[1];
c4a3e0a5
BS		 867
868} __attribute__ ((packed));
869
870struct megasas_header {
871
872 u8 cmd; /*00h */
873 u8 sense_len; /*01h */
874 u8 cmd_status; /*02h */
875 u8 scsi_status; /*03h */
876
877 u8 target_id; /*04h */
878 u8 lun; /*05h */
879 u8 cdb_len; /*06h */
880 u8 sge_count; /*07h */
881
882 u32 context; /*08h */
883 u32 pad_0; /*0Ch */
884
885 u16 flags; /*10h */
886 u16 timeout; /*12h */
887 u32 data_xferlen; /*14h */
888
889} __attribute__ ((packed));
890
891union megasas_sgl_frame {
892
893 struct megasas_sge32 sge32[8];
894 struct megasas_sge64 sge64[5];
895
896} __attribute__ ((packed));
897
898struct megasas_init_frame {
899
900 u8 cmd; /*00h */
901 u8 reserved_0; /*01h */
902 u8 cmd_status; /*02h */
903
904 u8 reserved_1; /*03h */
905 u32 reserved_2; /*04h */
906
907 u32 context; /*08h */
908 u32 pad_0; /*0Ch */
909
910 u16 flags; /*10h */
911 u16 reserved_3; /*12h */
912 u32 data_xfer_len; /*14h */
913
914 u32 queue_info_new_phys_addr_lo; /*18h */
915 u32 queue_info_new_phys_addr_hi; /*1Ch */
916 u32 queue_info_old_phys_addr_lo; /*20h */
917 u32 queue_info_old_phys_addr_hi; /*24h */
918
919 u32 reserved_4[6]; /*28h */
920
921} __attribute__ ((packed));
922
923struct megasas_init_queue_info {
924
925 u32 init_flags; /*00h */
926 u32 reply_queue_entries; /*04h */
927
928 u32 reply_queue_start_phys_addr_lo; /*08h */
929 u32 reply_queue_start_phys_addr_hi; /*0Ch */
930 u32 producer_index_phys_addr_lo; /*10h */
931 u32 producer_index_phys_addr_hi; /*14h */
932 u32 consumer_index_phys_addr_lo; /*18h */
933 u32 consumer_index_phys_addr_hi; /*1Ch */
934
935} __attribute__ ((packed));
936
937struct megasas_io_frame {
938
939 u8 cmd; /*00h */
940 u8 sense_len; /*01h */
941 u8 cmd_status; /*02h */
942 u8 scsi_status; /*03h */
943
944 u8 target_id; /*04h */
945 u8 access_byte; /*05h */
946 u8 reserved_0; /*06h */
947 u8 sge_count; /*07h */
948
949 u32 context; /*08h */
950 u32 pad_0; /*0Ch */
951
952 u16 flags; /*10h */
953 u16 timeout; /*12h */
954 u32 lba_count; /*14h */
955
956 u32 sense_buf_phys_addr_lo; /*18h */
957 u32 sense_buf_phys_addr_hi; /*1Ch */
958
959 u32 start_lba_lo; /*20h */
960 u32 start_lba_hi; /*24h */
961
962 union megasas_sgl sgl; /*28h */
963
964} __attribute__ ((packed));
965
966struct megasas_pthru_frame {
967
968 u8 cmd; /*00h */
969 u8 sense_len; /*01h */
970 u8 cmd_status; /*02h */
971 u8 scsi_status; /*03h */
972
973 u8 target_id; /*04h */
974 u8 lun; /*05h */
975 u8 cdb_len; /*06h */
976 u8 sge_count; /*07h */
977
978 u32 context; /*08h */
979 u32 pad_0; /*0Ch */
980
981 u16 flags; /*10h */
982 u16 timeout; /*12h */
983 u32 data_xfer_len; /*14h */
984
985 u32 sense_buf_phys_addr_lo; /*18h */
986 u32 sense_buf_phys_addr_hi; /*1Ch */
987
988 u8 cdb[16]; /*20h */
989 union megasas_sgl sgl; /*30h */
990
991} __attribute__ ((packed));
992
993struct megasas_dcmd_frame {
994
995 u8 cmd; /*00h */
996 u8 reserved_0; /*01h */
997 u8 cmd_status; /*02h */
998 u8 reserved_1[4]; /*03h */
999 u8 sge_count; /*07h */
1000
1001 u32 context; /*08h */
1002 u32 pad_0; /*0Ch */
1003
1004 u16 flags; /*10h */
1005 u16 timeout; /*12h */
1006
1007 u32 data_xfer_len; /*14h */
1008 u32 opcode; /*18h */
1009
1010 union { /*1Ch */
1011 u8 b[12];
1012 u16 s[6];
1013 u32 w[3];
1014 } mbox;
1015
1016 union megasas_sgl sgl; /*28h */
1017
1018} __attribute__ ((packed));
1019
1020struct megasas_abort_frame {
1021
1022 u8 cmd; /*00h */
1023 u8 reserved_0; /*01h */
1024 u8 cmd_status; /*02h */
1025
1026 u8 reserved_1; /*03h */
1027 u32 reserved_2; /*04h */
1028
1029 u32 context; /*08h */
1030 u32 pad_0; /*0Ch */
1031
1032 u16 flags; /*10h */
1033 u16 reserved_3; /*12h */
1034 u32 reserved_4; /*14h */
1035
1036 u32 abort_context; /*18h */
1037 u32 pad_1; /*1Ch */
1038
1039 u32 abort_mfi_phys_addr_lo; /*20h */
1040 u32 abort_mfi_phys_addr_hi; /*24h */
1041
1042 u32 reserved_5[6]; /*28h */
1043
1044} __attribute__ ((packed));
1045
1046struct megasas_smp_frame {
1047
1048 u8 cmd; /*00h */
1049 u8 reserved_1; /*01h */
1050 u8 cmd_status; /*02h */
1051 u8 connection_status; /*03h */
1052
1053 u8 reserved_2[3]; /*04h */
1054 u8 sge_count; /*07h */
1055
1056 u32 context; /*08h */
1057 u32 pad_0; /*0Ch */
1058
1059 u16 flags; /*10h */
1060 u16 timeout; /*12h */
1061
1062 u32 data_xfer_len; /*14h */
1063 u64 sas_addr; /*18h */
1064
1065 union {
1066 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1067 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1068 } sgl;
1069
1070} __attribute__ ((packed));
1071
1072struct megasas_stp_frame {
1073
1074 u8 cmd; /*00h */
1075 u8 reserved_1; /*01h */
1076 u8 cmd_status; /*02h */
1077 u8 reserved_2; /*03h */
1078
1079 u8 target_id; /*04h */
1080 u8 reserved_3[2]; /*05h */
1081 u8 sge_count; /*07h */
1082
1083 u32 context; /*08h */
1084 u32 pad_0; /*0Ch */
1085
1086 u16 flags; /*10h */
1087 u16 timeout; /*12h */
1088
1089 u32 data_xfer_len; /*14h */
1090
1091 u16 fis[10]; /*18h */
1092 u32 stp_flags;
1093
1094 union {
1095 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1096 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1097 } sgl;
1098
1099} __attribute__ ((packed));
1100
1101union megasas_frame {
1102
1103 struct megasas_header hdr;
1104 struct megasas_init_frame init;
1105 struct megasas_io_frame io;
1106 struct megasas_pthru_frame pthru;
1107 struct megasas_dcmd_frame dcmd;
1108 struct megasas_abort_frame abort;
1109 struct megasas_smp_frame smp;
1110 struct megasas_stp_frame stp;
1111
1112 u8 raw_bytes[64];
1113};
1114
1115struct megasas_cmd;
1116
1117union megasas_evt_class_locale {
1118
1119 struct {
1120 u16 locale;
1121 u8 reserved;
1122 s8 class;
1123 } __attribute__ ((packed)) members;
1124
1125 u32 word;
1126
1127} __attribute__ ((packed));
1128
1129struct megasas_evt_log_info {
1130 u32 newest_seq_num;
1131 u32 oldest_seq_num;
1132 u32 clear_seq_num;
1133 u32 shutdown_seq_num;
1134 u32 boot_seq_num;
1135
1136} __attribute__ ((packed));
1137
1138struct megasas_progress {
1139
1140 u16 progress;
1141 u16 elapsed_seconds;
1142
1143} __attribute__ ((packed));
1144
1145struct megasas_evtarg_ld {
1146
1147 u16 target_id;
1148 u8 ld_index;
1149 u8 reserved;
1150
1151} __attribute__ ((packed));
1152
1153struct megasas_evtarg_pd {
1154 u16 device_id;
1155 u8 encl_index;
1156 u8 slot_number;
1157
1158} __attribute__ ((packed));
1159
1160struct megasas_evt_detail {
1161
1162 u32 seq_num;
1163 u32 time_stamp;
1164 u32 code;
1165 union megasas_evt_class_locale cl;
1166 u8 arg_type;
1167 u8 reserved1[15];
1168
1169 union {
1170 struct {
1171 struct megasas_evtarg_pd pd;
1172 u8 cdb_length;
1173 u8 sense_length;
1174 u8 reserved[2];
1175 u8 cdb[16];
1176 u8 sense[64];
1177 } __attribute__ ((packed)) cdbSense;
1178
1179 struct megasas_evtarg_ld ld;
1180
1181 struct {
1182 struct megasas_evtarg_ld ld;
1183 u64 count;
1184 } __attribute__ ((packed)) ld_count;
1185
1186 struct {
1187 u64 lba;
1188 struct megasas_evtarg_ld ld;
1189 } __attribute__ ((packed)) ld_lba;
1190
1191 struct {
1192 struct megasas_evtarg_ld ld;
1193 u32 prevOwner;
1194 u32 newOwner;
1195 } __attribute__ ((packed)) ld_owner;
1196
1197 struct {
1198 u64 ld_lba;
1199 u64 pd_lba;
1200 struct megasas_evtarg_ld ld;
1201 struct megasas_evtarg_pd pd;
1202 } __attribute__ ((packed)) ld_lba_pd_lba;
1203
1204 struct {
1205 struct megasas_evtarg_ld ld;
1206 struct megasas_progress prog;
1207 } __attribute__ ((packed)) ld_prog;
1208
1209 struct {
1210 struct megasas_evtarg_ld ld;
1211 u32 prev_state;
1212 u32 new_state;
1213 } __attribute__ ((packed)) ld_state;
1214
1215 struct {
1216 u64 strip;
1217 struct megasas_evtarg_ld ld;
1218 } __attribute__ ((packed)) ld_strip;
1219
1220 struct megasas_evtarg_pd pd;
1221
1222 struct {
1223 struct megasas_evtarg_pd pd;
1224 u32 err;
1225 } __attribute__ ((packed)) pd_err;
1226
1227 struct {
1228 u64 lba;
1229 struct megasas_evtarg_pd pd;
1230 } __attribute__ ((packed)) pd_lba;
1231
1232 struct {
1233 u64 lba;
1234 struct megasas_evtarg_pd pd;
1235 struct megasas_evtarg_ld ld;
1236 } __attribute__ ((packed)) pd_lba_ld;
1237
1238 struct {
1239 struct megasas_evtarg_pd pd;
1240 struct megasas_progress prog;
1241 } __attribute__ ((packed)) pd_prog;
1242
1243 struct {
1244 struct megasas_evtarg_pd pd;
1245 u32 prevState;
1246 u32 newState;
1247 } __attribute__ ((packed)) pd_state;
1248
1249 struct {
1250 u16 vendorId;
1251 u16 deviceId;
1252 u16 subVendorId;
1253 u16 subDeviceId;
1254 } __attribute__ ((packed)) pci;
1255
1256 u32 rate;
1257 char str[96];
1258
1259 struct {
1260 u32 rtc;
1261 u32 elapsedSeconds;
1262 } __attribute__ ((packed)) time;
1263
1264 struct {
1265 u32 ecar;
1266 u32 elog;
1267 char str[64];
1268 } __attribute__ ((packed)) ecc;
1269
1270 u8 b[96];
1271 u16 s[48];
1272 u32 w[24];
1273 u64 d[12];
1274 } args;
1275
1276 char description[128];
1277
1278} __attribute__ ((packed));
1279
7e8a75f4 1280struct megasas_aen_event {
c1d390d8 1281 struct delayed_work hotplug_work;
7e8a75f4
YB		 1282 struct megasas_instance *instance;
1283};
1284
c8e858fe
AR		 1285struct megasas_irq_context {
1286 struct megasas_instance *instance;
1287 u32 MSIxIndex;
1288};
1289
c4a3e0a5
BS		 1290struct megasas_instance {
1291
1292 u32 *producer;
1293 dma_addr_t producer_h;
1294 u32 *consumer;
1295 dma_addr_t consumer_h;
1296
1297 u32 *reply_queue;
1298 dma_addr_t reply_queue_h;
1299
c4a3e0a5
BS		 1300 struct megasas_register_set __iomem *reg_set;
1301
81e403ce 1302 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
bdc6fb8d 1303 u8 ld_ids[MEGASAS_MAX_LD_IDS];
c4a3e0a5 1304 s8 init_id;
c4a3e0a5
BS		 1305
1306 u16 max_num_sge;
1307 u16 max_fw_cmds;
9c915a8c
AR		 1308 /* For Fusion its num IOCTL cmds, for others MFI based its
1309 max_fw_cmds */
1310 u16 max_mfi_cmds;
c4a3e0a5 1311 u32 max_sectors_per_req;
7e8a75f4 1312 struct megasas_aen_event *ev;
c4a3e0a5
BS		 1313
1314 struct megasas_cmd **cmd_list;
1315 struct list_head cmd_pool;
39a98554 1316 /* used to sync fire the cmd to fw */
c4a3e0a5 1317 spinlock_t cmd_pool_lock;
39a98554 1318 /* used to sync fire the cmd to fw */
1319 spinlock_t hba_lock;
7343eb65 1320 /* used to synch producer, consumer ptrs in dpc */
1321 spinlock_t completion_lock;
c4a3e0a5
BS		 1322 struct dma_pool *frame_dma_pool;
1323 struct dma_pool *sense_dma_pool;
1324
1325 struct megasas_evt_detail *evt_detail;
1326 dma_addr_t evt_detail_h;
1327 struct megasas_cmd *aen_cmd;
e5a69e27 1328 struct mutex aen_mutex;
c4a3e0a5
BS		 1329 struct semaphore ioctl_sem;
1330
1331 struct Scsi_Host *host;
1332
1333 wait_queue_head_t int_cmd_wait_q;
1334 wait_queue_head_t abort_cmd_wait_q;
1335
1336 struct pci_dev *pdev;
1337 u32 unique_id;
39a98554 1338 u32 fw_support_ieee;
c4a3e0a5 1339
e4a082c7 1340 atomic_t fw_outstanding;
39a98554 1341 atomic_t fw_reset_no_pci_access;
1341c939
SP		 1342
1343 struct megasas_instance_template *instancet;
5d018ad0 1344 struct tasklet_struct isr_tasklet;
39a98554 1345 struct work_struct work_init;
05e9ebbe
SP		 1346
1347 u8 flag;
c3518837 1348 u8 unload;
f4c9a131 1349 u8 flag_ieee;
39a98554 1350 u8 issuepend_done;
1351 u8 disableOnlineCtrlReset;
1352 u8 adprecovery;
05e9ebbe 1353 unsigned long last_time;
39a98554 1354 u32 mfiStatus;
1355 u32 last_seq_num;
ad84db2e 1356
39a98554 1357 struct list_head internal_reset_pending_q;
80d9da98 1358
25985edc 1359 /* Ptr to hba specific information */
9c915a8c 1360 void *ctrl_context;
c8e858fe
AR		 1361 unsigned int msix_vectors;
1362 struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES];
1363 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
9c915a8c
AR		 1364 u64 map_id;
1365 struct megasas_cmd *map_update_cmd;
b6d5d880 1366 unsigned long bar;
9c915a8c
AR		 1367 long reset_flags;
1368 struct mutex reset_mutex;
c5daa6a9 1369 int throttlequeuedepth;
39a98554 1370};
1371
1372enum {
1373 MEGASAS_HBA_OPERATIONAL = 0,
1374 MEGASAS_ADPRESET_SM_INFAULT = 1,
1375 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1376 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
1377 MEGASAS_HW_CRITICAL_ERROR = 4,
1378 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
c4a3e0a5
BS		 1379};
1380
0c79e681
YB		 1381struct megasas_instance_template {
1382 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1383 u32, struct megasas_register_set __iomem *);
1384
1385 void (*enable_intr)(struct megasas_register_set __iomem *) ;
1386 void (*disable_intr)(struct megasas_register_set __iomem *);
1387
1388 int (*clear_intr)(struct megasas_register_set __iomem *);
1389
1390 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
39a98554 1391 int (*adp_reset)(struct megasas_instance *, \
1392 struct megasas_register_set __iomem *);
1393 int (*check_reset)(struct megasas_instance *, \
1394 struct megasas_register_set __iomem *);
cd50ba8e
AR		 1395 irqreturn_t (*service_isr)(int irq, void *devp);
1396 void (*tasklet)(unsigned long);
1397 u32 (*init_adapter)(struct megasas_instance *);
1398 u32 (*build_and_issue_cmd) (struct megasas_instance *,
1399 struct scsi_cmnd *);
1400 void (*issue_dcmd) (struct megasas_instance *instance,
1401 struct megasas_cmd *cmd);
0c79e681
YB		 1402};
1403
c4a3e0a5 1404#define MEGASAS_IS_LOGICAL(scp) \
bb3445f8 1405 ((scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
c4a3e0a5
BS		 1406
1407#define MEGASAS_DEV_INDEX(inst, scp) \
1408 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1409 scp->device->id
1410
1411struct megasas_cmd {
1412
1413 union megasas_frame *frame;
1414 dma_addr_t frame_phys_addr;
1415 u8 *sense;
1416 dma_addr_t sense_phys_addr;
1417
1418 u32 index;
1419 u8 sync_cmd;
1420 u8 cmd_status;
39a98554 1421 u8 abort_aen;
1422 u8 retry_for_fw_reset;
1423
c4a3e0a5
BS		 1424
1425 struct list_head list;
1426 struct scsi_cmnd *scmd;
1427 struct megasas_instance *instance;
9c915a8c
AR		 1428 union {
1429 struct {
1430 u16 smid;
1431 u16 resvd;
1432 } context;
1433 u32 frame_count;
1434 };
c4a3e0a5
BS		 1435};
1436
1437#define MAX_MGMT_ADAPTERS 1024
1438#define MAX_IOCTL_SGE 16
1439
1440struct megasas_iocpacket {
1441
1442 u16 host_no;
1443 u16 __pad1;
1444 u32 sgl_off;
1445 u32 sge_count;
1446 u32 sense_off;
1447 u32 sense_len;
1448 union {
1449 u8 raw[128];
1450 struct megasas_header hdr;
1451 } frame;
1452
1453 struct iovec sgl[MAX_IOCTL_SGE];
1454
1455} __attribute__ ((packed));
1456
1457struct megasas_aen {
1458 u16 host_no;
1459 u16 __pad1;
1460 u32 seq_num;
1461 u32 class_locale_word;
1462} __attribute__ ((packed));
1463
1464#ifdef CONFIG_COMPAT
1465struct compat_megasas_iocpacket {
1466 u16 host_no;
1467 u16 __pad1;
1468 u32 sgl_off;
1469 u32 sge_count;
1470 u32 sense_off;
1471 u32 sense_len;
1472 union {
1473 u8 raw[128];
1474 struct megasas_header hdr;
1475 } frame;
1476 struct compat_iovec sgl[MAX_IOCTL_SGE];
1477} __attribute__ ((packed));
1478
0e98936c 1479#define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
c4a3e0a5
BS		 1480#endif
1481
cb59aa6a 1482#define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
c4a3e0a5
BS		 1483#define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1484
1485struct megasas_mgmt_info {
1486
1487 u16 count;
1488 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1489 int max_index;
1490};
1491
1492#endif /*LSI_MEGARAID_SAS_H */
kernel source for telekom puls (alcatel/mediatek)