projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SCSI] megaraid_sas: Remove duplicate code
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / megaraid / megaraid_sas.h
CommitLineData
c4a3e0a5 1/*
3f1530c1 2 * Linux MegaRAID driver for SAS based RAID controllers
c4a3e0a5 3 *
3f1530c1 4 * Copyright (c) 2009-2011 LSI Corporation.
c4a3e0a5 5 *
3f1530c1
AR		 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
c4a3e0a5 10 *
3f1530c1
AR		 11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
c4a3e0a5 15 *
3f1530c1
AR		 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * FILE: megaraid_sas.h
21 *
22 * Authors: LSI Corporation
23 *
24 * Send feedback to: <megaraidlinux@lsi.com>
25 *
26 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
27 * ATTN: Linuxraid
c4a3e0a5
BS		 28 */
29
30#ifndef LSI_MEGARAID_SAS_H
31#define LSI_MEGARAID_SAS_H
32
a69b74d3 33/*
c4a3e0a5
BS		 34 * MegaRAID SAS Driver meta data
35 */
cdd75750
AR		 36#define MEGASAS_VERSION "00.00.06.18-rc1"
37#define MEGASAS_RELDATE "Jun. 17, 2012"
38#define MEGASAS_EXT_VERSION "Tue. Jun. 17 17:00:00 PDT 2012"
0e98936c
SP		 39
40/*
41 * Device IDs
42 */
43#define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
af7a5647 44#define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
0e98936c 45#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
6610a6b3
YB		 46#define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
47#define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
87911122
YB		 48#define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
49#define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
9c915a8c 50#define PCI_DEVICE_ID_LSI_FUSION 0x005b
36807e67 51#define PCI_DEVICE_ID_LSI_INVADER 0x005d
0e98936c 52
c4a3e0a5
BS		 53/*
54 * =====================================
55 * MegaRAID SAS MFI firmware definitions
56 * =====================================
57 */
58
59/*
60 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
61 * protocol between the software and firmware. Commands are issued using
62 * "message frames"
63 */
64
a69b74d3 65/*
c4a3e0a5
BS		 66 * FW posts its state in upper 4 bits of outbound_msg_0 register
67 */
68#define MFI_STATE_MASK 0xF0000000
69#define MFI_STATE_UNDEFINED 0x00000000
70#define MFI_STATE_BB_INIT 0x10000000
71#define MFI_STATE_FW_INIT 0x40000000
72#define MFI_STATE_WAIT_HANDSHAKE 0x60000000
73#define MFI_STATE_FW_INIT_2 0x70000000
74#define MFI_STATE_DEVICE_SCAN 0x80000000
e3bbff9f 75#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
c4a3e0a5
BS		 76#define MFI_STATE_FLUSH_CACHE 0xA0000000
77#define MFI_STATE_READY 0xB0000000
78#define MFI_STATE_OPERATIONAL 0xC0000000
79#define MFI_STATE_FAULT 0xF0000000
7e70e733
AR		 80#define MFI_RESET_REQUIRED 0x00000001
81#define MFI_RESET_ADAPTER 0x00000002
c4a3e0a5
BS		 82#define MEGAMFI_FRAME_SIZE 64
83
a69b74d3 84/*
c4a3e0a5
BS		 85 * During FW init, clear pending cmds & reset state using inbound_msg_0
86 *
87 * ABORT : Abort all pending cmds
88 * READY : Move from OPERATIONAL to READY state; discard queue info
89 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
90 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
e3bbff9f
SP		 91 * HOTPLUG : Resume from Hotplug
92 * MFI_STOP_ADP : Send signal to FW to stop processing
c4a3e0a5 93 */
39a98554 94#define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
95#define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
96#define DIAG_WRITE_ENABLE (0x00000080)
97#define DIAG_RESET_ADAPTER (0x00000004)
98
99#define MFI_ADP_RESET 0x00000040
e3bbff9f 100#define MFI_INIT_ABORT 0x00000001
c4a3e0a5
BS		 101#define MFI_INIT_READY 0x00000002
102#define MFI_INIT_MFIMODE 0x00000004
103#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
e3bbff9f
SP		 104#define MFI_INIT_HOTPLUG 0x00000010
105#define MFI_STOP_ADP 0x00000020
106#define MFI_RESET_FLAGS MFI_INIT_READY| \
107 MFI_INIT_MFIMODE| \
108 MFI_INIT_ABORT
c4a3e0a5 109
a69b74d3 110/*
c4a3e0a5
BS		 111 * MFI frame flags
112 */
113#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
114#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
115#define MFI_FRAME_SGL32 0x0000
116#define MFI_FRAME_SGL64 0x0002
117#define MFI_FRAME_SENSE32 0x0000
118#define MFI_FRAME_SENSE64 0x0004
119#define MFI_FRAME_DIR_NONE 0x0000
120#define MFI_FRAME_DIR_WRITE 0x0008
121#define MFI_FRAME_DIR_READ 0x0010
122#define MFI_FRAME_DIR_BOTH 0x0018
f4c9a131 123#define MFI_FRAME_IEEE 0x0020
c4a3e0a5 124
a69b74d3 125/*
c4a3e0a5
BS		 126 * Definition for cmd_status
127 */
128#define MFI_CMD_STATUS_POLL_MODE 0xFF
129
a69b74d3 130/*
c4a3e0a5
BS		 131 * MFI command opcodes
132 */
133#define MFI_CMD_INIT 0x00
134#define MFI_CMD_LD_READ 0x01
135#define MFI_CMD_LD_WRITE 0x02
136#define MFI_CMD_LD_SCSI_IO 0x03
137#define MFI_CMD_PD_SCSI_IO 0x04
138#define MFI_CMD_DCMD 0x05
139#define MFI_CMD_ABORT 0x06
140#define MFI_CMD_SMP 0x07
141#define MFI_CMD_STP 0x08
e5f93a36 142#define MFI_CMD_INVALID 0xff
c4a3e0a5
BS		 143
144#define MR_DCMD_CTRL_GET_INFO 0x01010000
bdc6fb8d 145#define MR_DCMD_LD_GET_LIST 0x03010000
c4a3e0a5
BS		 146
147#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
148#define MR_FLUSH_CTRL_CACHE 0x01
149#define MR_FLUSH_DISK_CACHE 0x02
150
151#define MR_DCMD_CTRL_SHUTDOWN 0x01050000
31ea7088 152#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
c4a3e0a5
BS		 153#define MR_ENABLE_DRIVE_SPINDOWN 0x01
154
155#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
156#define MR_DCMD_CTRL_EVENT_GET 0x01040300
157#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
158#define MR_DCMD_LD_GET_PROPERTIES 0x03030000
159
160#define MR_DCMD_CLUSTER 0x08000000
161#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
162#define MR_DCMD_CLUSTER_RESET_LD 0x08010200
81e403ce 163#define MR_DCMD_PD_LIST_QUERY 0x02010100
c4a3e0a5 164
a69b74d3 165/*
c4a3e0a5
BS		 166 * MFI command completion codes
167 */
168enum MFI_STAT {
169 MFI_STAT_OK = 0x00,
170 MFI_STAT_INVALID_CMD = 0x01,
171 MFI_STAT_INVALID_DCMD = 0x02,
172 MFI_STAT_INVALID_PARAMETER = 0x03,
173 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
174 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
175 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
176 MFI_STAT_APP_IN_USE = 0x07,
177 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
178 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
179 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
180 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
181 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
182 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
183 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
184 MFI_STAT_FLASH_BUSY = 0x0f,
185 MFI_STAT_FLASH_ERROR = 0x10,
186 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
187 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
188 MFI_STAT_FLASH_NOT_OPEN = 0x13,
189 MFI_STAT_FLASH_NOT_STARTED = 0x14,
190 MFI_STAT_FLUSH_FAILED = 0x15,
191 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
192 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
193 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
194 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
195 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
196 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
197 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
198 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
199 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
200 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
201 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
202 MFI_STAT_MFC_HW_ERROR = 0x21,
203 MFI_STAT_NO_HW_PRESENT = 0x22,
204 MFI_STAT_NOT_FOUND = 0x23,
205 MFI_STAT_NOT_IN_ENCL = 0x24,
206 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
207 MFI_STAT_PD_TYPE_WRONG = 0x26,
208 MFI_STAT_PR_DISABLED = 0x27,
209 MFI_STAT_ROW_INDEX_INVALID = 0x28,
210 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
211 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
212 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
213 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
214 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
215 MFI_STAT_SCSI_IO_FAILED = 0x2e,
216 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
217 MFI_STAT_SHUTDOWN_FAILED = 0x30,
218 MFI_STAT_TIME_NOT_SET = 0x31,
219 MFI_STAT_WRONG_STATE = 0x32,
220 MFI_STAT_LD_OFFLINE = 0x33,
221 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
222 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
223 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
224 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
225 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
36807e67 226 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
c4a3e0a5
BS		 227
228 MFI_STAT_INVALID_STATUS = 0xFF
229};
230
231/*
232 * Number of mailbox bytes in DCMD message frame
233 */
234#define MFI_MBOX_SIZE 12
235
236enum MR_EVT_CLASS {
237
238 MR_EVT_CLASS_DEBUG = -2,
239 MR_EVT_CLASS_PROGRESS = -1,
240 MR_EVT_CLASS_INFO = 0,
241 MR_EVT_CLASS_WARNING = 1,
242 MR_EVT_CLASS_CRITICAL = 2,
243 MR_EVT_CLASS_FATAL = 3,
244 MR_EVT_CLASS_DEAD = 4,
245
246};
247
248enum MR_EVT_LOCALE {
249
250 MR_EVT_LOCALE_LD = 0x0001,
251 MR_EVT_LOCALE_PD = 0x0002,
252 MR_EVT_LOCALE_ENCL = 0x0004,
253 MR_EVT_LOCALE_BBU = 0x0008,
254 MR_EVT_LOCALE_SAS = 0x0010,
255 MR_EVT_LOCALE_CTRL = 0x0020,
256 MR_EVT_LOCALE_CONFIG = 0x0040,
257 MR_EVT_LOCALE_CLUSTER = 0x0080,
258 MR_EVT_LOCALE_ALL = 0xffff,
259
260};
261
262enum MR_EVT_ARGS {
263
264 MR_EVT_ARGS_NONE,
265 MR_EVT_ARGS_CDB_SENSE,
266 MR_EVT_ARGS_LD,
267 MR_EVT_ARGS_LD_COUNT,
268 MR_EVT_ARGS_LD_LBA,
269 MR_EVT_ARGS_LD_OWNER,
270 MR_EVT_ARGS_LD_LBA_PD_LBA,
271 MR_EVT_ARGS_LD_PROG,
272 MR_EVT_ARGS_LD_STATE,
273 MR_EVT_ARGS_LD_STRIP,
274 MR_EVT_ARGS_PD,
275 MR_EVT_ARGS_PD_ERR,
276 MR_EVT_ARGS_PD_LBA,
277 MR_EVT_ARGS_PD_LBA_LD,
278 MR_EVT_ARGS_PD_PROG,
279 MR_EVT_ARGS_PD_STATE,
280 MR_EVT_ARGS_PCI,
281 MR_EVT_ARGS_RATE,
282 MR_EVT_ARGS_STR,
283 MR_EVT_ARGS_TIME,
284 MR_EVT_ARGS_ECC,
81e403ce
YB		 285 MR_EVT_ARGS_LD_PROP,
286 MR_EVT_ARGS_PD_SPARE,
287 MR_EVT_ARGS_PD_INDEX,
288 MR_EVT_ARGS_DIAG_PASS,
289 MR_EVT_ARGS_DIAG_FAIL,
290 MR_EVT_ARGS_PD_LBA_LBA,
291 MR_EVT_ARGS_PORT_PHY,
292 MR_EVT_ARGS_PD_MISSING,
293 MR_EVT_ARGS_PD_ADDRESS,
294 MR_EVT_ARGS_BITMAP,
295 MR_EVT_ARGS_CONNECTOR,
296 MR_EVT_ARGS_PD_PD,
297 MR_EVT_ARGS_PD_FRU,
298 MR_EVT_ARGS_PD_PATHINFO,
299 MR_EVT_ARGS_PD_POWER_STATE,
300 MR_EVT_ARGS_GENERIC,
301};
c4a3e0a5 302
81e403ce
YB		 303/*
304 * define constants for device list query options
305 */
306enum MR_PD_QUERY_TYPE {
307 MR_PD_QUERY_TYPE_ALL = 0,
308 MR_PD_QUERY_TYPE_STATE = 1,
309 MR_PD_QUERY_TYPE_POWER_STATE = 2,
310 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
311 MR_PD_QUERY_TYPE_SPEED = 4,
312 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
c4a3e0a5
BS		 313};
314
7e8a75f4
YB		 315#define MR_EVT_CFG_CLEARED 0x0004
316#define MR_EVT_LD_STATE_CHANGE 0x0051
317#define MR_EVT_PD_INSERTED 0x005b
318#define MR_EVT_PD_REMOVED 0x0070
319#define MR_EVT_LD_CREATED 0x008a
320#define MR_EVT_LD_DELETED 0x008b
321#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
322#define MR_EVT_LD_OFFLINE 0x00fc
323#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
324#define MAX_LOGICAL_DRIVES 64
325
81e403ce
YB		 326enum MR_PD_STATE {
327 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
328 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
329 MR_PD_STATE_HOT_SPARE = 0x02,
330 MR_PD_STATE_OFFLINE = 0x10,
331 MR_PD_STATE_FAILED = 0x11,
332 MR_PD_STATE_REBUILD = 0x14,
333 MR_PD_STATE_ONLINE = 0x18,
334 MR_PD_STATE_COPYBACK = 0x20,
335 MR_PD_STATE_SYSTEM = 0x40,
336 };
337
338
339 /*
340 * defines the physical drive address structure
341 */
342struct MR_PD_ADDRESS {
343 u16 deviceId;
344 u16 enclDeviceId;
345
346 union {
347 struct {
348 u8 enclIndex;
349 u8 slotNumber;
350 } mrPdAddress;
351 struct {
352 u8 enclPosition;
353 u8 enclConnectorIndex;
354 } mrEnclAddress;
355 };
356 u8 scsiDevType;
357 union {
358 u8 connectedPortBitmap;
359 u8 connectedPortNumbers;
360 };
361 u64 sasAddr[2];
362} __packed;
363
364/*
365 * defines the physical drive list structure
366 */
367struct MR_PD_LIST {
368 u32 size;
369 u32 count;
370 struct MR_PD_ADDRESS addr[1];
371} __packed;
372
373struct megasas_pd_list {
374 u16 tid;
375 u8 driveType;
376 u8 driveState;
377} __packed;
378
bdc6fb8d
YB		 379 /*
380 * defines the logical drive reference structure
381 */
382union MR_LD_REF {
383 struct {
384 u8 targetId;
385 u8 reserved;
386 u16 seqNum;
387 };
388 u32 ref;
389} __packed;
390
391/*
392 * defines the logical drive list structure
393 */
394struct MR_LD_LIST {
395 u32 ldCount;
396 u32 reserved;
397 struct {
398 union MR_LD_REF ref;
399 u8 state;
400 u8 reserved[3];
401 u64 size;
402 } ldList[MAX_LOGICAL_DRIVES];
403} __packed;
404
c4a3e0a5
BS		 405/*
406 * SAS controller properties
407 */
408struct megasas_ctrl_prop {
409
410 u16 seq_num;
411 u16 pred_fail_poll_interval;
412 u16 intr_throttle_count;
413 u16 intr_throttle_timeouts;
414 u8 rebuild_rate;
415 u8 patrol_read_rate;
416 u8 bgi_rate;
417 u8 cc_rate;
418 u8 recon_rate;
419 u8 cache_flush_interval;
420 u8 spinup_drv_count;
421 u8 spinup_delay;
422 u8 cluster_enable;
423 u8 coercion_mode;
424 u8 alarm_enable;
425 u8 disable_auto_rebuild;
426 u8 disable_battery_warn;
427 u8 ecc_bucket_size;
428 u16 ecc_bucket_leak_rate;
429 u8 restore_hotspare_on_insertion;
430 u8 expose_encl_devices;
39a98554 431 u8 maintainPdFailHistory;
432 u8 disallowHostRequestReordering;
433 u8 abortCCOnError;
434 u8 loadBalanceMode;
435 u8 disableAutoDetectBackplane;
436
437 u8 snapVDSpace;
438
439 /*
440 * Add properties that can be controlled by
441 * a bit in the following structure.
442 */
39a98554 443 struct {
444 u32 copyBackDisabled : 1;
445 u32 SMARTerEnabled : 1;
446 u32 prCorrectUnconfiguredAreas : 1;
447 u32 useFdeOnly : 1;
448 u32 disableNCQ : 1;
449 u32 SSDSMARTerEnabled : 1;
450 u32 SSDPatrolReadEnabled : 1;
451 u32 enableSpinDownUnconfigured : 1;
452 u32 autoEnhancedImport : 1;
453 u32 enableSecretKeyControl : 1;
454 u32 disableOnlineCtrlReset : 1;
455 u32 allowBootWithPinnedCache : 1;
456 u32 disableSpinDownHS : 1;
457 u32 enableJBOD : 1;
458 u32 reserved :18;
459 } OnOffProperties;
460 u8 autoSnapVDSpace;
461 u8 viewSpace;
462 u16 spinDownTime;
463 u8 reserved[24];
81e403ce 464} __packed;
c4a3e0a5
BS		 465
466/*
467 * SAS controller information
468 */
469struct megasas_ctrl_info {
470
471 /*
472 * PCI device information
473 */
474 struct {
475
476 u16 vendor_id;
477 u16 device_id;
478 u16 sub_vendor_id;
479 u16 sub_device_id;
480 u8 reserved[24];
481
482 } __attribute__ ((packed)) pci;
483
484 /*
485 * Host interface information
486 */
487 struct {
488
489 u8 PCIX:1;
490 u8 PCIE:1;
491 u8 iSCSI:1;
492 u8 SAS_3G:1;
493 u8 reserved_0:4;
494 u8 reserved_1[6];
495 u8 port_count;
496 u64 port_addr[8];
497
498 } __attribute__ ((packed)) host_interface;
499
500 /*
501 * Device (backend) interface information
502 */
503 struct {
504
505 u8 SPI:1;
506 u8 SAS_3G:1;
507 u8 SATA_1_5G:1;
508 u8 SATA_3G:1;
509 u8 reserved_0:4;
510 u8 reserved_1[6];
511 u8 port_count;
512 u64 port_addr[8];
513
514 } __attribute__ ((packed)) device_interface;
515
516 /*
517 * List of components residing in flash. All str are null terminated
518 */
519 u32 image_check_word;
520 u32 image_component_count;
521
522 struct {
523
524 char name[8];
525 char version[32];
526 char build_date[16];
527 char built_time[16];
528
529 } __attribute__ ((packed)) image_component[8];
530
531 /*
532 * List of flash components that have been flashed on the card, but
533 * are not in use, pending reset of the adapter. This list will be
534 * empty if a flash operation has not occurred. All stings are null
535 * terminated
536 */
537 u32 pending_image_component_count;
538
539 struct {
540
541 char name[8];
542 char version[32];
543 char build_date[16];
544 char build_time[16];
545
546 } __attribute__ ((packed)) pending_image_component[8];
547
548 u8 max_arms;
549 u8 max_spans;
550 u8 max_arrays;
551 u8 max_lds;
552
553 char product_name[80];
554 char serial_no[32];
555
556 /*
557 * Other physical/controller/operation information. Indicates the
558 * presence of the hardware
559 */
560 struct {
561
562 u32 bbu:1;
563 u32 alarm:1;
564 u32 nvram:1;
565 u32 uart:1;
566 u32 reserved:28;
567
568 } __attribute__ ((packed)) hw_present;
569
570 u32 current_fw_time;
571
572 /*
573 * Maximum data transfer sizes
574 */
575 u16 max_concurrent_cmds;
576 u16 max_sge_count;
577 u32 max_request_size;
578
579 /*
580 * Logical and physical device counts
581 */
582 u16 ld_present_count;
583 u16 ld_degraded_count;
584 u16 ld_offline_count;
585
586 u16 pd_present_count;
587 u16 pd_disk_present_count;
588 u16 pd_disk_pred_failure_count;
589 u16 pd_disk_failed_count;
590
591 /*
592 * Memory size information
593 */
594 u16 nvram_size;
595 u16 memory_size;
596 u16 flash_size;
597
598 /*
599 * Error counters
600 */
601 u16 mem_correctable_error_count;
602 u16 mem_uncorrectable_error_count;
603
604 /*
605 * Cluster information
606 */
607 u8 cluster_permitted;
608 u8 cluster_active;
609
610 /*
611 * Additional max data transfer sizes
612 */
613 u16 max_strips_per_io;
614
615 /*
616 * Controller capabilities structures
617 */
618 struct {
619
620 u32 raid_level_0:1;
621 u32 raid_level_1:1;
622 u32 raid_level_5:1;
623 u32 raid_level_1E:1;
624 u32 raid_level_6:1;
625 u32 reserved:27;
626
627 } __attribute__ ((packed)) raid_levels;
628
629 struct {
630
631 u32 rbld_rate:1;
632 u32 cc_rate:1;
633 u32 bgi_rate:1;
634 u32 recon_rate:1;
635 u32 patrol_rate:1;
636 u32 alarm_control:1;
637 u32 cluster_supported:1;
638 u32 bbu:1;
639 u32 spanning_allowed:1;
640 u32 dedicated_hotspares:1;
641 u32 revertible_hotspares:1;
642 u32 foreign_config_import:1;
643 u32 self_diagnostic:1;
644 u32 mixed_redundancy_arr:1;
645 u32 global_hot_spares:1;
646 u32 reserved:17;
647
648 } __attribute__ ((packed)) adapter_operations;
649
650 struct {
651
652 u32 read_policy:1;
653 u32 write_policy:1;
654 u32 io_policy:1;
655 u32 access_policy:1;
656 u32 disk_cache_policy:1;
657 u32 reserved:27;
658
659 } __attribute__ ((packed)) ld_operations;
660
661 struct {
662
663 u8 min;
664 u8 max;
665 u8 reserved[2];
666
667 } __attribute__ ((packed)) stripe_sz_ops;
668
669 struct {
670
671 u32 force_online:1;
672 u32 force_offline:1;
673 u32 force_rebuild:1;
674 u32 reserved:29;
675
676 } __attribute__ ((packed)) pd_operations;
677
678 struct {
679
680 u32 ctrl_supports_sas:1;
681 u32 ctrl_supports_sata:1;
682 u32 allow_mix_in_encl:1;
683 u32 allow_mix_in_ld:1;
684 u32 allow_sata_in_cluster:1;
685 u32 reserved:27;
686
687 } __attribute__ ((packed)) pd_mix_support;
688
689 /*
690 * Define ECC single-bit-error bucket information
691 */
692 u8 ecc_bucket_count;
693 u8 reserved_2[11];
694
695 /*
696 * Include the controller properties (changeable items)
697 */
698 struct megasas_ctrl_prop properties;
699
700 /*
701 * Define FW pkg version (set in envt v'bles on OEM basis)
702 */
703 char package_version[0x60];
704
705 u8 pad[0x800 - 0x6a0];
706
81e403ce 707} __packed;
c4a3e0a5
BS		 708
709/*
710 * ===============================
711 * MegaRAID SAS driver definitions
712 * ===============================
713 */
714#define MEGASAS_MAX_PD_CHANNELS 2
715#define MEGASAS_MAX_LD_CHANNELS 2
716#define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
717 MEGASAS_MAX_LD_CHANNELS)
718#define MEGASAS_MAX_DEV_PER_CHANNEL 128
719#define MEGASAS_DEFAULT_INIT_ID -1
720#define MEGASAS_MAX_LUN 8
721#define MEGASAS_MAX_LD 64
6bf579a3 722#define MEGASAS_DEFAULT_CMD_PER_LUN 256
81e403ce
YB		 723#define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
724 MEGASAS_MAX_DEV_PER_CHANNEL)
bdc6fb8d
YB		 725#define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
726 MEGASAS_MAX_DEV_PER_CHANNEL)
c4a3e0a5 727
1fd10685 728#define MEGASAS_MAX_SECTORS (2*1024)
42a8d2b3 729#define MEGASAS_MAX_SECTORS_IEEE (2*128)
658dcedb
SP		 730#define MEGASAS_DBG_LVL 1
731
05e9ebbe
SP		 732#define MEGASAS_FW_BUSY 1
733
d532dbe2 734/* Frame Type */
735#define IO_FRAME 0
736#define PTHRU_FRAME 1
737
c4a3e0a5
BS		 738/*
739 * When SCSI mid-layer calls driver's reset routine, driver waits for
740 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
741 * that the driver cannot _actually_ abort or reset pending commands. While
742 * it is waiting for the commands to complete, it prints a diagnostic message
743 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
744 */
745#define MEGASAS_RESET_WAIT_TIME 180
2a3681e5 746#define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
c4a3e0a5 747#define MEGASAS_RESET_NOTICE_INTERVAL 5
c4a3e0a5 748#define MEGASAS_IOCTL_CMD 0
05e9ebbe 749#define MEGASAS_DEFAULT_CMD_TIMEOUT 90
c5daa6a9 750#define MEGASAS_THROTTLE_QUEUE_DEPTH 16
c4a3e0a5
BS		 751
752/*
753 * FW reports the maximum of number of commands that it can accept (maximum
754 * commands that can be outstanding) at any time. The driver must report a
755 * lower number to the mid layer because it can issue a few internal commands
756 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
757 * is shown below
758 */
759#define MEGASAS_INT_CMDS 32
7bebf5c7 760#define MEGASAS_SKINNY_INT_CMDS 5
c4a3e0a5 761
c8e858fe 762#define MEGASAS_MAX_MSIX_QUEUES 16
c4a3e0a5
BS		 763/*
764 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
765 * SGLs based on the size of dma_addr_t
766 */
767#define IS_DMA64 (sizeof(dma_addr_t) == 8)
768
39a98554 769#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
770
771#define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
772#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
773#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
774
c4a3e0a5 775#define MFI_OB_INTR_STATUS_MASK 0x00000002
14faea9f 776#define MFI_POLL_TIMEOUT_SECS 60
c4a3e0a5 777
f9876f0b 778#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
6610a6b3
YB		 779#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
780#define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
87911122
YB		 781#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
782#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
0e98936c 783
39a98554 784#define MFI_1068_PCSR_OFFSET 0x84
785#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
786#define MFI_1068_FW_READY 0xDDDD0000
0e98936c
SP		 787/*
788* register set for both 1068 and 1078 controllers
789* structure extended for 1078 registers
790*/
f9876f0b 791
c4a3e0a5 792struct megasas_register_set {
9c915a8c
AR		 793 u32 doorbell; /*0000h*/
794 u32 fusion_seq_offset; /*0004h*/
795 u32 fusion_host_diag; /*0008h*/
796 u32 reserved_01; /*000Ch*/
c4a3e0a5 797
f9876f0b
SP		 798 u32 inbound_msg_0; /*0010h*/
799 u32 inbound_msg_1; /*0014h*/
800 u32 outbound_msg_0; /*0018h*/
801 u32 outbound_msg_1; /*001Ch*/
c4a3e0a5 802
f9876f0b
SP		 803 u32 inbound_doorbell; /*0020h*/
804 u32 inbound_intr_status; /*0024h*/
805 u32 inbound_intr_mask; /*0028h*/
c4a3e0a5 806
f9876f0b
SP		 807 u32 outbound_doorbell; /*002Ch*/
808 u32 outbound_intr_status; /*0030h*/
809 u32 outbound_intr_mask; /*0034h*/
c4a3e0a5 810
f9876f0b 811 u32 reserved_1[2]; /*0038h*/
c4a3e0a5 812
f9876f0b
SP		 813 u32 inbound_queue_port; /*0040h*/
814 u32 outbound_queue_port; /*0044h*/
c4a3e0a5 815
9c915a8c
AR		 816 u32 reserved_2[9]; /*0048h*/
817 u32 reply_post_host_index; /*006Ch*/
818 u32 reserved_2_2[12]; /*0070h*/
c4a3e0a5 819
f9876f0b 820 u32 outbound_doorbell_clear; /*00A0h*/
c4a3e0a5 821
f9876f0b
SP		 822 u32 reserved_3[3]; /*00A4h*/
823
824 u32 outbound_scratch_pad ; /*00B0h*/
9c915a8c 825 u32 outbound_scratch_pad_2; /*00B4h*/
f9876f0b 826
9c915a8c 827 u32 reserved_4[2]; /*00B8h*/
f9876f0b
SP		 828
829 u32 inbound_low_queue_port ; /*00C0h*/
830
831 u32 inbound_high_queue_port ; /*00C4h*/
832
833 u32 reserved_5; /*00C8h*/
39a98554 834 u32 res_6[11]; /*CCh*/
835 u32 host_diag;
836 u32 seq_offset;
837 u32 index_registers[807]; /*00CCh*/
c4a3e0a5
BS		 838} __attribute__ ((packed));
839
840struct megasas_sge32 {
841
842 u32 phys_addr;
843 u32 length;
844
845} __attribute__ ((packed));
846
847struct megasas_sge64 {
848
849 u64 phys_addr;
850 u32 length;
851
852} __attribute__ ((packed));
853
f4c9a131
YB		 854struct megasas_sge_skinny {
855 u64 phys_addr;
856 u32 length;
857 u32 flag;
858} __packed;
859
c4a3e0a5
BS		 860union megasas_sgl {
861
862 struct megasas_sge32 sge32[1];
863 struct megasas_sge64 sge64[1];
f4c9a131 864 struct megasas_sge_skinny sge_skinny[1];
c4a3e0a5
BS		 865
866} __attribute__ ((packed));
867
868struct megasas_header {
869
870 u8 cmd; /*00h */
871 u8 sense_len; /*01h */
872 u8 cmd_status; /*02h */
873 u8 scsi_status; /*03h */
874
875 u8 target_id; /*04h */
876 u8 lun; /*05h */
877 u8 cdb_len; /*06h */
878 u8 sge_count; /*07h */
879
880 u32 context; /*08h */
881 u32 pad_0; /*0Ch */
882
883 u16 flags; /*10h */
884 u16 timeout; /*12h */
885 u32 data_xferlen; /*14h */
886
887} __attribute__ ((packed));
888
889union megasas_sgl_frame {
890
891 struct megasas_sge32 sge32[8];
892 struct megasas_sge64 sge64[5];
893
894} __attribute__ ((packed));
895
896struct megasas_init_frame {
897
898 u8 cmd; /*00h */
899 u8 reserved_0; /*01h */
900 u8 cmd_status; /*02h */
901
902 u8 reserved_1; /*03h */
903 u32 reserved_2; /*04h */
904
905 u32 context; /*08h */
906 u32 pad_0; /*0Ch */
907
908 u16 flags; /*10h */
909 u16 reserved_3; /*12h */
910 u32 data_xfer_len; /*14h */
911
912 u32 queue_info_new_phys_addr_lo; /*18h */
913 u32 queue_info_new_phys_addr_hi; /*1Ch */
914 u32 queue_info_old_phys_addr_lo; /*20h */
915 u32 queue_info_old_phys_addr_hi; /*24h */
916
917 u32 reserved_4[6]; /*28h */
918
919} __attribute__ ((packed));
920
921struct megasas_init_queue_info {
922
923 u32 init_flags; /*00h */
924 u32 reply_queue_entries; /*04h */
925
926 u32 reply_queue_start_phys_addr_lo; /*08h */
927 u32 reply_queue_start_phys_addr_hi; /*0Ch */
928 u32 producer_index_phys_addr_lo; /*10h */
929 u32 producer_index_phys_addr_hi; /*14h */
930 u32 consumer_index_phys_addr_lo; /*18h */
931 u32 consumer_index_phys_addr_hi; /*1Ch */
932
933} __attribute__ ((packed));
934
935struct megasas_io_frame {
936
937 u8 cmd; /*00h */
938 u8 sense_len; /*01h */
939 u8 cmd_status; /*02h */
940 u8 scsi_status; /*03h */
941
942 u8 target_id; /*04h */
943 u8 access_byte; /*05h */
944 u8 reserved_0; /*06h */
945 u8 sge_count; /*07h */
946
947 u32 context; /*08h */
948 u32 pad_0; /*0Ch */
949
950 u16 flags; /*10h */
951 u16 timeout; /*12h */
952 u32 lba_count; /*14h */
953
954 u32 sense_buf_phys_addr_lo; /*18h */
955 u32 sense_buf_phys_addr_hi; /*1Ch */
956
957 u32 start_lba_lo; /*20h */
958 u32 start_lba_hi; /*24h */
959
960 union megasas_sgl sgl; /*28h */
961
962} __attribute__ ((packed));
963
964struct megasas_pthru_frame {
965
966 u8 cmd; /*00h */
967 u8 sense_len; /*01h */
968 u8 cmd_status; /*02h */
969 u8 scsi_status; /*03h */
970
971 u8 target_id; /*04h */
972 u8 lun; /*05h */
973 u8 cdb_len; /*06h */
974 u8 sge_count; /*07h */
975
976 u32 context; /*08h */
977 u32 pad_0; /*0Ch */
978
979 u16 flags; /*10h */
980 u16 timeout; /*12h */
981 u32 data_xfer_len; /*14h */
982
983 u32 sense_buf_phys_addr_lo; /*18h */
984 u32 sense_buf_phys_addr_hi; /*1Ch */
985
986 u8 cdb[16]; /*20h */
987 union megasas_sgl sgl; /*30h */
988
989} __attribute__ ((packed));
990
991struct megasas_dcmd_frame {
992
993 u8 cmd; /*00h */
994 u8 reserved_0; /*01h */
995 u8 cmd_status; /*02h */
996 u8 reserved_1[4]; /*03h */
997 u8 sge_count; /*07h */
998
999 u32 context; /*08h */
1000 u32 pad_0; /*0Ch */
1001
1002 u16 flags; /*10h */
1003 u16 timeout; /*12h */
1004
1005 u32 data_xfer_len; /*14h */
1006 u32 opcode; /*18h */
1007
1008 union { /*1Ch */
1009 u8 b[12];
1010 u16 s[6];
1011 u32 w[3];
1012 } mbox;
1013
1014 union megasas_sgl sgl; /*28h */
1015
1016} __attribute__ ((packed));
1017
1018struct megasas_abort_frame {
1019
1020 u8 cmd; /*00h */
1021 u8 reserved_0; /*01h */
1022 u8 cmd_status; /*02h */
1023
1024 u8 reserved_1; /*03h */
1025 u32 reserved_2; /*04h */
1026
1027 u32 context; /*08h */
1028 u32 pad_0; /*0Ch */
1029
1030 u16 flags; /*10h */
1031 u16 reserved_3; /*12h */
1032 u32 reserved_4; /*14h */
1033
1034 u32 abort_context; /*18h */
1035 u32 pad_1; /*1Ch */
1036
1037 u32 abort_mfi_phys_addr_lo; /*20h */
1038 u32 abort_mfi_phys_addr_hi; /*24h */
1039
1040 u32 reserved_5[6]; /*28h */
1041
1042} __attribute__ ((packed));
1043
1044struct megasas_smp_frame {
1045
1046 u8 cmd; /*00h */
1047 u8 reserved_1; /*01h */
1048 u8 cmd_status; /*02h */
1049 u8 connection_status; /*03h */
1050
1051 u8 reserved_2[3]; /*04h */
1052 u8 sge_count; /*07h */
1053
1054 u32 context; /*08h */
1055 u32 pad_0; /*0Ch */
1056
1057 u16 flags; /*10h */
1058 u16 timeout; /*12h */
1059
1060 u32 data_xfer_len; /*14h */
1061 u64 sas_addr; /*18h */
1062
1063 union {
1064 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1065 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1066 } sgl;
1067
1068} __attribute__ ((packed));
1069
1070struct megasas_stp_frame {
1071
1072 u8 cmd; /*00h */
1073 u8 reserved_1; /*01h */
1074 u8 cmd_status; /*02h */
1075 u8 reserved_2; /*03h */
1076
1077 u8 target_id; /*04h */
1078 u8 reserved_3[2]; /*05h */
1079 u8 sge_count; /*07h */
1080
1081 u32 context; /*08h */
1082 u32 pad_0; /*0Ch */
1083
1084 u16 flags; /*10h */
1085 u16 timeout; /*12h */
1086
1087 u32 data_xfer_len; /*14h */
1088
1089 u16 fis[10]; /*18h */
1090 u32 stp_flags;
1091
1092 union {
1093 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1094 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1095 } sgl;
1096
1097} __attribute__ ((packed));
1098
1099union megasas_frame {
1100
1101 struct megasas_header hdr;
1102 struct megasas_init_frame init;
1103 struct megasas_io_frame io;
1104 struct megasas_pthru_frame pthru;
1105 struct megasas_dcmd_frame dcmd;
1106 struct megasas_abort_frame abort;
1107 struct megasas_smp_frame smp;
1108 struct megasas_stp_frame stp;
1109
1110 u8 raw_bytes[64];
1111};
1112
1113struct megasas_cmd;
1114
1115union megasas_evt_class_locale {
1116
1117 struct {
1118 u16 locale;
1119 u8 reserved;
1120 s8 class;
1121 } __attribute__ ((packed)) members;
1122
1123 u32 word;
1124
1125} __attribute__ ((packed));
1126
1127struct megasas_evt_log_info {
1128 u32 newest_seq_num;
1129 u32 oldest_seq_num;
1130 u32 clear_seq_num;
1131 u32 shutdown_seq_num;
1132 u32 boot_seq_num;
1133
1134} __attribute__ ((packed));
1135
1136struct megasas_progress {
1137
1138 u16 progress;
1139 u16 elapsed_seconds;
1140
1141} __attribute__ ((packed));
1142
1143struct megasas_evtarg_ld {
1144
1145 u16 target_id;
1146 u8 ld_index;
1147 u8 reserved;
1148
1149} __attribute__ ((packed));
1150
1151struct megasas_evtarg_pd {
1152 u16 device_id;
1153 u8 encl_index;
1154 u8 slot_number;
1155
1156} __attribute__ ((packed));
1157
1158struct megasas_evt_detail {
1159
1160 u32 seq_num;
1161 u32 time_stamp;
1162 u32 code;
1163 union megasas_evt_class_locale cl;
1164 u8 arg_type;
1165 u8 reserved1[15];
1166
1167 union {
1168 struct {
1169 struct megasas_evtarg_pd pd;
1170 u8 cdb_length;
1171 u8 sense_length;
1172 u8 reserved[2];
1173 u8 cdb[16];
1174 u8 sense[64];
1175 } __attribute__ ((packed)) cdbSense;
1176
1177 struct megasas_evtarg_ld ld;
1178
1179 struct {
1180 struct megasas_evtarg_ld ld;
1181 u64 count;
1182 } __attribute__ ((packed)) ld_count;
1183
1184 struct {
1185 u64 lba;
1186 struct megasas_evtarg_ld ld;
1187 } __attribute__ ((packed)) ld_lba;
1188
1189 struct {
1190 struct megasas_evtarg_ld ld;
1191 u32 prevOwner;
1192 u32 newOwner;
1193 } __attribute__ ((packed)) ld_owner;
1194
1195 struct {
1196 u64 ld_lba;
1197 u64 pd_lba;
1198 struct megasas_evtarg_ld ld;
1199 struct megasas_evtarg_pd pd;
1200 } __attribute__ ((packed)) ld_lba_pd_lba;
1201
1202 struct {
1203 struct megasas_evtarg_ld ld;
1204 struct megasas_progress prog;
1205 } __attribute__ ((packed)) ld_prog;
1206
1207 struct {
1208 struct megasas_evtarg_ld ld;
1209 u32 prev_state;
1210 u32 new_state;
1211 } __attribute__ ((packed)) ld_state;
1212
1213 struct {
1214 u64 strip;
1215 struct megasas_evtarg_ld ld;
1216 } __attribute__ ((packed)) ld_strip;
1217
1218 struct megasas_evtarg_pd pd;
1219
1220 struct {
1221 struct megasas_evtarg_pd pd;
1222 u32 err;
1223 } __attribute__ ((packed)) pd_err;
1224
1225 struct {
1226 u64 lba;
1227 struct megasas_evtarg_pd pd;
1228 } __attribute__ ((packed)) pd_lba;
1229
1230 struct {
1231 u64 lba;
1232 struct megasas_evtarg_pd pd;
1233 struct megasas_evtarg_ld ld;
1234 } __attribute__ ((packed)) pd_lba_ld;
1235
1236 struct {
1237 struct megasas_evtarg_pd pd;
1238 struct megasas_progress prog;
1239 } __attribute__ ((packed)) pd_prog;
1240
1241 struct {
1242 struct megasas_evtarg_pd pd;
1243 u32 prevState;
1244 u32 newState;
1245 } __attribute__ ((packed)) pd_state;
1246
1247 struct {
1248 u16 vendorId;
1249 u16 deviceId;
1250 u16 subVendorId;
1251 u16 subDeviceId;
1252 } __attribute__ ((packed)) pci;
1253
1254 u32 rate;
1255 char str[96];
1256
1257 struct {
1258 u32 rtc;
1259 u32 elapsedSeconds;
1260 } __attribute__ ((packed)) time;
1261
1262 struct {
1263 u32 ecar;
1264 u32 elog;
1265 char str[64];
1266 } __attribute__ ((packed)) ecc;
1267
1268 u8 b[96];
1269 u16 s[48];
1270 u32 w[24];
1271 u64 d[12];
1272 } args;
1273
1274 char description[128];
1275
1276} __attribute__ ((packed));
1277
7e8a75f4
YB		 1278struct megasas_aen_event {
1279 struct work_struct hotplug_work;
1280 struct megasas_instance *instance;
1281};
1282
c8e858fe
AR		 1283struct megasas_irq_context {
1284 struct megasas_instance *instance;
1285 u32 MSIxIndex;
1286};
1287
c4a3e0a5
BS		 1288struct megasas_instance {
1289
1290 u32 *producer;
1291 dma_addr_t producer_h;
1292 u32 *consumer;
1293 dma_addr_t consumer_h;
1294
1295 u32 *reply_queue;
1296 dma_addr_t reply_queue_h;
1297
1298 unsigned long base_addr;
1299 struct megasas_register_set __iomem *reg_set;
1300
81e403ce 1301 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
bdc6fb8d 1302 u8 ld_ids[MEGASAS_MAX_LD_IDS];
c4a3e0a5 1303 s8 init_id;
c4a3e0a5
BS		 1304
1305 u16 max_num_sge;
1306 u16 max_fw_cmds;
9c915a8c
AR		 1307 /* For Fusion its num IOCTL cmds, for others MFI based its
1308 max_fw_cmds */
1309 u16 max_mfi_cmds;
c4a3e0a5 1310 u32 max_sectors_per_req;
7e8a75f4 1311 struct megasas_aen_event *ev;
c4a3e0a5
BS		 1312
1313 struct megasas_cmd **cmd_list;
1314 struct list_head cmd_pool;
39a98554 1315 /* used to sync fire the cmd to fw */
c4a3e0a5 1316 spinlock_t cmd_pool_lock;
39a98554 1317 /* used to sync fire the cmd to fw */
1318 spinlock_t hba_lock;
7343eb65 1319 /* used to synch producer, consumer ptrs in dpc */
1320 spinlock_t completion_lock;
c4a3e0a5
BS		 1321 struct dma_pool *frame_dma_pool;
1322 struct dma_pool *sense_dma_pool;
1323
1324 struct megasas_evt_detail *evt_detail;
1325 dma_addr_t evt_detail_h;
1326 struct megasas_cmd *aen_cmd;
e5a69e27 1327 struct mutex aen_mutex;
c4a3e0a5
BS		 1328 struct semaphore ioctl_sem;
1329
1330 struct Scsi_Host *host;
1331
1332 wait_queue_head_t int_cmd_wait_q;
1333 wait_queue_head_t abort_cmd_wait_q;
1334
1335 struct pci_dev *pdev;
1336 u32 unique_id;
39a98554 1337 u32 fw_support_ieee;
c4a3e0a5 1338
e4a082c7 1339 atomic_t fw_outstanding;
39a98554 1340 atomic_t fw_reset_no_pci_access;
1341c939
SP		 1341
1342 struct megasas_instance_template *instancet;
5d018ad0 1343 struct tasklet_struct isr_tasklet;
39a98554 1344 struct work_struct work_init;
05e9ebbe
SP		 1345
1346 u8 flag;
c3518837 1347 u8 unload;
f4c9a131 1348 u8 flag_ieee;
39a98554 1349 u8 issuepend_done;
1350 u8 disableOnlineCtrlReset;
1351 u8 adprecovery;
05e9ebbe 1352 unsigned long last_time;
39a98554 1353 u32 mfiStatus;
1354 u32 last_seq_num;
ad84db2e 1355
39a98554 1356 struct list_head internal_reset_pending_q;
80d9da98 1357
25985edc 1358 /* Ptr to hba specific information */
9c915a8c 1359 void *ctrl_context;
c8e858fe
AR		 1360 unsigned int msix_vectors;
1361 struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES];
1362 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
9c915a8c
AR		 1363 u64 map_id;
1364 struct megasas_cmd *map_update_cmd;
b6d5d880 1365 unsigned long bar;
9c915a8c
AR		 1366 long reset_flags;
1367 struct mutex reset_mutex;
c5daa6a9 1368 int throttlequeuedepth;
39a98554 1369};
1370
1371enum {
1372 MEGASAS_HBA_OPERATIONAL = 0,
1373 MEGASAS_ADPRESET_SM_INFAULT = 1,
1374 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1375 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
1376 MEGASAS_HW_CRITICAL_ERROR = 4,
1377 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
c4a3e0a5
BS		 1378};
1379
0c79e681
YB		 1380struct megasas_instance_template {
1381 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1382 u32, struct megasas_register_set __iomem *);
1383
1384 void (*enable_intr)(struct megasas_register_set __iomem *) ;
1385 void (*disable_intr)(struct megasas_register_set __iomem *);
1386
1387 int (*clear_intr)(struct megasas_register_set __iomem *);
1388
1389 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
39a98554 1390 int (*adp_reset)(struct megasas_instance *, \
1391 struct megasas_register_set __iomem *);
1392 int (*check_reset)(struct megasas_instance *, \
1393 struct megasas_register_set __iomem *);
cd50ba8e
AR		 1394 irqreturn_t (*service_isr)(int irq, void *devp);
1395 void (*tasklet)(unsigned long);
1396 u32 (*init_adapter)(struct megasas_instance *);
1397 u32 (*build_and_issue_cmd) (struct megasas_instance *,
1398 struct scsi_cmnd *);
1399 void (*issue_dcmd) (struct megasas_instance *instance,
1400 struct megasas_cmd *cmd);
0c79e681
YB		 1401};
1402
c4a3e0a5
BS		 1403#define MEGASAS_IS_LOGICAL(scp) \
1404 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1405
1406#define MEGASAS_DEV_INDEX(inst, scp) \
1407 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1408 scp->device->id
1409
1410struct megasas_cmd {
1411
1412 union megasas_frame *frame;
1413 dma_addr_t frame_phys_addr;
1414 u8 *sense;
1415 dma_addr_t sense_phys_addr;
1416
1417 u32 index;
1418 u8 sync_cmd;
1419 u8 cmd_status;
39a98554 1420 u8 abort_aen;
1421 u8 retry_for_fw_reset;
1422
c4a3e0a5
BS		 1423
1424 struct list_head list;
1425 struct scsi_cmnd *scmd;
1426 struct megasas_instance *instance;
9c915a8c
AR		 1427 union {
1428 struct {
1429 u16 smid;
1430 u16 resvd;
1431 } context;
1432 u32 frame_count;
1433 };
c4a3e0a5
BS		 1434};
1435
1436#define MAX_MGMT_ADAPTERS 1024
1437#define MAX_IOCTL_SGE 16
1438
1439struct megasas_iocpacket {
1440
1441 u16 host_no;
1442 u16 __pad1;
1443 u32 sgl_off;
1444 u32 sge_count;
1445 u32 sense_off;
1446 u32 sense_len;
1447 union {
1448 u8 raw[128];
1449 struct megasas_header hdr;
1450 } frame;
1451
1452 struct iovec sgl[MAX_IOCTL_SGE];
1453
1454} __attribute__ ((packed));
1455
1456struct megasas_aen {
1457 u16 host_no;
1458 u16 __pad1;
1459 u32 seq_num;
1460 u32 class_locale_word;
1461} __attribute__ ((packed));
1462
1463#ifdef CONFIG_COMPAT
1464struct compat_megasas_iocpacket {
1465 u16 host_no;
1466 u16 __pad1;
1467 u32 sgl_off;
1468 u32 sge_count;
1469 u32 sense_off;
1470 u32 sense_len;
1471 union {
1472 u8 raw[128];
1473 struct megasas_header hdr;
1474 } frame;
1475 struct compat_iovec sgl[MAX_IOCTL_SGE];
1476} __attribute__ ((packed));
1477
0e98936c 1478#define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
c4a3e0a5
BS		 1479#endif
1480
cb59aa6a 1481#define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
c4a3e0a5
BS		 1482#define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1483
1484struct megasas_mgmt_info {
1485
1486 u16 count;
1487 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1488 int max_index;
1489};
1490
66192dfe
AR		 1491#define msi_control_reg(base) (base + PCI_MSI_FLAGS)
1492#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
1493
c4a3e0a5 1494#endif /*LSI_MEGARAID_SAS_H */
kernel source for telekom puls (alcatel/mediatek)