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[SCSI] megaraid_sas: Add struct megasas_instance_template changes
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / megaraid / megaraid_sas.h
CommitLineData
c4a3e0a5 1/*
3f1530c1 2 * Linux MegaRAID driver for SAS based RAID controllers
c4a3e0a5 3 *
3f1530c1 4 * Copyright (c) 2009-2011 LSI Corporation.
c4a3e0a5 5 *
3f1530c1
AR		 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
c4a3e0a5 10 *
3f1530c1
AR		 11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
c4a3e0a5 15 *
3f1530c1
AR		 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * FILE: megaraid_sas.h
21 *
22 * Authors: LSI Corporation
23 *
24 * Send feedback to: <megaraidlinux@lsi.com>
25 *
26 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
27 * ATTN: Linuxraid
c4a3e0a5
BS		 28 */
29
30#ifndef LSI_MEGARAID_SAS_H
31#define LSI_MEGARAID_SAS_H
32
a69b74d3 33/*
c4a3e0a5
BS		 34 * MegaRAID SAS Driver meta data
35 */
e340c353
YB		 36#define MEGASAS_VERSION "00.00.04.31-rc1"
37#define MEGASAS_RELDATE "May 3, 2010"
38#define MEGASAS_EXT_VERSION "Mon. May 3, 11:41:51 PST 2010"
0e98936c
SP		 39
40/*
41 * Device IDs
42 */
43#define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
af7a5647 44#define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
0e98936c 45#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
6610a6b3
YB		 46#define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
47#define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
87911122
YB		 48#define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
49#define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
0e98936c 50
c4a3e0a5
BS		 51/*
52 * =====================================
53 * MegaRAID SAS MFI firmware definitions
54 * =====================================
55 */
56
57/*
58 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
59 * protocol between the software and firmware. Commands are issued using
60 * "message frames"
61 */
62
a69b74d3 63/*
c4a3e0a5
BS		 64 * FW posts its state in upper 4 bits of outbound_msg_0 register
65 */
66#define MFI_STATE_MASK 0xF0000000
67#define MFI_STATE_UNDEFINED 0x00000000
68#define MFI_STATE_BB_INIT 0x10000000
69#define MFI_STATE_FW_INIT 0x40000000
70#define MFI_STATE_WAIT_HANDSHAKE 0x60000000
71#define MFI_STATE_FW_INIT_2 0x70000000
72#define MFI_STATE_DEVICE_SCAN 0x80000000
e3bbff9f 73#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
c4a3e0a5
BS		 74#define MFI_STATE_FLUSH_CACHE 0xA0000000
75#define MFI_STATE_READY 0xB0000000
76#define MFI_STATE_OPERATIONAL 0xC0000000
77#define MFI_STATE_FAULT 0xF0000000
39a98554 78#define MFI_RESET_REQUIRED 0x00000001
c4a3e0a5
BS		 79
80#define MEGAMFI_FRAME_SIZE 64
81
a69b74d3 82/*
c4a3e0a5
BS		 83 * During FW init, clear pending cmds & reset state using inbound_msg_0
84 *
85 * ABORT : Abort all pending cmds
86 * READY : Move from OPERATIONAL to READY state; discard queue info
87 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
88 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
e3bbff9f
SP		 89 * HOTPLUG : Resume from Hotplug
90 * MFI_STOP_ADP : Send signal to FW to stop processing
c4a3e0a5 91 */
39a98554 92#define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
93#define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
94#define DIAG_WRITE_ENABLE (0x00000080)
95#define DIAG_RESET_ADAPTER (0x00000004)
96
97#define MFI_ADP_RESET 0x00000040
e3bbff9f 98#define MFI_INIT_ABORT 0x00000001
c4a3e0a5
BS		 99#define MFI_INIT_READY 0x00000002
100#define MFI_INIT_MFIMODE 0x00000004
101#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
e3bbff9f
SP		 102#define MFI_INIT_HOTPLUG 0x00000010
103#define MFI_STOP_ADP 0x00000020
104#define MFI_RESET_FLAGS MFI_INIT_READY| \
105 MFI_INIT_MFIMODE| \
106 MFI_INIT_ABORT
c4a3e0a5 107
a69b74d3 108/*
c4a3e0a5
BS		 109 * MFI frame flags
110 */
111#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
112#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
113#define MFI_FRAME_SGL32 0x0000
114#define MFI_FRAME_SGL64 0x0002
115#define MFI_FRAME_SENSE32 0x0000
116#define MFI_FRAME_SENSE64 0x0004
117#define MFI_FRAME_DIR_NONE 0x0000
118#define MFI_FRAME_DIR_WRITE 0x0008
119#define MFI_FRAME_DIR_READ 0x0010
120#define MFI_FRAME_DIR_BOTH 0x0018
f4c9a131 121#define MFI_FRAME_IEEE 0x0020
c4a3e0a5 122
a69b74d3 123/*
c4a3e0a5
BS		 124 * Definition for cmd_status
125 */
126#define MFI_CMD_STATUS_POLL_MODE 0xFF
127
a69b74d3 128/*
c4a3e0a5
BS		 129 * MFI command opcodes
130 */
131#define MFI_CMD_INIT 0x00
132#define MFI_CMD_LD_READ 0x01
133#define MFI_CMD_LD_WRITE 0x02
134#define MFI_CMD_LD_SCSI_IO 0x03
135#define MFI_CMD_PD_SCSI_IO 0x04
136#define MFI_CMD_DCMD 0x05
137#define MFI_CMD_ABORT 0x06
138#define MFI_CMD_SMP 0x07
139#define MFI_CMD_STP 0x08
140
141#define MR_DCMD_CTRL_GET_INFO 0x01010000
bdc6fb8d 142#define MR_DCMD_LD_GET_LIST 0x03010000
c4a3e0a5
BS		 143
144#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
145#define MR_FLUSH_CTRL_CACHE 0x01
146#define MR_FLUSH_DISK_CACHE 0x02
147
148#define MR_DCMD_CTRL_SHUTDOWN 0x01050000
31ea7088 149#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
c4a3e0a5
BS		 150#define MR_ENABLE_DRIVE_SPINDOWN 0x01
151
152#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
153#define MR_DCMD_CTRL_EVENT_GET 0x01040300
154#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
155#define MR_DCMD_LD_GET_PROPERTIES 0x03030000
156
157#define MR_DCMD_CLUSTER 0x08000000
158#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
159#define MR_DCMD_CLUSTER_RESET_LD 0x08010200
81e403ce 160#define MR_DCMD_PD_LIST_QUERY 0x02010100
c4a3e0a5 161
a69b74d3 162/*
c4a3e0a5
BS		 163 * MFI command completion codes
164 */
165enum MFI_STAT {
166 MFI_STAT_OK = 0x00,
167 MFI_STAT_INVALID_CMD = 0x01,
168 MFI_STAT_INVALID_DCMD = 0x02,
169 MFI_STAT_INVALID_PARAMETER = 0x03,
170 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
171 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
172 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
173 MFI_STAT_APP_IN_USE = 0x07,
174 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
175 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
176 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
177 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
178 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
179 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
180 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
181 MFI_STAT_FLASH_BUSY = 0x0f,
182 MFI_STAT_FLASH_ERROR = 0x10,
183 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
184 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
185 MFI_STAT_FLASH_NOT_OPEN = 0x13,
186 MFI_STAT_FLASH_NOT_STARTED = 0x14,
187 MFI_STAT_FLUSH_FAILED = 0x15,
188 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
189 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
190 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
191 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
192 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
193 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
194 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
195 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
196 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
197 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
198 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
199 MFI_STAT_MFC_HW_ERROR = 0x21,
200 MFI_STAT_NO_HW_PRESENT = 0x22,
201 MFI_STAT_NOT_FOUND = 0x23,
202 MFI_STAT_NOT_IN_ENCL = 0x24,
203 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
204 MFI_STAT_PD_TYPE_WRONG = 0x26,
205 MFI_STAT_PR_DISABLED = 0x27,
206 MFI_STAT_ROW_INDEX_INVALID = 0x28,
207 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
208 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
209 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
210 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
211 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
212 MFI_STAT_SCSI_IO_FAILED = 0x2e,
213 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
214 MFI_STAT_SHUTDOWN_FAILED = 0x30,
215 MFI_STAT_TIME_NOT_SET = 0x31,
216 MFI_STAT_WRONG_STATE = 0x32,
217 MFI_STAT_LD_OFFLINE = 0x33,
218 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
219 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
220 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
221 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
222 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
223
224 MFI_STAT_INVALID_STATUS = 0xFF
225};
226
227/*
228 * Number of mailbox bytes in DCMD message frame
229 */
230#define MFI_MBOX_SIZE 12
231
232enum MR_EVT_CLASS {
233
234 MR_EVT_CLASS_DEBUG = -2,
235 MR_EVT_CLASS_PROGRESS = -1,
236 MR_EVT_CLASS_INFO = 0,
237 MR_EVT_CLASS_WARNING = 1,
238 MR_EVT_CLASS_CRITICAL = 2,
239 MR_EVT_CLASS_FATAL = 3,
240 MR_EVT_CLASS_DEAD = 4,
241
242};
243
244enum MR_EVT_LOCALE {
245
246 MR_EVT_LOCALE_LD = 0x0001,
247 MR_EVT_LOCALE_PD = 0x0002,
248 MR_EVT_LOCALE_ENCL = 0x0004,
249 MR_EVT_LOCALE_BBU = 0x0008,
250 MR_EVT_LOCALE_SAS = 0x0010,
251 MR_EVT_LOCALE_CTRL = 0x0020,
252 MR_EVT_LOCALE_CONFIG = 0x0040,
253 MR_EVT_LOCALE_CLUSTER = 0x0080,
254 MR_EVT_LOCALE_ALL = 0xffff,
255
256};
257
258enum MR_EVT_ARGS {
259
260 MR_EVT_ARGS_NONE,
261 MR_EVT_ARGS_CDB_SENSE,
262 MR_EVT_ARGS_LD,
263 MR_EVT_ARGS_LD_COUNT,
264 MR_EVT_ARGS_LD_LBA,
265 MR_EVT_ARGS_LD_OWNER,
266 MR_EVT_ARGS_LD_LBA_PD_LBA,
267 MR_EVT_ARGS_LD_PROG,
268 MR_EVT_ARGS_LD_STATE,
269 MR_EVT_ARGS_LD_STRIP,
270 MR_EVT_ARGS_PD,
271 MR_EVT_ARGS_PD_ERR,
272 MR_EVT_ARGS_PD_LBA,
273 MR_EVT_ARGS_PD_LBA_LD,
274 MR_EVT_ARGS_PD_PROG,
275 MR_EVT_ARGS_PD_STATE,
276 MR_EVT_ARGS_PCI,
277 MR_EVT_ARGS_RATE,
278 MR_EVT_ARGS_STR,
279 MR_EVT_ARGS_TIME,
280 MR_EVT_ARGS_ECC,
81e403ce
YB		 281 MR_EVT_ARGS_LD_PROP,
282 MR_EVT_ARGS_PD_SPARE,
283 MR_EVT_ARGS_PD_INDEX,
284 MR_EVT_ARGS_DIAG_PASS,
285 MR_EVT_ARGS_DIAG_FAIL,
286 MR_EVT_ARGS_PD_LBA_LBA,
287 MR_EVT_ARGS_PORT_PHY,
288 MR_EVT_ARGS_PD_MISSING,
289 MR_EVT_ARGS_PD_ADDRESS,
290 MR_EVT_ARGS_BITMAP,
291 MR_EVT_ARGS_CONNECTOR,
292 MR_EVT_ARGS_PD_PD,
293 MR_EVT_ARGS_PD_FRU,
294 MR_EVT_ARGS_PD_PATHINFO,
295 MR_EVT_ARGS_PD_POWER_STATE,
296 MR_EVT_ARGS_GENERIC,
297};
c4a3e0a5 298
81e403ce
YB		 299/*
300 * define constants for device list query options
301 */
302enum MR_PD_QUERY_TYPE {
303 MR_PD_QUERY_TYPE_ALL = 0,
304 MR_PD_QUERY_TYPE_STATE = 1,
305 MR_PD_QUERY_TYPE_POWER_STATE = 2,
306 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
307 MR_PD_QUERY_TYPE_SPEED = 4,
308 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
c4a3e0a5
BS		 309};
310
7e8a75f4
YB		 311#define MR_EVT_CFG_CLEARED 0x0004
312#define MR_EVT_LD_STATE_CHANGE 0x0051
313#define MR_EVT_PD_INSERTED 0x005b
314#define MR_EVT_PD_REMOVED 0x0070
315#define MR_EVT_LD_CREATED 0x008a
316#define MR_EVT_LD_DELETED 0x008b
317#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
318#define MR_EVT_LD_OFFLINE 0x00fc
319#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
320#define MAX_LOGICAL_DRIVES 64
321
81e403ce
YB		 322enum MR_PD_STATE {
323 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
324 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
325 MR_PD_STATE_HOT_SPARE = 0x02,
326 MR_PD_STATE_OFFLINE = 0x10,
327 MR_PD_STATE_FAILED = 0x11,
328 MR_PD_STATE_REBUILD = 0x14,
329 MR_PD_STATE_ONLINE = 0x18,
330 MR_PD_STATE_COPYBACK = 0x20,
331 MR_PD_STATE_SYSTEM = 0x40,
332 };
333
334
335 /*
336 * defines the physical drive address structure
337 */
338struct MR_PD_ADDRESS {
339 u16 deviceId;
340 u16 enclDeviceId;
341
342 union {
343 struct {
344 u8 enclIndex;
345 u8 slotNumber;
346 } mrPdAddress;
347 struct {
348 u8 enclPosition;
349 u8 enclConnectorIndex;
350 } mrEnclAddress;
351 };
352 u8 scsiDevType;
353 union {
354 u8 connectedPortBitmap;
355 u8 connectedPortNumbers;
356 };
357 u64 sasAddr[2];
358} __packed;
359
360/*
361 * defines the physical drive list structure
362 */
363struct MR_PD_LIST {
364 u32 size;
365 u32 count;
366 struct MR_PD_ADDRESS addr[1];
367} __packed;
368
369struct megasas_pd_list {
370 u16 tid;
371 u8 driveType;
372 u8 driveState;
373} __packed;
374
bdc6fb8d
YB		 375 /*
376 * defines the logical drive reference structure
377 */
378union MR_LD_REF {
379 struct {
380 u8 targetId;
381 u8 reserved;
382 u16 seqNum;
383 };
384 u32 ref;
385} __packed;
386
387/*
388 * defines the logical drive list structure
389 */
390struct MR_LD_LIST {
391 u32 ldCount;
392 u32 reserved;
393 struct {
394 union MR_LD_REF ref;
395 u8 state;
396 u8 reserved[3];
397 u64 size;
398 } ldList[MAX_LOGICAL_DRIVES];
399} __packed;
400
c4a3e0a5
BS		 401/*
402 * SAS controller properties
403 */
404struct megasas_ctrl_prop {
405
406 u16 seq_num;
407 u16 pred_fail_poll_interval;
408 u16 intr_throttle_count;
409 u16 intr_throttle_timeouts;
410 u8 rebuild_rate;
411 u8 patrol_read_rate;
412 u8 bgi_rate;
413 u8 cc_rate;
414 u8 recon_rate;
415 u8 cache_flush_interval;
416 u8 spinup_drv_count;
417 u8 spinup_delay;
418 u8 cluster_enable;
419 u8 coercion_mode;
420 u8 alarm_enable;
421 u8 disable_auto_rebuild;
422 u8 disable_battery_warn;
423 u8 ecc_bucket_size;
424 u16 ecc_bucket_leak_rate;
425 u8 restore_hotspare_on_insertion;
426 u8 expose_encl_devices;
39a98554 427 u8 maintainPdFailHistory;
428 u8 disallowHostRequestReordering;
429 u8 abortCCOnError;
430 u8 loadBalanceMode;
431 u8 disableAutoDetectBackplane;
432
433 u8 snapVDSpace;
434
435 /*
436 * Add properties that can be controlled by
437 * a bit in the following structure.
438 */
c4a3e0a5 439
39a98554 440 struct {
441 u32 copyBackDisabled : 1;
442 u32 SMARTerEnabled : 1;
443 u32 prCorrectUnconfiguredAreas : 1;
444 u32 useFdeOnly : 1;
445 u32 disableNCQ : 1;
446 u32 SSDSMARTerEnabled : 1;
447 u32 SSDPatrolReadEnabled : 1;
448 u32 enableSpinDownUnconfigured : 1;
449 u32 autoEnhancedImport : 1;
450 u32 enableSecretKeyControl : 1;
451 u32 disableOnlineCtrlReset : 1;
452 u32 allowBootWithPinnedCache : 1;
453 u32 disableSpinDownHS : 1;
454 u32 enableJBOD : 1;
455 u32 reserved :18;
456 } OnOffProperties;
457 u8 autoSnapVDSpace;
458 u8 viewSpace;
459 u16 spinDownTime;
460 u8 reserved[24];
81e403ce 461} __packed;
c4a3e0a5
BS		 462
463/*
464 * SAS controller information
465 */
466struct megasas_ctrl_info {
467
468 /*
469 * PCI device information
470 */
471 struct {
472
473 u16 vendor_id;
474 u16 device_id;
475 u16 sub_vendor_id;
476 u16 sub_device_id;
477 u8 reserved[24];
478
479 } __attribute__ ((packed)) pci;
480
481 /*
482 * Host interface information
483 */
484 struct {
485
486 u8 PCIX:1;
487 u8 PCIE:1;
488 u8 iSCSI:1;
489 u8 SAS_3G:1;
490 u8 reserved_0:4;
491 u8 reserved_1[6];
492 u8 port_count;
493 u64 port_addr[8];
494
495 } __attribute__ ((packed)) host_interface;
496
497 /*
498 * Device (backend) interface information
499 */
500 struct {
501
502 u8 SPI:1;
503 u8 SAS_3G:1;
504 u8 SATA_1_5G:1;
505 u8 SATA_3G:1;
506 u8 reserved_0:4;
507 u8 reserved_1[6];
508 u8 port_count;
509 u64 port_addr[8];
510
511 } __attribute__ ((packed)) device_interface;
512
513 /*
514 * List of components residing in flash. All str are null terminated
515 */
516 u32 image_check_word;
517 u32 image_component_count;
518
519 struct {
520
521 char name[8];
522 char version[32];
523 char build_date[16];
524 char built_time[16];
525
526 } __attribute__ ((packed)) image_component[8];
527
528 /*
529 * List of flash components that have been flashed on the card, but
530 * are not in use, pending reset of the adapter. This list will be
531 * empty if a flash operation has not occurred. All stings are null
532 * terminated
533 */
534 u32 pending_image_component_count;
535
536 struct {
537
538 char name[8];
539 char version[32];
540 char build_date[16];
541 char build_time[16];
542
543 } __attribute__ ((packed)) pending_image_component[8];
544
545 u8 max_arms;
546 u8 max_spans;
547 u8 max_arrays;
548 u8 max_lds;
549
550 char product_name[80];
551 char serial_no[32];
552
553 /*
554 * Other physical/controller/operation information. Indicates the
555 * presence of the hardware
556 */
557 struct {
558
559 u32 bbu:1;
560 u32 alarm:1;
561 u32 nvram:1;
562 u32 uart:1;
563 u32 reserved:28;
564
565 } __attribute__ ((packed)) hw_present;
566
567 u32 current_fw_time;
568
569 /*
570 * Maximum data transfer sizes
571 */
572 u16 max_concurrent_cmds;
573 u16 max_sge_count;
574 u32 max_request_size;
575
576 /*
577 * Logical and physical device counts
578 */
579 u16 ld_present_count;
580 u16 ld_degraded_count;
581 u16 ld_offline_count;
582
583 u16 pd_present_count;
584 u16 pd_disk_present_count;
585 u16 pd_disk_pred_failure_count;
586 u16 pd_disk_failed_count;
587
588 /*
589 * Memory size information
590 */
591 u16 nvram_size;
592 u16 memory_size;
593 u16 flash_size;
594
595 /*
596 * Error counters
597 */
598 u16 mem_correctable_error_count;
599 u16 mem_uncorrectable_error_count;
600
601 /*
602 * Cluster information
603 */
604 u8 cluster_permitted;
605 u8 cluster_active;
606
607 /*
608 * Additional max data transfer sizes
609 */
610 u16 max_strips_per_io;
611
612 /*
613 * Controller capabilities structures
614 */
615 struct {
616
617 u32 raid_level_0:1;
618 u32 raid_level_1:1;
619 u32 raid_level_5:1;
620 u32 raid_level_1E:1;
621 u32 raid_level_6:1;
622 u32 reserved:27;
623
624 } __attribute__ ((packed)) raid_levels;
625
626 struct {
627
628 u32 rbld_rate:1;
629 u32 cc_rate:1;
630 u32 bgi_rate:1;
631 u32 recon_rate:1;
632 u32 patrol_rate:1;
633 u32 alarm_control:1;
634 u32 cluster_supported:1;
635 u32 bbu:1;
636 u32 spanning_allowed:1;
637 u32 dedicated_hotspares:1;
638 u32 revertible_hotspares:1;
639 u32 foreign_config_import:1;
640 u32 self_diagnostic:1;
641 u32 mixed_redundancy_arr:1;
642 u32 global_hot_spares:1;
643 u32 reserved:17;
644
645 } __attribute__ ((packed)) adapter_operations;
646
647 struct {
648
649 u32 read_policy:1;
650 u32 write_policy:1;
651 u32 io_policy:1;
652 u32 access_policy:1;
653 u32 disk_cache_policy:1;
654 u32 reserved:27;
655
656 } __attribute__ ((packed)) ld_operations;
657
658 struct {
659
660 u8 min;
661 u8 max;
662 u8 reserved[2];
663
664 } __attribute__ ((packed)) stripe_sz_ops;
665
666 struct {
667
668 u32 force_online:1;
669 u32 force_offline:1;
670 u32 force_rebuild:1;
671 u32 reserved:29;
672
673 } __attribute__ ((packed)) pd_operations;
674
675 struct {
676
677 u32 ctrl_supports_sas:1;
678 u32 ctrl_supports_sata:1;
679 u32 allow_mix_in_encl:1;
680 u32 allow_mix_in_ld:1;
681 u32 allow_sata_in_cluster:1;
682 u32 reserved:27;
683
684 } __attribute__ ((packed)) pd_mix_support;
685
686 /*
687 * Define ECC single-bit-error bucket information
688 */
689 u8 ecc_bucket_count;
690 u8 reserved_2[11];
691
692 /*
693 * Include the controller properties (changeable items)
694 */
695 struct megasas_ctrl_prop properties;
696
697 /*
698 * Define FW pkg version (set in envt v'bles on OEM basis)
699 */
700 char package_version[0x60];
701
702 u8 pad[0x800 - 0x6a0];
703
81e403ce 704} __packed;
c4a3e0a5
BS		 705
706/*
707 * ===============================
708 * MegaRAID SAS driver definitions
709 * ===============================
710 */
711#define MEGASAS_MAX_PD_CHANNELS 2
712#define MEGASAS_MAX_LD_CHANNELS 2
713#define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
714 MEGASAS_MAX_LD_CHANNELS)
715#define MEGASAS_MAX_DEV_PER_CHANNEL 128
716#define MEGASAS_DEFAULT_INIT_ID -1
717#define MEGASAS_MAX_LUN 8
718#define MEGASAS_MAX_LD 64
81e403ce
YB		 719#define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
720 MEGASAS_MAX_DEV_PER_CHANNEL)
bdc6fb8d
YB		 721#define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
722 MEGASAS_MAX_DEV_PER_CHANNEL)
c4a3e0a5 723
1fd10685 724#define MEGASAS_MAX_SECTORS (2*1024)
658dcedb
SP		 725#define MEGASAS_DBG_LVL 1
726
05e9ebbe
SP		 727#define MEGASAS_FW_BUSY 1
728
d532dbe2 729/* Frame Type */
730#define IO_FRAME 0
731#define PTHRU_FRAME 1
732
c4a3e0a5
BS		 733/*
734 * When SCSI mid-layer calls driver's reset routine, driver waits for
735 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
736 * that the driver cannot _actually_ abort or reset pending commands. While
737 * it is waiting for the commands to complete, it prints a diagnostic message
738 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
739 */
740#define MEGASAS_RESET_WAIT_TIME 180
2a3681e5 741#define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
c4a3e0a5 742#define MEGASAS_RESET_NOTICE_INTERVAL 5
c4a3e0a5 743#define MEGASAS_IOCTL_CMD 0
05e9ebbe 744#define MEGASAS_DEFAULT_CMD_TIMEOUT 90
c4a3e0a5
BS		 745
746/*
747 * FW reports the maximum of number of commands that it can accept (maximum
748 * commands that can be outstanding) at any time. The driver must report a
749 * lower number to the mid layer because it can issue a few internal commands
750 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
751 * is shown below
752 */
753#define MEGASAS_INT_CMDS 32
7bebf5c7 754#define MEGASAS_SKINNY_INT_CMDS 5
c4a3e0a5
BS		 755
756/*
757 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
758 * SGLs based on the size of dma_addr_t
759 */
760#define IS_DMA64 (sizeof(dma_addr_t) == 8)
761
39a98554 762#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
763
764#define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
765#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
766#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
767
c4a3e0a5 768#define MFI_OB_INTR_STATUS_MASK 0x00000002
14faea9f 769#define MFI_POLL_TIMEOUT_SECS 60
ad84db2e 770#define MEGASAS_COMPLETION_TIMER_INTERVAL (HZ/10)
c4a3e0a5 771
f9876f0b 772#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
6610a6b3
YB		 773#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
774#define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
87911122
YB		 775#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
776#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
0e98936c 777
39a98554 778#define MFI_1068_PCSR_OFFSET 0x84
779#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
780#define MFI_1068_FW_READY 0xDDDD0000
0e98936c
SP		 781/*
782* register set for both 1068 and 1078 controllers
783* structure extended for 1078 registers
784*/
f9876f0b 785
c4a3e0a5 786struct megasas_register_set {
f9876f0b 787 u32 reserved_0[4]; /*0000h*/
c4a3e0a5 788
f9876f0b
SP		 789 u32 inbound_msg_0; /*0010h*/
790 u32 inbound_msg_1; /*0014h*/
791 u32 outbound_msg_0; /*0018h*/
792 u32 outbound_msg_1; /*001Ch*/
c4a3e0a5 793
f9876f0b
SP		 794 u32 inbound_doorbell; /*0020h*/
795 u32 inbound_intr_status; /*0024h*/
796 u32 inbound_intr_mask; /*0028h*/
c4a3e0a5 797
f9876f0b
SP		 798 u32 outbound_doorbell; /*002Ch*/
799 u32 outbound_intr_status; /*0030h*/
800 u32 outbound_intr_mask; /*0034h*/
c4a3e0a5 801
f9876f0b 802 u32 reserved_1[2]; /*0038h*/
c4a3e0a5 803
f9876f0b
SP		 804 u32 inbound_queue_port; /*0040h*/
805 u32 outbound_queue_port; /*0044h*/
c4a3e0a5 806
f9876f0b 807 u32 reserved_2[22]; /*0048h*/
c4a3e0a5 808
f9876f0b 809 u32 outbound_doorbell_clear; /*00A0h*/
c4a3e0a5 810
f9876f0b
SP		 811 u32 reserved_3[3]; /*00A4h*/
812
813 u32 outbound_scratch_pad ; /*00B0h*/
814
815 u32 reserved_4[3]; /*00B4h*/
816
817 u32 inbound_low_queue_port ; /*00C0h*/
818
819 u32 inbound_high_queue_port ; /*00C4h*/
820
821 u32 reserved_5; /*00C8h*/
39a98554 822 u32 res_6[11]; /*CCh*/
823 u32 host_diag;
824 u32 seq_offset;
825 u32 index_registers[807]; /*00CCh*/
c4a3e0a5
BS		 826} __attribute__ ((packed));
827
828struct megasas_sge32 {
829
830 u32 phys_addr;
831 u32 length;
832
833} __attribute__ ((packed));
834
835struct megasas_sge64 {
836
837 u64 phys_addr;
838 u32 length;
839
840} __attribute__ ((packed));
841
f4c9a131
YB		 842struct megasas_sge_skinny {
843 u64 phys_addr;
844 u32 length;
845 u32 flag;
846} __packed;
847
c4a3e0a5
BS		 848union megasas_sgl {
849
850 struct megasas_sge32 sge32[1];
851 struct megasas_sge64 sge64[1];
f4c9a131 852 struct megasas_sge_skinny sge_skinny[1];
c4a3e0a5
BS		 853
854} __attribute__ ((packed));
855
856struct megasas_header {
857
858 u8 cmd; /*00h */
859 u8 sense_len; /*01h */
860 u8 cmd_status; /*02h */
861 u8 scsi_status; /*03h */
862
863 u8 target_id; /*04h */
864 u8 lun; /*05h */
865 u8 cdb_len; /*06h */
866 u8 sge_count; /*07h */
867
868 u32 context; /*08h */
869 u32 pad_0; /*0Ch */
870
871 u16 flags; /*10h */
872 u16 timeout; /*12h */
873 u32 data_xferlen; /*14h */
874
875} __attribute__ ((packed));
876
877union megasas_sgl_frame {
878
879 struct megasas_sge32 sge32[8];
880 struct megasas_sge64 sge64[5];
881
882} __attribute__ ((packed));
883
884struct megasas_init_frame {
885
886 u8 cmd; /*00h */
887 u8 reserved_0; /*01h */
888 u8 cmd_status; /*02h */
889
890 u8 reserved_1; /*03h */
891 u32 reserved_2; /*04h */
892
893 u32 context; /*08h */
894 u32 pad_0; /*0Ch */
895
896 u16 flags; /*10h */
897 u16 reserved_3; /*12h */
898 u32 data_xfer_len; /*14h */
899
900 u32 queue_info_new_phys_addr_lo; /*18h */
901 u32 queue_info_new_phys_addr_hi; /*1Ch */
902 u32 queue_info_old_phys_addr_lo; /*20h */
903 u32 queue_info_old_phys_addr_hi; /*24h */
904
905 u32 reserved_4[6]; /*28h */
906
907} __attribute__ ((packed));
908
909struct megasas_init_queue_info {
910
911 u32 init_flags; /*00h */
912 u32 reply_queue_entries; /*04h */
913
914 u32 reply_queue_start_phys_addr_lo; /*08h */
915 u32 reply_queue_start_phys_addr_hi; /*0Ch */
916 u32 producer_index_phys_addr_lo; /*10h */
917 u32 producer_index_phys_addr_hi; /*14h */
918 u32 consumer_index_phys_addr_lo; /*18h */
919 u32 consumer_index_phys_addr_hi; /*1Ch */
920
921} __attribute__ ((packed));
922
923struct megasas_io_frame {
924
925 u8 cmd; /*00h */
926 u8 sense_len; /*01h */
927 u8 cmd_status; /*02h */
928 u8 scsi_status; /*03h */
929
930 u8 target_id; /*04h */
931 u8 access_byte; /*05h */
932 u8 reserved_0; /*06h */
933 u8 sge_count; /*07h */
934
935 u32 context; /*08h */
936 u32 pad_0; /*0Ch */
937
938 u16 flags; /*10h */
939 u16 timeout; /*12h */
940 u32 lba_count; /*14h */
941
942 u32 sense_buf_phys_addr_lo; /*18h */
943 u32 sense_buf_phys_addr_hi; /*1Ch */
944
945 u32 start_lba_lo; /*20h */
946 u32 start_lba_hi; /*24h */
947
948 union megasas_sgl sgl; /*28h */
949
950} __attribute__ ((packed));
951
952struct megasas_pthru_frame {
953
954 u8 cmd; /*00h */
955 u8 sense_len; /*01h */
956 u8 cmd_status; /*02h */
957 u8 scsi_status; /*03h */
958
959 u8 target_id; /*04h */
960 u8 lun; /*05h */
961 u8 cdb_len; /*06h */
962 u8 sge_count; /*07h */
963
964 u32 context; /*08h */
965 u32 pad_0; /*0Ch */
966
967 u16 flags; /*10h */
968 u16 timeout; /*12h */
969 u32 data_xfer_len; /*14h */
970
971 u32 sense_buf_phys_addr_lo; /*18h */
972 u32 sense_buf_phys_addr_hi; /*1Ch */
973
974 u8 cdb[16]; /*20h */
975 union megasas_sgl sgl; /*30h */
976
977} __attribute__ ((packed));
978
979struct megasas_dcmd_frame {
980
981 u8 cmd; /*00h */
982 u8 reserved_0; /*01h */
983 u8 cmd_status; /*02h */
984 u8 reserved_1[4]; /*03h */
985 u8 sge_count; /*07h */
986
987 u32 context; /*08h */
988 u32 pad_0; /*0Ch */
989
990 u16 flags; /*10h */
991 u16 timeout; /*12h */
992
993 u32 data_xfer_len; /*14h */
994 u32 opcode; /*18h */
995
996 union { /*1Ch */
997 u8 b[12];
998 u16 s[6];
999 u32 w[3];
1000 } mbox;
1001
1002 union megasas_sgl sgl; /*28h */
1003
1004} __attribute__ ((packed));
1005
1006struct megasas_abort_frame {
1007
1008 u8 cmd; /*00h */
1009 u8 reserved_0; /*01h */
1010 u8 cmd_status; /*02h */
1011
1012 u8 reserved_1; /*03h */
1013 u32 reserved_2; /*04h */
1014
1015 u32 context; /*08h */
1016 u32 pad_0; /*0Ch */
1017
1018 u16 flags; /*10h */
1019 u16 reserved_3; /*12h */
1020 u32 reserved_4; /*14h */
1021
1022 u32 abort_context; /*18h */
1023 u32 pad_1; /*1Ch */
1024
1025 u32 abort_mfi_phys_addr_lo; /*20h */
1026 u32 abort_mfi_phys_addr_hi; /*24h */
1027
1028 u32 reserved_5[6]; /*28h */
1029
1030} __attribute__ ((packed));
1031
1032struct megasas_smp_frame {
1033
1034 u8 cmd; /*00h */
1035 u8 reserved_1; /*01h */
1036 u8 cmd_status; /*02h */
1037 u8 connection_status; /*03h */
1038
1039 u8 reserved_2[3]; /*04h */
1040 u8 sge_count; /*07h */
1041
1042 u32 context; /*08h */
1043 u32 pad_0; /*0Ch */
1044
1045 u16 flags; /*10h */
1046 u16 timeout; /*12h */
1047
1048 u32 data_xfer_len; /*14h */
1049 u64 sas_addr; /*18h */
1050
1051 union {
1052 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1053 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1054 } sgl;
1055
1056} __attribute__ ((packed));
1057
1058struct megasas_stp_frame {
1059
1060 u8 cmd; /*00h */
1061 u8 reserved_1; /*01h */
1062 u8 cmd_status; /*02h */
1063 u8 reserved_2; /*03h */
1064
1065 u8 target_id; /*04h */
1066 u8 reserved_3[2]; /*05h */
1067 u8 sge_count; /*07h */
1068
1069 u32 context; /*08h */
1070 u32 pad_0; /*0Ch */
1071
1072 u16 flags; /*10h */
1073 u16 timeout; /*12h */
1074
1075 u32 data_xfer_len; /*14h */
1076
1077 u16 fis[10]; /*18h */
1078 u32 stp_flags;
1079
1080 union {
1081 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1082 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1083 } sgl;
1084
1085} __attribute__ ((packed));
1086
1087union megasas_frame {
1088
1089 struct megasas_header hdr;
1090 struct megasas_init_frame init;
1091 struct megasas_io_frame io;
1092 struct megasas_pthru_frame pthru;
1093 struct megasas_dcmd_frame dcmd;
1094 struct megasas_abort_frame abort;
1095 struct megasas_smp_frame smp;
1096 struct megasas_stp_frame stp;
1097
1098 u8 raw_bytes[64];
1099};
1100
1101struct megasas_cmd;
1102
1103union megasas_evt_class_locale {
1104
1105 struct {
1106 u16 locale;
1107 u8 reserved;
1108 s8 class;
1109 } __attribute__ ((packed)) members;
1110
1111 u32 word;
1112
1113} __attribute__ ((packed));
1114
1115struct megasas_evt_log_info {
1116 u32 newest_seq_num;
1117 u32 oldest_seq_num;
1118 u32 clear_seq_num;
1119 u32 shutdown_seq_num;
1120 u32 boot_seq_num;
1121
1122} __attribute__ ((packed));
1123
1124struct megasas_progress {
1125
1126 u16 progress;
1127 u16 elapsed_seconds;
1128
1129} __attribute__ ((packed));
1130
1131struct megasas_evtarg_ld {
1132
1133 u16 target_id;
1134 u8 ld_index;
1135 u8 reserved;
1136
1137} __attribute__ ((packed));
1138
1139struct megasas_evtarg_pd {
1140 u16 device_id;
1141 u8 encl_index;
1142 u8 slot_number;
1143
1144} __attribute__ ((packed));
1145
1146struct megasas_evt_detail {
1147
1148 u32 seq_num;
1149 u32 time_stamp;
1150 u32 code;
1151 union megasas_evt_class_locale cl;
1152 u8 arg_type;
1153 u8 reserved1[15];
1154
1155 union {
1156 struct {
1157 struct megasas_evtarg_pd pd;
1158 u8 cdb_length;
1159 u8 sense_length;
1160 u8 reserved[2];
1161 u8 cdb[16];
1162 u8 sense[64];
1163 } __attribute__ ((packed)) cdbSense;
1164
1165 struct megasas_evtarg_ld ld;
1166
1167 struct {
1168 struct megasas_evtarg_ld ld;
1169 u64 count;
1170 } __attribute__ ((packed)) ld_count;
1171
1172 struct {
1173 u64 lba;
1174 struct megasas_evtarg_ld ld;
1175 } __attribute__ ((packed)) ld_lba;
1176
1177 struct {
1178 struct megasas_evtarg_ld ld;
1179 u32 prevOwner;
1180 u32 newOwner;
1181 } __attribute__ ((packed)) ld_owner;
1182
1183 struct {
1184 u64 ld_lba;
1185 u64 pd_lba;
1186 struct megasas_evtarg_ld ld;
1187 struct megasas_evtarg_pd pd;
1188 } __attribute__ ((packed)) ld_lba_pd_lba;
1189
1190 struct {
1191 struct megasas_evtarg_ld ld;
1192 struct megasas_progress prog;
1193 } __attribute__ ((packed)) ld_prog;
1194
1195 struct {
1196 struct megasas_evtarg_ld ld;
1197 u32 prev_state;
1198 u32 new_state;
1199 } __attribute__ ((packed)) ld_state;
1200
1201 struct {
1202 u64 strip;
1203 struct megasas_evtarg_ld ld;
1204 } __attribute__ ((packed)) ld_strip;
1205
1206 struct megasas_evtarg_pd pd;
1207
1208 struct {
1209 struct megasas_evtarg_pd pd;
1210 u32 err;
1211 } __attribute__ ((packed)) pd_err;
1212
1213 struct {
1214 u64 lba;
1215 struct megasas_evtarg_pd pd;
1216 } __attribute__ ((packed)) pd_lba;
1217
1218 struct {
1219 u64 lba;
1220 struct megasas_evtarg_pd pd;
1221 struct megasas_evtarg_ld ld;
1222 } __attribute__ ((packed)) pd_lba_ld;
1223
1224 struct {
1225 struct megasas_evtarg_pd pd;
1226 struct megasas_progress prog;
1227 } __attribute__ ((packed)) pd_prog;
1228
1229 struct {
1230 struct megasas_evtarg_pd pd;
1231 u32 prevState;
1232 u32 newState;
1233 } __attribute__ ((packed)) pd_state;
1234
1235 struct {
1236 u16 vendorId;
1237 u16 deviceId;
1238 u16 subVendorId;
1239 u16 subDeviceId;
1240 } __attribute__ ((packed)) pci;
1241
1242 u32 rate;
1243 char str[96];
1244
1245 struct {
1246 u32 rtc;
1247 u32 elapsedSeconds;
1248 } __attribute__ ((packed)) time;
1249
1250 struct {
1251 u32 ecar;
1252 u32 elog;
1253 char str[64];
1254 } __attribute__ ((packed)) ecc;
1255
1256 u8 b[96];
1257 u16 s[48];
1258 u32 w[24];
1259 u64 d[12];
1260 } args;
1261
1262 char description[128];
1263
1264} __attribute__ ((packed));
1265
7e8a75f4
YB		 1266struct megasas_aen_event {
1267 struct work_struct hotplug_work;
1268 struct megasas_instance *instance;
1269};
1270
c4a3e0a5
BS		 1271struct megasas_instance {
1272
1273 u32 *producer;
1274 dma_addr_t producer_h;
1275 u32 *consumer;
1276 dma_addr_t consumer_h;
1277
1278 u32 *reply_queue;
1279 dma_addr_t reply_queue_h;
1280
1281 unsigned long base_addr;
1282 struct megasas_register_set __iomem *reg_set;
1283
81e403ce 1284 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
bdc6fb8d 1285 u8 ld_ids[MEGASAS_MAX_LD_IDS];
c4a3e0a5 1286 s8 init_id;
c4a3e0a5
BS		 1287
1288 u16 max_num_sge;
1289 u16 max_fw_cmds;
1290 u32 max_sectors_per_req;
7e8a75f4 1291 struct megasas_aen_event *ev;
c4a3e0a5
BS		 1292
1293 struct megasas_cmd **cmd_list;
1294 struct list_head cmd_pool;
39a98554 1295 /* used to sync fire the cmd to fw */
c4a3e0a5 1296 spinlock_t cmd_pool_lock;
39a98554 1297 /* used to sync fire the cmd to fw */
1298 spinlock_t hba_lock;
7343eb65 1299 /* used to synch producer, consumer ptrs in dpc */
1300 spinlock_t completion_lock;
c4a3e0a5
BS		 1301 struct dma_pool *frame_dma_pool;
1302 struct dma_pool *sense_dma_pool;
1303
1304 struct megasas_evt_detail *evt_detail;
1305 dma_addr_t evt_detail_h;
1306 struct megasas_cmd *aen_cmd;
e5a69e27 1307 struct mutex aen_mutex;
c4a3e0a5
BS		 1308 struct semaphore ioctl_sem;
1309
1310 struct Scsi_Host *host;
1311
1312 wait_queue_head_t int_cmd_wait_q;
1313 wait_queue_head_t abort_cmd_wait_q;
1314
1315 struct pci_dev *pdev;
1316 u32 unique_id;
39a98554 1317 u32 fw_support_ieee;
c4a3e0a5 1318
e4a082c7 1319 atomic_t fw_outstanding;
39a98554 1320 atomic_t fw_reset_no_pci_access;
1341c939
SP		 1321
1322 struct megasas_instance_template *instancet;
5d018ad0 1323 struct tasklet_struct isr_tasklet;
39a98554 1324 struct work_struct work_init;
05e9ebbe
SP		 1325
1326 u8 flag;
c3518837 1327 u8 unload;
f4c9a131 1328 u8 flag_ieee;
39a98554 1329 u8 issuepend_done;
1330 u8 disableOnlineCtrlReset;
1331 u8 adprecovery;
05e9ebbe 1332 unsigned long last_time;
39a98554 1333 u32 mfiStatus;
1334 u32 last_seq_num;
ad84db2e 1335
1336 struct timer_list io_completion_timer;
39a98554 1337 struct list_head internal_reset_pending_q;
80d9da98
AR		 1338
1339 u8 msi_flag;
1340 struct msix_entry msixentry;
b6d5d880 1341 unsigned long bar;
39a98554 1342};
1343
1344enum {
1345 MEGASAS_HBA_OPERATIONAL = 0,
1346 MEGASAS_ADPRESET_SM_INFAULT = 1,
1347 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1348 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
1349 MEGASAS_HW_CRITICAL_ERROR = 4,
1350 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
c4a3e0a5
BS		 1351};
1352
0c79e681
YB		 1353struct megasas_instance_template {
1354 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1355 u32, struct megasas_register_set __iomem *);
1356
1357 void (*enable_intr)(struct megasas_register_set __iomem *) ;
1358 void (*disable_intr)(struct megasas_register_set __iomem *);
1359
1360 int (*clear_intr)(struct megasas_register_set __iomem *);
1361
1362 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
39a98554 1363 int (*adp_reset)(struct megasas_instance *, \
1364 struct megasas_register_set __iomem *);
1365 int (*check_reset)(struct megasas_instance *, \
1366 struct megasas_register_set __iomem *);
cd50ba8e
AR		 1367 irqreturn_t (*service_isr)(int irq, void *devp);
1368 void (*tasklet)(unsigned long);
1369 u32 (*init_adapter)(struct megasas_instance *);
1370 u32 (*build_and_issue_cmd) (struct megasas_instance *,
1371 struct scsi_cmnd *);
1372 void (*issue_dcmd) (struct megasas_instance *instance,
1373 struct megasas_cmd *cmd);
0c79e681
YB		 1374};
1375
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BS		 1376#define MEGASAS_IS_LOGICAL(scp) \
1377 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1378
1379#define MEGASAS_DEV_INDEX(inst, scp) \
1380 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1381 scp->device->id
1382
1383struct megasas_cmd {
1384
1385 union megasas_frame *frame;
1386 dma_addr_t frame_phys_addr;
1387 u8 *sense;
1388 dma_addr_t sense_phys_addr;
1389
1390 u32 index;
1391 u8 sync_cmd;
1392 u8 cmd_status;
39a98554 1393 u8 abort_aen;
1394 u8 retry_for_fw_reset;
1395
c4a3e0a5
BS		 1396
1397 struct list_head list;
1398 struct scsi_cmnd *scmd;
1399 struct megasas_instance *instance;
1400 u32 frame_count;
1401};
1402
1403#define MAX_MGMT_ADAPTERS 1024
1404#define MAX_IOCTL_SGE 16
1405
1406struct megasas_iocpacket {
1407
1408 u16 host_no;
1409 u16 __pad1;
1410 u32 sgl_off;
1411 u32 sge_count;
1412 u32 sense_off;
1413 u32 sense_len;
1414 union {
1415 u8 raw[128];
1416 struct megasas_header hdr;
1417 } frame;
1418
1419 struct iovec sgl[MAX_IOCTL_SGE];
1420
1421} __attribute__ ((packed));
1422
1423struct megasas_aen {
1424 u16 host_no;
1425 u16 __pad1;
1426 u32 seq_num;
1427 u32 class_locale_word;
1428} __attribute__ ((packed));
1429
1430#ifdef CONFIG_COMPAT
1431struct compat_megasas_iocpacket {
1432 u16 host_no;
1433 u16 __pad1;
1434 u32 sgl_off;
1435 u32 sge_count;
1436 u32 sense_off;
1437 u32 sense_len;
1438 union {
1439 u8 raw[128];
1440 struct megasas_header hdr;
1441 } frame;
1442 struct compat_iovec sgl[MAX_IOCTL_SGE];
1443} __attribute__ ((packed));
1444
0e98936c 1445#define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
c4a3e0a5
BS		 1446#endif
1447
cb59aa6a 1448#define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
c4a3e0a5
BS		 1449#define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1450
1451struct megasas_mgmt_info {
1452
1453 u16 count;
1454 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1455 int max_index;
1456};
1457
1458#endif /*LSI_MEGARAID_SAS_H */
kernel source for telekom puls (alcatel/mediatek)