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Merge tag 'v3.10.108' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / phy / marvell.c
CommitLineData
00db8189
AF		 1/*
2 * drivers/net/phy/marvell.c
3 *
4 * Driver for Marvell PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
3871c387
MS		 10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
11 *
00db8189
AF		 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
00db8189 18#include <linux/kernel.h>
00db8189
AF		 19#include <linux/string.h>
20#include <linux/errno.h>
21#include <linux/unistd.h>
00db8189
AF		 22#include <linux/interrupt.h>
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/spinlock.h>
29#include <linux/mm.h>
30#include <linux/module.h>
00db8189
AF		 31#include <linux/mii.h>
32#include <linux/ethtool.h>
33#include <linux/phy.h>
2f495c39 34#include <linux/marvell_phy.h>
cf41a51d 35#include <linux/of.h>
00db8189
AF		 36
37#include <asm/io.h>
38#include <asm/irq.h>
39#include <asm/uaccess.h>
40
27d916d6
DD		 41#define MII_MARVELL_PHY_PAGE 22
42
00db8189
AF		 43#define MII_M1011_IEVENT 0x13
44#define MII_M1011_IEVENT_CLEAR 0x0000
45
46#define MII_M1011_IMASK 0x12
47#define MII_M1011_IMASK_INIT 0x6400
48#define MII_M1011_IMASK_CLEAR 0x0000
49
76884679
AF		 50#define MII_M1011_PHY_SCR 0x10
51#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
52
53#define MII_M1145_PHY_EXT_CR 0x14
54#define MII_M1145_RGMII_RX_DELAY 0x0080
55#define MII_M1145_RGMII_TX_DELAY 0x0002
56
76884679
AF		 57#define MII_M1111_PHY_LED_CONTROL 0x18
58#define MII_M1111_PHY_LED_DIRECT 0x4100
59#define MII_M1111_PHY_LED_COMBINE 0x411c
895ee682
KP		 60#define MII_M1111_PHY_EXT_CR 0x14
61#define MII_M1111_RX_DELAY 0x80
62#define MII_M1111_TX_DELAY 0x2
63#define MII_M1111_PHY_EXT_SR 0x1b
be937f1f
AS		 64
65#define MII_M1111_HWCFG_MODE_MASK 0xf
66#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
67#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
4117b5be 68#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
5f8cbc13 69#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
be937f1f
AS		 70#define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
71#define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
72
73#define MII_M1111_COPPER 0
74#define MII_M1111_FIBER 1
75
c477d044
CC		 76#define MII_88E1121_PHY_MSCR_PAGE 2
77#define MII_88E1121_PHY_MSCR_REG 21
78#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
79#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
80#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
81
337ac9d5
CC		 82#define MII_88E1318S_PHY_MSCR1_REG 16
83#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
3ff1c259 84
3871c387
MS		 85/* Copper Specific Interrupt Enable Register */
86#define MII_88E1318S_PHY_CSIER 0x12
87/* WOL Event Interrupt Enable */
88#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
89
90/* LED Timer Control Register */
91#define MII_88E1318S_PHY_LED_PAGE 0x03
92#define MII_88E1318S_PHY_LED_TCR 0x12
93#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
94#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
95#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
96
97/* Magic Packet MAC address registers */
98#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
99#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
100#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
101
102#define MII_88E1318S_PHY_WOL_PAGE 0x11
103#define MII_88E1318S_PHY_WOL_CTRL 0x10
104#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
105#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
106
140bc929
SP		 107#define MII_88E1121_PHY_LED_CTRL 16
108#define MII_88E1121_PHY_LED_PAGE 3
109#define MII_88E1121_PHY_LED_DEF 0x0030
140bc929 110
be937f1f
AS		 111#define MII_M1011_PHY_STATUS 0x11
112#define MII_M1011_PHY_STATUS_1000 0x8000
113#define MII_M1011_PHY_STATUS_100 0x4000
114#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
115#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
116#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
117#define MII_M1011_PHY_STATUS_LINK 0x0400
118
76884679 119
00db8189
AF		 120MODULE_DESCRIPTION("Marvell PHY driver");
121MODULE_AUTHOR("Andy Fleming");
122MODULE_LICENSE("GPL");
123
124static int marvell_ack_interrupt(struct phy_device *phydev)
125{
126 int err;
127
128 /* Clear the interrupts by reading the reg */
129 err = phy_read(phydev, MII_M1011_IEVENT);
130
131 if (err < 0)
132 return err;
133
134 return 0;
135}
136
137static int marvell_config_intr(struct phy_device *phydev)
138{
139 int err;
140
76884679 141 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
00db8189
AF		 142 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
143 else
144 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
145
146 return err;
147}
148
149static int marvell_config_aneg(struct phy_device *phydev)
150{
151 int err;
152
153 /* The Marvell PHY has an errata which requires
154 * that certain registers get written in order
155 * to restart autonegotiation */
156 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
157
158 if (err < 0)
159 return err;
160
161 err = phy_write(phydev, 0x1d, 0x1f);
162 if (err < 0)
163 return err;
164
165 err = phy_write(phydev, 0x1e, 0x200c);
166 if (err < 0)
167 return err;
168
169 err = phy_write(phydev, 0x1d, 0x5);
170 if (err < 0)
171 return err;
172
173 err = phy_write(phydev, 0x1e, 0);
174 if (err < 0)
175 return err;
176
177 err = phy_write(phydev, 0x1e, 0x100);
178 if (err < 0)
179 return err;
180
76884679
AF		 181 err = phy_write(phydev, MII_M1011_PHY_SCR,
182 MII_M1011_PHY_SCR_AUTO_CROSS);
183 if (err < 0)
184 return err;
185
186 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
187 MII_M1111_PHY_LED_DIRECT);
188 if (err < 0)
189 return err;
00db8189
AF		 190
191 err = genphy_config_aneg(phydev);
8ff44985
AV		 192 if (err < 0)
193 return err;
00db8189 194
8ff44985
AV		 195 if (phydev->autoneg != AUTONEG_ENABLE) {
196 int bmcr;
197
198 /*
199 * A write to speed/duplex bits (that is performed by
200 * genphy_config_aneg() call above) must be followed by
201 * a software reset. Otherwise, the write has no effect.
202 */
203 bmcr = phy_read(phydev, MII_BMCR);
204 if (bmcr < 0)
205 return bmcr;
206
207 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
208 if (err < 0)
209 return err;
210 }
211
212 return 0;
00db8189
AF		 213}
214
cf41a51d
DD		 215#ifdef CONFIG_OF_MDIO
216/*
217 * Set and/or override some configuration registers based on the
218 * marvell,reg-init property stored in the of_node for the phydev.
219 *
220 * marvell,reg-init = <reg-page reg mask value>,...;
221 *
222 * There may be one or more sets of <reg-page reg mask value>:
223 *
224 * reg-page: which register bank to use.
225 * reg: the register.
226 * mask: if non-zero, ANDed with existing register value.
227 * value: ORed with the masked value and written to the regiser.
228 *
229 */
230static int marvell_of_reg_init(struct phy_device *phydev)
231{
232 const __be32 *paddr;
233 int len, i, saved_page, current_page, page_changed, ret;
234
235 if (!phydev->dev.of_node)
236 return 0;
237
238 paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len);
239 if (!paddr || len < (4 * sizeof(*paddr)))
240 return 0;
241
242 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
243 if (saved_page < 0)
244 return saved_page;
245 page_changed = 0;
246 current_page = saved_page;
247
248 ret = 0;
249 len /= sizeof(*paddr);
250 for (i = 0; i < len - 3; i += 4) {
251 u16 reg_page = be32_to_cpup(paddr + i);
252 u16 reg = be32_to_cpup(paddr + i + 1);
253 u16 mask = be32_to_cpup(paddr + i + 2);
254 u16 val_bits = be32_to_cpup(paddr + i + 3);
255 int val;
256
257 if (reg_page != current_page) {
258 current_page = reg_page;
259 page_changed = 1;
260 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
261 if (ret < 0)
262 goto err;
263 }
264
265 val = 0;
266 if (mask) {
267 val = phy_read(phydev, reg);
268 if (val < 0) {
269 ret = val;
270 goto err;
271 }
272 val &= mask;
273 }
274 val |= val_bits;
275
276 ret = phy_write(phydev, reg, val);
277 if (ret < 0)
278 goto err;
279
280 }
281err:
282 if (page_changed) {
283 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
284 if (ret == 0)
285 ret = i;
286 }
287 return ret;
288}
289#else
290static int marvell_of_reg_init(struct phy_device *phydev)
291{
292 return 0;
293}
294#endif /* CONFIG_OF_MDIO */
295
140bc929
SP		 296static int m88e1121_config_aneg(struct phy_device *phydev)
297{
c477d044
CC		 298 int err, oldpage, mscr;
299
27d916d6 300 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
c477d044 301
27d916d6 302 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
c477d044
CC		 303 MII_88E1121_PHY_MSCR_PAGE);
304 if (err < 0)
305 return err;
be8c6480
AP		 306
307 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
308 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
309 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
310 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
311
312 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
313 MII_88E1121_PHY_MSCR_DELAY_MASK;
314
315 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
316 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
317 MII_88E1121_PHY_MSCR_TX_DELAY);
318 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
319 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
320 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
321 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
322
323 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
324 if (err < 0)
325 return err;
326 }
c477d044 327
27d916d6 328 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
140bc929
SP		 329
330 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
331 if (err < 0)
332 return err;
333
334 err = phy_write(phydev, MII_M1011_PHY_SCR,
335 MII_M1011_PHY_SCR_AUTO_CROSS);
336 if (err < 0)
337 return err;
338
27d916d6 339 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
140bc929 340
27d916d6 341 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
140bc929 342 phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
27d916d6 343 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
140bc929
SP		 344
345 err = genphy_config_aneg(phydev);
346
347 return err;
348}
349
337ac9d5 350static int m88e1318_config_aneg(struct phy_device *phydev)
3ff1c259
CC		 351{
352 int err, oldpage, mscr;
353
27d916d6 354 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
3ff1c259 355
27d916d6 356 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
3ff1c259
CC		 357 MII_88E1121_PHY_MSCR_PAGE);
358 if (err < 0)
359 return err;
360
337ac9d5
CC		 361 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
362 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
3ff1c259 363
337ac9d5 364 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
3ff1c259
CC		 365 if (err < 0)
366 return err;
367
27d916d6 368 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
3ff1c259
CC		 369 if (err < 0)
370 return err;
371
372 return m88e1121_config_aneg(phydev);
373}
374
895ee682
KP		 375static int m88e1111_config_init(struct phy_device *phydev)
376{
377 int err;
be937f1f 378 int temp;
be937f1f 379
895ee682 380 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
9daf5a76
KP		 381 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
382 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
383 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
895ee682 384
9daf5a76
KP		 385 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
386 if (temp < 0)
387 return temp;
895ee682 388
9daf5a76 389 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
895ee682 390 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
9daf5a76
KP		 391 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
392 temp &= ~MII_M1111_TX_DELAY;
393 temp |= MII_M1111_RX_DELAY;
394 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
395 temp &= ~MII_M1111_RX_DELAY;
396 temp |= MII_M1111_TX_DELAY;
895ee682
KP		 397 }
398
9daf5a76
KP		 399 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
400 if (err < 0)
401 return err;
402
895ee682
KP		 403 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
404 if (temp < 0)
405 return temp;
406
407 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
be937f1f 408
7239016d 409 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
be937f1f
AS		 410 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
411 else
412 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
895ee682
KP		 413
414 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
415 if (err < 0)
416 return err;
417 }
418
4117b5be 419 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
4117b5be
KJ		 420 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
421 if (temp < 0)
422 return temp;
423
424 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
425 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
32d0c1e1 426 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
4117b5be
KJ		 427
428 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
429 if (err < 0)
430 return err;
431 }
432
5f8cbc13
LYB		 433 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
434 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
435 if (temp < 0)
436 return temp;
437 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
438 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
439 if (err < 0)
440 return err;
441
442 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
443 if (temp < 0)
444 return temp;
445 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
446 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
447 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
448 if (err < 0)
449 return err;
450
451 /* soft reset */
452 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
453 if (err < 0)
454 return err;
455 do
456 temp = phy_read(phydev, MII_BMCR);
457 while (temp & BMCR_RESET);
458
459 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
460 if (temp < 0)
461 return temp;
462 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
463 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
464 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
465 if (err < 0)
466 return err;
467 }
468
cf41a51d
DD		 469 err = marvell_of_reg_init(phydev);
470 if (err < 0)
471 return err;
5f8cbc13 472
cc90cb3b 473 return phy_write(phydev, MII_BMCR, BMCR_RESET);
895ee682
KP		 474}
475
605f196e
RM		 476static int m88e1118_config_aneg(struct phy_device *phydev)
477{
478 int err;
479
480 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
481 if (err < 0)
482 return err;
483
484 err = phy_write(phydev, MII_M1011_PHY_SCR,
485 MII_M1011_PHY_SCR_AUTO_CROSS);
486 if (err < 0)
487 return err;
488
489 err = genphy_config_aneg(phydev);
490 return 0;
491}
492
493static int m88e1118_config_init(struct phy_device *phydev)
494{
495 int err;
496
497 /* Change address */
27d916d6 498 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
605f196e
RM		 499 if (err < 0)
500 return err;
501
502 /* Enable 1000 Mbit */
503 err = phy_write(phydev, 0x15, 0x1070);
504 if (err < 0)
505 return err;
506
507 /* Change address */
27d916d6 508 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
605f196e
RM		 509 if (err < 0)
510 return err;
511
512 /* Adjust LED Control */
2f495c39
BH		 513 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
514 err = phy_write(phydev, 0x10, 0x1100);
515 else
516 err = phy_write(phydev, 0x10, 0x021e);
605f196e
RM		 517 if (err < 0)
518 return err;
519
cf41a51d
DD		 520 err = marvell_of_reg_init(phydev);
521 if (err < 0)
522 return err;
523
605f196e 524 /* Reset address */
27d916d6 525 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
605f196e
RM		 526 if (err < 0)
527 return err;
528
cc90cb3b 529 return phy_write(phydev, MII_BMCR, BMCR_RESET);
605f196e
RM		 530}
531
90600732
DD		 532static int m88e1149_config_init(struct phy_device *phydev)
533{
534 int err;
535
536 /* Change address */
537 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
538 if (err < 0)
539 return err;
540
541 /* Enable 1000 Mbit */
542 err = phy_write(phydev, 0x15, 0x1048);
543 if (err < 0)
544 return err;
545
cf41a51d
DD		 546 err = marvell_of_reg_init(phydev);
547 if (err < 0)
548 return err;
549
90600732
DD		 550 /* Reset address */
551 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
552 if (err < 0)
553 return err;
554
cc90cb3b 555 return phy_write(phydev, MII_BMCR, BMCR_RESET);
90600732
DD		 556}
557
76884679
AF		 558static int m88e1145_config_init(struct phy_device *phydev)
559{
560 int err;
561
562 /* Take care of errata E0 & E1 */
563 err = phy_write(phydev, 0x1d, 0x001b);
564 if (err < 0)
565 return err;
566
567 err = phy_write(phydev, 0x1e, 0x418f);
568 if (err < 0)
569 return err;
570
571 err = phy_write(phydev, 0x1d, 0x0016);
572 if (err < 0)
573 return err;
574
575 err = phy_write(phydev, 0x1e, 0xa2da);
576 if (err < 0)
577 return err;
578
895ee682 579 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
76884679
AF		 580 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
581 if (temp < 0)
582 return temp;
583
584 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
585
586 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
587 if (err < 0)
588 return err;
589
2f495c39 590 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
76884679
AF		 591 err = phy_write(phydev, 0x1d, 0x0012);
592 if (err < 0)
593 return err;
594
595 temp = phy_read(phydev, 0x1e);
596 if (temp < 0)
597 return temp;
598
599 temp &= 0xf03f;
600 temp |= 2 << 9; /* 36 ohm */
601 temp |= 2 << 6; /* 39 ohm */
602
603 err = phy_write(phydev, 0x1e, temp);
604 if (err < 0)
605 return err;
606
607 err = phy_write(phydev, 0x1d, 0x3);
608 if (err < 0)
609 return err;
610
611 err = phy_write(phydev, 0x1e, 0x8000);
612 if (err < 0)
613 return err;
614 }
615 }
616
cf41a51d
DD		 617 err = marvell_of_reg_init(phydev);
618 if (err < 0)
619 return err;
620
76884679
AF		 621 return 0;
622}
00db8189 623
be937f1f
AS		 624/* marvell_read_status
625 *
626 * Generic status code does not detect Fiber correctly!
f0c88f9c 627 * Description:
be937f1f
AS		 628 * Check the link, then figure out the current state
629 * by comparing what we advertise with what the link partner
630 * advertises. Start by checking the gigabit possibilities,
631 * then move on to 10/100.
632 */
633static int marvell_read_status(struct phy_device *phydev)
634{
635 int adv;
636 int err;
637 int lpa;
638 int status = 0;
639
640 /* Update the link, but return if there
641 * was an error */
642 err = genphy_update_link(phydev);
643 if (err)
644 return err;
645
646 if (AUTONEG_ENABLE == phydev->autoneg) {
647 status = phy_read(phydev, MII_M1011_PHY_STATUS);
648 if (status < 0)
649 return status;
650
651 lpa = phy_read(phydev, MII_LPA);
652 if (lpa < 0)
653 return lpa;
654
655 adv = phy_read(phydev, MII_ADVERTISE);
656 if (adv < 0)
657 return adv;
658
be937f1f
AS		 659 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
660 phydev->duplex = DUPLEX_FULL;
661 else
662 phydev->duplex = DUPLEX_HALF;
663
664 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
665 phydev->pause = phydev->asym_pause = 0;
666
667 switch (status) {
668 case MII_M1011_PHY_STATUS_1000:
669 phydev->speed = SPEED_1000;
670 break;
671
672 case MII_M1011_PHY_STATUS_100:
673 phydev->speed = SPEED_100;
674 break;
675
676 default:
677 phydev->speed = SPEED_10;
678 break;
679 }
680
681 if (phydev->duplex == DUPLEX_FULL) {
682 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
683 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
684 }
685 } else {
686 int bmcr = phy_read(phydev, MII_BMCR);
687
688 if (bmcr < 0)
689 return bmcr;
690
691 if (bmcr & BMCR_FULLDPLX)
692 phydev->duplex = DUPLEX_FULL;
693 else
694 phydev->duplex = DUPLEX_HALF;
695
696 if (bmcr & BMCR_SPEED1000)
697 phydev->speed = SPEED_1000;
698 else if (bmcr & BMCR_SPEED100)
699 phydev->speed = SPEED_100;
700 else
701 phydev->speed = SPEED_10;
702
703 phydev->pause = phydev->asym_pause = 0;
704 }
705
706 return 0;
707}
708
dcd07be3
AG		 709static int m88e1121_did_interrupt(struct phy_device *phydev)
710{
711 int imask;
712
713 imask = phy_read(phydev, MII_M1011_IEVENT);
714
715 if (imask & MII_M1011_IMASK_INIT)
716 return 1;
717
718 return 0;
719}
720
3871c387
MS		 721static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
722{
723 wol->supported = WAKE_MAGIC;
724 wol->wolopts = 0;
725
726 if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
727 MII_88E1318S_PHY_WOL_PAGE) < 0)
728 return;
729
730 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
731 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
732 wol->wolopts |= WAKE_MAGIC;
733
734 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
735 return;
736}
737
738static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
739{
740 int err, oldpage, temp;
741
742 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
743
744 if (wol->wolopts & WAKE_MAGIC) {
745 /* Explicitly switch to page 0x00, just to be sure */
746 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
747 if (err < 0)
748 return err;
749
750 /* Enable the WOL interrupt */
751 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
752 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
753 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
754 if (err < 0)
755 return err;
756
757 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
758 MII_88E1318S_PHY_LED_PAGE);
759 if (err < 0)
760 return err;
761
762 /* Setup LED[2] as interrupt pin (active low) */
763 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
764 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
765 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
766 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
767 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
768 if (err < 0)
769 return err;
770
771 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
772 MII_88E1318S_PHY_WOL_PAGE);
773 if (err < 0)
774 return err;
775
776 /* Store the device address for the magic packet */
777 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
778 ((phydev->attached_dev->dev_addr[5] << 8) |
779 phydev->attached_dev->dev_addr[4]));
780 if (err < 0)
781 return err;
782 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
783 ((phydev->attached_dev->dev_addr[3] << 8) |
784 phydev->attached_dev->dev_addr[2]));
785 if (err < 0)
786 return err;
787 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
788 ((phydev->attached_dev->dev_addr[1] << 8) |
789 phydev->attached_dev->dev_addr[0]));
790 if (err < 0)
791 return err;
792
793 /* Clear WOL status and enable magic packet matching */
794 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
795 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
796 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
797 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
798 if (err < 0)
799 return err;
800 } else {
801 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
802 MII_88E1318S_PHY_WOL_PAGE);
803 if (err < 0)
804 return err;
805
806 /* Clear WOL status and disable magic packet matching */
807 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
808 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
809 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
810 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
811 if (err < 0)
812 return err;
813 }
814
815 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
816 if (err < 0)
817 return err;
818
819 return 0;
820}
821
e5479239
OJ		 822static struct phy_driver marvell_drivers[] = {
823 {
2f495c39
BH		 824 .phy_id = MARVELL_PHY_ID_88E1101,
825 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 826 .name = "Marvell 88E1101",
827 .features = PHY_GBIT_FEATURES,
828 .flags = PHY_HAS_INTERRUPT,
829 .config_aneg = &marvell_config_aneg,
830 .read_status = &genphy_read_status,
831 .ack_interrupt = &marvell_ack_interrupt,
832 .config_intr = &marvell_config_intr,
ac8c635a 833 .driver = { .owner = THIS_MODULE },
e5479239 834 },
85cfb534 835 {
2f495c39
BH		 836 .phy_id = MARVELL_PHY_ID_88E1112,
837 .phy_id_mask = MARVELL_PHY_ID_MASK,
85cfb534
OJ		 838 .name = "Marvell 88E1112",
839 .features = PHY_GBIT_FEATURES,
840 .flags = PHY_HAS_INTERRUPT,
841 .config_init = &m88e1111_config_init,
842 .config_aneg = &marvell_config_aneg,
843 .read_status = &genphy_read_status,
844 .ack_interrupt = &marvell_ack_interrupt,
845 .config_intr = &marvell_config_intr,
ac8c635a 846 .driver = { .owner = THIS_MODULE },
85cfb534 847 },
e5479239 848 {
2f495c39
BH		 849 .phy_id = MARVELL_PHY_ID_88E1111,
850 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 851 .name = "Marvell 88E1111",
852 .features = PHY_GBIT_FEATURES,
853 .flags = PHY_HAS_INTERRUPT,
854 .config_init = &m88e1111_config_init,
855 .config_aneg = &marvell_config_aneg,
be937f1f 856 .read_status = &marvell_read_status,
e5479239
OJ		 857 .ack_interrupt = &marvell_ack_interrupt,
858 .config_intr = &marvell_config_intr,
ac8c635a 859 .driver = { .owner = THIS_MODULE },
e5479239 860 },
605f196e 861 {
2f495c39
BH		 862 .phy_id = MARVELL_PHY_ID_88E1118,
863 .phy_id_mask = MARVELL_PHY_ID_MASK,
605f196e
RM		 864 .name = "Marvell 88E1118",
865 .features = PHY_GBIT_FEATURES,
866 .flags = PHY_HAS_INTERRUPT,
867 .config_init = &m88e1118_config_init,
868 .config_aneg = &m88e1118_config_aneg,
869 .read_status = &genphy_read_status,
870 .ack_interrupt = &marvell_ack_interrupt,
871 .config_intr = &marvell_config_intr,
872 .driver = {.owner = THIS_MODULE,},
873 },
140bc929 874 {
2f495c39
BH		 875 .phy_id = MARVELL_PHY_ID_88E1121R,
876 .phy_id_mask = MARVELL_PHY_ID_MASK,
140bc929
SP		 877 .name = "Marvell 88E1121R",
878 .features = PHY_GBIT_FEATURES,
879 .flags = PHY_HAS_INTERRUPT,
880 .config_aneg = &m88e1121_config_aneg,
881 .read_status = &marvell_read_status,
882 .ack_interrupt = &marvell_ack_interrupt,
883 .config_intr = &marvell_config_intr,
dcd07be3 884 .did_interrupt = &m88e1121_did_interrupt,
140bc929
SP		 885 .driver = { .owner = THIS_MODULE },
886 },
3ff1c259 887 {
337ac9d5 888 .phy_id = MARVELL_PHY_ID_88E1318S,
6ba74014 889 .phy_id_mask = MARVELL_PHY_ID_MASK,
337ac9d5 890 .name = "Marvell 88E1318S",
3ff1c259
CC		 891 .features = PHY_GBIT_FEATURES,
892 .flags = PHY_HAS_INTERRUPT,
337ac9d5 893 .config_aneg = &m88e1318_config_aneg,
3ff1c259
CC		 894 .read_status = &marvell_read_status,
895 .ack_interrupt = &marvell_ack_interrupt,
896 .config_intr = &marvell_config_intr,
897 .did_interrupt = &m88e1121_did_interrupt,
3871c387
MS		 898 .get_wol = &m88e1318_get_wol,
899 .set_wol = &m88e1318_set_wol,
3ff1c259
CC		 900 .driver = { .owner = THIS_MODULE },
901 },
e5479239 902 {
2f495c39
BH		 903 .phy_id = MARVELL_PHY_ID_88E1145,
904 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 905 .name = "Marvell 88E1145",
906 .features = PHY_GBIT_FEATURES,
907 .flags = PHY_HAS_INTERRUPT,
908 .config_init = &m88e1145_config_init,
909 .config_aneg = &marvell_config_aneg,
910 .read_status = &genphy_read_status,
911 .ack_interrupt = &marvell_ack_interrupt,
912 .config_intr = &marvell_config_intr,
ac8c635a
OJ		 913 .driver = { .owner = THIS_MODULE },
914 },
90600732
DD		 915 {
916 .phy_id = MARVELL_PHY_ID_88E1149R,
917 .phy_id_mask = MARVELL_PHY_ID_MASK,
918 .name = "Marvell 88E1149R",
919 .features = PHY_GBIT_FEATURES,
920 .flags = PHY_HAS_INTERRUPT,
921 .config_init = &m88e1149_config_init,
922 .config_aneg = &m88e1118_config_aneg,
923 .read_status = &genphy_read_status,
924 .ack_interrupt = &marvell_ack_interrupt,
925 .config_intr = &marvell_config_intr,
926 .driver = { .owner = THIS_MODULE },
927 },
ac8c635a 928 {
2f495c39
BH		 929 .phy_id = MARVELL_PHY_ID_88E1240,
930 .phy_id_mask = MARVELL_PHY_ID_MASK,
ac8c635a
OJ		 931 .name = "Marvell 88E1240",
932 .features = PHY_GBIT_FEATURES,
933 .flags = PHY_HAS_INTERRUPT,
934 .config_init = &m88e1111_config_init,
935 .config_aneg = &marvell_config_aneg,
936 .read_status = &genphy_read_status,
937 .ack_interrupt = &marvell_ack_interrupt,
938 .config_intr = &marvell_config_intr,
939 .driver = { .owner = THIS_MODULE },
940 },
00db8189
AF		 941};
942
943static int __init marvell_init(void)
944{
d5bf9071
CH		 945 return phy_drivers_register(marvell_drivers,
946 ARRAY_SIZE(marvell_drivers));
00db8189
AF		 947}
948
949static void __exit marvell_exit(void)
950{
d5bf9071
CH		 951 phy_drivers_unregister(marvell_drivers,
952 ARRAY_SIZE(marvell_drivers));
00db8189
AF		 953}
954
955module_init(marvell_init);
956module_exit(marvell_exit);
4e4f10f6 957
cf93c945 958static struct mdio_device_id __maybe_unused marvell_tbl[] = {
4e4f10f6
DW		 959 { 0x01410c60, 0xfffffff0 },
960 { 0x01410c90, 0xfffffff0 },
961 { 0x01410cc0, 0xfffffff0 },
962 { 0x01410e10, 0xfffffff0 },
963 { 0x01410cb0, 0xfffffff0 },
964 { 0x01410cd0, 0xfffffff0 },
90600732 965 { 0x01410e50, 0xfffffff0 },
4e4f10f6 966 { 0x01410e30, 0xfffffff0 },
3ff1c259 967 { 0x01410e90, 0xfffffff0 },
4e4f10f6
DW		 968 { }
969};
970
971MODULE_DEVICE_TABLE(mdio, marvell_tbl);
kernel source for telekom puls (alcatel/mediatek)