[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / phy / marvell.c

/*
 * drivers/net/phy/marvell.c
 *
 * Driver for Marvell PHYs
 *
 * Author: Andy Fleming
 *
 * Copyright (c) 2004 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/unistd.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/phy.h>
#include <linux/marvell_phy.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>

#define MII_M1011_IEVENT		0x13
#define MII_M1011_IEVENT_CLEAR		0x0000

#define MII_M1011_IMASK			0x12
#define MII_M1011_IMASK_INIT		0x6400
#define MII_M1011_IMASK_CLEAR		0x0000

#define MII_M1011_PHY_SCR		0x10
#define MII_M1011_PHY_SCR_AUTO_CROSS	0x0060

#define MII_M1145_PHY_EXT_CR		0x14
#define MII_M1145_RGMII_RX_DELAY	0x0080
#define MII_M1145_RGMII_TX_DELAY	0x0002

#define MII_M1111_PHY_LED_CONTROL	0x18
#define MII_M1111_PHY_LED_DIRECT	0x4100
#define MII_M1111_PHY_LED_COMBINE	0x411c
#define MII_M1111_PHY_EXT_CR		0x14
#define MII_M1111_RX_DELAY		0x80
#define MII_M1111_TX_DELAY		0x2
#define MII_M1111_PHY_EXT_SR		0x1b

#define MII_M1111_HWCFG_MODE_MASK		0xf
#define MII_M1111_HWCFG_MODE_COPPER_RGMII	0xb
#define MII_M1111_HWCFG_MODE_FIBER_RGMII	0x3
#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK	0x4
#define MII_M1111_HWCFG_MODE_COPPER_RTBI	0x9
#define MII_M1111_HWCFG_FIBER_COPPER_AUTO	0x8000
#define MII_M1111_HWCFG_FIBER_COPPER_RES	0x2000

#define MII_M1111_COPPER		0
#define MII_M1111_FIBER			1

#define MII_88E1121_PHY_LED_CTRL	16
#define MII_88E1121_PHY_LED_PAGE	3
#define MII_88E1121_PHY_LED_DEF		0x0030
#define MII_88E1121_PHY_PAGE		22

#define MII_M1011_PHY_STATUS		0x11
#define MII_M1011_PHY_STATUS_1000	0x8000
#define MII_M1011_PHY_STATUS_100	0x4000
#define MII_M1011_PHY_STATUS_SPD_MASK	0xc000
#define MII_M1011_PHY_STATUS_FULLDUPLEX	0x2000
#define MII_M1011_PHY_STATUS_RESOLVED	0x0800
#define MII_M1011_PHY_STATUS_LINK	0x0400


MODULE_DESCRIPTION("Marvell PHY driver");
MODULE_AUTHOR("Andy Fleming");
MODULE_LICENSE("GPL");

static int marvell_ack_interrupt(struct phy_device *phydev)
{
	int err;

	/* Clear the interrupts by reading the reg */
	err = phy_read(phydev, MII_M1011_IEVENT);

	if (err < 0)
		return err;

	return 0;
}

static int marvell_config_intr(struct phy_device *phydev)
{
	int err;

	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
		err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
	else
		err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);

	return err;
}

static int marvell_config_aneg(struct phy_device *phydev)
{
	int err;

	/* The Marvell PHY has an errata which requires
	 * that certain registers get written in order
	 * to restart autonegotiation */
	err = phy_write(phydev, MII_BMCR, BMCR_RESET);

	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1d, 0x1f);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1e, 0x200c);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1d, 0x5);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1e, 0);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1e, 0x100);
	if (err < 0)
		return err;

	err = phy_write(phydev, MII_M1011_PHY_SCR,
			MII_M1011_PHY_SCR_AUTO_CROSS);
	if (err < 0)
		return err;

	err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
			MII_M1111_PHY_LED_DIRECT);
	if (err < 0)
		return err;

	err = genphy_config_aneg(phydev);
	if (err < 0)
		return err;

	if (phydev->autoneg != AUTONEG_ENABLE) {
		int bmcr;

		/*
		 * A write to speed/duplex bits (that is performed by
		 * genphy_config_aneg() call above) must be followed by
		 * a software reset. Otherwise, the write has no effect.
		 */
		bmcr = phy_read(phydev, MII_BMCR);
		if (bmcr < 0)
			return bmcr;

		err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
		if (err < 0)
			return err;
	}

	return 0;
}

static int m88e1121_config_aneg(struct phy_device *phydev)
{
	int err, temp;

	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	if (err < 0)
		return err;

	err = phy_write(phydev, MII_M1011_PHY_SCR,
			MII_M1011_PHY_SCR_AUTO_CROSS);
	if (err < 0)
		return err;

	temp = phy_read(phydev, MII_88E1121_PHY_PAGE);

	phy_write(phydev, MII_88E1121_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
	phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
	phy_write(phydev, MII_88E1121_PHY_PAGE, temp);

	err = genphy_config_aneg(phydev);

	return err;
}

static int m88e1111_config_init(struct phy_device *phydev)
{
	int err;
	int temp;

	/* Enable Fiber/Copper auto selection */
	temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
	temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO;
	phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);

	temp = phy_read(phydev, MII_BMCR);
	temp |= BMCR_RESET;
	phy_write(phydev, MII_BMCR, temp);

	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {

		temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
		if (temp < 0)
			return temp;

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
			temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
		} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
			temp &= ~MII_M1111_TX_DELAY;
			temp |= MII_M1111_RX_DELAY;
		} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
			temp &= ~MII_M1111_RX_DELAY;
			temp |= MII_M1111_TX_DELAY;
		}

		err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
		if (err < 0)
			return err;

		temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
		if (temp < 0)
			return temp;

		temp &= ~(MII_M1111_HWCFG_MODE_MASK);

		if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
			temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
		else
			temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;

		err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
		if (err < 0)
			return err;
	}

	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
		temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
		if (temp < 0)
			return temp;

		temp &= ~(MII_M1111_HWCFG_MODE_MASK);
		temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
		temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;

		err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
		if (err < 0)
			return err;
	}

	if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
		temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
		if (temp < 0)
			return temp;
		temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
		err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
		if (err < 0)
			return err;

		temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
		if (temp < 0)
			return temp;
		temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
		temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
		err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
		if (err < 0)
			return err;

		/* soft reset */
		err = phy_write(phydev, MII_BMCR, BMCR_RESET);
		if (err < 0)
			return err;
		do
			temp = phy_read(phydev, MII_BMCR);
		while (temp & BMCR_RESET);

		temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
		if (temp < 0)
			return temp;
		temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
		temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
		err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
		if (err < 0)
			return err;
	}


	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	if (err < 0)
		return err;

	return 0;
}

static int m88e1118_config_aneg(struct phy_device *phydev)
{
	int err;

	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	if (err < 0)
		return err;

	err = phy_write(phydev, MII_M1011_PHY_SCR,
			MII_M1011_PHY_SCR_AUTO_CROSS);
	if (err < 0)
		return err;

	err = genphy_config_aneg(phydev);
	return 0;
}

static int m88e1118_config_init(struct phy_device *phydev)
{
	int err;

	/* Change address */
	err = phy_write(phydev, 0x16, 0x0002);
	if (err < 0)
		return err;

	/* Enable 1000 Mbit */
	err = phy_write(phydev, 0x15, 0x1070);
	if (err < 0)
		return err;

	/* Change address */
	err = phy_write(phydev, 0x16, 0x0003);
	if (err < 0)
		return err;

	/* Adjust LED Control */
	if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
		err = phy_write(phydev, 0x10, 0x1100);
	else
		err = phy_write(phydev, 0x10, 0x021e);
	if (err < 0)
		return err;

	/* Reset address */
	err = phy_write(phydev, 0x16, 0x0);
	if (err < 0)
		return err;

	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	if (err < 0)
		return err;

	return 0;
}

static int m88e1145_config_init(struct phy_device *phydev)
{
	int err;

	/* Take care of errata E0 & E1 */
	err = phy_write(phydev, 0x1d, 0x001b);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1e, 0x418f);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1d, 0x0016);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1e, 0xa2da);
	if (err < 0)
		return err;

	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
		int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
		if (temp < 0)
			return temp;

		temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);

		err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
		if (err < 0)
			return err;

		if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
			err = phy_write(phydev, 0x1d, 0x0012);
			if (err < 0)
				return err;

			temp = phy_read(phydev, 0x1e);
			if (temp < 0)
				return temp;

			temp &= 0xf03f;
			temp |= 2 << 9;	/* 36 ohm */
			temp |= 2 << 6;	/* 39 ohm */

			err = phy_write(phydev, 0x1e, temp);
			if (err < 0)
				return err;

			err = phy_write(phydev, 0x1d, 0x3);
			if (err < 0)
				return err;

			err = phy_write(phydev, 0x1e, 0x8000);
			if (err < 0)
				return err;
		}
	}

	return 0;
}

/* marvell_read_status
 *
 * Generic status code does not detect Fiber correctly!
 * Description:
 *   Check the link, then figure out the current state
 *   by comparing what we advertise with what the link partner
 *   advertises.  Start by checking the gigabit possibilities,
 *   then move on to 10/100.
 */
static int marvell_read_status(struct phy_device *phydev)
{
	int adv;
	int err;
	int lpa;
	int status = 0;

	/* Update the link, but return if there
	 * was an error */
	err = genphy_update_link(phydev);
	if (err)
		return err;

	if (AUTONEG_ENABLE == phydev->autoneg) {
		status = phy_read(phydev, MII_M1011_PHY_STATUS);
		if (status < 0)
			return status;

		lpa = phy_read(phydev, MII_LPA);
		if (lpa < 0)
			return lpa;

		adv = phy_read(phydev, MII_ADVERTISE);
		if (adv < 0)
			return adv;

		lpa &= adv;

		if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
			phydev->duplex = DUPLEX_FULL;
		else
			phydev->duplex = DUPLEX_HALF;

		status = status & MII_M1011_PHY_STATUS_SPD_MASK;
		phydev->pause = phydev->asym_pause = 0;

		switch (status) {
		case MII_M1011_PHY_STATUS_1000:
			phydev->speed = SPEED_1000;
			break;

		case MII_M1011_PHY_STATUS_100:
			phydev->speed = SPEED_100;
			break;

		default:
			phydev->speed = SPEED_10;
			break;
		}

		if (phydev->duplex == DUPLEX_FULL) {
			phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
			phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
		}
	} else {
		int bmcr = phy_read(phydev, MII_BMCR);

		if (bmcr < 0)
			return bmcr;

		if (bmcr & BMCR_FULLDPLX)
			phydev->duplex = DUPLEX_FULL;
		else
			phydev->duplex = DUPLEX_HALF;

		if (bmcr & BMCR_SPEED1000)
			phydev->speed = SPEED_1000;
		else if (bmcr & BMCR_SPEED100)
			phydev->speed = SPEED_100;
		else
			phydev->speed = SPEED_10;

		phydev->pause = phydev->asym_pause = 0;
	}

	return 0;
}

static int m88e1121_did_interrupt(struct phy_device *phydev)
{
	int imask;

	imask = phy_read(phydev, MII_M1011_IEVENT);

	if (imask & MII_M1011_IMASK_INIT)
		return 1;

	return 0;
}

static struct phy_driver marvell_drivers[] = {
	{
		.phy_id = MARVELL_PHY_ID_88E1101,
		.phy_id_mask = MARVELL_PHY_ID_MASK,
		.name = "Marvell 88E1101",
		.features = PHY_GBIT_FEATURES,
		.flags = PHY_HAS_INTERRUPT,
		.config_aneg = &marvell_config_aneg,
		.read_status = &genphy_read_status,
		.ack_interrupt = &marvell_ack_interrupt,
		.config_intr = &marvell_config_intr,
		.driver = { .owner = THIS_MODULE },
	},
	{
		.phy_id = MARVELL_PHY_ID_88E1112,
		.phy_id_mask = MARVELL_PHY_ID_MASK,
		.name = "Marvell 88E1112",
		.features = PHY_GBIT_FEATURES,
		.flags = PHY_HAS_INTERRUPT,
		.config_init = &m88e1111_config_init,
		.config_aneg = &marvell_config_aneg,
		.read_status = &genphy_read_status,
		.ack_interrupt = &marvell_ack_interrupt,
		.config_intr = &marvell_config_intr,
		.driver = { .owner = THIS_MODULE },
	},
	{
		.phy_id = MARVELL_PHY_ID_88E1111,
		.phy_id_mask = MARVELL_PHY_ID_MASK,
		.name = "Marvell 88E1111",
		.features = PHY_GBIT_FEATURES,
		.flags = PHY_HAS_INTERRUPT,
		.config_init = &m88e1111_config_init,
		.config_aneg = &marvell_config_aneg,
		.read_status = &marvell_read_status,
		.ack_interrupt = &marvell_ack_interrupt,
		.config_intr = &marvell_config_intr,
		.driver = { .owner = THIS_MODULE },
	},
	{
		.phy_id = MARVELL_PHY_ID_88E1118,
		.phy_id_mask = MARVELL_PHY_ID_MASK,
		.name = "Marvell 88E1118",
		.features = PHY_GBIT_FEATURES,
		.flags = PHY_HAS_INTERRUPT,
		.config_init = &m88e1118_config_init,
		.config_aneg = &m88e1118_config_aneg,
		.read_status = &genphy_read_status,
		.ack_interrupt = &marvell_ack_interrupt,
		.config_intr = &marvell_config_intr,
		.driver = {.owner = THIS_MODULE,},
	},
	{
		.phy_id = MARVELL_PHY_ID_88E1121R,
		.phy_id_mask = MARVELL_PHY_ID_MASK,
		.name = "Marvell 88E1121R",
		.features = PHY_GBIT_FEATURES,
		.flags = PHY_HAS_INTERRUPT,
		.config_aneg = &m88e1121_config_aneg,
		.read_status = &marvell_read_status,
		.ack_interrupt = &marvell_ack_interrupt,
		.config_intr = &marvell_config_intr,
		.did_interrupt = &m88e1121_did_interrupt,
		.driver = { .owner = THIS_MODULE },
	},
	{
		.phy_id = MARVELL_PHY_ID_88E1145,
		.phy_id_mask = MARVELL_PHY_ID_MASK,
		.name = "Marvell 88E1145",
		.features = PHY_GBIT_FEATURES,
		.flags = PHY_HAS_INTERRUPT,
		.config_init = &m88e1145_config_init,
		.config_aneg = &marvell_config_aneg,
		.read_status = &genphy_read_status,
		.ack_interrupt = &marvell_ack_interrupt,
		.config_intr = &marvell_config_intr,
		.driver = { .owner = THIS_MODULE },
	},
	{
		.phy_id = MARVELL_PHY_ID_88E1240,
		.phy_id_mask = MARVELL_PHY_ID_MASK,
		.name = "Marvell 88E1240",
		.features = PHY_GBIT_FEATURES,
		.flags = PHY_HAS_INTERRUPT,
		.config_init = &m88e1111_config_init,
		.config_aneg = &marvell_config_aneg,
		.read_status = &genphy_read_status,
		.ack_interrupt = &marvell_ack_interrupt,
		.config_intr = &marvell_config_intr,
		.driver = { .owner = THIS_MODULE },
	},
};

static int __init marvell_init(void)
{
	int ret;
	int i;

	for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++) {
		ret = phy_driver_register(&marvell_drivers[i]);

		if (ret) {
			while (i-- > 0)
				phy_driver_unregister(&marvell_drivers[i]);
			return ret;
		}
	}

	return 0;
}

static void __exit marvell_exit(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++)
		phy_driver_unregister(&marvell_drivers[i]);
}

module_init(marvell_init);
module_exit(marvell_exit);

static struct mdio_device_id marvell_tbl[] = {
	{ 0x01410c60, 0xfffffff0 },
	{ 0x01410c90, 0xfffffff0 },
	{ 0x01410cc0, 0xfffffff0 },
	{ 0x01410e10, 0xfffffff0 },
	{ 0x01410cb0, 0xfffffff0 },
	{ 0x01410cd0, 0xfffffff0 },
	{ 0x01410e30, 0xfffffff0 },
	{ }
};

MODULE_DEVICE_TABLE(mdio, marvell_tbl);
Commit	Line	Data
00db8189 AF	1	/*
	2	* drivers/net/phy/marvell.c
	3	*
	4	* Driver for Marvell PHYs
	5	*
	6	* Author: Andy Fleming
	7	*
	8	* Copyright (c) 2004 Freescale Semiconductor, Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*
	15	*/
00db8189	16	#include <linux/kernel.h>
00db8189 AF	17	#include <linux/string.h>
	18	#include <linux/errno.h>
	19	#include <linux/unistd.h>
00db8189 AF	20	#include <linux/interrupt.h>
	21	#include <linux/init.h>
	22	#include <linux/delay.h>
	23	#include <linux/netdevice.h>
	24	#include <linux/etherdevice.h>
	25	#include <linux/skbuff.h>
	26	#include <linux/spinlock.h>
	27	#include <linux/mm.h>
	28	#include <linux/module.h>
00db8189 AF	29	#include <linux/mii.h>
	30	#include <linux/ethtool.h>
	31	#include <linux/phy.h>
2f495c39	32	#include <linux/marvell_phy.h>
00db8189 AF	33
	34	#include <asm/io.h>
	35	#include <asm/irq.h>
	36	#include <asm/uaccess.h>
	37
	38	#define MII_M1011_IEVENT 0x13
	39	#define MII_M1011_IEVENT_CLEAR 0x0000
	40
	41	#define MII_M1011_IMASK 0x12
	42	#define MII_M1011_IMASK_INIT 0x6400
	43	#define MII_M1011_IMASK_CLEAR 0x0000
	44
76884679 AF	45	#define MII_M1011_PHY_SCR 0x10
	46	#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
	47
	48	#define MII_M1145_PHY_EXT_CR 0x14
	49	#define MII_M1145_RGMII_RX_DELAY 0x0080
	50	#define MII_M1145_RGMII_TX_DELAY 0x0002
	51
76884679 AF	52	#define MII_M1111_PHY_LED_CONTROL 0x18
	53	#define MII_M1111_PHY_LED_DIRECT 0x4100
	54	#define MII_M1111_PHY_LED_COMBINE 0x411c
895ee682 KP	55	#define MII_M1111_PHY_EXT_CR 0x14
	56	#define MII_M1111_RX_DELAY 0x80
	57	#define MII_M1111_TX_DELAY 0x2
	58	#define MII_M1111_PHY_EXT_SR 0x1b
be937f1f AS	59
	60	#define MII_M1111_HWCFG_MODE_MASK 0xf
	61	#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
	62	#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
4117b5be	63	#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
5f8cbc13	64	#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
be937f1f AS	65	#define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
	66	#define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
	67
	68	#define MII_M1111_COPPER 0
	69	#define MII_M1111_FIBER 1
	70
140bc929 SP	71	#define MII_88E1121_PHY_LED_CTRL 16
	72	#define MII_88E1121_PHY_LED_PAGE 3
	73	#define MII_88E1121_PHY_LED_DEF 0x0030
	74	#define MII_88E1121_PHY_PAGE 22
	75
be937f1f AS	76	#define MII_M1011_PHY_STATUS 0x11
	77	#define MII_M1011_PHY_STATUS_1000 0x8000
	78	#define MII_M1011_PHY_STATUS_100 0x4000
	79	#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
	80	#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
	81	#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
	82	#define MII_M1011_PHY_STATUS_LINK 0x0400
	83
76884679	84
00db8189 AF	85	MODULE_DESCRIPTION("Marvell PHY driver");
	86	MODULE_AUTHOR("Andy Fleming");
	87	MODULE_LICENSE("GPL");
	88
	89	static int marvell_ack_interrupt(struct phy_device *phydev)
	90	{
	91	int err;
	92
	93	/* Clear the interrupts by reading the reg */
	94	err = phy_read(phydev, MII_M1011_IEVENT);
	95
	96	if (err < 0)
	97	return err;
	98
	99	return 0;
	100	}
	101
	102	static int marvell_config_intr(struct phy_device *phydev)
	103	{
	104	int err;
	105
76884679	106	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
00db8189 AF	107	err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
	108	else
	109	err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
	110
	111	return err;
	112	}
	113
	114	static int marvell_config_aneg(struct phy_device *phydev)
	115	{
	116	int err;
	117
	118	/* The Marvell PHY has an errata which requires
	119	* that certain registers get written in order
	120	* to restart autonegotiation */
	121	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	122
	123	if (err < 0)
	124	return err;
	125
	126	err = phy_write(phydev, 0x1d, 0x1f);
	127	if (err < 0)
	128	return err;
	129
	130	err = phy_write(phydev, 0x1e, 0x200c);
	131	if (err < 0)
	132	return err;
	133
	134	err = phy_write(phydev, 0x1d, 0x5);
	135	if (err < 0)
	136	return err;
	137
	138	err = phy_write(phydev, 0x1e, 0);
	139	if (err < 0)
	140	return err;
	141
	142	err = phy_write(phydev, 0x1e, 0x100);
	143	if (err < 0)
	144	return err;
	145
76884679 AF	146	err = phy_write(phydev, MII_M1011_PHY_SCR,
	147	MII_M1011_PHY_SCR_AUTO_CROSS);
	148	if (err < 0)
	149	return err;
	150
	151	err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
	152	MII_M1111_PHY_LED_DIRECT);
	153	if (err < 0)
	154	return err;
00db8189 AF	155
00db8189 AF	156	err = genphy_config_aneg(phydev);
8ff44985 AV	157	if (err < 0)
8ff44985 AV	158	return err;
00db8189	159
8ff44985 AV	160	if (phydev->autoneg != AUTONEG_ENABLE) {
	161	int bmcr;
	162
	163	/*
	164	* A write to speed/duplex bits (that is performed by
	165	* genphy_config_aneg() call above) must be followed by
	166	* a software reset. Otherwise, the write has no effect.
	167	*/
	168	bmcr = phy_read(phydev, MII_BMCR);
	169	if (bmcr < 0)
	170	return bmcr;
	171
	172	err = phy_write(phydev, MII_BMCR, bmcr \| BMCR_RESET);
	173	if (err < 0)
	174	return err;
	175	}
	176
	177	return 0;
00db8189 AF	178	}
00db8189 AF	179
140bc929 SP	180	static int m88e1121_config_aneg(struct phy_device *phydev)
	181	{
	182	int err, temp;
	183
	184	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	185	if (err < 0)
	186	return err;
	187
	188	err = phy_write(phydev, MII_M1011_PHY_SCR,
	189	MII_M1011_PHY_SCR_AUTO_CROSS);
	190	if (err < 0)
	191	return err;
	192
	193	temp = phy_read(phydev, MII_88E1121_PHY_PAGE);
	194
	195	phy_write(phydev, MII_88E1121_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
	196	phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
	197	phy_write(phydev, MII_88E1121_PHY_PAGE, temp);
	198
	199	err = genphy_config_aneg(phydev);
	200
	201	return err;
	202	}
	203
895ee682 KP	204	static int m88e1111_config_init(struct phy_device *phydev)
	205	{
	206	int err;
be937f1f	207	int temp;
be937f1f AS	208
	209	/* Enable Fiber/Copper auto selection */
	210	temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
9cf8fa43	211	temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO;
be937f1f AS	212	phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
	213
	214	temp = phy_read(phydev, MII_BMCR);
	215	temp \|= BMCR_RESET;
	216	phy_write(phydev, MII_BMCR, temp);
895ee682 KP	217
895ee682 KP	218	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) \|\|
9daf5a76 KP	219	(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) \|\|
	220	(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) \|\|
	221	(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
895ee682	222
9daf5a76 KP	223	temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
	224	if (temp < 0)
	225	return temp;
895ee682	226
9daf5a76	227	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
895ee682	228	temp \|= (MII_M1111_RX_DELAY \| MII_M1111_TX_DELAY);
9daf5a76 KP	229	} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
	230	temp &= ~MII_M1111_TX_DELAY;
	231	temp \|= MII_M1111_RX_DELAY;
	232	} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
	233	temp &= ~MII_M1111_RX_DELAY;
	234	temp \|= MII_M1111_TX_DELAY;
895ee682 KP	235	}
895ee682 KP	236
9daf5a76 KP	237	err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
	238	if (err < 0)
	239	return err;
	240
895ee682 KP	241	temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
	242	if (temp < 0)
	243	return temp;
	244
	245	temp &= ~(MII_M1111_HWCFG_MODE_MASK);
be937f1f	246
7239016d	247	if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
be937f1f AS	248	temp \|= MII_M1111_HWCFG_MODE_FIBER_RGMII;
	249	else
	250	temp \|= MII_M1111_HWCFG_MODE_COPPER_RGMII;
895ee682 KP	251
	252	err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
	253	if (err < 0)
	254	return err;
	255	}
	256
4117b5be	257	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
4117b5be KJ	258	temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
	259	if (temp < 0)
	260	return temp;
	261
	262	temp &= ~(MII_M1111_HWCFG_MODE_MASK);
	263	temp \|= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
32d0c1e1	264	temp \|= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
4117b5be KJ	265
	266	err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
	267	if (err < 0)
	268	return err;
	269	}
	270
5f8cbc13 LYB	271	if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
	272	temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
	273	if (temp < 0)
	274	return temp;
	275	temp \|= (MII_M1111_RX_DELAY \| MII_M1111_TX_DELAY);
	276	err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
	277	if (err < 0)
	278	return err;
	279
	280	temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
	281	if (temp < 0)
	282	return temp;
	283	temp &= ~(MII_M1111_HWCFG_MODE_MASK \| MII_M1111_HWCFG_FIBER_COPPER_RES);
	284	temp \|= 0x7 \| MII_M1111_HWCFG_FIBER_COPPER_AUTO;
	285	err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
	286	if (err < 0)
	287	return err;
	288
	289	/* soft reset */
	290	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	291	if (err < 0)
	292	return err;
	293	do
	294	temp = phy_read(phydev, MII_BMCR);
	295	while (temp & BMCR_RESET);
	296
	297	temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
	298	if (temp < 0)
	299	return temp;
	300	temp &= ~(MII_M1111_HWCFG_MODE_MASK \| MII_M1111_HWCFG_FIBER_COPPER_RES);
	301	temp \|= MII_M1111_HWCFG_MODE_COPPER_RTBI \| MII_M1111_HWCFG_FIBER_COPPER_AUTO;
	302	err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
	303	if (err < 0)
	304	return err;
	305	}
	306
	307
895ee682 KP	308	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	309	if (err < 0)
	310	return err;
	311
	312	return 0;
	313	}
	314
605f196e RM	315	static int m88e1118_config_aneg(struct phy_device *phydev)
	316	{
	317	int err;
	318
	319	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	320	if (err < 0)
	321	return err;
	322
	323	err = phy_write(phydev, MII_M1011_PHY_SCR,
	324	MII_M1011_PHY_SCR_AUTO_CROSS);
	325	if (err < 0)
	326	return err;
	327
	328	err = genphy_config_aneg(phydev);
	329	return 0;
	330	}
	331
	332	static int m88e1118_config_init(struct phy_device *phydev)
	333	{
	334	int err;
	335
	336	/* Change address */
	337	err = phy_write(phydev, 0x16, 0x0002);
	338	if (err < 0)
	339	return err;
	340
	341	/* Enable 1000 Mbit */
	342	err = phy_write(phydev, 0x15, 0x1070);
	343	if (err < 0)
	344	return err;
	345
	346	/* Change address */
	347	err = phy_write(phydev, 0x16, 0x0003);
	348	if (err < 0)
	349	return err;
	350
	351	/* Adjust LED Control */
2f495c39 BH	352	if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
	353	err = phy_write(phydev, 0x10, 0x1100);
	354	else
	355	err = phy_write(phydev, 0x10, 0x021e);
605f196e RM	356	if (err < 0)
	357	return err;
	358
	359	/* Reset address */
	360	err = phy_write(phydev, 0x16, 0x0);
	361	if (err < 0)
	362	return err;
	363
	364	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	365	if (err < 0)
	366	return err;
	367
	368	return 0;
	369	}
	370
76884679 AF	371	static int m88e1145_config_init(struct phy_device *phydev)
	372	{
	373	int err;
	374
	375	/* Take care of errata E0 & E1 */
	376	err = phy_write(phydev, 0x1d, 0x001b);
	377	if (err < 0)
	378	return err;
	379
	380	err = phy_write(phydev, 0x1e, 0x418f);
	381	if (err < 0)
	382	return err;
	383
	384	err = phy_write(phydev, 0x1d, 0x0016);
	385	if (err < 0)
	386	return err;
	387
	388	err = phy_write(phydev, 0x1e, 0xa2da);
	389	if (err < 0)
	390	return err;
	391
895ee682	392	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
76884679 AF	393	int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
	394	if (temp < 0)
	395	return temp;
	396
	397	temp \|= (MII_M1145_RGMII_RX_DELAY \| MII_M1145_RGMII_TX_DELAY);
	398
	399	err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
	400	if (err < 0)
	401	return err;
	402
2f495c39	403	if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
76884679 AF	404	err = phy_write(phydev, 0x1d, 0x0012);
	405	if (err < 0)
	406	return err;
	407
	408	temp = phy_read(phydev, 0x1e);
	409	if (temp < 0)
	410	return temp;
	411
	412	temp &= 0xf03f;
	413	temp \|= 2 << 9; /* 36 ohm */
	414	temp \|= 2 << 6; /* 39 ohm */
	415
	416	err = phy_write(phydev, 0x1e, temp);
	417	if (err < 0)
	418	return err;
	419
	420	err = phy_write(phydev, 0x1d, 0x3);
	421	if (err < 0)
	422	return err;
	423
	424	err = phy_write(phydev, 0x1e, 0x8000);
	425	if (err < 0)
	426	return err;
	427	}
	428	}
	429
	430	return 0;
	431	}
00db8189	432
be937f1f AS	433	/* marvell_read_status
	434	*
	435	* Generic status code does not detect Fiber correctly!
f0c88f9c	436	* Description:
be937f1f AS	437	* Check the link, then figure out the current state
	438	* by comparing what we advertise with what the link partner
	439	* advertises. Start by checking the gigabit possibilities,
	440	* then move on to 10/100.
	441	*/
	442	static int marvell_read_status(struct phy_device *phydev)
	443	{
	444	int adv;
	445	int err;
	446	int lpa;
	447	int status = 0;
	448
	449	/* Update the link, but return if there
	450	* was an error */
	451	err = genphy_update_link(phydev);
	452	if (err)
	453	return err;
	454
	455	if (AUTONEG_ENABLE == phydev->autoneg) {
	456	status = phy_read(phydev, MII_M1011_PHY_STATUS);
	457	if (status < 0)
	458	return status;
	459
	460	lpa = phy_read(phydev, MII_LPA);
	461	if (lpa < 0)
	462	return lpa;
	463
	464	adv = phy_read(phydev, MII_ADVERTISE);
	465	if (adv < 0)
	466	return adv;
	467
	468	lpa &= adv;
	469
	470	if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
	471	phydev->duplex = DUPLEX_FULL;
	472	else
	473	phydev->duplex = DUPLEX_HALF;
	474
	475	status = status & MII_M1011_PHY_STATUS_SPD_MASK;
	476	phydev->pause = phydev->asym_pause = 0;
	477
	478	switch (status) {
	479	case MII_M1011_PHY_STATUS_1000:
	480	phydev->speed = SPEED_1000;
	481	break;
	482
	483	case MII_M1011_PHY_STATUS_100:
	484	phydev->speed = SPEED_100;
	485	break;
	486
	487	default:
	488	phydev->speed = SPEED_10;
	489	break;
	490	}
	491
	492	if (phydev->duplex == DUPLEX_FULL) {
	493	phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
	494	phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
	495	}
	496	} else {
	497	int bmcr = phy_read(phydev, MII_BMCR);
	498
	499	if (bmcr < 0)
	500	return bmcr;
501
502	if (bmcr & BMCR_FULLDPLX)
503	phydev->duplex = DUPLEX_FULL;
504	else
505	phydev->duplex = DUPLEX_HALF;
506
507	if (bmcr & BMCR_SPEED1000)
508	phydev->speed = SPEED_1000;
509	else if (bmcr & BMCR_SPEED100)
510	phydev->speed = SPEED_100;
511	else
512	phydev->speed = SPEED_10;
513
514	phydev->pause = phydev->asym_pause = 0;
515	}
516
517	return 0;
518	}
519
dcd07be3 AG	520	static int m88e1121_did_interrupt(struct phy_device *phydev)
	521	{
	522	int imask;
	523
	524	imask = phy_read(phydev, MII_M1011_IEVENT);
	525
	526	if (imask & MII_M1011_IMASK_INIT)
	527	return 1;
	528
	529	return 0;
	530	}
	531
e5479239 OJ	532	static struct phy_driver marvell_drivers[] = {
e5479239 OJ	533	{
2f495c39 BH	534	.phy_id = MARVELL_PHY_ID_88E1101,
2f495c39 BH	535	.phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239 OJ	536	.name = "Marvell 88E1101",
	537	.features = PHY_GBIT_FEATURES,
	538	.flags = PHY_HAS_INTERRUPT,
	539	.config_aneg = &marvell_config_aneg,
	540	.read_status = &genphy_read_status,
	541	.ack_interrupt = &marvell_ack_interrupt,
	542	.config_intr = &marvell_config_intr,
ac8c635a	543	.driver = { .owner = THIS_MODULE },
e5479239	544	},
85cfb534	545	{
2f495c39 BH	546	.phy_id = MARVELL_PHY_ID_88E1112,
2f495c39 BH	547	.phy_id_mask = MARVELL_PHY_ID_MASK,
85cfb534 OJ	548	.name = "Marvell 88E1112",
	549	.features = PHY_GBIT_FEATURES,
	550	.flags = PHY_HAS_INTERRUPT,
	551	.config_init = &m88e1111_config_init,
	552	.config_aneg = &marvell_config_aneg,
	553	.read_status = &genphy_read_status,
	554	.ack_interrupt = &marvell_ack_interrupt,
	555	.config_intr = &marvell_config_intr,
ac8c635a	556	.driver = { .owner = THIS_MODULE },
85cfb534	557	},
e5479239	558	{
2f495c39 BH	559	.phy_id = MARVELL_PHY_ID_88E1111,
2f495c39 BH	560	.phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239 OJ	561	.name = "Marvell 88E1111",
	562	.features = PHY_GBIT_FEATURES,
	563	.flags = PHY_HAS_INTERRUPT,
	564	.config_init = &m88e1111_config_init,
	565	.config_aneg = &marvell_config_aneg,
be937f1f	566	.read_status = &marvell_read_status,
e5479239 OJ	567	.ack_interrupt = &marvell_ack_interrupt,
e5479239 OJ	568	.config_intr = &marvell_config_intr,
ac8c635a	569	.driver = { .owner = THIS_MODULE },
e5479239	570	},
605f196e	571	{
2f495c39 BH	572	.phy_id = MARVELL_PHY_ID_88E1118,
2f495c39 BH	573	.phy_id_mask = MARVELL_PHY_ID_MASK,
605f196e RM	574	.name = "Marvell 88E1118",
	575	.features = PHY_GBIT_FEATURES,
	576	.flags = PHY_HAS_INTERRUPT,
	577	.config_init = &m88e1118_config_init,
	578	.config_aneg = &m88e1118_config_aneg,
	579	.read_status = &genphy_read_status,
	580	.ack_interrupt = &marvell_ack_interrupt,
	581	.config_intr = &marvell_config_intr,
	582	.driver = {.owner = THIS_MODULE,},
	583	},
140bc929	584	{
2f495c39 BH	585	.phy_id = MARVELL_PHY_ID_88E1121R,
2f495c39 BH	586	.phy_id_mask = MARVELL_PHY_ID_MASK,
140bc929 SP	587	.name = "Marvell 88E1121R",
	588	.features = PHY_GBIT_FEATURES,
	589	.flags = PHY_HAS_INTERRUPT,
	590	.config_aneg = &m88e1121_config_aneg,
	591	.read_status = &marvell_read_status,
	592	.ack_interrupt = &marvell_ack_interrupt,
	593	.config_intr = &marvell_config_intr,
dcd07be3	594	.did_interrupt = &m88e1121_did_interrupt,
140bc929 SP	595	.driver = { .owner = THIS_MODULE },
140bc929 SP	596	},
e5479239	597	{
2f495c39 BH	598	.phy_id = MARVELL_PHY_ID_88E1145,
2f495c39 BH	599	.phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239 OJ	600	.name = "Marvell 88E1145",
	601	.features = PHY_GBIT_FEATURES,
	602	.flags = PHY_HAS_INTERRUPT,
	603	.config_init = &m88e1145_config_init,
	604	.config_aneg = &marvell_config_aneg,
	605	.read_status = &genphy_read_status,
	606	.ack_interrupt = &marvell_ack_interrupt,
	607	.config_intr = &marvell_config_intr,
ac8c635a OJ	608	.driver = { .owner = THIS_MODULE },
	609	},
	610	{
2f495c39 BH	611	.phy_id = MARVELL_PHY_ID_88E1240,
2f495c39 BH	612	.phy_id_mask = MARVELL_PHY_ID_MASK,
ac8c635a OJ	613	.name = "Marvell 88E1240",
	614	.features = PHY_GBIT_FEATURES,
	615	.flags = PHY_HAS_INTERRUPT,
	616	.config_init = &m88e1111_config_init,
	617	.config_aneg = &marvell_config_aneg,
	618	.read_status = &genphy_read_status,
	619	.ack_interrupt = &marvell_ack_interrupt,
	620	.config_intr = &marvell_config_intr,
	621	.driver = { .owner = THIS_MODULE },
	622	},
00db8189 AF	623	};
	624
	625	static int __init marvell_init(void)
	626	{
76884679	627	int ret;
e5479239	628	int i;
76884679	629
e5479239 OJ	630	for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++) {
e5479239 OJ	631	ret = phy_driver_register(&marvell_drivers[i]);
76884679	632
e5479239 OJ	633	if (ret) {
	634	while (i-- > 0)
	635	phy_driver_unregister(&marvell_drivers[i]);
	636	return ret;
	637	}
	638	}
76884679 AF	639
76884679 AF	640	return 0;
00db8189 AF	641	}
	642
	643	static void __exit marvell_exit(void)
	644	{
e5479239 OJ	645	int i;
	646
	647	for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++)
	648	phy_driver_unregister(&marvell_drivers[i]);
00db8189 AF	649	}
	650
	651	module_init(marvell_init);
	652	module_exit(marvell_exit);
4e4f10f6 DW	653
	654	static struct mdio_device_id marvell_tbl[] = {
	655	{ 0x01410c60, 0xfffffff0 },
	656	{ 0x01410c90, 0xfffffff0 },
	657	{ 0x01410cc0, 0xfffffff0 },
	658	{ 0x01410e10, 0xfffffff0 },
	659	{ 0x01410cb0, 0xfffffff0 },
	660	{ 0x01410cd0, 0xfffffff0 },
	661	{ 0x01410e30, 0xfffffff0 },
	662	{ }
	663	};
	664
	665	MODULE_DEVICE_TABLE(mdio, marvell_tbl);