[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / phy / marvell.c

/*
 * drivers/net/phy/marvell.c
 *
 * Driver for Marvell PHYs
 *
 * Author: Andy Fleming
 *
 * Copyright (c) 2004 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/unistd.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/phy.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>

#define MII_M1011_IEVENT		0x13
#define MII_M1011_IEVENT_CLEAR		0x0000

#define MII_M1011_IMASK			0x12
#define MII_M1011_IMASK_INIT		0x6400
#define MII_M1011_IMASK_CLEAR		0x0000

#define MII_M1011_PHY_SCR		0x10
#define MII_M1011_PHY_SCR_AUTO_CROSS	0x0060

#define MII_M1145_PHY_EXT_CR		0x14
#define MII_M1145_RGMII_RX_DELAY	0x0080
#define MII_M1145_RGMII_TX_DELAY	0x0002

#define M1145_DEV_FLAGS_RESISTANCE	0x00000001

#define MII_M1111_PHY_LED_CONTROL	0x18
#define MII_M1111_PHY_LED_DIRECT	0x4100
#define MII_M1111_PHY_LED_COMBINE	0x411c
#define MII_M1111_PHY_EXT_CR		0x14
#define MII_M1111_RX_DELAY		0x80
#define MII_M1111_TX_DELAY		0x2
#define MII_M1111_PHY_EXT_SR		0x1b

#define MII_M1111_HWCFG_MODE_MASK		0xf
#define MII_M1111_HWCFG_MODE_COPPER_RGMII	0xb
#define MII_M1111_HWCFG_MODE_FIBER_RGMII	0x3
#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK	0x4
#define MII_M1111_HWCFG_FIBER_COPPER_AUTO	0x8000
#define MII_M1111_HWCFG_FIBER_COPPER_RES	0x2000

#define MII_M1111_COPPER		0
#define MII_M1111_FIBER			1

#define MII_88E1121_PHY_LED_CTRL	16
#define MII_88E1121_PHY_LED_PAGE	3
#define MII_88E1121_PHY_LED_DEF		0x0030
#define MII_88E1121_PHY_PAGE		22

#define MII_M1011_PHY_STATUS		0x11
#define MII_M1011_PHY_STATUS_1000	0x8000
#define MII_M1011_PHY_STATUS_100	0x4000
#define MII_M1011_PHY_STATUS_SPD_MASK	0xc000
#define MII_M1011_PHY_STATUS_FULLDUPLEX	0x2000
#define MII_M1011_PHY_STATUS_RESOLVED	0x0800
#define MII_M1011_PHY_STATUS_LINK	0x0400


MODULE_DESCRIPTION("Marvell PHY driver");
MODULE_AUTHOR("Andy Fleming");
MODULE_LICENSE("GPL");

static int marvell_ack_interrupt(struct phy_device *phydev)
{
	int err;

	/* Clear the interrupts by reading the reg */
	err = phy_read(phydev, MII_M1011_IEVENT);

	if (err < 0)
		return err;

	return 0;
}

static int marvell_config_intr(struct phy_device *phydev)
{
	int err;

	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
		err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
	else
		err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);

	return err;
}

static int marvell_config_aneg(struct phy_device *phydev)
{
	int err;

	/* The Marvell PHY has an errata which requires
	 * that certain registers get written in order
	 * to restart autonegotiation */
	err = phy_write(phydev, MII_BMCR, BMCR_RESET);

	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1d, 0x1f);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1e, 0x200c);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1d, 0x5);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1e, 0);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1e, 0x100);
	if (err < 0)
		return err;

	err = phy_write(phydev, MII_M1011_PHY_SCR,
			MII_M1011_PHY_SCR_AUTO_CROSS);
	if (err < 0)
		return err;

	err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
			MII_M1111_PHY_LED_DIRECT);
	if (err < 0)
		return err;

	err = genphy_config_aneg(phydev);

	return err;
}

static int m88e1121_config_aneg(struct phy_device *phydev)
{
	int err, temp;

	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	if (err < 0)
		return err;

	err = phy_write(phydev, MII_M1011_PHY_SCR,
			MII_M1011_PHY_SCR_AUTO_CROSS);
	if (err < 0)
		return err;

	temp = phy_read(phydev, MII_88E1121_PHY_PAGE);

	phy_write(phydev, MII_88E1121_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
	phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
	phy_write(phydev, MII_88E1121_PHY_PAGE, temp);

	err = genphy_config_aneg(phydev);

	return err;
}

static int m88e1111_config_init(struct phy_device *phydev)
{
	int err;
	int temp;

	/* Enable Fiber/Copper auto selection */
	temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
	temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO;
	phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);

	temp = phy_read(phydev, MII_BMCR);
	temp |= BMCR_RESET;
	phy_write(phydev, MII_BMCR, temp);

	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {

		temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
		if (temp < 0)
			return temp;

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
			temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
		} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
			temp &= ~MII_M1111_TX_DELAY;
			temp |= MII_M1111_RX_DELAY;
		} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
			temp &= ~MII_M1111_RX_DELAY;
			temp |= MII_M1111_TX_DELAY;
		}

		err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
		if (err < 0)
			return err;

		temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
		if (temp < 0)
			return temp;

		temp &= ~(MII_M1111_HWCFG_MODE_MASK);

		if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
			temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
		else
			temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;

		err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
		if (err < 0)
			return err;
	}

	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
		temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
		if (temp < 0)
			return temp;

		temp &= ~(MII_M1111_HWCFG_MODE_MASK);
		temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;

		err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
		if (err < 0)
			return err;
	}

	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	if (err < 0)
		return err;

	return 0;
}

static int m88e1118_config_aneg(struct phy_device *phydev)
{
	int err;

	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	if (err < 0)
		return err;

	err = phy_write(phydev, MII_M1011_PHY_SCR,
			MII_M1011_PHY_SCR_AUTO_CROSS);
	if (err < 0)
		return err;

	err = genphy_config_aneg(phydev);
	return 0;
}

static int m88e1118_config_init(struct phy_device *phydev)
{
	int err;

	/* Change address */
	err = phy_write(phydev, 0x16, 0x0002);
	if (err < 0)
		return err;

	/* Enable 1000 Mbit */
	err = phy_write(phydev, 0x15, 0x1070);
	if (err < 0)
		return err;

	/* Change address */
	err = phy_write(phydev, 0x16, 0x0003);
	if (err < 0)
		return err;

	/* Adjust LED Control */
	err = phy_write(phydev, 0x10, 0x021e);
	if (err < 0)
		return err;

	/* Reset address */
	err = phy_write(phydev, 0x16, 0x0);
	if (err < 0)
		return err;

	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	if (err < 0)
		return err;

	return 0;
}

static int m88e1145_config_init(struct phy_device *phydev)
{
	int err;

	/* Take care of errata E0 & E1 */
	err = phy_write(phydev, 0x1d, 0x001b);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1e, 0x418f);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1d, 0x0016);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1e, 0xa2da);
	if (err < 0)
		return err;

	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
		int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
		if (temp < 0)
			return temp;

		temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);

		err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
		if (err < 0)
			return err;

		if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) {
			err = phy_write(phydev, 0x1d, 0x0012);
			if (err < 0)
				return err;

			temp = phy_read(phydev, 0x1e);
			if (temp < 0)
				return temp;

			temp &= 0xf03f;
			temp |= 2 << 9;	/* 36 ohm */
			temp |= 2 << 6;	/* 39 ohm */

			err = phy_write(phydev, 0x1e, temp);
			if (err < 0)
				return err;

			err = phy_write(phydev, 0x1d, 0x3);
			if (err < 0)
				return err;

			err = phy_write(phydev, 0x1e, 0x8000);
			if (err < 0)
				return err;
		}
	}

	return 0;
}

/* marvell_read_status
 *
 * Generic status code does not detect Fiber correctly!
 * Description:
 *   Check the link, then figure out the current state
 *   by comparing what we advertise with what the link partner
 *   advertises.  Start by checking the gigabit possibilities,
 *   then move on to 10/100.
 */
static int marvell_read_status(struct phy_device *phydev)
{
	int adv;
	int err;
	int lpa;
	int status = 0;

	/* Update the link, but return if there
	 * was an error */
	err = genphy_update_link(phydev);
	if (err)
		return err;

	if (AUTONEG_ENABLE == phydev->autoneg) {
		status = phy_read(phydev, MII_M1011_PHY_STATUS);
		if (status < 0)
			return status;

		lpa = phy_read(phydev, MII_LPA);
		if (lpa < 0)
			return lpa;

		adv = phy_read(phydev, MII_ADVERTISE);
		if (adv < 0)
			return adv;

		lpa &= adv;

		if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
			phydev->duplex = DUPLEX_FULL;
		else
			phydev->duplex = DUPLEX_HALF;

		status = status & MII_M1011_PHY_STATUS_SPD_MASK;
		phydev->pause = phydev->asym_pause = 0;

		switch (status) {
		case MII_M1011_PHY_STATUS_1000:
			phydev->speed = SPEED_1000;
			break;

		case MII_M1011_PHY_STATUS_100:
			phydev->speed = SPEED_100;
			break;

		default:
			phydev->speed = SPEED_10;
			break;
		}

		if (phydev->duplex == DUPLEX_FULL) {
			phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
			phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
		}
	} else {
		int bmcr = phy_read(phydev, MII_BMCR);

		if (bmcr < 0)
			return bmcr;

		if (bmcr & BMCR_FULLDPLX)
			phydev->duplex = DUPLEX_FULL;
		else
			phydev->duplex = DUPLEX_HALF;

		if (bmcr & BMCR_SPEED1000)
			phydev->speed = SPEED_1000;
		else if (bmcr & BMCR_SPEED100)
			phydev->speed = SPEED_100;
		else
			phydev->speed = SPEED_10;

		phydev->pause = phydev->asym_pause = 0;
	}

	return 0;
}

static int m88e1121_did_interrupt(struct phy_device *phydev)
{
	int imask;

	imask = phy_read(phydev, MII_M1011_IEVENT);

	if (imask & MII_M1011_IMASK_INIT)
		return 1;

	return 0;
}

static struct phy_driver marvell_drivers[] = {
	{
		.phy_id = 0x01410c60,
		.phy_id_mask = 0xfffffff0,
		.name = "Marvell 88E1101",
		.features = PHY_GBIT_FEATURES,
		.flags = PHY_HAS_INTERRUPT,
		.config_aneg = &marvell_config_aneg,
		.read_status = &genphy_read_status,
		.ack_interrupt = &marvell_ack_interrupt,
		.config_intr = &marvell_config_intr,
		.driver = { .owner = THIS_MODULE },
	},
	{
		.phy_id = 0x01410c90,
		.phy_id_mask = 0xfffffff0,
		.name = "Marvell 88E1112",
		.features = PHY_GBIT_FEATURES,
		.flags = PHY_HAS_INTERRUPT,
		.config_init = &m88e1111_config_init,
		.config_aneg = &marvell_config_aneg,
		.read_status = &genphy_read_status,
		.ack_interrupt = &marvell_ack_interrupt,
		.config_intr = &marvell_config_intr,
		.driver = { .owner = THIS_MODULE },
	},
	{
		.phy_id = 0x01410cc0,
		.phy_id_mask = 0xfffffff0,
		.name = "Marvell 88E1111",
		.features = PHY_GBIT_FEATURES,
		.flags = PHY_HAS_INTERRUPT,
		.config_init = &m88e1111_config_init,
		.config_aneg = &marvell_config_aneg,
		.read_status = &marvell_read_status,
		.ack_interrupt = &marvell_ack_interrupt,
		.config_intr = &marvell_config_intr,
		.driver = { .owner = THIS_MODULE },
	},
	{
		.phy_id = 0x01410e10,
		.phy_id_mask = 0xfffffff0,
		.name = "Marvell 88E1118",
		.features = PHY_GBIT_FEATURES,
		.flags = PHY_HAS_INTERRUPT,
		.config_init = &m88e1118_config_init,
		.config_aneg = &m88e1118_config_aneg,
		.read_status = &genphy_read_status,
		.ack_interrupt = &marvell_ack_interrupt,
		.config_intr = &marvell_config_intr,
		.driver = {.owner = THIS_MODULE,},
	},
	{
		.phy_id = 0x01410cb0,
		.phy_id_mask = 0xfffffff0,
		.name = "Marvell 88E1121R",
		.features = PHY_GBIT_FEATURES,
		.flags = PHY_HAS_INTERRUPT,
		.config_aneg = &m88e1121_config_aneg,
		.read_status = &marvell_read_status,
		.ack_interrupt = &marvell_ack_interrupt,
		.config_intr = &marvell_config_intr,
		.did_interrupt = &m88e1121_did_interrupt,
		.driver = { .owner = THIS_MODULE },
	},
	{
		.phy_id = 0x01410cd0,
		.phy_id_mask = 0xfffffff0,
		.name = "Marvell 88E1145",
		.features = PHY_GBIT_FEATURES,
		.flags = PHY_HAS_INTERRUPT,
		.config_init = &m88e1145_config_init,
		.config_aneg = &marvell_config_aneg,
		.read_status = &genphy_read_status,
		.ack_interrupt = &marvell_ack_interrupt,
		.config_intr = &marvell_config_intr,
		.driver = { .owner = THIS_MODULE },
	},
	{
		.phy_id = 0x01410e30,
		.phy_id_mask = 0xfffffff0,
		.name = "Marvell 88E1240",
		.features = PHY_GBIT_FEATURES,
		.flags = PHY_HAS_INTERRUPT,
		.config_init = &m88e1111_config_init,
		.config_aneg = &marvell_config_aneg,
		.read_status = &genphy_read_status,
		.ack_interrupt = &marvell_ack_interrupt,
		.config_intr = &marvell_config_intr,
		.driver = { .owner = THIS_MODULE },
	},
};

static int __init marvell_init(void)
{
	int ret;
	int i;

	for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++) {
		ret = phy_driver_register(&marvell_drivers[i]);

		if (ret) {
			while (i-- > 0)
				phy_driver_unregister(&marvell_drivers[i]);
			return ret;
		}
	}

	return 0;
}

static void __exit marvell_exit(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++)
		phy_driver_unregister(&marvell_drivers[i]);
}

module_init(marvell_init);
module_exit(marvell_exit);
Commit	Line	Data
00db8189 AF	1	/*
	2	* drivers/net/phy/marvell.c
	3	*
	4	* Driver for Marvell PHYs
	5	*
	6	* Author: Andy Fleming
	7	*
	8	* Copyright (c) 2004 Freescale Semiconductor, Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*
	15	*/
00db8189	16	#include <linux/kernel.h>
00db8189 AF	17	#include <linux/string.h>
	18	#include <linux/errno.h>
	19	#include <linux/unistd.h>
	20	#include <linux/slab.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/init.h>
	23	#include <linux/delay.h>
	24	#include <linux/netdevice.h>
	25	#include <linux/etherdevice.h>
	26	#include <linux/skbuff.h>
	27	#include <linux/spinlock.h>
	28	#include <linux/mm.h>
	29	#include <linux/module.h>
00db8189 AF	30	#include <linux/mii.h>
	31	#include <linux/ethtool.h>
	32	#include <linux/phy.h>
	33
	34	#include <asm/io.h>
	35	#include <asm/irq.h>
	36	#include <asm/uaccess.h>
	37
	38	#define MII_M1011_IEVENT 0x13
	39	#define MII_M1011_IEVENT_CLEAR 0x0000
	40
	41	#define MII_M1011_IMASK 0x12
	42	#define MII_M1011_IMASK_INIT 0x6400
	43	#define MII_M1011_IMASK_CLEAR 0x0000
	44
76884679 AF	45	#define MII_M1011_PHY_SCR 0x10
	46	#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
	47
	48	#define MII_M1145_PHY_EXT_CR 0x14
	49	#define MII_M1145_RGMII_RX_DELAY 0x0080
	50	#define MII_M1145_RGMII_TX_DELAY 0x0002
	51
	52	#define M1145_DEV_FLAGS_RESISTANCE 0x00000001
	53
	54	#define MII_M1111_PHY_LED_CONTROL 0x18
	55	#define MII_M1111_PHY_LED_DIRECT 0x4100
	56	#define MII_M1111_PHY_LED_COMBINE 0x411c
895ee682 KP	57	#define MII_M1111_PHY_EXT_CR 0x14
	58	#define MII_M1111_RX_DELAY 0x80
	59	#define MII_M1111_TX_DELAY 0x2
	60	#define MII_M1111_PHY_EXT_SR 0x1b
be937f1f AS	61
	62	#define MII_M1111_HWCFG_MODE_MASK 0xf
	63	#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
	64	#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
4117b5be	65	#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
be937f1f AS	66	#define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
	67	#define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
	68
	69	#define MII_M1111_COPPER 0
	70	#define MII_M1111_FIBER 1
	71
140bc929 SP	72	#define MII_88E1121_PHY_LED_CTRL 16
	73	#define MII_88E1121_PHY_LED_PAGE 3
	74	#define MII_88E1121_PHY_LED_DEF 0x0030
	75	#define MII_88E1121_PHY_PAGE 22
	76
be937f1f AS	77	#define MII_M1011_PHY_STATUS 0x11
	78	#define MII_M1011_PHY_STATUS_1000 0x8000
	79	#define MII_M1011_PHY_STATUS_100 0x4000
	80	#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
	81	#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
	82	#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
	83	#define MII_M1011_PHY_STATUS_LINK 0x0400
	84
76884679	85
00db8189 AF	86	MODULE_DESCRIPTION("Marvell PHY driver");
	87	MODULE_AUTHOR("Andy Fleming");
	88	MODULE_LICENSE("GPL");
	89
	90	static int marvell_ack_interrupt(struct phy_device *phydev)
	91	{
	92	int err;
	93
	94	/* Clear the interrupts by reading the reg */
	95	err = phy_read(phydev, MII_M1011_IEVENT);
	96
	97	if (err < 0)
	98	return err;
	99
	100	return 0;
	101	}
	102
	103	static int marvell_config_intr(struct phy_device *phydev)
	104	{
	105	int err;
	106
76884679	107	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
00db8189 AF	108	err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
	109	else
	110	err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
	111
	112	return err;
	113	}
	114
	115	static int marvell_config_aneg(struct phy_device *phydev)
	116	{
	117	int err;
	118
	119	/* The Marvell PHY has an errata which requires
	120	* that certain registers get written in order
	121	* to restart autonegotiation */
	122	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	123
	124	if (err < 0)
	125	return err;
	126
	127	err = phy_write(phydev, 0x1d, 0x1f);
	128	if (err < 0)
	129	return err;
	130
	131	err = phy_write(phydev, 0x1e, 0x200c);
	132	if (err < 0)
	133	return err;
	134
	135	err = phy_write(phydev, 0x1d, 0x5);
	136	if (err < 0)
	137	return err;
	138
	139	err = phy_write(phydev, 0x1e, 0);
	140	if (err < 0)
	141	return err;
	142
	143	err = phy_write(phydev, 0x1e, 0x100);
	144	if (err < 0)
	145	return err;
	146
76884679 AF	147	err = phy_write(phydev, MII_M1011_PHY_SCR,
	148	MII_M1011_PHY_SCR_AUTO_CROSS);
	149	if (err < 0)
	150	return err;
	151
	152	err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
	153	MII_M1111_PHY_LED_DIRECT);
	154	if (err < 0)
	155	return err;
00db8189 AF	156
	157	err = genphy_config_aneg(phydev);
	158
	159	return err;
	160	}
	161
140bc929 SP	162	static int m88e1121_config_aneg(struct phy_device *phydev)
	163	{
	164	int err, temp;
	165
	166	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	167	if (err < 0)
	168	return err;
	169
	170	err = phy_write(phydev, MII_M1011_PHY_SCR,
	171	MII_M1011_PHY_SCR_AUTO_CROSS);
	172	if (err < 0)
	173	return err;
	174
	175	temp = phy_read(phydev, MII_88E1121_PHY_PAGE);
	176
	177	phy_write(phydev, MII_88E1121_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
	178	phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
	179	phy_write(phydev, MII_88E1121_PHY_PAGE, temp);
	180
	181	err = genphy_config_aneg(phydev);
	182
	183	return err;
	184	}
	185
895ee682 KP	186	static int m88e1111_config_init(struct phy_device *phydev)
	187	{
	188	int err;
be937f1f	189	int temp;
be937f1f AS	190
	191	/* Enable Fiber/Copper auto selection */
	192	temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
9cf8fa43	193	temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO;
be937f1f AS	194	phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
	195
	196	temp = phy_read(phydev, MII_BMCR);
	197	temp \|= BMCR_RESET;
	198	phy_write(phydev, MII_BMCR, temp);
895ee682 KP	199
895ee682 KP	200	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) \|\|
9daf5a76 KP	201	(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) \|\|
	202	(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) \|\|
	203	(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
895ee682	204
9daf5a76 KP	205	temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
	206	if (temp < 0)
	207	return temp;
895ee682	208
9daf5a76	209	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
895ee682	210	temp \|= (MII_M1111_RX_DELAY \| MII_M1111_TX_DELAY);
9daf5a76 KP	211	} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
	212	temp &= ~MII_M1111_TX_DELAY;
	213	temp \|= MII_M1111_RX_DELAY;
	214	} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
	215	temp &= ~MII_M1111_RX_DELAY;
	216	temp \|= MII_M1111_TX_DELAY;
895ee682 KP	217	}
895ee682 KP	218
9daf5a76 KP	219	err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
	220	if (err < 0)
	221	return err;
	222
895ee682 KP	223	temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
	224	if (temp < 0)
	225	return temp;
	226
	227	temp &= ~(MII_M1111_HWCFG_MODE_MASK);
be937f1f	228
7239016d	229	if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
be937f1f AS	230	temp \|= MII_M1111_HWCFG_MODE_FIBER_RGMII;
	231	else
	232	temp \|= MII_M1111_HWCFG_MODE_COPPER_RGMII;
895ee682 KP	233
	234	err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
	235	if (err < 0)
	236	return err;
	237	}
	238
4117b5be	239	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
4117b5be KJ	240	temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
	241	if (temp < 0)
	242	return temp;
	243
	244	temp &= ~(MII_M1111_HWCFG_MODE_MASK);
	245	temp \|= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
	246
	247	err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
	248	if (err < 0)
	249	return err;
	250	}
	251
895ee682 KP	252	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	253	if (err < 0)
	254	return err;
	255
	256	return 0;
	257	}
	258
605f196e RM	259	static int m88e1118_config_aneg(struct phy_device *phydev)
	260	{
	261	int err;
	262
	263	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	264	if (err < 0)
	265	return err;
	266
	267	err = phy_write(phydev, MII_M1011_PHY_SCR,
	268	MII_M1011_PHY_SCR_AUTO_CROSS);
	269	if (err < 0)
	270	return err;
	271
	272	err = genphy_config_aneg(phydev);
	273	return 0;
	274	}
	275
	276	static int m88e1118_config_init(struct phy_device *phydev)
	277	{
	278	int err;
	279
	280	/* Change address */
	281	err = phy_write(phydev, 0x16, 0x0002);
	282	if (err < 0)
	283	return err;
	284
	285	/* Enable 1000 Mbit */
	286	err = phy_write(phydev, 0x15, 0x1070);
	287	if (err < 0)
	288	return err;
	289
	290	/* Change address */
	291	err = phy_write(phydev, 0x16, 0x0003);
	292	if (err < 0)
	293	return err;
	294
	295	/* Adjust LED Control */
	296	err = phy_write(phydev, 0x10, 0x021e);
	297	if (err < 0)
	298	return err;
	299
	300	/* Reset address */
	301	err = phy_write(phydev, 0x16, 0x0);
	302	if (err < 0)
	303	return err;
	304
	305	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	306	if (err < 0)
	307	return err;
	308
	309	return 0;
	310	}
	311
76884679 AF	312	static int m88e1145_config_init(struct phy_device *phydev)
	313	{
	314	int err;
	315
	316	/* Take care of errata E0 & E1 */
	317	err = phy_write(phydev, 0x1d, 0x001b);
	318	if (err < 0)
	319	return err;
	320
	321	err = phy_write(phydev, 0x1e, 0x418f);
	322	if (err < 0)
	323	return err;
	324
	325	err = phy_write(phydev, 0x1d, 0x0016);
	326	if (err < 0)
	327	return err;
	328
	329	err = phy_write(phydev, 0x1e, 0xa2da);
	330	if (err < 0)
	331	return err;
	332
895ee682	333	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
76884679 AF	334	int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
	335	if (temp < 0)
	336	return temp;
	337
	338	temp \|= (MII_M1145_RGMII_RX_DELAY \| MII_M1145_RGMII_TX_DELAY);
	339
	340	err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
	341	if (err < 0)
	342	return err;
	343
	344	if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) {
	345	err = phy_write(phydev, 0x1d, 0x0012);
	346	if (err < 0)
	347	return err;
	348
	349	temp = phy_read(phydev, 0x1e);
	350	if (temp < 0)
	351	return temp;
	352
	353	temp &= 0xf03f;
	354	temp \|= 2 << 9; /* 36 ohm */
	355	temp \|= 2 << 6; /* 39 ohm */
	356
	357	err = phy_write(phydev, 0x1e, temp);
	358	if (err < 0)
	359	return err;
	360
	361	err = phy_write(phydev, 0x1d, 0x3);
	362	if (err < 0)
	363	return err;
	364
	365	err = phy_write(phydev, 0x1e, 0x8000);
	366	if (err < 0)
	367	return err;
	368	}
	369	}
	370
	371	return 0;
	372	}
00db8189	373
be937f1f AS	374	/* marvell_read_status
	375	*
	376	* Generic status code does not detect Fiber correctly!
f0c88f9c	377	* Description:
be937f1f AS	378	* Check the link, then figure out the current state
	379	* by comparing what we advertise with what the link partner
	380	* advertises. Start by checking the gigabit possibilities,
	381	* then move on to 10/100.
	382	*/
	383	static int marvell_read_status(struct phy_device *phydev)
	384	{
	385	int adv;
	386	int err;
	387	int lpa;
	388	int status = 0;
	389
	390	/* Update the link, but return if there
	391	* was an error */
	392	err = genphy_update_link(phydev);
	393	if (err)
	394	return err;
	395
	396	if (AUTONEG_ENABLE == phydev->autoneg) {
	397	status = phy_read(phydev, MII_M1011_PHY_STATUS);
	398	if (status < 0)
	399	return status;
	400
	401	lpa = phy_read(phydev, MII_LPA);
	402	if (lpa < 0)
	403	return lpa;
	404
	405	adv = phy_read(phydev, MII_ADVERTISE);
	406	if (adv < 0)
	407	return adv;
	408
	409	lpa &= adv;
	410
	411	if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
	412	phydev->duplex = DUPLEX_FULL;
	413	else
	414	phydev->duplex = DUPLEX_HALF;
	415
	416	status = status & MII_M1011_PHY_STATUS_SPD_MASK;
	417	phydev->pause = phydev->asym_pause = 0;
	418
	419	switch (status) {
	420	case MII_M1011_PHY_STATUS_1000:
	421	phydev->speed = SPEED_1000;
	422	break;
	423
	424	case MII_M1011_PHY_STATUS_100:
	425	phydev->speed = SPEED_100;
	426	break;
	427
	428	default:
	429	phydev->speed = SPEED_10;
	430	break;
	431	}
	432
	433	if (phydev->duplex == DUPLEX_FULL) {
	434	phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
	435	phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
	436	}
	437	} else {
	438	int bmcr = phy_read(phydev, MII_BMCR);
	439
	440	if (bmcr < 0)
	441	return bmcr;
442
443	if (bmcr & BMCR_FULLDPLX)
444	phydev->duplex = DUPLEX_FULL;
445	else
446	phydev->duplex = DUPLEX_HALF;
447
448	if (bmcr & BMCR_SPEED1000)
449	phydev->speed = SPEED_1000;
450	else if (bmcr & BMCR_SPEED100)
451	phydev->speed = SPEED_100;
452	else
453	phydev->speed = SPEED_10;
454
455	phydev->pause = phydev->asym_pause = 0;
456	}
457
458	return 0;
459	}
460
dcd07be3 AG	461	static int m88e1121_did_interrupt(struct phy_device *phydev)
	462	{
	463	int imask;
	464
	465	imask = phy_read(phydev, MII_M1011_IEVENT);
	466
	467	if (imask & MII_M1011_IMASK_INIT)
	468	return 1;
	469
	470	return 0;
	471	}
	472
e5479239 OJ	473	static struct phy_driver marvell_drivers[] = {
	474	{
	475	.phy_id = 0x01410c60,
	476	.phy_id_mask = 0xfffffff0,
	477	.name = "Marvell 88E1101",
	478	.features = PHY_GBIT_FEATURES,
	479	.flags = PHY_HAS_INTERRUPT,
	480	.config_aneg = &marvell_config_aneg,
	481	.read_status = &genphy_read_status,
	482	.ack_interrupt = &marvell_ack_interrupt,
	483	.config_intr = &marvell_config_intr,
ac8c635a	484	.driver = { .owner = THIS_MODULE },
e5479239	485	},
85cfb534 OJ	486	{
	487	.phy_id = 0x01410c90,
	488	.phy_id_mask = 0xfffffff0,
	489	.name = "Marvell 88E1112",
	490	.features = PHY_GBIT_FEATURES,
	491	.flags = PHY_HAS_INTERRUPT,
	492	.config_init = &m88e1111_config_init,
	493	.config_aneg = &marvell_config_aneg,
	494	.read_status = &genphy_read_status,
	495	.ack_interrupt = &marvell_ack_interrupt,
	496	.config_intr = &marvell_config_intr,
ac8c635a	497	.driver = { .owner = THIS_MODULE },
85cfb534	498	},
e5479239 OJ	499	{
	500	.phy_id = 0x01410cc0,
	501	.phy_id_mask = 0xfffffff0,
	502	.name = "Marvell 88E1111",
	503	.features = PHY_GBIT_FEATURES,
	504	.flags = PHY_HAS_INTERRUPT,
	505	.config_init = &m88e1111_config_init,
	506	.config_aneg = &marvell_config_aneg,
be937f1f	507	.read_status = &marvell_read_status,
e5479239 OJ	508	.ack_interrupt = &marvell_ack_interrupt,
e5479239 OJ	509	.config_intr = &marvell_config_intr,
ac8c635a	510	.driver = { .owner = THIS_MODULE },
e5479239	511	},
605f196e RM	512	{
	513	.phy_id = 0x01410e10,
	514	.phy_id_mask = 0xfffffff0,
	515	.name = "Marvell 88E1118",
	516	.features = PHY_GBIT_FEATURES,
	517	.flags = PHY_HAS_INTERRUPT,
	518	.config_init = &m88e1118_config_init,
	519	.config_aneg = &m88e1118_config_aneg,
	520	.read_status = &genphy_read_status,
	521	.ack_interrupt = &marvell_ack_interrupt,
	522	.config_intr = &marvell_config_intr,
	523	.driver = {.owner = THIS_MODULE,},
	524	},
140bc929 SP	525	{
	526	.phy_id = 0x01410cb0,
	527	.phy_id_mask = 0xfffffff0,
	528	.name = "Marvell 88E1121R",
	529	.features = PHY_GBIT_FEATURES,
	530	.flags = PHY_HAS_INTERRUPT,
	531	.config_aneg = &m88e1121_config_aneg,
	532	.read_status = &marvell_read_status,
	533	.ack_interrupt = &marvell_ack_interrupt,
	534	.config_intr = &marvell_config_intr,
dcd07be3	535	.did_interrupt = &m88e1121_did_interrupt,
140bc929 SP	536	.driver = { .owner = THIS_MODULE },
140bc929 SP	537	},
e5479239 OJ	538	{
	539	.phy_id = 0x01410cd0,
	540	.phy_id_mask = 0xfffffff0,
	541	.name = "Marvell 88E1145",
	542	.features = PHY_GBIT_FEATURES,
	543	.flags = PHY_HAS_INTERRUPT,
	544	.config_init = &m88e1145_config_init,
	545	.config_aneg = &marvell_config_aneg,
	546	.read_status = &genphy_read_status,
	547	.ack_interrupt = &marvell_ack_interrupt,
	548	.config_intr = &marvell_config_intr,
ac8c635a OJ	549	.driver = { .owner = THIS_MODULE },
	550	},
	551	{
	552	.phy_id = 0x01410e30,
	553	.phy_id_mask = 0xfffffff0,
	554	.name = "Marvell 88E1240",
	555	.features = PHY_GBIT_FEATURES,
	556	.flags = PHY_HAS_INTERRUPT,
	557	.config_init = &m88e1111_config_init,
	558	.config_aneg = &marvell_config_aneg,
	559	.read_status = &genphy_read_status,
	560	.ack_interrupt = &marvell_ack_interrupt,
	561	.config_intr = &marvell_config_intr,
	562	.driver = { .owner = THIS_MODULE },
	563	},
00db8189 AF	564	};
	565
	566	static int __init marvell_init(void)
	567	{
76884679	568	int ret;
e5479239	569	int i;
76884679	570
e5479239 OJ	571	for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++) {
e5479239 OJ	572	ret = phy_driver_register(&marvell_drivers[i]);
76884679	573
e5479239 OJ	574	if (ret) {
	575	while (i-- > 0)
	576	phy_driver_unregister(&marvell_drivers[i]);
	577	return ret;
	578	}
	579	}
76884679 AF	580
76884679 AF	581	return 0;
00db8189 AF	582	}
	583
	584	static void __exit marvell_exit(void)
	585	{
e5479239 OJ	586	int i;
	587
	588	for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++)
	589	phy_driver_unregister(&marvell_drivers[i]);
00db8189 AF	590	}
	591
	592	module_init(marvell_init);
	593	module_exit(marvell_exit);