sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
   7  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <sound/core.h>
  30 #include <sound/pcm.h>
  31 #include <sound/pcm_params.h>
  32 #include <sound/initval.h>
  33 #include <sound/soc.h>
  34
  35 #include <plat/cpu.h>
  36 #include <plat/dma.h>
  37 #include <linux/platform_data/asoc-ti-mcbsp.h>
  38 #include "mcbsp.h"
  39 #include "omap-mcbsp.h"
  40 #include "omap-pcm.h"
  41
  42 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  43
  44 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
  45         xhandler_get, xhandler_put) \
  46 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  47         .info = omap_mcbsp_st_info_volsw, \
  48         .get = xhandler_get, .put = xhandler_put, \
  49         .private_value = (unsigned long) &(struct soc_mixer_control) \
  50         {.min = xmin, .max = xmax} }
  51
  52 enum {
  53         OMAP_MCBSP_WORD_8 = 0,
  54         OMAP_MCBSP_WORD_12,
  55         OMAP_MCBSP_WORD_16,
  56         OMAP_MCBSP_WORD_20,
  57         OMAP_MCBSP_WORD_24,
  58         OMAP_MCBSP_WORD_32,
  59 };
  60
  61 /*
  62  * Stream DMA parameters. DMA request line and port address are set runtime
  63  * since they are different between OMAP1 and later OMAPs
  64  */
  65 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
  66 {
  67         struct snd_soc_pcm_runtime *rtd = substream->private_data;
  68         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  69         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  70         struct omap_pcm_dma_data *dma_data;
  71         int words;
  72
  73         dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
  74
  75         /*
  76          * Configure McBSP threshold based on either:
  77          * packet_size, when the sDMA is in packet mode, or based on the
  78          * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
  79          * for mono streams.
  80          */
  81         if (dma_data->packet_size)
  82                 words = dma_data->packet_size;
  83         else if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
  84                 words = snd_pcm_lib_period_bytes(substream) /
  85                                                 (mcbsp->wlen / 8);
  86         else
  87                 words = 1;
  88
  89         /* Configure McBSP internal buffer usage */
  90         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  91                 omap_mcbsp_set_tx_threshold(mcbsp, words);
  92         else
  93                 omap_mcbsp_set_rx_threshold(mcbsp, words);
  94 }
  95
  96 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
  97                                     struct snd_pcm_hw_rule *rule)
  98 {
  99         struct snd_interval *buffer_size = hw_param_interval(params,
 100                                         SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
 101         struct snd_interval *channels = hw_param_interval(params,
 102                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 103         struct omap_mcbsp *mcbsp = rule->private;
 104         struct snd_interval frames;
 105         int size;
 106
 107         snd_interval_any(&frames);
 108         size = mcbsp->pdata->buffer_size;
 109
 110         frames.min = size / channels->min;
 111         frames.integer = 1;
 112         return snd_interval_refine(buffer_size, &frames);
 113 }
 114
 115 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 116                                   struct snd_soc_dai *cpu_dai)
 117 {
 118         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 119         int err = 0;
 120
 121         if (!cpu_dai->active)
 122                 err = omap_mcbsp_request(mcbsp);
 123
 124         /*
 125          * OMAP3 McBSP FIFO is word structured.
 126          * McBSP2 has 1024 + 256 = 1280 word long buffer,
 127          * McBSP1,3,4,5 has 128 word long buffer
 128          * This means that the size of the FIFO depends on the sample format.
 129          * For example on McBSP3:
 130          * 16bit samples: size is 128 * 2 = 256 bytes
 131          * 32bit samples: size is 128 * 4 = 512 bytes
 132          * It is simpler to place constraint for buffer and period based on
 133          * channels.
 134          * McBSP3 as example again (16 or 32 bit samples):
 135          * 1 channel (mono): size is 128 frames (128 words)
 136          * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
 137          * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
 138          */
 139         if (mcbsp->pdata->buffer_size) {
 140                 /*
 141                 * Rule for the buffer size. We should not allow
 142                 * smaller buffer than the FIFO size to avoid underruns.
 143                 * This applies only for the playback stream.
 144                 */
 145                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 146                         snd_pcm_hw_rule_add(substream->runtime, 0,
 147                                             SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 148                                             omap_mcbsp_hwrule_min_buffersize,
 149                                             mcbsp,
 150                                             SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 151
 152                 /* Make sure, that the period size is always even */
 153                 snd_pcm_hw_constraint_step(substream->runtime, 0,
 154                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
 155         }
 156
 157         return err;
 158 }
 159
 160 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 161                                     struct snd_soc_dai *cpu_dai)
 162 {
 163         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 164
 165         if (!cpu_dai->active) {
 166                 omap_mcbsp_free(mcbsp);
 167                 mcbsp->configured = 0;
 168         }
 169 }
 170
 171 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 172                                   struct snd_soc_dai *cpu_dai)
 173 {
 174         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 175         int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 176
 177         switch (cmd) {
 178         case SNDRV_PCM_TRIGGER_START:
 179         case SNDRV_PCM_TRIGGER_RESUME:
 180         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 181                 mcbsp->active++;
 182                 omap_mcbsp_start(mcbsp, play, !play);
 183                 break;
 184
 185         case SNDRV_PCM_TRIGGER_STOP:
 186         case SNDRV_PCM_TRIGGER_SUSPEND:
 187         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 188                 omap_mcbsp_stop(mcbsp, play, !play);
 189                 mcbsp->active--;
 190                 break;
 191         default:
 192                 err = -EINVAL;
 193         }
 194
 195         return err;
 196 }
 197
 198 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
 199                         struct snd_pcm_substream *substream,
 200                         struct snd_soc_dai *dai)
 201 {
 202         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 203         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 204         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 205         u16 fifo_use;
 206         snd_pcm_sframes_t delay;
 207
 208         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 209                 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
 210         else
 211                 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
 212
 213         /*
 214          * Divide the used locations with the channel count to get the
 215          * FIFO usage in samples (don't care about partial samples in the
 216          * buffer).
 217          */
 218         delay = fifo_use / substream->runtime->channels;
 219
 220         return delay;
 221 }
 222
 223 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 224                                     struct snd_pcm_hw_params *params,
 225                                     struct snd_soc_dai *cpu_dai)
 226 {
 227         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 228         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 229         struct omap_pcm_dma_data *dma_data;
 230         int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
 231         int pkt_size = 0;
 232         unsigned int format, div, framesize, master;
 233
 234         dma_data = &mcbsp->dma_data[substream->stream];
 235         channels = params_channels(params);
 236
 237         switch (params_format(params)) {
 238         case SNDRV_PCM_FORMAT_S16_LE:
 239                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
 240                 wlen = 16;
 241                 break;
 242         case SNDRV_PCM_FORMAT_S32_LE:
 243                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S32;
 244                 wlen = 32;
 245                 break;
 246         default:
 247                 return -EINVAL;
 248         }
 249         if (mcbsp->pdata->buffer_size) {
 250                 dma_data->set_threshold = omap_mcbsp_set_threshold;
 251                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 252                         int period_words, max_thrsh;
 253
 254                         period_words = params_period_bytes(params) / (wlen / 8);
 255                         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 256                                 max_thrsh = mcbsp->max_tx_thres;
 257                         else
 258                                 max_thrsh = mcbsp->max_rx_thres;
 259                         /*
 260                          * If the period contains less or equal number of words,
 261                          * we are using the original threshold mode setup:
 262                          * McBSP threshold = sDMA frame size = period_size
 263                          * Otherwise we switch to sDMA packet mode:
 264                          * McBSP threshold = sDMA packet size
 265                          * sDMA frame size = period size
 266                          */
 267                         if (period_words > max_thrsh) {
 268                                 int divider = 0;
 269
 270                                 /*
 271                                  * Look for the biggest threshold value, which
 272                                  * divides the period size evenly.
 273                                  */
 274                                 divider = period_words / max_thrsh;
 275                                 if (period_words % max_thrsh)
 276                                         divider++;
 277                                 while (period_words % divider &&
 278                                         divider < period_words)
 279                                         divider++;
 280                                 if (divider == period_words)
 281                                         return -EINVAL;
 282
 283                                 pkt_size = period_words / divider;
 284                                 sync_mode = OMAP_DMA_SYNC_PACKET;
 285                         } else {
 286                                 sync_mode = OMAP_DMA_SYNC_FRAME;
 287                         }
 288                 } else if (channels > 1) {
 289                         /* Use packet mode for non mono streams */
 290                         pkt_size = channels;
 291                         sync_mode = OMAP_DMA_SYNC_PACKET;
 292                 }
 293         }
 294
 295         dma_data->sync_mode = sync_mode;
 296         dma_data->packet_size = pkt_size;
 297
 298         snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
 299
 300         if (mcbsp->configured) {
 301                 /* McBSP already configured by another stream */
 302                 return 0;
 303         }
 304
 305         regs->rcr2      &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
 306         regs->xcr2      &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
 307         regs->rcr1      &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
 308         regs->xcr1      &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
 309         format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 310         wpf = channels;
 311         if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
 312                               format == SND_SOC_DAIFMT_LEFT_J)) {
 313                 /* Use dual-phase frames */
 314                 regs->rcr2      |= RPHASE;
 315                 regs->xcr2      |= XPHASE;
 316                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
 317                 wpf--;
 318                 regs->rcr2      |= RFRLEN2(wpf - 1);
 319                 regs->xcr2      |= XFRLEN2(wpf - 1);
 320         }
 321
 322         regs->rcr1      |= RFRLEN1(wpf - 1);
 323         regs->xcr1      |= XFRLEN1(wpf - 1);
 324
 325         switch (params_format(params)) {
 326         case SNDRV_PCM_FORMAT_S16_LE:
 327                 /* Set word lengths */
 328                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 329                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 330                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 331                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 332                 break;
 333         case SNDRV_PCM_FORMAT_S32_LE:
 334                 /* Set word lengths */
 335                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_32);
 336                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_32);
 337                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_32);
 338                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_32);
 339                 break;
 340         default:
 341                 /* Unsupported PCM format */
 342                 return -EINVAL;
 343         }
 344
 345         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
 346          * by _counting_ BCLKs. Calculate frame size in BCLKs */
 347         master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 348         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
 349                 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
 350                 framesize = (mcbsp->in_freq / div) / params_rate(params);
 351
 352                 if (framesize < wlen * channels) {
 353                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
 354                                         "channels\n", __func__);
 355                         return -EINVAL;
 356                 }
 357         } else
 358                 framesize = wlen * channels;
 359
 360         /* Set FS period and length in terms of bit clock periods */
 361         regs->srgr2     &= ~FPER(0xfff);
 362         regs->srgr1     &= ~FWID(0xff);
 363         switch (format) {
 364         case SND_SOC_DAIFMT_I2S:
 365         case SND_SOC_DAIFMT_LEFT_J:
 366                 regs->srgr2     |= FPER(framesize - 1);
 367                 regs->srgr1     |= FWID((framesize >> 1) - 1);
 368                 break;
 369         case SND_SOC_DAIFMT_DSP_A:
 370         case SND_SOC_DAIFMT_DSP_B:
 371                 regs->srgr2     |= FPER(framesize - 1);
 372                 regs->srgr1     |= FWID(0);
 373                 break;
 374         }
 375
 376         omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
 377         mcbsp->wlen = wlen;
 378         mcbsp->configured = 1;
 379
 380         return 0;
 381 }
 382
 383 /*
 384  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 385  * cache is initialized here
 386  */
 387 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 388                                       unsigned int fmt)
 389 {
 390         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 391         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 392         bool inv_fs = false;
 393
 394         if (mcbsp->configured)
 395                 return 0;
 396
 397         mcbsp->fmt = fmt;
 398         memset(regs, 0, sizeof(*regs));
 399         /* Generic McBSP register settings */
 400         regs->spcr2     |= XINTM(3) | FREE;
 401         regs->spcr1     |= RINTM(3);
 402         /* RFIG and XFIG are not defined in 34xx */
 403         if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) {
 404                 regs->rcr2      |= RFIG;
 405                 regs->xcr2      |= XFIG;
 406         }
 407         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 408                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 409                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 410         }
 411
 412         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 413         case SND_SOC_DAIFMT_I2S:
 414                 /* 1-bit data delay */
 415                 regs->rcr2      |= RDATDLY(1);
 416                 regs->xcr2      |= XDATDLY(1);
 417                 break;
 418         case SND_SOC_DAIFMT_LEFT_J:
 419                 /* 0-bit data delay */
 420                 regs->rcr2      |= RDATDLY(0);
 421                 regs->xcr2      |= XDATDLY(0);
 422                 regs->spcr1     |= RJUST(2);
 423                 /* Invert FS polarity configuration */
 424                 inv_fs = true;
 425                 break;
 426         case SND_SOC_DAIFMT_DSP_A:
 427                 /* 1-bit data delay */
 428                 regs->rcr2      |= RDATDLY(1);
 429                 regs->xcr2      |= XDATDLY(1);
 430                 /* Invert FS polarity configuration */
 431                 inv_fs = true;
 432                 break;
 433         case SND_SOC_DAIFMT_DSP_B:
 434                 /* 0-bit data delay */
 435                 regs->rcr2      |= RDATDLY(0);
 436                 regs->xcr2      |= XDATDLY(0);
 437                 /* Invert FS polarity configuration */
 438                 inv_fs = true;
 439                 break;
 440         default:
 441                 /* Unsupported data format */
 442                 return -EINVAL;
 443         }
 444
 445         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 446         case SND_SOC_DAIFMT_CBS_CFS:
 447                 /* McBSP master. Set FS and bit clocks as outputs */
 448                 regs->pcr0      |= FSXM | FSRM |
 449                                    CLKXM | CLKRM;
 450                 /* Sample rate generator drives the FS */
 451                 regs->srgr2     |= FSGM;
 452                 break;
 453         case SND_SOC_DAIFMT_CBM_CFM:
 454                 /* McBSP slave */
 455                 break;
 456         default:
 457                 /* Unsupported master/slave configuration */
 458                 return -EINVAL;
 459         }
 460
 461         /* Set bit clock (CLKX/CLKR) and FS polarities */
 462         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 463         case SND_SOC_DAIFMT_NB_NF:
 464                 /*
 465                  * Normal BCLK + FS.
 466                  * FS active low. TX data driven on falling edge of bit clock
 467                  * and RX data sampled on rising edge of bit clock.
 468                  */
 469                 regs->pcr0      |= FSXP | FSRP |
 470                                    CLKXP | CLKRP;
 471                 break;
 472         case SND_SOC_DAIFMT_NB_IF:
 473                 regs->pcr0      |= CLKXP | CLKRP;
 474                 break;
 475         case SND_SOC_DAIFMT_IB_NF:
 476                 regs->pcr0      |= FSXP | FSRP;
 477                 break;
 478         case SND_SOC_DAIFMT_IB_IF:
 479                 break;
 480         default:
 481                 return -EINVAL;
 482         }
 483         if (inv_fs == true)
 484                 regs->pcr0 ^= FSXP | FSRP;
 485
 486         return 0;
 487 }
 488
 489 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 490                                      int div_id, int div)
 491 {
 492         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 493         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 494
 495         if (div_id != OMAP_MCBSP_CLKGDV)
 496                 return -ENODEV;
 497
 498         mcbsp->clk_div = div;
 499         regs->srgr1     &= ~CLKGDV(0xff);
 500         regs->srgr1     |= CLKGDV(div - 1);
 501
 502         return 0;
 503 }
 504
 505 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 506                                          int clk_id, unsigned int freq,
 507                                          int dir)
 508 {
 509         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 510         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 511         int err = 0;
 512
 513         if (mcbsp->active) {
 514                 if (freq == mcbsp->in_freq)
 515                         return 0;
 516                 else
 517                         return -EBUSY;
 518         }
 519
 520         if (clk_id == OMAP_MCBSP_SYSCLK_CLK ||
 521             clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK ||
 522             clk_id == OMAP_MCBSP_SYSCLK_CLKS_EXT ||
 523             clk_id == OMAP_MCBSP_SYSCLK_CLKX_EXT ||
 524             clk_id == OMAP_MCBSP_SYSCLK_CLKR_EXT) {
 525                 mcbsp->in_freq = freq;
 526                 regs->srgr2     &= ~CLKSM;
 527                 regs->pcr0      &= ~SCLKME;
 528         } else if (cpu_class_is_omap1()) {
 529                 /*
 530                  * McBSP CLKR/FSR signal muxing functions are only available on
 531                  * OMAP2 or newer versions
 532                  */
 533                 return -EINVAL;
 534         }
 535
 536         switch (clk_id) {
 537         case OMAP_MCBSP_SYSCLK_CLK:
 538                 regs->srgr2     |= CLKSM;
 539                 break;
 540         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 541                 if (cpu_class_is_omap1()) {
 542                         err = -EINVAL;
 543                         break;
 544                 }
 545                 err = omap2_mcbsp_set_clks_src(mcbsp,
 546                                                MCBSP_CLKS_PRCM_SRC);
 547                 break;
 548         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 549                 if (cpu_class_is_omap1()) {
 550                         err = 0;
 551                         break;
 552                 }
 553                 err = omap2_mcbsp_set_clks_src(mcbsp,
 554                                                MCBSP_CLKS_PAD_SRC);
 555                 break;
 556
 557         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 558                 regs->srgr2     |= CLKSM;
 559         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 560                 regs->pcr0      |= SCLKME;
 561                 break;
 562
 563
 564         case OMAP_MCBSP_CLKR_SRC_CLKR:
 565                 err = omap_mcbsp_6pin_src_mux(mcbsp, CLKR_SRC_CLKR);
 566                 break;
 567         case OMAP_MCBSP_CLKR_SRC_CLKX:
 568                 err = omap_mcbsp_6pin_src_mux(mcbsp, CLKR_SRC_CLKX);
 569                 break;
 570         case OMAP_MCBSP_FSR_SRC_FSR:
 571                 err = omap_mcbsp_6pin_src_mux(mcbsp, FSR_SRC_FSR);
 572                 break;
 573         case OMAP_MCBSP_FSR_SRC_FSX:
 574                 err = omap_mcbsp_6pin_src_mux(mcbsp, FSR_SRC_FSX);
 575                 break;
 576         default:
 577                 err = -ENODEV;
 578         }
 579
 580         return err;
 581 }
 582
 583 static const struct snd_soc_dai_ops mcbsp_dai_ops = {
 584         .startup        = omap_mcbsp_dai_startup,
 585         .shutdown       = omap_mcbsp_dai_shutdown,
 586         .trigger        = omap_mcbsp_dai_trigger,
 587         .delay          = omap_mcbsp_dai_delay,
 588         .hw_params      = omap_mcbsp_dai_hw_params,
 589         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
 590         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
 591         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
 592 };
 593
 594 static int omap_mcbsp_probe(struct snd_soc_dai *dai)
 595 {
 596         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
 597
 598         pm_runtime_enable(mcbsp->dev);
 599
 600         return 0;
 601 }
 602
 603 static int omap_mcbsp_remove(struct snd_soc_dai *dai)
 604 {
 605         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
 606
 607         pm_runtime_disable(mcbsp->dev);
 608
 609         return 0;
 610 }
 611
 612 static struct snd_soc_dai_driver omap_mcbsp_dai = {
 613         .probe = omap_mcbsp_probe,
 614         .remove = omap_mcbsp_remove,
 615         .playback = {
 616                 .channels_min = 1,
 617                 .channels_max = 16,
 618                 .rates = OMAP_MCBSP_RATES,
 619                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 620         },
 621         .capture = {
 622                 .channels_min = 1,
 623                 .channels_max = 16,
 624                 .rates = OMAP_MCBSP_RATES,
 625                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 626         },
 627         .ops = &mcbsp_dai_ops,
 628 };
 629
 630 static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
 631                         struct snd_ctl_elem_info *uinfo)
 632 {
 633         struct soc_mixer_control *mc =
 634                 (struct soc_mixer_control *)kcontrol->private_value;
 635         int max = mc->max;
 636         int min = mc->min;
 637
 638         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 639         uinfo->count = 1;
 640         uinfo->value.integer.min = min;
 641         uinfo->value.integer.max = max;
 642         return 0;
 643 }
 644
 645 #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(channel)                       \
 646 static int                                                              \
 647 omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
 648                                         struct snd_ctl_elem_value *uc)  \
 649 {                                                                       \
 650         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);            \
 651         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);    \
 652         struct soc_mixer_control *mc =                                  \
 653                 (struct soc_mixer_control *)kc->private_value;          \
 654         int max = mc->max;                                              \
 655         int min = mc->min;                                              \
 656         int val = uc->value.integer.value[0];                           \
 657                                                                         \
 658         if (val < min || val > max)                                     \
 659                 return -EINVAL;                                         \
 660                                                                         \
 661         /* OMAP McBSP implementation uses index values 0..4 */          \
 662         return omap_st_set_chgain(mcbsp, channel, val);                 \
 663 }
 664
 665 #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(channel)                       \
 666 static int                                                              \
 667 omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
 668                                         struct snd_ctl_elem_value *uc)  \
 669 {                                                                       \
 670         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);            \
 671         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);    \
 672         s16 chgain;                                                     \
 673                                                                         \
 674         if (omap_st_get_chgain(mcbsp, channel, &chgain))                \
 675                 return -EAGAIN;                                         \
 676                                                                         \
 677         uc->value.integer.value[0] = chgain;                            \
 678         return 0;                                                       \
 679 }
 680
 681 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(0)
 682 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(1)
 683 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(0)
 684 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(1)
 685
 686 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
 687                                 struct snd_ctl_elem_value *ucontrol)
 688 {
 689         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
 690         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 691         u8 value = ucontrol->value.integer.value[0];
 692
 693         if (value == omap_st_is_enabled(mcbsp))
 694                 return 0;
 695
 696         if (value)
 697                 omap_st_enable(mcbsp);
 698         else
 699                 omap_st_disable(mcbsp);
 700
 701         return 1;
 702 }
 703
 704 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
 705                                 struct snd_ctl_elem_value *ucontrol)
 706 {
 707         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
 708         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 709
 710         ucontrol->value.integer.value[0] = omap_st_is_enabled(mcbsp);
 711         return 0;
 712 }
 713
 714 static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
 715         SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
 716                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
 717         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
 718                                       -32768, 32767,
 719                                       omap_mcbsp_get_st_ch0_volume,
 720                                       omap_mcbsp_set_st_ch0_volume),
 721         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
 722                                       -32768, 32767,
 723                                       omap_mcbsp_get_st_ch1_volume,
 724                                       omap_mcbsp_set_st_ch1_volume),
 725 };
 726
 727 static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
 728         SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
 729                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
 730         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
 731                                       -32768, 32767,
 732                                       omap_mcbsp_get_st_ch0_volume,
 733                                       omap_mcbsp_set_st_ch0_volume),
 734         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
 735                                       -32768, 32767,
 736                                       omap_mcbsp_get_st_ch1_volume,
 737                                       omap_mcbsp_set_st_ch1_volume),
 738 };
 739
 740 int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd)
 741 {
 742         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 743         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 744
 745         if (!mcbsp->st_data)
 746                 return -ENODEV;
 747
 748         switch (cpu_dai->id) {
 749         case 2: /* McBSP 2 */
 750                 return snd_soc_add_dai_controls(cpu_dai,
 751                                         omap_mcbsp2_st_controls,
 752                                         ARRAY_SIZE(omap_mcbsp2_st_controls));
 753         case 3: /* McBSP 3 */
 754                 return snd_soc_add_dai_controls(cpu_dai,
 755                                         omap_mcbsp3_st_controls,
 756                                         ARRAY_SIZE(omap_mcbsp3_st_controls));
 757         default:
 758                 break;
 759         }
 760
 761         return -EINVAL;
 762 }
 763 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
 764
 765 static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
 766 {
 767         struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
 768         struct omap_mcbsp *mcbsp;
 769         int ret;
 770
 771         if (!pdata) {
 772                 dev_err(&pdev->dev, "missing platform data.\n");
 773                 return -EINVAL;
 774         }
 775         mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
 776         if (!mcbsp)
 777                 return -ENOMEM;
 778
 779         mcbsp->id = pdev->id;
 780         mcbsp->pdata = pdata;
 781         mcbsp->dev = &pdev->dev;
 782         platform_set_drvdata(pdev, mcbsp);
 783
 784         ret = omap_mcbsp_init(pdev);
 785         if (!ret)
 786                 return snd_soc_register_dai(&pdev->dev, &omap_mcbsp_dai);
 787
 788         return ret;
 789 }
 790
 791 static int __devexit asoc_mcbsp_remove(struct platform_device *pdev)
 792 {
 793         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 794
 795         snd_soc_unregister_dai(&pdev->dev);
 796
 797         if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 798                 mcbsp->pdata->ops->free(mcbsp->id);
 799
 800         omap_mcbsp_sysfs_remove(mcbsp);
 801
 802         clk_put(mcbsp->fclk);
 803
 804         platform_set_drvdata(pdev, NULL);
 805
 806         return 0;
 807 }
 808
 809 static struct platform_driver asoc_mcbsp_driver = {
 810         .driver = {
 811                         .name = "omap-mcbsp",
 812                         .owner = THIS_MODULE,
 813         },
 814
 815         .probe = asoc_mcbsp_probe,
 816         .remove = __devexit_p(asoc_mcbsp_remove),
 817 };
 818
 819 module_platform_driver(asoc_mcbsp_driver);
 820
 821 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
 822 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 823 MODULE_LICENSE("GPL");
 824 MODULE_ALIAS("platform:omap-mcbsp");