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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / mediatek / mt_soc_audio_v3 / mt_soc_afe_control.c
1 /*
2 * Copyright (C) 2007 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16 /*******************************************************************************
17 *
18 * Filename:
19 * ---------
20 * mt_sco_afe_control.c
21 *
22 * Project:
23 * --------
24 * MT6583 Audio Driver Kernel Function
25 *
26 * Description:
27 * ------------
28 * Audio register
29 *
30 * Author:
31 * -------
32 * Chipeng Chang
33 *
34 *------------------------------------------------------------------------------
35 * $Revision: #1 $
36 * $Modtime:$
37 * $Log:$
38 *
39 *
40 *******************************************************************************/
41
42
43 /*****************************************************************************
44 * C O M P I L E R F L A G S
45 *****************************************************************************/
46
47
48 /*****************************************************************************
49 * E X T E R N A L R E F E R E N C E S
50 *****************************************************************************/
51
52 #include "AudDrv_Common.h"
53 #include "AudDrv_Def.h"
54 #include "AudDrv_Afe.h"
55 #include "AudDrv_Ana.h"
56 #include "AudDrv_Clk.h"
57 #include "mt_soc_digital_type.h"
58 #include "AudDrv_Def.h"
59 #include "AudDrv_Kernel.h"
60 #include "mt_soc_afe_control.h"
61 #include "mt_soc_afe_connection.h"
62
63 #include <linux/kernel.h>
64 #include <linux/module.h>
65 #include <linux/init.h>
66 #include <linux/device.h>
67 #include <linux/slab.h>
68 #include <linux/fs.h>
69 #include <linux/completion.h>
70 #include <linux/mm.h>
71 #include <linux/delay.h>
72 #include <linux/interrupt.h>
73 #include <linux/dma-mapping.h>
74 #include <linux/vmalloc.h>
75 #include <linux/platform_device.h>
76 #include <linux/miscdevice.h>
77 #include <linux/wait.h>
78 #include <linux/spinlock.h>
79 #include <linux/sched.h>
80 #include <linux/wakelock.h>
81 #include <linux/semaphore.h>
82 #include <linux/jiffies.h>
83 #include <linux/proc_fs.h>
84 #include <linux/string.h>
85 #include <linux/mutex.h>
86 #include <linux/xlog.h>
87 #include <mach/irqs.h>
88 #include <asm/uaccess.h>
89 #include <asm/irq.h>
90 #include <asm/io.h>
91 #include <mach/mt_reg_base.h>
92 #include <asm/div64.h>
93 #include <linux/aee.h>
94 #include <mach/pmic_mt6325_sw.h>
95 #include <mach/upmu_common.h>
96 #include <mach/upmu_hw.h>
97 #include <mach/mt_gpio.h>
98 #include <mach/mt_typedefs.h>
99
100 #include <linux/clk.h>
101 #include <linux/delay.h>
102 #include <linux/gpio.h>
103 #include <linux/platform_device.h>
104 #include <linux/slab.h>
105 #include <sound/core.h>
106 #include <sound/soc.h>
107 #include <sound/soc-dapm.h>
108 #include <sound/pcm.h>
109 #include <sound/jack.h>
110 //#include <asm/mach-types.h>
111
112 #include <mach/mt_gpio.h>
113 #include <mach/mt_boot.h>
114 #include <cust_eint.h>
115 #include <cust_gpio_usage.h>
116 #include <mach/eint.h>
117 #include "AudDrv_Common.h"
118
119 static DEFINE_SPINLOCK(afe_control_lock);
120 static DEFINE_SPINLOCK(afe_sram_control_lock);
121 static DEFINE_SPINLOCK(afe_mem_lock);
122
123
124 // static variable
125 static bool AudioDaiBtStatus = false;
126 static bool AudioAdcI2SStatus = false;
127 static bool Audio2ndAdcI2SStatus = false;
128 static bool AudioMrgStatus = false;
129 static bool mAudioInit = false;
130 static bool mVOWStatus = false;
131 static unsigned int MCLKFS = 128;
132 static AudioDigtalI2S *AudioAdcI2S = NULL;
133 static AudioDigtalI2S *m2ndI2S = NULL; // input
134 static AudioDigtalI2S *m2ndI2Sout = NULL; // output
135
136 static AudioHdmi *mHDMIOutput = NULL;
137 static AudioMrgIf *mAudioMrg = NULL;
138 static AudioDigitalDAIBT *AudioDaiBt = NULL;
139
140 static AFE_MEM_CONTROL_T *AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_HDMI + 1] = {NULL};
141 static struct snd_dma_buffer *Audio_dma_buf[Soc_Aud_Digital_Block_MEM_HDMI + 1] = {NULL};
142
143 static AudioIrqMcuMode *mAudioMcuMode[Soc_Aud_IRQ_MCU_MODE_NUM_OF_IRQ_MODE] = {NULL};
144 static AudioMemIFAttribute *mAudioMEMIF[Soc_Aud_Digital_Block_NUM_OF_DIGITAL_BLOCK] = {NULL};
145
146 static AudioAfeRegCache mAudioRegCache;
147 static AudioSramManager mAudioSramManager;
148 const unsigned int AudioSramPlaybackFullSize = 1024 * 48;
149 const unsigned int AudioSramPlaybackPartialSize = 1024 * 32;
150 const unsigned int AudioDramPlaybackSize = 1024 * 48;
151 const size_t AudioSramCaptureSize = 1024 * 48;
152 const size_t AudioDramCaptureSize = 1024 * 48;
153 const size_t AudioInterruptLimiter = 100;
154
155
156 static bool mExternalModemStatus = false;
157
158 extern bool get_voice_bt_status(void);
159 extern bool get_voice_status(void);
160 extern void Auddrv_Read_Efuse_HPOffset(void);
161
162 // mutex lock
163 static DEFINE_MUTEX(afe_control_mutex);
164 static DEFINE_SPINLOCK(auddrv_dl1_lock);
165 static DEFINE_SPINLOCK(auddrv_ul1_lock);
166
167
168 static const uint16_t kSideToneCoefficientTable16k[] =
169 {
170 0x049C, 0x09E8, 0x09E0, 0x089C,
171 0xFF54, 0xF488, 0xEAFC, 0xEBAC,
172 0xfA40, 0x17AC, 0x3D1C, 0x6028,
173 0x7538
174 };
175
176 static const uint16_t kSideToneCoefficientTable32k[] =
177 {
178 0xff58, 0x0063, 0x0086, 0x00bf,
179 0x0100, 0x013d, 0x0169, 0x0178,
180 0x0160, 0x011c, 0x00aa, 0x0011,
181 0xff5d, 0xfea1, 0xfdf6, 0xfd75,
182 0xfd39, 0xfd5a, 0xfde8, 0xfeea,
183 0x005f, 0x0237, 0x0458, 0x069f,
184 0x08e2, 0x0af7, 0x0cb2, 0x0df0,
185 0x0e96
186 };
187
188 /*
189 * function implementation
190 */
191 static irqreturn_t AudDrv_IRQ_handler(int irq, void *dev_id);
192
193 static bool CheckSize(uint32 size)
194 {
195 if (size == 0)
196 {
197 printk("CheckSize size = 0\n");
198 return true;
199 }
200 return false;
201 }
202
203 void AfeControlMutexLock(void)
204 {
205 mutex_lock(&afe_control_mutex);
206 }
207
208 void AfeControlMutexUnLock(void)
209 {
210 mutex_unlock(&afe_control_mutex);
211 }
212
213 void AfeControlSramLock(void)
214 {
215 spin_lock(&afe_sram_control_lock);
216 }
217
218 void AfeControlSramUnLock(void)
219 {
220 spin_unlock(&afe_sram_control_lock);
221 }
222
223 #if 0
224 static unsigned long afecontrolMenflags = 0;
225 void AfeControlMemLock(void)
226 {
227 spin_lock_irqsave(&afe_mem_lock, afecontrolMenflags);
228 }
229
230 void AfeControlMemUnLock(void)
231 {
232 spin_unlock_irqrestore(&afe_mem_lock, afecontrolMenflags);
233 }
234 #endif
235
236 unsigned int GetSramState(void)
237 {
238 return mAudioSramManager.mMemoryState;
239 }
240
241 void SetSramState(unsigned int State)
242 {
243 printk("%s state= %d\n", __func__, State);
244 mAudioSramManager.mMemoryState |= State;
245 }
246
247 void ClearSramState(unsigned int State)
248 {
249 printk("%s state= %d\n", __func__, State);
250 mAudioSramManager.mMemoryState &= (~State);
251 }
252
253 unsigned int GetPLaybackSramFullSize(void)
254 {
255 return AudioSramPlaybackFullSize;
256 }
257
258 unsigned int GetPLaybackSramPartial(void)
259 {
260 return AudioSramPlaybackPartialSize;
261 }
262
263 unsigned int GetPLaybackDramSize(void)
264 {
265 return AudioSramCaptureSize;
266 }
267
268 size_t GetCaptureSramSize(void)
269 {
270 return AudioSramCaptureSize;
271 }
272
273 size_t GetCaptureDramSize(void)
274 {
275 return AudioDramCaptureSize;
276 }
277
278 // function get internal mode status.
279 bool get_internalmd_status(void)
280 {
281 bool ret = (get_voice_bt_status() || get_voice_status());
282 return (mExternalModemStatus == true) ? false : ret;
283 }
284
285 #if 0
286 void DumpMemifSubStream(void)
287 {
288 int i = 0;
289 //printk("+%s \n ", __func__);
290 for (i = 0 ; i <= Soc_Aud_Digital_Block_MEM_HDMI ; i++)
291 {
292 substreamList *head = AFE_Mem_Control_context[i]->substreamL;
293 while (head != NULL)
294 {
295 //printk("%s AFE_Mem_Control_context[%d] head = %p head->substream = %p \n ", __func__,i, head,head->substream);
296 head = head->next;
297 }
298 }
299 //printk("-%s \n ", __func__);
300 }
301 #endif
302
303
304 static void FillDatatoDlmemory(volatile unsigned int *memorypointer, unsigned int fillsize, unsigned short value)
305 {
306 int addr = 0;
307 unsigned int tempvalue = value;
308 tempvalue = tempvalue << 16;
309 tempvalue |= value;
310 // set memory to DC value
311 for (addr = 0; addr < (fillsize >> 2) ; addr++)
312 {
313 *memorypointer = tempvalue;
314 memorypointer++;
315 }
316 }
317
318 static struct snd_dma_buffer *Dl1_Playback_dma_buf = NULL;
319
320 static void SetDL1BufferwithBuf(void)
321 {
322 #define Dl1_MAX_BUFFER_SIZE (48*1024)
323
324 AudDrv_Allocate_mem_Buffer(NULL, Soc_Aud_Digital_Block_MEM_DL1, Dl1_MAX_BUFFER_SIZE);
325 Dl1_Playback_dma_buf = Get_Mem_Buffer(Soc_Aud_Digital_Block_MEM_DL1);
326 Afe_Set_Reg(AFE_DL1_BASE , Dl1_Playback_dma_buf->addr, 0xffffffff);
327 Afe_Set_Reg(AFE_DL1_END , Dl1_Playback_dma_buf->addr + (Dl1_MAX_BUFFER_SIZE - 1), 0xffffffff);
328 }
329
330
331 void OpenAfeDigitaldl1(bool bEnable)
332 {
333 volatile unsigned int *Sramdata;
334
335 if (bEnable == true)
336 {
337 SetDL1BufferwithBuf();
338 SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_16_BIT);
339 SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_16_BIT);
340 SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O03);
341 SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O04);
342 SetSampleRate(Soc_Aud_Digital_Block_MEM_I2S, 44100);
343 SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I05, Soc_Aud_InterConnectionOutput_O03);
344 SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I06, Soc_Aud_InterConnectionOutput_O04);
345 SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1, true);
346
347 Sramdata = (unsigned int *)(Dl1_Playback_dma_buf->area);
348 FillDatatoDlmemory(Sramdata , Dl1_Playback_dma_buf->bytes , 0);
349 msleep(5);
350
351 if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC) == false)
352 {
353 SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true);
354 SetI2SDacOut(44100, false, Soc_Aud_I2S_WLEN_WLEN_16BITS);
355 SetI2SDacEnable(true);
356 }
357 else
358 {
359 SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true);
360 }
361 EnableAfe(true);
362 }
363 else
364 {
365 SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, false);
366 SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1, false);
367 if (GetI2SDacEnable() == false)
368 {
369 SetI2SDacEnable(false);
370 }
371 EnableAfe(false);
372 }
373 }
374
375 void SetExternalModemStatus(const bool bEnable)
376 {
377 printk("%s(), mExternalModemStatus : %d => %d\n", __func__, mExternalModemStatus, bEnable);
378 mExternalModemStatus = bEnable;
379 }
380
381
382 /*****************************************************************************
383 * FUNCTION
384 * InitAfeControl ,ResetAfeControl
385 *
386 * DESCRIPTION
387 * afe init function
388 *
389 *****************************************************************************
390 */
391
392 bool InitAfeControl(void)
393 {
394 int i = 0;
395 printk("InitAfeControl \n");
396 // first time to init , reg init.
397 Auddrv_Reg_map();
398 AudDrv_Clk_Power_On();
399 Auddrv_Bus_Init();
400
401 Auddrv_Read_Efuse_HPOffset();
402
403 AfeControlMutexLock();
404 // allocate memory for pointers
405 if (mAudioInit == false)
406 {
407 mAudioInit = true;
408 mAudioMrg = kzalloc(sizeof(AudioMrgIf), GFP_KERNEL);
409 AudioDaiBt = kzalloc(sizeof(AudioDigitalDAIBT), GFP_KERNEL);
410 AudioAdcI2S = kzalloc(sizeof(AudioDigtalI2S), GFP_KERNEL);
411 m2ndI2S = kzalloc(sizeof(AudioDigtalI2S), GFP_KERNEL);
412 m2ndI2Sout = kzalloc(sizeof(AudioDigtalI2S), GFP_KERNEL);
413 mHDMIOutput = kzalloc(sizeof(AudioHdmi), GFP_KERNEL);
414 for (i = 0; i < Soc_Aud_IRQ_MCU_MODE_NUM_OF_IRQ_MODE ; i ++)
415 {
416 mAudioMcuMode[i] = kzalloc(sizeof(AudioIrqMcuMode) , GFP_KERNEL);
417 }
418 for (i = 0; i < Soc_Aud_Digital_Block_NUM_OF_DIGITAL_BLOCK ; i ++)
419 {
420 mAudioMEMIF[i] = kzalloc(sizeof(AudioMemIFAttribute), GFP_KERNEL);
421 }
422 for (i = 0; i <= Soc_Aud_Digital_Block_MEM_HDMI ; i ++)
423 {
424 AFE_Mem_Control_context[i] = kzalloc(sizeof(AFE_MEM_CONTROL_T), GFP_KERNEL);
425 AFE_Mem_Control_context[i]->substreamL = NULL;
426 }
427 for (i = 0; i <= Soc_Aud_Digital_Block_MEM_HDMI ; i ++)
428 {
429 Audio_dma_buf[i] = kzalloc(sizeof(Audio_dma_buf), GFP_KERNEL);
430 }
431 }
432 AudioDaiBtStatus = false;
433 AudioAdcI2SStatus = false;
434 Audio2ndAdcI2SStatus = false;
435 AudioMrgStatus = false;
436 memset((void *)&mAudioSramManager, 0, sizeof(AudioSramManager));
437
438 mAudioMrg->Mrg_I2S_SampleRate = SampleRateTransform(44100);
439
440 for (i = AUDIO_APLL1_DIV0 ; i <= AUDIO_APLL2_DIV5 ; i++)
441 {
442 EnableI2SDivPower(i , false);
443 }
444
445 // set APLL clock setting
446 AfeControlMutexUnLock();
447 return true;
448 }
449
450 bool ResetAfeControl(void)
451 {
452 int i = 0;
453 printk("ResetAfeControl \n");
454 AfeControlMutexLock();
455 mAudioInit = false;
456 memset((void *)(mAudioMrg), 0, sizeof(AudioMrgIf));
457 memset((void *)(AudioDaiBt), 0, sizeof(AudioDigitalDAIBT));
458 for (i = 0; i < Soc_Aud_IRQ_MCU_MODE_NUM_OF_IRQ_MODE ; i ++)
459 {
460 memset((void *)(mAudioMcuMode[i]), 0, sizeof(AudioIrqMcuMode));
461 }
462 for (i = 0; i < Soc_Aud_Digital_Block_NUM_OF_DIGITAL_BLOCK ; i ++)
463 {
464 memset((void *)(mAudioMEMIF[i]), 0, sizeof(AudioMemIFAttribute));
465 }
466 for (i = 0; i < (Soc_Aud_Digital_Block_MEM_HDMI + 1) ; i ++)
467 {
468 memset((void *)(AFE_Mem_Control_context[i]), 0, sizeof(AFE_MEM_CONTROL_T));
469 }
470 AfeControlMutexUnLock();
471 return true;
472 }
473
474
475 /*****************************************************************************
476 * FUNCTION
477 * Register_aud_irq
478 *
479 * DESCRIPTION
480 * IRQ handler
481 *
482 *****************************************************************************
483 */
484
485 bool Register_Aud_Irq(void *dev, uint32 afe_irq_number)
486 {
487 int ret;
488 #ifdef CONFIG_OF
489 ret = request_irq(afe_irq_number, AudDrv_IRQ_handler, IRQF_TRIGGER_LOW, "Afe_ISR_Handle", dev);
490 if (ret)
491 {
492 printk("Register_Aud_Irq AFE IRQ register fail!!!\n");
493 }
494 #else
495 printk("%s dev name =%s \n", __func__, dev_name(dev));
496 ret = request_irq(MT6735_AFE_MCU_IRQ_LINE, AudDrv_IRQ_handler, IRQF_TRIGGER_LOW/*IRQF_TRIGGER_FALLING*/, "Afe_ISR_Handle", dev);
497 #endif
498 return ret;
499 }
500
501 static int irqcount = 0;
502 /*****************************************************************************
503 * FUNCTION
504 * AudDrv_IRQ_handler / AudDrv_magic_tasklet
505 *
506 * DESCRIPTION
507 * IRQ handler
508 *
509 *****************************************************************************
510 */
511 irqreturn_t AudDrv_IRQ_handler(int irq, void *dev_id)
512 {
513 //unsigned long flags;
514 kal_uint32 volatile u4RegValue;
515 kal_uint32 volatile u4tmpValue;
516 kal_uint32 volatile u4tmpValue1;
517 kal_uint32 volatile u4tmpValue2;
518
519 AudDrv_Clk_On();
520 u4RegValue = Afe_Get_Reg(AFE_IRQ_MCU_STATUS);
521 u4RegValue &= 0xff;
522
523 u4tmpValue = Afe_Get_Reg(AFE_IRQ_MCU_EN);
524 u4tmpValue &= 0xff;
525
526 u4tmpValue1 = Afe_Get_Reg(AFE_IRQ_CNT5);
527 u4tmpValue1 &= 0x0003ffff;
528
529 u4tmpValue2 = Afe_Get_Reg(AFE_IRQ_DEBUG);
530 u4tmpValue2 &= 0x0003ffff;
531
532 // here is error handle , for interrupt is trigger but not status , clear all interrupt with bit 6
533 if (u4RegValue == 0)
534 {
535 printk("u4RegValue == 0 irqcount =0\n");
536 Afe_Set_Reg(AFE_IRQ_MCU_CLR, 1 << 6 , 0xff);
537 Afe_Set_Reg(AFE_IRQ_MCU_CLR, 1 , 0xff);
538 Afe_Set_Reg(AFE_IRQ_MCU_CLR, 1 << 1 , 0xff);
539 Afe_Set_Reg(AFE_IRQ_MCU_CLR, 1 << 2 , 0xff);
540 Afe_Set_Reg(AFE_IRQ_MCU_CLR, 1 << 3 , 0xff);
541 Afe_Set_Reg(AFE_IRQ_MCU_CLR, 1 << 4 , 0xff);
542 Afe_Set_Reg(AFE_IRQ_MCU_CLR, 1 << 5 , 0xff);
543 irqcount++;
544 if (irqcount > AudioInterruptLimiter)
545 {
546 SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, false);
547 SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, false);
548 irqcount = 0;
549 }
550 goto AudDrv_IRQ_handler_exit;
551 }
552
553 if (u4RegValue & INTERRUPT_IRQ1_MCU)
554 {
555 if (mAudioMEMIF[Soc_Aud_Digital_Block_MEM_DL1]->mState == true)
556 {
557 Auddrv_DL1_Interrupt_Handler();
558 }
559 }
560 if (u4RegValue & INTERRUPT_IRQ2_MCU)
561 {
562 if (mAudioMEMIF[Soc_Aud_Digital_Block_MEM_VUL]->mState == true)
563 {
564 Auddrv_UL1_Interrupt_Handler();
565 }
566 if (mAudioMEMIF[Soc_Aud_Digital_Block_MEM_AWB]->mState == true)
567 {
568 Auddrv_AWB_Interrupt_Handler();
569 }
570 if (mAudioMEMIF[Soc_Aud_Digital_Block_MEM_DAI]->mState == true)
571 {
572 Auddrv_DAI_Interrupt_Handler();
573 }
574 if (mAudioMEMIF[Soc_Aud_Digital_Block_MEM_VUL_DATA2]->mState == true)
575 {
576 Auddrv_UL2_Interrupt_Handler();
577 }
578 }
579 if (u4RegValue & INTERRUPT_IRQ3_MCU)
580 {
581 }
582 if (u4RegValue & INTERRUPT_IRQ4_MCU)
583 {
584 }
585 if (u4RegValue & INTERRUPT_IRQ5_MCU)
586 {
587 Auddrv_HDMI_Interrupt_Handler();
588 }
589 // clear irq
590 Afe_Set_Reg(AFE_IRQ_MCU_CLR, u4RegValue , 0xff);
591 AudDrv_IRQ_handler_exit:
592 AudDrv_Clk_Off();
593 return IRQ_HANDLED;
594 }
595
596 uint32 GetApllbySampleRate(uint32 SampleRate)
597 {
598 if (SampleRate == 176400 || SampleRate == 88200 || SampleRate == 44100 || SampleRate == 22050 || SampleRate == 11025)
599 {
600 return Soc_Aud_APLL1;
601 }
602 else
603 {
604 return Soc_Aud_APLL2;
605 }
606 }
607
608 void SetckSel(uint32 I2snum, uint32 SampleRate)
609 {
610 uint32 ApllSource = GetApllbySampleRate(SampleRate);
611 switch (I2snum)
612 {
613 case Soc_Aud_I2S0:
614 Afe_Set_Reg(AUDIO_CLK_AUDDIV_0, ApllSource << 4, 1 << 4);
615 break;
616 case Soc_Aud_I2S1:
617 Afe_Set_Reg(AUDIO_CLK_AUDDIV_0, ApllSource << 5, 1 << 5);
618 break;
619 case Soc_Aud_I2S2:
620 Afe_Set_Reg(AUDIO_CLK_AUDDIV_0, ApllSource << 6, 1 << 6);
621 break;
622 case Soc_Aud_I2S3:
623 Afe_Set_Reg(AUDIO_CLK_AUDDIV_0, ApllSource << 7, 1 << 7);
624 break;
625 }
626 printk("%s I2snum = %d ApllSource = %d \n", __func__, I2snum, ApllSource);
627
628 }
629
630 uint32 SetCLkMclk(uint32 I2snum, uint32 SampleRate)
631 {
632 uint32 I2S_APll = 0;
633 uint32 I2s_ck_div = 0;
634 if (GetApllbySampleRate(SampleRate) == Soc_Aud_APLL1)
635 {
636 I2S_APll = 22579200 * 8;
637 }
638 else
639 {
640 I2S_APll = 24576000 * 8 ;
641 }
642
643 SetckSel(I2snum, SampleRate); // set I2Sx mck source
644
645 switch (I2snum)
646 {
647 case Soc_Aud_I2S0:
648 I2s_ck_div = (I2S_APll / MCLKFS / SampleRate) - 1;
649 Afe_Set_Reg(AUDIO_CLK_AUDDIV_1, I2s_ck_div, 0x000000ff);
650 Afe_Set_Reg(AUDIO_CLK_AUDDIV_2, I2s_ck_div, 0x000000ff);
651 break;
652 case Soc_Aud_I2S1:
653 I2s_ck_div = (I2S_APll / MCLKFS / SampleRate) - 1;
654 Afe_Set_Reg(AUDIO_CLK_AUDDIV_1, I2s_ck_div << 8, 0x0000ff00);
655 Afe_Set_Reg(AUDIO_CLK_AUDDIV_2, I2s_ck_div << 8, 0x0000ff00);
656 break;
657 case Soc_Aud_I2S2:
658 I2s_ck_div = (I2S_APll / MCLKFS / SampleRate) - 1;
659 Afe_Set_Reg(AUDIO_CLK_AUDDIV_1, I2s_ck_div << 16, 0x00ff0000);
660 Afe_Set_Reg(AUDIO_CLK_AUDDIV_2, I2s_ck_div << 16, 0x00ff0000);
661 break;
662 case Soc_Aud_I2S3:
663 I2s_ck_div = (I2S_APll / MCLKFS / SampleRate) - 1;
664 Afe_Set_Reg(AUDIO_CLK_AUDDIV_1, I2s_ck_div << 24, 0xff000000);
665 Afe_Set_Reg(AUDIO_CLK_AUDDIV_2, I2s_ck_div << 24, 0xff000000);
666 break;
667 }
668 printk("%s I2snum = %d I2s_ck_div = %d I2S_APll = %d\n", __func__, I2snum, I2s_ck_div, I2S_APll);
669 return I2s_ck_div;
670 }
671
672 void SetCLkBclk(uint32 MckDiv, uint32 SampleRate, uint32 Channels , uint32 Wlength)
673 {
674 uint32 I2S_APll = 0;
675 uint32 I2S_Bclk = 0;
676 uint32 I2s_Bck_div = 0;
677 printk("%s MckDiv = %dv SampleRate = %d Channels = %d Wlength = %d\n", __func__, MckDiv, SampleRate, Channels, Wlength);
678 MckDiv++;
679
680 if (GetApllbySampleRate(SampleRate) == Soc_Aud_APLL1)
681 {
682 I2S_APll = 22579200 * 8;
683 }
684 else
685 {
686 I2S_APll = 24576000 * 8 ;
687 }
688 I2S_Bclk = SampleRate * Channels * (Wlength + 1) * 16;
689 I2s_Bck_div = (I2S_APll / MckDiv) / I2S_Bclk;
690
691 printk("%s I2S_APll = %dv I2S_Bclk = %d I2s_Bck_div = %d\n", __func__, I2S_APll, I2S_Bclk, I2s_Bck_div);
692 I2s_Bck_div--;
693 // bclk dived is not in AUDDIV_3
694 //Afe_Set_Reg(AUDIO_CLK_AUDDIV_3, I2s_Bck_div, 0x0000000f);
695 //Afe_Set_Reg(AUDIO_CLK_AUDDIV_3, I2s_Bck_div << 4, 0x000000f0);
696 }
697
698
699 void EnableI2SDivPower(uint32 Diveder_name, bool bEnable)
700 {
701 if (bEnable)
702 {
703 //AUDIO_APLL1_DIV0
704 Afe_Set_Reg(AUDIO_CLK_AUDDIV_3, 0 << Diveder_name, 1 << Diveder_name);
705 }
706 else
707 {
708 Afe_Set_Reg(AUDIO_CLK_AUDDIV_3, 1 << Diveder_name , 1 << Diveder_name);
709 }
710 }
711
712 void EnableApll1(bool bEnable)
713 {
714 if (bEnable)
715 {
716 Afe_Set_Reg(AUDIO_CLK_AUDDIV_0, 0x3, 0x3);
717 Afe_Set_Reg(AUDIO_CLK_AUDDIV_0, 0x07000000, 0x0f000000);
718 AudDrv_APLL22M_Clk_On();
719 Afe_Set_Reg(AUDIO_CLK_AUDDIV_0, 0x0, 0x3);
720 SetClkCfg(AUDIO_CLK_CFG_6, 0x00010000, 0x00810000);
721 }
722 else
723 {
724 Afe_Set_Reg(AUDIO_CLK_AUDDIV_0, 0x07000000, 0x0f000000);
725 AudDrv_APLL22M_Clk_Off();
726 Afe_Set_Reg(AUDIO_CLK_AUDDIV_0, 0x3, 0x3);
727 SetClkCfg(AUDIO_CLK_CFG_6, 0x00810000, 0x00810000);
728 }
729 }
730
731 void EnableApll2(bool bEnable)
732 {
733 if (bEnable)
734 {
735 Afe_Set_Reg(AUDIO_CLK_AUDDIV_0, 0xc, 0xc);
736 Afe_Set_Reg(AUDIO_CLK_AUDDIV_0, 0x70000000, 0xf0000000);
737 AudDrv_APLL24M_Clk_On();
738 Afe_Set_Reg(AUDIO_CLK_AUDDIV_0, 0x0, 0xc);
739 SetClkCfg(AUDIO_CLK_CFG_6, 0x01000000, 0x81000000);
740 }
741 else
742 {
743 SetClkCfg(AUDIO_CLK_CFG_7, 0x00000080, 0x00000083);
744 AudDrv_APLL24M_Clk_Off();
745 Afe_Set_Reg(AUDIO_CLK_AUDDIV_0, 0xc, 0xc);
746 SetClkCfg(AUDIO_CLK_CFG_6, 0x81000000, 0x81000000);
747 }
748 }
749
750 static bool CheckMemIfEnable(void)
751 {
752 int i = 0;
753 for (i = 0 ; i < Soc_Aud_Digital_Block_NUM_OF_DIGITAL_BLOCK ; i++)
754 {
755 if ((mAudioMEMIF[i]->mState) == true)
756 {
757 //printk("CheckMemIfEnable == true\n");
758 return true;
759 }
760 }
761 //printk("CheckMemIfEnable == false\n");
762 return false;
763 }
764
765
766 // record VOW status for AFE GPIO control
767 void SetVOWStatus(bool bEnable)
768 {
769 unsigned long flags;
770 if (mVOWStatus != bEnable)
771 {
772 spin_lock_irqsave(&afe_control_lock, flags);
773 mVOWStatus = bEnable;
774 printk("SetVOWStatus, mVOWStatus= %d\n", mVOWStatus);
775 spin_unlock_irqrestore(&afe_control_lock, flags);
776 }
777 }
778
779 /*****************************************************************************
780 * FUNCTION
781 * Auddrv_Reg_map
782 *
783 * DESCRIPTION
784 * Auddrv_Reg_map
785 *
786 *****************************************************************************
787 */
788 #ifdef CONFIG_OF
789 static unsigned int pin_audclk, pin_audmiso, pin_audmosi;
790 static unsigned int pin_mode_audclk, pin_mode_audmosi, pin_mode_audmiso;
791 #endif
792 void EnableAfe(bool bEnable)
793 {
794 unsigned long flags;
795 bool MemEnable = false;
796 #ifdef CONFIG_OF
797 int ret;
798 ret = GetGPIO_Info(1, &pin_audclk, &pin_mode_audclk);
799 if (ret < 0)
800 {
801 printk("EnableAfe GetGPIO_Info FAIL1!!! \n");
802 return;
803 }
804
805 ret = GetGPIO_Info(2, &pin_audmiso, &pin_mode_audmiso);
806 if (ret < 0)
807 {
808 printk("EnableAfe GetGPIO_Info FAIL2!!! \n");
809 return;
810 }
811
812 ret = GetGPIO_Info(3, &pin_audmosi, &pin_mode_audmosi);
813 if (ret < 0)
814 {
815 printk("EnableAfe GetGPIO_Info FAIL3!!! \n");
816 return;
817 }
818 #endif
819 spin_lock_irqsave(&afe_control_lock, flags);
820 MemEnable = CheckMemIfEnable();
821 if (false == bEnable && false == MemEnable)
822 {
823 Afe_Set_Reg(AFE_DAC_CON0, 0x0, 0x0);
824 #ifndef FPGA_EARLY_PORTING
825 #ifdef CONFIG_OF
826 mt_set_gpio_mode(pin_audclk, GPIO_MODE_00); //GPIO24, AUD_CLK_MOSI.
827 if (mVOWStatus != true) //this GPIO only use in record and VOW
828 {
829 mt_set_gpio_mode(pin_audmiso, GPIO_MODE_00); //GPIO25, AUD_DAT_MISO
830 }
831 mt_set_gpio_mode(pin_audmosi, GPIO_MODE_00); //GPIO26, AUD_DAT_MOSI
832 #else
833 mt_set_gpio_mode(GPIO_AUD_CLK_MOSI_PIN, GPIO_MODE_00); //GPIO24, AUD_CLK_MOSI.
834 if (mVOWStatus != true) //this GPIO only use in record and VOW
835 {
836 mt_set_gpio_mode(GPIO_AUD_DAT_MISO_PIN, GPIO_MODE_00); //GPIO25, AUD_DAT_MISO
837 }
838 mt_set_gpio_mode(GPIO_AUD_DAT_MOSI_PIN, GPIO_MODE_00); //GPIO26, AUD_DAT_MOSI
839 #endif
840 #endif
841 }
842 else if (true == bEnable && true == MemEnable)
843 {
844 #ifndef FPGA_EARLY_PORTING
845 #ifdef CONFIG_OF
846 mt_set_gpio_mode(pin_audclk, GPIO_MODE_01); //GPIO24, AUD_CLK_MOSI
847 if (mVOWStatus != true) //this GPIO only use in record and VOW
848 {
849 mt_set_gpio_mode(pin_audmiso, GPIO_MODE_01); //GPIO25, AUD_DAT_MISO
850 }
851 mt_set_gpio_mode(pin_audmosi, GPIO_MODE_01); //GPIO26, AUD_DAT_MOSI
852 #else
853 mt_set_gpio_mode(GPIO_AUD_CLK_MOSI_PIN, GPIO_MODE_01); //GPIO24, AUD_CLK_MOSI
854 if (mVOWStatus != true) //this GPIO only use in record and VOW
855 {
856 mt_set_gpio_mode(GPIO_AUD_DAT_MISO_PIN, GPIO_MODE_01); //GPIO25, AUD_DAT_MISO
857 }
858 mt_set_gpio_mode(GPIO_AUD_DAT_MOSI_PIN, GPIO_MODE_01); //GPIO26, AUD_DAT_MOSI
859 #endif
860 #endif
861 Afe_Set_Reg(AFE_DAC_CON0, 0x1, 0x1);
862 }
863 spin_unlock_irqrestore(&afe_control_lock, flags);
864 }
865
866 uint32 SampleRateTransform(uint32 SampleRate)
867 {
868 switch (SampleRate)
869 {
870 case 8000:
871 return Soc_Aud_I2S_SAMPLERATE_I2S_8K;
872 case 11025:
873 return Soc_Aud_I2S_SAMPLERATE_I2S_11K;
874 case 12000:
875 return Soc_Aud_I2S_SAMPLERATE_I2S_12K;
876 case 16000:
877 return Soc_Aud_I2S_SAMPLERATE_I2S_16K;
878 case 22050:
879 return Soc_Aud_I2S_SAMPLERATE_I2S_22K;
880 case 24000:
881 return Soc_Aud_I2S_SAMPLERATE_I2S_24K;
882 case 32000:
883 return Soc_Aud_I2S_SAMPLERATE_I2S_32K;
884 case 44100:
885 return Soc_Aud_I2S_SAMPLERATE_I2S_44K;
886 case 48000:
887 return Soc_Aud_I2S_SAMPLERATE_I2S_48K;
888 case 88000:
889 return Soc_Aud_I2S_SAMPLERATE_I2S_88K;
890 case 96000:
891 return Soc_Aud_I2S_SAMPLERATE_I2S_96K;
892 case 174000:
893 return Soc_Aud_I2S_SAMPLERATE_I2S_174K;
894 case 192000:
895 return Soc_Aud_I2S_SAMPLERATE_I2S_192K;
896 case 260000:
897 return Soc_Aud_I2S_SAMPLERATE_I2S_260K;
898 default:
899 break;
900 }
901 return Soc_Aud_I2S_SAMPLERATE_I2S_44K;
902 }
903
904 bool SetSampleRate(uint32 Aud_block, uint32 SampleRate)
905 {
906 //printk("%s Aud_block = %d SampleRate = %d\n", __func__, Aud_block, SampleRate);
907 SampleRate = SampleRateTransform(SampleRate);
908 switch (Aud_block)
909 {
910 case Soc_Aud_Digital_Block_MEM_DL1:
911 {
912 Afe_Set_Reg(AFE_DAC_CON1, SampleRate , 0x0000000f);
913 break;
914 }
915 case Soc_Aud_Digital_Block_MEM_DL2:
916 {
917 Afe_Set_Reg(AFE_DAC_CON1, SampleRate << 4 , 0x000000f0);
918 break;
919 }
920 case Soc_Aud_Digital_Block_MEM_I2S:
921 {
922 Afe_Set_Reg(AFE_DAC_CON1, SampleRate << 8 , 0x00000f00);
923 break;
924 }
925 case Soc_Aud_Digital_Block_MEM_AWB:
926 {
927 Afe_Set_Reg(AFE_DAC_CON1, SampleRate << 12, 0x0000f000);
928 break;
929 }
930 case Soc_Aud_Digital_Block_MEM_VUL:
931 {
932 Afe_Set_Reg(AFE_DAC_CON1, SampleRate << 16, 0x000f0000);
933 break;
934 }
935 case Soc_Aud_Digital_Block_MEM_DAI:
936 {
937 if (SampleRate == Soc_Aud_I2S_SAMPLERATE_I2S_8K)
938 {
939 Afe_Set_Reg(AFE_DAC_CON0, 0 << 24 , 3 << 24);
940 }
941 else if (SampleRate == Soc_Aud_I2S_SAMPLERATE_I2S_16K)
942 {
943 Afe_Set_Reg(AFE_DAC_CON0, 1 << 24 , 3 << 24);
944 }
945 else if (SampleRate == Soc_Aud_I2S_SAMPLERATE_I2S_32K)
946 {
947 Afe_Set_Reg(AFE_DAC_CON0, 2 << 24 , 3 << 24);
948 }
949 else
950 {
951 return false;
952 }
953 break;
954 }
955 case Soc_Aud_Digital_Block_MEM_MOD_DAI:
956 {
957 if (SampleRate == Soc_Aud_I2S_SAMPLERATE_I2S_8K)
958 {
959 Afe_Set_Reg(AFE_DAC_CON1, 0 << 30, 3 << 30);
960 }
961 else if (SampleRate == Soc_Aud_I2S_SAMPLERATE_I2S_16K)
962 {
963 Afe_Set_Reg(AFE_DAC_CON1, 1 << 30, 3 << 30);
964 }
965 else
966 {
967 return false;
968 }
969 break;
970 }
971 case Soc_Aud_Digital_Block_MEM_VUL_DATA2:
972 {
973 Afe_Set_Reg(AFE_DAC_CON0, SampleRate << 20, 0x00f00000);
974 break;
975 }
976 return true;
977 }
978 return false;
979 }
980
981 bool SetChannels(uint32 Memory_Interface, uint32 channel)
982 {
983 const bool bMono = (channel == 1) ? true : false;
984
985 //printk("SetChannels Memory_Interface = %d channels = %d\n", Memory_Interface, channel);
986
987 switch (Memory_Interface)
988 {
989 case Soc_Aud_Digital_Block_MEM_DL1:
990 {
991 Afe_Set_Reg(AFE_DAC_CON1, bMono << 21, 1 << 21);
992 break;
993 }
994 case Soc_Aud_Digital_Block_MEM_AWB:
995 {
996 Afe_Set_Reg(AFE_DAC_CON1, bMono << 24, 1 << 24);
997 break;
998 }
999 case Soc_Aud_Digital_Block_MEM_VUL:
1000 {
1001 Afe_Set_Reg(AFE_DAC_CON1, bMono << 27, 1 << 27);
1002 break;
1003 }
1004 case Soc_Aud_Digital_Block_MEM_VUL_DATA2:
1005 {
1006 Afe_Set_Reg(AFE_DAC_CON0, bMono << 10, 1 << 10);
1007 break;
1008 }
1009 default:
1010 printk("SetChannels Memory_Interface = %d, channel = %d, bMono = %d\n", Memory_Interface, channel, bMono);
1011 return false;
1012 }
1013 return true;
1014 }
1015
1016
1017 bool Set2ndI2SOutAttribute(uint32_t sampleRate)
1018 {
1019 printk("+%s(), sampleRate = %d\n", __FUNCTION__, sampleRate);
1020 m2ndI2Sout->mLR_SWAP = Soc_Aud_LR_SWAP_NO_SWAP;
1021 m2ndI2Sout->mI2S_SLAVE = Soc_Aud_I2S_SRC_MASTER_MODE;
1022 m2ndI2Sout->mINV_LRCK = Soc_Aud_INV_LRCK_NO_INVERSE;
1023 m2ndI2Sout->mI2S_FMT = Soc_Aud_I2S_FORMAT_I2S;
1024 m2ndI2Sout->mI2S_WLEN = Soc_Aud_I2S_WLEN_WLEN_16BITS;
1025 m2ndI2Sout->mI2S_HDEN = Soc_Aud_NORMAL_CLOCK;
1026 m2ndI2Sout->mI2S_SAMPLERATE = sampleRate;
1027 Set2ndI2SOut(m2ndI2Sout);
1028 return true;
1029 }
1030
1031 bool Set2ndI2SOut(AudioDigtalI2S *DigtalI2S)
1032 {
1033 uint32 u32AudioI2S = 0;
1034 memcpy((void *)m2ndI2Sout, (void *)DigtalI2S, sizeof(AudioDigtalI2S));
1035 u32AudioI2S = SampleRateTransform(m2ndI2Sout->mI2S_SAMPLERATE) << 8;
1036 u32AudioI2S |= m2ndI2Sout->mLR_SWAP << 31;
1037 u32AudioI2S |= m2ndI2Sout->mI2S_HDEN << 12;
1038 u32AudioI2S |= m2ndI2Sout->mINV_LRCK << 5;
1039 u32AudioI2S |= m2ndI2Sout->mI2S_FMT << 3;
1040 u32AudioI2S |= m2ndI2Sout->mI2S_WLEN << 1;
1041 Afe_Set_Reg(AFE_I2S_CON3, u32AudioI2S, AFE_MASK_ALL);
1042 return true;
1043 }
1044
1045 bool Set2ndI2SOutEnable(bool benable)
1046 {
1047 if (benable)
1048 {
1049 Afe_Set_Reg(AFE_I2S_CON3, 0x1, 0x1);
1050 }
1051 else
1052 {
1053 Afe_Set_Reg(AFE_I2S_CON3, 0x0, 0x1);
1054 }
1055 return true;
1056 }
1057
1058 bool SetDaiBt(AudioDigitalDAIBT *mAudioDaiBt)
1059 {
1060 AudioDaiBt->mBT_LEN = mAudioDaiBt->mBT_LEN;
1061 AudioDaiBt->mUSE_MRGIF_INPUT = mAudioDaiBt->mUSE_MRGIF_INPUT;
1062 AudioDaiBt->mDAI_BT_MODE = mAudioDaiBt->mDAI_BT_MODE;
1063 AudioDaiBt->mDAI_DEL = mAudioDaiBt->mDAI_DEL;
1064 AudioDaiBt->mBT_LEN = mAudioDaiBt->mBT_LEN;
1065 AudioDaiBt->mDATA_RDY = mAudioDaiBt->mDATA_RDY;
1066 AudioDaiBt->mBT_SYNC = mAudioDaiBt->mBT_SYNC;
1067 return true;
1068 }
1069
1070 bool SetDaiBtEnable(bool bEanble)
1071 {
1072 printk("%s bEanble = %d\n", __func__, bEanble);
1073 if (bEanble == true) // turn on dai bt
1074 {
1075 Afe_Set_Reg(AFE_DAIBT_CON0, AudioDaiBt->mDAI_BT_MODE << 9, 0x1 << 9);
1076 if (mAudioMrg->MrgIf_En == true)
1077 {
1078 Afe_Set_Reg(AFE_DAIBT_CON0, 0x1 << 12, 0x1 << 12); // use merge
1079 Afe_Set_Reg(AFE_DAIBT_CON0, 0x1 << 3, 0x1 << 3); // data ready
1080 Afe_Set_Reg(AFE_DAIBT_CON0, 0x3, 0x3); //Turn on DAIBT
1081 }
1082 else // turn on merge and daiBT
1083 {
1084 Afe_Set_Reg(AFE_MRGIF_CON, mAudioMrg->Mrg_I2S_SampleRate << 20, 0xF00000); // set Mrg_I2S Samping Rate
1085 Afe_Set_Reg(AFE_MRGIF_CON, 1 << 16, 1 << 16); // set Mrg_I2S enable
1086 Afe_Set_Reg(AFE_MRGIF_CON, 1, 0x1); // Turn on Merge Interface
1087 udelay(100);
1088 Afe_Set_Reg(AFE_DAIBT_CON0, 0x1 << 12, 0x1 << 12); // use merge
1089 Afe_Set_Reg(AFE_DAIBT_CON0, 0x1 << 3, 0x1 << 3); // data ready
1090 Afe_Set_Reg(AFE_DAIBT_CON0, 0x3, 0x3); //Turn on DAIBT
1091 }
1092 AudioDaiBt->mBT_ON = true;
1093 AudioDaiBt->mDAIBT_ON = true;
1094 mAudioMrg->MrgIf_En = true;
1095 }
1096 else
1097 {
1098 if (mAudioMrg->Mergeif_I2S_Enable == true)
1099 {
1100 Afe_Set_Reg(AFE_DAIBT_CON0, 0, 0x3); //Turn off DAIBT
1101 }
1102 else
1103 {
1104 Afe_Set_Reg(AFE_DAIBT_CON0, 0, 0x3); //Turn on DAIBT
1105 udelay(100);
1106 Afe_Set_Reg(AFE_MRGIF_CON, 0 << 16, 1 << 16); // set Mrg_I2S enable
1107 Afe_Set_Reg(AFE_MRGIF_CON, 0, 0x1); // Turn on Merge Interface
1108 mAudioMrg->MrgIf_En = false;
1109 }
1110 AudioDaiBt->mBT_ON = false;
1111 AudioDaiBt->mDAIBT_ON = false;
1112 }
1113 return true;
1114 }
1115
1116 bool GetMrgI2SEnable()
1117 {
1118 return mAudioMEMIF[Soc_Aud_Digital_Block_MRG_I2S_OUT]->mState ;
1119 }
1120
1121 bool SetMrgI2SEnable(bool bEnable, unsigned int sampleRate)
1122 {
1123 printk("%s bEnable = %d\n", __func__, bEnable);
1124 if (bEnable == true)
1125 {
1126 // To enable MrgI2S
1127 if (mAudioMrg->MrgIf_En == true)
1128 {
1129 // Merge Interface already turn on.
1130 //if sample Rate change, then it need to restart with new setting; else do nothing.
1131 if (mAudioMrg->Mrg_I2S_SampleRate != SampleRateTransform(sampleRate))
1132 {
1133 //Turn off Merge Interface first to switch I2S sampling rate
1134 Afe_Set_Reg(AFE_MRGIF_CON, 0, 1 << 16); // Turn off I2S
1135 if (AudioDaiBt->mDAIBT_ON == true)
1136 {
1137 Afe_Set_Reg(AFE_DAIBT_CON0, 0, 0x1); //Turn off DAIBT first
1138 }
1139 udelay(100);
1140 Afe_Set_Reg(AFE_MRGIF_CON, 0, 0x1); // Turn off Merge Interface
1141 udelay(100);
1142 Afe_Set_Reg(AFE_MRGIF_CON, 1, 0x1); // Turn on Merge Interface
1143 if (AudioDaiBt->mDAIBT_ON == true)
1144 {
1145 Afe_Set_Reg(AFE_DAIBT_CON0, AudioDaiBt->mDAI_BT_MODE << 9, 0x1 << 9); // use merge
1146 Afe_Set_Reg(AFE_DAIBT_CON0, 0x1 << 12, 0x1 << 12); // use merge
1147 Afe_Set_Reg(AFE_DAIBT_CON0, 0x1 << 3, 0x1 << 3); // data ready
1148 Afe_Set_Reg(AFE_DAIBT_CON0, 0x3, 0x3); //Turn on DAIBT
1149 }
1150 mAudioMrg->Mrg_I2S_SampleRate = SampleRateTransform(sampleRate);
1151 Afe_Set_Reg(AFE_MRGIF_CON, mAudioMrg->Mrg_I2S_SampleRate << 20, 0xF00000); // set Mrg_I2S Samping Rate
1152 Afe_Set_Reg(AFE_MRGIF_CON, 1 << 16, 1 << 16); // set Mrg_I2S enable
1153 }
1154 }
1155 else
1156 {
1157 // turn on merge Interface from off state
1158 mAudioMrg->Mrg_I2S_SampleRate = SampleRateTransform(sampleRate);
1159 Afe_Set_Reg(AFE_MRGIF_CON, mAudioMrg->Mrg_I2S_SampleRate << 20, 0xF00000); // set Mrg_I2S Samping rates
1160 Afe_Set_Reg(AFE_MRGIF_CON, 1 << 16, 1 << 16); // set Mrg_I2S enable
1161 udelay(100);
1162 Afe_Set_Reg(AFE_MRGIF_CON, 1, 0x1); // Turn on Merge Interface
1163 udelay(100);
1164 if (AudioDaiBt->mDAIBT_ON == true)
1165 {
1166 Afe_Set_Reg(AFE_DAIBT_CON0, AudioDaiBt->mDAI_BT_MODE << 9, 0x1 << 9); // use merge
1167 Afe_Set_Reg(AFE_DAIBT_CON0, 0x1 << 12, 0x1 << 12); // use merge
1168 Afe_Set_Reg(AFE_DAIBT_CON0, 0x1 << 3, 0x1 << 3); // data ready
1169 Afe_Set_Reg(AFE_DAIBT_CON0, 0x3, 0x3); //Turn on DAIBT
1170 }
1171 }
1172 mAudioMrg->MrgIf_En = true;
1173 mAudioMrg->Mergeif_I2S_Enable = true;
1174 }
1175 else
1176 {
1177 if (mAudioMrg->MrgIf_En == true)
1178 {
1179 Afe_Set_Reg(AFE_MRGIF_CON, 0, 1 << 16); // Turn off I2S
1180 if (AudioDaiBt->mDAIBT_ON == false)
1181 {
1182 udelay(100);
1183 // DAIBT also not using, then it's OK to disable Merge Interface
1184 Afe_Set_Reg(AFE_MRGIF_CON, 0, 0x1); // Turn off Merge Interface
1185 mAudioMrg->MrgIf_En = false;
1186 }
1187 }
1188 mAudioMrg->Mergeif_I2S_Enable = false;
1189 }
1190 return true;
1191 }
1192 bool Set2ndI2SAdcIn(AudioDigtalI2S *DigtalI2S)
1193 {
1194 //K2 todo?
1195 return true;
1196 }
1197
1198 bool SetI2SAdcIn(AudioDigtalI2S *DigtalI2S)
1199 {
1200 uint32 Audio_I2S_Adc = 0;
1201 memcpy((void *)AudioAdcI2S, (void *)DigtalI2S, sizeof(AudioDigtalI2S));
1202
1203 if (false == AudioAdcI2SStatus)
1204 {
1205 uint32 eSamplingRate = SampleRateTransform(AudioAdcI2S->mI2S_SAMPLERATE);
1206 uint32 dVoiceModeSelect = 0;
1207 Afe_Set_Reg(AFE_ADDA_TOP_CON0, 0, 0x1); //Using Internal ADC
1208 if (eSamplingRate == Soc_Aud_I2S_SAMPLERATE_I2S_8K)
1209 {
1210 dVoiceModeSelect = 0;
1211 }
1212 else if (eSamplingRate == Soc_Aud_I2S_SAMPLERATE_I2S_16K)
1213 {
1214 dVoiceModeSelect = 1;
1215 }
1216 else if (eSamplingRate == Soc_Aud_I2S_SAMPLERATE_I2S_32K)
1217 {
1218 dVoiceModeSelect = 2;
1219 }
1220 else if (eSamplingRate == Soc_Aud_I2S_SAMPLERATE_I2S_48K)
1221 {
1222 dVoiceModeSelect = 3;
1223 }
1224 else
1225 {
1226 }
1227 Afe_Set_Reg(AFE_ADDA_UL_SRC_CON0, (dVoiceModeSelect << 19) | (dVoiceModeSelect << 17), 0x001E0000);
1228 Afe_Set_Reg(AFE_ADDA_NEWIF_CFG0, 0x03F87201, 0xFFFFFFFF); // up8x txif sat on
1229 Afe_Set_Reg(AFE_ADDA_NEWIF_CFG1, ((dVoiceModeSelect < 3) ? 1 : 3) << 10, 0x00000C00);
1230 }
1231 else
1232 {
1233 Afe_Set_Reg(AFE_ADDA_TOP_CON0, 1, 0x1); //Using External ADC
1234 Audio_I2S_Adc |= (AudioAdcI2S->mLR_SWAP << 31);
1235 Audio_I2S_Adc |= (AudioAdcI2S->mBuffer_Update_word << 24);
1236 Audio_I2S_Adc |= (AudioAdcI2S->mINV_LRCK << 23);
1237 Audio_I2S_Adc |= (AudioAdcI2S->mFpga_bit_test << 22);
1238 Audio_I2S_Adc |= (AudioAdcI2S->mFpga_bit << 21);
1239 Audio_I2S_Adc |= (AudioAdcI2S->mloopback << 20);
1240 Audio_I2S_Adc |= (SampleRateTransform(AudioAdcI2S->mI2S_SAMPLERATE) << 8);
1241 Audio_I2S_Adc |= (AudioAdcI2S->mI2S_FMT << 3);
1242 Audio_I2S_Adc |= (AudioAdcI2S->mI2S_WLEN << 1);
1243 printk("%s Audio_I2S_Adc = 0x%x", __FUNCTION__, Audio_I2S_Adc);
1244 Afe_Set_Reg(AFE_I2S_CON2, Audio_I2S_Adc, MASK_ALL);
1245 }
1246 return true;
1247 }
1248
1249 bool EnableSideGenHw(uint32 connection , bool direction , bool Enable)
1250 {
1251 printk("+%s(), connection = %d, direction = %d, Enable= %d\n", __FUNCTION__, connection, direction, Enable);
1252 if (Enable && direction)
1253 {
1254 switch (connection)
1255 {
1256 case Soc_Aud_InterConnectionInput_I00:
1257 case Soc_Aud_InterConnectionInput_I01:
1258 Afe_Set_Reg(AFE_SGEN_CON0, 0x048C2762, 0xffffffff);
1259 break;
1260 case Soc_Aud_InterConnectionInput_I02:
1261 Afe_Set_Reg(AFE_SGEN_CON0, 0x146C2662, 0xffffffff);
1262 break;
1263 case Soc_Aud_InterConnectionInput_I03:
1264 case Soc_Aud_InterConnectionInput_I04:
1265 Afe_Set_Reg(AFE_SGEN_CON0, 0x24862862, 0xffffffff);
1266 break;
1267 case Soc_Aud_InterConnectionInput_I05:
1268 case Soc_Aud_InterConnectionInput_I06:
1269 Afe_Set_Reg(AFE_SGEN_CON0, 0x348C28C2, 0xffffffff);
1270 break;
1271 case Soc_Aud_InterConnectionInput_I07:
1272 case Soc_Aud_InterConnectionInput_I08:
1273 Afe_Set_Reg(AFE_SGEN_CON0, 0x446C2662, 0xffffffff);
1274 break;
1275 case Soc_Aud_InterConnectionInput_I09:
1276 Afe_Set_Reg(AFE_SGEN_CON0, 0x546C2662, 0xffffffff);
1277 case Soc_Aud_InterConnectionInput_I10:
1278 case Soc_Aud_InterConnectionInput_I11:
1279 Afe_Set_Reg(AFE_SGEN_CON0, 0x646C2662, 0xffffffff);
1280 break;
1281 case Soc_Aud_InterConnectionInput_I12:
1282 case Soc_Aud_InterConnectionInput_I13:
1283 Afe_Set_Reg(AFE_SGEN_CON0, 0x746C2662, 0xffffffff);
1284 break;
1285 case Soc_Aud_InterConnectionInput_I14:
1286 Afe_Set_Reg(AFE_SGEN_CON0, 0x846C2662, 0xffffffff);
1287 break;
1288 case Soc_Aud_InterConnectionInput_I15:
1289 case Soc_Aud_InterConnectionInput_I16:
1290 Afe_Set_Reg(AFE_SGEN_CON0, 0x946C2662, 0xffffffff);
1291 break;
1292 case Soc_Aud_InterConnectionInput_I17:
1293 case Soc_Aud_InterConnectionInput_I18:
1294 Afe_Set_Reg(AFE_SGEN_CON0, 0xa46C2662, 0xffffffff);
1295 break;
1296 case Soc_Aud_InterConnectionInput_I19:
1297 case Soc_Aud_InterConnectionInput_I20:
1298 Afe_Set_Reg(AFE_SGEN_CON0, 0xb46C2662, 0xffffffff);
1299 break;
1300 case Soc_Aud_InterConnectionInput_I21:
1301 case Soc_Aud_InterConnectionInput_I22:
1302 break;
1303 Afe_Set_Reg(AFE_SGEN_CON0, 0xc46C2662, 0xffffffff);
1304 default:
1305 break;
1306 }
1307 }
1308 else if (Enable)
1309 {
1310 switch (connection)
1311 {
1312 case Soc_Aud_InterConnectionOutput_O00:
1313 case Soc_Aud_InterConnectionOutput_O01:
1314 Afe_Set_Reg(AFE_SGEN_CON0, 0x0c7c27c2, 0xffffffff);
1315 break;
1316 case Soc_Aud_InterConnectionOutput_O02:
1317 Afe_Set_Reg(AFE_SGEN_CON0, 0x1c6c26c2, 0xffffffff);
1318 break;
1319 case Soc_Aud_InterConnectionOutput_O03:
1320 case Soc_Aud_InterConnectionOutput_O04:
1321 Afe_Set_Reg(AFE_SGEN_CON0, 0x2c8c28c2, 0xffffffff);
1322 break;
1323 case Soc_Aud_InterConnectionOutput_O05:
1324 case Soc_Aud_InterConnectionOutput_O06:
1325 Afe_Set_Reg(AFE_SGEN_CON0, 0x3c6c26c2, 0xffffffff);
1326 break;
1327 case Soc_Aud_InterConnectionOutput_O07:
1328 case Soc_Aud_InterConnectionOutput_O08:
1329 Afe_Set_Reg(AFE_SGEN_CON0, 0x4c6c26c2, 0xffffffff);
1330 break;
1331 case Soc_Aud_InterConnectionOutput_O09:
1332 case Soc_Aud_InterConnectionOutput_O10:
1333 Afe_Set_Reg(AFE_SGEN_CON0, 0x5c6c26c2, 0xffffffff);
1334 break;
1335 case Soc_Aud_InterConnectionOutput_O11:
1336 Afe_Set_Reg(AFE_SGEN_CON0, 0x6c6c26c2, 0xffffffff);
1337 break;
1338 case Soc_Aud_InterConnectionOutput_O12:
1339 if (Soc_Aud_I2S_SAMPLERATE_I2S_8K == mAudioMEMIF[Soc_Aud_Digital_Block_MEM_MOD_DAI]->mSampleRate) //MD connect BT Verify (8K SamplingRate)
1340 {
1341 Afe_Set_Reg(AFE_SGEN_CON0, 0x7c0e80e8, 0xffffffff);
1342 }
1343 else if (Soc_Aud_I2S_SAMPLERATE_I2S_16K == mAudioMEMIF[Soc_Aud_Digital_Block_MEM_MOD_DAI]->mSampleRate)
1344 {
1345 Afe_Set_Reg(AFE_SGEN_CON0, 0x7c0f00f0, 0xffffffff);
1346 }
1347 else
1348 {
1349 Afe_Set_Reg(AFE_SGEN_CON0, 0x7c6c26c2, 0xffffffff); //Default
1350 }
1351 break;
1352 case Soc_Aud_InterConnectionOutput_O13:
1353 case Soc_Aud_InterConnectionOutput_O14:
1354 Afe_Set_Reg(AFE_SGEN_CON0, 0x8c6c26c2, 0xffffffff);
1355 break;
1356 case Soc_Aud_InterConnectionOutput_O15:
1357 case Soc_Aud_InterConnectionOutput_O16:
1358 Afe_Set_Reg(AFE_SGEN_CON0, 0x9c6c26c2, 0xffffffff);
1359 break;
1360 case Soc_Aud_InterConnectionOutput_O17:
1361 case Soc_Aud_InterConnectionOutput_O18:
1362 Afe_Set_Reg(AFE_SGEN_CON0, 0xac6c26c2, 0xffffffff);
1363 break;
1364 case Soc_Aud_InterConnectionOutput_O19:
1365 case Soc_Aud_InterConnectionOutput_O20:
1366 Afe_Set_Reg(AFE_SGEN_CON0, 0xbc6c26c2, 0xffffffff);
1367 break;
1368 case Soc_Aud_InterConnectionOutput_O21:
1369 case Soc_Aud_InterConnectionOutput_O22:
1370 Afe_Set_Reg(AFE_SGEN_CON0, 0xcc6c26c2, 0xffffffff);
1371 break;
1372 case Soc_Aud_InterConnectionOutput_O23:
1373 case Soc_Aud_InterConnectionOutput_O24:
1374 Afe_Set_Reg(AFE_SGEN_CON0, 0xdc6c26c2, 0xffffffff);
1375 break;
1376 case Soc_Aud_InterConnectionOutput_O25:
1377 Afe_Set_Reg(AFE_SGEN_CON0, 0xec6c26c2, 0xffffffff);
1378 default:
1379 break;
1380 }
1381 }
1382 else
1383 {
1384 //don't set [31:28] as 0 when disable sinetone HW, because it will repalce i00/i01 input with sine gen output.
1385 //Set 0xf is correct way to disconnect sinetone HW to any I/O.
1386 Afe_Set_Reg(AFE_SGEN_CON0, 0xf0000000 , 0xffffffff);
1387 }
1388 return true;
1389 }
1390
1391 bool SetSideGenSampleRate(uint32 SampleRate)
1392 {
1393 uint32 sine_mode_ch1 = 0;
1394 uint32 sine_mode_ch2 = 0;
1395
1396 printk("+%s(), SampleRate = %d\n", __FUNCTION__, SampleRate);
1397
1398 sine_mode_ch1 = SampleRateTransform(SampleRate) << 8;
1399 sine_mode_ch2 = SampleRateTransform(SampleRate) << 20;
1400
1401 Afe_Set_Reg(AFE_SGEN_CON0, sine_mode_ch1, 0x00000f00);
1402 Afe_Set_Reg(AFE_SGEN_CON0, sine_mode_ch2, 0x00f00000);
1403 return true;
1404 }
1405
1406 bool Set2ndI2SAdcEnable(bool bEnable)
1407 {
1408 // K2 todo?
1409 return true;
1410 }
1411
1412 bool SetI2SAdcEnable(bool bEnable)
1413 {
1414 Afe_Set_Reg(AFE_ADDA_UL_SRC_CON0, bEnable ? 1 : 0, 0x01);
1415 mAudioMEMIF[Soc_Aud_Digital_Block_I2S_IN_ADC]->mState = bEnable;
1416 if (bEnable == true)
1417 {
1418 Afe_Set_Reg(AFE_ADDA_UL_DL_CON0, 0x0001, 0x0001);
1419 }
1420 else if (mAudioMEMIF[Soc_Aud_Digital_Block_I2S_OUT_DAC]->mState == false &&
1421 mAudioMEMIF[Soc_Aud_Digital_Block_I2S_IN_ADC]->mState == false &&
1422 mAudioMEMIF[Soc_Aud_Digital_Block_I2S_IN_ADC_2]->mState == false)
1423 {
1424 Afe_Set_Reg(AFE_ADDA_UL_DL_CON0, 0x0000, 0x0001);
1425 }
1426 return true;
1427 }
1428
1429 bool Set2ndI2SEnable(bool bEnable)
1430 {
1431 Afe_Set_Reg(AFE_I2S_CON, bEnable, 0x1);
1432 return true;
1433 }
1434
1435 bool CleanPreDistortion()
1436 {
1437 //printk("%s \n", __FUNCTION__);
1438 Afe_Set_Reg(AFE_ADDA_PREDIS_CON0, 0, MASK_ALL);
1439 Afe_Set_Reg(AFE_ADDA_PREDIS_CON1, 0, MASK_ALL);
1440 return true;
1441 }
1442
1443 bool SetDLSrc2(uint32 SampleRate)
1444 {
1445 uint32 AfeAddaDLSrc2Con0, AfeAddaDLSrc2Con1;
1446 if (SampleRate == 8000)
1447 {
1448 AfeAddaDLSrc2Con0 = 0;
1449 }
1450 else if (SampleRate == 11025)
1451 {
1452 AfeAddaDLSrc2Con0 = 1;
1453 }
1454 else if (SampleRate == 12000)
1455 {
1456 AfeAddaDLSrc2Con0 = 2;
1457 }
1458 else if (SampleRate == 16000)
1459 {
1460 AfeAddaDLSrc2Con0 = 3;
1461 }
1462 else if (SampleRate == 22050)
1463 {
1464 AfeAddaDLSrc2Con0 = 4;
1465 }
1466 else if (SampleRate == 24000)
1467 {
1468 AfeAddaDLSrc2Con0 = 5;
1469 }
1470 else if (SampleRate == 32000)
1471 {
1472 AfeAddaDLSrc2Con0 = 6;
1473 }
1474 else if (SampleRate == 44100)
1475 {
1476 AfeAddaDLSrc2Con0 = 7;
1477 }
1478 else if (SampleRate == 48000)
1479 {
1480 AfeAddaDLSrc2Con0 = 8;
1481 }
1482 else
1483 {
1484 AfeAddaDLSrc2Con0 = 7; //Default 44100
1485 }
1486 //ASSERT(0);
1487 if (AfeAddaDLSrc2Con0 == 0 || AfeAddaDLSrc2Con0 == 3) //8k or 16k voice mode
1488 {
1489 AfeAddaDLSrc2Con0 = (AfeAddaDLSrc2Con0 << 28) | (0x03 << 24) | (0x03 << 11) | (0x01 << 5);
1490 }
1491 else
1492 {
1493 AfeAddaDLSrc2Con0 = (AfeAddaDLSrc2Con0 << 28) | (0x03 << 24) | (0x03 << 11);
1494 }
1495 //SA suggest apply -0.3db to audio/speech path
1496 AfeAddaDLSrc2Con0 = AfeAddaDLSrc2Con0 | (0x01 << 1); //2013.02.22 for voice mode degrade 0.3 db
1497 AfeAddaDLSrc2Con1 = 0xf74f0000;
1498
1499 Afe_Set_Reg(AFE_ADDA_DL_SRC2_CON0, AfeAddaDLSrc2Con0, MASK_ALL);
1500 Afe_Set_Reg(AFE_ADDA_DL_SRC2_CON1, AfeAddaDLSrc2Con1, MASK_ALL);
1501 return true;
1502
1503 }
1504
1505 bool SetI2SDacOut(uint32 SampleRate , bool lowjitter, bool I2SWLen)
1506 {
1507 uint32 Audio_I2S_Dac = 0;
1508 printk("SetI2SDacOut SampleRate %d, lowjitter %d, I2SWLen %d\n",SampleRate,lowjitter,I2SWLen);
1509 CleanPreDistortion();
1510 SetDLSrc2(SampleRate);
1511 Audio_I2S_Dac |= (Soc_Aud_LR_SWAP_NO_SWAP << 31);
1512 Audio_I2S_Dac |= (SampleRateTransform(SampleRate) << 8);
1513 Audio_I2S_Dac |= (Soc_Aud_INV_LRCK_NO_INVERSE << 5);
1514 Audio_I2S_Dac |= (Soc_Aud_I2S_FORMAT_I2S << 3);
1515 Audio_I2S_Dac |= (I2SWLen << 1);
1516 Audio_I2S_Dac |= (lowjitter << 12); // low gitter mode
1517 Afe_Set_Reg(AFE_I2S_CON1, Audio_I2S_Dac, MASK_ALL);
1518 return true;
1519 }
1520
1521 bool SetHwDigitalGainMode(uint32 GainType, uint32 SampleRate, uint32 SamplePerStep)
1522 {
1523 //printk("SetHwDigitalGainMode GainType = %d, SampleRate = %d, SamplePerStep= %d\n", GainType, SampleRate, SamplePerStep);
1524 uint32 value = 0;
1525 value = (SamplePerStep << 8) | (SampleRateTransform(SampleRate) << 4);
1526 switch (GainType)
1527 {
1528 case Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1:
1529 Afe_Set_Reg(AFE_GAIN1_CON0, value, 0xfff0);
1530 break;
1531 case Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN2:
1532 Afe_Set_Reg(AFE_GAIN2_CON0, value, 0xfff0);
1533 break;
1534 default:
1535 return false;
1536 }
1537 return true;
1538 }
1539
1540 bool SetHwDigitalGainEnable(int GainType, bool Enable)
1541 {
1542 printk("+%s(), GainType = %d, Enable = %d\n", __FUNCTION__, GainType, Enable);
1543 switch (GainType)
1544 {
1545 case Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1:
1546 if (Enable)
1547 {
1548 Afe_Set_Reg(AFE_GAIN1_CUR, 0, 0xFFFFFFFF); //Let current gain be 0 to ramp up
1549 }
1550 Afe_Set_Reg(AFE_GAIN1_CON0, Enable, 0x1);
1551 break;
1552 case Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN2:
1553 if (Enable)
1554 {
1555 Afe_Set_Reg(AFE_GAIN2_CUR, 0, 0xFFFFFFFF); //Let current gain be 0 to ramp up
1556 }
1557 Afe_Set_Reg(AFE_GAIN2_CON0, Enable, 0x1);
1558 break;
1559 default:
1560 printk("%s with no match type\n", __func__);
1561 return false;
1562 }
1563 return true;
1564 }
1565
1566 bool SetHwDigitalGain(uint32 Gain , int GainType)
1567 {
1568 printk("+%s(), Gain = 0x%x, gain type = %d\n", __func__, Gain, GainType);
1569 switch (GainType)
1570 {
1571 case Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1:
1572 Afe_Set_Reg(AFE_GAIN1_CON1, Gain, 0xffffffff);
1573 break;
1574 case Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN2:
1575 Afe_Set_Reg(AFE_GAIN2_CON1, Gain, 0xffffffff);
1576 break;
1577 default:
1578 printk("%s with no match type\n", __func__);
1579 return false;
1580 }
1581 return true;
1582 }
1583
1584 bool SetModemPcmConfig(int modem_index , AudioDigitalPCM p_modem_pcm_attribute)
1585 {
1586 uint32 reg_pcm2_intf_con = 0;
1587 uint32 reg_pcm_intf_con1 = 0;
1588 printk("+%s()\n", __func__);
1589 if (modem_index == MODEM_1)
1590 {
1591 reg_pcm2_intf_con |= (p_modem_pcm_attribute.mTxLchRepeatSel & 0x1) << 13;
1592 reg_pcm2_intf_con |= (p_modem_pcm_attribute.mVbt16kModeSel & 0x1) << 12;
1593 reg_pcm2_intf_con |= (p_modem_pcm_attribute.mSingelMicSel & 0x1) << 7;
1594 reg_pcm2_intf_con |= (p_modem_pcm_attribute.mAsyncFifoSel & 0x1) << 6;
1595 reg_pcm2_intf_con |= (p_modem_pcm_attribute.mPcmWordLength & 0x1) << 5;
1596 reg_pcm2_intf_con |= (p_modem_pcm_attribute.mPcmModeWidebandSel & 0x3) << 3;
1597 reg_pcm2_intf_con |= (p_modem_pcm_attribute.mPcmFormat & 0x3) << 1;
1598 printk("%s(), PCM2_INTF_CON(0x%lx) = 0x%x\n", __FUNCTION__, PCM2_INTF_CON, reg_pcm2_intf_con);
1599 Afe_Set_Reg(PCM2_INTF_CON, reg_pcm2_intf_con, MASK_ALL);
1600 if (p_modem_pcm_attribute.mPcmModeWidebandSel == Soc_Aud_PCM_MODE_PCM_MODE_8K)
1601 {
1602 Afe_Set_Reg(AFE_ASRC2_CON1, 0x00098580, 0xffffffff);
1603 Afe_Set_Reg(AFE_ASRC2_CON2, 0x00400000, 0xffffffff);
1604 Afe_Set_Reg(AFE_ASRC2_CON3, 0x00400000, 0xffffffff);
1605 Afe_Set_Reg(AFE_ASRC2_CON4, 0x00098580, 0xffffffff);
1606 Afe_Set_Reg(AFE_ASRC2_CON7, 0x0004c2c0, 0xffffffff);
1607 Afe_Set_Reg(AFE_ASRC3_CON1, 0x00098580, 0xffffffff);
1608 Afe_Set_Reg(AFE_ASRC3_CON2, 0x00400000, 0xffffffff);
1609 Afe_Set_Reg(AFE_ASRC3_CON3, 0x00400000, 0xffffffff);
1610 Afe_Set_Reg(AFE_ASRC3_CON4, 0x00098580, 0xffffffff);
1611 Afe_Set_Reg(AFE_ASRC3_CON7, 0x0004c2c0, 0xffffffff);
1612 }
1613 else if (p_modem_pcm_attribute.mPcmModeWidebandSel == Soc_Aud_PCM_MODE_PCM_MODE_16K)
1614 {
1615 Afe_Set_Reg(AFE_ASRC2_CON1, 0x0004c2c0, 0xffffffff);
1616 Afe_Set_Reg(AFE_ASRC2_CON2, 0x00400000, 0xffffffff);
1617 Afe_Set_Reg(AFE_ASRC2_CON3, 0x00400000, 0xffffffff);
1618 Afe_Set_Reg(AFE_ASRC2_CON4, 0x0004c2c0, 0xffffffff);
1619 Afe_Set_Reg(AFE_ASRC2_CON7, 0x00026160, 0xffffffff);
1620 Afe_Set_Reg(AFE_ASRC3_CON1, 0x0004c2c0, 0xffffffff);
1621 Afe_Set_Reg(AFE_ASRC3_CON2, 0x00400000, 0xffffffff);
1622 Afe_Set_Reg(AFE_ASRC3_CON3, 0x00400000, 0xffffffff);
1623 Afe_Set_Reg(AFE_ASRC3_CON4, 0x0004c2c0, 0xffffffff);
1624 Afe_Set_Reg(AFE_ASRC3_CON7, 0x00026160, 0xffffffff);
1625 }
1626 else if (p_modem_pcm_attribute.mPcmModeWidebandSel == Soc_Aud_PCM_MODE_PCM_MODE_32K)
1627 {
1628 Afe_Set_Reg(AFE_ASRC2_CON1, 0x00026160, 0xffffffff);
1629 Afe_Set_Reg(AFE_ASRC2_CON2, 0x00400000, 0xffffffff);
1630 Afe_Set_Reg(AFE_ASRC2_CON3, 0x00400000, 0xffffffff);
1631 Afe_Set_Reg(AFE_ASRC2_CON4, 0x00026160, 0xffffffff);
1632 Afe_Set_Reg(AFE_ASRC2_CON7, 0x000130b0, 0xffffffff);
1633 Afe_Set_Reg(AFE_ASRC3_CON1, 0x00026160, 0xffffffff);
1634 Afe_Set_Reg(AFE_ASRC3_CON2, 0x00400000, 0xffffffff);
1635 Afe_Set_Reg(AFE_ASRC3_CON3, 0x00400000, 0xffffffff);
1636 Afe_Set_Reg(AFE_ASRC3_CON4, 0x00026160, 0xffffffff);
1637 Afe_Set_Reg(AFE_ASRC3_CON7, 0x000130b0, 0xffffffff);
1638 }
1639
1640 }
1641 else if (modem_index == MODEM_2 || modem_index == MODEM_EXTERNAL) // MODEM_2 use PCM_INTF_CON1 (0x530) !!!
1642 {
1643 if (p_modem_pcm_attribute.mPcmModeWidebandSel == Soc_Aud_PCM_MODE_PCM_MODE_8K)
1644 {
1645 Afe_Set_Reg(AFE_ASRC_CON1, 0x00098580, 0xffffffff);
1646 Afe_Set_Reg(AFE_ASRC_CON2, 0x00400000, 0xffffffff);
1647 Afe_Set_Reg(AFE_ASRC_CON3, 0x00400000, 0xffffffff);
1648 Afe_Set_Reg(AFE_ASRC_CON4, 0x00098580, 0xffffffff);
1649 Afe_Set_Reg(AFE_ASRC_CON7, 0x0004c2c0, 0xffffffff);
1650
1651 Afe_Set_Reg(AFE_ASRC4_CON1, 0x00098580, 0xffffffff);
1652 Afe_Set_Reg(AFE_ASRC4_CON2, 0x00400000, 0xffffffff);
1653 Afe_Set_Reg(AFE_ASRC4_CON3, 0x00400000, 0xffffffff);
1654 Afe_Set_Reg(AFE_ASRC4_CON4, 0x00098580, 0xffffffff);
1655 Afe_Set_Reg(AFE_ASRC4_CON7, 0x0004c2c0, 0xffffffff);
1656 }
1657 else if (p_modem_pcm_attribute.mPcmModeWidebandSel == Soc_Aud_PCM_MODE_PCM_MODE_16K)
1658 {
1659 Afe_Set_Reg(AFE_ASRC_CON1, 0x0004c2c0, 0xffffffff);
1660 Afe_Set_Reg(AFE_ASRC_CON2, 0x00400000, 0xffffffff);
1661 Afe_Set_Reg(AFE_ASRC_CON3, 0x00400000, 0xffffffff);
1662 Afe_Set_Reg(AFE_ASRC_CON4, 0x0004c2c0, 0xffffffff);
1663 Afe_Set_Reg(AFE_ASRC_CON7, 0x00026160, 0xffffffff);
1664
1665 Afe_Set_Reg(AFE_ASRC4_CON1, 0x0004c2c0, 0xffffffff);
1666 Afe_Set_Reg(AFE_ASRC4_CON2, 0x00400000, 0xffffffff);
1667 Afe_Set_Reg(AFE_ASRC4_CON3, 0x00400000, 0xffffffff);
1668 Afe_Set_Reg(AFE_ASRC4_CON4, 0x0004c2c0, 0xffffffff);
1669 Afe_Set_Reg(AFE_ASRC4_CON7, 0x00026160, 0xffffffff);
1670 }
1671 else if (p_modem_pcm_attribute.mPcmModeWidebandSel == Soc_Aud_PCM_MODE_PCM_MODE_32K)
1672 {
1673 Afe_Set_Reg(AFE_ASRC_CON1, 0x00026160, 0xffffffff);
1674 Afe_Set_Reg(AFE_ASRC_CON2, 0x00400000, 0xffffffff);
1675 Afe_Set_Reg(AFE_ASRC_CON3, 0x00400000, 0xffffffff);
1676 Afe_Set_Reg(AFE_ASRC_CON4, 0x00026160, 0xffffffff);
1677 Afe_Set_Reg(AFE_ASRC_CON7, 0x000130b0, 0xffffffff);
1678
1679 Afe_Set_Reg(AFE_ASRC4_CON1, 0x00026160, 0xffffffff);
1680 Afe_Set_Reg(AFE_ASRC4_CON2, 0x00400000, 0xffffffff);
1681 Afe_Set_Reg(AFE_ASRC4_CON3, 0x00400000, 0xffffffff);
1682 Afe_Set_Reg(AFE_ASRC4_CON4, 0x00026160, 0xffffffff);
1683 Afe_Set_Reg(AFE_ASRC4_CON7, 0x000130b0, 0xffffffff);
1684 }
1685
1686 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mBclkOutInv & 0x01) << 22;
1687 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mTxLchRepeatSel & 0x01) << 19;
1688 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mVbt16kModeSel & 0x01) << 18;
1689 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mExtModemSel & 0x01) << 17;
1690 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mExtendBckSyncLength & 0x1F) << 9;
1691 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mExtendBckSyncTypeSel & 0x01) << 8;
1692 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mSingelMicSel & 0x01) << 7;
1693 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mAsyncFifoSel & 0x01) << 6;
1694 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mSlaveModeSel & 0x01) << 5;
1695 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mPcmModeWidebandSel & 0x03) << 3;
1696 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mPcmFormat & 0x03) << 1;
1697
1698 printk("%s(), PCM_INTF_CON1(0x%lx) = 0x%x", __FUNCTION__, PCM_INTF_CON, reg_pcm_intf_con1);
1699 Afe_Set_Reg(PCM_INTF_CON, reg_pcm_intf_con1, MASK_ALL);
1700
1701 }
1702 return true;
1703 }
1704
1705 bool SetModemPcmEnable(int modem_index, bool modem_pcm_on)
1706 {
1707 uint32 dNeedDisableASM = 0, mPcm1AsyncFifo;
1708 printk("+%s(), modem_index = %d, modem_pcm_on = %d\n", __FUNCTION__, modem_index, modem_pcm_on);
1709
1710 if (modem_index == MODEM_1) // MODEM_1 use PCM2_INTF_CON (0x53C) !!!
1711 {
1712 // todo:: temp for use fifo
1713 Afe_Set_Reg(PCM2_INTF_CON, modem_pcm_on, 0x1);
1714 mAudioMEMIF[Soc_Aud_Digital_Block_MODEM_PCM_1_O]->mState = modem_pcm_on;
1715 }
1716 else if (modem_index == MODEM_2 || modem_index == MODEM_EXTERNAL) // MODEM_2 use PCM_INTF_CON1 (0x530) !!!
1717 {
1718 if (modem_pcm_on == true) // turn on ASRC before Modem PCM on
1719 {
1720 mPcm1AsyncFifo = (Afe_Get_Reg(PCM_INTF_CON) & 0x0040) >> 6;
1721 if (mPcm1AsyncFifo == 0)
1722 {
1723 Afe_Set_Reg(AFE_ASRC_CON6, 0x005f188f, MASK_ALL);
1724 Afe_Set_Reg(AFE_ASRC_CON0, 0x86083031, MASK_ALL);
1725
1726 Afe_Set_Reg(AFE_ASRC4_CON6, 0x005f188f, MASK_ALL);
1727 Afe_Set_Reg(AFE_ASRC4_CON0, 0x06003031, MASK_ALL);
1728 }
1729 Afe_Set_Reg(PCM_INTF_CON, 0x1, 0x1);
1730 }
1731 else if (modem_pcm_on == false) // turn off ASRC after Modem PCM off
1732 {
1733 Afe_Set_Reg(PCM_INTF_CON, 0x0, 0x1);
1734
1735 Afe_Set_Reg(AFE_ASRC_CON6, 0x00000000, MASK_ALL);
1736 dNeedDisableASM = (Afe_Get_Reg(AFE_ASRC_CON0) & 0x1) ? 1 : 0;
1737 Afe_Set_Reg(AFE_ASRC_CON0, 0, (1 << 4 | 1 << 5 | dNeedDisableASM));
1738 Afe_Set_Reg(AFE_ASRC_CON0, 0x0, 0x1);
1739
1740 Afe_Set_Reg(AFE_ASRC4_CON6, 0x00000000, MASK_ALL);
1741 Afe_Set_Reg(AFE_ASRC4_CON0, 0, (1 << 4 | 1 << 5));
1742 Afe_Set_Reg(AFE_ASRC4_CON0, 0x0, 0x1);
1743 }
1744 mAudioMEMIF[Soc_Aud_Digital_Block_MODEM_PCM_2_O]->mState = modem_pcm_on;
1745 }
1746 else
1747 {
1748 printk("%s(), no such modem_index: %d!!", __FUNCTION__, modem_index);
1749 return false;
1750 }
1751 return true;
1752 }
1753
1754
1755 bool EnableSideToneFilter(bool stf_on)
1756 {
1757
1758 // MD max support 16K sampling rate
1759 const uint8_t kSideToneHalfTapNum = sizeof(kSideToneCoefficientTable16k) / sizeof(uint16_t);
1760 printk("+%s(), stf_on = %d\n", __func__, stf_on);
1761 AudDrv_Clk_On();
1762
1763 if (stf_on == false)
1764 {
1765 // bypass STF result & disable
1766 const bool bypass_stf_on = true;
1767 uint32_t reg_value = (bypass_stf_on << 31) | (stf_on << 8);
1768 Afe_Set_Reg(AFE_SIDETONE_CON1, reg_value, MASK_ALL);
1769 printk("%s(), AFE_SIDETONE_CON1[0x%lx] = 0x%x\n", __FUNCTION__, AFE_SIDETONE_CON1, reg_value);
1770
1771 // set side tone gain = 0
1772 Afe_Set_Reg(AFE_SIDETONE_GAIN, 0, MASK_ALL);
1773 printk("%s(), AFE_SIDETONE_GAIN[0x%lx] = 0x%x\n", __FUNCTION__, AFE_SIDETONE_GAIN, 0);
1774 }
1775 else
1776 {
1777 const bool bypass_stf_on = false;
1778 // using STF result & enable & set half tap num
1779 uint32_t write_reg_value = (bypass_stf_on << 31) | (stf_on << 8) | kSideToneHalfTapNum;
1780
1781 // set side tone coefficient
1782 const bool enable_read_write = true; // enable read/write side tone coefficient
1783 const bool read_write_sel = true; // for write case
1784 const bool sel_ch2 = false; // using uplink ch1 as STF input
1785 uint32_t read_reg_value = Afe_Get_Reg(AFE_SIDETONE_CON0);
1786 size_t coef_addr = 0;
1787
1788 printk("%s(), AFE_SIDETONE_GAIN[0x%lx] = 0x%x\n", __FUNCTION__, AFE_SIDETONE_GAIN, 0);
1789 // set side tone gain
1790 Afe_Set_Reg(AFE_SIDETONE_GAIN, 0, MASK_ALL);
1791 Afe_Set_Reg(AFE_SIDETONE_CON1, write_reg_value, MASK_ALL);
1792 printk("%s(), AFE_SIDETONE_CON1[0x%lx] = 0x%x\n", __FUNCTION__, AFE_SIDETONE_CON1, write_reg_value);
1793
1794 for (coef_addr = 0; coef_addr < kSideToneHalfTapNum; coef_addr++)
1795 {
1796 bool old_write_ready = (read_reg_value >> 29) & 0x1;
1797 bool new_write_ready = 0;
1798 int try_cnt = 0;
1799 write_reg_value = enable_read_write << 25 |
1800 read_write_sel << 24 |
1801 sel_ch2 << 23 |
1802 coef_addr << 16 |
1803 kSideToneCoefficientTable16k[coef_addr];
1804 Afe_Set_Reg(AFE_SIDETONE_CON0, write_reg_value, 0x39FFFFF);
1805 printk("%s(), AFE_SIDETONE_CON0[0x%lx] = 0x%x\n", __FUNCTION__, AFE_SIDETONE_CON0, write_reg_value);
1806
1807 // wait until flag write_ready changed (means write done)
1808 for (try_cnt = 0; try_cnt < 10; try_cnt++) // max try 10 times
1809 {
1810 msleep(3);
1811 read_reg_value = Afe_Get_Reg(AFE_SIDETONE_CON0);
1812 new_write_ready = (read_reg_value >> 29) & 0x1;
1813 if (new_write_ready != old_write_ready) // flip => ok
1814 {
1815 break;
1816 }
1817 else
1818 {
1819 BUG_ON(new_write_ready != old_write_ready);
1820 return false;
1821 }
1822 }
1823 }
1824 }
1825 AudDrv_Clk_Off();
1826 printk("-%s(), stf_on = %d\n", __FUNCTION__, stf_on);
1827 return true;
1828 }
1829
1830
1831 bool SetMemoryPathEnable(uint32 Aud_block, bool bEnable)
1832 {
1833 printk("%s Aud_block = %d bEnable = %d \n", __func__, Aud_block, bEnable);
1834 if (Aud_block >= Soc_Aud_Digital_Block_NUM_OF_DIGITAL_BLOCK)
1835 {
1836 return false;
1837 }
1838 // set for counter
1839 if (bEnable == true)
1840 {
1841 if (mAudioMEMIF[Aud_block]->mUserCount == 0)
1842 {
1843 mAudioMEMIF[Aud_block]->mState = true;
1844 }
1845 mAudioMEMIF[Aud_block]->mUserCount++;
1846 }
1847 else
1848 {
1849 mAudioMEMIF[Aud_block]->mUserCount--;
1850 if (mAudioMEMIF[Aud_block]->mUserCount == 0)
1851 {
1852 mAudioMEMIF[Aud_block]->mState = false;
1853 }
1854 if (mAudioMEMIF[Aud_block]->mUserCount < 0)
1855 {
1856 mAudioMEMIF[Aud_block]->mUserCount = 0;
1857 printk("warning , user count <0 \n");
1858 }
1859 }
1860 printk("%s Aud_block = %d mAudioMEMIF[Aud_block]->mUserCount = %d \n", __func__, Aud_block, mAudioMEMIF[Aud_block]->mUserCount);
1861
1862 if (Aud_block > Soc_Aud_Digital_Block_NUM_OF_MEM_INTERFACE)
1863 {
1864 return true;
1865 }
1866
1867 if ((bEnable == true) && (mAudioMEMIF[Aud_block]->mUserCount == 1))
1868 {
1869 Afe_Set_Reg(AFE_DAC_CON0, bEnable << (Aud_block + 1) , 1 << (Aud_block + 1));
1870 }
1871 else if ((bEnable == false) && (mAudioMEMIF[Aud_block]->mUserCount == 0))
1872 {
1873 Afe_Set_Reg(AFE_DAC_CON0, bEnable << (Aud_block + 1), 1 << (Aud_block + 1));
1874 }
1875
1876 return true;
1877 }
1878
1879 bool GetMemoryPathEnable(uint32 Aud_block)
1880 {
1881 if (Aud_block < Soc_Aud_Digital_Block_NUM_OF_DIGITAL_BLOCK)
1882 {
1883 return mAudioMEMIF[Aud_block]->mState;
1884 }
1885 return false;
1886 }
1887
1888 bool SetI2SDacEnable(bool bEnable)
1889 {
1890 printk("%s bEnable = %d", __func__, bEnable);
1891 if (bEnable)
1892 {
1893 Afe_Set_Reg(AFE_ADDA_DL_SRC2_CON0, bEnable, 0x01);
1894 Afe_Set_Reg(AFE_I2S_CON1, bEnable, 0x1);
1895 Afe_Set_Reg(AFE_ADDA_UL_DL_CON0, bEnable, 0x0001);
1896 Afe_Set_Reg(FPGA_CFG1, 0, 0x10); //For FPGA Pin the same with DAC
1897 }
1898 else
1899 {
1900 Afe_Set_Reg(AFE_ADDA_DL_SRC2_CON0, bEnable, 0x01);
1901 Afe_Set_Reg(AFE_I2S_CON1, bEnable, 0x1);
1902
1903 if (mAudioMEMIF[Soc_Aud_Digital_Block_I2S_OUT_DAC]->mState == false &&
1904 mAudioMEMIF[Soc_Aud_Digital_Block_I2S_IN_ADC]->mState == false)
1905 {
1906 Afe_Set_Reg(AFE_ADDA_UL_DL_CON0, bEnable, 0x0001);
1907 }
1908 Afe_Set_Reg(FPGA_CFG1, 1 << 4, 0x10); //For FPGA Pin the same with DAC
1909 }
1910 return true;
1911 }
1912
1913 bool GetI2SDacEnable()
1914 {
1915 return mAudioMEMIF[Soc_Aud_Digital_Block_I2S_OUT_DAC]->mState ;
1916 }
1917
1918 bool checkUplinkMEMIfStatus()
1919 {
1920 int i = 0;
1921 for (i = Soc_Aud_Digital_Block_MEM_VUL ; i <= Soc_Aud_Digital_Block_MEM_VUL_DATA2 ; i ++)
1922 {
1923 if (mAudioMEMIF[i]->mState == true)
1924 {
1925 return true;
1926 }
1927 }
1928 return false;
1929 }
1930
1931 bool SetHDMIChannels(uint32 Channels)
1932 {
1933 // k2 removed
1934 printk("+%s(), not supported!!!\n", __func__);
1935 return true;
1936 }
1937
1938 bool SetHDMIEnable(bool bEnable)
1939 {
1940 // k2 removed
1941 printk("+%s(), not supported!!!\n", __func__);
1942 return true;
1943 }
1944
1945 bool SetHDMIConnection(uint32 ConnectionState, uint32 Input , uint32 Output)
1946 {
1947 // k2 removed
1948 return true;
1949 }
1950
1951 bool SetConnection(uint32 ConnectionState, uint32 Input , uint32 Output)
1952 {
1953 return SetConnectionState(ConnectionState, Input, Output);
1954 }
1955
1956 bool SetIrqEnable(uint32 Irqmode, bool bEnable)
1957 {
1958 //printk("+%s(), Irqmode = %d, bEnable = %d\n", __FUNCTION__, Irqmode, bEnable);
1959 switch (Irqmode)
1960 {
1961 case Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE:
1962 {
1963 Afe_Set_Reg(AFE_IRQ_MCU_CON, (bEnable << Irqmode), (1 << Irqmode));
1964 break;
1965 }
1966 case Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE:
1967 {
1968 if (checkUplinkMEMIfStatus() == false)
1969 {
1970 Afe_Set_Reg(AFE_IRQ_MCU_CON, (bEnable << Irqmode), (1 << Irqmode));
1971 }
1972 break;
1973 }
1974 case Soc_Aud_IRQ_MCU_MODE_IRQ3_MCU_MODE:
1975 {
1976 Afe_Set_Reg(AFE_IRQ_MCU_EN, (bEnable << Irqmode), (1 << Irqmode));
1977
1978 Afe_Set_Reg(AFE_IRQ_MCU_CON, (bEnable << Irqmode), (1 << Irqmode));
1979 break;
1980 }
1981 case Soc_Aud_IRQ_MCU_MODE_IRQ5_MCU_MODE:
1982 {
1983 Afe_Set_Reg(AFE_IRQ_MCU_EN, (bEnable << Irqmode), (1 << Irqmode));
1984
1985 Afe_Set_Reg(AFE_IRQ_MCU_CON, (bEnable << 12), (1 << 12));
1986 break;
1987 }
1988 default:
1989 break;
1990 }
1991 //printk("-%s(), Irqmode = %d, bEnable = %d\n", __FUNCTION__, Irqmode, bEnable);
1992 return true;
1993 }
1994
1995 bool SetIrqMcuSampleRate(uint32 Irqmode, uint32 SampleRate)
1996 {
1997 switch (Irqmode)
1998 {
1999 case Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE:
2000 {
2001 Afe_Set_Reg(AFE_IRQ_MCU_CON, (SampleRateTransform(SampleRate) << 4), 0x000000f0);
2002 break;
2003 }
2004 case Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE:
2005 {
2006 Afe_Set_Reg(AFE_IRQ_MCU_CON, (SampleRateTransform(SampleRate) << 8), 0x00000f00);
2007 break;
2008 }
2009 case Soc_Aud_IRQ_MCU_MODE_IRQ3_MCU_MODE:
2010 {
2011 Afe_Set_Reg(AFE_IRQ_MCU_CON, (SampleRateTransform(SampleRate) << 16), 0x000f0000);
2012 break;
2013 }
2014
2015 default:
2016 return false;
2017 }
2018 return true;
2019 }
2020
2021 bool SetIrqMcuCounter(uint32 Irqmode, uint32 Counter)
2022 {
2023 //printk(" %s Irqmode = %d Counter = %d ", __func__, Irqmode, Counter);
2024 uint32 CurrentCount = 0;
2025 switch (Irqmode)
2026 {
2027 case Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE:
2028 {
2029 Afe_Set_Reg(AFE_IRQ_MCU_CNT1, Counter, 0xffffffff);
2030 break;
2031 }
2032 case Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE:
2033 {
2034 CurrentCount = Afe_Get_Reg(AFE_IRQ_MCU_CNT2);
2035 if (CurrentCount == 0)
2036 {
2037 Afe_Set_Reg(AFE_IRQ_MCU_CNT2, Counter, 0xffffffff);
2038 }
2039 else if ((Counter < CurrentCount))
2040 {
2041 printk("update counter latency CurrentCount = %d Counter = %d", CurrentCount, Counter);
2042 Afe_Set_Reg(AFE_IRQ_MCU_CNT2, Counter, 0xffffffff);
2043 }
2044 else
2045 {
2046 printk("not to add counter latency CurrentCount = %d Counter = %d", CurrentCount, Counter);
2047 }
2048 break;
2049 }
2050 case Soc_Aud_IRQ_MCU_MODE_IRQ3_MCU_MODE:
2051 {
2052 Afe_Set_Reg(AFE_IRQ_MCU_CNT1, Counter << 20, 0xfff00000);
2053 break;
2054 }
2055 case Soc_Aud_IRQ_MCU_MODE_IRQ5_MCU_MODE:
2056 {
2057 Afe_Set_Reg(AFE_IRQ_CNT5, Counter , 0x0003ffff); // ox3BC [0~17] , ex 24bit , stereo, 48BCKs @CNT
2058
2059 break;
2060 }
2061 default:
2062 return false;
2063 }
2064 return true;
2065 }
2066
2067 bool SetMemDuplicateWrite(uint32 InterfaceType, int dupwrite)
2068 {
2069 switch (InterfaceType)
2070 {
2071 case Soc_Aud_Digital_Block_MEM_DAI:
2072 {
2073 Afe_Set_Reg(AFE_DAC_CON1, dupwrite << 29, 1 << 29);
2074 break;
2075 }
2076 case Soc_Aud_Digital_Block_MEM_MOD_DAI:
2077 {
2078 Afe_Set_Reg(AFE_DAC_CON1, dupwrite << 31, 1 << 31);
2079 break;
2080 }
2081 default:
2082 return false;
2083 }
2084 return true;
2085 }
2086
2087
2088 bool Set2ndI2SInConfig(unsigned int sampleRate, bool bIsSlaveMode)
2089 {
2090 AudioDigtalI2S I2S2ndIn_attribute;
2091 memset((void *)&I2S2ndIn_attribute, 0, sizeof(I2S2ndIn_attribute));
2092 I2S2ndIn_attribute.mLR_SWAP = Soc_Aud_LR_SWAP_NO_SWAP;
2093 I2S2ndIn_attribute.mI2S_SLAVE = bIsSlaveMode;
2094 I2S2ndIn_attribute.mI2S_SAMPLERATE = sampleRate;
2095 I2S2ndIn_attribute.mINV_LRCK = Soc_Aud_INV_LRCK_NO_INVERSE;
2096 I2S2ndIn_attribute.mI2S_FMT = Soc_Aud_I2S_FORMAT_I2S;
2097 I2S2ndIn_attribute.mI2S_WLEN = Soc_Aud_I2S_WLEN_WLEN_16BITS;
2098 Set2ndI2SIn(&I2S2ndIn_attribute);
2099 return true;
2100 }
2101
2102 bool Set2ndI2SIn(AudioDigtalI2S *mDigitalI2S)
2103 {
2104 uint32 Audio_I2S_Adc = 0;
2105 memcpy((void *)m2ndI2S, (void *)mDigitalI2S, sizeof(AudioDigtalI2S));
2106 if (!m2ndI2S->mI2S_SLAVE) //Master setting SampleRate only
2107 {
2108 SetSampleRate(Soc_Aud_Digital_Block_MEM_I2S, m2ndI2S->mI2S_SAMPLERATE);
2109 }
2110 Audio_I2S_Adc |= (m2ndI2S->mINV_LRCK << 5);
2111 Audio_I2S_Adc |= (m2ndI2S->mI2S_FMT << 3);
2112 Audio_I2S_Adc |= (m2ndI2S->mI2S_SLAVE << 2);
2113 Audio_I2S_Adc |= (m2ndI2S->mI2S_WLEN << 1);
2114 Audio_I2S_Adc |= (m2ndI2S->mI2S_IN_PAD_SEL << 28);
2115 Audio_I2S_Adc |= 1 << 31;//Default enable phase_shift_fix for better quality
2116 printk("Set2ndI2SIn Audio_I2S_Adc= 0x%x", Audio_I2S_Adc);
2117 Afe_Set_Reg(AFE_I2S_CON, Audio_I2S_Adc, 0xfffffffe);
2118 if (!m2ndI2S->mI2S_SLAVE)
2119 {
2120 Afe_Set_Reg(FPGA_CFG1, 1 << 8, 0x0100);
2121 }
2122 else
2123 {
2124 Afe_Set_Reg(FPGA_CFG1, 0, 0x0100);
2125 }
2126 return true;
2127 }
2128
2129 bool Set2ndI2SInEnable(bool bEnable)
2130 {
2131 printk("Set2ndI2SInEnable bEnable = %d", bEnable);
2132 m2ndI2S->mI2S_EN = bEnable;
2133 Afe_Set_Reg(AFE_I2S_CON, bEnable, 0x1);
2134 mAudioMEMIF[Soc_Aud_Digital_Block_I2S_IN_2]->mState = bEnable;
2135 return true;
2136 }
2137
2138 bool SetI2SASRCConfig(bool bIsUseASRC, unsigned int dToSampleRate)
2139 {
2140 printk("+%s() bIsUseASRC [%d] dToSampleRate [%d]\n", __FUNCTION__, bIsUseASRC, dToSampleRate);
2141 if (true == bIsUseASRC)
2142 {
2143 BUG_ON(!(dToSampleRate == 44100 || dToSampleRate == 48000));
2144 Afe_Set_Reg(AFE_CONN4, 0, 1 << 30);
2145 SetSampleRate(Soc_Aud_Digital_Block_MEM_I2S, dToSampleRate);//To target sample rate
2146 Afe_Set_Reg(AFE_ASRC_CON13, 0, 1 << 16); //0:Stereo 1:Mono
2147 if (dToSampleRate == 44100)
2148 {
2149 Afe_Set_Reg(AFE_ASRC_CON14, 0xDC8000, AFE_MASK_ALL);
2150 Afe_Set_Reg(AFE_ASRC_CON15, 0xA00000, AFE_MASK_ALL);
2151 Afe_Set_Reg(AFE_ASRC_CON17, 0x1FBD, AFE_MASK_ALL);
2152 }
2153 else
2154 {
2155 Afe_Set_Reg(AFE_ASRC_CON14, 0x600000, AFE_MASK_ALL);
2156 Afe_Set_Reg(AFE_ASRC_CON15, 0x400000, AFE_MASK_ALL);
2157 Afe_Set_Reg(AFE_ASRC_CON17, 0xCB2, AFE_MASK_ALL);
2158 }
2159
2160 Afe_Set_Reg(AFE_ASRC_CON16, 0x00075987, AFE_MASK_ALL);//Calibration setting
2161 Afe_Set_Reg(AFE_ASRC_CON20, 0x00001b00, AFE_MASK_ALL);//Calibration setting
2162 }
2163 else
2164 {
2165 Afe_Set_Reg(AFE_CONN4, 1 << 30, 1 << 30);
2166 }
2167 return true;
2168 }
2169
2170 bool SetI2SASRCEnable(bool bEnable)
2171 {
2172 if (true == bEnable)
2173 {
2174 Afe_Set_Reg(AFE_ASRC_CON0, ((1 << 6) | (1 << 0)), ((1 << 6) | (1 << 0)));
2175 }
2176 else
2177 {
2178 uint32 dNeedDisableASM = (Afe_Get_Reg(AFE_ASRC_CON0) & 0x0030) ? 1 : 0;
2179 Afe_Set_Reg(AFE_ASRC_CON0, 0, (1 << 6 | dNeedDisableASM));
2180 }
2181 return true;
2182 }
2183
2184 bool SetMemIfFetchFormatPerSample(uint32 InterfaceType, uint32 eFetchFormat)
2185 {
2186 mAudioMEMIF[InterfaceType]->mFetchFormatPerSample = eFetchFormat;
2187 /*
2188 printk("+%s(), InterfaceType = %d, eFetchFormat = %d, mAudioMEMIF[InterfaceType].mFetchFormatPerSample = %d\n", __FUNCTION__
2189 , InterfaceType, eFetchFormat, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample);*/
2190 switch (InterfaceType)
2191 {
2192 case Soc_Aud_Digital_Block_MEM_DL1:
2193 {
2194 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 16 , 0x00030000);
2195 break;
2196 }
2197 case Soc_Aud_Digital_Block_MEM_DL1_DATA2:
2198 {
2199 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 12 , 0x00003000);
2200 break;
2201 }
2202 case Soc_Aud_Digital_Block_MEM_DL2:
2203 {
2204 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 18 , 0x0000c000);
2205 break;
2206 }
2207 case Soc_Aud_Digital_Block_MEM_I2S:
2208 {
2209 //Afe_Set_Reg(AFE_DAC_CON1, mAudioMEMIF[InterfaceType].mSampleRate << 8 , 0x00000f00);
2210 printk("Unsupport MEM_I2S");
2211 break;
2212 }
2213 case Soc_Aud_Digital_Block_MEM_AWB:
2214 {
2215 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 20, 0x00300000);
2216 break;
2217 }
2218 case Soc_Aud_Digital_Block_MEM_VUL:
2219 {
2220 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 22, 0x00C00000);
2221 break;
2222 }
2223 case Soc_Aud_Digital_Block_MEM_VUL_DATA2:
2224 {
2225 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 14, 0x000C0000);
2226 break;
2227 }
2228 case Soc_Aud_Digital_Block_MEM_DAI:
2229 {
2230 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 24, 0x03000000);
2231 break;
2232 }
2233 case Soc_Aud_Digital_Block_MEM_MOD_DAI:
2234 {
2235 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 26, 0x0C000000);
2236 break;
2237 }
2238 case Soc_Aud_Digital_Block_MEM_HDMI:
2239 {
2240 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 28, 0x30000000);
2241 break;
2242 }
2243 default:
2244 return false;
2245 }
2246 return true;
2247 }
2248
2249 bool SetoutputConnectionFormat(uint32 ConnectionFormat, uint32 Output)
2250 {
2251 //printk("+%s(), Data Format = %d, Output = %d\n", __FUNCTION__, ConnectionFormat, Output);
2252 Afe_Set_Reg(AFE_CONN_24BIT, (ConnectionFormat << Output), (1 << Output));
2253 return true;
2254 }
2255
2256 bool SetHDMIMCLK()
2257 {
2258 uint32 mclksamplerate = mHDMIOutput->mSampleRate * 256;
2259 uint32 hdmi_APll = GetHDMIApLLSource();
2260 uint32 hdmi_mclk_div = 0;
2261 printk("%s \n", __func__);
2262 if (hdmi_APll == APLL_SOURCE_24576)
2263 {
2264 hdmi_APll = 24576000;
2265 }
2266 else
2267 {
2268 hdmi_APll = 22579200;
2269 }
2270 printk("%s hdmi_mclk_div = %d mclksamplerate = %d\n", __func__, hdmi_mclk_div, mclksamplerate);
2271 hdmi_mclk_div = (hdmi_APll / mclksamplerate / 2) - 1;
2272 mHDMIOutput->mHdmiMckDiv = hdmi_mclk_div;
2273 printk("%s hdmi_mclk_div = %d\n", __func__, hdmi_mclk_div);
2274 Afe_Set_Reg(FPGA_CFG1, hdmi_mclk_div << 24, 0x3f000000);
2275
2276 SetCLkMclk(Soc_Aud_I2S3, mHDMIOutput->mSampleRate);
2277 return true;
2278 }
2279
2280 bool SetHDMIBCLK()
2281 {
2282 mHDMIOutput->mBckSamplerate = mHDMIOutput->mSampleRate * mHDMIOutput->mChannels;
2283 printk("%s mBckSamplerate = %d mSampleRate = %d mChannels = %d\n", __func__, mHDMIOutput->mBckSamplerate, mHDMIOutput->mSampleRate , mHDMIOutput->mChannels);
2284 mHDMIOutput->mBckSamplerate *= (mHDMIOutput->mI2S_WLEN + 1) * 16;
2285 printk("%s mBckSamplerate = %d mApllSamplerate = %d\n", __func__, mHDMIOutput->mBckSamplerate, mHDMIOutput->mApllSamplerate);
2286 mHDMIOutput->mHdmiBckDiv = (mHDMIOutput->mApllSamplerate / mHDMIOutput->mBckSamplerate / 2) - 1;
2287 printk("%s mHdmiBckDiv = %d\n", __func__, mHDMIOutput->mHdmiBckDiv);
2288 Afe_Set_Reg(FPGA_CFG1, (mHDMIOutput->mHdmiBckDiv) << 16, 0x00ff0000);
2289 return true;
2290 }
2291
2292 uint32 GetHDMIApLLSource()
2293 {
2294 printk("%s ApllSource = %d \n", __func__, mHDMIOutput->mApllSource);
2295 return mHDMIOutput->mApllSource ;
2296 }
2297
2298 bool SetHDMIApLL(uint32 ApllSource)
2299 {
2300 printk("%s ApllSource = %d", __func__, ApllSource);
2301 if (ApllSource == APLL_SOURCE_24576)
2302 {
2303 Afe_Set_Reg(FPGA_CFG1, 0 << 31, 1 << 31);
2304 mHDMIOutput->mApllSource = APLL_SOURCE_24576;
2305 mHDMIOutput->mApllSamplerate = 24576000;
2306 }
2307 else if (ApllSource == APLL_SOURCE_225792)
2308 {
2309 Afe_Set_Reg(FPGA_CFG1, 1 << 31, 1 << 31);
2310 mHDMIOutput->mApllSource = APLL_SOURCE_225792;
2311 mHDMIOutput->mApllSamplerate = 22579200;
2312 }
2313 return true;
2314 }
2315
2316 bool SetHDMIdatalength(uint32 length)
2317 {
2318 printk("%s length = %d\n ", __func__, length);
2319 mHDMIOutput->mI2S_WLEN = length;
2320 return true;
2321 }
2322
2323 bool SetHDMIsamplerate(uint32 samplerate)
2324 {
2325 uint32 SampleRateinedx = SampleRateTransform(samplerate);
2326 mHDMIOutput->mSampleRate = samplerate;
2327 printk("%s samplerate = %d \n", __func__, samplerate);
2328 switch (SampleRateinedx)
2329 {
2330 case Soc_Aud_I2S_SAMPLERATE_I2S_8K:
2331 SetHDMIApLL(APLL_SOURCE_24576);
2332 break;
2333 case Soc_Aud_I2S_SAMPLERATE_I2S_11K:
2334 SetHDMIApLL(APLL_SOURCE_225792);
2335 break;
2336 case Soc_Aud_I2S_SAMPLERATE_I2S_12K:
2337 SetHDMIApLL(APLL_SOURCE_24576);
2338 break;
2339 case Soc_Aud_I2S_SAMPLERATE_I2S_16K:
2340 SetHDMIApLL(APLL_SOURCE_24576);
2341 break;
2342 case Soc_Aud_I2S_SAMPLERATE_I2S_22K:
2343 SetHDMIApLL(APLL_SOURCE_225792);
2344 break;
2345 case Soc_Aud_I2S_SAMPLERATE_I2S_24K:
2346 SetHDMIApLL(APLL_SOURCE_24576);
2347 break;
2348 case Soc_Aud_I2S_SAMPLERATE_I2S_32K:
2349 SetHDMIApLL(APLL_SOURCE_24576);
2350 break;
2351 case Soc_Aud_I2S_SAMPLERATE_I2S_44K:
2352 SetHDMIApLL(APLL_SOURCE_225792);
2353 break;
2354 case Soc_Aud_I2S_SAMPLERATE_I2S_48K:
2355 SetHDMIApLL(APLL_SOURCE_24576);
2356 break;
2357 case Soc_Aud_I2S_SAMPLERATE_I2S_88K:
2358 SetHDMIApLL(APLL_SOURCE_225792);
2359 break;
2360 case Soc_Aud_I2S_SAMPLERATE_I2S_96K:
2361 SetHDMIApLL(APLL_SOURCE_24576);
2362 break;
2363 default:
2364 break;
2365 }
2366 return true;
2367 }
2368
2369 bool SetTDMLrckWidth(uint32 cycles)
2370 {
2371 printk("%s mt6572 not support!!!\n", __func__);
2372 return true;
2373 }
2374
2375 bool SetTDMbckcycle(uint32 cycles)
2376 {
2377 printk("%s mt6572 not support!!!\n", __func__);
2378 return true;
2379 }
2380
2381 bool SetTDMChannelsSdata(uint32 channels)
2382 {
2383 printk("%s mt6572 not support!!!\n", __func__);
2384 return true;
2385 }
2386
2387 bool SetTDMDatalength(uint32 length)
2388 {
2389 printk("%s mt6572 not support!!!\n", __func__);
2390 return true;
2391 }
2392
2393 bool SetTDMI2Smode(uint32 mode)
2394 {
2395 printk("%s mt6572 not support!!!\n", __func__);
2396 return true;
2397 }
2398
2399 bool SetTDMLrckInverse(bool enable)
2400 {
2401 printk("%s mt6572 not support!!!\n", __func__);
2402 return true;
2403 }
2404 bool SetTDMBckInverse(bool enable)
2405 {
2406 printk("%s mt6572 not support!!!\n", __func__);
2407 return true;
2408 }
2409 bool SetTDMEnable(bool enable)
2410 {
2411 printk("%s mt6572 not support!!!\n", __func__);
2412 return true;
2413 }
2414
2415 /*****************************************************************************
2416 * FUNCTION
2417 * AudDrv_Allocate_DL1_Buffer / AudDrv_Free_DL1_Buffer
2418 *
2419 * DESCRIPTION
2420 * allocate DL1 Buffer
2421 *
2422
2423 ******************************************************************************/
2424 int AudDrv_Allocate_DL1_Buffer(struct device *pDev, kal_uint32 Afe_Buf_Length)
2425 {
2426 #ifdef AUDIO_MEMORY_SRAM
2427 kal_uint32 u4PhyAddr = 0;
2428 #endif
2429 AFE_BLOCK_T *pblock;
2430 printk("%s Afe_Buf_Length = %d \n ", __func__, Afe_Buf_Length);
2431
2432 pblock = &(AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_DL1]->rBlock);
2433 pblock->u4BufferSize = Afe_Buf_Length;
2434
2435 #ifdef AUDIO_MEMORY_SRAM
2436 if (Afe_Buf_Length > AFE_INTERNAL_SRAM_SIZE)
2437 {
2438 PRINTK_AUDDRV("Afe_Buf_Length > AUDDRV_DL1_MAX_BUFFER_LENGTH \n");
2439 return -1;
2440 }
2441 #endif
2442 // allocate memory
2443 {
2444 #ifdef AUDIO_MEMORY_SRAM
2445 // todo , there should be a sram manager to allocate memory for low power.
2446 u4PhyAddr = AFE_INTERNAL_SRAM_PHY_BASE;
2447 pblock->pucPhysBufAddr = u4PhyAddr;
2448
2449 #ifdef AUDIO_MEM_IOREMAP
2450 PRINTK_AUDDRV("AudDrv_Allocate_DL1_Buffer length AUDIO_MEM_IOREMAP = %d\n",
2451 Afe_Buf_Length);
2452 pblock->pucVirtBufAddr = (kal_uint8 *)Get_Afe_SramBase_Pointer();
2453 #else
2454 pblock->pucVirtBufAddr = AFE_INTERNAL_SRAM_VIR_BASE;
2455 #endif
2456
2457 #else
2458 PRINTK_AUDDRV("AudDrv_Allocate_DL1_Buffer use dram");
2459 pblock->pucVirtBufAddr = dma_alloc_coherent(pDev, pblock->u4BufferSize, &pblock->pucPhysBufAddr, GFP_KERNEL);
2460 #endif
2461 }
2462 PRINTK_AUDDRV("AudDrv_Allocate_DL1_Buffer Afe_Buf_Length = %dpucVirtBufAddr = %p\n", Afe_Buf_Length, pblock->pucVirtBufAddr);
2463
2464 // check 32 bytes align
2465 if ((pblock->pucPhysBufAddr & 0x1f) != 0)
2466 {
2467 PRINTK_AUDDRV("[Auddrv] AudDrv_Allocate_DL1_Buffer is not aligned (0x%x) \n", pblock->pucPhysBufAddr);
2468 }
2469
2470 pblock->u4SampleNumMask = 0x001f; // 32 byte align
2471 pblock->u4WriteIdx = 0;
2472 pblock->u4DMAReadIdx = 0;
2473 pblock->u4DataRemained = 0;
2474 pblock->u4fsyncflag = false;
2475 pblock->uResetFlag = true;
2476
2477 // set sram address top hardware
2478 Afe_Set_Reg(AFE_DL1_BASE , pblock->pucPhysBufAddr , 0xffffffff);
2479 Afe_Set_Reg(AFE_DL1_END , pblock->pucPhysBufAddr + (Afe_Buf_Length - 1), 0xffffffff);
2480 memset(pblock->pucVirtBufAddr, 0, pblock->u4BufferSize);
2481 return 0;
2482 }
2483
2484 int AudDrv_Allocate_mem_Buffer(struct device *pDev, Soc_Aud_Digital_Block MemBlock, uint32 Buffer_length)
2485 {
2486 switch (MemBlock)
2487 {
2488 case Soc_Aud_Digital_Block_MEM_DL1:
2489 case Soc_Aud_Digital_Block_MEM_DL2:
2490 case Soc_Aud_Digital_Block_MEM_DAI:
2491 case Soc_Aud_Digital_Block_MEM_AWB:
2492 case Soc_Aud_Digital_Block_MEM_MOD_DAI:
2493 case Soc_Aud_Digital_Block_MEM_DL1_DATA2:
2494 case Soc_Aud_Digital_Block_MEM_VUL_DATA2:
2495 case Soc_Aud_Digital_Block_MEM_HDMI:
2496 {
2497 printk("%s MemBlock =%d Buffer_length = %d\n ", __func__, MemBlock, Buffer_length);
2498 if (Audio_dma_buf[MemBlock] != NULL)
2499 {
2500 printk("AudDrv_Allocate_mem_Buffer MemBlock = %d dma_alloc_coherent\n", MemBlock);
2501 if (Audio_dma_buf[MemBlock] ->area == NULL)
2502 {
2503 printk("dma_alloc_coherent\n");
2504 Audio_dma_buf[MemBlock] ->area = dma_alloc_coherent(pDev, Buffer_length,
2505 &Audio_dma_buf[MemBlock] ->addr, GFP_KERNEL);
2506 if (Audio_dma_buf[MemBlock] ->area)
2507 {
2508 Audio_dma_buf[MemBlock] ->bytes = Buffer_length;
2509 }
2510 }
2511 printk("area = %p \n", Audio_dma_buf[MemBlock] ->area);
2512 }
2513 }
2514 break;
2515 case Soc_Aud_Digital_Block_MEM_VUL:
2516 {
2517 printk("%s MemBlock =%d Buffer_length = %d\n ", __func__, MemBlock, Buffer_length);
2518 if (Audio_dma_buf[MemBlock] != NULL)
2519 {
2520 printk("AudDrv_Allocate_mem_Buffer MemBlock = %d dma_alloc_coherent\n", MemBlock);
2521 if (Audio_dma_buf[MemBlock] ->area == NULL)
2522 {
2523 printk("dma_alloc_coherent\n");
2524 Audio_dma_buf[MemBlock] ->area = dma_alloc_coherent(pDev, Buffer_length,
2525 &Audio_dma_buf[MemBlock] ->addr, GFP_KERNEL);
2526 if (Audio_dma_buf[MemBlock] ->area)
2527 {
2528 Audio_dma_buf[MemBlock] ->bytes = Buffer_length;
2529 }
2530 }
2531 printk("area = %p \n", Audio_dma_buf[MemBlock] ->area);
2532 }
2533 break;
2534 }
2535 case Soc_Aud_Digital_Block_MEM_I2S:
2536 printk("currently not support \n");
2537 default:
2538 printk("%s not support \n", __func__);
2539 }
2540 return true;
2541 }
2542
2543 AFE_MEM_CONTROL_T *Get_Mem_ControlT(Soc_Aud_Digital_Block MemBlock)
2544 {
2545 if (MemBlock >= 0 && MemBlock <= Soc_Aud_Digital_Block_MEM_HDMI)
2546 {
2547 return AFE_Mem_Control_context[MemBlock];
2548 }
2549 else
2550 {
2551 printk("%s error \n", __func__);
2552 return NULL;
2553 }
2554 }
2555
2556 bool SetMemifSubStream(Soc_Aud_Digital_Block MemBlock , struct snd_pcm_substream *substream)
2557 {
2558 substreamList *head;
2559 substreamList *temp = NULL;
2560 unsigned long flags;
2561 printk("+%s MemBlock = %d substream = %p \n ", __func__, MemBlock, substream);
2562 spin_lock_irqsave(&afe_mem_lock, flags);
2563 head = AFE_Mem_Control_context[MemBlock]->substreamL;
2564 if (head == NULL) // frst item is NULL
2565 {
2566 //printk("%s head == NULL\n ", __func__);
2567 temp = kzalloc(sizeof(substreamList), GFP_ATOMIC);
2568 temp->substream = substream;
2569 temp->next = NULL;
2570 AFE_Mem_Control_context[MemBlock]->substreamL = temp;
2571 }
2572 else // find out Null pointer
2573 {
2574 while (head->next != NULL)
2575 {
2576 head = head->next;
2577 }
2578 // head->next is NULL
2579 temp = kzalloc(sizeof(substreamList), GFP_ATOMIC);
2580 temp->substream = substream;
2581 temp->next = NULL;
2582 head->next = temp;
2583 }
2584 spin_unlock_irqrestore(&afe_mem_lock, flags);
2585 printk("-%s MemBlock = %d \n ", __func__, MemBlock);
2586 //DumpMemifSubStream();
2587 return true;
2588 }
2589
2590 bool ClearMemBlock(Soc_Aud_Digital_Block MemBlock)
2591 {
2592 if (MemBlock >= 0 && MemBlock <= Soc_Aud_Digital_Block_MEM_HDMI)
2593 {
2594 AFE_BLOCK_T *pBlock = &AFE_Mem_Control_context[MemBlock]->rBlock;
2595 memset(pBlock->pucVirtBufAddr, 0, pBlock->u4BufferSize);
2596 pBlock->u4WriteIdx = 0;
2597 pBlock->u4DMAReadIdx = 0;
2598 pBlock->u4DataRemained = 0;
2599 pBlock->u4fsyncflag = false;
2600 pBlock->uResetFlag = true;
2601 }
2602 else
2603 {
2604 printk("%s error \n", __func__);
2605 return NULL;
2606 }
2607 return true;
2608 }
2609
2610 bool RemoveMemifSubStream(Soc_Aud_Digital_Block MemBlock, struct snd_pcm_substream *substream)
2611 {
2612 substreamList *head;
2613 substreamList *temp = NULL;
2614 unsigned long flags;
2615 spin_lock_irqsave(&afe_mem_lock, flags);
2616 head = AFE_Mem_Control_context[MemBlock]->substreamL;
2617 printk("+ %s MemBlock = %d substream = %p \n ", __func__, MemBlock, substream);
2618 if (head == NULL) // no object
2619 {
2620 // do nothing
2621 }
2622 else
2623 {
2624 // condition for first item hit and ony 1 item
2625 if (head->substream == substream)
2626 {
2627 //printk("%s head->substream = %p \n ", __func__, head->substream);
2628 AFE_Mem_Control_context[MemBlock]->substreamL = head->next;
2629 spin_unlock_irqrestore(&afe_mem_lock, flags);
2630 kfree(head);
2631 //DumpMemifSubStream();
2632 return true;
2633 }
2634 temp = head;
2635 head = head->next;
2636 while (head)
2637 {
2638 if (head->substream == substream)
2639 {
2640 temp->next = head->next;
2641 if (head)
2642 {
2643 kfree(head);
2644 head = NULL;
2645 }
2646 break;
2647 }
2648 temp = head;
2649 head = head->next;
2650 }
2651 }
2652 spin_unlock_irqrestore(&afe_mem_lock, flags);
2653 //DumpMemifSubStream();
2654
2655 if (AFE_Mem_Control_context[MemBlock]->substreamL == NULL)
2656 {
2657 ClearMemBlock(MemBlock);
2658 return true;
2659 }
2660 else
2661 {
2662 printk("%s substreram is not NULL MemBlock = %d \n", __func__, MemBlock);
2663 return true;
2664 }
2665 printk("- %s MemBlock = %d \n ", __func__, MemBlock);
2666 }
2667
2668 static unsigned long dl1_flags = 0;
2669 void Auddrv_Dl1_Spinlock_lock(void)
2670 {
2671 spin_lock_irqsave(&auddrv_dl1_lock, dl1_flags);
2672 }
2673
2674 void Auddrv_Dl1_Spinlock_unlock(void)
2675 {
2676 spin_unlock_irqrestore(&auddrv_dl1_lock, dl1_flags);
2677 }
2678
2679 static unsigned long ul1_flags = 0;
2680 void Auddrv_UL1_Spinlock_lock(void)
2681 {
2682 spin_lock_irqsave(&auddrv_ul1_lock, ul1_flags);
2683 }
2684 void Auddrv_UL1_Spinlock_unlock(void)
2685 {
2686 spin_unlock_irqrestore(&auddrv_ul1_lock, ul1_flags);
2687 }
2688
2689 void Auddrv_HDMI_Interrupt_Handler(void) // irq5 ISR handler
2690 {
2691 // K2 removed
2692 }
2693
2694
2695
2696 static void TraverseAllSubStream(substreamList *Head)
2697 {
2698 //printk("+%s\n",__func__);
2699 substreamList *temp = Head;
2700 while (temp != NULL)
2701 {
2702 //printk("temp = %p temp->substream = %p\n", temp, temp->substream);
2703 if (temp->substream != NULL)
2704 {
2705 snd_pcm_period_elapsed(temp->substream);
2706 }
2707 temp = temp->next;
2708 }
2709 //printk("-%s\n",__func__);
2710 }
2711
2712 void Auddrv_AWB_Interrupt_Handler(void)
2713 {
2714 AFE_MEM_CONTROL_T *Mem_Block = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_AWB];
2715 kal_uint32 HW_Cur_ReadIdx = 0;
2716 kal_uint32 MaxCopySize = 0;
2717 kal_int32 Hw_Get_bytes = 0;
2718 substreamList *Temp = NULL;
2719 AFE_BLOCK_T *mBlock = NULL;
2720 unsigned long flags;
2721
2722 if (Mem_Block == NULL)
2723 {
2724 return;
2725 }
2726 if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_AWB) == false)
2727 {
2728 //printk("%s(), GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_AWB) == false, return\n ", __func__);
2729 return;
2730 }
2731 mBlock = &Mem_Block->rBlock;
2732 HW_Cur_ReadIdx = Align64ByteSize(Afe_Get_Reg(AFE_AWB_CUR));
2733 PRINTK_AUD_AWB("Auddrv_AWB_Interrupt_Handler HW_Cur_ReadIdx = 0x%x\n ", HW_Cur_ReadIdx);
2734
2735 if (CheckSize(HW_Cur_ReadIdx))
2736 {
2737 return;
2738 }
2739 if (mBlock->pucVirtBufAddr == NULL)
2740 {
2741 return;
2742 }
2743
2744 MaxCopySize = Get_Mem_MaxCopySize(Soc_Aud_Digital_Block_MEM_AWB);
2745 PRINTK_AUD_AWB("1 mBlock = %p MaxCopySize = 0x%x u4BufferSize = 0x%x \n", mBlock, MaxCopySize, mBlock->u4BufferSize);
2746 if (MaxCopySize)
2747 {
2748 if (MaxCopySize > mBlock->u4BufferSize)
2749 {
2750 MaxCopySize = mBlock->u4BufferSize;
2751 }
2752 mBlock->u4DataRemained -= MaxCopySize;
2753 mBlock->u4DMAReadIdx += MaxCopySize;
2754 mBlock->u4DMAReadIdx %= mBlock->u4BufferSize;
2755 Clear_Mem_CopySize(Soc_Aud_Digital_Block_MEM_AWB);
2756 PRINTK_AUD_AWB("update read pointer u4DMAReadIdx:0x%x, u4WriteIdx:0x%x, pucPhysBufAddr:0x%x mBlock->u4MaxCopySize =0x%x\n",
2757 mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->pucPhysBufAddr, mBlock->u4MaxCopySize);
2758 }
2759
2760 // HW already fill in
2761 Hw_Get_bytes = (HW_Cur_ReadIdx - mBlock->pucPhysBufAddr) - mBlock->u4WriteIdx;
2762 if (Hw_Get_bytes < 0)
2763 {
2764 Hw_Get_bytes += mBlock->u4BufferSize;
2765 }
2766
2767 PRINTK_AUD_AWB("+Auddrv_Handle_Mem_context Hw_Get_bytes:0x%x, HW_Cur_ReadIdx:0x%x, u4DMAReadIdx:0x%x, u4WriteIdx:0x%x, pucPhysBufAddr:0x%x mBlock->u4MaxCopySize =0x%x mBlock->u4DataRemained = 0x%x\n",
2768 Hw_Get_bytes, HW_Cur_ReadIdx, mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->pucPhysBufAddr, mBlock->u4MaxCopySize, mBlock->u4DataRemained);
2769
2770 mBlock->u4WriteIdx += Hw_Get_bytes;
2771 mBlock->u4WriteIdx %= mBlock->u4BufferSize;
2772 mBlock->u4DataRemained += Hw_Get_bytes;
2773 // buffer overflow
2774 if (mBlock->u4DataRemained > mBlock->u4BufferSize)
2775 {
2776 printk("Auddrv_Handle_Mem_context buffer overflow u4DMAReadIdx:%x, u4WriteIdx:%x, u4DataRemained:%x, u4BufferSize:%x \n",
2777 mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->u4DataRemained, mBlock->u4BufferSize);
2778 mBlock->u4DataRemained -= mBlock->u4BufferSize;
2779 }
2780 Mem_Block->interruptTrigger = 1;
2781
2782 spin_lock_irqsave(&afe_mem_lock, flags);
2783 Temp = Mem_Block->substreamL;
2784 spin_unlock_irqrestore(&afe_mem_lock, flags);
2785 if(Temp != NULL)
2786 {
2787 TraverseAllSubStream(Temp);
2788 }
2789 PRINTK_AUD_AWB("-Auddrv_Handle_Mem_context u4DMAReadIdx:0x%x, u4WriteIdx:0x%x mBlock->u4DataRemained = 0x%x \n", mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->u4DataRemained);
2790
2791 }
2792
2793 void Auddrv_DAI_Interrupt_Handler(void)
2794 {
2795 AFE_MEM_CONTROL_T *Mem_Block = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_DAI];
2796 kal_uint32 HW_Cur_ReadIdx = 0;
2797 kal_int32 Hw_Get_bytes = 0;
2798 AFE_BLOCK_T *mBlock = NULL;
2799 substreamList *Temp = NULL;
2800 unsigned long flags;
2801
2802 if (Mem_Block == NULL)
2803 {
2804 return;
2805 }
2806 if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DAI) == false)
2807 {
2808 //printk("%s(), GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DAI) == false, return\n ", __func__);
2809 return;
2810 }
2811
2812 mBlock = &Mem_Block->rBlock;
2813 HW_Cur_ReadIdx = Align64ByteSize(Afe_Get_Reg(AFE_DAI_CUR));
2814
2815 if (CheckSize(HW_Cur_ReadIdx))
2816 {
2817 return;
2818 }
2819 if (mBlock->pucVirtBufAddr == NULL)
2820 {
2821 return;
2822 }
2823
2824 // HW already fill in
2825 Hw_Get_bytes = (HW_Cur_ReadIdx - mBlock->pucPhysBufAddr) - mBlock->u4WriteIdx;
2826 if (Hw_Get_bytes < 0)
2827 {
2828 Hw_Get_bytes += mBlock->u4BufferSize;
2829 }
2830
2831 PRINTK_AUD_DAI("Auddrv_DAI_Interrupt_Handler Hw_Get_bytes:0x%x, HW_Cur_ReadIdx:0x%x, u4DMAReadIdx:0x%x, u4WriteIdx:0x%x, pucPhysBufAddr:0x%x Mem_Block->MemIfNum = %d \n",
2832 Hw_Get_bytes, HW_Cur_ReadIdx, mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->pucPhysBufAddr, Mem_Block->MemIfNum);
2833
2834 mBlock->u4WriteIdx += Hw_Get_bytes;
2835 mBlock->u4WriteIdx %= mBlock->u4BufferSize;
2836 mBlock->u4DataRemained += Hw_Get_bytes;
2837
2838 // buffer overflow
2839 if (mBlock->u4DataRemained > mBlock->u4BufferSize)
2840 {
2841 PRINTK_AUD_DAI("Auddrv_DAI_Interrupt_Handler buffer overflow u4DMAReadIdx:%x, u4WriteIdx:%x, u4DataRemained:%x, u4BufferSize:%x \n",
2842 mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->u4DataRemained, mBlock->u4BufferSize);
2843 /*
2844 mBlock->u4DataRemained = mBlock->u4BufferSize / 2;
2845 mBlock->u4DMAReadIdx = mBlock->u4WriteIdx - mBlock->u4BufferSize / 2;
2846 if (mBlock->u4DMAReadIdx < 0)
2847 {
2848 mBlock->u4DMAReadIdx += mBlock->u4BufferSize;
2849 }*/
2850 }
2851 Mem_Block->interruptTrigger = 1;
2852
2853 spin_lock_irqsave(&afe_mem_lock, flags);
2854 Temp = Mem_Block->substreamL;
2855 spin_unlock_irqrestore(&afe_mem_lock, flags);
2856 if (Temp != NULL)
2857 {
2858 if (Temp->substream != NULL)
2859 {
2860 snd_pcm_period_elapsed(Temp->substream);
2861 }
2862 }
2863 }
2864
2865 void Auddrv_DL1_Interrupt_Handler(void) // irq1 ISR handler
2866 {
2867 #define MAGIC_NUMBER 0xFFFFFFC0
2868
2869 kal_int32 Afe_consumed_bytes = 0;
2870 kal_int32 HW_memory_index = 0;
2871 kal_int32 HW_Cur_ReadIdx = 0;
2872 AFE_BLOCK_T *Afe_Block = &(AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_DL1]->rBlock);
2873 substreamList *Temp = NULL;
2874 unsigned long flags;
2875 if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1) == false)
2876 {
2877 //printk("%s(), GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1) == false, return\n ", __func__);
2878 return;
2879 }
2880
2881 HW_Cur_ReadIdx = Afe_Get_Reg(AFE_DL1_CUR);
2882 if (HW_Cur_ReadIdx == 0)
2883 {
2884 PRINTK_AUDDRV("[Auddrv] HW_Cur_ReadIdx ==0 \n");
2885 HW_Cur_ReadIdx = Afe_Block->pucPhysBufAddr;
2886 }
2887 HW_memory_index = (HW_Cur_ReadIdx - Afe_Block->pucPhysBufAddr);
2888
2889 PRINTK_AUD_DL1("[Auddrv] HW_Cur_ReadIdx=0x%x HW_memory_index = 0x%x Afe_Block->pucPhysBufAddr = 0x%x\n",
2890 HW_Cur_ReadIdx, HW_memory_index, Afe_Block->pucPhysBufAddr);
2891
2892
2893 // get hw consume bytes
2894 if (HW_memory_index > Afe_Block->u4DMAReadIdx)
2895 {
2896 Afe_consumed_bytes = HW_memory_index - Afe_Block->u4DMAReadIdx;
2897 }
2898 else
2899 {
2900 Afe_consumed_bytes = Afe_Block->u4BufferSize + HW_memory_index - Afe_Block->u4DMAReadIdx ;
2901 }
2902
2903 Afe_consumed_bytes = Afe_consumed_bytes & MAGIC_NUMBER; //64 bytes align
2904
2905 /*
2906 if ((Afe_consumed_bytes & 0x1f) != 0)
2907 {
2908 printk("[Auddrv] DMA address is not aligned 32 bytes \n");
2909 }*/
2910
2911 PRINTK_AUD_DL1("+Auddrv_DL1_Interrupt_Handler ReadIdx:%x WriteIdx:%x, DataRemained:%x, Afe_consumed_bytes:%x HW_memory_index = %x \n",
2912 Afe_Block->u4DMAReadIdx, Afe_Block->u4WriteIdx, Afe_Block->u4DataRemained, Afe_consumed_bytes, HW_memory_index);
2913
2914 if (Afe_Block->u4DataRemained < Afe_consumed_bytes || Afe_Block->u4DataRemained <= 0 || Afe_Block->u4DataRemained > Afe_Block->u4BufferSize)
2915 {
2916 printk("DL_Handling underflow \n");
2917 }
2918 else
2919 {
2920
2921 PRINTK_AUD_DL1("+DL_Handling normal ReadIdx:%x ,DataRemained:%x, WriteIdx:%x \n",
2922 Afe_Block->u4DMAReadIdx, Afe_Block->u4DataRemained, Afe_Block->u4WriteIdx);
2923 Afe_Block->u4DataRemained -= Afe_consumed_bytes;
2924 Afe_Block->u4DMAReadIdx += Afe_consumed_bytes;
2925 Afe_Block->u4DMAReadIdx %= Afe_Block->u4BufferSize;
2926 }
2927 AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_DL1]->interruptTrigger = 1 ;
2928 PRINTK_AUD_DL1("-DL_Handling normal ReadIdx:%x ,DataRemained:%x, WriteIdx:%x \n",
2929 Afe_Block->u4DMAReadIdx, Afe_Block->u4DataRemained, Afe_Block->u4WriteIdx);
2930 spin_lock_irqsave(&afe_mem_lock, flags);
2931 Temp = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_DL1]->substreamL;
2932 spin_unlock_irqrestore(&afe_mem_lock, flags);
2933 if (Temp != NULL)
2934 {
2935 if (Temp->substream != NULL)
2936 {
2937 snd_pcm_period_elapsed(Temp->substream);
2938 }
2939 }
2940 }
2941
2942 struct snd_dma_buffer *Get_Mem_Buffer(Soc_Aud_Digital_Block MemBlock)
2943 {
2944 printk("%s MemBlock = %d\n", __func__, MemBlock);
2945 switch (MemBlock)
2946 {
2947 case Soc_Aud_Digital_Block_MEM_DL1:
2948 return Audio_dma_buf[MemBlock] ;
2949 case Soc_Aud_Digital_Block_MEM_DL2:
2950 return Audio_dma_buf[MemBlock] ;
2951 case Soc_Aud_Digital_Block_MEM_VUL:
2952 return Audio_dma_buf[MemBlock] ;
2953 case Soc_Aud_Digital_Block_MEM_DAI:
2954 return Audio_dma_buf[MemBlock] ;
2955 case Soc_Aud_Digital_Block_MEM_AWB:
2956 return Audio_dma_buf[MemBlock] ;
2957 case Soc_Aud_Digital_Block_MEM_MOD_DAI:
2958 return Audio_dma_buf[MemBlock] ;
2959 case Soc_Aud_Digital_Block_MEM_DL1_DATA2:
2960 return Audio_dma_buf[MemBlock] ;
2961 case Soc_Aud_Digital_Block_MEM_VUL_DATA2:
2962 return Audio_dma_buf[MemBlock] ;
2963 case Soc_Aud_Digital_Block_MEM_HDMI:
2964 return Audio_dma_buf[MemBlock];
2965 case Soc_Aud_Digital_Block_MEM_I2S:
2966 printk("currently not support \n");
2967 break;
2968 default:
2969 break;
2970 }
2971 return NULL;
2972 }
2973
2974 void Auddrv_UL1_Interrupt_Handler(void)
2975 {
2976 AFE_MEM_CONTROL_T *Mem_Block = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_VUL];
2977
2978 kal_uint32 HW_Cur_ReadIdx = 0;
2979 kal_int32 Hw_Get_bytes = 0;
2980 AFE_BLOCK_T *mBlock = NULL;
2981 substreamList *Temp = NULL;
2982 unsigned long flags;
2983 if (Mem_Block == NULL)
2984 {
2985 printk("Mem_Block == NULL \n ");
2986 return;
2987 }
2988 if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_VUL) == false)
2989 {
2990 //printk("%s(), GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_VUL) == false, return\n ", __func__);
2991 return;
2992 }
2993
2994 mBlock = &Mem_Block->rBlock;
2995 HW_Cur_ReadIdx = Align64ByteSize(Afe_Get_Reg(AFE_VUL_CUR));
2996 if (CheckSize(HW_Cur_ReadIdx))
2997 {
2998 return;
2999 }
3000 if (mBlock->pucVirtBufAddr == NULL)
3001 {
3002 return;
3003 }
3004
3005 // HW already fill in
3006 Hw_Get_bytes = (HW_Cur_ReadIdx - mBlock->pucPhysBufAddr) - mBlock->u4WriteIdx;
3007 if (Hw_Get_bytes < 0)
3008 {
3009 Hw_Get_bytes += mBlock->u4BufferSize;
3010 }
3011
3012 PRINTK_AUD_UL1("Auddrv_Handle_Mem_context Hw_Get_bytes:%x, HW_Cur_ReadIdx:%x, u4DMAReadIdx:%x, u4WriteIdx:0x%x, pucPhysBufAddr:%x Mem_Block->MemIfNum = %d \n",
3013 Hw_Get_bytes, HW_Cur_ReadIdx, mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->pucPhysBufAddr, Mem_Block->MemIfNum);
3014
3015 mBlock->u4WriteIdx += Hw_Get_bytes;
3016 mBlock->u4WriteIdx %= mBlock->u4BufferSize;
3017 mBlock->u4DataRemained += Hw_Get_bytes;
3018
3019 // buffer overflow
3020 if (mBlock->u4DataRemained > mBlock->u4BufferSize)
3021 {
3022 printk("Auddrv_Handle_Mem_context buffer overflow u4DMAReadIdx:%x, u4WriteIdx:%x, u4DataRemained:%x, u4BufferSize:%x \n",
3023 mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->u4DataRemained, mBlock->u4BufferSize);
3024 }
3025 AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_VUL]->interruptTrigger = 1;
3026
3027 spin_lock_irqsave(&afe_mem_lock, flags);
3028 Temp = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_VUL]->substreamL;
3029 spin_unlock_irqrestore(&afe_mem_lock, flags);
3030 if (Temp != NULL)
3031 {
3032 if (Temp->substream != NULL)
3033 {
3034 snd_pcm_period_elapsed(Temp->substream);
3035 }
3036 }
3037 }
3038
3039 void Clear_Mem_CopySize(Soc_Aud_Digital_Block MemBlock)
3040 {
3041 substreamList *head;
3042 unsigned long flags;
3043 spin_lock_irqsave(&afe_mem_lock, flags);
3044 head = AFE_Mem_Control_context[MemBlock]->substreamL;
3045 //printk("+%s MemBlock = %d \n ", __func__, MemBlock);
3046 while (head != NULL) // frst item is NULL
3047 {
3048 head->u4MaxCopySize = 0;
3049 head = head->next;
3050 }
3051 spin_unlock_irqrestore(&afe_mem_lock, flags);
3052 //printk("-%s MemBlock = %d \n ", __func__, MemBlock);
3053 }
3054
3055 kal_uint32 Get_Mem_CopySizeByStream(Soc_Aud_Digital_Block MemBlock, struct snd_pcm_substream *substream)
3056 {
3057 substreamList *head;
3058 unsigned long flags;
3059 kal_uint32 MaxCopySize;
3060 spin_lock_irqsave(&afe_mem_lock, flags);
3061 head = AFE_Mem_Control_context[MemBlock]->substreamL;
3062 //printk("+%s MemBlock = %d \n ", __func__, MemBlock);
3063 while (head != NULL) // frst item is NULL
3064 {
3065 if (head->substream == substream)
3066 {
3067 MaxCopySize = head->u4MaxCopySize;
3068 spin_unlock_irqrestore(&afe_mem_lock, flags);
3069 return MaxCopySize;
3070 }
3071 head = head->next;
3072 }
3073 spin_unlock_irqrestore(&afe_mem_lock, flags);
3074 //printk("-%s MemBlock = %d \n ", __func__, MemBlock);
3075 return 0;
3076 }
3077
3078 kal_uint32 Get_Mem_MaxCopySize(Soc_Aud_Digital_Block MemBlock)
3079 {
3080 substreamList *head;
3081 unsigned long flags;
3082 kal_uint32 MaxCopySize;
3083 spin_lock_irqsave(&afe_mem_lock, flags);
3084 head = AFE_Mem_Control_context[MemBlock]->substreamL;
3085 MaxCopySize = 0;
3086 //printk("+%s MemBlock = %d \n ", __func__, MemBlock);
3087 while (head != NULL) // frst item is NULL
3088 {
3089 if (MaxCopySize < head->u4MaxCopySize)
3090 {
3091 MaxCopySize = head->u4MaxCopySize;
3092 }
3093 head = head->next;
3094 }
3095 spin_unlock_irqrestore(&afe_mem_lock, flags);
3096 //printk("-%s MemBlock = %d \n ", __func__, MemBlock);
3097 return MaxCopySize;
3098 }
3099
3100 void Set_Mem_CopySizeByStream(Soc_Aud_Digital_Block MemBlock, struct snd_pcm_substream *substream, uint32 size)
3101 {
3102 substreamList *head;
3103 unsigned long flags;
3104 spin_lock_irqsave(&afe_mem_lock, flags);
3105 head = AFE_Mem_Control_context[MemBlock]->substreamL;
3106 //printk("+%s MemBlock = %d \n ", __func__, MemBlock);
3107 while (head != NULL) // frst item is NULL
3108 {
3109 if (head->substream == substream)
3110 {
3111 head->u4MaxCopySize += size;
3112 break;
3113 }
3114 head = head->next;
3115 }
3116 spin_unlock_irqrestore(&afe_mem_lock, flags);
3117 //printk("-%s MemBlock = %d \n ", __func__, MemBlock);
3118 }
3119
3120 void Auddrv_UL2_Interrupt_Handler(void)
3121 {
3122 AFE_MEM_CONTROL_T *Mem_Block = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_VUL_DATA2];
3123 kal_uint32 HW_Cur_ReadIdx = 0;
3124 kal_int32 Hw_Get_bytes = 0;
3125 AFE_BLOCK_T *mBlock = NULL;
3126 substreamList *Temp = NULL;
3127 unsigned long flags;
3128
3129 PRINTK_AUD_UL2("Auddrv_UL2_Interrupt_Handler \n ");
3130
3131 if (Mem_Block == NULL)
3132 {
3133 printk("Mem_Block == NULL \n ");
3134 return;
3135 }
3136 if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_VUL_DATA2) == false)
3137 {
3138 //printk("%s(), GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_VUL_DATA2) == false, return\n ", __func__);
3139 return;
3140 }
3141
3142 mBlock = &Mem_Block->rBlock;
3143 HW_Cur_ReadIdx = Align64ByteSize(Afe_Get_Reg(AFE_VUL_D2_CUR));
3144 PRINTK_AUD_UL2("Auddrv_UL2_Interrupt_Handler HW_Cur_ReadIdx = 0x%x\n ", HW_Cur_ReadIdx);
3145
3146 if (CheckSize(HW_Cur_ReadIdx))
3147 {
3148 return;
3149 }
3150 if (mBlock->pucVirtBufAddr == NULL)
3151 {
3152 return;
3153 }
3154
3155 // HW already fill in
3156 Hw_Get_bytes = (HW_Cur_ReadIdx - mBlock->pucPhysBufAddr) - mBlock->u4WriteIdx;
3157 if (Hw_Get_bytes < 0)
3158 {
3159 Hw_Get_bytes += mBlock->u4BufferSize;
3160 }
3161
3162 PRINTK_AUD_UL2("Auddrv_UL2_Interrupt_Handler Hw_Get_bytes:%x, HW_Cur_ReadIdx:%x, u4DMAReadIdx:%x, u4WriteIdx:0x%x, pucPhysBufAddr:%x Mem_Block->MemIfNum = %d \n",
3163 Hw_Get_bytes, HW_Cur_ReadIdx, mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->pucPhysBufAddr, Mem_Block->MemIfNum);
3164
3165 mBlock->u4WriteIdx += Hw_Get_bytes;
3166 mBlock->u4WriteIdx %= mBlock->u4BufferSize;
3167 mBlock->u4DataRemained += Hw_Get_bytes;
3168
3169 // buffer overflow
3170 if (mBlock->u4DataRemained > mBlock->u4BufferSize)
3171 {
3172 PRINTK_AUD_UL1("Auddrv_UL2_Interrupt_Handler buffer overflow u4DMAReadIdx:%x, u4WriteIdx:%x, u4DataRemained:%x, u4BufferSize:%x \n",
3173 mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->u4DataRemained, mBlock->u4BufferSize);
3174 mBlock->u4DataRemained = mBlock->u4BufferSize / 2;
3175 mBlock->u4DMAReadIdx = mBlock->u4WriteIdx - mBlock->u4BufferSize / 2;
3176 if (mBlock->u4DMAReadIdx < 0)
3177 {
3178 mBlock->u4DMAReadIdx += mBlock->u4BufferSize;
3179 }
3180 }
3181 AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_VUL_DATA2]->interruptTrigger = 1;
3182 spin_lock_irqsave(&afe_mem_lock, flags);
3183 Temp = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_VUL_DATA2]->substreamL;
3184 spin_unlock_irqrestore(&afe_mem_lock, flags);
3185 if (Temp != NULL)
3186 {
3187 if (Temp->substream != NULL)
3188 {
3189 snd_pcm_period_elapsed(Temp->substream);
3190 }
3191 }
3192 }
3193
3194 bool BackUp_Audio_Register(void)
3195 {
3196 AudDrv_Clk_On();
3197 mAudioRegCache.REG_AUDIO_TOP_CON1 = Afe_Get_Reg(AUDIO_TOP_CON1);
3198 mAudioRegCache.REG_AUDIO_TOP_CON2 = Afe_Get_Reg(AUDIO_TOP_CON2);
3199 mAudioRegCache.REG_AUDIO_TOP_CON3 = Afe_Get_Reg(AUDIO_TOP_CON3);
3200 mAudioRegCache.REG_AFE_DAC_CON0 = Afe_Get_Reg(AFE_DAC_CON0);
3201 mAudioRegCache.REG_AFE_DAC_CON1 = Afe_Get_Reg(AFE_DAC_CON1);
3202 mAudioRegCache.REG_AFE_I2S_CON = Afe_Get_Reg(AFE_I2S_CON);
3203 mAudioRegCache.REG_AFE_DAIBT_CON0 = Afe_Get_Reg(AFE_DAIBT_CON0);
3204 mAudioRegCache.REG_AFE_CONN0 = Afe_Get_Reg(AFE_CONN0);
3205 mAudioRegCache.REG_AFE_CONN1 = Afe_Get_Reg(AFE_CONN1);
3206 mAudioRegCache.REG_AFE_CONN2 = Afe_Get_Reg(AFE_CONN2);
3207 mAudioRegCache.REG_AFE_CONN3 = Afe_Get_Reg(AFE_CONN3);
3208 mAudioRegCache.REG_AFE_CONN4 = Afe_Get_Reg(AFE_CONN4);
3209 mAudioRegCache.REG_AFE_I2S_CON1 = Afe_Get_Reg(AFE_I2S_CON1);
3210 mAudioRegCache.REG_AFE_I2S_CON2 = Afe_Get_Reg(AFE_I2S_CON2);
3211 mAudioRegCache.REG_AFE_MRGIF_CON = Afe_Get_Reg(AFE_MRGIF_CON);
3212 mAudioRegCache.REG_AFE_DL1_BASE = Afe_Get_Reg(AFE_DL1_BASE);
3213 mAudioRegCache.REG_AFE_DL1_CUR = Afe_Get_Reg(AFE_DL1_CUR);
3214 mAudioRegCache.REG_AFE_DL1_END = Afe_Get_Reg(AFE_DL1_END);
3215 mAudioRegCache.REG_AFE_DL1_D2_BASE = Afe_Get_Reg(AFE_DL1_D2_BASE);
3216 mAudioRegCache.REG_AFE_DL1_D2_CUR = Afe_Get_Reg(AFE_DL1_D2_CUR);
3217 mAudioRegCache.REG_AFE_DL1_D2_END = Afe_Get_Reg(AFE_DL1_D2_END);
3218 mAudioRegCache.REG_AFE_VUL_D2_BASE = Afe_Get_Reg(AFE_VUL_D2_BASE);
3219 mAudioRegCache.REG_AFE_VUL_D2_END = Afe_Get_Reg(AFE_VUL_D2_END);
3220 mAudioRegCache.REG_AFE_VUL_D2_CUR = Afe_Get_Reg(AFE_VUL_D2_CUR);
3221 mAudioRegCache.REG_AFE_I2S_CON3 = Afe_Get_Reg(AFE_I2S_CON3);
3222 mAudioRegCache.REG_AFE_DL2_BASE = Afe_Get_Reg(AFE_DL2_BASE);
3223 mAudioRegCache.REG_AFE_DL2_CUR = Afe_Get_Reg(AFE_DL2_CUR);
3224 mAudioRegCache.REG_AFE_DL2_END = Afe_Get_Reg(AFE_DL2_END);
3225 mAudioRegCache.REG_AFE_CONN5 = Afe_Get_Reg(AFE_CONN5);
3226 mAudioRegCache.REG_AFE_CONN_24BIT = Afe_Get_Reg(AFE_CONN_24BIT);
3227 mAudioRegCache.REG_AFE_AWB_BASE = Afe_Get_Reg(AFE_AWB_BASE);
3228 mAudioRegCache.REG_AFE_AWB_END = Afe_Get_Reg(AFE_AWB_END);
3229 mAudioRegCache.REG_AFE_AWB_CUR = Afe_Get_Reg(AFE_AWB_CUR);
3230 mAudioRegCache.REG_AFE_VUL_BASE = Afe_Get_Reg(AFE_VUL_BASE);
3231 mAudioRegCache.REG_AFE_VUL_END = Afe_Get_Reg(AFE_VUL_END);
3232 mAudioRegCache.REG_AFE_VUL_CUR = Afe_Get_Reg(AFE_VUL_CUR);
3233 mAudioRegCache.REG_AFE_DAI_BASE = Afe_Get_Reg(AFE_DAI_BASE);
3234 mAudioRegCache.REG_AFE_DAI_END = Afe_Get_Reg(AFE_DAI_END);
3235 mAudioRegCache.REG_AFE_DAI_CUR = Afe_Get_Reg(AFE_DAI_CUR);
3236 mAudioRegCache.REG_AFE_CONN6 = Afe_Get_Reg(AFE_CONN6);
3237
3238 mAudioRegCache.REG_AFE_MEMIF_MSB = Afe_Get_Reg(AFE_MEMIF_MSB);
3239
3240 mAudioRegCache.REG_AFE_ADDA_DL_SRC2_CON0 = Afe_Get_Reg(AFE_ADDA_DL_SRC2_CON0);
3241 mAudioRegCache.REG_AFE_ADDA_DL_SRC2_CON1 = Afe_Get_Reg(AFE_ADDA_DL_SRC2_CON1);
3242 mAudioRegCache.REG_AFE_ADDA_UL_SRC_CON0 = Afe_Get_Reg(AFE_ADDA_UL_SRC_CON0);
3243 mAudioRegCache.REG_AFE_ADDA_UL_SRC_CON1 = Afe_Get_Reg(AFE_ADDA_UL_SRC_CON1);
3244 mAudioRegCache.REG_AFE_ADDA_TOP_CON0 = Afe_Get_Reg(AFE_ADDA_TOP_CON0);
3245 mAudioRegCache.REG_AFE_ADDA_UL_DL_CON0 = Afe_Get_Reg(AFE_ADDA_UL_DL_CON0);
3246
3247 mAudioRegCache.REG_AFE_ADDA_NEWIF_CFG0 = Afe_Get_Reg(AFE_ADDA_NEWIF_CFG0);
3248 mAudioRegCache.REG_AFE_ADDA_NEWIF_CFG1 = Afe_Get_Reg(AFE_ADDA_NEWIF_CFG1);
3249
3250 mAudioRegCache.REG_AFE_SIDETONE_CON0 = Afe_Get_Reg(AFE_SIDETONE_CON0);
3251 mAudioRegCache.REG_AFE_SIDETONE_COEFF = Afe_Get_Reg(AFE_SIDETONE_COEFF);
3252 mAudioRegCache.REG_AFE_SIDETONE_CON1 = Afe_Get_Reg(AFE_SIDETONE_CON1);
3253 mAudioRegCache.REG_AFE_SIDETONE_GAIN = Afe_Get_Reg(AFE_SIDETONE_GAIN);
3254 mAudioRegCache.REG_AFE_SGEN_CON0 = Afe_Get_Reg(AFE_SGEN_CON0);
3255 mAudioRegCache.REG_AFE_TOP_CON0 = Afe_Get_Reg(AFE_TOP_CON0);
3256 mAudioRegCache.REG_AFE_ADDA_PREDIS_CON0 = Afe_Get_Reg(AFE_ADDA_PREDIS_CON0);
3257 mAudioRegCache.REG_AFE_ADDA_PREDIS_CON1 = Afe_Get_Reg(AFE_ADDA_PREDIS_CON1);
3258
3259 mAudioRegCache.REG_AFE_MOD_DAI_BASE = Afe_Get_Reg(AFE_MOD_DAI_BASE);
3260 mAudioRegCache.REG_AFE_MOD_DAI_END = Afe_Get_Reg(AFE_MOD_DAI_END);
3261 mAudioRegCache.REG_AFE_MOD_DAI_CUR = Afe_Get_Reg(AFE_MOD_DAI_CUR);
3262 mAudioRegCache.REG_AFE_IRQ_MCU_CON = Afe_Get_Reg(AFE_IRQ_MCU_CON);
3263 mAudioRegCache.REG_AFE_IRQ_MCU_CNT1 = Afe_Get_Reg(AFE_IRQ_MCU_CNT1);
3264 mAudioRegCache.REG_AFE_IRQ_MCU_CNT2 = Afe_Get_Reg(AFE_IRQ_MCU_CNT2);
3265 mAudioRegCache.REG_AFE_IRQ_MCU_EN = Afe_Get_Reg(AFE_IRQ_MCU_EN);
3266 mAudioRegCache.REG_AFE_MEMIF_MAXLEN = Afe_Get_Reg(AFE_MEMIF_MAXLEN);
3267 mAudioRegCache.REG_AFE_MEMIF_PBUF_SIZE = Afe_Get_Reg(AFE_MEMIF_PBUF_SIZE);
3268 mAudioRegCache.REG_AFE_IRQ_MCU_CNT7 = Afe_Get_Reg(AFE_IRQ_MCU_CNT7); // K2 add
3269
3270 mAudioRegCache.REG_AFE_APLL1_TUNER_CFG = Afe_Get_Reg(AFE_APLL1_TUNER_CFG);
3271 mAudioRegCache.REG_AFE_APLL2_TUNER_CFG = Afe_Get_Reg(AFE_APLL2_TUNER_CFG);
3272 mAudioRegCache.REG_AFE_GAIN1_CON0 = Afe_Get_Reg(AFE_GAIN1_CON0);
3273 mAudioRegCache.REG_AFE_GAIN1_CON1 = Afe_Get_Reg(AFE_GAIN1_CON1);
3274 mAudioRegCache.REG_AFE_GAIN1_CON2 = Afe_Get_Reg(AFE_GAIN1_CON2);
3275 mAudioRegCache.REG_AFE_GAIN1_CON3 = Afe_Get_Reg(AFE_GAIN1_CON3);
3276 mAudioRegCache.REG_AFE_GAIN1_CONN = Afe_Get_Reg(AFE_GAIN1_CONN);
3277 mAudioRegCache.REG_AFE_GAIN1_CUR = Afe_Get_Reg(AFE_GAIN1_CUR);
3278 mAudioRegCache.REG_AFE_GAIN2_CON0 = Afe_Get_Reg(AFE_GAIN1_CON0);
3279 mAudioRegCache.REG_AFE_GAIN2_CON1 = Afe_Get_Reg(AFE_GAIN1_CON1);
3280 mAudioRegCache.REG_AFE_GAIN2_CON2 = Afe_Get_Reg(AFE_GAIN1_CON2);
3281 mAudioRegCache.REG_AFE_GAIN2_CON3 = Afe_Get_Reg(AFE_GAIN1_CON3);
3282 mAudioRegCache.REG_AFE_GAIN2_CONN = Afe_Get_Reg(AFE_GAIN1_CONN);
3283 mAudioRegCache.REG_AFE_GAIN2_CUR = Afe_Get_Reg(AFE_GAIN2_CUR);
3284 mAudioRegCache.REG_AFE_GAIN2_CONN2 = Afe_Get_Reg(AFE_GAIN2_CONN2);
3285 mAudioRegCache.REG_AFE_GAIN2_CONN3 = Afe_Get_Reg(AFE_GAIN2_CONN3);
3286 mAudioRegCache.REG_AFE_GAIN1_CONN2 = Afe_Get_Reg(AFE_GAIN1_CONN2);
3287 mAudioRegCache.REG_AFE_GAIN1_CONN3 = Afe_Get_Reg(AFE_GAIN1_CONN3);
3288 mAudioRegCache.REG_AFE_CONN7 = Afe_Get_Reg(AFE_CONN7);
3289 mAudioRegCache.REG_AFE_CONN8 = Afe_Get_Reg(AFE_CONN8);
3290 mAudioRegCache.REG_AFE_CONN9 = Afe_Get_Reg(AFE_CONN9);
3291 mAudioRegCache.REG_AFE_CONN10 = Afe_Get_Reg(AFE_CONN10); // K2 add
3292
3293 mAudioRegCache.REG_FPGA_CFG2 = Afe_Get_Reg(FPGA_CFG2);
3294 mAudioRegCache.REG_FPGA_CFG3 = Afe_Get_Reg(FPGA_CFG3);
3295 mAudioRegCache.REG_FPGA_CFG0 = Afe_Get_Reg(FPGA_CFG0);
3296 mAudioRegCache.REG_FPGA_CFG1 = Afe_Get_Reg(FPGA_CFG1);
3297
3298 mAudioRegCache.REG_AFE_ASRC_CON0 = Afe_Get_Reg(AFE_ASRC_CON0);
3299 mAudioRegCache.REG_AFE_ASRC_CON1 = Afe_Get_Reg(AFE_ASRC_CON1);
3300 mAudioRegCache.REG_AFE_ASRC_CON2 = Afe_Get_Reg(AFE_ASRC_CON2);
3301 mAudioRegCache.REG_AFE_ASRC_CON3 = Afe_Get_Reg(AFE_ASRC_CON3);
3302 mAudioRegCache.REG_AFE_ASRC_CON4 = Afe_Get_Reg(AFE_ASRC_CON4);
3303 mAudioRegCache.REG_AFE_ASRC_CON5 = Afe_Get_Reg(AFE_ASRC_CON5);
3304 mAudioRegCache.REG_AFE_ASRC_CON6 = Afe_Get_Reg(AFE_ASRC_CON6);
3305 mAudioRegCache.REG_AFE_ASRC_CON7 = Afe_Get_Reg(AFE_ASRC_CON7);
3306 mAudioRegCache.REG_AFE_ASRC_CON8 = Afe_Get_Reg(AFE_ASRC_CON8);
3307 mAudioRegCache.REG_AFE_ASRC_CON9 = Afe_Get_Reg(AFE_ASRC_CON9);
3308 mAudioRegCache.REG_AFE_ASRC_CON10 = Afe_Get_Reg(AFE_ASRC_CON10);
3309 mAudioRegCache.REG_AFE_ASRC_CON11 = Afe_Get_Reg(AFE_ASRC_CON11);
3310 mAudioRegCache.REG_PCM_INTF_CON = Afe_Get_Reg(PCM_INTF_CON);
3311 mAudioRegCache.REG_PCM_INTF_CON2 = Afe_Get_Reg(PCM_INTF_CON2);
3312 mAudioRegCache.REG_PCM2_INTF_CON = Afe_Get_Reg(PCM2_INTF_CON);
3313 //K2 add
3314 mAudioRegCache.REG_AUDIO_CLK_AUDDIV_0 = Afe_Get_Reg(AUDIO_CLK_AUDDIV_0);
3315 mAudioRegCache.REG_AUDIO_CLK_AUDDIV_1 = Afe_Get_Reg(AUDIO_CLK_AUDDIV_1);
3316 mAudioRegCache.REG_AUDIO_CLK_AUDDIV_2 = Afe_Get_Reg(AUDIO_CLK_AUDDIV_2);
3317 mAudioRegCache.REG_AUDIO_CLK_AUDDIV_3 = Afe_Get_Reg(AUDIO_CLK_AUDDIV_3);
3318 mAudioRegCache.REG_AFE_ASRC4_CON0 = Afe_Get_Reg(AFE_ASRC4_CON0);
3319 mAudioRegCache.REG_AFE_ASRC4_CON1 = Afe_Get_Reg(AFE_ASRC4_CON1);
3320 mAudioRegCache.REG_AFE_ASRC4_CON2 = Afe_Get_Reg(AFE_ASRC4_CON2);
3321 mAudioRegCache.REG_AFE_ASRC4_CON3 = Afe_Get_Reg(AFE_ASRC4_CON3);
3322 mAudioRegCache.REG_AFE_ASRC4_CON4 = Afe_Get_Reg(AFE_ASRC4_CON4);
3323 mAudioRegCache.REG_AFE_ASRC4_CON5 = Afe_Get_Reg(AFE_ASRC4_CON5);
3324 mAudioRegCache.REG_AFE_ASRC4_CON6 = Afe_Get_Reg(AFE_ASRC4_CON6);
3325 mAudioRegCache.REG_AFE_ASRC4_CON7 = Afe_Get_Reg(AFE_ASRC4_CON7);
3326 mAudioRegCache.REG_AFE_ASRC4_CON8 = Afe_Get_Reg(AFE_ASRC4_CON8);
3327 mAudioRegCache.REG_AFE_ASRC4_CON9 = Afe_Get_Reg(AFE_ASRC4_CON9);
3328 mAudioRegCache.REG_AFE_ASRC4_CON10 = Afe_Get_Reg(AFE_ASRC4_CON10);
3329 mAudioRegCache.REG_AFE_ASRC4_CON11 = Afe_Get_Reg(AFE_ASRC4_CON11);
3330 mAudioRegCache.REG_AFE_ASRC4_CON12 = Afe_Get_Reg(AFE_ASRC4_CON12);
3331 mAudioRegCache.REG_AFE_ASRC4_CON13 = Afe_Get_Reg(AFE_ASRC4_CON13);
3332 mAudioRegCache.REG_AFE_ASRC4_CON14 = Afe_Get_Reg(AFE_ASRC4_CON14);
3333
3334 mAudioRegCache.REG_AFE_ASRC_CON13 = Afe_Get_Reg(AFE_ASRC_CON13);
3335 mAudioRegCache.REG_AFE_ASRC_CON14 = Afe_Get_Reg(AFE_ASRC_CON14);
3336 mAudioRegCache.REG_AFE_ASRC_CON15 = Afe_Get_Reg(AFE_ASRC_CON15);
3337 mAudioRegCache.REG_AFE_ASRC_CON16 = Afe_Get_Reg(AFE_ASRC_CON16);
3338 mAudioRegCache.REG_AFE_ASRC_CON17 = Afe_Get_Reg(AFE_ASRC_CON17);
3339 mAudioRegCache.REG_AFE_ASRC_CON18 = Afe_Get_Reg(AFE_ASRC_CON18);
3340 mAudioRegCache.REG_AFE_ASRC_CON19 = Afe_Get_Reg(AFE_ASRC_CON19);
3341 mAudioRegCache.REG_AFE_ASRC_CON20 = Afe_Get_Reg(AFE_ASRC_CON20);
3342 mAudioRegCache.REG_AFE_ASRC_CON21 = Afe_Get_Reg(AFE_ASRC_CON21);
3343 mAudioRegCache.REG_AFE_ASRC2_CON0 = Afe_Get_Reg(AFE_ASRC2_CON0);
3344 mAudioRegCache.REG_AFE_ASRC2_CON1 = Afe_Get_Reg(AFE_ASRC2_CON1);
3345 mAudioRegCache.REG_AFE_ASRC2_CON2 = Afe_Get_Reg(AFE_ASRC2_CON2);
3346 mAudioRegCache.REG_AFE_ASRC2_CON3 = Afe_Get_Reg(AFE_ASRC2_CON3);
3347 mAudioRegCache.REG_AFE_ASRC2_CON4 = Afe_Get_Reg(AFE_ASRC2_CON4);
3348 mAudioRegCache.REG_AFE_ASRC2_CON5 = Afe_Get_Reg(AFE_ASRC2_CON5);
3349 mAudioRegCache.REG_AFE_ASRC2_CON6 = Afe_Get_Reg(AFE_ASRC2_CON6);
3350 mAudioRegCache.REG_AFE_ASRC2_CON7 = Afe_Get_Reg(AFE_ASRC2_CON7);
3351 mAudioRegCache.REG_AFE_ASRC2_CON8 = Afe_Get_Reg(AFE_ASRC2_CON8);
3352 mAudioRegCache.REG_AFE_ASRC2_CON9 = Afe_Get_Reg(AFE_ASRC2_CON9);
3353 mAudioRegCache.REG_AFE_ASRC2_CON10 = Afe_Get_Reg(AFE_ASRC2_CON10);
3354 mAudioRegCache.REG_AFE_ASRC2_CON11 = Afe_Get_Reg(AFE_ASRC2_CON11);
3355 mAudioRegCache.REG_AFE_ASRC2_CON12 = Afe_Get_Reg(AFE_ASRC2_CON12);
3356 mAudioRegCache.REG_AFE_ASRC2_CON13 = Afe_Get_Reg(AFE_ASRC2_CON13);
3357 mAudioRegCache.REG_AFE_ASRC2_CON14 = Afe_Get_Reg(AFE_ASRC2_CON14);
3358 mAudioRegCache.REG_AFE_ASRC3_CON0 = Afe_Get_Reg(AFE_ASRC3_CON0);
3359 mAudioRegCache.REG_AFE_ASRC3_CON1 = Afe_Get_Reg(AFE_ASRC3_CON1);
3360 mAudioRegCache.REG_AFE_ASRC3_CON2 = Afe_Get_Reg(AFE_ASRC3_CON2);
3361 mAudioRegCache.REG_AFE_ASRC3_CON3 = Afe_Get_Reg(AFE_ASRC3_CON3);
3362 mAudioRegCache.REG_AFE_ASRC3_CON4 = Afe_Get_Reg(AFE_ASRC3_CON4);
3363 mAudioRegCache.REG_AFE_ASRC3_CON5 = Afe_Get_Reg(AFE_ASRC3_CON5);
3364 mAudioRegCache.REG_AFE_ASRC3_CON6 = Afe_Get_Reg(AFE_ASRC3_CON6);
3365 mAudioRegCache.REG_AFE_ASRC3_CON7 = Afe_Get_Reg(AFE_ASRC3_CON7);
3366 mAudioRegCache.REG_AFE_ASRC3_CON8 = Afe_Get_Reg(AFE_ASRC3_CON8);
3367 mAudioRegCache.REG_AFE_ASRC3_CON9 = Afe_Get_Reg(AFE_ASRC3_CON9);
3368 mAudioRegCache.REG_AFE_ASRC3_CON10 = Afe_Get_Reg(AFE_ASRC3_CON10);
3369 mAudioRegCache.REG_AFE_ASRC3_CON11 = Afe_Get_Reg(AFE_ASRC3_CON11);
3370 mAudioRegCache.REG_AFE_ASRC3_CON12 = Afe_Get_Reg(AFE_ASRC3_CON12);
3371 mAudioRegCache.REG_AFE_ASRC3_CON13 = Afe_Get_Reg(AFE_ASRC3_CON13);
3372 mAudioRegCache.REG_AFE_ASRC3_CON14 = Afe_Get_Reg(AFE_ASRC3_CON14);
3373 //K2 add
3374 mAudioRegCache.REG_AFE_ADDA4_TOP_CON0 = Afe_Get_Reg(AFE_ADDA4_TOP_CON0);
3375 mAudioRegCache.REG_AFE_ADDA4_UL_SRC_CON0 = Afe_Get_Reg(AFE_ADDA4_UL_SRC_CON0);
3376 mAudioRegCache.REG_AFE_ADDA4_UL_SRC_CON1 = Afe_Get_Reg(AFE_ADDA4_UL_SRC_CON1);
3377 mAudioRegCache.REG_AFE_ADDA4_NEWIF_CFG0 = Afe_Get_Reg(AFE_ADDA4_NEWIF_CFG0);
3378 mAudioRegCache.REG_AFE_ADDA4_NEWIF_CFG1 = Afe_Get_Reg(AFE_ADDA4_NEWIF_CFG1);
3379 mAudioRegCache.REG_AFE_ADDA4_ULCF_CFG_02_01 = Afe_Get_Reg(AFE_ADDA4_ULCF_CFG_02_01);
3380 mAudioRegCache.REG_AFE_ADDA4_ULCF_CFG_04_03 = Afe_Get_Reg(AFE_ADDA4_ULCF_CFG_04_03);
3381 mAudioRegCache.REG_AFE_ADDA4_ULCF_CFG_06_05 = Afe_Get_Reg(AFE_ADDA4_ULCF_CFG_06_05);
3382 mAudioRegCache.REG_AFE_ADDA4_ULCF_CFG_08_07 = Afe_Get_Reg(AFE_ADDA4_ULCF_CFG_08_07);
3383 mAudioRegCache.REG_AFE_ADDA4_ULCF_CFG_10_09 = Afe_Get_Reg(AFE_ADDA4_ULCF_CFG_10_09);
3384 mAudioRegCache.REG_AFE_ADDA4_ULCF_CFG_12_11 = Afe_Get_Reg(AFE_ADDA4_ULCF_CFG_12_11);
3385 mAudioRegCache.REG_AFE_ADDA4_ULCF_CFG_14_13 = Afe_Get_Reg(AFE_ADDA4_ULCF_CFG_14_13);
3386 mAudioRegCache.REG_AFE_ADDA4_ULCF_CFG_16_15 = Afe_Get_Reg(AFE_ADDA4_ULCF_CFG_16_15);
3387 mAudioRegCache.REG_AFE_ADDA4_ULCF_CFG_18_17 = Afe_Get_Reg(AFE_ADDA4_ULCF_CFG_18_17);
3388 mAudioRegCache.REG_AFE_ADDA4_ULCF_CFG_20_19 = Afe_Get_Reg(AFE_ADDA4_ULCF_CFG_20_19);
3389 mAudioRegCache.REG_AFE_ADDA4_ULCF_CFG_22_21 = Afe_Get_Reg(AFE_ADDA4_ULCF_CFG_22_21);
3390 mAudioRegCache.REG_AFE_ADDA4_ULCF_CFG_24_23 = Afe_Get_Reg(AFE_ADDA4_ULCF_CFG_24_23);
3391 mAudioRegCache.REG_AFE_ADDA4_ULCF_CFG_26_25 = Afe_Get_Reg(AFE_ADDA4_ULCF_CFG_26_25);
3392 mAudioRegCache.REG_AFE_ADDA4_ULCF_CFG_28_27 = Afe_Get_Reg(AFE_ADDA4_ULCF_CFG_28_27);
3393 mAudioRegCache.REG_AFE_ADDA4_ULCF_CFG_30_29 = Afe_Get_Reg(AFE_ADDA4_ULCF_CFG_30_29);
3394
3395 AudDrv_Clk_Off();
3396 return true;
3397 }
3398
3399 bool Restore_Audio_Register(void)
3400 {
3401 // K2 TODO?
3402 return true;
3403 }
3404
3405 unsigned int Align64ByteSize(unsigned int insize)
3406 {
3407 #define MAGIC_NUMBER 0xFFFFFFC0
3408
3409 unsigned int align_size;
3410 align_size = insize & MAGIC_NUMBER;
3411 return align_size;
3412 }
3413
3414
kernel source for telekom puls (alcatel/mediatek)