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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / mediatek / mt_soc_audio_v1 / mt_soc_codec_63xx.c
1 /*
2 * Copyright (C) 2007 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16 /*******************************************************************************
17 *
18 * Filename:
19 * ---------
20 * mtk_soc_codec_63xx
21 *
22 * Project:
23 * --------
24 *
25 *
26 * Description:
27 * ------------
28 * Audio codec stub file
29 *
30 * Author:
31 * -------
32 * Chipeng Chang
33 *
34 *------------------------------------------------------------------------------
35 * $Revision: #1 $
36 * $Modtime:$
37 * $Log:$
38 *
39 *
40 *******************************************************************************/
41
42
43 /*****************************************************************************
44 * C O M P I L E R F L A G S
45 *****************************************************************************/
46
47
48 /*****************************************************************************
49 * E X T E R N A L R E F E R E N C E S
50 *****************************************************************************/
51
52 #include <linux/dma-mapping.h>
53 #include <linux/platform_device.h>
54 #include <linux/slab.h>
55 #include <linux/module.h>
56 #include <linux/of_device.h>
57 #include <sound/core.h>
58 #include <sound/pcm.h>
59 #include <sound/soc.h>
60
61 #include "AudDrv_Common.h"
62 #include "AudDrv_Def.h"
63 #include "AudDrv_Afe.h"
64 #include "AudDrv_Ana.h"
65 #include "AudDrv_Clk.h"
66 #include "mt_soc_analog_type.h"
67 #include <mach/mt_clkbuf_ctl.h>
68 #include <sound/mt_soc_audio.h>
69 #include <mach/vow_api.h>
70 #ifdef CONFIG_MTK_SPEAKER
71 #include "mt_soc_codec_speaker_63xx.h"
72 #endif
73
74 #include "mt_soc_pcm_common.h"
75
76 //#define VOW_TONE_TEST
77
78 #ifndef CONFIG_MTK_FPGA
79 extern void mt6331_upmu_set_rg_audmicbias1lowpen(kal_uint32 val);
80 extern void mt6331_upmu_set_rg_audmicbias1dcswnen(kal_uint32 val);
81 extern void mt6331_upmu_set_rg_audmicbias1dcswpen(kal_uint32 val);
82 extern void mt6331_upmu_set_rg_audpwdbmicbias1(kal_uint32 val);
83
84 extern void mt6331_upmu_set_rg_audmicbias0lowpen(kal_uint32 val);
85 extern void mt6331_upmu_set_rg_audmicbias0dcswnen(kal_uint32 val);
86 extern void mt6331_upmu_set_rg_audmicbias0dcswpen(kal_uint32 val);
87 extern void mt6331_upmu_set_rg_audpwdbmicbias0(kal_uint32 val);
88 #endif
89
90 // static function declaration
91 static void HeadsetRVolumeSet(void);
92 static void HeadsetLVolumeSet(void);
93 static bool AudioPreAmp1_Sel(int Mul_Sel);
94 static bool GetAdcStatus(void);
95 static void Apply_Speaker_Gain(void);
96 static bool TurnOnVOWDigitalHW(bool enable);
97 static void TurnOffDacPower(void);
98 static void TurnOnDacPower(void);
99 static void OpenClassH(void);
100 static void OpenClassAB(void);
101 static void SetDcCompenSation(void);
102 static bool GetDLStatus(void);
103 static void EnableMicBias(uint32_t Mic, bool bEnable);
104 static void OpenMicbias0(bool bEanble);
105 static void OpenMicbias1(bool bEanble);
106 static void OpenMicbias2(bool bEanble);
107 static void OpenMicbias3(bool bEanble);
108 static void Audio_ADC1_Set_Input(int Input);
109 static void Audio_ADC2_Set_Input(int Input);
110 static void Audio_ADC3_Set_Input(int Input);
111 static void Audio_ADC4_Set_Input(int Input);
112 static void Voice_Amp_Change(bool enable);
113 static void Speaker_Amp_Change(bool enable);
114 static bool TurnOnVOWADcPowerACC(int ADCType, bool enable);
115 static void Audio_Amp_Change(int channels , bool enable);
116 void OpenAnalogHeadphone(bool bEnable);
117
118
119 #ifndef CONFIG_MTK_FPGA
120 extern int PMIC_IMM_GetOneChannelValue(int dwChannel, int deCount, int trimd);
121 #endif
122
123 static mt6331_Codec_Data_Priv *mCodec_data = NULL;
124 static uint32 mBlockSampleRate[AUDIO_ANALOG_DEVICE_INOUT_MAX] = {48000, 48000, 48000};
125 static DEFINE_MUTEX(Ana_Ctrl_Mutex);
126 static DEFINE_MUTEX(Ana_buf_Ctrl_Mutex);
127 static DEFINE_MUTEX(Ana_Clk_Mutex);
128 static DEFINE_MUTEX(Ana_Power_Mutex);
129 static DEFINE_MUTEX(AudAna_lock);
130
131 static int mAudio_Analog_Mic1_mode = AUDIO_ANALOGUL_MODE_ACC;
132 static int mAudio_Analog_Mic2_mode = AUDIO_ANALOGUL_MODE_ACC;
133 static int mAudio_Analog_Mic3_mode = AUDIO_ANALOGUL_MODE_ACC;
134 static int mAudio_Analog_Mic4_mode = AUDIO_ANALOGUL_MODE_ACC;
135
136 static int mAudio_Vow_Analog_Func_Enable = false;
137 static int mAudio_Vow_Digital_Func_Enable = false;
138 static int TrimOffset = 2048;
139 //static const int DC1unit_in_uv = 21576*2; // in uv
140 static const int DC1unit_in_uv = 19184; // in uv with 0DB
141 static const int DC1devider = 8; // in uv
142
143 #ifdef CONFIG_MTK_SPEAKER
144 static int Speaker_mode = AUDIO_SPEAKER_MODE_AB;
145 static unsigned int Speaker_pga_gain = 1 ; // default 0Db.
146 static bool mSpeaker_Ocflag = false;
147 static int mEnableAuxAdc = 0;
148 #endif
149 static int mAdc_Power_Mode = 0;
150 static unsigned int dAuxAdcChannel = 16;
151 static const int mDcOffsetTrimChannel = 9;
152 static bool mInitCodec = false;
153
154 static int reg_AFE_VOW_CFG0 = 0xffff; //bias removing reference amp
155 static int reg_AFE_VOW_CFG1 = 0x0200; //watch dog timer initial value
156 static int reg_AFE_VOW_CFG2 = 0x2424; //VOW A/B value
157 static int reg_AFE_VOW_CFG3 = 0x8767; //VOW alpha/beta value
158 static int reg_AFE_VOW_CFG4 = 0x000c; //VOW ADC test config
159 static int reg_AFE_VOW_CFG5 = 0x0000; //N min value
160
161 static void SavePowerState(void)
162 {
163 int i = 0;
164 for (i = 0; i < AUDIO_ANALOG_VOLUME_TYPE_MAX ; i++)
165 {
166 mCodec_data->mAudio_BackUpAna_DevicePower[i] = mCodec_data->mAudio_Ana_DevicePower[i];
167 }
168 }
169
170 static void RestorePowerState(void)
171 {
172 int i = 0;
173 for (i = 0; i < AUDIO_ANALOG_VOLUME_TYPE_MAX ; i++)
174 {
175 mCodec_data->mAudio_Ana_DevicePower[i] = mCodec_data->mAudio_BackUpAna_DevicePower[i];
176 }
177 }
178
179
180 static bool mAnaSuspend = false;
181 void SetAnalogSuspend(bool bEnable)
182 {
183 printk("%s bEnable ==%d mAnaSuspend = %d \n", __func__, bEnable, mAnaSuspend);
184 if ((bEnable == true) && (mAnaSuspend == false))
185 {
186 Ana_Log_Print();
187 SavePowerState();
188 if (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTL] == true)
189 {
190 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTL] = false;
191 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_LEFT1 , false);
192 }
193 if (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTR] == true)
194 {
195 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTR] = false;
196 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_RIGHT1 , false);
197 }
198 if (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HSOUTL] == true)
199 {
200 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HSOUTL] = false;
201 Voice_Amp_Change(false);
202 }
203 if (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_SPKL] == true)
204 {
205 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_SPKL] = false;
206 Speaker_Amp_Change(false);
207 }
208 Ana_Log_Print();
209 mAnaSuspend = true;
210 }
211 else if ((bEnable == false) && (mAnaSuspend == true))
212 {
213 Ana_Log_Print();
214 if (mCodec_data->mAudio_BackUpAna_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTL] == true)
215 {
216 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_LEFT1 , true);
217 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTL] = true;
218 }
219 if (mCodec_data->mAudio_BackUpAna_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTR] == true)
220 {
221 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_RIGHT1 , true);
222 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTR] = false;
223 }
224 if (mCodec_data->mAudio_BackUpAna_DevicePower[AUDIO_ANALOG_VOLUME_HSOUTL] == true)
225 {
226 Voice_Amp_Change(true);
227 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HSOUTL] = false;
228 }
229 if (mCodec_data->mAudio_BackUpAna_DevicePower[AUDIO_ANALOG_VOLUME_SPKL] == true)
230 {
231 Speaker_Amp_Change(true);
232 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_SPKL] = false;
233 }
234 RestorePowerState();
235 Ana_Log_Print();
236 mAnaSuspend = false;
237 }
238 }
239
240
241 static int audck_buf_Count = 0;
242 void audckbufEnable(bool enable)
243 {
244 printk("audckbufEnable audck_buf_Count = %d enable = %d \n", audck_buf_Count, enable);
245 mutex_lock(&Ana_buf_Ctrl_Mutex);
246 if (enable)
247 {
248 if (audck_buf_Count == 0)
249 {
250 printk("+clk_buf_ctrl(CLK_BUF_AUDIO,true)\n");
251 clk_buf_ctrl(CLK_BUF_AUDIO, true);
252 printk("-clk_buf_ctrl(CLK_BUF_AUDIO,true)\n");
253 }
254 audck_buf_Count++;
255 }
256 else
257 {
258 audck_buf_Count--;
259 if (audck_buf_Count == 0)
260 {
261 printk("+clk_buf_ctrl(CLK_BUF_AUDIO,false)\n");
262 clk_buf_ctrl(CLK_BUF_AUDIO, false);
263 printk("-clk_buf_ctrl(CLK_BUF_AUDIO,false)\n");
264 }
265 if (audck_buf_Count < 0)
266 {
267 printk("audck_buf_Count count <0 \n");
268 audck_buf_Count = 0;
269 }
270 }
271 mutex_unlock(&Ana_buf_Ctrl_Mutex);
272 }
273
274 static int ClsqAuxCount = 0;
275 static void ClsqAuxEnable(bool enable)
276 {
277 printk("ClsqAuxEnable ClsqAuxCount = %d enable = %d \n", ClsqAuxCount, enable);
278 mutex_lock(& AudAna_lock);
279 if (enable)
280 {
281 if (ClsqAuxCount == 0)
282 {
283 Ana_Set_Reg(TOP_CLKSQ, 0x0002, 0x0002); //CKSQ Enable
284 }
285 ClsqAuxCount++;
286 }
287 else
288 {
289 ClsqAuxCount--;
290 if (ClsqAuxCount < 0)
291 {
292 printk("ClsqAuxEnable count <0 \n");
293 ClsqAuxCount = 0;
294 }
295 if (ClsqAuxCount == 0)
296 {
297 Ana_Set_Reg(TOP_CLKSQ, 0x0000, 0x0002);
298 }
299 }
300 mutex_unlock(& AudAna_lock);
301 }
302
303 static int ClsqCount = 0;
304 static void ClsqEnable(bool enable)
305 {
306 printk("ClsqEnable ClsqAuxCount = %d enable = %d \n", ClsqCount, enable);
307 mutex_lock(& AudAna_lock);
308 if (enable)
309 {
310 if (ClsqCount == 0)
311 {
312 Ana_Set_Reg(TOP_CLKSQ, 0x0001, 0x0001); //CKSQ Enable
313 }
314 ClsqCount++;
315 }
316 else
317 {
318 ClsqCount--;
319 if (ClsqCount < 0)
320 {
321 printk("ClsqEnable count <0 \n");
322 ClsqCount = 0;
323 }
324 if (ClsqCount == 0)
325 {
326 Ana_Set_Reg(TOP_CLKSQ, 0x0000, 0x0001);
327 }
328 }
329 mutex_unlock(& AudAna_lock);
330 }
331
332 static int TopCkCount = 0;
333 static void Topck_Enable(bool enable)
334 {
335 printk("Topck_Enable enable = %d TopCkCount = %d \n", enable, TopCkCount);
336 mutex_lock(&Ana_Clk_Mutex);
337 if (enable == true)
338 {
339 if (TopCkCount == 0)
340 {
341 Ana_Set_Reg(TOP_CKPDN_CON0_CLR, 0x3000, 0x3000); //AUD clock power down released
342 }
343 TopCkCount++;
344 }
345 else
346 {
347 TopCkCount--;
348 if (TopCkCount == 0)
349 {
350 Ana_Set_Reg(TOP_CKPDN_CON0_SET, 0x3000, 0x3000);
351 }
352 if (TopCkCount <= 0)
353 {
354 printk("TopCkCount <0 =%d\n ", TopCkCount);
355 TopCkCount = 0;
356 }
357 }
358 mutex_unlock(&Ana_Clk_Mutex);
359 }
360
361 static int NvRegCount = 0;
362 static void NvregEnable(bool enable)
363 {
364 printk("NvregEnable NvRegCount == %d enable = %d \n", NvRegCount, enable);
365 mutex_lock(&Ana_Clk_Mutex);
366 if (enable == true)
367 {
368 if (NvRegCount == 0)
369 {
370 Ana_Set_Reg(AUDNVREGGLB_CFG0, 0x0000, 0xffff); //AUD clock power down released
371 }
372 NvRegCount++;
373 }
374 else
375 {
376 NvRegCount--;
377 if (NvRegCount == 0)
378 {
379 Ana_Set_Reg(AUDNVREGGLB_CFG0, 0x0001, 0xffff);
380 }
381 if (NvRegCount < 0)
382 {
383 printk("NvRegCount <0 =%d\n ", NvRegCount);
384 NvRegCount = 0;
385 }
386 }
387 mutex_unlock(&Ana_Clk_Mutex);
388 }
389
390 static int AdcClockCount = 0;
391 static void AdcClockEnable(bool enable)
392 {
393 mutex_lock(&Ana_Clk_Mutex);
394 if (enable == true)
395 {
396 if (AdcClockCount == 0)
397 {
398 Ana_Set_Reg(TOP_CKPDN_CON0_CLR, 0x3000, 0xffff); //AUD clock power down released
399 }
400 AdcClockCount++;
401 }
402 else
403 {
404 AdcClockCount--;
405 if (AdcClockCount == 0)
406 {
407 Ana_Set_Reg(TOP_CKPDN_CON0_SET, 0x3000, 0xffff);
408 }
409 if (AdcClockCount <= 0)
410 {
411 printk("TopCkCount <0 =%d\n ", AdcClockCount);
412 AdcClockCount = 0;
413 }
414 }
415 mutex_unlock(&Ana_Clk_Mutex);
416 }
417
418 #if defined (MTK_VOW_SUPPORT)
419 void vow_irq_handler(void)
420 {
421 printk("audio irq event....\n");
422 //TurnOnVOWADcPowerACC(AUDIO_ANALOG_DEVICE_IN_ADC1, false);
423 TurnOnVOWDigitalHW(false);
424 #if defined(VOW_TONE_TEST)
425 EnableSideGenHw(Soc_Aud_InterConnectionOutput_O03, Soc_Aud_MemIF_Direction_DIRECTION_OUTPUT, true);
426 #endif
427 VowDrv_ChangeStatus();
428 }
429 #endif
430
431 static int LowPowerAdcClockCount = 0;
432 static void LowPowerAdcClockEnable(bool enable)
433 {
434 mutex_lock(&Ana_Clk_Mutex);
435 if (enable == true)
436 {
437 if (LowPowerAdcClockCount == 0)
438 {
439 Ana_Set_Reg(TOP_CKPDN_CON0_CLR, 0x8000, 0xffff); //Lowpower AUD clock power down released
440 }
441 LowPowerAdcClockCount++;
442 }
443 else
444 {
445 LowPowerAdcClockCount--;
446 if (LowPowerAdcClockCount == 0)
447 {
448 Ana_Set_Reg(TOP_CKPDN_CON0_SET, 0x8000, 0xffff);
449 }
450 if (LowPowerAdcClockCount < 0)
451 {
452 printk("LowPowerAdcClockCount <0 =%d\n ", LowPowerAdcClockCount);
453 LowPowerAdcClockCount = 0;
454 }
455 }
456 mutex_unlock(&Ana_Clk_Mutex);
457 }
458
459
460 #ifdef CONFIG_MTK_SPEAKER
461 static void Apply_Speaker_Gain(void)
462 {
463 Ana_Set_Reg(SPK_CON9, Speaker_pga_gain << 8, 0xf << 8);
464 }
465 #else
466 static void Apply_Speaker_Gain(void)
467 {
468
469 }
470 #endif
471
472 void setOffsetTrimMux(unsigned int Mux)
473 {
474 printk("%s Mux = %d\n", __func__, Mux);
475 Ana_Set_Reg(AUDBUF_CFG7 , Mux << 12, 0xf << 12); // buffer mux select
476 }
477
478 void setOffsetTrimBufferGain(unsigned int gain)
479 {
480 Ana_Set_Reg(AUDBUF_CFG7 , gain << 10, 0x3 << 10); // buffer mux select
481 }
482
483 static int mHplTrimOffset = 2048;
484 static int mHprTrimOffset = 2048;
485
486 void SetHplTrimOffset(int Offset)
487 {
488 printk("%s Offset = %d\n",__func__,Offset);
489 mHplTrimOffset = Offset;
490 if ((Offset > 2098) || (Offset < 1998))
491 {
492 mHplTrimOffset = 2048;
493 printk("SetHplTrimOffset offset may be invalid offset = %d\n", Offset);
494 }
495 }
496
497 void SetHprTrimOffset(int Offset)
498 {
499 printk("%s Offset = %d\n",__func__,Offset);
500 mHprTrimOffset = Offset;
501 if ((Offset > 2098) || (Offset < 1998))
502 {
503 mHplTrimOffset = 2048;
504 printk("SetHplTrimOffset offset may be invalid offset = %d\n", Offset);
505 }
506 }
507
508 void EnableTrimbuffer(bool benable)
509 {
510 if (benable == true)
511 {
512 Ana_Set_Reg(AUDBUF_CFG8 , 0x1 << 13, 0x1 << 13); // trim buffer enable
513 }
514 else
515 {
516 Ana_Set_Reg(AUDBUF_CFG8 , 0x0 << 13, 0x1 << 13); // trim buffer enable
517 }
518 }
519
520 void OpenTrimBufferHardware(bool enable)
521 {
522 if (enable)
523 {
524 TurnOnDacPower();
525 printk("%s \n", __func__);
526 Ana_Set_Reg(AUDNVREGGLB_CFG0, 0x0000, 0xffff); // Enable AUDGLB
527 OpenClassAB();
528 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0028, 0xffff); // Enable cap-less LDOs (1.6V)
529 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0068, 0xffff); // Enable NV regulator (-1.6V)
530 Ana_Set_Reg(AUDBUF_CFG5, 0x001f, 0xffff); // enable HP bias circuits
531 msleep(1);
532 Ana_Set_Reg(ZCD_CON0, 0x0000, 0xffff); // Disable AUD_ZCD_CFG0
533 Ana_Set_Reg(AUDBUF_CFG0, 0xE008, 0xffff); // Disable headphone, voice and short-ckt protection.
534 Ana_Set_Reg(IBIASDIST_CFG0, 0x0092, 0xffff); //Enable IBIST
535 Ana_Set_Reg(ZCD_CON2, 0x0489 , 0xffff); // Set HPR/HPL gain as 0dB, step by step
536 Ana_Set_Reg(ZCD_CON3, 0x001F , 0xffff); //Set voice gain as minimum (~ -40dB)
537 Ana_Set_Reg(AUDBUF_CFG1, 0x0900 , 0xffff); //De_OSC of HP and enable output STBENH
538 Ana_Set_Reg(AUDBUF_CFG2, 0x0022 , 0xffff); //De_OSC of voice, enable output STBENH
539 Ana_Set_Reg(AUDBUF_CFG0, 0xE009 , 0xffff); //Enable voice driver
540 Ana_Set_Reg(AUDBUF_CFG1, 0x0940 , 0xffff); //Enable pre-charge buffer
541 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5501 , 0xffff); //Enable AUD_CLK
542 Ana_Set_Reg(AUDDAC_CFG0, 0x000c , 0x000c); //Enable Audio DAC
543 Ana_Set_Reg(AUDDAC_CFG0, 0x0003 , 0x0003); //Enable Audio DAC
544 }
545 else
546 {
547 printk("Audio_Amp_Change off amp\n");
548 Ana_Set_Reg(AUDDAC_CFG0, 0x0000, 0xffff); // Disable Audio DAC
549 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5500, 0xffff); // Disable AUD_CLK
550 Ana_Set_Reg(IBIASDIST_CFG0, 0x0192, 0xffff); // Disable IBIST
551 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0028, 0xffff); // Disable NV regulator (-1.6V)
552 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0000, 0xffff); // Disable cap-less LDOs (1.6V)
553 Ana_Set_Reg(AUDDAC_CFG0, 0x000e, 0xffff); // enable audio bias. enable audio DAC, HP buffers
554 Ana_Set_Reg(AUDDAC_CFG0, 0x000d, 0xffff); // enable audio bias. enable audio DAC, HP buffers
555 Ana_Set_Reg(AFE_DL_SRC2_CON0_L , 0x1800 , 0xffffffff);
556 Ana_Set_Reg(AFE_UL_DL_CON0, 0x0000, 0xffff); //turn off afe
557 TurnOffDacPower();
558 }
559 }
560
561
562 void OpenAnalogTrimHardware(bool enable)
563 {
564 if (enable)
565 {
566 TurnOnDacPower();
567 printk("%s \n", __func__);
568 //Ana_Set_Reg(AUDNVREGGLB_CFG0, 0x0000, 0xffff); // Enable AUDGLB
569 OpenClassAB();
570 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0028, 0xffff); // Enable cap-less LDOs (1.6V)
571 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0068, 0xffff); // Enable NV regulator (-1.6V)
572 Ana_Set_Reg(AUDBUF_CFG5, 0x001f, 0xffff); // enable HP bias circuits
573 msleep(1);
574 Ana_Set_Reg(ZCD_CON0, 0x0000, 0xffff); // Disable AUD_ZCD_CFG0
575 Ana_Set_Reg(AUDBUF_CFG0, 0xE008, 0xffff); // Disable headphone, voice and short-ckt protection.
576 Ana_Set_Reg(IBIASDIST_CFG0, 0x0092, 0xffff); //Enable IBIST
577 Ana_Set_Reg(ZCD_CON2, 0x0489 , 0xffff); // Set HPR/HPL gain as 0dB, step by step
578 Ana_Set_Reg(ZCD_CON3, 0x001F , 0xffff); //Set voice gain as minimum (~ -40dB)
579 Ana_Set_Reg(AUDBUF_CFG1, 0x0900 , 0xffff); //De_OSC of HP and enable output STBENH
580 Ana_Set_Reg(AUDBUF_CFG2, 0x0022 , 0xffff); //De_OSC of voice, enable output STBENH
581 Ana_Set_Reg(AUDBUF_CFG0, 0xE009 , 0xffff); //Enable voice driver
582 Ana_Set_Reg(AUDBUF_CFG1, 0x0940 , 0xffff); //Enable pre-charge buffer
583 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5501 , 0xffff); //Enable AUD_CLK
584 Ana_Set_Reg(AUDDAC_CFG0, 0x000c , 0x000c); //Enable Audio DAC
585 Ana_Set_Reg(AUDDAC_CFG0, 0x0003 , 0x0003); //Enable Audio DAC
586 }
587 else
588 {
589 printk("Audio_Amp_Change off amp\n");
590 Ana_Set_Reg(AUDDAC_CFG0, 0x0000, 0xffff); // Disable Audio DAC
591 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5500, 0xffff); // Disable AUD_CLK
592 Ana_Set_Reg(IBIASDIST_CFG0, 0x0192, 0xffff); // Disable IBIST
593 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0028, 0xffff); // Disable NV regulator (-1.6V)
594 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0000, 0xffff); // Disable cap-less LDOs (1.6V)
595 Ana_Set_Reg(AUDDAC_CFG0, 0x000e, 0xffff); // enable audio bias. enable audio DAC, HP buffers
596 Ana_Set_Reg(AUDDAC_CFG0, 0x000d, 0xffff); // enable audio bias. enable audio DAC, HP buffers
597 Ana_Set_Reg(AFE_DL_SRC2_CON0_L , 0x1800 , 0xffffffff);
598 Ana_Set_Reg(AFE_UL_DL_CON0, 0x0000, 0xffff); //turn off afe
599 TurnOffDacPower();
600 }
601 }
602
603 void OpenAnalogHeadphone(bool bEnable)
604 {
605 printk("OpenAnalogHeadphone bEnable = %d", bEnable);
606 if (bEnable)
607 {
608 SetHplTrimOffset(2048);
609 SetHprTrimOffset(2048);
610 mBlockSampleRate[AUDIO_ANALOG_DEVICE_OUT_DAC] = 44100;
611 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_LEFT1 , true);
612 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTL] = true;
613 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_RIGHT1 , true);
614 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTR] = true;
615 }
616 else
617 {
618 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTL] = false;
619 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_LEFT1 , false);
620 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTR] = false;
621 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_RIGHT1 , false);
622 }
623 }
624
625 bool OpenHeadPhoneImpedanceSetting(bool bEnable)
626 {
627 printk("%s benable = %d\n", __func__, bEnable);
628 if (GetDLStatus() == true)
629 {
630 return false;
631 }
632
633 if (bEnable == true)
634 {
635 TurnOnDacPower();
636 OpenClassAB();
637 Ana_Set_Reg(AUDBUF_CFG5, 0x0003, 0x0003); // enable HP bias circuits
638 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0028, 0xffff); // Enable cap-less LDOs (1.6V)
639 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0068, 0xffff); // Enable NV regulator (-1.6V)
640 Ana_Set_Reg(ZCD_CON0, 0x0000, 0xffff);
641 Ana_Set_Reg(AUDBUF_CFG0, 0xE000, 0xffff);
642 Ana_Set_Reg(AUDBUF_CFG1, 0x0000, 0xffff);
643 Ana_Set_Reg(AUDBUF_CFG8, 0x4000, 0xffff);
644 Ana_Set_Reg(IBIASDIST_CFG0, 0x0092, 0xffff);
645 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5501, 0xffff);
646 Ana_Set_Reg(AUDDAC_CFG0, 0x0009, 0xffff);
647 Ana_Set_Reg(AUDBUF_CFG6, 0x4800, 0xffff);
648 }
649 else
650 {
651 Ana_Set_Reg(AUDDAC_CFG0, 0x0000, 0xffff); // Disable Audio DAC
652 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5500, 0xffff); // Disable AUD_CLK
653 Ana_Set_Reg(IBIASDIST_CFG0, 0x0192, 0xffff); // Disable IBIST
654 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0028, 0xffff); // Disable NV regulator (-1.6V)
655 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0000, 0xffff); // Disable cap-less LDOs (1.6V)
656 Ana_Set_Reg(AUDBUF_CFG8, 0x0000, 0xffff);
657 Ana_Set_Reg(AUDBUF_CFG5, 0x0000, 0x0003); // disable HP bias circuits
658 TurnOffDacPower();
659 Ana_Set_Reg(AUDBUF_CFG6, 0x0000, 0xffff);
660 }
661 return true;
662 }
663
664 void setHpGainZero(void)
665 {
666 Ana_Set_Reg(ZCD_CON2, 0x8 << 7, 0x0f80);
667 Ana_Set_Reg(ZCD_CON2, 0x8 , 0x001f);
668 }
669
670 void SetSdmLevel(unsigned int level)
671 {
672 Ana_Set_Reg(AFE_DL_SDM_CON1, level, 0xffffffff);
673 }
674
675
676 static void SetHprOffset(int OffsetTrimming)
677 {
678 short Dccompsentation = 0;
679 int DCoffsetValue = 0;
680 unsigned short RegValue = 0;
681 printk("%s OffsetTrimming = %d \n",__func__,OffsetTrimming);
682 DCoffsetValue = OffsetTrimming * 1000000;
683 DCoffsetValue = (DCoffsetValue / DC1devider); // in uv
684 printk("%s DCoffsetValue = %d \n",__func__,DCoffsetValue);
685 DCoffsetValue = (DCoffsetValue / DC1unit_in_uv);
686 printk("%s DCoffsetValue = %d \n",__func__,DCoffsetValue);
687 Dccompsentation = DCoffsetValue;
688 RegValue = Dccompsentation;
689 printk("%s RegValue = 0x%x\n",__func__,RegValue);
690 Ana_Set_Reg(AFE_DL_DC_COMP_CFG1, RegValue , 0xffff);
691 }
692
693 static void SetHplOffset(int OffsetTrimming)
694 {
695 short Dccompsentation = 0;
696 int DCoffsetValue = 0;
697 unsigned short RegValue = 0;
698 printk("%s OffsetTrimming = %d \n",__func__,OffsetTrimming);
699 DCoffsetValue = OffsetTrimming *1000000;
700 DCoffsetValue = (DCoffsetValue / DC1devider); // in uv
701 printk("%s DCoffsetValue = %d \n",__func__,DCoffsetValue);
702 DCoffsetValue = (DCoffsetValue / DC1unit_in_uv);
703 printk("%s DCoffsetValue = %d \n",__func__,DCoffsetValue);
704 Dccompsentation = DCoffsetValue;
705 RegValue = Dccompsentation;
706 printk("%s RegValue = 0x%x\n",__func__,RegValue);
707 Ana_Set_Reg(AFE_DL_DC_COMP_CFG0, RegValue , 0xffff);
708 }
709
710 static void EnableDcCompensation(bool bEnable)
711 {
712 if(bEnable == true)
713 {
714 Ana_Set_Reg(AFE_DL_DC_COMP_CFG2, bEnable , 0x1);
715 }
716 else
717 {
718 Ana_Set_Reg(AFE_DL_DC_COMP_CFG2, bEnable , 0x1);
719 }
720 }
721
722 static void SetHprOffsetTrim(void)
723 {
724 int OffsetTrimming = mHprTrimOffset - TrimOffset;
725 printk("%s mHprTrimOffset = %d TrimOffset = %d \n",__func__,mHprTrimOffset,TrimOffset);
726 SetHprOffset(OffsetTrimming);
727 }
728
729 static void SetHpLOffsetTrim(void)
730 {
731 int OffsetTrimming = mHplTrimOffset - TrimOffset;
732 printk("%s mHprTrimOffset = %d TrimOffset = %d \n",__func__,mHplTrimOffset,TrimOffset);
733 SetHplOffset(OffsetTrimming);
734 }
735
736 static void SetDcCompenSation(void)
737 {
738 SetHprOffsetTrim();
739 SetHpLOffsetTrim();
740 EnableDcCompensation(true);
741 }
742
743 static void OpenClassH(void)
744 {
745 Ana_Set_Reg(AFE_CLASSH_CFG7, 0xAD2D, 0xffff); // Classh CK fix 591KHz
746 Ana_Set_Reg(AFE_CLASSH_CFG8, 0x1313, 0xffff); // Classh CK fix 591KHz
747 Ana_Set_Reg(AFE_CLASSH_CFG9, 0x132d, 0xffff); // Classh CK fix 591KHz
748 Ana_Set_Reg(AFE_CLASSH_CFG10, 0x2d13, 0xffff); // Classh CK fix 591KHz
749 Ana_Set_Reg(AFE_CLASSH_CFG11, 0x1315, 0xffff); // Classh CK fix 591KHz
750 Ana_Set_Reg(AFE_CLASSH_CFG12, 0x6464, 0xffff); // Classh CK fix 591KHz
751 Ana_Set_Reg(AFE_CLASSH_CFG13, 0x2a2a, 0xffff); // Classh CK fix 591KHz
752 Ana_Set_Reg(AFE_CLASSH_CFG14, 0x009c, 0xffff); // Classh CK fix 591KHz
753 Ana_Set_Reg(AFE_CLASSH_CFG26, 0x9313, 0xffff); // Classh CK fix 591KHz
754 Ana_Set_Reg(AFE_CLASSH_CFG27, 0x1313, 0xffff); // Classh CK fix 591KHz
755 Ana_Set_Reg(AFE_CLASSH_CFG28, 0x1315, 0xffff); // Classh CK fix 591KHz
756 Ana_Set_Reg(AFE_CLASSH_CFG29, 0x1515, 0xffff); // Classh CK fix 591KHz
757 Ana_Set_Reg(AFE_CLASSH_CFG30, 0x1515, 0xffff); // Classh CK fix 591KHz
758 Ana_Set_Reg(AFE_CLASSH_CFG1, 0xBF04, 0xffff); // Classh CK fix 591KHz
759 Ana_Set_Reg(AFE_CLASSH_CFG2, 0x5fbf, 0xffff); // Classh CK fix 591KHz
760 Ana_Set_Reg(AFE_CLASSH_CFG3, 0x1104, 0xffff); // Classh CK fix 591KHz
761 Ana_Set_Reg(AFE_CLASSH_CFG4, 0x2412, 0xffff); // Classh CK fix 591KHz
762 Ana_Set_Reg(AFE_CLASSH_CFG5, 0x0201, 0xffff); // Classh CK fix 591KHz
763 Ana_Set_Reg(AFE_CLASSH_CFG6, 0x2800, 0xffff); // Classh CK fix 591KHz
764 Ana_Set_Reg(AFE_CLASSH_CFG14, 0x009c, 0xffff); // Classh CK fix 591KHz
765 Ana_Set_Reg(AFE_CLASSH_CFG21, 0x2108, 0xffff); // Classh CK fix 591KHz
766 Ana_Set_Reg(AFE_CLASSH_CFG22, 0x06db, 0xffff); // Classh CK fix 591KHz
767 Ana_Set_Reg(AFE_CLASSH_CFG23, 0xffff , 0xffff); // Classh CK fix 591KHz
768 Ana_Set_Reg(AFE_CLASSH_CFG24, 0x0bd6, 0xffff); // Classh CK fix 591KHz
769 Ana_Set_Reg(AFE_CLASSH_CFG25, 0x1740, 0xffff); // Classh CK fix 591KHz
770 Ana_Set_Reg(AFE_CLASSH_CFG0, 0xd608, 0xffff); // Classh CK fix 591KHz
771 udelay(100);
772 Ana_Set_Reg(AFE_CLASSH_CFG0, 0xd20d, 0xffff); // Classh CK fix 591KHz
773 udelay(100);
774 }
775
776 static void OpenClassAB(void)
777 {
778 Ana_Set_Reg(AFE_CLASSH_CFG7, 0x8909, 0xffff); // Classh CK fix 591KHz
779 Ana_Set_Reg(AFE_CLASSH_CFG8, 0x0909, 0xffff); // Classh CK fix 591KHz
780 Ana_Set_Reg(AFE_CLASSH_CFG9, 0x1309, 0xffff); // Classh CK fix 591KHz
781 Ana_Set_Reg(AFE_CLASSH_CFG10, 0x0909, 0xffff); // Classh CK fix 591KHz
782 Ana_Set_Reg(AFE_CLASSH_CFG11, 0x0915, 0xffff); // Classh CK fix 591KHz
783 Ana_Set_Reg(AFE_CLASSH_CFG12, 0x1414, 0xffff); // Classh CK fix 591KHz
784 Ana_Set_Reg(AFE_CLASSH_CFG13, 0x1414, 0xffff); // Classh CK fix 591KHz
785 Ana_Set_Reg(AFE_CLASSH_CFG14, 0x009c, 0xffff); // Classh CK fix 591KHz
786 Ana_Set_Reg(AFE_CLASSH_CFG26, 0x9313, 0xffff); // Classh CK fix 591KHz
787 Ana_Set_Reg(AFE_CLASSH_CFG27, 0x1313, 0xffff); // Classh CK fix 591KHz
788 Ana_Set_Reg(AFE_CLASSH_CFG28, 0x1315, 0xffff); // Classh CK fix 591KHz
789 Ana_Set_Reg(AFE_CLASSH_CFG29, 0x1515, 0xffff); // Classh CK fix 591KHz
790 Ana_Set_Reg(AFE_CLASSH_CFG30, 0x1515, 0xffff); // Classh CK fix 591KHz
791 Ana_Set_Reg(AFE_CLASSH_CFG1, 0x0024, 0xffff); // Classh CK fix 591KHz
792 Ana_Set_Reg(AFE_CLASSH_CFG2, 0x2f90, 0xffff); // Classh CK fix 591KHz
793 Ana_Set_Reg(AFE_CLASSH_CFG3, 0x1104, 0xffff); // Classh CK fix 591KHz
794 Ana_Set_Reg(AFE_CLASSH_CFG4, 0x2412, 0xffff); // Classh CK fix 591KHz
795 Ana_Set_Reg(AFE_CLASSH_CFG5, 0x0201, 0xffff); // Classh CK fix 591KHz
796 Ana_Set_Reg(AFE_CLASSH_CFG6, 0x2800, 0xffff); // Classh CK fix 591KHz
797 Ana_Set_Reg(AFE_CLASSH_CFG21, 0xa108, 0xffff); // Classh CK fix 591KHz
798 Ana_Set_Reg(AFE_CLASSH_CFG22, 0x06db, 0xffff); // Classh CK fix 591KHz
799 Ana_Set_Reg(AFE_CLASSH_CFG23, 0x0bd6, 0xffff); // Classh CK fix 591KHz
800 Ana_Set_Reg(AFE_CLASSH_CFG24, 0x1492, 0xffff); // Classh CK fix 591KHz
801 Ana_Set_Reg(AFE_CLASSH_CFG25, 0x1740, 0xffff); // Classh CK fix 591KHz
802 Ana_Set_Reg(AFE_CLASSH_CFG0, 0xd419, 0xffff); // Classh CK fix 591KHz
803 Ana_Set_Reg(AFE_CLASSH_CFG1, 0x0021, 0xffff); // Classh CK fix 591KHz
804 }
805
806 static void SetDCcoupleNP(int ADCType, int mode)
807 {
808 printk("%s ADCType= %d mode = %d\n", __func__, ADCType, mode);
809 #ifndef CONFIG_MTK_FPGA
810 switch (mode)
811 {
812 case AUDIO_ANALOGUL_MODE_ACC:
813 case AUDIO_ANALOGUL_MODE_DCC:
814 case AUDIO_ANALOGUL_MODE_DMIC:
815 {
816 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1)
817 {
818 mt6331_upmu_set_rg_audmicbias0dcswnen(false); // mic0 DC N external
819 mt6331_upmu_set_rg_audmicbias0dcswpen(false); // mic0 DC P external
820 }
821 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2)
822 {
823 mt6331_upmu_set_rg_audmicbias1dcswnen(false); // mic0 DC N external
824 mt6331_upmu_set_rg_audmicbias1dcswpen(false); // mic0 DC P external
825 }
826 }
827 break;
828 case AUDIO_ANALOGUL_MODE_DCCECMDIFF:
829 {
830 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1)
831 {
832 mt6331_upmu_set_rg_audmicbias0dcswnen(true); // mic0 DC N internal
833 mt6331_upmu_set_rg_audmicbias0dcswpen(true); // mic0 DC P internal
834 }
835 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2)
836 {
837 mt6331_upmu_set_rg_audmicbias1dcswnen(true); // mic0 DC N internal
838 mt6331_upmu_set_rg_audmicbias1dcswpen(true); // mic0 DC P internal
839 }
840 }
841 break;
842 case AUDIO_ANALOGUL_MODE_DCCECMSINGLE:
843 {
844 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1)
845 {
846 mt6331_upmu_set_rg_audmicbias0dcswnen(false); // mic0 DC N internal
847 mt6331_upmu_set_rg_audmicbias0dcswpen(true); // mic0 DC P internal
848 }
849 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2)
850 {
851 mt6331_upmu_set_rg_audmicbias1dcswnen(true); // mic0 DC N internal
852 mt6331_upmu_set_rg_audmicbias1dcswpen(false); // mic0 DC P internal
853 }
854 }
855 break;
856 default:
857 break;
858 }
859 #endif
860 }
861
862 static void OpenMicbias3(bool bEnable)
863 {
864 Ana_Set_Reg(AUDMICBIAS_CFG1, (bEnable << 7), (0x1 << 7));
865 }
866
867 static void OpenMicbias2(bool bEnable)
868 {
869 Ana_Set_Reg(AUDMICBIAS_CFG1, (bEnable << 0), (0x1 << 0));
870 }
871
872 static void SetMicVref2(uint32_t vRef)
873 {
874 Ana_Set_Reg(AUDMICBIAS_CFG1, vRef << 1, 0x7 << 1);
875 }
876
877 static void SetMicVref3(uint32_t vRef)
878 {
879 Ana_Set_Reg(AUDMICBIAS_CFG1, vRef << 8, 0x7 << 8);
880 }
881
882 static void EnableMicBias(uint32_t Mic, bool bEnable)
883 {
884 if (bEnable == true)
885 {
886 switch (Mic)
887 {
888 case AUDIO_ANALOG_DEVICE_IN_ADC1:
889 OpenMicbias0(true);
890 OpenMicbias1(true);
891 break;
892 case AUDIO_ANALOG_DEVICE_IN_ADC2:
893 OpenMicbias2(true);
894 break;
895 case AUDIO_ANALOG_DEVICE_IN_ADC3:
896 case AUDIO_ANALOG_DEVICE_IN_ADC4:
897 OpenMicbias3(true);
898 break;
899 }
900 }
901 else
902 {
903 switch (Mic)
904 {
905 case AUDIO_ANALOG_DEVICE_IN_ADC1:
906 OpenMicbias0(false);
907 OpenMicbias1(false);
908 break;
909 case AUDIO_ANALOG_DEVICE_IN_ADC2:
910 OpenMicbias2(false);
911 break;
912 case AUDIO_ANALOG_DEVICE_IN_ADC3:
913 case AUDIO_ANALOG_DEVICE_IN_ADC4:
914 OpenMicbias3(false);
915 break;
916 }
917 }
918 }
919
920 static void SetMic2DCcoupleSwitch(bool internal)
921 {
922 Ana_Set_Reg(AUDMICBIAS_CFG1, internal << 4, 0x1 << 4);
923 Ana_Set_Reg(AUDMICBIAS_CFG1, internal << 5, 0x1 << 5);
924 }
925
926 static void SetMic3DCcoupleSwitch(bool internal)
927 {
928 Ana_Set_Reg(AUDMICBIAS_CFG1, internal << 11, 0x1 << 4);
929 Ana_Set_Reg(AUDMICBIAS_CFG1, internal << 12, 0x1 << 5);
930 }
931
932 /*static void SetMic2DCcoupleSwitchSingle(bool internal)
933 {
934 Ana_Set_Reg(AUDMICBIAS_CFG1, 1 << 4, 0x1 << 4);
935 Ana_Set_Reg(AUDMICBIAS_CFG1, 0 << 5, 0x1 << 5);
936 }
937
938 static void SetMic3DCcoupleSwitchSingle(bool internal)
939 {
940 Ana_Set_Reg(AUDMICBIAS_CFG1, 1 << 11, 0x1 << 4);
941 Ana_Set_Reg(AUDMICBIAS_CFG1, 0 << 12, 0x1 << 5);
942 }*/
943
944 static void SetMic2powermode(bool lowpower)
945 {
946 Ana_Set_Reg(AUDMICBIAS_CFG1, lowpower << 6, 0x1 << 6);
947 }
948
949 static void SetMic3powermode(bool lowpower)
950 {
951 Ana_Set_Reg(AUDMICBIAS_CFG1, lowpower << 13, 0x1 << 13);
952 }
953
954
955 static void OpenMicbias1(bool bEnable)
956 {
957 printk("%s bEnable = %d \n", __func__, bEnable);
958 #ifndef CONFIG_MTK_FPGA
959 if (bEnable == true)
960 {
961 mt6331_upmu_set_rg_audpwdbmicbias1(true); // mic bias power 1 on
962 }
963 else
964 {
965 mt6331_upmu_set_rg_audmicbias1lowpen(true); // mic 1 low power mode
966 mt6331_upmu_set_rg_audpwdbmicbias1(false); // mic bias power 1 off
967 }
968 #endif
969 }
970
971 static void SetMicbias1lowpower(bool benable)
972 {
973 #ifndef CONFIG_MTK_FPGA
974 mt6331_upmu_set_rg_audmicbias1lowpen(benable); // mic 1 power mode
975 #endif
976 }
977
978 static void OpenMicbias0(bool bEanble)
979 {
980 printk("%s bEanble = %d\n", __func__, bEanble);
981 #ifndef CONFIG_MTK_FPGA
982 if (bEanble == true)
983 {
984 mt6331_upmu_set_rg_audpwdbmicbias0(true); // mic bias power 0 on
985 mt6331_upmu_set_rg_audmicbias0vref(0x2); // set to 1.9V
986 }
987 else
988 {
989 mt6331_upmu_set_rg_audmicbias0lowpen(true); // mic 0 low power mode
990 mt6331_upmu_set_rg_audpwdbmicbias0(false); // mic bias power 0 off
991 }
992 #endif
993 }
994
995 static void SetMicbias0lowpower(bool benable)
996 {
997 #ifndef CONFIG_MTK_FPGA
998 mt6331_upmu_set_rg_audmicbias0lowpen(benable); // mic 1 power mode
999 #endif
1000 }
1001
1002
1003
1004 /*static bool Dl_Hpdet_impedence(void)
1005 {
1006 ClsqAuxEnable(true);
1007 ClsqEnable(true);
1008 Topck_Enable(true);
1009 NvregEnable(true);
1010 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0000, 0xffff); //power on clock
1011 OpenClassH();
1012 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0028, 0xffff); //Enable cap-less LDOs (1.6V)
1013 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0068, 0xffff); //Enable NV regulator (-1.6V)
1014 Ana_Set_Reg(AUDBUF_CFG5, 0x001f, 0xffff); // enable HP bias circuits
1015 Ana_Set_Reg(ZCD_CON0, 0x0000, 0xffff); //Disable AUD_ZCD
1016 Ana_Set_Reg(AUDBUF_CFG0, 0xE000, 0xffff); //Disable headphone, voice and short-ckt protection.
1017 Ana_Set_Reg(AUDBUF_CFG1, 0x0000, 0xffff); //De_OSC of HP and output STBENH disable
1018 Ana_Set_Reg(AUDBUF_CFG8, 0x4000, 0xffff); //HPDET circuit enable
1019 Ana_Set_Reg(IBIASDIST_CFG0, 0x0092, 0xffff); //Enable IBIST
1020 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5501, 0xffff); //Enable AUD_CLK
1021 Ana_Set_Reg(AUDDAC_CFG0, 0x0009, 0xffff); //Enable Audio DAC
1022 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x4800, 0xffff); //Select HPR as HPDET output and select DACLP as HPDET circuit input
1023 //Hereafter, use AUXADC for HP impedance detection , start ADC....
1024
1025
1026 ClsqAuxEnable(false);
1027 ClsqEnable(false);
1028 Topck_Enable(false);
1029 NvregEnable(false);
1030 return true;
1031 }*/
1032
1033
1034 static uint32 GetULNewIFFrequency(uint32 frequency)
1035 {
1036 uint32 Reg_value = 0;
1037 switch (frequency)
1038 {
1039 case 8000:
1040 case 16000:
1041 case 32000:
1042 Reg_value = 1;
1043 break;
1044 case 48000:
1045 Reg_value = 3;
1046 default:
1047 break;
1048 }
1049 return Reg_value;
1050 }
1051
1052 uint32 GetULFrequency(uint32 frequency)
1053 {
1054 uint32 Reg_value = 0;
1055 printk("%s frequency =%d\n", __func__, frequency);
1056 switch (frequency)
1057 {
1058 case 8000:
1059 case 16000:
1060 case 32000:
1061 Reg_value = 0x0;
1062 break;
1063 case 48000:
1064 Reg_value = 0x1;
1065 default:
1066 break;
1067
1068 }
1069 return Reg_value;
1070 }
1071
1072
1073 uint32 ULSampleRateTransform(uint32 SampleRate)
1074 {
1075 switch (SampleRate)
1076 {
1077 case 8000:
1078 return 0;
1079 case 16000:
1080 return 1;
1081 case 32000:
1082 return 2;
1083 case 48000:
1084 return 3;
1085 default:
1086 break;
1087 }
1088 return 0;
1089 }
1090
1091
1092 static int mt63xx_codec_startup(struct snd_pcm_substream *substream , struct snd_soc_dai *Daiport)
1093 {
1094 //printk("+mt63xx_codec_startup name = %s number = %d\n", substream->name, substream->number);
1095 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && substream->runtime->rate)
1096 {
1097 //printk("mt63xx_codec_startup set up SNDRV_PCM_STREAM_CAPTURE rate = %d\n", substream->runtime->rate);
1098 mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC] = substream->runtime->rate;
1099
1100 }
1101 else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && substream->runtime->rate)
1102 {
1103 //printk("mt63xx_codec_startup set up SNDRV_PCM_STREAM_PLAYBACK rate = %d\n", substream->runtime->rate);
1104 mBlockSampleRate[AUDIO_ANALOG_DEVICE_OUT_DAC] = substream->runtime->rate;
1105 }
1106 //printk("-mt63xx_codec_startup name = %s number = %d\n", substream->name, substream->number);
1107 return 0;
1108 }
1109
1110 static int mt63xx_codec_prepare(struct snd_pcm_substream *substream , struct snd_soc_dai *Daiport)
1111 {
1112 //printk("mt63xx_codec_prepare set up rate = %d\n", substream->runtime->rate);
1113 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1114 {
1115 printk("mt63xx_codec_prepare set up SNDRV_PCM_STREAM_CAPTURE rate = %d\n", substream->runtime->rate);
1116 mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC] = substream->runtime->rate;
1117
1118 }
1119 else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1120 {
1121 printk("mt63xx_codec_prepare set up SNDRV_PCM_STREAM_PLAYBACK rate = %d\n", substream->runtime->rate);
1122 mBlockSampleRate[AUDIO_ANALOG_DEVICE_OUT_DAC] = substream->runtime->rate;
1123 }
1124 return 0;
1125 }
1126
1127 static int mt6323_codec_trigger(struct snd_pcm_substream *substream , int command , struct snd_soc_dai *Daiport)
1128 {
1129 switch (command)
1130 {
1131 case SNDRV_PCM_TRIGGER_START:
1132 case SNDRV_PCM_TRIGGER_RESUME:
1133 case SNDRV_PCM_TRIGGER_STOP:
1134 case SNDRV_PCM_TRIGGER_SUSPEND:
1135 break;
1136 }
1137
1138 //printk("mt6323_codec_trigger command = %d\n ", command);
1139 return 0;
1140 }
1141
1142 static const struct snd_soc_dai_ops mt6323_aif1_dai_ops =
1143 {
1144 .startup = mt63xx_codec_startup,
1145 .prepare = mt63xx_codec_prepare,
1146 .trigger = mt6323_codec_trigger,
1147 };
1148
1149 static struct snd_soc_dai_driver mtk_6331_dai_codecs[] =
1150 {
1151 {
1152 .name = MT_SOC_CODEC_TXDAI_NAME,
1153 .ops = &mt6323_aif1_dai_ops,
1154 .playback = {
1155 .stream_name = MT_SOC_DL1_STREAM_NAME,
1156 .channels_min = 1,
1157 .channels_max = 2,
1158 .rates = SNDRV_PCM_RATE_8000_48000,
1159 .formats = SND_SOC_ADV_MT_FMTS,
1160 },
1161 },
1162 {
1163 .name = MT_SOC_CODEC_RXDAI_NAME,
1164 .ops = &mt6323_aif1_dai_ops,
1165 .capture = {
1166 .stream_name = MT_SOC_UL1_STREAM_NAME,
1167 .channels_min = 1,
1168 .channels_max = 2,
1169 .rates = SNDRV_PCM_RATE_8000_48000,
1170 .formats = SND_SOC_ADV_MT_FMTS,
1171 },
1172 },
1173 {
1174 .name = MT_SOC_CODEC_TDMRX_DAI_NAME,
1175 .ops = &mt6323_aif1_dai_ops,
1176 .capture = {
1177 .stream_name = MT_SOC_TDM_CAPTURE_STREAM_NAME,
1178 .channels_min = 1,
1179 .channels_max = 2,
1180 .rates = SNDRV_PCM_RATE_8000_192000,
1181 .formats = SND_SOC_ADV_MT_FMTS,
1182 },
1183 },
1184 {
1185 .name = MT_SOC_CODEC_I2S0TXDAI_NAME,
1186 .ops = &mt6323_aif1_dai_ops,
1187 .playback = {
1188 .stream_name = MT_SOC_I2SDL1_STREAM_NAME,
1189 .channels_min = 1,
1190 .channels_max = 2,
1191 .rates = SNDRV_PCM_RATE_8000_48000,
1192 .formats = SND_SOC_ADV_MT_FMTS,
1193 }
1194 },
1195 {
1196 .name = MT_SOC_CODEC_PCMTXDAI_NAME,
1197 .ops = &mt6323_aif1_dai_ops,
1198 .playback = {
1199 .stream_name = MT_SOC_PCM2_STREAM_NAME,
1200 .channels_min = 1,
1201 .channels_max = 2,
1202 .rates = SNDRV_PCM_RATE_8000_48000,
1203 .formats = SND_SOC_ADV_MT_FMTS,
1204 },
1205 .capture = {
1206 .stream_name = MT_SOC_PCM2_STREAM_NAME,
1207 .channels_min = 1,
1208 .channels_max = 2,
1209 .rates = SNDRV_PCM_RATE_8000_48000,
1210 .formats = SND_SOC_ADV_MT_FMTS,
1211 },
1212 },
1213 {
1214 .name = MT_SOC_CODEC_PCMRXDAI_NAME,
1215 .ops = &mt6323_aif1_dai_ops,
1216 .playback = {
1217 .stream_name = MT_SOC_PCM1_STREAM_NAME,
1218 .channels_min = 1,
1219 .channels_max = 2,
1220 .rates = SNDRV_PCM_RATE_8000_48000,
1221 .formats = SND_SOC_ADV_MT_FMTS,
1222 },
1223 .capture = {
1224 .stream_name = MT_SOC_PCM1_STREAM_NAME,
1225 .channels_min = 1,
1226 .channels_max = 2,
1227 .rates = SNDRV_PCM_RATE_8000_48000,
1228 .formats = SND_SOC_ADV_MT_FMTS,
1229 },
1230 },
1231 {
1232 .name = MT_SOC_CODEC_VOICECALLEXTINTDAI_NAME,
1233 .ops = &mt6323_aif1_dai_ops,
1234 .playback = {
1235 .stream_name = MT_SOC_VOICE_EXTINT_STREAM_NAME,
1236 .channels_min = 1,
1237 .channels_max = 2,
1238 .rates = SNDRV_PCM_RATE_8000_48000,
1239 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1240 },
1241 .capture = {
1242 .stream_name = MT_SOC_VOICE_EXTINT_STREAM_NAME,
1243 .channels_min = 1,
1244 .channels_max = 2,
1245 .rates = SNDRV_PCM_RATE_8000_48000,
1246 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1247 },
1248 },
1249 {
1250 .name = MT_SOC_CODEC_FMI2S2RXDAI_NAME,
1251 .ops = &mt6323_aif1_dai_ops,
1252 .playback = {
1253 .stream_name = MT_SOC_FM_I2S2_STREAM_NAME,
1254 .channels_min = 1,
1255 .channels_max = 2,
1256 .rates = SNDRV_PCM_RATE_8000_48000,
1257 .formats = SND_SOC_ADV_MT_FMTS,
1258 },
1259 .capture = {
1260 .stream_name = MT_SOC_FM_I2S2_RECORD_STREAM_NAME,
1261 .channels_min = 1,
1262 .channels_max = 2,
1263 .rates = SNDRV_PCM_RATE_8000_48000,
1264 .formats = SND_SOC_ADV_MT_FMTS,
1265 },
1266 },
1267 {
1268 .name = MT_SOC_CODEC_FMMRGTXDAI_DUMMY_DAI_NAME,
1269 .ops = &mt6323_aif1_dai_ops,
1270 .playback = {
1271 .stream_name = MT_SOC_FM_MRGTX_STREAM_NAME,
1272 .channels_min = 1,
1273 .channels_max = 2,
1274 .rates = SNDRV_PCM_RATE_44100,
1275 .formats = SND_SOC_ADV_MT_FMTS,
1276 },
1277 },
1278 {
1279 .name = MT_SOC_CODEC_ULDLLOOPBACK_NAME,
1280 .ops = &mt6323_aif1_dai_ops,
1281 .playback = {
1282 .stream_name = MT_SOC_ULDLLOOPBACK_STREAM_NAME,
1283 .channels_min = 1,
1284 .channels_max = 2,
1285 .rates = SNDRV_PCM_RATE_8000_48000,
1286 .formats = SND_SOC_ADV_MT_FMTS,
1287 },
1288 .capture = {
1289 .stream_name = MT_SOC_ULDLLOOPBACK_STREAM_NAME,
1290 .channels_min = 1,
1291 .channels_max = 2,
1292 .rates = SNDRV_PCM_RATE_8000_48000,
1293 .formats = SND_SOC_ADV_MT_FMTS,
1294 },
1295 },
1296 {
1297 .name = MT_SOC_CODEC_STUB_NAME,
1298 .ops = &mt6323_aif1_dai_ops,
1299 .playback = {
1300 .stream_name = MT_SOC_ROUTING_STREAM_NAME,
1301 .channels_min = 1,
1302 .channels_max = 2,
1303 .rates = SNDRV_PCM_RATE_8000_48000,
1304 .formats = SND_SOC_ADV_MT_FMTS,
1305 },
1306 },
1307 {
1308 .name = MT_SOC_CODEC_RXDAI2_NAME,
1309 .capture = {
1310 .stream_name = MT_SOC_UL1DATA2_STREAM_NAME,
1311 .channels_min = 1,
1312 .channels_max = 2,
1313 .rates = SNDRV_PCM_RATE_8000_48000,
1314 .formats = SND_SOC_ADV_MT_FMTS,
1315 },
1316 },
1317 {
1318 .name = MT_SOC_CODEC_MRGRX_DAI_NAME,
1319 .ops = &mt6323_aif1_dai_ops,
1320 .playback = {
1321 .stream_name = MT_SOC_MRGRX_STREAM_NAME,
1322 .channels_min = 1,
1323 .channels_max = 8,
1324 .rates = SNDRV_PCM_RATE_8000_192000,
1325 .formats = SND_SOC_ADV_MT_FMTS,
1326 },
1327 .capture = {
1328 .stream_name = MT_SOC_MRGRX_STREAM_NAME,
1329 .channels_min = 1,
1330 .channels_max = 8,
1331 .rates = SNDRV_PCM_RATE_8000_192000,
1332 .formats = SND_SOC_ADV_MT_FMTS,
1333 },
1334 },
1335 {
1336 .name = MT_SOC_CODEC_HP_IMPEDANCE_NAME,
1337 .ops = &mt6323_aif1_dai_ops,
1338 .playback = {
1339 .stream_name = MT_SOC_HP_IMPEDANCE_STREAM_NAME,
1340 .channels_min = 1,
1341 .channels_max = 2,
1342 .rates = SNDRV_PCM_RATE_8000_48000,
1343 .formats = SND_SOC_ADV_MT_FMTS,
1344 },
1345 },
1346 {
1347 .name = MT_SOC_CODEC_MOD_DAI_NAME,
1348 .ops = &mt6323_aif1_dai_ops,
1349 .capture = {
1350 .stream_name = MT_SOC_MODDAI_STREAM_NAME,
1351 .channels_min = 1,
1352 .channels_max = 2,
1353 .rates = SNDRV_PCM_RATE_8000_48000,
1354 .formats = SND_SOC_ADV_MT_FMTS,
1355 },
1356 },
1357 };
1358
1359
1360 uint32 GetDLNewIFFrequency(unsigned int frequency)
1361 {
1362 uint32 Reg_value = 0;
1363 //printk("AudioPlatformDevice ApplyDLNewIFFrequency ApplyDLNewIFFrequency = %d", frequency);
1364 switch (frequency)
1365 {
1366 case 8000:
1367 Reg_value = 0;
1368 break;
1369 case 11025:
1370 Reg_value = 1;
1371 break;
1372 case 12000:
1373 Reg_value = 2;
1374 break;
1375 case 16000:
1376 Reg_value = 3;
1377 break;
1378 case 22050:
1379 Reg_value = 4;
1380 break;
1381 case 24000:
1382 Reg_value = 5;
1383 break;
1384 case 32000:
1385 Reg_value = 6;
1386 break;
1387 case 44100:
1388 Reg_value = 7;
1389 break;
1390 case 48000:
1391 Reg_value = 8;
1392 default:
1393 printk("ApplyDLNewIFFrequency with frequency = %d", frequency);
1394 }
1395 return Reg_value;
1396 }
1397
1398 static bool GetDLStatus(void)
1399 {
1400 int i = 0;
1401 for (i = 0; i < AUDIO_ANALOG_DEVICE_2IN1_SPK ; i++)
1402 {
1403 if (mCodec_data->mAudio_Ana_DevicePower[i] == true)
1404 {
1405 return true;
1406 }
1407 }
1408 return false;
1409 }
1410
1411 static void TurnOnDacPower(void)
1412 {
1413 printk("TurnOnDacPower\n");
1414 audckbufEnable(true);
1415 ClsqEnable(true);
1416 Topck_Enable(true);
1417 NvregEnable(true);
1418 if ((GetAdcStatus() == false))
1419 {
1420 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x003a, 0xffff); //power on clock
1421 }
1422 else
1423 {
1424 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0000, 0xffff); //power on clock
1425 }
1426 Ana_Set_Reg(AFUNC_AUD_CON2, 0x0006, 0xffffffff);
1427 Ana_Set_Reg(AFUNC_AUD_CON0, 0xc3a1, 0xffffffff); //sdm audio fifo clock power on
1428 Ana_Set_Reg(AFUNC_AUD_CON2, 0x0003, 0xffffffff); //sdm power on
1429 Ana_Set_Reg(AFUNC_AUD_CON2, 0x000b, 0xffffffff); //sdm fifo enable
1430 Ana_Set_Reg(AFE_DL_SDM_CON1, 0x001e, 0xffffffff); //set attenuation gainQuant
1431 Ana_Set_Reg(AFE_UL_DL_CON0 , 0x0001, 0xffffffff); //[0] afe enable
1432
1433 Ana_Set_Reg(AFE_PMIC_NEWIF_CFG0 , GetDLNewIFFrequency(mBlockSampleRate[AUDIO_ANALOG_DEVICE_OUT_DAC]) << 12 | 0x330 , 0xffffffff);
1434 Ana_Set_Reg(AFE_DL_SRC2_CON0_H , GetDLNewIFFrequency(mBlockSampleRate[AUDIO_ANALOG_DEVICE_OUT_DAC]) << 12 | 0x330 , 0xffffffff);
1435
1436 Ana_Set_Reg(AFE_DL_SRC2_CON0_L , 0x1801 , 0xffffffff); //turn off mute function and turn on dl
1437 Ana_Set_Reg(PMIC_AFE_TOP_CON0 , 0x0000 , 0xffffffff); //set DL in normal path, not from sine gen table
1438
1439 }
1440
1441 static void TurnOffDacPower(void)
1442 {
1443 printk("TurnOffDacPower\n");
1444 Ana_Set_Reg(AFE_CLASSH_CFG1, 0x24, 0xffff);
1445 Ana_Set_Reg(AFE_CLASSH_CFG0, 0xd518, 0xffff); // ClassH off
1446 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0, 0xffff); // NCP off
1447 ClsqEnable(false);
1448 Topck_Enable(false);
1449 NvregEnable(false);
1450 audckbufEnable(false);
1451 }
1452
1453 static void HeadsetVoloumeRestore(void)
1454 {
1455 int index = 0,oldindex = 0,offset =0,count =1;
1456 printk("%s\n", __func__);
1457 index = 8 ;
1458 oldindex = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR];
1459 if(index > oldindex)
1460 {
1461 printk("index = %d oldindex = %d \n",index,oldindex);
1462 offset = index - oldindex;
1463 while(offset >0)
1464 {
1465 Ana_Set_Reg(ZCD_CON2, ((oldindex + count)<<7 )|(oldindex + count) , 0xf9f);
1466 offset--;
1467 count++;
1468 udelay(100);
1469 }
1470 }
1471 else
1472 {
1473 printk("index = %d oldindex = %d \n",index,oldindex);
1474 offset = oldindex - index;
1475 while(offset >0)
1476 {
1477 Ana_Set_Reg(ZCD_CON2, ((oldindex-count)<<7)|(oldindex-count) , 0xf9f);
1478 offset--;
1479 count++;
1480 udelay(100);
1481 }
1482 }
1483 Ana_Set_Reg(ZCD_CON2, 0x489, 0xf9f);
1484 }
1485
1486 static void HeadsetVoloumeSet(void)
1487 {
1488 int index = 0,oldindex = 0,offset =0, count =1;
1489 printk("%s\n", __func__);
1490 index = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR];
1491 oldindex = 8;
1492 if(index > oldindex)
1493 {
1494 printk("index = %d oldindex = %d \n",index,oldindex);
1495 offset = index - oldindex;
1496 while(offset >0)
1497 {
1498 Ana_Set_Reg(ZCD_CON2, ((oldindex + count)<<7 )|(oldindex + count) , 0xf9f);
1499 offset--;
1500 count++;
1501 udelay(200);
1502 }
1503 }
1504 else
1505 {
1506 printk("index = %d oldindex = %d \n",index,oldindex);
1507 offset = oldindex - index;
1508 while(offset >0)
1509 {
1510 Ana_Set_Reg(ZCD_CON2, ((oldindex-count)<<7)|(oldindex-count) , 0xf9f);
1511 offset--;
1512 count++;
1513 udelay(200);
1514 }
1515 }
1516 Ana_Set_Reg(ZCD_CON2, (index << 7) | (index), 0xf9f);
1517 }
1518
1519 static void Audio_Amp_Change(int channels , bool enable)
1520 {
1521 if (enable)
1522 {
1523 if (GetDLStatus() == false)
1524 {
1525 TurnOnDacPower();
1526 }
1527 // here pmic analog control
1528 if (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTL] == false &&
1529 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTR] == false)
1530 {
1531 printk("%s \n", __func__);
1532
1533 OpenClassH();
1534
1535 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0028, 0xffff); // Enable cap-less LDOs (1.6V)
1536 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0068, 0xffff); // Enable NV regulator (-1.6V)
1537
1538 Ana_Set_Reg(ZCD_CON0, 0x0000, 0xffff); // Disable AUD_ZCD_CFG0
1539 Ana_Set_Reg(AUDBUF_CFG0, 0xE000, 0xffff); // Disable headphone, voice and short-ckt protection.
1540 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x8068, 0xffff); // Enable AU_REFN short circuit
1541 Ana_Set_Reg(IBIASDIST_CFG0, 0x0092, 0xffff); //Enable IBIST
1542 Ana_Set_Reg(AUDBUF_CFG5, 0x0007, 0x0007); // enable HP bias circuits
1543
1544 Ana_Set_Reg(ZCD_CON2, 0x0489 , 0xffff); // Set HPR/HPL gain as 0dB, step by step
1545 Ana_Set_Reg(ZCD_CON3, 0x001F , 0xffff); //Set voice gain as minimum (~ -40dB)
1546 Ana_Set_Reg(AUDBUF_CFG1, 0x900 , 0xffff); //De_OSC of HP and enable output STBENH
1547 Ana_Set_Reg(AUDBUF_CFG2, 0x0022 , 0xffff); //De_OSC of voice, enable output STBENH
1548 Ana_Set_Reg(AUDBUF_CFG0, 0xE001 , 0xffff); //Enable voice driver
1549 Ana_Set_Reg(AUDBUF_CFG1, 0x940 , 0xffff); //Enable pre-charge buffer
1550 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5501 , 0xffff); //Enable AUD_CLK
1551 Ana_Set_Reg(AUDDAC_CFG0, 0x000f , 0x000f); //Enable Audio DAC_DL_PGA_Handset_GAIN
1552 udelay(100);
1553 Ana_Set_Reg(AUDBUF_CFG0, 0xE141 , 0xffff);
1554 Ana_Set_Reg(ZCD_CON2, 0x0489 , 0xffff); //Set HPR/HPL gain as 0dB gain
1555 SetDcCompenSation();
1556 udelay(100);
1557 // here may cause pop
1558 Ana_Set_Reg(AUDBUF_CFG0, 0xe147 , 0xffff); // Enable HPR/HPL
1559 Ana_Set_Reg(AUDBUF_CFG0, 0xE14e , 0xffff); // Enable HPR/HPL
1560 Ana_Set_Reg(AUDBUF_CFG5, 0x0003, 0x0007); // enable HP bias circuits
1561 Ana_Set_Reg(AUDBUF_CFG1, 0x0900 , 0xffff); // Disable pre-charge buffer
1562 Ana_Set_Reg(AUDBUF_CFG2, 0x0020 , 0xffff); // Disable De_OSC of voice
1563 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0068, 0xffff);//Disable AU_REFN short circuit
1564
1565 // apply volume setting
1566 HeadsetVoloumeSet();
1567 }
1568 else if (channels == AUDIO_ANALOG_CHANNELS_LEFT1)
1569 {
1570 //Ana_Set_Reg(AUDDAC_CFG0, 0x000f, 0xffff); // enable audio bias. enable audio DAC, HP buffers
1571
1572 }
1573 else if (channels == AUDIO_ANALOG_CHANNELS_RIGHT1)
1574 {
1575 //Ana_Set_Reg(AUDDAC_CFG0, 0x000f, 0xffff); // enable audio bias. enable audio DAC, HP buffers
1576 }
1577 }
1578 else
1579 {
1580
1581 if (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTL] == false &&
1582 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTR] == false)
1583 {
1584 printk("Audio_Amp_Change off amp\n");
1585 HeadsetVoloumeRestore();// Set HPR/HPL gain as 0dB, step by step
1586 //Ana_Set_Reg(ZCD_CON2, 0x0489 , 0xffff);
1587 Ana_Set_Reg(AUDBUF_CFG0, 0xE148, 0xffff); // Disable HPR/HPL
1588 Ana_Set_Reg(AUDDAC_CFG0, 0x0000, 0xffff); // Disable Audio DAC
1589 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5500, 0xffff); // Disable AUD_CLK
1590 Ana_Set_Reg(IBIASDIST_CFG0, 0x0192, 0xffff); // Disable IBIST
1591 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0028, 0xffff); // Disable NV regulator (-1.6V)
1592 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0000, 0xffff); // Disable cap-less LDOs (1.6V)
1593 Ana_Set_Reg(AUDBUF_CFG5, 0x0000, 0x0003); // enable HP bias circuits
1594 EnableDcCompensation(false);
1595 }
1596 else if (channels == AUDIO_ANALOG_CHANNELS_LEFT1)
1597 {
1598 //Ana_Set_Reg(AUDDAC_CFG0, 0x000e, 0xffff); // enable audio bias. enable audio DAC, HP buffers
1599 }
1600 else if (channels == AUDIO_ANALOG_CHANNELS_RIGHT1)
1601 {
1602 //Ana_Set_Reg(AUDDAC_CFG0, 0x000d, 0xffff); // enable audio bias. enable audio DAC, HP buffers
1603 }
1604 if (GetDLStatus() == false)
1605 {
1606 Ana_Set_Reg(AFE_DL_SRC2_CON0_L , 0x1800 , 0xffffffff);
1607 if (GetAdcStatus() == false)
1608 {
1609 Ana_Set_Reg(AFE_UL_DL_CON0, 0x0000, 0xffff); //turn off afe
1610 }
1611 TurnOffDacPower();
1612 }
1613 }
1614 }
1615
1616 static int Audio_AmpL_Get(struct snd_kcontrol *kcontrol,
1617 struct snd_ctl_elem_value *ucontrol)
1618 {
1619 printk("Audio_AmpL_Get = %d\n", mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTL]);
1620 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTL];
1621 return 0;
1622 }
1623
1624 static int Audio_AmpL_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1625 {
1626 mutex_lock(&Ana_Ctrl_Mutex);
1627
1628 printk("%s() gain = %ld \n ", __func__, ucontrol->value.integer.value[0]);
1629 if ((ucontrol->value.integer.value[0] == true) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTL] == false))
1630 {
1631 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_LEFT1 , true);
1632 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTL] = ucontrol->value.integer.value[0];
1633 }
1634 else if ((ucontrol->value.integer.value[0] == false) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTL] == true))
1635 {
1636 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTL] = ucontrol->value.integer.value[0];
1637 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_LEFT1 , false);
1638 }
1639 mutex_unlock(&Ana_Ctrl_Mutex);
1640 return 0;
1641 }
1642
1643 static int Audio_AmpR_Get(struct snd_kcontrol *kcontrol,
1644 struct snd_ctl_elem_value *ucontrol)
1645 {
1646 printk("Audio_AmpR_Get = %d\n", mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTR]);
1647 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTR];
1648 return 0;
1649 }
1650
1651 static int Audio_AmpR_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1652 {
1653 mutex_lock(&Ana_Ctrl_Mutex);
1654
1655 printk("%s()\n", __func__);
1656 if ((ucontrol->value.integer.value[0] == true) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTR] == false))
1657 {
1658 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_RIGHT1 , true);
1659 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTR] = ucontrol->value.integer.value[0];
1660 }
1661 else if ((ucontrol->value.integer.value[0] == false) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTR] == true))
1662 {
1663 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HPOUTR] = ucontrol->value.integer.value[0];
1664 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_RIGHT1 , false);
1665 }
1666 mutex_unlock(&Ana_Ctrl_Mutex);
1667 return 0;
1668 }
1669
1670 /*static void SetVoiceAmpVolume(void)
1671 {
1672 int index;
1673 printk("%s\n", __func__);
1674 index = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HSOUTL];
1675 Ana_Set_Reg(ZCD_CON3, index , 0x001f);
1676 }*/
1677
1678 static void Voice_Amp_Change(bool enable)
1679 {
1680 if (enable)
1681 {
1682 printk("turn on ampL\n");
1683 if (GetDLStatus() == false)
1684 {
1685 Ana_Set_Reg(0x0680, 0x0000, 0xffff); // Enable AUDGLB
1686 Ana_Set_Reg(TOP_CKSEL_CON_CLR, 0x0001, 0x0001); //use internal 26M
1687 TurnOnDacPower();
1688 printk("Voice_Amp_Change on amp\n");
1689 OpenClassAB();
1690 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0028, 0xffff); // Enable cap-less LDOs (1.6V)
1691 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0068, 0xffff); // Enable NV regulator (-1.6V)
1692 Ana_Set_Reg(AUDBUF_CFG5, 0x001f, 0xffff); // enable HP bias circuits
1693 Ana_Set_Reg(ZCD_CON0, 0x0700, 0xffff); // Disable AUD_ZCD
1694 Ana_Set_Reg(AUDBUF_CFG0, 0xE008, 0xffff); // Disable headphone, voice and short-ckt protection.
1695 Ana_Set_Reg(IBIASDIST_CFG0, 0x0092, 0xffff); //Enable IBIST
1696 Ana_Set_Reg(ZCD_CON3, 0x001F , 0xffff); //Set voice gain as minimum (~ -40dB)
1697 Ana_Set_Reg(AUDBUF_CFG2, 0x0022 , 0xffff); //De_OSC of voice, enable output STBENH
1698 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5501 , 0xffff); //Enable voice driver
1699 Ana_Set_Reg(AUDDAC_CFG0, 0x0009 , 0xffff); //Switch voice MUX to audio DAC
1700 Ana_Set_Reg(AUDBUF_CFG0, 0xE010 , 0xffff); //Enable voice driver
1701 Ana_Set_Reg(AUDBUF_CFG0, 0xE011 , 0xffff); //Enable voice driver
1702 Ana_Set_Reg(ZCD_CON3, 0x0009 , 0xffff); //Set voice gain as 0dB
1703 }
1704 }
1705 else
1706 {
1707 printk("turn off ampL\n");
1708 if (GetDLStatus() == false)
1709 {
1710 TurnOffDacPower();
1711 Ana_Set_Reg(AUDBUF_CFG0, 0xE010 , 0xffff); //Disable voice driver
1712 Ana_Set_Reg(AUDDAC_CFG0, 0x0000 , 0xffff); //Disable L-ch Audio DAC
1713 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5500 , 0xffff); //Disable AUD_CLK
1714 Ana_Set_Reg(IBIASDIST_CFG0, 0x0192 , 0xffff); //Disable IBIST
1715 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0028 , 0xffff); //Disable NV regulator (-1.6V)
1716 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0000 , 0xffff); //Disable cap-less LDOs (1.6V)
1717 }
1718 }
1719 }
1720
1721 static int Voice_Amp_Get(struct snd_kcontrol *kcontrol,
1722 struct snd_ctl_elem_value *ucontrol)
1723 {
1724 printk("Voice_Amp_Get = %d\n", mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HSOUTL]);
1725 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HSOUTL];
1726 return 0;
1727 }
1728
1729 static int Voice_Amp_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1730 {
1731 mutex_lock(&Ana_Ctrl_Mutex);
1732 printk("%s()\n", __func__);
1733 if ((ucontrol->value.integer.value[0] == true) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HSOUTL] == false))
1734 {
1735 Voice_Amp_Change(true);
1736 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HSOUTL] = ucontrol->value.integer.value[0];
1737 }
1738 else if ((ucontrol->value.integer.value[0] == false) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HSOUTL] == true))
1739 {
1740 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_HSOUTL] = ucontrol->value.integer.value[0];
1741 Voice_Amp_Change(false);
1742 }
1743 mutex_unlock(&Ana_Ctrl_Mutex);
1744 return 0;
1745 }
1746
1747 static void Speaker_Amp_Change(bool enable)
1748 {
1749 if (enable)
1750 {
1751 if (GetDLStatus() == false)
1752 {
1753 TurnOnDacPower();
1754 }
1755 printk("turn on Speaker_Amp_Change \n");
1756 // here pmic analog control
1757 //Ana_Set_Reg(AUDNVREGGLB_CFG0 , 0x0000 , 0xffffffff);
1758 OpenClassAB();
1759 Ana_Set_Reg(AUDLDO_NVREG_CFG0 , 0x0028 , 0xffffffff); //Enable cap-less LDOs (1.6V)
1760 Ana_Set_Reg(AUDLDO_NVREG_CFG0 , 0x0068 , 0xffffffff); //Enable NV regulator (-1.6V)
1761 Ana_Set_Reg(AUDBUF_CFG5, 0x001f, 0xffff); // enable HP bias circuits
1762 Ana_Set_Reg(ZCD_CON0 , 0x0700 , 0xffffffff); //Disable AUD_ZCD
1763 Ana_Set_Reg(AUDBUF_CFG6 , 0x00C0 , 0xffffffff); // Disable line-out and short-ckt protection. LO MUX is opened
1764 Ana_Set_Reg(IBIASDIST_CFG0 , 0x0092 , 0xffffffff); // Enable IBIST
1765 Ana_Set_Reg(ZCD_CON1 , 0x0F9F , 0xffffffff); // Set LOR/LOL gain as minimum (~ -40dB)
1766 Ana_Set_Reg(AUDBUF_CFG7 , 0x0102 , 0xffffffff); // De_OSC of LO and enable output STBENH
1767 Ana_Set_Reg(AUDCLKGEN_CFG0 , 0x5501 , 0xffffffff); // Enable AUD_CLK
1768 Ana_Set_Reg(AUDDAC_CFG0 , 0x000F , 0xffffffff); //Enable Audio DAC
1769 SetDcCompenSation();
1770 Ana_Set_Reg(AUDBUF_CFG6 , 0x00E8 , 0xffffffff); //Switch LO MUX to audio DAC
1771 Ana_Set_Reg(AUDBUF_CFG6 , 0x00EB , 0xffffffff); //Enable LOR/LOL
1772 Ana_Set_Reg(ZCD_CON1 , 0x0489 , 0xffffffff); // Set LOR/LOL gain as 0dB
1773 #ifdef CONFIG_MTK_SPEAKER
1774 if (Speaker_mode == AUDIO_SPEAKER_MODE_D)
1775 {
1776 Speaker_ClassD_Open();
1777 }
1778 else if (Speaker_mode == AUDIO_SPEAKER_MODE_AB)
1779 {
1780 Speaker_ClassAB_Open();
1781 }
1782 else if (Speaker_mode == AUDIO_SPEAKER_MODE_RECEIVER)
1783 {
1784 Speaker_ReveiverMode_Open();
1785 }
1786 #endif
1787 Apply_Speaker_Gain();
1788 }
1789 else
1790 {
1791 printk("turn off Speaker_Amp_Change \n");
1792 #ifdef CONFIG_MTK_SPEAKER
1793 if (Speaker_mode == AUDIO_SPEAKER_MODE_D)
1794 {
1795 Speaker_ClassD_close();
1796 }
1797 else if (Speaker_mode == AUDIO_SPEAKER_MODE_AB)
1798 {
1799 Speaker_ClassAB_close();
1800 }
1801 else if (Speaker_mode == AUDIO_SPEAKER_MODE_RECEIVER)
1802 {
1803 Speaker_ReveiverMode_close();
1804 }
1805 #endif
1806 if (GetDLStatus() == false)
1807 {
1808 TurnOffDacPower();
1809 }
1810 Ana_Set_Reg(AUDBUF_CFG6 , 0x00E8 , 0xffffffff); // Disable LOR/LOL
1811 Ana_Set_Reg(AUDBUF_CFG6 , 0x0000 , 0xffffffff);
1812 Ana_Set_Reg(AUDBUF_CFG7 , 0x0900 , 0xffffffff);
1813 Ana_Set_Reg(AUDDAC_CFG0 , 0x0000 , 0xffffffff); // Disable Audio DAC
1814 Ana_Set_Reg(AUDCLKGEN_CFG0 , 0x5500 , 0xffffffff); // Disable AUD_CLK
1815 Ana_Set_Reg(IBIASDIST_CFG0 , 0x0192 , 0xffffffff); // Disable IBIST
1816 Ana_Set_Reg(AUDLDO_NVREG_CFG0 , 0x0028 , 0xffffffff); // Disable NV regulator (-1.6V)
1817 Ana_Set_Reg(AUDLDO_NVREG_CFG0 , 0x0000 , 0xffffffff); // Disable cap-less LDOs (1.6V)
1818 }
1819 }
1820
1821 static int Speaker_Amp_Get(struct snd_kcontrol *kcontrol,
1822 struct snd_ctl_elem_value *ucontrol)
1823 {
1824 printk("%s()\n", __func__);
1825 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_SPKL] ;
1826 return 0;
1827 }
1828
1829 static int Speaker_Amp_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1830 {
1831
1832 printk("%s() value = %ld \n ", __func__, ucontrol->value.integer.value[0]);
1833 if ((ucontrol->value.integer.value[0] == true) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_SPKL] == false))
1834 {
1835 Speaker_Amp_Change(true);
1836 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_SPKL] = ucontrol->value.integer.value[0];
1837 }
1838 else if ((ucontrol->value.integer.value[0] == false) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_SPKL] == true))
1839 {
1840 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_SPKL] = ucontrol->value.integer.value[0];
1841 Speaker_Amp_Change(false);
1842 }
1843 return 0;
1844 }
1845
1846 static void Headset_Speaker_Amp_Change(bool enable)
1847 {
1848 if (enable)
1849 {
1850 if (GetDLStatus() == false)
1851 {
1852 TurnOnDacPower();
1853 }
1854 printk("turn on Speaker_Amp_Change \n");
1855 // here pmic analog control
1856 //Ana_Set_Reg(AUDNVREGGLB_CFG0 , 0x0000 , 0xffffffff);
1857 OpenClassAB();
1858
1859 Ana_Set_Reg(AUDLDO_NVREG_CFG0 , 0x0028 , 0xffffffff); //Enable cap-less LDOs (1.6V)
1860 Ana_Set_Reg(AUDLDO_NVREG_CFG0 , 0x0068 , 0xffffffff); //Enable NV regulator (-1.6V)
1861 Ana_Set_Reg(AUDBUF_CFG5, 0x001f, 0xffff); // enable HP bias circuits
1862 Ana_Set_Reg(ZCD_CON0 , 0x0700 , 0xffffffff); //Disable AUD_ZCD
1863
1864 Ana_Set_Reg(AUDBUF_CFG0 , 0xE008 , 0xffffffff); //Disable headphone, voice and short-ckt protection.
1865 Ana_Set_Reg(AUDBUF_CFG6 , 0x00C0 , 0xffffffff); // Disable line-out and short-ckt protection. LO MUX is opened
1866
1867 Ana_Set_Reg(IBIASDIST_CFG0 , 0x0092 , 0xffffffff); // Enable IBIST
1868 Ana_Set_Reg(ZCD_CON2 , 0x0489 , 0xffffffff); // Set LOR/LOL gain as minimum (~ -40dB)
1869 Ana_Set_Reg(ZCD_CON1 , 0x0489 , 0xffffffff); // Set LOR/LOL gain as minimum (~ -40dB)
1870 Ana_Set_Reg(ZCD_CON3 , 0x001F , 0xffffffff); // Set voice gain as minimum (~ -40dB)
1871
1872 Ana_Set_Reg(AUDBUF_CFG1 , 0x0900 , 0xffffffff); // De_OSC of HP and enable output STBENH
1873 Ana_Set_Reg(AUDBUF_CFG7 , 0x0102 , 0xffffffff); // De_OSC of LO and enable output STBENH
1874 Ana_Set_Reg(AUDBUF_CFG2 , 0x0022 , 0xffffffff); // De_OSC of voice, enable output STBENH
1875 Ana_Set_Reg(AUDBUF_CFG0 , 0xE009 , 0xffffffff); // Enable voice driver
1876 Ana_Set_Reg(AUDBUF_CFG1 , 0x0940 , 0xffffffff); // Enable pre-charge buffer_map_state
1877 msleep(1);
1878
1879 Ana_Set_Reg(AUDCLKGEN_CFG0 , 0x5501 , 0xffffffff); // Enable AUD_CLK
1880 Ana_Set_Reg(AUDDAC_CFG0 , 0x000F , 0xffffffff); //Enable Audio DAC
1881 SetDcCompenSation();
1882 Ana_Set_Reg(AUDBUF_CFG6 , 0x00E8 , 0xffffffff); //Switch LO MUX to audio DAC
1883 Ana_Set_Reg(AUDBUF_CFG6 , 0x00EB , 0xffffffff); //Enable LOR/LOL
1884 Ana_Set_Reg(ZCD_CON1 , 0x0489 , 0xffffffff); // Set LOR/LOL gain as 0dB
1885
1886 Ana_Set_Reg(AUDBUF_CFG0 , 0xE0A9 , 0xffffffff); // Switch HP MUX to audio DAC
1887 Ana_Set_Reg(AUDBUF_CFG0 , 0xE0AF , 0xffffffff); // Enable HPR/HPL
1888 Ana_Set_Reg(AUDBUF_CFG1 , 0x0900 , 0xffffffff); // Disable pre-charge buffer
1889 Ana_Set_Reg(AUDBUF_CFG2 , 0x0020 , 0xffffffff); // Disable De_OSC of voice
1890 Ana_Set_Reg(AUDBUF_CFG0 , 0xE0AE , 0xffffffff); // Disable voice buffer
1891 Ana_Set_Reg(AUDBUF_CFG2 , 0x0489 , 0xffffffff); // Set HPR/HPL gain as 0dB
1892
1893 #ifdef CONFIG_MTK_SPEAKER
1894 if (Speaker_mode == AUDIO_SPEAKER_MODE_D)
1895 {
1896 Speaker_ClassD_Open();
1897 }
1898 else if (Speaker_mode == AUDIO_SPEAKER_MODE_AB)
1899 {
1900 Speaker_ClassAB_Open();
1901 }
1902 else if (Speaker_mode == AUDIO_SPEAKER_MODE_RECEIVER)
1903 {
1904 Speaker_ReveiverMode_Open();
1905 }
1906 #endif
1907 HeadsetRVolumeSet();
1908 HeadsetLVolumeSet();
1909 Apply_Speaker_Gain();
1910 }
1911 else
1912 {
1913
1914 #ifdef CONFIG_MTK_SPEAKER
1915 if (Speaker_mode == AUDIO_SPEAKER_MODE_D)
1916 {
1917 Speaker_ClassD_close();
1918 }
1919 else if (Speaker_mode == AUDIO_SPEAKER_MODE_AB)
1920 {
1921 Speaker_ClassAB_close();
1922 }
1923 else if (Speaker_mode == AUDIO_SPEAKER_MODE_RECEIVER)
1924 {
1925 Speaker_ReveiverMode_close();
1926 }
1927 #endif
1928
1929 Ana_Set_Reg(AUDBUF_CFG0 , 0xE149 , 0xffff); // Disable HPR/HPL
1930 Ana_Set_Reg(AUDDAC_CFG0 , 0x0000 , 0xffff); // Disable Audio DAC
1931 Ana_Set_Reg(AUDBUF_CFG0 , 0xE148 , 0xffff);
1932 Ana_Set_Reg(AUDBUF_CFG2 , 0x0020 , 0xffff);
1933 Ana_Set_Reg(AUDBUF_CFG6 , 0x0000 , 0xffff);
1934 Ana_Set_Reg(AUDBUF_CFG7 , 0x0902 , 0xffff);
1935 Ana_Set_Reg(AUDCLKGEN_CFG0 , 0x5500 , 0xffff); // Disable AUD_CLK
1936 Ana_Set_Reg(IBIASDIST_CFG0 , 0x0192 , 0xffff); // Disable IBIST
1937 Ana_Set_Reg(AUDLDO_NVREG_CFG0 , 0x0028 , 0xffff); // Disable NV regulator (-1.6V)
1938 Ana_Set_Reg(AUDLDO_NVREG_CFG0 , 0x0000 , 0xffff); // Disable cap-less LDOs (1.6V)
1939
1940 printk("turn off Speaker_Amp_Change \n");
1941 if (GetDLStatus() == false)
1942 {
1943 Ana_Set_Reg(AFE_DL_SRC2_CON0_L , 0x1800 , 0xffff);
1944 if (GetAdcStatus() == false)
1945 {
1946 Ana_Set_Reg(AFE_UL_DL_CON0, 0x0000, 0xffff); //turn off afe
1947 }
1948 TurnOffDacPower();
1949 }
1950 }
1951
1952 }
1953
1954
1955 static int Headset_Speaker_Amp_Get(struct snd_kcontrol *kcontrol,
1956 struct snd_ctl_elem_value *ucontrol)
1957 {
1958 printk("%s()\n", __func__);
1959 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_SPEAKER_HEADSET_R] ;
1960 return 0;
1961 }
1962
1963 static int Headset_Speaker_Amp_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1964 {
1965 //struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1966
1967 printk("%s() gain = %lu \n ", __func__, ucontrol->value.integer.value[0]);
1968 if ((ucontrol->value.integer.value[0] == true) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_SPEAKER_HEADSET_R] == false))
1969 {
1970 Headset_Speaker_Amp_Change(true);
1971 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_SPEAKER_HEADSET_R] = ucontrol->value.integer.value[0];
1972 }
1973 else if ((ucontrol->value.integer.value[0] == false) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_SPEAKER_HEADSET_R] == true))
1974 {
1975 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_VOLUME_SPEAKER_HEADSET_R] = ucontrol->value.integer.value[0];
1976 Headset_Speaker_Amp_Change(false);
1977 }
1978 return 0;
1979 }
1980
1981 #ifdef CONFIG_MTK_SPEAKER
1982 static const char *speaker_amp_function[] = {"CALSSD", "CLASSAB", "RECEIVER"};
1983 static const char *speaker_PGA_function[] = {"0Db", "4Db", "5Db", "6Db", "7Db", "8Db", "9Db", "10Db",
1984 "11Db", "12Db", "13Db", "14Db", "15Db", "16Db", "17Db"
1985 };
1986 static const char *speaker_OC_function[] = {"Off", "On"};
1987 static const char *speaker_CS_function[] = {"Off", "On"};
1988 static const char *speaker_CSPeakDetecReset_function[] = {"Off", "On"};
1989
1990 static int Audio_Speaker_Class_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1991 {
1992 mutex_lock(&Ana_Ctrl_Mutex);
1993 Speaker_mode = ucontrol->value.integer.value[0];
1994 mutex_unlock(&Ana_Ctrl_Mutex);
1995 return 0;
1996 }
1997
1998 static int Audio_Speaker_Class_Get(struct snd_kcontrol *kcontrol,
1999 struct snd_ctl_elem_value *ucontrol)
2000 {
2001 ucontrol->value.integer.value[0] = Speaker_mode ;
2002 return 0;
2003 }
2004
2005 static int Audio_Speaker_Pga_Gain_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2006 {
2007 Speaker_pga_gain = ucontrol->value.integer.value[0];
2008 Ana_Set_Reg(SPK_CON9, (Speaker_pga_gain +1)<< 8, 0xf << 8);
2009 return 0;
2010 }
2011
2012 static int Audio_Speaker_OcFlag_Get(struct snd_kcontrol *kcontrol,
2013 struct snd_ctl_elem_value *ucontrol)
2014 {
2015 mSpeaker_Ocflag = GetSpeakerOcFlag();
2016 ucontrol->value.integer.value[0] = mSpeaker_Ocflag ;
2017 return 0;
2018 }
2019
2020 static int Audio_Speaker_OcFlag_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2021 {
2022 printk("%s is not support setting \n", __func__);
2023 return 0;
2024 }
2025
2026 static int Audio_Speaker_Pga_Gain_Get(struct snd_kcontrol *kcontrol,
2027 struct snd_ctl_elem_value *ucontrol)
2028 {
2029 ucontrol->value.integer.value[0] = Speaker_pga_gain ;
2030 return 0;
2031 }
2032
2033 static int Audio_Speaker_Current_Sensing_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2034 {
2035 static int dauxadc1_tempval = 0;
2036
2037 if (ucontrol->value.integer.value[0])
2038 {
2039 printk("enable Audio_Speaker_Current_Sensing_Set\n");
2040 //Ana_Set_Reg (SPK_CON12, 0x9300, 0xffff);CON12 invalid @ 6332
2041 Ana_Set_Reg(SPK_CON16, 0x8000, 0x8000); //[15]ISENSE enable
2042 Ana_Set_Reg(SPK_CON14, 0x0050, 0x0050); //[6]VSENSE enable
2043 mEnableAuxAdc = 1;
2044 dauxadc1_tempval = Ana_Get_Reg(0x886a);
2045 Ana_Set_Reg(0x886a, 0x00b0, 0xFFFF); // Important
2046 }
2047 else
2048 {
2049 printk("disable Audio_Speaker_Current_Sensing_Set\n");
2050 //Ana_Set_Reg (SPK_CON12, 0x1300, 0xffff); CON12 invalid @ 6332
2051 Ana_Set_Reg(SPK_CON16, 0x0, 0x8000); //[15]ISENSE disable
2052 Ana_Set_Reg(SPK_CON14, 0x0, 0x0050); //[6]VSENSE enable
2053 Ana_Set_Reg(0x80be, 0x02, 0x02);
2054 Ana_Set_Reg(0x80c0, 0x02, 0x02);
2055 Ana_Set_Reg(MT6332_AUXADC_CON12, 0, 0x8000); //[15]Set Speaker mode
2056 Ana_Set_Reg(MT6332_AUXADC_CON0, 0x0000, 0x8000);
2057 Ana_Set_Reg(0x886a, dauxadc1_tempval, 0xFFFF); // Important
2058 mEnableAuxAdc = 0;
2059 }
2060 return 0;
2061 }
2062
2063 static int Audio_Speaker_Current_Sensing_Get(struct snd_kcontrol *kcontrol,
2064 struct snd_ctl_elem_value *ucontrol)
2065 {
2066 //ucontrol->value.integer.value[0] = (Ana_Get_Reg (SPK_CON12)>>15)&0x01;
2067 ucontrol->value.integer.value[0] = (Ana_Get_Reg(SPK_CON16) >> 15) & 0x01; //[15]ISENSE
2068 return 0;
2069 }
2070
2071 static int Audio_Speaker_Current_Sensing_Peak_Detector_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2072 {
2073 /*
2074 if (ucontrol->value.integer.value[0])
2075 Ana_Set_Reg (SPK_CON12, 1<<14, 1<<14);
2076 else
2077 Ana_Set_Reg (SPK_CON12, 0, 1<<14);
2078 */
2079 return 0;
2080 }
2081
2082 static int Audio_Speaker_Current_Sensing_Peak_Detector_Get(struct snd_kcontrol *kcontrol,
2083 struct snd_ctl_elem_value *ucontrol)
2084 {
2085 /*
2086 ucontrol->value.integer.value[0] = (Ana_Get_Reg (SPK_CON12)>>14)&0x01;
2087 */
2088 return 0;
2089 }
2090
2091
2092 static const struct soc_enum Audio_Speaker_Enum[] =
2093 {
2094 // speaker class setting
2095 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(speaker_amp_function), speaker_amp_function),
2096 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(speaker_PGA_function), speaker_PGA_function),
2097 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(speaker_OC_function), speaker_OC_function),
2098 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(speaker_CS_function), speaker_CS_function),
2099 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(speaker_CSPeakDetecReset_function), speaker_CSPeakDetecReset_function),
2100 };
2101
2102 static const struct snd_kcontrol_new mt6331_snd_Speaker_controls[] =
2103 {
2104 SOC_ENUM_EXT("Audio_Speaker_class_Switch", Audio_Speaker_Enum[0], Audio_Speaker_Class_Get, Audio_Speaker_Class_Set),
2105 SOC_ENUM_EXT("Audio_Speaker_PGA_gain", Audio_Speaker_Enum[1], Audio_Speaker_Pga_Gain_Get, Audio_Speaker_Pga_Gain_Set),
2106 SOC_ENUM_EXT("Audio_Speaker_OC_Falg", Audio_Speaker_Enum[2], Audio_Speaker_OcFlag_Get, Audio_Speaker_OcFlag_Set),
2107 SOC_ENUM_EXT("Audio_Speaker_CurrentSensing", Audio_Speaker_Enum[3], Audio_Speaker_Current_Sensing_Get, Audio_Speaker_Current_Sensing_Set),
2108 SOC_ENUM_EXT("Audio_Speaker_CurrentPeakDetector", Audio_Speaker_Enum[4], Audio_Speaker_Current_Sensing_Peak_Detector_Get, Audio_Speaker_Current_Sensing_Peak_Detector_Set),
2109 };
2110
2111 #define HW_BUFFER_LENGTH 21
2112 const uint32 V_Buffer_Table[HW_BUFFER_LENGTH] =
2113 {
2114 MT6332_AUXADC_ADC19,
2115 MT6332_AUXADC_ADC20,
2116 MT6332_AUXADC_ADC21,
2117 MT6332_AUXADC_ADC22,
2118 MT6332_AUXADC_ADC23,
2119 MT6332_AUXADC_ADC24,
2120 MT6332_AUXADC_ADC25,
2121 MT6332_AUXADC_ADC26,
2122 MT6332_AUXADC_ADC27,
2123 MT6332_AUXADC_ADC28,
2124 MT6332_AUXADC_ADC29,
2125 MT6332_AUXADC_ADC30,
2126 MT6332_AUXADC_ADC0,
2127 MT6332_AUXADC_ADC1,
2128 MT6332_AUXADC_ADC2,
2129 MT6332_AUXADC_ADC3,
2130 MT6332_AUXADC_ADC4,
2131 MT6332_AUXADC_ADC5,
2132 MT6332_AUXADC_ADC6,
2133 MT6332_AUXADC_ADC7,
2134 MT6332_AUXADC_ADC8
2135 };
2136
2137 const uint32 I_Buffer_Table[HW_BUFFER_LENGTH] =
2138 {
2139 MT6332_AUXADC_ADC31,
2140 MT6332_AUXADC_ADC32,
2141 MT6332_AUXADC_ADC33,
2142 MT6332_AUXADC_ADC34,
2143 MT6332_AUXADC_ADC35,
2144 MT6332_AUXADC_ADC36,
2145 MT6332_AUXADC_ADC37,
2146 MT6332_AUXADC_ADC38,
2147 MT6332_AUXADC_ADC39,
2148 MT6332_AUXADC_ADC40,
2149 MT6332_AUXADC_ADC41,
2150 MT6332_AUXADC_ADC42,
2151 MT6332_AUXADC_ADC9,
2152 MT6332_AUXADC_ADC10,
2153 MT6332_AUXADC_ADC11,
2154 MT6332_AUXADC_ADC12,
2155 MT6332_AUXADC_ADC13,
2156 MT6332_AUXADC_ADC14,
2157 MT6332_AUXADC_ADC15,
2158 MT6332_AUXADC_ADC16,
2159 MT6332_AUXADC_ADC17
2160 };
2161
2162 int Audio_AuxAdcData_Get_ext(void)
2163 {
2164 const int dRecCount = 1024;
2165 int dRecReadIndex = 0;
2166 int dValidCount = 0;
2167 int dCheckCount = 0;
2168 int cnt1, cnt2, iv_queue, v_cnt, i_cnt, cnt, i, hw_read_idx, iov_flag, iov_cnt;
2169 int dMax, dCurValue;
2170 int output_freq, freq_meter_data;
2171
2172 printk("vibspk auxadc in+\n");
2173
2174 if (mEnableAuxAdc == 0)
2175 {
2176 return 0;
2177 }
2178
2179 if (mEnableAuxAdc == 1)
2180 {
2181 Ana_Set_Reg(0x80be, 0x02, 0x02);
2182 Ana_Set_Reg(0x80c0, 0x02, 0x02);
2183 Ana_Set_Reg(MT6332_AUXADC_CON0, 0x8000, 0x8000);
2184 Ana_Set_Reg(0x8094, 0, 0xFFFF);
2185 Ana_Set_Reg(0x809a, 0x6023, 0xFFFF);
2186 Ana_Set_Reg(0x80a0, 0x004a, 0xFFFF);
2187 Ana_Set_Reg(0x80b2, 0x01ff, 0xFFFF);
2188 Ana_Set_Reg(0x80c2, 0x0005, 0xFFFF);
2189 //Ana_Set_Reg(0x886a, 0x00b0, 0xFFFF); // Important
2190 }
2191
2192 #if 1
2193 if (mEnableAuxAdc == 1)
2194 {
2195 Ana_Set_Reg(0x0680, 0x0000, 0xFFFF);
2196 Ana_Set_Reg(0x015A, 0x0001, 0xFFFF);
2197 Ana_Set_Reg(0x015C, 0x0003, 0xFFFF);
2198 Ana_Set_Reg(0x013C, 0x3000, 0xFFFF);
2199 Ana_Set_Reg(0x809A, 0x6025, 0xFFFF);
2200 Ana_Set_Reg(0x8552, 0x0004, 0xFFFF);
2201 Ana_Set_Reg(0x853E, 0x0021, 0xFFFF);
2202 Ana_Set_Reg(0x8534, 0x0300, 0xFFFF);
2203 Ana_Set_Reg(0x853A, 0x0000, 0xFFFF);
2204 Ana_Set_Reg(0x8542, 0x8542, 0xFFFF);
2205 Ana_Set_Reg(0x8094, 0x0000, 0xFFFF);
2206 Ana_Set_Reg(0x809E, 0x0004, 0xFFFF);
2207 while ((Ana_Get_Reg(0x809A) & 0x4) != 0)
2208 {
2209 printk("WAITING clock\n");
2210 }
2211
2212 Ana_Set_Reg(0x809A, 0x6023, 0xFFFF); //0x6027
2213 //TOP_CKSEL_CON0[1] = 1?b1swtich to SMPS_CK, 1'b0 switch to 32KHz
2214 Ana_Set_Reg(0x80A6, 0x0100, 0xFFFF);
2215 Ana_Set_Reg(0x80BC, 0x0040, 0xFFFF);
2216 Ana_Set_Reg(0x80BC, 0x0000, 0xFFFF);
2217 //FQMTR_CON1[15:0] = Frequency meter window setting (= numbers of auxadc_12M_CK cycles)
2218 Ana_Set_Reg(0x8CD0, 175, 0xFFFF); // setting window value = 175
2219 // FQMTR_CON0[2:0]=1 ,select meter clock = 12M
2220 // FQMTR_CON0[15]=1 enable fqmtr
2221 Ana_Set_Reg(0x8CCE, 0x8000, 0xFFFF); //0 :turn on FQMTR
2222 msleep(2);
2223 while ((Ana_Get_Reg(0x8CCE) & 0x8) != 0)
2224 {
2225 printk("WAITING FQMTR_CON0[3]\n");
2226 //Do nothing;
2227 }
2228 //delay 1ms ，ensure Busy =1
2229 // FQMTR_CON0[3] =1?b0 ,wait FQMTR busy bit become to 0
2230 //Use 32KHz to meter variable 12MHz
2231 freq_meter_data = Ana_Get_Reg(0x8CD2); // check if [3] becomes to 0
2232 //read FQMTR data
2233 output_freq = (32768 * freq_meter_data) / (175);
2234 //output_freq = (32000*freq_meter_data)/(366*33);
2235 //output_freq = (12000000*freq_meter_data)/64;
2236 printk("freq_meter_data %d %d\n", freq_meter_data, output_freq);
2237 output_freq = output_freq / 96000;
2238 printk("freq divider %d\n", output_freq);
2239 }
2240 #endif
2241 dMax = dCurValue = 0;
2242 hw_read_idx = 0;
2243 if (mEnableAuxAdc == 1)
2244 {
2245 Ana_Set_Reg(MT6332_AUXADC_CON13, 20, 0x01FF); //[0:8]: period
2246 Ana_Set_Reg(MT6332_AUXADC_CON12, 21, 0x007F); //Set Buffer Length
2247 }
2248 Ana_Set_Reg(MT6332_AUXADC_CON12, 0x0040, 0x0040);
2249 Ana_Set_Reg(MT6332_AUXADC_CON12, 0x0080, 0x0080);
2250 Ana_Set_Reg(MT6332_AUXADC_CON12, 0x0100, 0x0100);
2251 msleep(1);
2252 Ana_Set_Reg(MT6332_AUXADC_CON12, 0, 0x0040);
2253 Ana_Set_Reg(MT6332_AUXADC_CON12, 0, 0x0080);
2254 Ana_Set_Reg(MT6332_AUXADC_CON12, 0, 0x0100);
2255 if (mEnableAuxAdc == 1)
2256 {
2257 Ana_Set_Reg(MT6332_AUXADC_CON12, 21, 0x007F); //Set Buffer Length
2258 Ana_Set_Reg(MT6332_AUXADC_CON36, 0xAB, 0x01FF); //Set Channel 10 & 11 for V and I
2259 Ana_Set_Reg(MT6332_AUXADC_CON12, 0x8000, 0x8000); //[15]Set Speaker mode
2260 }
2261
2262 // Ana_Set_Reg(MT6332_AUXADC_CON33, 0, 0xFFFF);
2263
2264 // printk("hochi CON13 [%x] CON12 [%x]\n", Ana_Get_Reg(MT6332_AUXADC_CON13), Ana_Get_Reg(MT6332_AUXADC_CON12));
2265 Ana_Set_Reg(MT6332_AUXADC_CON13, 0x0200, 0x0200); //[9]: enable
2266
2267 // printk("hochi while+ [%x]\n", Ana_Get_Reg(MT6332_AUXADC_CON33));
2268
2269 do
2270 {
2271 iv_queue = Ana_Get_Reg(MT6332_AUXADC_CON33);
2272 v_cnt = (iv_queue >> 8) & 0x3F;
2273 i_cnt = iv_queue & 0x3F;
2274 //ov_flag = iv_queue & 0x8000;
2275 // printk("hochi o [%d] v [%d] i [%d] t [%d]\n",ov_flag,v_cnt,i_cnt,dRecReadIndex);
2276 /*
2277 if (ov_flag != 0)
2278 {
2279 printk("hochi %s overflow \n", __func__);
2280 printk("hochi ov MT6332_AUXADC_CON33 [%x]\n", iv_queue);
2281 break;
2282 }
2283 else
2284 */
2285 {
2286 dCheckCount++;
2287 }
2288 //printk("o [%d] v [%d] i [%d]",ov_flag,v_cnt,i_cnt);
2289
2290 if (/*(v_cnt > 0) ||*/ (i_cnt > 0))
2291 {
2292 dValidCount++;
2293 /*
2294 if (v_cnt > i_cnt)
2295 {
2296 cnt = i_cnt;
2297 }
2298 else
2299 {
2300 cnt = v_cnt;
2301 }
2302 */
2303 if (i_cnt > HW_BUFFER_LENGTH)
2304 {
2305 iov_cnt = i_cnt;
2306 iov_flag = 1;
2307 i_cnt = HW_BUFFER_LENGTH;
2308 }
2309 else
2310 {
2311 iov_flag = 0;
2312 }
2313
2314 cnt = i_cnt;
2315 if (cnt + hw_read_idx >= HW_BUFFER_LENGTH)
2316 {
2317 cnt1 = HW_BUFFER_LENGTH - hw_read_idx;
2318 cnt2 = cnt - cnt1;
2319 }
2320 else
2321 {
2322 cnt1 = cnt;
2323 cnt2 = 0;
2324 }
2325
2326 for (i = 0; i < cnt1; i++)
2327 {
2328 int /*v_tmp, */i_tmp;
2329
2330 i_tmp = Ana_Get_Reg(I_Buffer_Table[hw_read_idx]);
2331 //v_tmp = Ana_Get_Reg(V_Buffer_Table[hw_read_idx]);
2332 /*
2333 if( hw_read_idx == 19)
2334 {
2335 bufferBase[ring_write_idx++] = ((v_tmp >> 3) & 0xFFF); //LSB 15 bits
2336 }
2337 else
2338 {
2339 bufferBase[ring_write_idx++] = (v_tmp & 0xFFF); //LSB 12 bits
2340 }
2341 */
2342 if (hw_read_idx == 17 || hw_read_idx == 18 || hw_read_idx == 19)
2343 {
2344 dCurValue = ((i_tmp >> 3) & 0xFFF); //LSB 15 bits
2345 }
2346 else
2347 {
2348 dCurValue = (i_tmp & 0xFFF); //LSB 12 bits
2349 }
2350
2351 // if (/*(v_tmp & 0x8000) == 0 || */(i_tmp & 0x8000) == 0)
2352 // {
2353 //must_print("AUXADC_CON33=0x%x at %d\n\n", iv_queue, hw_read_idx);
2354 //must_print("v_tmp=0x%x i_tmp= 0x%x, hw_read_idx %d, V_Addr 0x%x, I_Addr 0x%x\n\n", v_tmp, i_tmp, hw_read_idx, I_Buffer_Table[hw_read_idx], V_Buffer_Table[hw_read_idx]);
2355 // }
2356 if (dCurValue > dMax)
2357 {
2358 dMax = dCurValue;
2359 }
2360 hw_read_idx++;
2361
2362 if (hw_read_idx >= HW_BUFFER_LENGTH)
2363 {
2364 hw_read_idx = 0;
2365 }
2366 }
2367
2368 //If warp to head, do second round
2369 for (i = 0; i < cnt2; i++)
2370 {
2371 int /*v_tmp, */i_tmp;
2372
2373 i_tmp = Ana_Get_Reg(I_Buffer_Table[hw_read_idx]);
2374 //v_tmp = Ana_Get_Reg(V_Buffer_Table[hw_read_idx]);
2375 /*
2376 if( hw_read_idx == 19)
2377 {
2378 bufferBase[ring_write_idx++] = ((v_tmp >> 3)& 0xFFF); //LSB 15 bits
2379 }
2380 else
2381 {
2382 bufferBase[ring_write_idx++] = (v_tmp & 0xFFF); //LSB 12 bits
2383 }
2384 */
2385 if (hw_read_idx == 17 || hw_read_idx == 18 || hw_read_idx == 19)
2386 {
2387 dCurValue = ((i_tmp >> 3) & 0xFFF); //LSB 15 bits
2388 }
2389 else
2390 {
2391 dCurValue = (i_tmp & 0xFFF); //LSB 12 bits
2392 }
2393 /*
2394 if ((v_tmp & 0x8000) == 0 || (i_tmp & 0x8000) == 0)
2395 {
2396 printk("hochi AUXADC_CON33=0x%x at %d\n\n", iv_queue, hw_read_idx);
2397 printk("hochi v_tmp=0x%x i_tmp= 0x%x, hw_read_idx %d, V_Addr 0x%x, I_Addr 0x%x\n\n", v_tmp, i_tmp, hw_read_idx, I_Buffer_Table[hw_read_idx], V_Buffer_Table[hw_read_idx]);
2398 }
2399 */
2400 if (dCurValue > dMax)
2401 {
2402 dMax = dCurValue;
2403 }
2404 hw_read_idx++;
2405 if (hw_read_idx >= HW_BUFFER_LENGTH)
2406 {
2407 hw_read_idx = 0;
2408 }
2409 }
2410
2411 dRecReadIndex += cnt;
2412
2413 if (iov_flag)
2414 {
2415 Ana_Set_Reg(MT6332_AUXADC_CON12, 0x0080, 0x0080);
2416 printk("vibspk auxadc skip io [%d] i [%d]\n", iov_flag, iov_cnt);
2417 Ana_Set_Reg(MT6332_AUXADC_CON12, 0, 0x0080);
2418 }
2419 }
2420
2421
2422 }
2423 while (dRecCount > dRecReadIndex/* && dValidCount > 0*/);
2424
2425 // if (ov_flag)
2426 // printk("hochi : overflow dRecReadIndex [%d] dValidCount [%d] dCheckCount [%d]\n",dRecReadIndex,dValidCount,dCheckCount);
2427 // else
2428 printk("vibspk auxadc- : dMax = %d dRecReadIndex [%d] dValidCount [%d] dCheckCount [%d]\n", dMax, dRecReadIndex, dValidCount, dCheckCount);
2429 #if 0//0519
2430 Ana_Set_Reg(0x80be, 0x02, 0x02);
2431 Ana_Set_Reg(0x80c0, 0x02, 0x02);
2432
2433 Ana_Set_Reg(MT6332_AUXADC_CON12, 0, 0x8000); //[15]Set Speaker mode
2434 Ana_Set_Reg(MT6332_AUXADC_CON13, 0, 0x0200); //[9]: enable
2435 Ana_Set_Reg(MT6332_AUXADC_CON0, 0x0000, 0x8000);
2436 #endif
2437 Ana_Set_Reg(MT6332_AUXADC_CON13, 0, 0x0200); //[9]: enable
2438 mEnableAuxAdc = 2;
2439 printk("vibspk auxadc-\n");
2440 return dMax;
2441 }
2442
2443
2444 #endif
2445 //int PMIC_IMM_GetOneChannelValue(int dwChannel, int deCount, int trimd);
2446
2447 static int Audio_AuxAdcData_Get(struct snd_kcontrol *kcontrol,
2448 struct snd_ctl_elem_value *ucontrol)
2449 {
2450 #ifdef CONFIG_MTK_SPEAKER
2451 ucontrol->value.integer.value[0] = Audio_AuxAdcData_Get_ext();//PMIC_IMM_GetSPK_THR_IOneChannelValue(0x001B, 1, 0);
2452 #else
2453 ucontrol->value.integer.value[0] = 0;
2454 #endif
2455 return 0;
2456 }
2457
2458 static int Audio_AuxAdcData_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2459 {
2460 dAuxAdcChannel = ucontrol->value.integer.value[0];
2461 printk("%s dAuxAdcChannel = 0x%x \n", __func__, dAuxAdcChannel);
2462 return 0;
2463 }
2464
2465
2466 static const struct snd_kcontrol_new Audio_snd_auxadc_controls[] =
2467 {
2468 SOC_SINGLE_EXT("Audio AUXADC Data", SND_SOC_NOPM, 0, 0x80000, 0, Audio_AuxAdcData_Get, Audio_AuxAdcData_Set),
2469 };
2470
2471
2472 static const char *amp_function[] = {"Off", "On"};
2473 static const char *aud_clk_buf_function[] = {"Off", "On"};
2474
2475 //static const char *DAC_SampleRate_function[] = {"8000", "11025", "16000", "24000", "32000", "44100", "48000"};
2476 static const char *DAC_DL_PGA_Headset_GAIN[] = {"8Db", "7Db", "6Db", "5Db", "4Db", "3Db", "2Db", "1Db", "0Db", "-1Db", "-2Db", "-3Db",
2477 "-4Db", "-5Db", "-6Db", "-7Db", "-8Db", "-9Db", "-10Db" , "-40Db"
2478 };
2479 static const char *DAC_DL_PGA_Handset_GAIN[] = {"8Db", "7Db", "6Db", "5Db", "4Db", "3Db", "2Db", "1Db", "0Db", "-1Db", "-2Db", "-3Db",
2480 "-4Db", "-5Db", "-6Db", "-7Db", "-8Db", "-9Db", "-10Db" , "-40Db"
2481 };
2482
2483 static const char *DAC_DL_PGA_Speaker_GAIN[] = {"8Db", "7Db", "6Db", "5Db", "4Db", "3Db", "2Db", "1Db", "0Db", "-1Db", "-2Db", "-3Db",
2484 "-4Db", "-5Db", "-6Db", "-7Db", "-8Db", "-9Db", "-10Db" , "-40Db"
2485 };
2486
2487 //static const char *Voice_Mux_function[] = {"Voice", "Speaker"};
2488
2489 static int Lineout_PGAL_Get(struct snd_kcontrol *kcontrol,
2490 struct snd_ctl_elem_value *ucontrol)
2491 {
2492 printk("Speaker_PGA_Get = %d\n", mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_SPKL]);
2493 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_SPKL];
2494 return 0;
2495 }
2496
2497 static int Lineout_PGAL_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2498 {
2499 int index = 0;
2500 printk("%s(), index = %d\n", __func__, ucontrol->value.enumerated.item[0]);
2501
2502 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(DAC_DL_PGA_Speaker_GAIN))
2503 {
2504 printk("return -EINVAL\n");
2505 return -EINVAL;
2506 }
2507 index = ucontrol->value.integer.value[0];
2508 if (ucontrol->value.enumerated.item[0] == (ARRAY_SIZE(DAC_DL_PGA_Speaker_GAIN) - 1))
2509 {
2510 index = 0x1f;
2511 }
2512 Ana_Set_Reg(ZCD_CON1, index , 0x001f);
2513 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_SPKL] = ucontrol->value.integer.value[0];
2514 return 0;
2515 }
2516
2517 static int Lineout_PGAR_Get(struct snd_kcontrol *kcontrol,
2518 struct snd_ctl_elem_value *ucontrol)
2519 {
2520 printk("%s = %d\n", __func__, mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_SPKR]);
2521 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_SPKR];
2522 return 0;
2523 }
2524
2525 static int Lineout_PGAR_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2526 {
2527 // struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2528 int index = 0;
2529 printk("%s(), index = %d\n", __func__, ucontrol->value.enumerated.item[0]);
2530
2531 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(DAC_DL_PGA_Speaker_GAIN))
2532 {
2533 printk("return -EINVAL\n");
2534 return -EINVAL;
2535 }
2536 index = ucontrol->value.integer.value[0];
2537 if (ucontrol->value.enumerated.item[0] == (ARRAY_SIZE(DAC_DL_PGA_Speaker_GAIN) - 1))
2538 {
2539 index = 0x1f;
2540 }
2541 Ana_Set_Reg(ZCD_CON1, index << 7 , 0x0f10);
2542 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_SPKR] = ucontrol->value.integer.value[0];
2543 return 0;
2544 }
2545
2546 static int Handset_PGA_Get(struct snd_kcontrol *kcontrol,
2547 struct snd_ctl_elem_value *ucontrol)
2548 {
2549 printk("Handset_PGA_Get = %d\n", mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HSOUTL]);
2550 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HSOUTL];
2551 return 0;
2552 }
2553
2554 static int Handset_PGA_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2555 {
2556 // struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2557 int index = 0;
2558
2559 printk("%s(), index = %d\n", __func__, ucontrol->value.enumerated.item[0]);
2560
2561 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(DAC_DL_PGA_Handset_GAIN))
2562 {
2563 printk("return -EINVAL\n");
2564 return -EINVAL;
2565 }
2566 index = ucontrol->value.integer.value[0];
2567 if (ucontrol->value.enumerated.item[0] == (ARRAY_SIZE(DAC_DL_PGA_Handset_GAIN) - 1))
2568 {
2569 index = 0x1f;
2570 }
2571 Ana_Set_Reg(ZCD_CON3, index , 0x001f);
2572 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HSOUTL] = ucontrol->value.integer.value[0];
2573 return 0;
2574 }
2575
2576
2577 static void HeadsetLVolumeSet(void)
2578 {
2579 int index = 0;
2580 printk("%s\n", __func__);
2581 index = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTL];
2582 Ana_Set_Reg(ZCD_CON2, index , 0x001f);
2583 }
2584
2585 static int Headset_PGAL_Get(struct snd_kcontrol *kcontrol,
2586 struct snd_ctl_elem_value *ucontrol)
2587 {
2588 printk("Headset_PGAL_Get = %d\n", mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTL]);
2589 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTL];
2590 return 0;
2591 }
2592
2593 static int Headset_PGAL_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2594 {
2595 // struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2596 int index = 0;
2597 int offset = 0 , step = 0;
2598
2599 //printk("%s(), index = %d arraysize = %lu \n", __func__, ucontrol->value.enumerated.item[0], ARRAY_SIZE(DAC_DL_PGA_Headset_GAIN));
2600
2601 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(DAC_DL_PGA_Headset_GAIN))
2602 {
2603 printk("return -EINVAL\n");
2604 return -EINVAL;
2605 }
2606 index = ucontrol->value.integer.value[0];
2607 if (ucontrol->value.enumerated.item[0] == (ARRAY_SIZE(DAC_DL_PGA_Headset_GAIN) - 1))
2608 {
2609 index = 0x1f;
2610 }
2611 offset = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTL] - ucontrol->value.integer.value[0];
2612
2613 if (offset > 0)
2614 {
2615 step = -1;
2616 }
2617 else if (offset == 0)
2618 {
2619 printk("return for gain is the same");
2620 return 0;
2621 }
2622 else
2623 {
2624 step = 1;
2625 }
2626 //remove while due to headset gain update too late for user experience, trade off: headset pop hw limitation
2627 #if 0
2628 while (offset != 0)
2629 {
2630 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTL] += step;
2631 Ana_Set_Reg(ZCD_CON2, (mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTL]), 0x001f);
2632 msleep(1);
2633 offset += step;
2634 }
2635 #endif
2636 msleep(1);
2637 Ana_Set_Reg(ZCD_CON2, index , 0x001f);
2638 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTL] = ucontrol->value.integer.value[0];
2639 return 0;
2640 }
2641
2642 static void HeadsetRVolumeSet(void)
2643 {
2644 int index = 0;
2645 printk("%s\n", __func__);
2646 index = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR];
2647 Ana_Set_Reg(ZCD_CON2, index << 7, 0x0f80);
2648 }
2649
2650 static int Headset_PGAR_Get(struct snd_kcontrol *kcontrol,
2651 struct snd_ctl_elem_value *ucontrol)
2652 {
2653 printk("Headset_PGAR_Get = %d\n", mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR]);
2654 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR];
2655 return 0;
2656 }
2657
2658 static int Headset_PGAR_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2659 {
2660 // struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2661 int index = 0;
2662 int offset = 0 , step = 0;
2663
2664 printk("%s(), index = %d\n", __func__, ucontrol->value.enumerated.item[0]);
2665
2666 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(DAC_DL_PGA_Headset_GAIN))
2667 {
2668 printk("return -EINVAL\n");
2669 return -EINVAL;
2670 }
2671 index = ucontrol->value.integer.value[0];
2672 if (ucontrol->value.enumerated.item[0] == (ARRAY_SIZE(DAC_DL_PGA_Headset_GAIN) - 1))
2673 {
2674 index = 0x1f;
2675 }
2676
2677 offset = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR] - ucontrol->value.integer.value[0];
2678 if (offset > 0)
2679 {
2680 step = -1;
2681 }
2682 else if (offset == 0)
2683 {
2684 printk("return for gain is the same");
2685 return 0;
2686 }
2687 else
2688 {
2689 step = 1;
2690 }
2691 //remove while due to headset gain update too late for user experience, trade off: headset pop hw limitation
2692 #if 0
2693 while (offset != 0)
2694 {
2695 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR] += step;
2696 Ana_Set_Reg(ZCD_CON2, (mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR]) << 7, 0x0f80);
2697 msleep(1);
2698 offset += step;
2699 }
2700 #endif
2701 msleep(1);
2702 Ana_Set_Reg(ZCD_CON2, index << 7, 0x0f80);
2703 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR] = ucontrol->value.integer.value[0];
2704 return 0;
2705 }
2706
2707
2708 /*static int Voice_Mux_Get(struct snd_kcontrol *kcontrol,
2709 struct snd_ctl_elem_value *ucontrol)
2710 {
2711 printk("Voice_Mux_Get = %d\n", mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_VOICE]);
2712 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_VOICE];
2713 return 0;
2714 }
2715
2716 static int Voice_Mux_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2717 {
2718
2719 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2720 printk("%s()\n", __func__);
2721 if (ucontrol->value.integer.value[0])
2722 {
2723 printk("%s()\n", __func__);
2724 snd_soc_dapm_disable_pin(&codec->dapm, "SPEAKER");
2725 snd_soc_dapm_disable_pin(&codec->dapm, "RX_BIAS");
2726 snd_soc_dapm_sync(&codec->dapm);
2727 }
2728 else
2729 {
2730 printk("%s()\n", __func__);
2731 snd_soc_dapm_enable_pin(&codec->dapm, "SPEAKER");
2732 snd_soc_dapm_enable_pin(&codec->dapm, "RX_BIAS");
2733 snd_soc_dapm_sync(&codec->dapm);
2734 }
2735
2736 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_VOICE] = ucontrol->value.integer.value[0];
2737 return 0;
2738 }*/
2739
2740 static uint32 mHp_Impedance = 32;
2741
2742 static int Audio_Hp_Impedance_Get(struct snd_kcontrol *kcontrol,
2743 struct snd_ctl_elem_value *ucontrol)
2744 {
2745 printk("Audio_Hp_Impedance_Get = %d\n", mHp_Impedance);
2746 ucontrol->value.integer.value[0] = mHp_Impedance;
2747 return 0;
2748
2749 }
2750
2751 static int Audio_Hp_Impedance_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2752 {
2753 mHp_Impedance = ucontrol->value.integer.value[0];
2754 printk("%s Audio_Hp_Impedance_Set = 0x%x \n", __func__, mHp_Impedance);
2755 return 0;
2756 }
2757
2758 static int Aud_Clk_Buf_Get(struct snd_kcontrol *kcontrol,
2759 struct snd_ctl_elem_value *ucontrol)
2760 {
2761 printk("\%s n", __func__);
2762 ucontrol->value.integer.value[0] = audck_buf_Count;
2763 return 0;
2764 }
2765
2766 static int Aud_Clk_Buf_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2767 {
2768 //int index = 0;
2769 printk("%s(), value = %d\n", __func__, ucontrol->value.enumerated.item[0]);
2770 if (ucontrol->value.integer.value[0])
2771 {
2772 audckbufEnable(true);
2773 }
2774 else
2775 {
2776 audckbufEnable(false);
2777 }
2778 return 0;
2779 }
2780
2781
2782 static const struct soc_enum Audio_DL_Enum[] =
2783 {
2784 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(amp_function), amp_function),
2785 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(amp_function), amp_function),
2786 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(amp_function), amp_function),
2787 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(amp_function), amp_function),
2788 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(amp_function), amp_function),
2789 // here comes pga gain setting
2790 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(DAC_DL_PGA_Headset_GAIN), DAC_DL_PGA_Headset_GAIN),
2791 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(DAC_DL_PGA_Headset_GAIN), DAC_DL_PGA_Headset_GAIN),
2792 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(DAC_DL_PGA_Handset_GAIN), DAC_DL_PGA_Handset_GAIN),
2793 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(DAC_DL_PGA_Speaker_GAIN), DAC_DL_PGA_Speaker_GAIN),
2794 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(DAC_DL_PGA_Speaker_GAIN), DAC_DL_PGA_Speaker_GAIN),
2795 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(aud_clk_buf_function), aud_clk_buf_function),
2796 };
2797
2798 static const struct snd_kcontrol_new mt6331_snd_controls[] =
2799 {
2800 SOC_ENUM_EXT("Audio_Amp_R_Switch", Audio_DL_Enum[0], Audio_AmpR_Get, Audio_AmpR_Set),
2801 SOC_ENUM_EXT("Audio_Amp_L_Switch", Audio_DL_Enum[1], Audio_AmpL_Get, Audio_AmpL_Set),
2802 SOC_ENUM_EXT("Voice_Amp_Switch", Audio_DL_Enum[2], Voice_Amp_Get, Voice_Amp_Set),
2803 SOC_ENUM_EXT("Speaker_Amp_Switch", Audio_DL_Enum[3], Speaker_Amp_Get, Speaker_Amp_Set),
2804 SOC_ENUM_EXT("Headset_Speaker_Amp_Switch", Audio_DL_Enum[4], Headset_Speaker_Amp_Get, Headset_Speaker_Amp_Set),
2805 SOC_ENUM_EXT("Headset_PGAL_GAIN", Audio_DL_Enum[5], Headset_PGAL_Get, Headset_PGAL_Set),
2806 SOC_ENUM_EXT("Headset_PGAR_GAIN", Audio_DL_Enum[6], Headset_PGAR_Get, Headset_PGAR_Set),
2807 SOC_ENUM_EXT("Handset_PGA_GAIN", Audio_DL_Enum[7], Handset_PGA_Get, Handset_PGA_Set),
2808 SOC_ENUM_EXT("Lineout_PGAR_GAIN", Audio_DL_Enum[8], Lineout_PGAR_Get, Lineout_PGAR_Set),
2809 SOC_ENUM_EXT("Lineout_PGAL_GAIN", Audio_DL_Enum[9], Lineout_PGAL_Get, Lineout_PGAL_Set),
2810 SOC_ENUM_EXT("AUD_CLK_BUF_Switch", Audio_DL_Enum[10], Aud_Clk_Buf_Get, Aud_Clk_Buf_Set),
2811 SOC_SINGLE_EXT("Audio HP Impedance", SND_SOC_NOPM, 0, 512, 0, Audio_Hp_Impedance_Get, Audio_Hp_Impedance_Set),
2812 };
2813
2814 static const struct snd_kcontrol_new mt6331_Voice_Switch[] =
2815 {
2816 //SOC_DAPM_ENUM_EXT("Voice Mux", Audio_DL_Enum[10], Voice_Mux_Get, Voice_Mux_Set),
2817 };
2818
2819 void SetMicPGAGain(void)
2820 {
2821 int index = 0;
2822 index = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP1];
2823 Ana_Set_Reg(AUDPREAMPGAIN_CFG0, index , 0x0007);
2824 index = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP2];
2825 Ana_Set_Reg(AUDPREAMPGAIN_CFG0, index << 4, 0x0070);
2826 index = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP3];
2827 Ana_Set_Reg(AUDPREAMPGAIN_CFG0, index << 8, 0x0700);
2828 index = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP4];
2829 Ana_Set_Reg(AUDPREAMPGAIN_CFG0, index << 12, 0x7000);
2830 }
2831
2832 static bool GetAdcStatus(void)
2833 {
2834 int i = 0;
2835 for (i = AUDIO_ANALOG_DEVICE_IN_ADC1 ; i < AUDIO_ANALOG_DEVICE_MAX ; i++)
2836 {
2837 if (mCodec_data->mAudio_Ana_DevicePower[i] == true)
2838 {
2839 return true;
2840 }
2841 }
2842 return false;
2843 }
2844
2845 static bool GetDacStatus(void)
2846 {
2847 int i = 0;
2848 for (i = AUDIO_ANALOG_DEVICE_OUT_EARPIECER ; i < AUDIO_ANALOG_DEVICE_2IN1_SPK ; i++)
2849 {
2850 if (mCodec_data->mAudio_Ana_DevicePower[i] == true)
2851 {
2852 return true;
2853 }
2854 }
2855 return false;
2856 }
2857
2858
2859 static bool TurnOnADcPowerACC(int ADCType, bool enable)
2860 {
2861 printk("%s ADCType = %d enable = %d \n", __func__, ADCType, enable);
2862 if (enable)
2863 {
2864 //uint32 ULIndex = GetULFrequency(mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC]);
2865 uint32 SampleRate_VUL1 = mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC];
2866 uint32 SampleRate_VUL2 = mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC_2];
2867 if (GetAdcStatus() == false)
2868 {
2869 audckbufEnable(true);
2870 if (mAdc_Power_Mode == true)
2871 {
2872 Ana_Set_Reg(AUDBUF_CFG4, 0x0001, 0x0001); // Set AVDD32_AUD lowpower mode
2873 }
2874 else
2875 {
2876 Ana_Set_Reg(AUDBUF_CFG4, 0x0000, 0x0001); // Set AVDD32_AUD lowpower mode
2877 }
2878 NvregEnable(true);
2879 ClsqAuxEnable(true);
2880 ClsqEnable(true);
2881 if (mAdc_Power_Mode == true)
2882 {
2883 Ana_Set_Reg(AUDADC_CFG0, 0x4400, 0xffff); // Enable ADC CLK
2884 }
2885 else
2886 {
2887 Ana_Set_Reg(AUDADC_CFG0, 0x0400, 0xffff); // Enable ADC CLK
2888 }
2889 SetDCcoupleNP(AUDIO_ANALOG_DEVICE_IN_ADC1, mAudio_Analog_Mic1_mode);
2890 SetDCcoupleNP(AUDIO_ANALOG_DEVICE_IN_ADC2, mAudio_Analog_Mic2_mode);
2891
2892 //OpenMicbias1();
2893 //OpenMicbias0();
2894 if (mAdc_Power_Mode == false)
2895 {
2896 SetMicbias1lowpower(false);
2897 SetMicbias0lowpower(false);
2898 }
2899 else
2900 {
2901 SetMicbias1lowpower(true);
2902 SetMicbias0lowpower(true);
2903 }
2904
2905 //Ana_Set_Reg(AUDMICBIAS_CFG1, 0x78F, 0xffff); //Enable MICBIAS0,1 (2.7V)
2906 SetMicVref2(0x2);// 1.9V
2907 SetMicVref3(0x2); // 1.9V
2908 SetMic2DCcoupleSwitch(false);
2909 SetMic3DCcoupleSwitch(false);
2910 if (mAdc_Power_Mode == false)
2911 {
2912 SetMic2powermode(false);
2913 SetMic3powermode(false);
2914 }
2915 else
2916 {
2917 SetMic2powermode(true);
2918 SetMic3powermode(true);
2919 }
2920 //OpenMicbias3(true);
2921 //OpenMicbias2(true);
2922 if (mAdc_Power_Mode == false)
2923 {
2924 Ana_Set_Reg(AUDLDO_NVREG_CFG1, 0x0007, 0xffff); //Enable LCLDO18_ENC (1.8V), Remote-Sense
2925 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0000, 0x8888); //Enable LCLDO19_ADCCH0_1, Remote-Sense
2926 }
2927 else
2928 {
2929 Ana_Set_Reg(AUDLDO_NVREG_CFG1, 0x000f, 0xffff); //Enable LCLDO18_ENC (1.8V), Remote-Sense
2930 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x8888, 0x8888); //Enable LCLDO19_ADCCH0_1, Remote-Sense
2931 }
2932 //Ana_Set_Reg(AUDPREAMPGAIN_CFG0, 0x3333, 0xffff); //Set PGA CH0_1 gain = 18dB
2933 SetMicPGAGain();
2934 //Ana_Set_Reg(AUDPREAMP_CFG0, 0x0051, 0x001f); //Enable PGA CH0_1 (CH0 in)
2935 //Ana_Set_Reg(AUDPREAMP_CFG1, 0x16d5, 0xffff); //Enable ADC CH0_1 (PGA in)
2936
2937 //here to set digital part
2938 Topck_Enable(true);
2939 AdcClockEnable(true);
2940 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0x0000, 0xffff); //power on ADC clk
2941 if ((GetDacStatus() == false))
2942 {
2943 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x005a, 0xffff); //power on clock
2944 }
2945 else
2946 {
2947 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0000, 0xffff); //power on clock
2948 }
2949 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0x0000, 0xffff); //power on ADC clk
2950 Ana_Set_Reg(PMIC_AFE_TOP_CON0, 0x0000, 0xffff); //configure ADC setting
2951
2952 Ana_Set_Reg(AFE_MIC_ARRAY_CFG, 0x44e4, 0xffff); //AFE_MIC_ARRAY_CFG
2953 Ana_Set_Reg(AFE_UL_DL_CON0, 0x0001, 0xffff); //turn on afe
2954
2955 Ana_Set_Reg(AFE_PMIC_NEWIF_CFG2, 0x302F | (GetULNewIFFrequency(mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC]) << 10), 0xffff); // config UL up8x_rxif adc voice mode
2956 Ana_Set_Reg(AFE_UL_SRC0_CON0_H, (ULSampleRateTransform(SampleRate_VUL1) << 3 | ULSampleRateTransform(SampleRate_VUL1) << 1) , 0x001f);// ULsampling rate
2957 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_H, (ULSampleRateTransform(SampleRate_VUL2) << 3 | ULSampleRateTransform(SampleRate_VUL2) << 1) , 0x001f); // ULsampling rate
2958 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_L, 0x0041, 0xffff);
2959
2960 Ana_Set_Reg(AFE_UL_SRC0_CON0_L, 0x0041, 0xffff); //power on uplink
2961 }
2962
2963 // open ADC indivisaully
2964 EnableMicBias(ADCType, enable);
2965 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1)
2966 {
2967 if (mAdc_Power_Mode == false)
2968 {
2969 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0007, 0x000f); //Enable LCLDO19_ADCCH0_1, Remote-SENSEINFOBYTES
2970 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0070, 0x00f0); //Enable LCLDO19_ADCCH2, Remote-Sensen)
2971 }
2972 else
2973 {
2974 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x000f, 0x000f); //Enable LCLDO19_ADCCH0_1, Remote-Sense
2975 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x00f0, 0x00f0); //Enable LCLDO19_ADCCH2, Remote-Sensen)
2976 }
2977 Ana_Set_Reg(AUDPREAMP_CFG0, 0x0051, 0x001f); //Enable PGA CH0_1
2978 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0055, 0x007f); //Enable ADC CH0_1 (PGA in)
2979 AudioPreAmp1_Sel(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_1]);
2980 Audio_ADC1_Set_Input(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC1]);
2981 SetDCcoupleNP(AUDIO_ANALOG_DEVICE_IN_ADC1, mAudio_Analog_Mic1_mode);
2982 }
2983 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2)
2984 {
2985 if (mAdc_Power_Mode == false)
2986 {
2987 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0007, 0x000f); //Enable LCLDO19_ADCCH0_1, Remote-SENSEINFOBYTES
2988 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0070, 0x00f0); //Enable LCLDO19_ADCCH2, Remote-Sensen)
2989 }
2990 else
2991 {
2992 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x000f, 0x000f); //Enable LCLDO19_ADCCH0_1, Remote-Sense
2993 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x00f0, 0x00f0); //Enable LCLDO19_ADCCH2, Remote-Sensen)
2994 }
2995
2996 Ana_Set_Reg(AUDPREAMP_CFG0, 0x0040, 0x03c0); //Enable PGA CH2
2997 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0055, 0x007f); //Enable ADC CH0_1 (PGA in)
2998 Audio_ADC2_Set_Input(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC2]);
2999 SetDCcoupleNP(AUDIO_ANALOG_DEVICE_IN_ADC2, mAudio_Analog_Mic2_mode);
3000
3001 }
3002 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC3)
3003 {
3004 if (mAdc_Power_Mode == false)
3005 {
3006 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0700, 0x0f00); //Enable LCLDO19_ADCCH3, Remote-Sense
3007 }
3008 else
3009 {
3010 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0f00, 0x0f00); //Enable LCLDO19_ADCCH3, Remote-Sense
3011 }
3012 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0280, 0x0380); //Enable ADC CH3 (PGA in)
3013 Ana_Set_Reg(AUDPREAMP_CFG2, 0x0001, 0x000f); //Enable preamp CH3
3014 Audio_ADC3_Set_Input(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC3]);
3015 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_H, (ULSampleRateTransform(SampleRate_VUL2) << 3 | ULSampleRateTransform(SampleRate_VUL2) << 1) , 0x001f); // ULsampling rate
3016 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_L, 0x0041, 0xffff);
3017 }
3018 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC4)
3019 {
3020 if (mAdc_Power_Mode == false)
3021 {
3022 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x7000, 0xf000); //Enable LCLDO19_ADCCH4, Remote-Sense
3023 }
3024 else
3025 {
3026 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0xf000, 0xf000); //Enable LCLDO19_ADCCH4, Remote-Sense
3027 }
3028 Ana_Set_Reg(AUDPREAMP_CFG1, 0x1400, 0x1c00); //Enable ADC CH4 (PGA in)
3029 Ana_Set_Reg(AUDPREAMP_CFG2, 0x0010, 0x00f0); //Enable preamp CH4
3030 Audio_ADC4_Set_Input(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC4]);
3031 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_H, (ULSampleRateTransform(SampleRate_VUL2) << 3 | ULSampleRateTransform(SampleRate_VUL2) << 1) , 0x001f); // ULsampling rate
3032 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_L, 0x0041, 0xffff);
3033 }
3034 else
3035 {
3036 printk("\n");
3037 }
3038 }
3039 else
3040 {
3041 if ((GetAdcStatus() == false))
3042 {
3043 Ana_Set_Reg(AFE_UL_SRC0_CON0_L, 0x0000, 0xffff); //power on uplink
3044 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_L, 0x0000, 0xffff); //power on uplink
3045 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0xa000, 0xffff); //power off
3046
3047 Ana_Set_Reg(AUDPREAMP_CFG0, 0x0000, 0xffff); //Disable ADC CH0_1 (PGA in) Disable ADC CH_2 (PGA in)
3048 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0000, 0xffff); //Disable PGA CH0_1 (CH0 in) Disable PGA CH_2
3049 Ana_Set_Reg(AUDPREAMPGAIN_CFG0, 0x0000, 0xffff); //Set PGA CH0_1 gain = 0dB Set PGA CH_2 gain = 0dB
3050
3051 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x2222, 0xffff); //disable LCLDO19_ADCCH0_1, Remote-Sense
3052 Ana_Set_Reg(AUDLDO_NVREG_CFG1, 0x0002, 0xffff); //disable LCLDO18_ENC (1.8V), Remote-Sense
3053
3054 //Ana_Set_Reg(AUDMICBIAS_CFG1, 0x2020, 0xffff); //power on clock
3055 SetMic2powermode(true);
3056 SetMic3powermode(true);
3057
3058 Ana_Set_Reg(AUDADC_CFG0, 0x0000, 0xffff); //configure ADC setting
3059 ClsqAuxEnable(false);
3060 ClsqEnable(false);
3061 NvregEnable(false);
3062 Topck_Enable(false);
3063 audckbufEnable(false);
3064 if (GetDLStatus() == false)
3065 {
3066 // check for if DL/UL will share same register
3067
3068 }
3069 else
3070 {
3071
3072 }
3073
3074 }
3075 //todo , close analog
3076 EnableMicBias(ADCType, enable);
3077 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1)
3078 {
3079 }
3080 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2)
3081 {
3082 }
3083 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC3)
3084 {
3085 }
3086 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC4)
3087 {
3088 }
3089 }
3090 return true;
3091 }
3092
3093 static bool TurnOnADcPowerDmic(int ADCType, bool enable)
3094 {
3095 printk("%s ADCType = %d enable = %d \n", __func__, ADCType, enable);
3096 if (enable)
3097 {
3098 uint32 ULIndex = GetULFrequency(mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC]);
3099 uint32 SampleRate_VUL1 = mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC];
3100 uint32 SampleRate_VUL2 = mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC_2];
3101 if (GetAdcStatus() == false)
3102 {
3103 audckbufEnable(true);
3104 NvregEnable(true);
3105 ClsqAuxEnable(true);
3106 ClsqEnable(true);
3107 Ana_Set_Reg(AUDDIGMI_CFG0, 0x0041, 0xffff); //Enable DMIC0 (BIAS=10)
3108 Ana_Set_Reg(AUDDIGMI_CFG1, 0x0041, 0xffff); //Enable DMIC1 (BIAS=10)
3109
3110 Ana_Set_Reg(AUDADC_CFG0, 0x0400, 0xffff); // Enable ADC CLK
3111 //Ana_Set_Reg(AUDMICBIAS_CFG0, 0x78F, 0xffff); //Enable MICBIAS0,1 (2.7V)
3112 SetDCcoupleNP(AUDIO_ANALOG_DEVICE_IN_ADC1, AUDIO_ANALOGUL_MODE_DMIC);
3113 SetDCcoupleNP(AUDIO_ANALOG_DEVICE_IN_ADC2, AUDIO_ANALOGUL_MODE_DMIC);
3114 SetMicbias1lowpower(false);
3115 SetMicbias0lowpower(false);
3116
3117 //Ana_Set_Reg(AUDMICBIAS_CFG1, 0x285, 0xffff); //Enable MICBIAS2,3 (2.7V)
3118 SetMicVref2(0x2);// 1.9V
3119 SetMicVref3(0x2); // 1.9V
3120 SetMic2DCcoupleSwitch(false);
3121 SetMic3DCcoupleSwitch(false);
3122 SetMic2powermode(false);
3123 SetMic3powermode(false);
3124
3125
3126 //here to set digital part
3127 Topck_Enable(true);
3128 AdcClockEnable(true);
3129
3130 if ((GetDacStatus() == false))
3131 {
3132 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x005a, 0xffff); //power on clock
3133 }
3134 else
3135 {
3136 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0000, 0xffff); //power on clock
3137 }
3138
3139 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0x0000, 0xffff); //power on ADC clk
3140 Ana_Set_Reg(PMIC_AFE_TOP_CON0, (ULIndex << 7) | (ULIndex << 6), 0xffff); //configure ADC setting
3141 Ana_Set_Reg(AFE_UL_DL_CON0, 0x0001, 0xffff); //turn on afe
3142 Ana_Set_Reg(AFE_UL_SRC0_CON0_H, (ULSampleRateTransform(SampleRate_VUL1) << 3 | ULSampleRateTransform(SampleRate_VUL1) << 1) , 0x001f); // ULsampling rate
3143 Ana_Set_Reg(AFE_UL_SRC0_CON0_H, (1 << 5) | (1 << 6), (1 << 5) | (1 << 6)); // dmic open
3144
3145 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_H, (ULSampleRateTransform(SampleRate_VUL2) << 3 | ULSampleRateTransform(SampleRate_VUL2) << 1) , 0x001f); // ULsampling rate
3146 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_H, (1 << 5) | (1 << 6), (1 << 5) | (1 << 6)); // dmic open
3147 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_L, 0x0043, 0xffff);
3148
3149 Ana_Set_Reg(AFE_UL_SRC0_CON0_L, 0x0003, 0xffff); //power on uplink
3150
3151 }
3152 // todo , open ADC indivisaully
3153 EnableMicBias(ADCType, enable);
3154 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1)
3155 {
3156 }
3157 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2)
3158 {
3159 }
3160 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC3)
3161 {
3162
3163 }
3164 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC4)
3165 {
3166
3167 }
3168 else
3169 {
3170 printk("\n");
3171 }
3172 }
3173 else
3174 {
3175 if (GetAdcStatus() == false)
3176 {
3177
3178 //Ana_Set_Reg(AUDMICBIAS_CFG1, 0x2020, 0xffff); //Enable MICBIAS2,3 (2.7V)
3179 SetMic2powermode(true);
3180 SetMic3powermode(true);
3181 OpenMicbias3(false);
3182 OpenMicbias2(false);
3183 SetMic2powermode(true);
3184 SetMic3powermode(true);
3185 //EnableMicBias(ADCType, enable);
3186
3187 Ana_Set_Reg(AUDDIGMI_CFG0, 0x0040, 0xffff); //Disable DMIC0 (BIAS=10)
3188 Ana_Set_Reg(AUDDIGMI_CFG1, 0x0040, 0xffff); //Disable DMIC1 (BIAS=10)
3189
3190 Ana_Set_Reg(AFE_UL_SRC0_CON0_L, 0x0000, 0xffff); //power on uplink
3191 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_L, 0x0000, 0xffff); //power on uplink
3192 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0xa000, 0xffff); //power off
3193
3194 ClsqAuxEnable(false);
3195 ClsqEnable(false);
3196 NvregEnable(false);
3197 Topck_Enable(false);
3198 if (GetDLStatus() == false)
3199 {
3200 // check for if DL/UL will share same register
3201
3202 }
3203 else
3204 {
3205
3206 }
3207
3208 }
3209 //todo , close analog
3210 EnableMicBias(ADCType, enable);
3211 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1)
3212 {
3213
3214 }
3215 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2)
3216 {
3217
3218 }
3219 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC3)
3220 {
3221
3222 }
3223 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC4)
3224 {
3225
3226 }
3227 }
3228 return true;
3229 }
3230
3231 static bool TurnOnADcPowerDCC(int ADCType, bool enable)
3232 {
3233 printk("%s ADCType = %d enable = %d \n", __func__, ADCType, enable);
3234 if (enable)
3235 {
3236 //uint32 ULIndex = GetULFrequency(mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC]);
3237 uint32 SampleRate_VUL1 = mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC];
3238 uint32 SampleRate_VUL2 = mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC_2];
3239 if (GetAdcStatus() == false)
3240 {
3241 audckbufEnable(true);
3242 if (mAdc_Power_Mode == true)
3243 {
3244 Ana_Set_Reg(AUDBUF_CFG4, 0x0001, 0x0001); // Set AVDD32_AUD lowpower mode
3245 }
3246 else
3247 {
3248 Ana_Set_Reg(AUDBUF_CFG4, 0x0000, 0x0001); // Set AVDD32_AUD lowpower mode
3249 }
3250 NvregEnable(true); //Enable AUDGLB
3251 ClsqAuxEnable(true); //Enable ADC CLK
3252 ClsqEnable(true);
3253
3254 //here to set digital part
3255 Topck_Enable(true);
3256 AdcClockEnable(true);
3257
3258 if (mAdc_Power_Mode == true)
3259 {
3260 Ana_Set_Reg(AUDADC_CFG0, 0x4400, 0xffff); // Enable ADC CLK
3261 }
3262 else
3263 {
3264 Ana_Set_Reg(AUDADC_CFG0, 0x0400, 0xffff); // Enable ADC CLK
3265 }
3266 SetDCcoupleNP(AUDIO_ANALOG_DEVICE_IN_ADC1, mAudio_Analog_Mic1_mode);
3267 SetDCcoupleNP(AUDIO_ANALOG_DEVICE_IN_ADC2, mAudio_Analog_Mic2_mode);
3268 //OpenMicbias1();
3269 //OpenMicbias0();
3270 //EnableMicBias(ADCType, enable);
3271 if (mAdc_Power_Mode == false)
3272 {
3273 SetMicbias1lowpower(false);
3274 SetMicbias0lowpower(false);
3275 }
3276 else
3277 {
3278 SetMicbias1lowpower(true);
3279 SetMicbias0lowpower(true);
3280 }
3281
3282 //Ana_Set_Reg(AUDMICBIAS_CFG1, 0x1ab5, 0xffff); //Enable MICBIAS2,3
3283 //Ana_Set_Reg(AUDMICBIAS_CFG1, 0x78F, 0xffff); //Enable MICBIAS0,1 (2.7V)
3284 SetMicVref2(0x2);// 1.9V
3285 SetMicVref3(0x2); // 1.9V
3286 SetMic2DCcoupleSwitch(false);
3287 SetMic3DCcoupleSwitch(false);
3288 if (mAdc_Power_Mode == false)
3289 {
3290 SetMic2powermode(false);
3291 SetMic3powermode(false);
3292 }
3293 else
3294 {
3295 SetMic2powermode(true);
3296 SetMic3powermode(true);
3297 }
3298
3299 //OpenMicbias3(true);
3300 //OpenMicbias2(true);
3301 if (mAdc_Power_Mode == false)
3302 {
3303 Ana_Set_Reg(AUDLDO_NVREG_CFG1, 0x0007, 0xffff); //Enable LCLDO18_ENC (1.8V), Remote-SENSEINFOBYTES
3304 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0000, 0x8888); //Enable LCLDO19_ADCCH0_1, Remote-Sense
3305 }
3306 else
3307 {
3308 Ana_Set_Reg(AUDLDO_NVREG_CFG1, 0x000f, 0xffff); //Enable LCLDO18_ENC (1.8V), Remote-Sense
3309 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x8888, 0x8888); //Enable LCLDO19_ADCCH0_1, Remote-Sense
3310 }
3311
3312 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2061, 0xffff); //DC_26M_50K_EN
3313 SetMicPGAGain();
3314
3315 Ana_Set_Reg(AUDPREAMP_CFG0, 0x01c7, 0xffff); //Enable PGA CH0_1 (CH0 in)
3316 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0055, 0xffff); //Enable ADC CH0_1 (PGA in)
3317 Ana_Set_Reg(AUDPREAMP_CFG0, 0x00d3, 0xffff); //Enable PGA CH0_1 (CH0 in)
3318
3319 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0x0000, 0xffff); //power on ADC clk
3320
3321 if ((GetDacStatus() == false))
3322 {
3323 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x005a, 0xffff); //power on clock
3324 }
3325 else
3326 {
3327 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0000, 0xffff); //power on clock
3328 }
3329
3330 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0x0000, 0xffff); //power on ADC clk
3331 Ana_Set_Reg(PMIC_AFE_TOP_CON0, 0x0000, 0xffff); //configure ADC setting
3332
3333 Ana_Set_Reg(AFE_MIC_ARRAY_CFG, 0x44e4, 0xffff); //AFE_MIC_ARRAY_CFG
3334 Ana_Set_Reg(AFE_UL_DL_CON0, 0x0001, 0xffff); //turn on afe
3335
3336 Ana_Set_Reg(AFE_PMIC_NEWIF_CFG2, 0x302F | (GetULNewIFFrequency(mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC]) << 10), 0xffff); // config UL up8x_rxif adc voice mode
3337 Ana_Set_Reg(AFE_UL_SRC0_CON0_H, (ULSampleRateTransform(SampleRate_VUL1) << 3 | ULSampleRateTransform(SampleRate_VUL1) << 1) , 0x001f); // ULsampling rate
3338
3339 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_H, (ULSampleRateTransform(SampleRate_VUL2) << 3 | ULSampleRateTransform(SampleRate_VUL2) << 1) , 0x001f); // ULsampling rate
3340 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_L, 0x0041, 0xffff);
3341
3342 Ana_Set_Reg(AFE_UL_SRC0_CON0_L, 0x0041, 0xffff); //power on uplink
3343
3344 }
3345 // todo , open ADC indivisaully
3346 EnableMicBias(ADCType, enable);
3347 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1)
3348 {
3349 if (mAdc_Power_Mode == false)
3350 {
3351 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0007, 0x000f); //Enable LCLDO19_ADCCH0_1, Remote-SENSEINFOBYTES
3352 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0070, 0x00f0); //Enable LCLDO19_ADCCH2, Remote-Sensen)
3353 }
3354 else
3355 {
3356 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x000f, 0x000f); //Enable LCLDO19_ADCCH0_1, Remote-Sense
3357 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x00f0, 0x00f0); //Enable LCLDO19_ADCCH2, Remote-Sensen)
3358 }
3359
3360 Ana_Set_Reg(AUDPREAMP_CFG0, 0x0007, 0x003f); //Enable PGA CH0_1
3361 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0055, 0x007f); //Enable ADC CH0_1 (PGA in)
3362 Ana_Set_Reg(AUDPREAMP_CFG0, 0x0013, 0x003f); //Enable PGA CH0_1
3363 Audio_ADC1_Set_Input(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC1]);
3364 SetDCcoupleNP(AUDIO_ANALOG_DEVICE_IN_ADC1, mAudio_Analog_Mic1_mode);
3365 AudioPreAmp1_Sel(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_1]);
3366 }
3367 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2)
3368 {
3369 if (mAdc_Power_Mode == false)
3370 {
3371 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0007, 0x000f); //Enable LCLDO19_ADCCH0_1, Remote-SENSEINFOBYTES
3372 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0070, 0x00f0); //Enable LCLDO19_ADCCH2, Remote-Sensen)
3373 }
3374 else
3375 {
3376 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x000f, 0x000f); //Enable LCLDO19_ADCCH0_1, Remote-Sense
3377 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x00f0, 0x00f0); //Enable LCLDO19_ADCCH2, Remote-Sensen)
3378 }
3379
3380 SetDCcoupleNP(AUDIO_ANALOG_DEVICE_IN_ADC2, mAudio_Analog_Mic2_mode);
3381 Ana_Set_Reg(AUDPREAMP_CFG0, 0x01c0, 0x03c0); //Enable PGA CH2
3382 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0055, 0x007f); //Enable ADC CH0_1 (PGA in)
3383 Ana_Set_Reg(AUDPREAMP_CFG0, 0x00c0, 0x03c0); //Enable PGA CH2
3384 Audio_ADC2_Set_Input(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC2]);
3385 }
3386 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC3)
3387 {
3388 if (mAdc_Power_Mode == false)
3389 {
3390 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0700, 0x0f00); //Enable LCLDO19_ADCCH3, Remote-Sense
3391 }
3392 else
3393 {
3394 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0f00, 0x0f00); //Enable LCLDO19_ADCCH3, Remote-Sense
3395 }
3396 Ana_Set_Reg(AUDPREAMP_CFG2, 0x0007, 0x000f); //Enable preamp CH3
3397 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0280, 0x0380); //Enable ADC CH3 (PGA in)
3398 Ana_Set_Reg(AUDPREAMP_CFG2, 0x0003, 0x000f); //Enable preamp CH3
3399 Audio_ADC3_Set_Input(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC3]);
3400
3401 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_H, (ULSampleRateTransform(SampleRate_VUL2) << 3 | ULSampleRateTransform(SampleRate_VUL2) << 1) , 0x001f); // ULsampling rate
3402 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_L, 0x0041, 0xffff);
3403 }
3404 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC4)
3405 {
3406 if (mAdc_Power_Mode == false)
3407 {
3408 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x7000, 0xf000); //Enable LCLDO19_ADCCH4, Remote-Sense
3409 }
3410 else
3411 {
3412 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0xf000, 0xf000); //Enable LCLDO19_ADCCH4, Remote-Sense
3413 }
3414 Ana_Set_Reg(AUDPREAMP_CFG2, 0x0070, 0x00f0); //Enable preamp CH4
3415 Ana_Set_Reg(AUDPREAMP_CFG1, 0x1400, 0x1c00); //Enable ADC CH4 (PGA in)
3416 Ana_Set_Reg(AUDPREAMP_CFG2, 0x0030, 0x00f0); //Enable preamp CH4
3417 Audio_ADC4_Set_Input(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC4]);
3418 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_H, (ULSampleRateTransform(SampleRate_VUL2) << 3 | ULSampleRateTransform(SampleRate_VUL2) << 1) , 0x001f); // ULsampling rate
3419 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_L, 0x0041, 0xffff);
3420 }
3421 else
3422 {
3423 printk("\n");
3424 }
3425 }
3426 else
3427 {
3428 if ((GetAdcStatus() == false))
3429 {
3430 Ana_Set_Reg(AFE_UL_SRC0_CON0_L, 0x0000, 0xffff); //power on uplink
3431 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_L, 0x0000, 0xffff); //power on uplink
3432 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0xa000, 0xffff); //power off
3433
3434 Ana_Set_Reg(AUDPREAMP_CFG0, 0x0000, 0xffff); //Disable ADC CH0_1 (PGA in) Disable ADC CH_2 (PGA in)
3435 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0000, 0xffff); //Disable PGA CH0_1 (CH0 in) Disable PGA CH_2
3436 Ana_Set_Reg(AUDPREAMPGAIN_CFG0, 0x0000, 0xffff); //Set PGA CH0_1 gain = 0dB Set PGA CH_2 gain = 0dB
3437 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x0, 0xffff); //DC_26M_50K_ off
3438
3439 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x2222, 0xffff); //disable LCLDO19_ADCCH0_1, Remote-Sense
3440 Ana_Set_Reg(AUDLDO_NVREG_CFG1, 0x0002, 0xffff); //disable LCLDO18_ENC (1.8V), Remote-Sense
3441
3442 //Ana_Set_Reg(AUDMICBIAS_CFG1, 0x2020, 0xffff); //power on clock
3443 SetMic2powermode(true);
3444 SetMic3powermode(true);
3445 //OpenMicbias3(false);
3446 //penMicbias2(false);
3447 //Ana_Set_Reg(AUDMICBIAS_CFG0, 0x0000, 0xffff); //power on ADC clk
3448 //CloseMicbias1();
3449 //CloseMicbias0();
3450 //EnableMicBias(ADCType, enable);
3451
3452 Ana_Set_Reg(AUDADC_CFG0, 0x0000, 0xffff); //configure ADC setting
3453
3454 ClsqAuxEnable(false);
3455 ClsqEnable(false);
3456 NvregEnable(false);
3457 Topck_Enable(false);
3458 audckbufEnable(false);
3459 if (GetDLStatus() == false)
3460 {
3461 Ana_Set_Reg(AFE_UL_DL_CON0, 0x0000, 0xffff); //turn off afe
3462 }
3463 else
3464 {
3465
3466 }
3467
3468 }
3469 EnableMicBias(ADCType, enable);
3470 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1)
3471 {
3472
3473 }
3474 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2)
3475 {
3476
3477 }
3478 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC3)
3479 {
3480
3481 }
3482 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC4)
3483 {
3484
3485 }
3486 }
3487 return true;
3488 }
3489
3490
3491 static bool TurnOnADcPowerDCCECM(int ADCType, bool enable)
3492 {
3493 printk("%s ADCType = %d enable = %d \n", __func__, ADCType, enable);
3494 if (enable)
3495 {
3496 //uint32 ULIndex = GetULFrequency(mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC]);
3497 uint32 SampleRate_VUL1 = mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC];
3498 uint32 SampleRate_VUL2 = mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC_2];
3499 if (GetAdcStatus() == false)
3500 {
3501 audckbufEnable(true);
3502 if (mAdc_Power_Mode == true)
3503 {
3504 Ana_Set_Reg(AUDBUF_CFG4, 0x0001, 0x0001); // Set AVDD32_AUD lowpower mode
3505 }
3506 else
3507 {
3508 Ana_Set_Reg(AUDBUF_CFG4, 0x0000, 0x0001); // Set AVDD32_AUD lowpower mode
3509 }
3510 NvregEnable(true); //Enable AUDGLB
3511 ClsqAuxEnable(true); //Enable ADC CLK
3512 ClsqEnable(true);
3513
3514 //here to set digital part
3515 Topck_Enable(true);
3516 AdcClockEnable(true);
3517
3518 if (mAdc_Power_Mode == true)
3519 {
3520 Ana_Set_Reg(AUDADC_CFG0, 0x4400, 0xffff); // Enable ADC CLK
3521 }
3522 else
3523 {
3524 Ana_Set_Reg(AUDADC_CFG0, 0x0400, 0xffff); // Enable ADC CLK
3525 }
3526
3527 SetDCcoupleNP(AUDIO_ANALOG_DEVICE_IN_ADC1, mAudio_Analog_Mic1_mode);
3528 SetDCcoupleNP(AUDIO_ANALOG_DEVICE_IN_ADC2, mAudio_Analog_Mic2_mode);
3529
3530 //OpenMicbias1();
3531 //OpenMicbias0();
3532 if (mAdc_Power_Mode == false)
3533 {
3534 SetMicbias1lowpower(false);
3535 SetMicbias0lowpower(false);
3536 }
3537 else
3538 {
3539 SetMicbias1lowpower(true);
3540 SetMicbias0lowpower(true);
3541 }
3542 //EnableMicBias(ADCType, enable);
3543
3544
3545 //Ana_Set_Reg(AUDMICBIAS_CFG1, 0x1ab5, 0xffff); //Enable MICBIAS2,3
3546 //Ana_Set_Reg(AUDMICBIAS_CFG1, 0x78F, 0xffff); //Enable MICBIAS0,1 (2.7V)
3547 SetMicVref2(0x2);// 1.9V
3548 SetMicVref3(0x2); // 1.9V
3549 SetMic2DCcoupleSwitch(true);
3550 SetMic3DCcoupleSwitch(true);
3551 if (mAdc_Power_Mode == false)
3552 {
3553 SetMic2powermode(false);
3554 SetMic3powermode(false);
3555 }
3556 else
3557 {
3558 SetMic2powermode(true);
3559 SetMic3powermode(true);
3560 }
3561
3562 //OpenMicbias3(true);
3563 //OpenMicbias2(true);
3564
3565 if (mAdc_Power_Mode == false)
3566 {
3567 Ana_Set_Reg(AUDLDO_NVREG_CFG1, 0x0007, 0xffff); //Enable LCLDO18_ENC (1.8V), Remote-Sense
3568 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0000, 0x8888); //Enable LCLDO19_ADCCH0_1, Remote-Sense
3569 }
3570 else
3571 {
3572 Ana_Set_Reg(AUDLDO_NVREG_CFG1, 0x000f, 0xffff); //Enable LCLDO18_ENC (1.8V), Remote-Sense
3573 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x8888, 0x8888); //Enable LCLDO19_ADCCH0_1, Remote-Sense
3574 }
3575
3576 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2061, 0xffff); //DC_26M_50K_EN
3577
3578 Ana_Set_Reg(AUDPREAMPGAIN_CFG0, 0x3333, 0xffff); //Set PGA CH0_1 gain = 18dB
3579 SetMicPGAGain();
3580
3581 Ana_Set_Reg(AUDPREAMP_CFG0, 0x01c7, 0xffff); //Enable PGA CH0_1 (CH0 in)
3582 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0055, 0xffff); //Enable ADC CH0_1 (PGA in)
3583 Ana_Set_Reg(AUDPREAMP_CFG0, 0x00d3, 0xffff); //Enable PGA CH0_1 (CH0 in)
3584
3585
3586 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0x0000, 0xffff); //power on ADC clk
3587
3588 if ((GetDacStatus() == false))
3589 {
3590 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x005a, 0xffff); //power on clock
3591 }
3592 else
3593 {
3594 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0000, 0xffff); //power on clock
3595 }
3596
3597 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0x0000, 0xffff); //power on ADC clk
3598 Ana_Set_Reg(PMIC_AFE_TOP_CON0, 0x0000, 0xffff); //configure ADC setting
3599
3600 Ana_Set_Reg(AFE_MIC_ARRAY_CFG, 0x44e4, 0xffff); //AFE_MIC_ARRAY_CFG
3601 Ana_Set_Reg(AFE_UL_DL_CON0, 0x0001, 0xffff); //turn on afe
3602
3603 Ana_Set_Reg(AFE_PMIC_NEWIF_CFG2, 0x302F | (GetULNewIFFrequency(mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC]) << 10), 0xffff); // config UL up8x_rxif adc voice mode
3604 Ana_Set_Reg(AFE_UL_SRC0_CON0_H, (ULSampleRateTransform(SampleRate_VUL1) << 3 | ULSampleRateTransform(SampleRate_VUL1) << 1) , 0x001f); // ULsampling rate
3605
3606 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_H, (ULSampleRateTransform(SampleRate_VUL2) << 3 | ULSampleRateTransform(SampleRate_VUL2) << 1) , 0x001f); // ULsampling rate
3607 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_L, 0x0041, 0xffff);
3608
3609 Ana_Set_Reg(AFE_UL_SRC0_CON0_L, 0x0041, 0xffff); //power on uplink
3610
3611 }
3612 EnableMicBias(ADCType, enable);
3613 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1)
3614 {
3615 if (mAdc_Power_Mode == false)
3616 {
3617 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0007, 0x000f); //Enable LCLDO19_ADCCH0_1, Remote-SENSEINFOBYTES
3618 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0070, 0x00f0); //Enable LCLDO19_ADCCH2, Remote-Sensen)
3619 }
3620 else
3621 {
3622 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x000f, 0x000f); //Enable LCLDO19_ADCCH0_1, Remote-Sense
3623 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x00f0, 0x00f0); //Enable LCLDO19_ADCCH2, Remote-Sensen)
3624 }
3625 Ana_Set_Reg(AUDPREAMP_CFG0, 0x0007, 0x003f); //Enable PGA CH0_1
3626 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0055, 0x007f); //Enable ADC CH0_1 (PGA in)
3627 Ana_Set_Reg(AUDPREAMP_CFG0, 0x0013, 0x003f); //Enable PGA CH0_1
3628 AudioPreAmp1_Sel(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_1]);
3629 Audio_ADC1_Set_Input(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC1]);
3630 SetDCcoupleNP(AUDIO_ANALOG_DEVICE_IN_ADC1, mAudio_Analog_Mic1_mode);
3631
3632 }
3633 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2)
3634 {
3635 if (mAdc_Power_Mode == false)
3636 {
3637 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0007, 0x000f); //Enable LCLDO19_ADCCH0_1, Remote-SENSEINFOBYTES
3638 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0070, 0x00f0); //Enable LCLDO19_ADCCH2, Remote-Sensen)
3639 }
3640 else
3641 {
3642 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x000f, 0x000f); //Enable LCLDO19_ADCCH0_1, Remote-Sense
3643 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x00f0, 0x00f0); //Enable LCLDO19_ADCCH2, Remote-Sensen)
3644 }
3645 Ana_Set_Reg(AUDPREAMP_CFG0, 0x01c0, 0x03c0); //Enable PGA CH2
3646 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0055, 0x007f); //Enable ADC CH0_1 (PGA in)
3647 Ana_Set_Reg(AUDPREAMP_CFG0, 0x00c0, 0x03c0); //Enable PGA CH2
3648 Audio_ADC2_Set_Input(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC2]);
3649 SetDCcoupleNP(AUDIO_ANALOG_DEVICE_IN_ADC2, mAudio_Analog_Mic2_mode);
3650 }
3651 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC3)
3652 {
3653 if (mAdc_Power_Mode == false)
3654 {
3655 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0700, 0x0f00); //Enable LCLDO19_ADCCH3, Remote-Sense
3656 }
3657 else
3658 {
3659 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x0f00, 0x0f00); //Enable LCLDO19_ADCCH3, Remote-Sense
3660 }
3661
3662 Ana_Set_Reg(AUDPREAMP_CFG2, 0x0007, 0x000f); //Enable preamp CH3
3663 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0280, 0x0380); //Enable ADC CH3 (PGA in)
3664 Ana_Set_Reg(AUDPREAMP_CFG2, 0x0003, 0x000f); //Enable preamp CH3
3665 Audio_ADC3_Set_Input(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC3]);
3666
3667 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_H, (ULSampleRateTransform(SampleRate_VUL2) << 3 | ULSampleRateTransform(SampleRate_VUL2) << 1) , 0x001f); // ULsampling rate
3668 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_L, 0x0041, 0xffff);
3669 }
3670 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC4)
3671 {
3672 if (mAdc_Power_Mode == false)
3673 {
3674 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x7000, 0xf000); //Enable LCLDO19_ADCCH4, Remote-Sense
3675 }
3676 else
3677 {
3678 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0xf000, 0xf000); //Enable LCLDO19_ADCCH4, Remote-Sense
3679 }
3680
3681 Ana_Set_Reg(AUDPREAMP_CFG2, 0x0070, 0x00f0); //Enable preamp CH4
3682 Ana_Set_Reg(AUDPREAMP_CFG1, 0x1400, 0x1c00); //Enable ADC CH4 (PGA in)
3683 Ana_Set_Reg(AUDPREAMP_CFG2, 0x0030, 0x00f0); //Enable preamp CH4
3684 Audio_ADC4_Set_Input(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC4]);
3685
3686 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_H, (ULSampleRateTransform(SampleRate_VUL2) << 3 | ULSampleRateTransform(SampleRate_VUL2) << 1) , 0x001f); // ULsampling rate
3687 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_L, 0x0041, 0xffff);
3688 }
3689 else
3690 {
3691 printk("\n");
3692 }
3693 }
3694 else
3695 {
3696 if ((GetAdcStatus() == false))
3697 {
3698 Ana_Set_Reg(AFE_UL_SRC0_CON0_L, 0x0000, 0xffff); //power on uplink
3699 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_L, 0x0000, 0xffff); //power on uplink
3700 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0xa000, 0xffff); //power off
3701
3702 Ana_Set_Reg(AUDPREAMP_CFG0, 0x0000, 0xffff); //Disable ADC CH0_1 (PGA in) Disable ADC CH_2 (PGA in)
3703 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0000, 0xffff); //Disable PGA CH0_1 (CH0 in) Disable PGA CH_2
3704 Ana_Set_Reg(AUDPREAMPGAIN_CFG0, 0x0000, 0xffff); //Set PGA CH0_1 gain = 0dB Set PGA CH_2 gain = 0dB
3705 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x0, 0xffff); //DC_26M_50K_ off
3706
3707 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x2222, 0xffff); //disable LCLDO19_ADCCH0_1, Remote-Sense
3708 Ana_Set_Reg(AUDLDO_NVREG_CFG1, 0x0002, 0xffff); //disable LCLDO18_ENC (1.8V), Remote-Sense
3709
3710 //Ana_Set_Reg(AUDMICBIAS_CFG1, 0x2020, 0xffff); //power on clock
3711 SetMic2powermode(true);
3712 SetMic3powermode(true);
3713 //OpenMicbias3(false);
3714 //OpenMicbias2(false);
3715 //EnableMicBias(ADCType, enable);
3716
3717 //Ana_Set_Reg(AUDMICBIAS_CFG0, 0x0000, 0xffff); //power on ADC clk
3718 //CloseMicbias1();
3719 //CloseMicbias0();
3720
3721 Ana_Set_Reg(AUDADC_CFG0, 0x0000, 0xffff); //configure ADC setting
3722
3723 ClsqAuxEnable(false);
3724 ClsqEnable(false);
3725 NvregEnable(false);
3726 Topck_Enable(false);
3727 audckbufEnable(false);
3728 if (GetDLStatus() == false)
3729 {
3730 Ana_Set_Reg(AFE_UL_DL_CON0, 0x0000, 0xffff); //turn off afe
3731 }
3732 else
3733 {
3734
3735 }
3736
3737 }
3738 EnableMicBias(ADCType, enable);
3739 //todo , close analog
3740 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1)
3741 {
3742
3743 }
3744 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2)
3745 {
3746
3747 }
3748 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC3)
3749 {
3750
3751 }
3752 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC4)
3753 {
3754
3755 }
3756 }
3757 return true;
3758 }
3759
3760 static bool TurnOnVOWDigitalHW(bool enable)
3761 {
3762 printk("%s enable = %d \n", __func__, enable);
3763 if (enable)
3764 {
3765 Ana_Set_Reg(AFE_VOW_TOP, 0x0810, 0xffff); //VOW control (window mode)
3766 }
3767 else
3768 {
3769 Ana_Set_Reg(AFE_VOW_TOP, 0x0012, 0xffff); //VOW control
3770 Ana_Set_Reg(AFE_VOW_TOP, 0x8012, 0xffff); //VOW control
3771 }
3772 return true;
3773 }
3774
3775 static bool TurnOnVOWADcPowerACC(int ADCType, bool enable)
3776 {
3777 printk("%s ADCType = %d enable = %d \n", __func__, ADCType, enable);
3778 if (enable)
3779 {
3780 #if defined(VOW_TONE_TEST)
3781 OpenAfeDigitaldl1(false);
3782 OpenAnalogHeadphone(false);
3783 EnableSideGenHw(Soc_Aud_InterConnectionOutput_O03, Soc_Aud_InterConnectionOutput_Num_Output, false);
3784 AudDrv_Clk_Off();
3785 #endif
3786 #if defined (MTK_VOW_SUPPORT)
3787 //Set VOW driver status first
3788 VowDrv_EnableHW(true);
3789 #endif
3790 //uint32 ULIndex = GetULFrequency(mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC]);
3791 //uint32 SampleRate = 8000;//mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC];
3792 //if (GetAdcStatus() == false) //[Todo]Implement concurrncy test
3793 {
3794 NvregEnable(true); // Enable AUDGLB
3795 //Ana_Set_Reg(AUDNVREGGLB_CFG0, 0x0000, 0xffff);
3796 Ana_Set_Reg(ANALDO_CON3, 0xc542, 0xffff); //Enable AVDD32_AUD lowpower mode
3797 Ana_Set_Reg(AUDBUF_CFG4, 0x1, 0xffff); //Set AUDGLB lowpower mode
3798 Ana_Set_Reg(AUDMICBIAS_CFG0, 0x004f, 0xffff); //Set MICBIAS0 lowpower mode - Enable MICBIAS0 (2.7v)
3799 Ana_Set_Reg(AUDLDO_NVREG_CFG1, 0x000f, 0xffff); //Set LCLDO18_ENC low power mode
3800 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x222f, 0xffff); //Set LCLDO19_ADCCH0_1 low power mode
3801
3802 Ana_Set_Reg(AUDVOWPLL_CFG2, 0x002b, 0xffff); //enable PLL relatch
3803 Ana_Set_Reg(AUDVOWPLL_CFG0, 0x00bd, 0xffff); //enable PLL
3804
3805 Ana_Set_Reg(AUDADC_CFG0, 0x3400, 0xffff); //Set CLK from MADPLL and Enable ADCCLK (12.84MHz/4)
3806
3807 Ana_Set_Reg(AUDPREAMPGAIN_CFG0, 0x0002, 0xffff); //Set PGA CH0_1 gain=12dB
3808 Ana_Set_Reg(AUDPREAMP_CFG0, 0x0011, 0xffff); //Enable PGA CH0_1 (CH0 in)
3809
3810 Ana_Set_Reg(AUDADC_CFG1, 0x6400, 0xffff); //Set UP GLB lowpower mode, set ADC low CLK rate mode
3811
3812 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0005, 0xffff); //Enable ADC CH0_1 (PGA in)
3813
3814 //here to set digital part
3815 //Ana_Set_Reg(TOP_CLKSQ_SET, 0x0003, 0xffff); //Enable CLKSQ [Todo]Modify ClsqEnable
3816 ClsqEnable(true);
3817 ClsqAuxEnable(true);
3818 //Ana_Set_Reg(TOP_CKPDN_CON0_CLR, 0x8000, 0xffff); //Enable CLKSQ [Todo]Modify ClsqEnable
3819
3820
3821 //Topck_Enable(true);
3822 LowPowerAdcClockEnable(true);
3823 //Ana_Set_Reg(TOP_CKPDN_CON0_CLR, 0x8000, 0xffff);
3824 //[Todo]Enable VOW INT (has alredy done in pmic.c)
3825 //enable VOW INT in pmic driver
3826 //~
3827 #if 1 //Set by HAL
3828 Ana_Set_Reg(AFE_VOW_CFG0, reg_AFE_VOW_CFG0, 0xffff); //bias removing reference amp
3829 Ana_Set_Reg(AFE_VOW_CFG1, reg_AFE_VOW_CFG1, 0xffff); //watch dog timer initial value
3830 Ana_Set_Reg(AFE_VOW_CFG2, reg_AFE_VOW_CFG2, 0xffff); //VOW A/B value
3831 Ana_Set_Reg(AFE_VOW_CFG3, reg_AFE_VOW_CFG3, 0xffff); //VOW alpha/beta value
3832 Ana_Set_Reg(AFE_VOW_CFG4, reg_AFE_VOW_CFG4, 0xffff); //VOW ADC test config
3833 Ana_Set_Reg(AFE_VOW_CFG5, reg_AFE_VOW_CFG5, 0xffff); //N min value
3834 #endif
3835 //Ana_Set_Reg(AFE_VOW_TOP, 0x0810, 0xffff); //VOW control (window mode)
3836 //TurnOnVOWDigitalHW(true);//move to another digital control
3837 #if defined(VOW_TONE_TEST)
3838 //test output
3839 AudDrv_Clk_On();
3840 OpenAfeDigitaldl1(true);
3841 OpenAnalogHeadphone(true);
3842 #endif
3843 }
3844
3845 }
3846 else
3847 {
3848 #if defined (MTK_VOW_SUPPORT)
3849 //Set VOW driver status first
3850 VowDrv_EnableHW(false);
3851 #endif
3852 //if (GetAdcStatus() == false)
3853 {
3854 // turn off digital first
3855 //Ana_Set_Reg(AFE_VOW_TOP, 0x0012, 0xffff); //MAD control
3856 //Ana_Set_Reg(AFE_VOW_TOP, 0x8012, 0xffff); //MAD control
3857 //TurnOnVOWDigitalHW(false);//move to another digital control
3858 LowPowerAdcClockEnable(false);
3859 //Ana_Set_Reg(TOP_CKPDN_CON0_SET, 0x8000, 0xffff);
3860 ClsqEnable(false);
3861 ClsqAuxEnable(false);
3862 // turn off analog
3863 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0000, 0xffff); //Disable ADC CH0_1 (PGA in)
3864 Ana_Set_Reg(AUDADC_CFG1, 0x0400, 0xffff); //"Disable UP GLB lowpower mode Disable ADC low CLK rate mode"
3865 Ana_Set_Reg(AUDPREAMP_CFG0, 0x0000, 0xffff); //Disable PGA CH0_1 (CH0 in)
3866 Ana_Set_Reg(AUDPREAMPGAIN_CFG0, 0x0000, 0xffff); //Set PGA CH0_1 gain = 0dB
3867 Ana_Set_Reg(AUDADC_CFG0, 0x0000, 0xffff); //"Set CLK from CLKSQ Disable ADC CLK (12.84MHz/4)"
3868 Ana_Set_Reg(AUDVOWPLL_CFG0, 0x00BC, 0xffff); //Disable PLL (F=32768*(47+2)*8)
3869 Ana_Set_Reg(AUDVOWPLL_CFG2, 0x0023, 0xffff); //Disable PLL Relatch
3870 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x2222, 0xffff); //Disable LCLDO19_ADCCH0_1, Remote-Sense
3871 Ana_Set_Reg(AUDLDO_NVREG_CFG1, 0x0002, 0xffff); //"Disable LCLDO18_ENC (1.8V), Remote-Sense Set LCLDO19_ADC voltage 1.9V"
3872 Ana_Set_Reg(AUDMICBIAS_CFG0, 0x0000, 0xffff); //"Disable MICBIAS0 lowpower modeDisable MICBIAS0 (2.7V)"
3873 Ana_Set_Reg(AUDBUF_CFG4, 0x0000, 0xffff); //Disable AUDGLB lowpower mode
3874 Ana_Set_Reg(ANALDO_CON3, 0xC540, 0xffff); //Disable AVDD32_AUD lowpower mode
3875 //Ana_Set_Reg( AUDNVREGGLB_CFG0, 0x0001, 0xffff); //Disable AUDGLB
3876 //ClsqEnable(false);
3877 NvregEnable(false);
3878 //Ana_Set_Reg(AUDNVREGGLB_CFG0, 0x0001, 0xffff);
3879 //Topck_Enable(false);
3880 }
3881 }
3882 return true;
3883 }
3884
3885
3886
3887 // here start uplink power function
3888 static const char *ADC_function[] = {"Off", "On"};
3889 static const char *ADC_power_mode[] = {"normal", "lowpower"};
3890 static const char *PreAmp_Mux_function[] = {"OPEN", "IN_ADC1", "IN_ADC2"};
3891 static const char *ADC_UL_PGA_GAIN[] = { "0Db", "6Db", "12Db", "18Db", "24Db", "30Db"};
3892 static const char *Pmic_Digital_Mux[] = { "ADC1", "ADC2", "ADC3", "ADC4"};
3893 static const char *Adc_Input_Sel[] = { "idle", "AIN", "Preamp"};
3894 static const char *Audio_AnalogMic_Mode[] = { "ACCMODE", "DCCMODE", "DMIC", "DCCECMDIFFMODE", "DCCECMSINGLEMODE"};
3895 static const char *Audio_VOW_ADC_Function[] = {"Off", "On"};
3896 static const char *Audio_VOW_Digital_Function[] = {"Off", "On"};
3897
3898 static const struct soc_enum Audio_UL_Enum[] =
3899 {
3900 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_function), ADC_function),
3901 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_function), ADC_function),
3902 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_function), ADC_function),
3903 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_function), ADC_function),
3904 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(PreAmp_Mux_function), PreAmp_Mux_function),
3905 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Adc_Input_Sel), Adc_Input_Sel),
3906 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Adc_Input_Sel), Adc_Input_Sel),
3907 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Adc_Input_Sel), Adc_Input_Sel),
3908 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Adc_Input_Sel), Adc_Input_Sel),
3909 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_UL_PGA_GAIN), ADC_UL_PGA_GAIN),
3910 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_UL_PGA_GAIN), ADC_UL_PGA_GAIN),
3911 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_UL_PGA_GAIN), ADC_UL_PGA_GAIN),
3912 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_UL_PGA_GAIN), ADC_UL_PGA_GAIN),
3913 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Digital_Mux), Pmic_Digital_Mux),
3914 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Digital_Mux), Pmic_Digital_Mux),
3915 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Digital_Mux), Pmic_Digital_Mux),
3916 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Digital_Mux), Pmic_Digital_Mux),
3917 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Audio_AnalogMic_Mode), Audio_AnalogMic_Mode),
3918 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Audio_AnalogMic_Mode), Audio_AnalogMic_Mode),
3919 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Audio_AnalogMic_Mode), Audio_AnalogMic_Mode),
3920 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Audio_AnalogMic_Mode), Audio_AnalogMic_Mode),
3921 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_power_mode), ADC_power_mode),
3922 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Audio_VOW_ADC_Function), Audio_VOW_ADC_Function),
3923 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Audio_VOW_Digital_Function), Audio_VOW_Digital_Function),
3924 };
3925
3926 static int Audio_ADC1_Get(struct snd_kcontrol *kcontrol,
3927 struct snd_ctl_elem_value *ucontrol)
3928 {
3929 printk("Audio_ADC1_Get = %d\n", mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC1]);
3930 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC1];
3931 return 0;
3932 }
3933
3934 static int Audio_ADC1_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3935 {
3936 printk("%s()\n", __func__);
3937 mutex_lock(&Ana_Power_Mutex);
3938 if (ucontrol->value.integer.value[0])
3939 {
3940 if (mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_ACC)
3941 {
3942 TurnOnADcPowerACC(AUDIO_ANALOG_DEVICE_IN_ADC1 , true);
3943 }
3944 else if (mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_DCC)
3945 {
3946 TurnOnADcPowerDCC(AUDIO_ANALOG_DEVICE_IN_ADC1 , true);
3947 }
3948 else if (mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_DMIC)
3949 {
3950 TurnOnADcPowerDmic(AUDIO_ANALOG_DEVICE_IN_ADC1, true);
3951 }
3952 else if (mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_DCCECMDIFF || mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_DCCECMSINGLE)
3953 {
3954 TurnOnADcPowerDCCECM(AUDIO_ANALOG_DEVICE_IN_ADC1 , true);
3955 }
3956 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC1] = ucontrol->value.integer.value[0];
3957 }
3958 else
3959 {
3960 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC1] = ucontrol->value.integer.value[0];
3961 if (mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_ACC)
3962 {
3963 TurnOnADcPowerACC(AUDIO_ANALOG_DEVICE_IN_ADC1 , false);
3964 }
3965 else if (mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_DCC)
3966 {
3967 TurnOnADcPowerDCC(AUDIO_ANALOG_DEVICE_IN_ADC1 , false);
3968 }
3969 else if (mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_DMIC)
3970 {
3971 TurnOnADcPowerDmic(AUDIO_ANALOG_DEVICE_IN_ADC1, false);
3972 }
3973 else if (mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_DCCECMDIFF || mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_DCCECMSINGLE)
3974 {
3975 TurnOnADcPowerDCCECM(AUDIO_ANALOG_DEVICE_IN_ADC1, false);
3976 }
3977 }
3978 mutex_unlock(&Ana_Power_Mutex);
3979 return 0;
3980 }
3981
3982 static int Audio_ADC2_Get(struct snd_kcontrol *kcontrol,
3983 struct snd_ctl_elem_value *ucontrol)
3984 {
3985 printk("Audio_ADC2_Get = %d\n", mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC2]);
3986 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC2];
3987 return 0;
3988 }
3989
3990 static int Audio_ADC2_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3991 {
3992 printk("%s()\n", __func__);
3993 mutex_lock(&Ana_Power_Mutex);
3994 if (ucontrol->value.integer.value[0])
3995 {
3996 if (mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_ACC)
3997 {
3998 TurnOnADcPowerACC(AUDIO_ANALOG_DEVICE_IN_ADC2 , true);
3999 }
4000 else if (mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_DCC)
4001 {
4002 TurnOnADcPowerDCC(AUDIO_ANALOG_DEVICE_IN_ADC2 , true);
4003 }
4004 else if (mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_DMIC)
4005 {
4006 TurnOnADcPowerDmic(AUDIO_ANALOG_DEVICE_IN_ADC2 , true);
4007 }
4008 else if (mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_DCCECMDIFF || mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_DCCECMSINGLE)
4009 {
4010 TurnOnADcPowerDCCECM(AUDIO_ANALOG_DEVICE_IN_ADC2 , true);
4011 }
4012 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC2] = ucontrol->value.integer.value[0];
4013 }
4014 else
4015 {
4016 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC2] = ucontrol->value.integer.value[0];
4017 if (mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_ACC)
4018 {
4019 TurnOnADcPowerACC(AUDIO_ANALOG_DEVICE_IN_ADC2 , false);
4020 }
4021 else if (mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_DCC)
4022 {
4023 TurnOnADcPowerDCC(AUDIO_ANALOG_DEVICE_IN_ADC2 , false);
4024 }
4025 else if (mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_DMIC)
4026 {
4027 TurnOnADcPowerDmic(AUDIO_ANALOG_DEVICE_IN_ADC2 , false);
4028 }
4029 else if (mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_DCCECMDIFF || mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_DCCECMSINGLE)
4030 {
4031 TurnOnADcPowerDCCECM(AUDIO_ANALOG_DEVICE_IN_ADC2 , false);
4032 }
4033 }
4034 mutex_unlock(&Ana_Power_Mutex);
4035 return 0;
4036 }
4037
4038 static int Audio_ADC3_Get(struct snd_kcontrol *kcontrol,
4039 struct snd_ctl_elem_value *ucontrol)
4040 {
4041 printk("Audio_ADC3_Get = %d\n", mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC3]);
4042 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC3];
4043 return 0;
4044 }
4045
4046 static int Audio_ADC3_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4047 {
4048 printk("%s()\n", __func__);
4049 mutex_lock(&Ana_Power_Mutex);
4050 if (ucontrol->value.integer.value[0])
4051 {
4052 if (mAudio_Analog_Mic3_mode == AUDIO_ANALOGUL_MODE_ACC)
4053 {
4054 TurnOnADcPowerACC(AUDIO_ANALOG_DEVICE_IN_ADC3 , true);
4055 }
4056 else if (mAudio_Analog_Mic3_mode == AUDIO_ANALOGUL_MODE_DCC)
4057 {
4058 TurnOnADcPowerDCC(AUDIO_ANALOG_DEVICE_IN_ADC3 , true);
4059 }
4060 else if (mAudio_Analog_Mic3_mode == AUDIO_ANALOGUL_MODE_DMIC)
4061 {
4062 TurnOnADcPowerDmic(AUDIO_ANALOG_DEVICE_IN_ADC3 , true);
4063 }
4064 else if (mAudio_Analog_Mic3_mode == AUDIO_ANALOGUL_MODE_DCCECMDIFF || mAudio_Analog_Mic3_mode == AUDIO_ANALOGUL_MODE_DCCECMSINGLE)
4065 {
4066 TurnOnADcPowerDCCECM(AUDIO_ANALOG_DEVICE_IN_ADC3 , true);
4067 }
4068 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC3] = ucontrol->value.integer.value[0];
4069 }
4070 else
4071 {
4072 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC3] = ucontrol->value.integer.value[0];
4073
4074 if (mAudio_Analog_Mic3_mode == AUDIO_ANALOGUL_MODE_ACC)
4075 {
4076 TurnOnADcPowerACC(AUDIO_ANALOG_DEVICE_IN_ADC3 , false);
4077 }
4078 else if (mAudio_Analog_Mic3_mode == AUDIO_ANALOGUL_MODE_DCC)
4079 {
4080 TurnOnADcPowerDCC(AUDIO_ANALOG_DEVICE_IN_ADC3 , false);
4081 }
4082 else if (mAudio_Analog_Mic3_mode == AUDIO_ANALOGUL_MODE_DMIC)
4083 {
4084 TurnOnADcPowerDmic(AUDIO_ANALOG_DEVICE_IN_ADC3 , false);
4085 }
4086 else if (mAudio_Analog_Mic3_mode == AUDIO_ANALOGUL_MODE_DCCECMDIFF || mAudio_Analog_Mic3_mode == AUDIO_ANALOGUL_MODE_DCCECMSINGLE)
4087 {
4088 TurnOnADcPowerDCCECM(AUDIO_ANALOG_DEVICE_IN_ADC3 , false);
4089 }
4090 }
4091 mutex_unlock(&Ana_Power_Mutex);
4092 return 0;
4093 }
4094
4095 static int Audio_ADC4_Get(struct snd_kcontrol *kcontrol,
4096 struct snd_ctl_elem_value *ucontrol)
4097 {
4098 printk("Audio_ADC4_Get = %d\n", mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC4]);
4099 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC4];
4100 return 0;
4101 }
4102
4103 static int Audio_ADC4_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4104 {
4105 printk("%s()\n", __func__);
4106 mutex_lock(&Ana_Power_Mutex);
4107 if (ucontrol->value.integer.value[0])
4108 {
4109 if (mAudio_Analog_Mic4_mode == AUDIO_ANALOGUL_MODE_ACC)
4110 {
4111 TurnOnADcPowerACC(AUDIO_ANALOG_DEVICE_IN_ADC4 , true);
4112 }
4113 else if (mAudio_Analog_Mic4_mode == AUDIO_ANALOGUL_MODE_DCC)
4114 {
4115 TurnOnADcPowerDCC(AUDIO_ANALOG_DEVICE_IN_ADC4 , true);
4116 }
4117 else if (mAudio_Analog_Mic4_mode == AUDIO_ANALOGUL_MODE_DMIC)
4118 {
4119 TurnOnADcPowerDmic(AUDIO_ANALOG_DEVICE_IN_ADC4 , true);
4120 }
4121 else if (mAudio_Analog_Mic4_mode == AUDIO_ANALOGUL_MODE_DCCECMDIFF || mAudio_Analog_Mic4_mode == AUDIO_ANALOGUL_MODE_DCCECMSINGLE)
4122 {
4123 TurnOnADcPowerDCCECM(AUDIO_ANALOG_DEVICE_IN_ADC4 , true);
4124 }
4125 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC4] = ucontrol->value.integer.value[0];
4126 }
4127 else
4128 {
4129 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC4] = ucontrol->value.integer.value[0];
4130 if (mAudio_Analog_Mic4_mode == AUDIO_ANALOGUL_MODE_ACC)
4131 {
4132 TurnOnADcPowerACC(AUDIO_ANALOG_DEVICE_IN_ADC4 , false);
4133 }
4134 else if (mAudio_Analog_Mic4_mode == AUDIO_ANALOGUL_MODE_DCC)
4135 {
4136 TurnOnADcPowerDCC(AUDIO_ANALOG_DEVICE_IN_ADC4 , false);
4137 }
4138 else if (mAudio_Analog_Mic4_mode == AUDIO_ANALOGUL_MODE_DMIC)
4139 {
4140 TurnOnADcPowerDmic(AUDIO_ANALOG_DEVICE_IN_ADC4 , false);
4141 }
4142 else if (mAudio_Analog_Mic4_mode == AUDIO_ANALOGUL_MODE_DCCECMDIFF || mAudio_Analog_Mic4_mode == AUDIO_ANALOGUL_MODE_DCCECMSINGLE)
4143 {
4144 TurnOnADcPowerDCCECM(AUDIO_ANALOG_DEVICE_IN_ADC4 , false);
4145 }
4146 }
4147 mutex_unlock(&Ana_Power_Mutex);
4148 return 0;
4149 }
4150
4151 static int Audio_ADC1_Sel_Get(struct snd_kcontrol *kcontrol,
4152 struct snd_ctl_elem_value *ucontrol)
4153 {
4154 printk("%s() = %d\n", __func__, mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC1]);
4155 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC1];
4156 return 0;
4157 }
4158
4159 static void Audio_ADC1_Set_Input(int Input)
4160 {
4161 if (Input == AUDIO_ANALOG_AUDIOANALOG_INPUT_OPEN)
4162 {
4163 Ana_Set_Reg(AUDPREAMP_CFG1, (0x0000 << 1), 0x0006); // pinumx sel
4164 }
4165 else if (Input == AUDIO_ANALOG_AUDIOANALOG_INPUT_ADC)
4166 {
4167 Ana_Set_Reg(AUDPREAMP_CFG1, (0x0001 << 1), 0x0006);
4168 }
4169 // ADC2
4170 else if (Input == AUDIO_ANALOG_AUDIOANALOG_INPUT_PREAMP)
4171 {
4172 Ana_Set_Reg(AUDPREAMP_CFG1, (0x0002 << 1), 0x0006);
4173 }
4174 else
4175 {
4176 printk("%s() warning \n ", __func__);
4177 }
4178 printk("%s() done \n", __func__);
4179 }
4180
4181 static int Audio_ADC1_Sel_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4182 {
4183 int input = ucontrol->value.integer.value[0] ;
4184 printk("%s()\n", __func__);
4185 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Adc_Input_Sel))
4186 {
4187 printk("return -EINVAL\n");
4188 return -EINVAL;
4189 }
4190 Audio_ADC1_Set_Input(input);
4191 printk("%s() done \n", __func__);
4192 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC1] = ucontrol->value.integer.value[0];
4193 return 0;
4194 }
4195
4196 static int Audio_ADC2_Sel_Get(struct snd_kcontrol *kcontrol,
4197 struct snd_ctl_elem_value *ucontrol)
4198 {
4199 printk("%s() = %d\n", __func__, mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC2]);
4200 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC2];
4201 return 0;
4202 }
4203
4204 static void Audio_ADC2_Set_Input(int Input)
4205 {
4206 if (Input == AUDIO_ANALOG_AUDIOANALOG_INPUT_OPEN)
4207 {
4208 Ana_Set_Reg(AUDPREAMP_CFG1, (0x0000 << 5), 0x0060); // pinumx sel
4209 }
4210 else if (Input == AUDIO_ANALOG_AUDIOANALOG_INPUT_ADC)
4211 {
4212 Ana_Set_Reg(AUDPREAMP_CFG1, (0x0001 << 5), 0x0060);
4213 }
4214 else if (Input == AUDIO_ANALOG_AUDIOANALOG_INPUT_PREAMP)
4215 {
4216 Ana_Set_Reg(AUDPREAMP_CFG1, (0x0002 << 5), 0x0060);
4217 }
4218 else
4219 {
4220 printk("%s() warning \n ", __func__);
4221 }
4222 }
4223
4224
4225 static int Audio_ADC2_Sel_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4226 {
4227 int input = ucontrol->value.integer.value[0];
4228 printk("%s()\n", __func__);
4229 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Adc_Input_Sel))
4230 {
4231 printk("return -EINVAL\n");
4232 return -EINVAL;
4233 }
4234 Audio_ADC2_Set_Input(input);
4235 printk("%s() done \n", __func__);
4236 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC2] = ucontrol->value.integer.value[0];
4237 return 0;
4238 }
4239
4240 static void Audio_ADC3_Set_Input(int Input)
4241 {
4242 if (Input == AUDIO_ANALOG_AUDIOANALOG_INPUT_OPEN)
4243 {
4244 Ana_Set_Reg(AUDPREAMP_CFG1, (0x0000 << 8), 0x0300); // pinumx sel
4245 }
4246 else if (Input == AUDIO_ANALOG_AUDIOANALOG_INPUT_ADC)
4247 {
4248 Ana_Set_Reg(AUDPREAMP_CFG1, (0x0001 << 8), 0x0300);
4249 }
4250 else if (Input == AUDIO_ANALOG_AUDIOANALOG_INPUT_PREAMP)
4251 {
4252 Ana_Set_Reg(AUDPREAMP_CFG1, (0x0002 << 8), 0x0300);
4253 }
4254 else
4255 {
4256 printk("%s() warning \n ", __func__);
4257 }
4258 }
4259
4260 static int Audio_ADC3_Sel_Get(struct snd_kcontrol *kcontrol,
4261 struct snd_ctl_elem_value *ucontrol)
4262 {
4263 printk("%s() = %d\n", __func__, mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC3]);
4264 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC3];
4265 return 0;
4266 }
4267
4268 static int Audio_ADC3_Sel_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4269 {
4270 int input = ucontrol->value.integer.value[0];
4271 printk("%s()\n", __func__);
4272
4273 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Adc_Input_Sel))
4274 {
4275 printk("return -EINVAL\n");
4276 return -EINVAL;
4277 }
4278 Audio_ADC3_Set_Input(input);
4279 printk("%s() done \n", __func__);
4280 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC3] = ucontrol->value.integer.value[0];
4281 return 0;
4282 }
4283
4284 static int Audio_ADC4_Sel_Get(struct snd_kcontrol *kcontrol,
4285 struct snd_ctl_elem_value *ucontrol)
4286 {
4287 printk("%s() = %d\n", __func__, mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC4]);
4288 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC4];
4289 return 0;
4290 }
4291
4292 static void Audio_ADC4_Set_Input(int Input)
4293 {
4294 if (Input == AUDIO_ANALOG_AUDIOANALOG_INPUT_OPEN)
4295 {
4296 Ana_Set_Reg(AUDPREAMP_CFG1, (0x0000 << 11), 0x1800); // pinumx sel
4297 }
4298 else if (Input == AUDIO_ANALOG_AUDIOANALOG_INPUT_ADC)
4299 {
4300 Ana_Set_Reg(AUDPREAMP_CFG1, (0x0001 << 11), 0x1800);
4301 }
4302 else if (Input == AUDIO_ANALOG_AUDIOANALOG_INPUT_PREAMP)
4303 {
4304 Ana_Set_Reg(AUDPREAMP_CFG1, (0x0002 << 11), 0x1800);
4305 }
4306 else
4307 {
4308 printk("%s() warning \n ", __func__);
4309 }
4310 }
4311
4312
4313 static int Audio_ADC4_Sel_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4314 {
4315 int input = ucontrol->value.integer.value[0];
4316 printk("%s()\n", __func__);
4317
4318 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Adc_Input_Sel))
4319 {
4320 printk("return -EINVAL\n");
4321 return -EINVAL;
4322 }
4323 Audio_ADC4_Set_Input(input);
4324 printk("%s() done \n", __func__);
4325 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC4] = ucontrol->value.integer.value[0];
4326 return 0;
4327 }
4328
4329 static bool AudioPreAmp1_Sel(int Mul_Sel)
4330 {
4331 printk("%s Mul_Sel = %d ", __func__, Mul_Sel);
4332 if (Mul_Sel == 0)
4333 {
4334 Ana_Set_Reg(AUDPREAMP_CFG0, 0x0000, 0x0030); // pinumx open
4335 }
4336 else if (Mul_Sel == 1)
4337 {
4338 Ana_Set_Reg(AUDPREAMP_CFG0, 0x0010, 0x0030); // ADC 0
4339 }
4340 // ADC2
4341 else if (Mul_Sel == 2)
4342 {
4343 Ana_Set_Reg(AUDPREAMP_CFG0, 0x0020, 0x0030); // ADC 1
4344 }
4345 else
4346 {
4347 printk("AnalogSetMux warning");
4348 }
4349
4350 return true;
4351 }
4352
4353
4354 static int Audio_PreAmp1_Get(struct snd_kcontrol *kcontrol,
4355 struct snd_ctl_elem_value *ucontrol)
4356 {
4357 printk("%s() mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_1]; = %d\n", __func__, mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_1]);
4358 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_1];
4359 return 0;
4360 }
4361
4362 static int Audio_PreAmp1_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4363 {
4364 printk("%s()\n", __func__);
4365
4366 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(PreAmp_Mux_function))
4367 {
4368 printk("return -EINVAL\n");
4369 return -EINVAL;
4370 }
4371 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_1] = ucontrol->value.integer.value[0];
4372 AudioPreAmp1_Sel(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_1]);
4373 printk("%s() done \n", __func__);
4374 return 0;
4375 }
4376
4377 static int Audio_PGA1_Get(struct snd_kcontrol *kcontrol,
4378 struct snd_ctl_elem_value *ucontrol)
4379 {
4380 printk("Audio_AmpR_Get = %d\n", mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP1]);
4381 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP1];
4382 return 0;
4383 }
4384
4385 static int Audio_PGA1_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4386 {
4387 int index = 0;
4388 printk("%s()\n", __func__);
4389 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(ADC_UL_PGA_GAIN))
4390 {
4391 printk("return -EINVAL\n");
4392 return -EINVAL;
4393 }
4394 index = ucontrol->value.integer.value[0];
4395 Ana_Set_Reg(AUDPREAMPGAIN_CFG0, index , 0x0007);
4396 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP1] = ucontrol->value.integer.value[0];
4397 return 0;
4398 }
4399
4400
4401 static int Audio_PGA2_Get(struct snd_kcontrol *kcontrol,
4402 struct snd_ctl_elem_value *ucontrol)
4403 {
4404 printk("Audio_PGA2_Get = %d\n", mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP2]);
4405 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP2];
4406 return 0;
4407 }
4408
4409 static int Audio_PGA2_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4410 {
4411 int index = 0;
4412 printk("%s()\n", __func__);
4413 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(ADC_UL_PGA_GAIN))
4414 {
4415 printk("return -EINVAL\n");
4416 return -EINVAL;
4417 }
4418 index = ucontrol->value.integer.value[0];
4419 Ana_Set_Reg(AUDPREAMPGAIN_CFG0, index << 4, 0x0070);
4420 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP2] = ucontrol->value.integer.value[0];
4421 return 0;
4422 }
4423
4424
4425 static int Audio_PGA3_Get(struct snd_kcontrol *kcontrol,
4426 struct snd_ctl_elem_value *ucontrol)
4427 {
4428 printk("Audio_AmpR_Get = %d\n", mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP3]);
4429 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP3];
4430 return 0;
4431 }
4432
4433 static int Audio_PGA3_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4434 {
4435 int index = 0;
4436 printk("%s()\n", __func__);
4437 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(ADC_UL_PGA_GAIN))
4438 {
4439 printk("return -EINVAL\n");
4440 return -EINVAL;
4441 }
4442 index = ucontrol->value.integer.value[0];
4443 Ana_Set_Reg(AUDPREAMPGAIN_CFG0, index << 8, 0x0700);
4444 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP3] = ucontrol->value.integer.value[0];
4445 return 0;
4446 }
4447
4448 static int Audio_PGA4_Get(struct snd_kcontrol *kcontrol,
4449 struct snd_ctl_elem_value *ucontrol)
4450 {
4451 printk("Audio_AmpR_Get = %d \n", mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP4]);
4452 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP4];
4453 return 0;
4454 }
4455
4456 static int Audio_PGA4_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4457 {
4458 int index = 0;
4459 printk("%s()\n", __func__);
4460 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(ADC_UL_PGA_GAIN))
4461 {
4462 printk("return -EINVAL\n");
4463 return -EINVAL;
4464 }
4465 index = ucontrol->value.integer.value[0];
4466 Ana_Set_Reg(AUDPREAMPGAIN_CFG0, index << 12, 0x7000);
4467 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP4] = ucontrol->value.integer.value[0];
4468 return 0;
4469 }
4470
4471 static int Audio_MicSource1_Get(struct snd_kcontrol *kcontrol,
4472 struct snd_ctl_elem_value *ucontrol)
4473 {
4474 printk("Audio_MicSource1_Get = %d\n", mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1]);
4475 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1];
4476 return 0;
4477 }
4478
4479 static int Audio_MicSource1_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4480 {
4481 int index = 0;
4482 printk("%s()\n", __func__);
4483 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Pmic_Digital_Mux))
4484 {
4485 printk("return -EINVAL\n");
4486 return -EINVAL;
4487 }
4488 index = ucontrol->value.integer.value[0];
4489 printk("%s() index = %d done \n", __func__, index);
4490 Ana_Set_Reg(AFE_MIC_ARRAY_CFG, index | index << 8, 0x0303);
4491 mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] = ucontrol->value.integer.value[0];
4492 return 0;
4493 }
4494
4495 static int Audio_MicSource2_Get(struct snd_kcontrol *kcontrol,
4496 struct snd_ctl_elem_value *ucontrol)
4497 {
4498 printk("%s() = %d\n", __func__, mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_2]);
4499 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_2];
4500 return 0;
4501 }
4502
4503 static int Audio_MicSource2_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4504 {
4505 int index = 0;
4506 printk("%s()\n", __func__);
4507 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Pmic_Digital_Mux))
4508 {
4509 printk("return -EINVAL\n");
4510 return -EINVAL;
4511 }
4512 index = ucontrol->value.integer.value[0];
4513 printk("%s() done \n", __func__);
4514 Ana_Set_Reg(AFE_MIC_ARRAY_CFG, index << 2 | index << 10, 0x0c0c);
4515 mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_2] = ucontrol->value.integer.value[0];
4516 return 0;
4517 }
4518
4519 static int Audio_MicSource3_Get(struct snd_kcontrol *kcontrol,
4520 struct snd_ctl_elem_value *ucontrol)
4521 {
4522 printk("%s() = %d\n", __func__, mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_3]);
4523 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_3];
4524 return 0;
4525 }
4526
4527 static int Audio_MicSource3_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4528 {
4529 int index = 0;
4530 printk("%s()\n", __func__);
4531 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Pmic_Digital_Mux))
4532 {
4533 printk("return -EINVAL\n");
4534 return -EINVAL;
4535 }
4536 index = ucontrol->value.integer.value[0];
4537 printk("%s() done \n", __func__);
4538 Ana_Set_Reg(AFE_MIC_ARRAY_CFG, index << 4 | index << 12, 0x3030);
4539 mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_3] = ucontrol->value.integer.value[0];
4540 return 0;
4541 }
4542
4543
4544 static int Audio_MicSource4_Get(struct snd_kcontrol *kcontrol,
4545 struct snd_ctl_elem_value *ucontrol)
4546 {
4547 printk("%s() = %d\n", __func__, mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_4]);
4548 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_4];
4549 return 0;
4550 }
4551
4552 static int Audio_MicSource4_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4553 {
4554 int index = 0;
4555 printk("%s()\n", __func__);
4556 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Pmic_Digital_Mux))
4557 {
4558 printk("return -EINVAL\n");
4559 return -EINVAL;
4560 }
4561 index = ucontrol->value.integer.value[0];
4562 printk("%s() done \n", __func__);
4563 Ana_Set_Reg(AFE_MIC_ARRAY_CFG, index << 6 | index << 14, 0xc0c0);
4564 mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_4] = ucontrol->value.integer.value[0];
4565 return 0;
4566 }
4567
4568 // Mic ACC/DCC Mode Setting
4569 static int Audio_Mic1_Mode_Select_Get(struct snd_kcontrol *kcontrol,
4570 struct snd_ctl_elem_value *ucontrol)
4571 {
4572 printk("%s() mAudio_Analog_Mic1_mode = %d\n", __func__, mAudio_Analog_Mic1_mode);
4573 ucontrol->value.integer.value[0] = mAudio_Analog_Mic1_mode;
4574 return 0;
4575 }
4576
4577 static int Audio_Mic1_Mode_Select_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4578 {
4579 printk("%s()\n", __func__);
4580 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Audio_AnalogMic_Mode))
4581 {
4582 printk("return -EINVAL\n");
4583 return -EINVAL;
4584 }
4585 mAudio_Analog_Mic1_mode = ucontrol->value.integer.value[0];
4586 printk("%s() mAudio_Analog_Mic1_mode = %d \n", __func__, mAudio_Analog_Mic1_mode);
4587 return 0;
4588 }
4589
4590 static int Audio_Mic2_Mode_Select_Get(struct snd_kcontrol *kcontrol,
4591 struct snd_ctl_elem_value *ucontrol)
4592 {
4593 printk("%s() = %d\n", __func__, mAudio_Analog_Mic2_mode);
4594 ucontrol->value.integer.value[0] = mAudio_Analog_Mic2_mode;
4595 return 0;
4596 }
4597
4598 static int Audio_Mic2_Mode_Select_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4599 {
4600 printk("%s()\n", __func__);
4601 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Audio_AnalogMic_Mode))
4602 {
4603 printk("return -EINVAL\n");
4604 return -EINVAL;
4605 }
4606 mAudio_Analog_Mic2_mode = ucontrol->value.integer.value[0];
4607 printk("%s() mAudio_Analog_Mic1_mode = %d \n", __func__, mAudio_Analog_Mic2_mode);
4608 return 0;
4609 }
4610
4611
4612 static int Audio_Mic3_Mode_Select_Get(struct snd_kcontrol *kcontrol,
4613 struct snd_ctl_elem_value *ucontrol)
4614 {
4615 printk("%s() = %d\n", __func__, mAudio_Analog_Mic3_mode);
4616 ucontrol->value.integer.value[0] = mAudio_Analog_Mic3_mode;
4617 return 0;
4618 }
4619
4620 static int Audio_Mic3_Mode_Select_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4621 {
4622 printk("%s()\n", __func__);
4623 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Audio_AnalogMic_Mode))
4624 {
4625 printk("return -EINVAL\n");
4626 return -EINVAL;
4627 }
4628 mAudio_Analog_Mic3_mode = ucontrol->value.integer.value[0];
4629 printk("%s() mAudio_Analog_Mic1_mode = %d \n", __func__, mAudio_Analog_Mic3_mode);
4630 return 0;
4631 }
4632
4633 static int Audio_Mic4_Mode_Select_Get(struct snd_kcontrol *kcontrol,
4634 struct snd_ctl_elem_value *ucontrol)
4635 {
4636 printk("%s() = %d\n", __func__, mAudio_Analog_Mic4_mode);
4637 ucontrol->value.integer.value[0] = mAudio_Analog_Mic4_mode;
4638 return 0;
4639 }
4640
4641 static int Audio_Mic4_Mode_Select_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4642 {
4643 printk("%s()\n", __func__);
4644 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Audio_AnalogMic_Mode))
4645 {
4646 printk("return -EINVAL\n");
4647 return -EINVAL;
4648 }
4649 mAudio_Analog_Mic4_mode = ucontrol->value.integer.value[0];
4650 printk("%s() mAudio_Analog_Mic1_mode = %d \n", __func__, mAudio_Analog_Mic4_mode);
4651 return 0;
4652 }
4653
4654 static int Audio_Adc_Power_Mode_Get(struct snd_kcontrol *kcontrol,
4655 struct snd_ctl_elem_value *ucontrol)
4656 {
4657 printk("%s() = %d\n", __func__, mAdc_Power_Mode);
4658 ucontrol->value.integer.value[0] = mAdc_Power_Mode;
4659 return 0;
4660 }
4661
4662 static int Audio_Adc_Power_Mode_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4663 {
4664 printk("%s()\n", __func__);
4665 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(ADC_power_mode))
4666 {
4667 printk("return -EINVAL\n");
4668 return -EINVAL;
4669 }
4670 mAdc_Power_Mode = ucontrol->value.integer.value[0];
4671 printk("%s() mAudio_Analog_Mic1_mode = %d \n", __func__, mAdc_Power_Mode);
4672 return 0;
4673 }
4674
4675
4676 static int Audio_Vow_ADC_Func_Switch_Get(struct snd_kcontrol *kcontrol,
4677 struct snd_ctl_elem_value *ucontrol)
4678 {
4679 printk("%s() = %d\n", __func__, mAudio_Vow_Analog_Func_Enable);
4680 ucontrol->value.integer.value[0] = mAudio_Vow_Analog_Func_Enable;
4681 return 0;
4682 }
4683
4684 static int Audio_Vow_ADC_Func_Switch_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4685 {
4686 printk("%s()\n", __func__);
4687 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Audio_VOW_ADC_Function))
4688 {
4689 printk("return -EINVAL\n");
4690 return -EINVAL;
4691 }
4692
4693 if (ucontrol->value.integer.value[0])
4694 {
4695 TurnOnVOWADcPowerACC(AUDIO_ANALOG_DEVICE_IN_ADC1, true);
4696 }
4697 else
4698 {
4699 TurnOnVOWADcPowerACC(AUDIO_ANALOG_DEVICE_IN_ADC1, false);
4700 }
4701
4702 mAudio_Vow_Analog_Func_Enable = ucontrol->value.integer.value[0];
4703 printk("%s() mAudio_Analog_Mic1_mode = %d \n", __func__, mAudio_Vow_Analog_Func_Enable);
4704 return 0;
4705 }
4706
4707 static int Audio_Vow_Digital_Func_Switch_Get(struct snd_kcontrol *kcontrol,
4708 struct snd_ctl_elem_value *ucontrol)
4709 {
4710 printk("%s() = %d\n", __func__, mAudio_Vow_Digital_Func_Enable);
4711 ucontrol->value.integer.value[0] = mAudio_Vow_Digital_Func_Enable;
4712 return 0;
4713 }
4714
4715 static int Audio_Vow_Digital_Func_Switch_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4716 {
4717 printk("%s()\n", __func__);
4718 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Audio_VOW_Digital_Function))
4719 {
4720 printk("return -EINVAL\n");
4721 return -EINVAL;
4722 }
4723
4724 if (ucontrol->value.integer.value[0])
4725 {
4726 TurnOnVOWDigitalHW(true);
4727 }
4728 else
4729 {
4730 TurnOnVOWDigitalHW(false);
4731 }
4732
4733 mAudio_Vow_Digital_Func_Enable = ucontrol->value.integer.value[0];
4734 printk("%s() mAudio_Analog_Mic1_mode = %d \n", __func__, mAudio_Vow_Digital_Func_Enable);
4735 return 0;
4736 }
4737
4738
4739 static int Audio_Vow_Cfg0_Get(struct snd_kcontrol *kcontrol,
4740 struct snd_ctl_elem_value *ucontrol)
4741 {
4742 int value = /*Ana_Get_Reg(AFE_MAD_CFG0)*/reg_AFE_VOW_CFG0;
4743 printk("%s() = %d\n", __func__, value);
4744 ucontrol->value.integer.value[0] = value;
4745 return 0;
4746 }
4747
4748 static int Audio_Vow_Cfg0_Set(struct snd_kcontrol *kcontrol,
4749 struct snd_ctl_elem_value *ucontrol)
4750 {
4751 printk("%s() = %ld\n", __func__, ucontrol->value.integer.value[0]);
4752 //Ana_Set_Reg(AFE_MAD_CFG0, ucontrol->value.integer.value[0], 0xffff);
4753 reg_AFE_VOW_CFG0 = ucontrol->value.integer.value[0];
4754 return 0;
4755 }
4756
4757 static int Audio_Vow_Cfg1_Get(struct snd_kcontrol *kcontrol,
4758 struct snd_ctl_elem_value *ucontrol)
4759 {
4760 int value = /*Ana_Get_Reg(AFE_MAD_CFG1)*/reg_AFE_VOW_CFG1;
4761 printk("%s() = %d\n", __func__, value);
4762 ucontrol->value.integer.value[0] = value;
4763 return 0;
4764 }
4765
4766 static int Audio_Vow_Cfg1_Set(struct snd_kcontrol *kcontrol,
4767 struct snd_ctl_elem_value *ucontrol)
4768 {
4769 printk("%s() = %ld\n", __func__, ucontrol->value.integer.value[0]);
4770 //Ana_Set_Reg(AFE_MAD_CFG1, ucontrol->value.integer.value[0], 0xffff);
4771 reg_AFE_VOW_CFG1 = ucontrol->value.integer.value[0];
4772 return 0;
4773 }
4774
4775 static int Audio_Vow_Cfg2_Get(struct snd_kcontrol *kcontrol,
4776 struct snd_ctl_elem_value *ucontrol)
4777 {
4778 int value = /*Ana_Get_Reg(AFE_MAD_CFG2)*/reg_AFE_VOW_CFG2;
4779 printk("%s() = %d\n", __func__, value);
4780 ucontrol->value.integer.value[0] = value;
4781 return 0;
4782 }
4783
4784 static int Audio_Vow_Cfg2_Set(struct snd_kcontrol *kcontrol,
4785 struct snd_ctl_elem_value *ucontrol)
4786 {
4787 printk("%s() = %ld\n", __func__, ucontrol->value.integer.value[0]);
4788 //Ana_Set_Reg(AFE_MAD_CFG2, ucontrol->value.integer.value[0], 0xffff);
4789 reg_AFE_VOW_CFG2 = ucontrol->value.integer.value[0];
4790 return 0;
4791 }
4792
4793 static int Audio_Vow_Cfg3_Get(struct snd_kcontrol *kcontrol,
4794 struct snd_ctl_elem_value *ucontrol)
4795 {
4796 int value = /*Ana_Get_Reg(AFE_MAD_CFG3)*/reg_AFE_VOW_CFG3;
4797 printk("%s() = %d\n", __func__, value);
4798 ucontrol->value.integer.value[0] = value;
4799 return 0;
4800 }
4801
4802 static int Audio_Vow_Cfg3_Set(struct snd_kcontrol *kcontrol,
4803 struct snd_ctl_elem_value *ucontrol)
4804 {
4805 printk("%s() = %ld\n", __func__, ucontrol->value.integer.value[0]);
4806 //Ana_Set_Reg(AFE_MAD_CFG3, ucontrol->value.integer.value[0], 0xffff);
4807 reg_AFE_VOW_CFG3 = ucontrol->value.integer.value[0];
4808 return 0;
4809 }
4810
4811 static int Audio_Vow_Cfg4_Get(struct snd_kcontrol *kcontrol,
4812 struct snd_ctl_elem_value *ucontrol)
4813 {
4814 int value = /*Ana_Get_Reg(AFE_MAD_CFG4)*/reg_AFE_VOW_CFG4;
4815 printk("%s() = %d\n", __func__, value);
4816 ucontrol->value.integer.value[0] = value;
4817 return 0;
4818 }
4819
4820 static int Audio_Vow_Cfg4_Set(struct snd_kcontrol *kcontrol,
4821 struct snd_ctl_elem_value *ucontrol)
4822 {
4823 printk("%s() = %ld\n", __func__, ucontrol->value.integer.value[0]);
4824 //Ana_Set_Reg(AFE_MAD_CFG4, ucontrol->value.integer.value[0], 0xffff);
4825 reg_AFE_VOW_CFG4 = ucontrol->value.integer.value[0];
4826 return 0;
4827 }
4828
4829 static int Audio_Vow_Cfg5_Get(struct snd_kcontrol *kcontrol,
4830 struct snd_ctl_elem_value *ucontrol)
4831 {
4832 int value = /*Ana_Get_Reg(AFE_MAD_CFG5)*/reg_AFE_VOW_CFG5;
4833 printk("%s() = %d\n", __func__, value);
4834 ucontrol->value.integer.value[0] = value;
4835 return 0;
4836 }
4837
4838 static int Audio_Vow_Cfg5_Set(struct snd_kcontrol *kcontrol,
4839 struct snd_ctl_elem_value *ucontrol)
4840 {
4841 printk("%s() = %ld\n", __func__, ucontrol->value.integer.value[0]);
4842 //Ana_Set_Reg(AFE_MAD_CFG5, ucontrol->value.integer.value[0], 0xffff);
4843 reg_AFE_VOW_CFG5 = ucontrol->value.integer.value[0];
4844 return 0;
4845 }
4846
4847
4848 static bool SineTable_DAC_HP_flag = false;
4849 static bool SineTable_UL2_flag = false;
4850
4851 static int SineTable_UL2_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4852 {
4853 if (ucontrol->value.integer.value[0])
4854 {
4855 Ana_Set_Reg(PMIC_AFE_TOP_CON0 , 0x0002 , 0x2); //set DL sine gen table
4856 Ana_Set_Reg(AFE_SGEN_CFG0 , 0x0080 , 0xffffffff);
4857 Ana_Set_Reg(AFE_SGEN_CFG1 , 0x0101 , 0xffffffff);
4858 }
4859 else
4860 {
4861 Ana_Set_Reg(PMIC_AFE_TOP_CON0 , 0x0002 , 0x2); //set DL sine gen table
4862 Ana_Set_Reg(AFE_SGEN_CFG0 , 0x0000 , 0xffffffff);
4863 Ana_Set_Reg(AFE_SGEN_CFG1 , 0x0101 , 0xffffffff);
4864 }
4865 return 0;
4866 }
4867
4868 static int SineTable_UL2_Get(struct snd_kcontrol *kcontrol,
4869 struct snd_ctl_elem_value *ucontrol)
4870 {
4871 printk("%s()\n", __func__);
4872 ucontrol->value.integer.value[0] = SineTable_UL2_flag;
4873 return 0;
4874 }
4875
4876 static int SineTable_DAC_HP_Get(struct snd_kcontrol *kcontrol,
4877 struct snd_ctl_elem_value *ucontrol)
4878 {
4879 printk("%s()\n", __func__);
4880 ucontrol->value.integer.value[0] = SineTable_DAC_HP_flag;
4881 return 0;
4882 }
4883
4884 static int SineTable_DAC_HP_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4885 {
4886 printk("%s()\n", __func__);
4887 if (ucontrol->value.integer.value[0])
4888 {
4889 SineTable_DAC_HP_flag = ucontrol->value.integer.value[0];
4890 printk("TurnOnDacPower\n");
4891 audckbufEnable(true);
4892 ClsqEnable(true);
4893 Topck_Enable(true);
4894 NvregEnable(true);
4895 Ana_Set_Reg(AFUNC_AUD_CON2, 0x0006, 0xffffffff);
4896 Ana_Set_Reg(AFUNC_AUD_CON0, 0xc3a1, 0xffffffff); //sdm audio fifo clock power on
4897 Ana_Set_Reg(AFUNC_AUD_CON2, 0x0003, 0xffffffff); //sdm power on
4898 Ana_Set_Reg(AFUNC_AUD_CON2, 0x000b, 0xffffffff); //sdm fifo enable
4899 Ana_Set_Reg(AFE_DL_SDM_CON1, 0x001e, 0xffffffff); //set attenuation gain
4900 Ana_Set_Reg(AFE_UL_DL_CON0 , 0x0001, 0xffffffff); //[0] afe enable
4901
4902 Ana_Set_Reg(AFE_PMIC_NEWIF_CFG0 , 0x8330 , 0xffffffff);
4903 Ana_Set_Reg(AFE_DL_SRC2_CON0_H , 0x8330, 0xffff000f);
4904
4905 Ana_Set_Reg(AFE_DL_SRC2_CON0_L , 0x1801 , 0xffffffff); //turn off mute function and turn on dl
4906 Ana_Set_Reg(PMIC_AFE_TOP_CON0 , 0x0001 , 0xffffffff); //set DL sine gen table
4907 Ana_Set_Reg(AFE_SGEN_CFG0 , 0x0080 , 0xffffffff);
4908 Ana_Set_Reg(AFE_SGEN_CFG1 , 0x0101 , 0xffffffff);
4909
4910 Ana_Set_Reg(0x0680, 0x0000, 0xffff); // Enable AUDGLB
4911 OpenClassAB();
4912 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0028, 0xffff); // Enable cap-less LDOs (1.6V)
4913 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0068, 0xffff); // Enable NV regulator (-1.6V)
4914 Ana_Set_Reg(AUDBUF_CFG5, 0x001f, 0xffff); // enable HP bias circuits
4915 Ana_Set_Reg(ZCD_CON0, 0x0700, 0xffff); // Disable AUD_ZCD
4916 Ana_Set_Reg(AUDBUF_CFG0, 0xE008, 0xffff); // Disable headphone, voice and short-ckt protection.
4917 Ana_Set_Reg(IBIASDIST_CFG0, 0x0092, 0xffff); //Enable IBIST
4918 Ana_Set_Reg(ZCD_CON2, 0x0F9F , 0xffff); //Set HPR/HPL gain as minimum (~ -40dB)
4919 Ana_Set_Reg(ZCD_CON3, 0x001F , 0xffff); //Set voice gain as minimum (~ -40dB)
4920 Ana_Set_Reg(AUDBUF_CFG1, 0x0900 , 0xffff); //De_OSC of HP and enable output STBENH
4921 Ana_Set_Reg(AUDBUF_CFG2, 0x0022 , 0xffff); //De_OSC of voice, enable output STBENH
4922 Ana_Set_Reg(AUDBUF_CFG0, 0xE009 , 0xffff); //Enable voice driver
4923 Ana_Set_Reg(AUDBUF_CFG1, 0x0940 , 0xffff); //Enable pre-charge buffer
4924 msleep(1);
4925 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5501 , 0xffff); //Enable AUD_CLK
4926 Ana_Set_Reg(AUDDAC_CFG0, 0x000f , 0xffff); //Enable Audio DAC
4927 SetDcCompenSation();
4928
4929 Ana_Set_Reg(AUDBUF_CFG0, 0xE149 , 0xffff); // Switch HP MUX to audio DAC
4930 Ana_Set_Reg(AUDBUF_CFG0, 0xE14F , 0xffff); // Enable HPR/HPL
4931 Ana_Set_Reg(AUDBUF_CFG1, 0x0900 , 0xffff); // Disable pre-charge buffer
4932 Ana_Set_Reg(AUDBUF_CFG2, 0x0020 , 0xffff); // Disable De_OSC of voice
4933 Ana_Set_Reg(AUDBUF_CFG0, 0xE14E , 0xffff); // Disable voice buffer
4934 Ana_Set_Reg(ZCD_CON2, 0x0489 , 0xffff); // Set HPR/HPL gain as 0dB, step by step
4935
4936 }
4937 else
4938 {
4939 SineTable_DAC_HP_flag = ucontrol->value.integer.value[0];
4940 if (GetDLStatus() == false)
4941 {
4942 Ana_Set_Reg(AUDBUF_CFG0, 0xE149, 0xffff); // Disable HPR/HPL
4943 Ana_Set_Reg(AUDDAC_CFG0, 0x0000, 0xffff); // Disable Audio DAC
4944 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5500, 0xffff); // Disable AUD_CLK
4945 Ana_Set_Reg(IBIASDIST_CFG0, 0x0192, 0xffff); // Disable IBIST
4946 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0028, 0xffff); // Disable NV regulator (-1.6V)
4947 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0000, 0xffff); // Disable cap-less LDOs (1.6V)
4948 Ana_Set_Reg(AFE_CLASSH_CFG0, 0xd518, 0xffff); // ClassH off
4949 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0518, 0xffff); // NCP offset
4950 Ana_Set_Reg(PMIC_AFE_TOP_CON0 , 0x0000 , 0xffffffff); //set DL normal
4951 }
4952 }
4953 return 0;
4954 }
4955
4956 static void ADC_LOOP_DAC_Func(int command)
4957 {
4958 if (command == AUDIO_ANALOG_DAC_LOOP_DAC_HS_ON || command == AUDIO_ANALOG_DAC_LOOP_DAC_HP_ON)
4959 {
4960 audckbufEnable(true);
4961 ClsqEnable(true);
4962 Topck_Enable(true);
4963 NvregEnable(true);
4964 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0000, 0xffff); //power on clock
4965 Ana_Set_Reg(AUDADC_CFG0, 0x0400, 0xffff); // Enable ADC CLK
4966
4967 //Ana_Set_Reg(AUDMICBIAS_CFG0, 0x78F, 0xffff); //Enable MICBIAS0,1 (2.7V)
4968 OpenMicbias1(true);
4969 SetMicbias1lowpower(false);
4970 OpenMicbias0(true);
4971 SetMicbias0lowpower(false);
4972
4973 Ana_Set_Reg(AUDMICBIAS_CFG1, 0x285, 0xffff); //Enable MICBIAS2,3 (2.7V)
4974 Ana_Set_Reg(AUDLDO_NVREG_CFG1, 0x0007, 0xffff); //Enable LCLDO18_ENC (1.8V), Remote-Sense
4975 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x2277, 0xffff); //Enable LCLDO19_ADCCH0_1, Remote-Sense
4976 Ana_Set_Reg(AUDPREAMPGAIN_CFG0, 0x0022, 0xffff); //Set PGA CH0_1 gain = 12dB
4977 SetMicPGAGain();
4978 Ana_Set_Reg(AUDPREAMP_CFG0, 0x0051, 0xffff); //Enable PGA CH0_1 (CH0 in)
4979 Ana_Set_Reg(AUDPREAMP_CFG1, 0x0055, 0xffff); //Enable ADC CH0_1 (PGA in)
4980
4981 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0x0000, 0xffffffff); //power on ADC clk
4982 Ana_Set_Reg(AFE_TOP_CON0, 0x4000, 0xffffffff); //AFE[14] loopback test1 ( UL tx sdata to DL rx)
4983 Ana_Set_Reg(AFUNC_AUD_CON2, 0x0006, 0xffffffff);
4984 Ana_Set_Reg(AFUNC_AUD_CON0, 0xc3a1, 0xffffffff); //sdm audio fifo clock power on
4985 Ana_Set_Reg(AFUNC_AUD_CON2, 0x0003, 0xffffffff); //sdm power on
4986 Ana_Set_Reg(AFUNC_AUD_CON2, 0x000b, 0xffffffff); //sdm fifo enable
4987 Ana_Set_Reg(AFE_DL_SDM_CON1, 0x001e, 0xffffffff); //set attenuation gain
4988 Ana_Set_Reg(AFE_UL_DL_CON0 , 0x0001, 0xffffffff); //[0] afe enable
4989
4990 Ana_Set_Reg(AFE_UL_SRC0_CON0_H, 0x0000 , 0x0010); // UL1
4991
4992 Ana_Set_Reg(AFE_UL_SRC0_CON0_L, 0x0001, 0xffff); //power on uplink
4993 Ana_Set_Reg(AFE_PMIC_NEWIF_CFG0, 0x0380, 0xffff); //MTKIF
4994 Ana_Set_Reg(AFE_DL_SRC2_CON0_H, 0x0800, 0xffff); //DL
4995 Ana_Set_Reg(AFE_DL_SRC2_CON0_L, 0x0001, 0xffff); //DL
4996
4997 // here to start analog part
4998 //Ana_Set_Reg(AUDNVREGGLB_CFG0, 0x0000, 0xffff); //Enable AUDGLB
4999 OpenClassAB();
5000
5001 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0028, 0xffff); // Enable cap-less LDOs (1.6V)
5002 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0068, 0xffff); // Enable NV regulator (-1.6V)
5003 Ana_Set_Reg(AUDBUF_CFG5, 0x001f, 0xffff); // enable HP bias circuits
5004 Ana_Set_Reg(ZCD_CON0, 0x0700, 0xffff); // Disable AUD_ZCD
5005 Ana_Set_Reg(AUDBUF_CFG0, 0xE008, 0xffff); // Disable headphone, voice and short-ckt protection.
5006 Ana_Set_Reg(IBIASDIST_CFG0, 0x0092, 0xffff); //Enable IBIST
5007 if (command == AUDIO_ANALOG_DAC_LOOP_DAC_HS_ON)
5008 {
5009 Ana_Set_Reg(ZCD_CON3, 0x001f , 0xffff); //Set voice gain as minimum (~ -40dB)
5010 Ana_Set_Reg(AUDBUF_CFG2, 0x0022 , 0xffff); //De_OSC of voice, enable output STBENH
5011 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5501 , 0xffff); //Enable AUD_CLK
5012 Ana_Set_Reg(AUDDAC_CFG0, 0x0009 , 0xffff); //Enable Audio DAC
5013 SetDcCompenSation();
5014
5015 Ana_Set_Reg(AUDBUF_CFG0, 0xE010 , 0xffff); // Switch HP MUX to audio DAC
5016 Ana_Set_Reg(AUDBUF_CFG0, 0xE011 , 0xffff); // Enable HPR/HPL
5017 Ana_Set_Reg(ZCD_CON3, 0x0009 , 0xffff); // Set HPR/HPL gain as 0dB, step by step
5018 }
5019 else if (command == AUDIO_ANALOG_DAC_LOOP_DAC_HP_ON)
5020 {
5021 Ana_Set_Reg(ZCD_CON2, 0x0F9F , 0xffff); //Set HPR/HPL gain as minimum (~ -40dB)
5022 Ana_Set_Reg(ZCD_CON3, 0x001f , 0xffff); //Set voice gain as minimum (~ -40dB)
5023 Ana_Set_Reg(AUDBUF_CFG1, 0x0900 , 0xffff); //De_OSC of HP and enable output STBENH
5024 Ana_Set_Reg(AUDBUF_CFG2, 0x0022 , 0xffff); //De_OSC of voice, enable output STBENH
5025 Ana_Set_Reg(AUDBUF_CFG0, 0xE009 , 0xffff); //Enable voice driver
5026 Ana_Set_Reg(AUDBUF_CFG1, 0x0940 , 0xffff); //De_OSC of HP and enable output STBENH
5027 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5501 , 0xffff); //Enable AUD_CLK
5028 Ana_Set_Reg(AUDDAC_CFG0, 0x000F , 0xffff); //Enable Audio DAC
5029 SetDcCompenSation();
5030
5031 Ana_Set_Reg(AUDBUF_CFG0, 0xE149 , 0xffff); // Switch HP MUX to audio DAC
5032 Ana_Set_Reg(AUDBUF_CFG0, 0xE14F , 0xffff); // Enable HPR/HPL
5033 Ana_Set_Reg(AUDBUF_CFG1, 0x0900 , 0xffff); // Enable HPR/HPL
5034 Ana_Set_Reg(AUDBUF_CFG2, 0x0020 , 0xffff); // Enable HPR/HPL
5035 Ana_Set_Reg(AUDBUF_CFG0, 0xE14E , 0xffff); // Enable HPR/HPL
5036 Ana_Set_Reg(ZCD_CON2, 0x0489 , 0xffff); // Set HPR/HPL gain as 0dB, step by step
5037 }
5038 }
5039 else
5040 {
5041 if (command == AUDIO_ANALOG_DAC_LOOP_DAC_HS_ON)
5042 {
5043 Ana_Set_Reg(AUDBUF_CFG0, 0xe010 , 0xffff); // Disable voice driver
5044 Ana_Set_Reg(AUDDAC_CFG0, 0x0000, 0xffff); // Disable L-ch Audio DAC
5045 }
5046 else if (command == AUDIO_ANALOG_DAC_LOOP_DAC_HP_ON)
5047 {
5048 Ana_Set_Reg(AUDBUF_CFG0, 0xE149 , 0xffff); // Disable voice DRIVERMODE_CODEC_ONLY
5049 Ana_Set_Reg(AUDDAC_CFG0, 0x0000, 0xffff); // Disable L-ch Audio DAC
5050 }
5051 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5500, 0xffff); // Disable AUD_CLK
5052 Ana_Set_Reg(IBIASDIST_CFG0, 0x0192, 0xffff); //Disable IBIST
5053 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0028, 0xffff); //Disable NV regulator (-1.6V)
5054 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0000, 0xffff); //Disable cap-less LDOs (1.6V)
5055 Ana_Set_Reg(AFE_CLASSH_CFG0, 0xd518, 0xffff); // ClassH offset
5056 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0518, 0xffff); // NCP offset
5057 }
5058 }
5059
5060 static bool DAC_LOOP_DAC_HS_flag = false;
5061 static int ADC_LOOP_DAC_HS_Get(struct snd_kcontrol *kcontrol,
5062 struct snd_ctl_elem_value *ucontrol)
5063 {
5064 printk("%s()\n", __func__);
5065 ucontrol->value.integer.value[0] = DAC_LOOP_DAC_HS_flag;
5066 return 0;
5067 }
5068
5069 static int ADC_LOOP_DAC_HS_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
5070 {
5071 printk("%s()\n", __func__);
5072 if (ucontrol->value.integer.value[0])
5073 {
5074 DAC_LOOP_DAC_HS_flag = ucontrol->value.integer.value[0];
5075 ADC_LOOP_DAC_Func(AUDIO_ANALOG_DAC_LOOP_DAC_HS_ON);
5076 }
5077 else
5078 {
5079 DAC_LOOP_DAC_HS_flag = ucontrol->value.integer.value[0];
5080 ADC_LOOP_DAC_Func(AUDIO_ANALOG_DAC_LOOP_DAC_HS_OFF);
5081 }
5082 return 0;
5083 }
5084
5085 static bool DAC_LOOP_DAC_HP_flag = false;
5086 static int ADC_LOOP_DAC_HP_Get(struct snd_kcontrol *kcontrol,
5087 struct snd_ctl_elem_value *ucontrol)
5088 {
5089 printk("%s()\n", __func__);
5090 ucontrol->value.integer.value[0] = DAC_LOOP_DAC_HP_flag;
5091 return 0;
5092 }
5093
5094 static int ADC_LOOP_DAC_HP_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
5095 {
5096
5097 printk("%s()\n", __func__);
5098 if (ucontrol->value.integer.value[0])
5099 {
5100 DAC_LOOP_DAC_HP_flag = ucontrol->value.integer.value[0];
5101 ADC_LOOP_DAC_Func(AUDIO_ANALOG_DAC_LOOP_DAC_HP_ON);
5102 }
5103 else
5104 {
5105 DAC_LOOP_DAC_HP_flag = ucontrol->value.integer.value[0];
5106 ADC_LOOP_DAC_Func(AUDIO_ANALOG_DAC_LOOP_DAC_HP_OFF);
5107 }
5108 return 0;
5109 }
5110
5111 static bool Voice_Call_DAC_DAC_HS_flag = false;
5112 static int Voice_Call_DAC_DAC_HS_Get(struct snd_kcontrol *kcontrol,
5113 struct snd_ctl_elem_value *ucontrol)
5114 {
5115 printk("%s()\n", __func__);
5116 ucontrol->value.integer.value[0] = Voice_Call_DAC_DAC_HS_flag;
5117 return 0;
5118 }
5119
5120 static int Voice_Call_DAC_DAC_HS_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
5121 {
5122 printk("%s()\n", __func__);
5123 if (ucontrol->value.integer.value[0])
5124 {
5125 Voice_Call_DAC_DAC_HS_flag = ucontrol->value.integer.value[0];
5126 // here to set voice call 16L setting...
5127 Ana_Set_Reg(AUDNVREGGLB_CFG0, 0x0000 , 0xffff); // RG_AUDGLB_PWRDN_VA32 = 1'b0
5128 Ana_Set_Reg(TOP_CLKSQ, 0x0001, 0xffff); // CKSQ Enable
5129 Ana_Set_Reg(AUDADC_CFG0, 0x0400, 0xffff); // Enable ADC CLK26CALI
5130 //Ana_Set_Reg(AUDMICBIAS_CFG0, 0x78f, 0xffff); // Enable MICBIAS0 (2.7V)
5131 OpenMicbias1(true);
5132 SetMicbias1lowpower(false);
5133 OpenMicbias0(true);
5134 SetMicbias0lowpower(false);
5135
5136 Ana_Set_Reg(AUDMICBIAS_CFG1, 0x285, 0xffff); // Enable MICBIAS2 (2.7V)
5137 Ana_Set_Reg(AUDLDO_NVREG_CFG1, 0x0007, 0xffff); // Enable LCLDO18_ENC (1.8V), Remote-Sense ; Set LCLDO19_ADC voltage 1.9V
5138 Ana_Set_Reg(AUDLDO_NVREG_CFG2, 0x2277, 0xffff); // Enable LCLDO19_ADCCH0_1, Remote-Sense ; Enable LCLDO19_ADCCH_2, Remote-Sense
5139 Ana_Set_Reg(AUDPREAMPGAIN_CFG0, 0x033, 0xffff); // Set PGA CH0_1 gain = 18dB ; Set PGA CH_2 gain = 18dB
5140 SetMicPGAGain();
5141 Ana_Set_Reg(AUDPREAMP_CFG0, 0x051, 0xffff); // Enable PGA CH0_1 (CH0 in) ; Enable PGA CH_2
5142 Ana_Set_Reg(AUDPREAMP_CFG1, 0x055, 0xffff); // Enable ADC CH0_1 (PGA in) ; Enable ADC CH_2 (PGA in)
5143
5144 Ana_Set_Reg(TOP_CLKSQ_SET, 0x0003, 0xffff); //CKSQ Enable
5145 Ana_Set_Reg(TOP_CKPDN_CON0_CLR, 0x3000, 0xffff); //AUD clock power down released
5146 Ana_Set_Reg(TOP_CKSEL_CON_CLR, 0x0001, 0x0001); //use internal 26M
5147
5148 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0000, 0xffff); //power on clock
5149
5150 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0x0000, 0xffff); // power on ADC clk
5151 Ana_Set_Reg(AFUNC_AUD_CON2, 0x0006, 0xffff); // sdm audio fifo clock power on
5152 Ana_Set_Reg(AFUNC_AUD_CON0, 0xc3a1, 0xffff); // scrambler clock on enable
5153 Ana_Set_Reg(AFUNC_AUD_CON2, 0x0003, 0xffff); // sdm power on
5154 Ana_Set_Reg(AFUNC_AUD_CON2, 0x000b, 0xffff); // sdm fifo enable
5155 Ana_Set_Reg(AFE_DL_SDM_CON1, 0x001e, 0xffff); // set attenuation gain
5156 Ana_Set_Reg(AFE_UL_DL_CON0, 0x0001, 0xffff); // afe enable
5157 Ana_Set_Reg(AFE_PMIC_NEWIF_CFG0, 0x3330, 0xffff); //time slot1= 47, time slot2=24 @ 384K interval.
5158 Ana_Set_Reg(AFE_DL_SRC2_CON0_H, 0x3330, 0xffff); //16k samplerate
5159 Ana_Set_Reg(AFE_DL_SRC2_CON0_L, 0x1801, 0xffff); //turn off mute function and turn on dl
5160 Ana_Set_Reg(AFE_UL_SRC0_CON0_H, 0x000a, 0xffff); //UL1
5161 Ana_Set_Reg(AFE_UL_SRC0_CON0_L, 0x0001, 0xffff); //power on uplink
5162
5163 //============sine gen table============
5164 Ana_Set_Reg(PMIC_AFE_TOP_CON0, 0x0000, 0xffff); //no loopback
5165 Ana_Set_Reg(AFE_SGEN_CFG0, 0x0080, 0xffff); //L/R-ch @ sample rate = 8*8K for tone = 0dB of 1K Hz example.
5166 Ana_Set_Reg(AFE_SGEN_CFG1, 0x0101, 0xffff); //L/R-ch @ sample rate = 8*8K for tone = 0dB of 1K Hz example.
5167
5168 // ======================here set analog part (audio HP playback)=========================
5169 Ana_Set_Reg(AUDNVREGGLB_CFG0, 0x0000, 0xffff); // [0] RG_AUDGLB_PWRDN_VA32 = 1'b0
5170
5171 Ana_Set_Reg(AFE_CLASSH_CFG7, 0x8909, 0xffff); // Classh CK fix 591KHz
5172 Ana_Set_Reg(AFE_CLASSH_CFG8, 0x0d0d, 0xffff); // Classh CK fix 591KHz
5173 Ana_Set_Reg(AFE_CLASSH_CFG9, 0x0d10, 0xffff); // Classh CK fix 591KHz
5174 Ana_Set_Reg(AFE_CLASSH_CFG10, 0x1010, 0xffff); // Classh CK fix 591KHz
5175 Ana_Set_Reg(AFE_CLASSH_CFG11, 0x1010, 0xffff); // Classh CK fix 591KHz
5176 Ana_Set_Reg(AFE_CLASSH_CFG12, 0x0000, 0xffff); // Classh CK fix 591KHz
5177 Ana_Set_Reg(AFE_CLASSH_CFG13, 0x0000, 0xffff); // Classh CK fix 591KHz
5178 Ana_Set_Reg(AFE_CLASSH_CFG14, 0x009c, 0xffff); // Classh CK fix 591KHz
5179 Ana_Set_Reg(AFE_CLASSH_CFG26, 0x8d0d, 0xffff); // Classh CK fix 591KHz
5180 Ana_Set_Reg(AFE_CLASSH_CFG27, 0x0d0d, 0xffff); // Classh CK fix 591KHz
5181 Ana_Set_Reg(AFE_CLASSH_CFG28, 0x0d10, 0xffff); // Classh CK fix 591KHz
5182 Ana_Set_Reg(AFE_CLASSH_CFG29, 0x1010, 0xffff); // Classh CK fix 591KHz
5183 Ana_Set_Reg(AFE_CLASSH_CFG30, 0x1010, 0xffff); // Classh CK fix 591KHz
5184 Ana_Set_Reg(AFE_CLASSH_CFG1, 0x0024, 0xffff); // Classh CK fix 591KHz
5185 Ana_Set_Reg(AFE_CLASSH_CFG2, 0x2f90, 0xffff); // Classh CK fix 591KHz
5186 Ana_Set_Reg(AFE_CLASSH_CFG3, 0x1104, 0xffff); // Classh CK fix 591KHz
5187 Ana_Set_Reg(AFE_CLASSH_CFG4, 0x2412, 0xffff); // Classh CK fix 591KHz
5188 Ana_Set_Reg(AFE_CLASSH_CFG5, 0x0201, 0xffff); // Classh CK fix 591KHz
5189 Ana_Set_Reg(AFE_CLASSH_CFG6, 0x2800, 0xffff); // Classh CK fix 591KHz
5190 Ana_Set_Reg(AFE_CLASSH_CFG21, 0xa108, 0xffff); // Classh CK fix 591KHz
5191 Ana_Set_Reg(AFE_CLASSH_CFG22, 0x06db, 0xffff); // Classh CK fix 591KHz
5192 Ana_Set_Reg(AFE_CLASSH_CFG23, 0x0bd6, 0xffff); // Classh CK fix 591KHz
5193 Ana_Set_Reg(AFE_CLASSH_CFG24, 0x1492, 0xffff); // Classh CK fix 591KHz
5194 Ana_Set_Reg(AFE_CLASSH_CFG25, 0x1740, 0xffff); // Classh CK fix 591KHz
5195 Ana_Set_Reg(AFE_CLASSH_CFG0, 0xd518, 0xffff); // Classh CK fix 591KHz
5196 msleep(1);
5197 Ana_Set_Reg(AFE_CLASSH_CFG0, 0xd419, 0xffff); // Classh CK fix 591KHz
5198 msleep(1);
5199 Ana_Set_Reg(AFE_CLASSH_CFG1, 0x0021, 0xffff); // Classh CK fix 591KHz
5200 msleep(1);
5201
5202 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0028, 0xffff); // Enable cap-less LDOs (1.6V)
5203 Ana_Set_Reg(AUDLDO_NVREG_CFG0, 0x0068, 0xffff); // Enable NV regulator (-1.6V)
5204 Ana_Set_Reg(AUDBUF_CFG5, 0x001f, 0xffff); // enable HP bias circuits
5205 Ana_Set_Reg(ZCD_CON0, 0x0700, 0xffff); // Disable AUD_ZCD
5206 Ana_Set_Reg(AUDBUF_CFG0, 0xE008, 0xffff); // Disable headphone, voice and short-ckt protection.
5207 Ana_Set_Reg(IBIASDIST_CFG0, 0x0092, 0xffff); //Enable IBIST
5208
5209 Ana_Set_Reg(ZCD_CON2, 0x0F9F , 0xffff); //Set HPR/HPL gain as minimum (~ -40dB)
5210 Ana_Set_Reg(ZCD_CON3, 0x001f , 0xffff); //Set voice gain as minimum (~ -40dB)
5211 Ana_Set_Reg(AUDBUF_CFG1, 0x0900 , 0xffff); //De_OSC of HP and enable output STBENH
5212 Ana_Set_Reg(AUDBUF_CFG2, 0x0022 , 0xffff); //De_OSC of voice, enable output STBENH
5213 Ana_Set_Reg(AUDBUF_CFG0, 0xE009 , 0xffff); //Enable voice driver
5214 Ana_Set_Reg(AUDBUF_CFG1, 0x0940 , 0xffff); //De_OSC of HP and enable output STBENH
5215 Ana_Set_Reg(AUDCLKGEN_CFG0, 0x5501 , 0xffff); //Enable AUD_CLK
5216 Ana_Set_Reg(AUDDAC_CFG0, 0x000F , 0xffff); //Enable Audio DAC
5217 SetDcCompenSation();
5218
5219 Ana_Set_Reg(AUDBUF_CFG0, 0xE010 , 0xffff); // Switch HP MUX to audio DAC
5220 Ana_Set_Reg(AUDBUF_CFG0, 0xE011 , 0xffff);
5221 Ana_Set_Reg(AUDBUF_CFG1, 0x0900 , 0xffff);
5222 Ana_Set_Reg(AUDBUF_CFG2, 0x0020 , 0xffff);
5223 //Ana_Set_Reg(AUDBUF_CFG0, 0xE146 , 0xffff); // Enable HPR/HPL
5224 Ana_Set_Reg(ZCD_CON2, 0x0489 , 0xffff); // Set HPR/HPL gain as 0dB, step by step
5225 Ana_Set_Reg(ZCD_CON3, 0x0489 , 0xffff); // Set HPR/HPL gain as 0dB, step by step
5226
5227 //Phone_Call_16k_Vioce_mode_DL_UL
5228
5229 }
5230 else
5231 {
5232 Voice_Call_DAC_DAC_HS_flag = ucontrol->value.integer.value[0];
5233 }
5234 return 0;
5235 }
5236
5237
5238 /*static bool GetLoopbackStatus(void)
5239 {
5240 printk("%s DAC_LOOP_DAC_HP_flag = %d DAC_LOOP_DAC_HP_flag = %d \n", __func__, DAC_LOOP_DAC_HP_flag, DAC_LOOP_DAC_HP_flag);
5241 return (DAC_LOOP_DAC_HP_flag || DAC_LOOP_DAC_HP_flag);
5242 }*/
5243
5244
5245 // here start uplink power function
5246 static const char *Pmic_Test_function[] = {"Off", "On"};
5247
5248 static const struct soc_enum Pmic_Test_Enum[] =
5249 {
5250 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Test_function), Pmic_Test_function),
5251 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Test_function), Pmic_Test_function),
5252 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Test_function), Pmic_Test_function),
5253 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Test_function), Pmic_Test_function),
5254 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Test_function), Pmic_Test_function),
5255 };
5256
5257 static const struct snd_kcontrol_new mt6331_pmic_Test_controls[] =
5258 {
5259 SOC_ENUM_EXT("SineTable_DAC_HP", Pmic_Test_Enum[0], SineTable_DAC_HP_Get, SineTable_DAC_HP_Set),
5260 SOC_ENUM_EXT("DAC_LOOP_DAC_HS", Pmic_Test_Enum[1], ADC_LOOP_DAC_HS_Get, ADC_LOOP_DAC_HS_Set),
5261 SOC_ENUM_EXT("DAC_LOOP_DAC_HP", Pmic_Test_Enum[2], ADC_LOOP_DAC_HP_Get, ADC_LOOP_DAC_HP_Set),
5262 SOC_ENUM_EXT("Voice_Call_DAC_DAC_HS", Pmic_Test_Enum[3], Voice_Call_DAC_DAC_HS_Get, Voice_Call_DAC_DAC_HS_Set),
5263 SOC_ENUM_EXT("SineTable_UL2", Pmic_Test_Enum[4], SineTable_UL2_Get, SineTable_UL2_Set),
5264 };
5265
5266 static const struct snd_kcontrol_new mt6331_UL_Codec_controls[] =
5267 {
5268 SOC_ENUM_EXT("Audio_ADC_1_Switch", Audio_UL_Enum[0], Audio_ADC1_Get, Audio_ADC1_Set),
5269 SOC_ENUM_EXT("Audio_ADC_2_Switch", Audio_UL_Enum[1], Audio_ADC2_Get, Audio_ADC2_Set),
5270 SOC_ENUM_EXT("Audio_ADC_3_Switch", Audio_UL_Enum[2], Audio_ADC3_Get, Audio_ADC3_Set),
5271 SOC_ENUM_EXT("Audio_ADC_4_Switch", Audio_UL_Enum[3], Audio_ADC4_Get, Audio_ADC4_Set),
5272 SOC_ENUM_EXT("Audio_Preamp1_Switch", Audio_UL_Enum[4], Audio_PreAmp1_Get, Audio_PreAmp1_Set),
5273 SOC_ENUM_EXT("Audio_ADC_1_Sel", Audio_UL_Enum[5], Audio_ADC1_Sel_Get, Audio_ADC1_Sel_Set),
5274 SOC_ENUM_EXT("Audio_ADC_2_Sel", Audio_UL_Enum[6], Audio_ADC2_Sel_Get, Audio_ADC2_Sel_Set),
5275 SOC_ENUM_EXT("Audio_ADC_3_Sel", Audio_UL_Enum[7], Audio_ADC3_Sel_Get, Audio_ADC3_Sel_Set),
5276 SOC_ENUM_EXT("Audio_ADC_4_Sel", Audio_UL_Enum[8], Audio_ADC4_Sel_Get, Audio_ADC4_Sel_Set),
5277 SOC_ENUM_EXT("Audio_PGA1_Setting", Audio_UL_Enum[9], Audio_PGA1_Get, Audio_PGA1_Set),
5278 SOC_ENUM_EXT("Audio_PGA2_Setting", Audio_UL_Enum[10], Audio_PGA2_Get, Audio_PGA2_Set),
5279 SOC_ENUM_EXT("Audio_PGA3_Setting", Audio_UL_Enum[11], Audio_PGA3_Get, Audio_PGA3_Set),
5280 SOC_ENUM_EXT("Audio_PGA4_Setting", Audio_UL_Enum[12], Audio_PGA4_Get, Audio_PGA4_Set),
5281 SOC_ENUM_EXT("Audio_MicSource1_Setting", Audio_UL_Enum[13], Audio_MicSource1_Get, Audio_MicSource1_Set),
5282 SOC_ENUM_EXT("Audio_MicSource2_Setting", Audio_UL_Enum[14], Audio_MicSource2_Get, Audio_MicSource2_Set),
5283 SOC_ENUM_EXT("Audio_MicSource3_Setting", Audio_UL_Enum[15], Audio_MicSource3_Get, Audio_MicSource3_Set),
5284 SOC_ENUM_EXT("Audio_MicSource4_Setting", Audio_UL_Enum[16], Audio_MicSource4_Get, Audio_MicSource4_Set),
5285 SOC_ENUM_EXT("Audio_MIC1_Mode_Select", Audio_UL_Enum[17], Audio_Mic1_Mode_Select_Get, Audio_Mic1_Mode_Select_Set),
5286 SOC_ENUM_EXT("Audio_MIC2_Mode_Select", Audio_UL_Enum[18], Audio_Mic2_Mode_Select_Get, Audio_Mic2_Mode_Select_Set),
5287 SOC_ENUM_EXT("Audio_MIC3_Mode_Select", Audio_UL_Enum[19], Audio_Mic3_Mode_Select_Get, Audio_Mic3_Mode_Select_Set),
5288 SOC_ENUM_EXT("Audio_MIC4_Mode_Select", Audio_UL_Enum[20], Audio_Mic4_Mode_Select_Get, Audio_Mic4_Mode_Select_Set),
5289 SOC_ENUM_EXT("Audio_Mic_Power_Mode", Audio_UL_Enum[21], Audio_Adc_Power_Mode_Get, Audio_Adc_Power_Mode_Set),
5290 SOC_ENUM_EXT("Audio_Vow_ADC_Func_Switch", Audio_UL_Enum[22], Audio_Vow_ADC_Func_Switch_Get, Audio_Vow_ADC_Func_Switch_Set),
5291 SOC_ENUM_EXT("Audio_Vow_Digital_Func_Switch", Audio_UL_Enum[23], Audio_Vow_Digital_Func_Switch_Get, Audio_Vow_Digital_Func_Switch_Set),
5292 SOC_SINGLE_EXT("Audio VOWCFG0 Data", SND_SOC_NOPM, 0, 0x80000, 0, Audio_Vow_Cfg0_Get, Audio_Vow_Cfg0_Set),
5293 SOC_SINGLE_EXT("Audio VOWCFG1 Data", SND_SOC_NOPM, 0, 0x80000, 0, Audio_Vow_Cfg1_Get, Audio_Vow_Cfg1_Set),
5294 SOC_SINGLE_EXT("Audio VOWCFG2 Data", SND_SOC_NOPM, 0, 0x80000, 0, Audio_Vow_Cfg2_Get, Audio_Vow_Cfg2_Set),
5295 SOC_SINGLE_EXT("Audio VOWCFG3 Data", SND_SOC_NOPM, 0, 0x80000, 0, Audio_Vow_Cfg3_Get, Audio_Vow_Cfg3_Set),
5296 SOC_SINGLE_EXT("Audio VOWCFG4 Data", SND_SOC_NOPM, 0, 0x80000, 0, Audio_Vow_Cfg4_Get, Audio_Vow_Cfg4_Set),
5297 SOC_SINGLE_EXT("Audio VOWCFG5 Data", SND_SOC_NOPM, 0, 0x80000, 0, Audio_Vow_Cfg5_Get, Audio_Vow_Cfg5_Set),
5298 };
5299
5300 /*static void speaker_event(struct snd_soc_dapm_widget *w,
5301 struct snd_kcontrol *kcontrol, int event)
5302 {
5303 printk("speaker_event = %d\n", event);
5304 switch (event)
5305 {
5306 case SND_SOC_DAPM_PRE_PMU:
5307 printk("%s SND_SOC_DAPM_PRE_PMU", __func__);
5308 break;
5309 case SND_SOC_DAPM_POST_PMU:
5310 printk("%s SND_SOC_DAPM_POST_PMU", __func__);
5311 break;
5312 case SND_SOC_DAPM_PRE_PMD:
5313 printk("%s SND_SOC_DAPM_PRE_PMD", __func__);
5314 break;
5315 case SND_SOC_DAPM_POST_PMD:
5316 printk("%s SND_SOC_DAPM_POST_PMD", __func__);
5317 case SND_SOC_DAPM_PRE_REG:
5318 printk("%s SND_SOC_DAPM_PRE_REG", __func__);
5319 case SND_SOC_DAPM_POST_REG:
5320 printk("%s SND_SOC_DAPM_POST_REG", __func__);
5321 break;
5322 }
5323 }*/
5324
5325
5326 /* The register address is the same as other codec so it can use resmgr */
5327 /*static int codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
5328 struct snd_kcontrol *kcontrol, int event)
5329 {
5330 printk("codec_enable_rx_bias = %d\n", event);
5331 switch (event)
5332 {
5333 case SND_SOC_DAPM_PRE_PMU:
5334 printk("%s SND_SOC_DAPM_PRE_PMU", __func__);
5335 break;
5336 case SND_SOC_DAPM_POST_PMU:
5337 printk("%s SND_SOC_DAPM_POST_PMU", __func__);
5338 break;
5339 case SND_SOC_DAPM_PRE_PMD:
5340 printk("%s SND_SOC_DAPM_PRE_PMD", __func__);
5341 break;
5342 case SND_SOC_DAPM_POST_PMD:
5343 printk("%s SND_SOC_DAPM_POST_PMD", __func__);
5344 case SND_SOC_DAPM_PRE_REG:
5345 printk("%s SND_SOC_DAPM_PRE_REG", __func__);
5346 case SND_SOC_DAPM_POST_REG:
5347 printk("%s SND_SOC_DAPM_POST_REG", __func__);
5348 break;
5349 }
5350 return 0;
5351 }*/
5352
5353 static const struct snd_soc_dapm_widget mt6331_dapm_widgets[] =
5354 {
5355 /* Outputs */
5356 SND_SOC_DAPM_OUTPUT("EARPIECE"),
5357 SND_SOC_DAPM_OUTPUT("HEADSET"),
5358 SND_SOC_DAPM_OUTPUT("SPEAKER"),
5359 /*
5360 SND_SOC_DAPM_MUX_E("VOICE_Mux_E", SND_SOC_NOPM, 0, 0 , &mt6331_Voice_Switch, codec_enable_rx_bias,
5361 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
5362 SND_SOC_DAPM_PRE_REG | SND_SOC_DAPM_POST_REG),
5363 */
5364
5365 };
5366
5367 static const struct snd_soc_dapm_route mtk_audio_map[] =
5368 {
5369 {"VOICE_Mux_E", "Voice Mux", "SPEAKER PGA"},
5370 };
5371
5372 static void mt6331_codec_init_reg(struct snd_soc_codec *codec)
5373 {
5374 printk("%s \n", __func__);
5375 Ana_Set_Reg(TOP_CLKSQ, 0x0 , 0xffff);
5376 Ana_Set_Reg(AUDNVREGGLB_CFG0, 0x0001, 0xffff);
5377 Ana_Set_Reg(TOP_CKPDN_CON0_SET, 0x3000, 0x3000);
5378 Ana_Set_Reg(AUDBUF_CFG0, 0xE000 , 0xe000); //Disable voice DriverVer_type
5379 // set to lowe power mode
5380 #ifndef CONFIG_MTK_FPGA
5381 mt6331_upmu_set_rg_audmicbias1lowpen(true); // mic 1 low power mode
5382 mt6331_upmu_set_rg_audmicbias0lowpen(true); // mic 1 low power mode
5383 #endif
5384 Ana_Set_Reg(AUDMICBIAS_CFG1, 0x2020, 0xffff); //power on clock
5385 Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0xA000, 0xffff); //power on clock
5386 }
5387
5388 void InitCodecDefault(void)
5389 {
5390 printk("%s\n", __func__);
5391 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP1] = 3;
5392 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP2] = 3;
5393 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP3] = 3;
5394 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP4] = 3;
5395 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR] = 8;
5396 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR] = 8;
5397
5398 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC1] = AUDIO_ANALOG_AUDIOANALOG_INPUT_PREAMP;
5399 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC2] = AUDIO_ANALOG_AUDIOANALOG_INPUT_PREAMP;
5400 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC3] = AUDIO_ANALOG_AUDIOANALOG_INPUT_PREAMP;
5401 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC4] = AUDIO_ANALOG_AUDIOANALOG_INPUT_PREAMP;
5402 }
5403
5404 static int mt6331_codec_probe(struct snd_soc_codec *codec)
5405 {
5406 struct snd_soc_dapm_context *dapm = &codec->dapm;
5407 printk("%s()\n", __func__);
5408 if (mInitCodec == true)
5409 {
5410 return 0;
5411 }
5412
5413 snd_soc_dapm_new_controls(dapm, mt6331_dapm_widgets,
5414 ARRAY_SIZE(mt6331_dapm_widgets));
5415 snd_soc_dapm_add_routes(dapm, mtk_audio_map,
5416 ARRAY_SIZE(mtk_audio_map));
5417
5418 //add codec controls
5419 snd_soc_add_codec_controls(codec, mt6331_snd_controls,
5420 ARRAY_SIZE(mt6331_snd_controls));
5421 snd_soc_add_codec_controls(codec, mt6331_UL_Codec_controls,
5422 ARRAY_SIZE(mt6331_UL_Codec_controls));
5423 snd_soc_add_codec_controls(codec, mt6331_Voice_Switch,
5424 ARRAY_SIZE(mt6331_Voice_Switch));
5425 snd_soc_add_codec_controls(codec, mt6331_pmic_Test_controls,
5426 ARRAY_SIZE(mt6331_pmic_Test_controls));
5427
5428 #ifdef CONFIG_MTK_SPEAKER
5429 snd_soc_add_codec_controls(codec, mt6331_snd_Speaker_controls,
5430 ARRAY_SIZE(mt6331_snd_Speaker_controls));
5431 #endif
5432
5433 snd_soc_add_codec_controls(codec, Audio_snd_auxadc_controls,
5434 ARRAY_SIZE(Audio_snd_auxadc_controls));
5435
5436 // here to set private data
5437 mCodec_data = kzalloc(sizeof(mt6331_Codec_Data_Priv), GFP_KERNEL);
5438 if (!mCodec_data)
5439 {
5440 printk("Failed to allocate private data\n");
5441 return -ENOMEM;
5442 }
5443 snd_soc_codec_set_drvdata(codec, mCodec_data);
5444
5445 memset((void *)mCodec_data , 0 , sizeof(mt6331_Codec_Data_Priv));
5446 mt6331_codec_init_reg(codec);
5447 InitCodecDefault();
5448 mInitCodec = true;
5449
5450 return 0;
5451 }
5452
5453 static int mt6331_codec_remove(struct snd_soc_codec *codec)
5454 {
5455 printk("%s()\n", __func__);
5456 return 0;
5457 }
5458
5459 static unsigned int mt6331_read(struct snd_soc_codec *codec,
5460 unsigned int reg)
5461 {
5462 printk("mt6331_read reg = 0x%x", reg);
5463 Ana_Get_Reg(reg);
5464 return 0;
5465 }
5466
5467 static int mt6331_write(struct snd_soc_codec *codec, unsigned int reg,
5468 unsigned int value)
5469 {
5470 printk("mt6331_write reg = 0x%x value= 0x%x\n", reg, value);
5471 Ana_Set_Reg(reg , value , 0xffffffff);
5472 return 0;
5473 }
5474
5475 static int mt6331_Readable_registers(struct snd_soc_codec *codec,
5476 unsigned int reg)
5477 {
5478 return 1;
5479 }
5480
5481 static int mt6331_volatile_registers(struct snd_soc_codec *codec,
5482 unsigned int reg)
5483 {
5484 return 1;
5485 }
5486
5487 static struct snd_soc_codec_driver soc_mtk_codec =
5488 {
5489 .probe = mt6331_codec_probe,
5490 .remove = mt6331_codec_remove,
5491
5492 .read = mt6331_read,
5493 .write = mt6331_write,
5494
5495 .readable_register = mt6331_Readable_registers,
5496 .volatile_register = mt6331_volatile_registers,
5497
5498 // use add control to replace
5499 //.controls = mt6331_snd_controls,
5500 //.num_controls = ARRAY_SIZE(mt6331_snd_controls),
5501
5502 .dapm_widgets = mt6331_dapm_widgets,
5503 .num_dapm_widgets = ARRAY_SIZE(mt6331_dapm_widgets),
5504 .dapm_routes = mtk_audio_map,
5505 .num_dapm_routes = ARRAY_SIZE(mtk_audio_map),
5506
5507 };
5508
5509 static int mtk_mt6331_codec_dev_probe(struct platform_device *pdev)
5510 {
5511 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
5512 if (pdev->dev.dma_mask == NULL)
5513 {
5514 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
5515 }
5516
5517 if (pdev->dev.of_node)
5518 {
5519 dev_set_name(&pdev->dev, "%s", MT_SOC_CODEC_NAME);
5520 }
5521
5522 printk("%s: dev name %s\n", __func__, dev_name(&pdev->dev));
5523 return snd_soc_register_codec(&pdev->dev,
5524 &soc_mtk_codec, mtk_6331_dai_codecs, ARRAY_SIZE(mtk_6331_dai_codecs));
5525 }
5526
5527 static int mtk_mt6331_codec_dev_remove(struct platform_device *pdev)
5528 {
5529 printk("%s:\n", __func__);
5530
5531 snd_soc_unregister_codec(&pdev->dev);
5532 return 0;
5533
5534 }
5535
5536 #ifdef CONFIG_OF
5537 static const struct of_device_id mt_soc_codec_63xx_of_ids[] =
5538 {
5539 { .compatible = "mediatek,mt_soc_codec_63xx", },
5540 {}
5541 };
5542 #endif
5543
5544 static struct platform_driver mtk_codec_6331_driver =
5545 {
5546 .driver = {
5547 .name = MT_SOC_CODEC_NAME,
5548 .owner = THIS_MODULE,
5549 #ifdef CONFIG_OF
5550 .of_match_table = mt_soc_codec_63xx_of_ids,
5551 #endif
5552 },
5553 .probe = mtk_mt6331_codec_dev_probe,
5554 .remove = mtk_mt6331_codec_dev_remove,
5555 };
5556
5557 #ifndef CONFIG_OF
5558 static struct platform_device *soc_mtk_codec6331_dev;
5559 #endif
5560
5561 static int __init mtk_mt6331_codec_init(void)
5562 {
5563 int ret = 0;
5564 printk("%s:\n", __func__);
5565 #ifndef CONFIG_OF
5566 soc_mtk_codec6331_dev = platform_device_alloc(MT_SOC_CODEC_NAME, -1);
5567 if (!soc_mtk_codec6331_dev)
5568 {
5569 return -ENOMEM;
5570 }
5571
5572 ret = platform_device_add(soc_mtk_codec6331_dev);
5573 if (ret != 0)
5574 {
5575 platform_device_put(soc_mtk_codec6331_dev);
5576 return ret;
5577 }
5578 #endif
5579 ret = platform_driver_register(&mtk_codec_6331_driver);
5580 return ret;
5581 }
5582 module_init(mtk_mt6331_codec_init);
5583
5584 static void __exit mtk_mt6331_codec_exit(void)
5585 {
5586 printk("%s:\n", __func__);
5587
5588 platform_driver_unregister(&mtk_codec_6331_driver);
5589 }
5590
5591 module_exit(mtk_mt6331_codec_exit);
5592
5593 /* Module information */
5594 MODULE_DESCRIPTION("MTK codec driver");
5595 MODULE_LICENSE("GPL v2");
5596
kernel source for telekom puls (alcatel/mediatek)