sound/soc/mediatek/mt_soc_audio_v1/AudDrv_Ana.h

   1 /*
   2  * Copyright (C) 2007 The Android Open Source Project
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *      http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 /*******************************************************************************
  17  *
  18  * Filename:
  19  * ---------
  20  *   AudDrv_Ana.h
  21  *
  22  * Project:
  23  * --------
  24  *   MT6583  Audio Driver Ana
  25  *
  26  * Description:
  27  * ------------
  28  *   Audio register
  29  *
  30  * Author:
  31  * -------
  32  *   Chipeng Chang (mtk02308)
  33  *
  34  *------------------------------------------------------------------------------
  35  * $Revision: #1 $
  36  * $Modtime:$
  37  * $Log:$
  38  *
  39  *
  40  *******************************************************************************/
  41
  42 #ifndef _AUDDRV_ANA_H_
  43 #define _AUDDRV_ANA_H_
  44
  45 /*****************************************************************************
  46  *                     C O M P I L E R   F L A G S
  47  *****************************************************************************/
  48
  49
  50 /*****************************************************************************
  51  *                E X T E R N A L   R E F E R E N C E S
  52  *****************************************************************************/
  53
  54 #include "AudDrv_Common.h"
  55 #include "AudDrv_Def.h"
  56
  57
  58 /*****************************************************************************
  59  *                         D A T A   T Y P E S
  60  *****************************************************************************/
  61
  62
  63 /*****************************************************************************
  64  *                         M A C R O
  65  *****************************************************************************/
  66
  67 /*****************************************************************************
  68  *                  R E G I S T E R       D E F I N I T I O N
  69  *****************************************************************************/
  70 #define PMIC_REG_BASE                    (0x0000)
  71 #define AFE_UL_DL_CON0                                   ((UINT32)(PMIC_REG_BASE+0x2000+0x0))
  72 #define AFE_DL_SRC2_CON0_H                         ((UINT32)(PMIC_REG_BASE+0x2000+0x2))
  73 #define AFE_DL_SRC2_CON0_L                          ((UINT32)(PMIC_REG_BASE+0x2000+0x4))
  74 #define AFE_DL_SDM_CON0                                ((UINT32)(PMIC_REG_BASE+0x2000+0x6))
  75 #define AFE_DL_SDM_CON1                                ((UINT32)(PMIC_REG_BASE+0x2000+0x8))
  76 #define AFE_UL_SRC0_CON0_H                         ((UINT32)(PMIC_REG_BASE+0x2000+0xa))
  77 #define AFE_UL_SRC0_CON0_L                          ((UINT32)(PMIC_REG_BASE+0x2000+0xc))
  78 #define AFE_UL_SRC1_CON0_H                         ((UINT32)(PMIC_REG_BASE+0x2000+0xe))
  79 #define AFE_UL_SRC1_CON0_L                          ((UINT32)(PMIC_REG_BASE+0x2000+0x10))
  80 #define PMIC_AFE_TOP_CON0                            ((UINT32)(PMIC_REG_BASE+0x2000+0x12))
  81 #define AFE_AUDIO_TOP_CON0                         ((UINT32)(PMIC_REG_BASE+0x2000+0x14))
  82 #define AFE_DL_SRC_MON0                                ((UINT32)(PMIC_REG_BASE+0x2000+0x16))
  83 #define AFE_DL_SDM_TEST0                               ((UINT32)(PMIC_REG_BASE+0x2000+0x18))
  84 #define AFE_MON_DEBUG0                                 ((UINT32)(PMIC_REG_BASE+0x2000+0x1a))
  85 #define AFUNC_AUD_CON0                                 ((UINT32)(PMIC_REG_BASE+0x2000+0x1c))
  86 #define AFUNC_AUD_CON1                                 ((UINT32)(PMIC_REG_BASE+0x2000+0x1e))
  87 #define AFUNC_AUD_CON2                                 ((UINT32)(PMIC_REG_BASE+0x2000+0x20))
  88 #define AFUNC_AUD_CON3                                 ((UINT32)(PMIC_REG_BASE+0x2000+0x22))
  89 #define AFUNC_AUD_CON4                                 ((UINT32)(PMIC_REG_BASE+0x2000+0x24))
  90 #define AFUNC_AUD_MON0                                ((UINT32)(PMIC_REG_BASE+0x2000+0x26))
  91 #define AFUNC_AUD_MON1                                ((UINT32)(PMIC_REG_BASE+0x2000+0x28))
  92 #define AUDRC_TUNE_MON0                              ((UINT32)(PMIC_REG_BASE+0x2000+0x2a))
  93 #define AFE_UP8X_FIFO_CFG0                         ((UINT32)(PMIC_REG_BASE+0x2000+0x2c))
  94 #define AFE_UP8X_FIFO_LOG_MON0              ((UINT32)(PMIC_REG_BASE+0x2000+0x2e))
  95 #define AFE_UP8X_FIFO_LOG_MON1              ((UINT32)(PMIC_REG_BASE+0x2000+0x30))
  96 #define AFE_DL_DC_COMP_CFG0                    ((UINT32)(PMIC_REG_BASE+0x2000+0x32))
  97 #define AFE_DL_DC_COMP_CFG1                    ((UINT32)(PMIC_REG_BASE+0x2000+0x34))
  98 #define AFE_DL_DC_COMP_CFG2                    ((UINT32)(PMIC_REG_BASE+0x2000+0x36))
  99 #define AFE_PMIC_NEWIF_CFG0                     ((UINT32)(PMIC_REG_BASE+0x2000+0x38))
 100 #define AFE_PMIC_NEWIF_CFG1                     ((UINT32)(PMIC_REG_BASE+0x2000+0x3a))
 101 #define AFE_PMIC_NEWIF_CFG2                     ((UINT32)(PMIC_REG_BASE+0x2000+0x3c))
 102 #define AFE_PMIC_NEWIF_CFG3                     ((UINT32)(PMIC_REG_BASE+0x2000+0x3e))
 103 #define AFE_SGEN_CFG0                                   ((UINT32)(PMIC_REG_BASE+0x2000+0x40))
 104 #define AFE_SGEN_CFG1                                   ((UINT32)(PMIC_REG_BASE+0x2000+0x42))
 105 #define AFE_ADDA2_UL_SRC_CON0_H           ((UINT32)(PMIC_REG_BASE+0x2000+0x44))
 106 #define AFE_ADDA2_UL_SRC_CON0_L            ((UINT32)(PMIC_REG_BASE+0x2000+0x46))
 107 #define AFE_UL_SRC_CON1_H                          ((UINT32)(PMIC_REG_BASE+0x2000+0x48))
 108 #define AFE_ADDA2_UL_SRC_CON1_L          ((UINT32)(PMIC_REG_BASE+0x2000+0x4a))
 109 #define AFE_ADDA2_UP8X_FIFO_LOG_MON0   ((UINT32)(PMIC_REG_BASE+0x2000+0x4c))
 110 #define AFE_ADDA2_UP8X_FIFO_LOG_MON1   ((UINT32)(PMIC_REG_BASE+0x2000+0x4e))
 111 #define AFE_ADDA2_PMIC_NEWIF_CFG0       ((UINT32)(PMIC_REG_BASE+0x2000+0x50))
 112 #define AFE_ADDA2_PMIC_NEWIF_CFG1       ((UINT32)(PMIC_REG_BASE+0x2000+0x52))
 113 #define AFE_ADDA2_PMIC_NEWIF_CFG2       ((UINT32)(PMIC_REG_BASE+0x2000+0x54))
 114 #define AFE_MIC_ARRAY_CFG                          ((UINT32)(PMIC_REG_BASE+0x2000+0x56))
 115 #define AFE_ADC_ASYNC_FIFO_CFG              ((UINT32)(PMIC_REG_BASE+0x2000+0x58))
 116 #define AFE_ANC_CFG0                                     ((UINT32)(PMIC_REG_BASE+0x2000+0x5a))
 117 #define AFE_ANC_CFG1                                     ((UINT32)(PMIC_REG_BASE+0x2000+0x5c))
 118 #define AFE_ANC_COEF_B00                            ((UINT32)(PMIC_REG_BASE+0x2000+0x5e))
 119 #define AFE_ANC_COEF_ADDR                         ((UINT32)(PMIC_REG_BASE+0x2000+0x60))
 120 #define AFE_ANC_COEF_WDATA                      ((UINT32)(PMIC_REG_BASE+0x2000+0x62))
 121 #define AFE_ANC_COEF_RDATA                       ((UINT32)(PMIC_REG_BASE+0x2000+0x64))
 122 #define AUDRC_TUNE_UL2_MON0                     ((UINT32)(PMIC_REG_BASE+0x2000+0x66))
 123 #define AFE_MBIST_CFG0                                  ((UINT32)(PMIC_REG_BASE+0x2000+0x68))
 124 #define AFE_MBIST_CFG1                                  ((UINT32)(PMIC_REG_BASE+0x2000+0x6a))
 125 #define AFE_MBIST_CFG2                                  ((UINT32)(PMIC_REG_BASE+0x2000+0x6c))
 126 #define AFE_MBIST_CFG3                                  ((UINT32)(PMIC_REG_BASE+0x2000+0x6e))
 127 #define AFE_VOW_TOP                                        ((UINT32)(PMIC_REG_BASE+0x2000+0x70))
 128 #define AFE_VOW_CFG0                                     ((UINT32)(PMIC_REG_BASE+0x2000+0x72))
 129 #define AFE_VOW_CFG1                                     ((UINT32)(PMIC_REG_BASE+0x2000+0x74))
 130 #define AFE_VOW_CFG2                                     ((UINT32)(PMIC_REG_BASE+0x2000+0x76))
 131 #define AFE_VOW_CFG3                                     ((UINT32)(PMIC_REG_BASE+0x2000+0x78))
 132 #define AFE_VOW_CFG4                                     ((UINT32)(PMIC_REG_BASE+0x2000+0x7a))
 133 #define AFE_VOW_CFG5                                     ((UINT32)(PMIC_REG_BASE+0x2000+0x7c))
 134 #define AFE_VOW_MON0                                    ((UINT32)(PMIC_REG_BASE+0x2000+0x7e))
 135 #define AFE_VOW_MON1                                    ((UINT32)(PMIC_REG_BASE+0x2000+0x80))
 136 #define AFE_VOW_MON2                                    ((UINT32)(PMIC_REG_BASE+0x2000+0x82))
 137 #define AFE_VOW_MON3                                    ((UINT32)(PMIC_REG_BASE+0x2000+0x84))
 138 #define AFE_VOW_MON4                                    ((UINT32)(PMIC_REG_BASE+0x2000+0x86))
 139 #define AFE_VOW_MON5                                    ((UINT32)(PMIC_REG_BASE+0x2000+0x88))
 140 #define AFE_CLASSH_CFG0                               ((UINT32)(PMIC_REG_BASE+0x2000+0x8a))
 141 #define AFE_CLASSH_CFG1                               ((UINT32)(PMIC_REG_BASE+0x2000+0x8c))
 142 #define AFE_CLASSH_CFG2                               ((UINT32)(PMIC_REG_BASE+0x2000+0x8e))
 143 #define AFE_CLASSH_CFG3                               ((UINT32)(PMIC_REG_BASE+0x2000+0x90))
 144 #define AFE_CLASSH_CFG4                               ((UINT32)(PMIC_REG_BASE+0x2000+0x92))
 145 #define AFE_CLASSH_CFG5                               ((UINT32)(PMIC_REG_BASE+0x2000+0x94))
 146 #define AFE_CLASSH_CFG6                               ((UINT32)(PMIC_REG_BASE+0x2000+0x96))
 147 #define AFE_CLASSH_CFG7                               ((UINT32)(PMIC_REG_BASE+0x2000+0x98))
 148 #define AFE_CLASSH_CFG8                               ((UINT32)(PMIC_REG_BASE+0x2000+0x9a))
 149 #define AFE_CLASSH_CFG9                               ((UINT32)(PMIC_REG_BASE+0x2000+0x9c))
 150 #define AFE_CLASSH_CFG10                             ((UINT32)(PMIC_REG_BASE+0x2000+0x9e))
 151 #define AFE_CLASSH_CFG11                             ((UINT32)(PMIC_REG_BASE+0x2000+0xa0))
 152 #define AFE_CLASSH_CFG12                               ((UINT32)(PMIC_REG_BASE+0x2000+0xa2))
 153 #define AFE_CLASSH_CFG13                               ((UINT32)(PMIC_REG_BASE+0x2000+0xa4))
 154 #define AFE_CLASSH_CFG14                               ((UINT32)(PMIC_REG_BASE+0x2000+0xa6))
 155 #define AFE_CLASSH_CFG15                               ((UINT32)(PMIC_REG_BASE+0x2000+0xa8))
 156 #define AFE_CLASSH_CFG16                               ((UINT32)(PMIC_REG_BASE+0x2000+0xaa))
 157 #define AFE_CLASSH_CFG17                               ((UINT32)(PMIC_REG_BASE+0x2000+0xac))
 158 #define AFE_CLASSH_CFG18                               ((UINT32)(PMIC_REG_BASE+0x2000+0xae))
 159 #define AFE_CLASSH_CFG19                               ((UINT32)(PMIC_REG_BASE+0x2000+0xb0))
 160 #define AFE_CLASSH_CFG20                               ((UINT32)(PMIC_REG_BASE+0x2000+0xb2))
 161 #define AFE_CLASSH_CFG21                               ((UINT32)(PMIC_REG_BASE+0x2000+0xb4))
 162 #define AFE_CLASSH_CFG22                               ((UINT32)(PMIC_REG_BASE+0x2000+0xb6))
 163 #define AFE_CLASSH_CFG23                               ((UINT32)(PMIC_REG_BASE+0x2000+0xb8))
 164 #define AFE_CLASSH_CFG24                               ((UINT32)(PMIC_REG_BASE+0x2000+0xba))
 165 #define AFE_CLASSH_CFG25                               ((UINT32)(PMIC_REG_BASE+0x2000+0xbc))
 166 #define AFE_CLASSH_CFG26                               ((UINT32)(PMIC_REG_BASE+0x2000+0xbe))
 167 #define AFE_CLASSH_CFG27                               ((UINT32)(PMIC_REG_BASE+0x2000+0xc0))
 168 #define AFE_CLASSH_CFG28                               ((UINT32)(PMIC_REG_BASE+0x2000+0xc2))
 169 #define AFE_CLASSH_CFG29                               ((UINT32)(PMIC_REG_BASE+0x2000+0xc4))
 170 #define AFE_CLASSH_CFG30                               ((UINT32)(PMIC_REG_BASE+0x2000+0xc6))
 171 #define AFE_CLASSH_MON00                               ((UINT32)(PMIC_REG_BASE+0x2000+0xc8))
 172 #define AFE_CLASSH_MON1                                 ((UINT32)(PMIC_REG_BASE+0x2000+0xca))
 173 #define AFE_CLASSH_RESERVED0                       ((UINT32)(PMIC_REG_BASE+0x2000+0xcc))
 174 #define AFE_CLASSH_RESERVED1                       ((UINT32)(PMIC_REG_BASE+0x2000+0xce))
 175 #define AFE_DCCLK_CFG0                                     ((UINT32)(PMIC_REG_BASE+0x2000+0xd0))
 176 #define AFE_ANC_COEF_MON1                            ((UINT32)(PMIC_REG_BASE+0x2000+0xd2))
 177 #define AFE_ANC_COEF_MON2                            ((UINT32)(PMIC_REG_BASE+0x2000+0xd4))
 178 #define AFE_ANC_COEF_MON3                            ((UINT32)(PMIC_REG_BASE+0x2000+0xd6))
 179
 180
 181 #define TOP_STATUS                                               ((UINT32)(PMIC_REG_BASE+0x132))
 182 #define TOP_STATUS_SET                                       ((UINT32)(PMIC_REG_BASE+0x134))
 183 #define TOP_STATUS_CLR                                       ((UINT32)(PMIC_REG_BASE+0x136))
 184 #define TOP_CKPDN_CON0                                     ((UINT32)(PMIC_REG_BASE+0x138))
 185 #define TOP_CKPDN_CON0_SET                             ((UINT32)(PMIC_REG_BASE+0x13a))
 186 #define TOP_CKPDN_CON0_CLR                             ((UINT32)(PMIC_REG_BASE+0x13c))
 187 #define TOP_CKPDN_CON1                                     ((UINT32)(PMIC_REG_BASE+0x13e))
 188 #define TOP_CKPDN_CON1_SET                             ((UINT32)(PMIC_REG_BASE+0x140))
 189 #define TOP_CKPDN_CON1_CLR                             ((UINT32)(PMIC_REG_BASE+0x142))
 190 #define TOP_CKPDN_CON2                                      ((UINT32)(PMIC_REG_BASE+0x144))
 191 #define TOP_CKPDN_CON2_SET                             ((UINT32)(PMIC_REG_BASE+0x146))
 192 #define TOP_CKPDN_CON2_CLR                             ((UINT32)(PMIC_REG_BASE+0x148))
 193 #define TOP_CKSEL_CON                                         ((UINT32)(PMIC_REG_BASE+0x14a))
 194 #define TOP_CKSEL_CON_SET                                 ((UINT32)(PMIC_REG_BASE+0x14c))
 195 #define TOP_CKSEL_CON_CLR                                 ((UINT32)(PMIC_REG_BASE+0x14e))
 196 #define TOP_CKHWEN_CON                                     ((UINT32)(PMIC_REG_BASE+0x150))
 197 #define TOP_CKHWEN_CON_SET                             ((UINT32)(PMIC_REG_BASE+0x152))
 198 #define TOP_CKHWEN_CON_CLR                             ((UINT32)(PMIC_REG_BASE+0x154))
 199 #define TOP_CKTST_CON0                                        ((UINT32)(PMIC_REG_BASE+0x156))
 200 #define TOP_CKTST_CON0_SET                              ((UINT32)(PMIC_REG_BASE+0x158))
 201 #define TOP_CKTST_CON0_GET                              ((UINT32)(PMIC_REG_BASE+0x158))
 202
 203 #define TOP_CLKSQ                                                   ((UINT32)(PMIC_REG_BASE+0x15a))
 204 #define TOP_CLKSQ_SET                                          ((UINT32)(PMIC_REG_BASE+0x15C))
 205 #define TOP_CLKSQ_CLR                                          ((UINT32)(PMIC_REG_BASE+0x15e))
 206 #define TOP_RST_CON                                              ((UINT32)(PMIC_REG_BASE+0x160))
 207 #define TOP_RST_CON_SET                                     ((UINT32)(PMIC_REG_BASE+0x162))
 208 #define TOP_RST_CON_CLR                                     ((UINT32)(PMIC_REG_BASE+0x164))
 209
 210 #define ZCD_CON0                                                    ((UINT32)(PMIC_REG_BASE+0x400))
 211 #define ZCD_CON1                                                    ((UINT32)(PMIC_REG_BASE+0x402))
 212 #define ZCD_CON2                                                    ((UINT32)(PMIC_REG_BASE+0x404))
 213 #define ZCD_CON3                                                    ((UINT32)(PMIC_REG_BASE+0x406))
 214 #define ZCD_CON4                                                    ((UINT32)(PMIC_REG_BASE+0x408))
 215 #define ZCD_CON5                                                    ((UINT32)(PMIC_REG_BASE+0x40a))
 216
 217
 218 #define ANALDO_CON3                                            ((UINT32)(PMIC_REG_BASE+0x506))
 219
 220 #define AUDDAC_CFG0                                            ((UINT32)(PMIC_REG_BASE+0x662))
 221 #define AUDBUF_CFG0                                            ((UINT32)(PMIC_REG_BASE+0x664))
 222 #define AUDBUF_CFG1                                            ((UINT32)(PMIC_REG_BASE+0x666))
 223 #define AUDBUF_CFG2                                            ((UINT32)(PMIC_REG_BASE+0x668))
 224 #define AUDBUF_CFG3                                            ((UINT32)(PMIC_REG_BASE+0x66a))
 225 #define AUDBUF_CFG4                                            ((UINT32)(PMIC_REG_BASE+0x66c))
 226 #define AUDBUF_CFG5                                            ((UINT32)(PMIC_REG_BASE+0x66e))
 227 #define AUDBUF_CFG6                                            ((UINT32)(PMIC_REG_BASE+0x670))
 228 #define AUDBUF_CFG7                                            ((UINT32)(PMIC_REG_BASE+0x672))
 229 #define AUDBUF_CFG8                                            ((UINT32)(PMIC_REG_BASE+0x674))
 230 #define IBIASDIST_CFG0                                         ((UINT32)(PMIC_REG_BASE+0x676))
 231 #define AUDCLKGEN_CFG0                                      ((UINT32)(PMIC_REG_BASE+0x678))
 232 #define AUDLDO_CFG0                                            ((UINT32)(PMIC_REG_BASE+0x67a))
 233 #define AUDDCDC_CFG1                                          ((UINT32)(PMIC_REG_BASE+0x67c))
 234 #define AUDNVREGGLB_CFG0                                 ((UINT32)(PMIC_REG_BASE+0x680))
 235 #define AUD_NCP0                                                   ((UINT32)(PMIC_REG_BASE+0x682))
 236 #define AUD_ZCD_CFG0                                          ((UINT32)(PMIC_REG_BASE+0x684))
 237 #define AUDPREAMP_CFG0                                     ((UINT32)(PMIC_REG_BASE+0x686))
 238 #define AUDPREAMP_CFG1                                     ((UINT32)(PMIC_REG_BASE+0x688))
 239 #define AUDPREAMP_CFG2                                     ((UINT32)(PMIC_REG_BASE+0x68a))
 240 #define AUDADC_CFG0                                            ((UINT32)(PMIC_REG_BASE+0x68c))
 241 #define AUDADC_CFG1                                            ((UINT32)(PMIC_REG_BASE+0x68e))
 242 #define AUDADC_CFG2                                            ((UINT32)(PMIC_REG_BASE+0x690))
 243 #define AUDADC_CFG3                                            ((UINT32)(PMIC_REG_BASE+0x692))
 244 #define AUDADC_CFG4                                            ((UINT32)(PMIC_REG_BASE+0x694))
 245 #define AUDADC_CFG5                                            ((UINT32)(PMIC_REG_BASE+0x696))
 246 #define AUDDIGMI_CFG0                                         ((UINT32)(PMIC_REG_BASE+0x698))
 247 #define AUDDIGMI_CFG1                                         ((UINT32)(PMIC_REG_BASE+0x69a))
 248 #define AUDMICBIAS_CFG0                                     ((UINT32)(PMIC_REG_BASE+0x69c))
 249 #define AUDMICBIAS_CFG1                                     ((UINT32)(PMIC_REG_BASE+0x69e))
 250 #define AUDENCSPARE_CFG0                                  ((UINT32)(PMIC_REG_BASE+0x6a0))
 251 #define AUDPREAMPGAIN_CFG0                             ((UINT32)(PMIC_REG_BASE+0x6a2))
 252 #define AUDVOWPLL_CFG0                                      ((UINT32)(PMIC_REG_BASE+0x6a4))
 253 #define AUDVOWPLL_CFG1                                       ((UINT32)(PMIC_REG_BASE+0x6a6))
 254 #define AUDVOWPLL_CFG2                                       ((UINT32)(PMIC_REG_BASE+0x6a8))
 255 #define AUDLDO_NVREG_CFG0                                ((UINT32)(PMIC_REG_BASE+0x6aa))
 256 #define AUDLDO_NVREG_CFG1                                ((UINT32)(PMIC_REG_BASE+0x6ac))
 257 #define AUDLDO_NVREG_CFG2                                ((UINT32)(PMIC_REG_BASE+0x6ae))
 258
 259 #define SPK_TOP_CKPDN_CON0                                   ((UINT32)(0x8094))
 260 #define SPK_TOP_CKPDN_CON0_SET                          ((UINT32)(0x8096))
 261 #define SPK_TOP_CKPDN_CON0_CLR                          ((UINT32)(0x8098))
 262 #define SPK_TOP_CKPDN_CON1                                   ((UINT32)(0x809a))
 263 #define SPK_TOP_CKPDN_CON1_SET                          ((UINT32)(0x809c))
 264 #define SPK_TOP_CKPDN_CON1_CLR                          ((UINT32)(0x809e))
 265
 266
 267 #define SPK_INT_CON2                                            ((UINT32)(0x80d4))
 268 #define SPK_INT_CON2_SET                                   ((UINT32)(0x80d4))
 269 #define SPK_INT_CON2_CLR                                   ((UINT32)(0x809A))
 270
 271 #define VSBST_CON5                                                  ((UINT32)(0x8534))
 272
 273 #define VSBST_CON0                                                  ((UINT32)(0x852a))
 274 #define VSBST_CON1                                                  ((UINT32)(0x852c))
 275 #define VSBST_CON2                                                  ((UINT32)(0x852e))
 276 #define VSBST_CON3                                                  ((UINT32)(0x8530))
 277 #define VSBST_CON4                                                  ((UINT32)(0x8532))
 278 #define VSBST_CON5                                                  ((UINT32)(0x8534))
 279 #define VSBST_CON6                                                  ((UINT32)(0x8536))
 280 #define VSBST_CON7                                                  ((UINT32)(0x8538))
 281 #define VSBST_CON8                                                  ((UINT32)(0x853a))
 282 #define VSBST_CON9                                                  ((UINT32)(0x853c))
 283 #define VSBST_CON10                                               ((UINT32)(0x853e))
 284 #define VSBST_CON11                                               ((UINT32)(0x8540))
 285 #define VSBST_CON12                                               ((UINT32)(0x8542))
 286 #define VSBST_CON13                                               ((UINT32)(0x8544))
 287 #define VSBST_CON14                                               ((UINT32)(0x8546))
 288 #define VSBST_CON15                                               ((UINT32)(0x8548))
 289 #define VSBST_CON16                                               ((UINT32)(0x854a))
 290 #define VSBST_CON17                                               ((UINT32)(0x854c))
 291 #define VSBST_CON18                                               ((UINT32)(0x854e))
 292 #define VSBST_CON19                                               ((UINT32)(0x8550))
 293 #define VSBST_CON20                                               ((UINT32)(0x8552))
 294 #define VSBST_CON21                                               ((UINT32)(0x8554))
 295
 296
 297 #define SPK_CON0                                                      ((UINT32)(0x8cf2))
 298 #define SPK_CON1                                                      ((UINT32)(0x8cf4))
 299 #define SPK_CON2                                                      ((UINT32)(0x8cf6))
 300 #define SPK_CON3                                                      ((UINT32)(0x8cf8))
 301 #define SPK_CON4                                                      ((UINT32)(0x8cfa))
 302 #define SPK_CON5                                                      ((UINT32)(0x8cfc))
 303 #define SPK_CON6                                                      ((UINT32)(0x8cfe))
 304 #define SPK_CON7                                                      ((UINT32)(0x8d00))
 305 #define SPK_CON8                                                      ((UINT32)(0x8d02))
 306 #define SPK_CON9                                                      ((UINT32)(0x8d04))
 307 #define SPK_CON10                                                    ((UINT32)(0x8d06))
 308 #define SPK_CON11                                                    ((UINT32)(0x8d08))
 309 #define SPK_CON12                                                    ((UINT32)(0x8d0a))
 310 #define SPK_CON13                                                    ((UINT32)(0x8d0c))
 311 #define SPK_CON14                                                    ((UINT32)(0x8d0e))
 312 #define SPK_CON15                                                    ((UINT32)(0x8d10))
 313 #define SPK_CON16                                                    ((UINT32)(0x8d12))
 314
 315
 316 #define MT6332_PMIC_REG_BASE (0x8000)
 317
 318 #define MT6332_TOP_CKPDN_CON0     ((UINT32)(MT6332_PMIC_REG_BASE+0x0094))
 319
 320 #define MT6332_TOP_CKHWEN_CON     ((UINT32)(MT6332_PMIC_REG_BASE+0x00B2))
 321 #define MT6332_TOP_RST_CON     ((UINT32)(MT6332_PMIC_REG_BASE+0x00BC))
 322
 323 #define MT6332_TOP_RST_CON0           ((UINT32)(MT6332_PMIC_REG_BASE+0x0280))
 324 #define MT6332_LDO_CON1       ((UINT32)(MT6332_PMIC_REG_BASE+0x0CB6))
 325
 326
 327 #define MT6332_AUXADC_ADC0        ((UINT32)(MT6332_PMIC_REG_BASE+0x0800))
 328 #define MT6332_AUXADC_ADC1        ((UINT32)(MT6332_PMIC_REG_BASE+0x0802))
 329 #define MT6332_AUXADC_ADC2        ((UINT32)(MT6332_PMIC_REG_BASE+0x0804))
 330 #define MT6332_AUXADC_ADC3        ((UINT32)(MT6332_PMIC_REG_BASE+0x0806))
 331 #define MT6332_AUXADC_ADC4        ((UINT32)(MT6332_PMIC_REG_BASE+0x0808))
 332 #define MT6332_AUXADC_ADC5        ((UINT32)(MT6332_PMIC_REG_BASE+0x080A))
 333 #define MT6332_AUXADC_ADC6        ((UINT32)(MT6332_PMIC_REG_BASE+0x080C))
 334 #define MT6332_AUXADC_ADC7        ((UINT32)(MT6332_PMIC_REG_BASE+0x080E))
 335 #define MT6332_AUXADC_ADC8        ((UINT32)(MT6332_PMIC_REG_BASE+0x0810))
 336 #define MT6332_AUXADC_ADC9        ((UINT32)(MT6332_PMIC_REG_BASE+0x0812))
 337 #define MT6332_AUXADC_ADC10       ((UINT32)(MT6332_PMIC_REG_BASE+0x0814))
 338 #define MT6332_AUXADC_ADC11       ((UINT32)(MT6332_PMIC_REG_BASE+0x0816))
 339 #define MT6332_AUXADC_ADC12       ((UINT32)(MT6332_PMIC_REG_BASE+0x0818))
 340 #define MT6332_AUXADC_ADC13       ((UINT32)(MT6332_PMIC_REG_BASE+0x081A))
 341 #define MT6332_AUXADC_ADC14       ((UINT32)(MT6332_PMIC_REG_BASE+0x081C))
 342 #define MT6332_AUXADC_ADC15       ((UINT32)(MT6332_PMIC_REG_BASE+0x081E))
 343 #define MT6332_AUXADC_ADC16       ((UINT32)(MT6332_PMIC_REG_BASE+0x0820))
 344 #define MT6332_AUXADC_ADC17       ((UINT32)(MT6332_PMIC_REG_BASE+0x0822))
 345 #define MT6332_AUXADC_ADC18       ((UINT32)(MT6332_PMIC_REG_BASE+0x0824))
 346 #define MT6332_AUXADC_ADC19       ((UINT32)(MT6332_PMIC_REG_BASE+0x0826))
 347 #define MT6332_AUXADC_ADC20       ((UINT32)(MT6332_PMIC_REG_BASE+0x0828))
 348 #define MT6332_AUXADC_ADC21       ((UINT32)(MT6332_PMIC_REG_BASE+0x082A))
 349 #define MT6332_AUXADC_ADC22       ((UINT32)(MT6332_PMIC_REG_BASE+0x082C))
 350 #define MT6332_AUXADC_ADC23       ((UINT32)(MT6332_PMIC_REG_BASE+0x082E))
 351 #define MT6332_AUXADC_ADC24       ((UINT32)(MT6332_PMIC_REG_BASE+0x0830))
 352 #define MT6332_AUXADC_ADC25       ((UINT32)(MT6332_PMIC_REG_BASE+0x0832))
 353 #define MT6332_AUXADC_ADC26       ((UINT32)(MT6332_PMIC_REG_BASE+0x0834))
 354 #define MT6332_AUXADC_ADC27       ((UINT32)(MT6332_PMIC_REG_BASE+0x0836))
 355 #define MT6332_AUXADC_ADC28       ((UINT32)(MT6332_PMIC_REG_BASE+0x0838))
 356 #define MT6332_AUXADC_ADC29       ((UINT32)(MT6332_PMIC_REG_BASE+0x083A))
 357 #define MT6332_AUXADC_ADC30       ((UINT32)(MT6332_PMIC_REG_BASE+0x083C))
 358 #define MT6332_AUXADC_ADC31       ((UINT32)(MT6332_PMIC_REG_BASE+0x083E))
 359 #define MT6332_AUXADC_ADC32       ((UINT32)(MT6332_PMIC_REG_BASE+0x0840))
 360 #define MT6332_AUXADC_ADC33       ((UINT32)(MT6332_PMIC_REG_BASE+0x0842))
 361 #define MT6332_AUXADC_ADC34       ((UINT32)(MT6332_PMIC_REG_BASE+0x0844))
 362 #define MT6332_AUXADC_ADC35       ((UINT32)(MT6332_PMIC_REG_BASE+0x0846))
 363 #define MT6332_AUXADC_ADC36       ((UINT32)(MT6332_PMIC_REG_BASE+0x0848))
 364 #define MT6332_AUXADC_ADC37       ((UINT32)(MT6332_PMIC_REG_BASE+0x084A))
 365 #define MT6332_AUXADC_ADC38       ((UINT32)(MT6332_PMIC_REG_BASE+0x084C))
 366 #define MT6332_AUXADC_ADC39       ((UINT32)(MT6332_PMIC_REG_BASE+0x084E))
 367 #define MT6332_AUXADC_ADC40       ((UINT32)(MT6332_PMIC_REG_BASE+0x0850))
 368 #define MT6332_AUXADC_ADC41       ((UINT32)(MT6332_PMIC_REG_BASE+0x0852))
 369 #define MT6332_AUXADC_ADC42       ((UINT32)(MT6332_PMIC_REG_BASE+0x0854))
 370 #define MT6332_AUXADC_ADC43       ((UINT32)(MT6332_PMIC_REG_BASE+0x0856))
 371 #define MT6332_AUXADC_STA0        ((UINT32)(MT6332_PMIC_REG_BASE+0x0858))
 372 #define MT6332_AUXADC_STA1        ((UINT32)(MT6332_PMIC_REG_BASE+0x085A))
 373 #define MT6332_AUXADC_RQST0       ((UINT32)(MT6332_PMIC_REG_BASE+0x085C))
 374 #define MT6332_AUXADC_RQST0_SET   ((UINT32)(MT6332_PMIC_REG_BASE+0x085E))
 375 #define MT6332_AUXADC_RQST0_CLR   ((UINT32)(MT6332_PMIC_REG_BASE+0x0860))
 376 #define MT6332_AUXADC_RQST1       ((UINT32)(MT6332_PMIC_REG_BASE+0x0862))
 377 #define MT6332_AUXADC_RQST1_SET   ((UINT32)(MT6332_PMIC_REG_BASE+0x0864))
 378 #define MT6332_AUXADC_RQST1_CLR   ((UINT32)(MT6332_PMIC_REG_BASE+0x0866))
 379 #define MT6332_AUXADC_CON0        ((UINT32)(MT6332_PMIC_REG_BASE+0x0868))
 380 #define MT6332_AUXADC_CON1        ((UINT32)(MT6332_PMIC_REG_BASE+0x086A))
 381 #define MT6332_AUXADC_CON2        ((UINT32)(MT6332_PMIC_REG_BASE+0x086C))
 382 #define MT6332_AUXADC_CON3        ((UINT32)(MT6332_PMIC_REG_BASE+0x086E))
 383 #define MT6332_AUXADC_CON4        ((UINT32)(MT6332_PMIC_REG_BASE+0x0870))
 384 #define MT6332_AUXADC_CON5        ((UINT32)(MT6332_PMIC_REG_BASE+0x0872))
 385 #define MT6332_AUXADC_CON6        ((UINT32)(MT6332_PMIC_REG_BASE+0x0874))
 386 #define MT6332_AUXADC_CON7        ((UINT32)(MT6332_PMIC_REG_BASE+0x0876))
 387 #define MT6332_AUXADC_CON8        ((UINT32)(MT6332_PMIC_REG_BASE+0x0878))
 388 #define MT6332_AUXADC_CON9        ((UINT32)(MT6332_PMIC_REG_BASE+0x087A))
 389 #define MT6332_AUXADC_CON10       ((UINT32)(MT6332_PMIC_REG_BASE+0x087C))
 390 #define MT6332_AUXADC_CON11       ((UINT32)(MT6332_PMIC_REG_BASE+0x087E))
 391 #define MT6332_AUXADC_CON12       ((UINT32)(MT6332_PMIC_REG_BASE+0x0880))
 392 #define MT6332_AUXADC_CON13       ((UINT32)(MT6332_PMIC_REG_BASE+0x0882))
 393 #define MT6332_AUXADC_CON14       ((UINT32)(MT6332_PMIC_REG_BASE+0x0884))
 394 #define MT6332_AUXADC_CON15       ((UINT32)(MT6332_PMIC_REG_BASE+0x0886))
 395 #define MT6332_AUXADC_CON16       ((UINT32)(MT6332_PMIC_REG_BASE+0x0888))
 396 #define MT6332_AUXADC_CON17       ((UINT32)(MT6332_PMIC_REG_BASE+0x088A))
 397 #define MT6332_AUXADC_CON18       ((UINT32)(MT6332_PMIC_REG_BASE+0x088C))
 398 #define MT6332_AUXADC_CON19       ((UINT32)(MT6332_PMIC_REG_BASE+0x088E))
 399 #define MT6332_AUXADC_CON20       ((UINT32)(MT6332_PMIC_REG_BASE+0x0890))
 400 #define MT6332_AUXADC_CON21       ((UINT32)(MT6332_PMIC_REG_BASE+0x0892))
 401 #define MT6332_AUXADC_CON22       ((UINT32)(MT6332_PMIC_REG_BASE+0x0894))
 402 #define MT6332_AUXADC_CON23       ((UINT32)(MT6332_PMIC_REG_BASE+0x0896))
 403 #define MT6332_AUXADC_CON24       ((UINT32)(MT6332_PMIC_REG_BASE+0x0898))
 404 #define MT6332_AUXADC_CON25       ((UINT32)(MT6332_PMIC_REG_BASE+0x089A))
 405 #define MT6332_AUXADC_CON26       ((UINT32)(MT6332_PMIC_REG_BASE+0x089C))
 406 #define MT6332_AUXADC_CON27       ((UINT32)(MT6332_PMIC_REG_BASE+0x089E))
 407 #define MT6332_AUXADC_CON28       ((UINT32)(MT6332_PMIC_REG_BASE+0x08A0))
 408 #define MT6332_AUXADC_CON29       ((UINT32)(MT6332_PMIC_REG_BASE+0x08A2))
 409 #define MT6332_AUXADC_CON30       ((UINT32)(MT6332_PMIC_REG_BASE+0x08A4))
 410 #define MT6332_AUXADC_CON31       ((UINT32)(MT6332_PMIC_REG_BASE+0x08A6))
 411 #define MT6332_AUXADC_CON32       ((UINT32)(MT6332_PMIC_REG_BASE+0x08A8))
 412 #define MT6332_AUXADC_CON33       ((UINT32)(MT6332_PMIC_REG_BASE+0x08AA))
 413 #define MT6332_AUXADC_CON34       ((UINT32)(MT6332_PMIC_REG_BASE+0x08AC))
 414 #define MT6332_AUXADC_CON35       ((UINT32)(MT6332_PMIC_REG_BASE+0x08AE))
 415 #define MT6332_AUXADC_CON36       ((UINT32)(MT6332_PMIC_REG_BASE+0x08B0))
 416 #define MT6332_AUXADC_CON37       ((UINT32)(MT6332_PMIC_REG_BASE+0x08B2))
 417 #define MT6332_AUXADC_CON38       ((UINT32)(MT6332_PMIC_REG_BASE+0x08B4))
 418 #define MT6332_AUXADC_CON39       ((UINT32)(MT6332_PMIC_REG_BASE+0x08B6))
 419 #define MT6332_AUXADC_CON40       ((UINT32)(MT6332_PMIC_REG_BASE+0x08B8))
 420 #define MT6332_AUXADC_CON41       ((UINT32)(MT6332_PMIC_REG_BASE+0x08BA))
 421 #define MT6332_AUXADC_CON42       ((UINT32)(MT6332_PMIC_REG_BASE+0x08BC))
 422 #define MT6332_AUXADC_CON43       ((UINT32)(MT6332_PMIC_REG_BASE+0x08BE))
 423 #define MT6332_AUXADC_CON44       ((UINT32)(MT6332_PMIC_REG_BASE+0x08C0))
 424 #define MT6332_AUXADC_CON45       ((UINT32)(MT6332_PMIC_REG_BASE+0x08C2))
 425 #define MT6332_AUXADC_CON46       ((UINT32)(MT6332_PMIC_REG_BASE+0x08C4))
 426 #define MT6332_AUXADC_CON47       ((UINT32)(MT6332_PMIC_REG_BASE+0x08C6))
 427
 428
 429 #if 1
 430 //register number
 431
 432 #else
 433 #include <mach/upmu_hw.h>
 434 #endif
 435
 436 void Ana_Set_Reg(uint32 offset, uint32 value, uint32 mask);
 437 uint32  Ana_Get_Reg(uint32 offset);
 438
 439 // for debug usage
 440 void Ana_Log_Print(void);
 441
 442 #endif
 443
 444