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Merge tag 'sound-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / davinci / davinci-mcasp.c
1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/of.h>
26 #include <linux/of_platform.h>
27 #include <linux/of_device.h>
28
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/initval.h>
33 #include <sound/soc.h>
34
35 #include "davinci-pcm.h"
36 #include "davinci-mcasp.h"
37
38 /*
39 * McASP register definitions
40 */
41 #define DAVINCI_MCASP_PID_REG 0x00
42 #define DAVINCI_MCASP_PWREMUMGT_REG 0x04
43
44 #define DAVINCI_MCASP_PFUNC_REG 0x10
45 #define DAVINCI_MCASP_PDIR_REG 0x14
46 #define DAVINCI_MCASP_PDOUT_REG 0x18
47 #define DAVINCI_MCASP_PDSET_REG 0x1c
48
49 #define DAVINCI_MCASP_PDCLR_REG 0x20
50
51 #define DAVINCI_MCASP_TLGC_REG 0x30
52 #define DAVINCI_MCASP_TLMR_REG 0x34
53
54 #define DAVINCI_MCASP_GBLCTL_REG 0x44
55 #define DAVINCI_MCASP_AMUTE_REG 0x48
56 #define DAVINCI_MCASP_LBCTL_REG 0x4c
57
58 #define DAVINCI_MCASP_TXDITCTL_REG 0x50
59
60 #define DAVINCI_MCASP_GBLCTLR_REG 0x60
61 #define DAVINCI_MCASP_RXMASK_REG 0x64
62 #define DAVINCI_MCASP_RXFMT_REG 0x68
63 #define DAVINCI_MCASP_RXFMCTL_REG 0x6c
64
65 #define DAVINCI_MCASP_ACLKRCTL_REG 0x70
66 #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
67 #define DAVINCI_MCASP_RXTDM_REG 0x78
68 #define DAVINCI_MCASP_EVTCTLR_REG 0x7c
69
70 #define DAVINCI_MCASP_RXSTAT_REG 0x80
71 #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
72 #define DAVINCI_MCASP_RXCLKCHK_REG 0x88
73 #define DAVINCI_MCASP_REVTCTL_REG 0x8c
74
75 #define DAVINCI_MCASP_GBLCTLX_REG 0xa0
76 #define DAVINCI_MCASP_TXMASK_REG 0xa4
77 #define DAVINCI_MCASP_TXFMT_REG 0xa8
78 #define DAVINCI_MCASP_TXFMCTL_REG 0xac
79
80 #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
81 #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
82 #define DAVINCI_MCASP_TXTDM_REG 0xb8
83 #define DAVINCI_MCASP_EVTCTLX_REG 0xbc
84
85 #define DAVINCI_MCASP_TXSTAT_REG 0xc0
86 #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
87 #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
88 #define DAVINCI_MCASP_XEVTCTL_REG 0xcc
89
90 /* Left(even TDM Slot) Channel Status Register File */
91 #define DAVINCI_MCASP_DITCSRA_REG 0x100
92 /* Right(odd TDM slot) Channel Status Register File */
93 #define DAVINCI_MCASP_DITCSRB_REG 0x118
94 /* Left(even TDM slot) User Data Register File */
95 #define DAVINCI_MCASP_DITUDRA_REG 0x130
96 /* Right(odd TDM Slot) User Data Register File */
97 #define DAVINCI_MCASP_DITUDRB_REG 0x148
98
99 /* Serializer n Control Register */
100 #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
101 #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
102 (n << 2))
103
104 /* Transmit Buffer for Serializer n */
105 #define DAVINCI_MCASP_TXBUF_REG 0x200
106 /* Receive Buffer for Serializer n */
107 #define DAVINCI_MCASP_RXBUF_REG 0x280
108
109 /* McASP FIFO Registers */
110 #define DAVINCI_MCASP_WFIFOCTL (0x1010)
111 #define DAVINCI_MCASP_WFIFOSTS (0x1014)
112 #define DAVINCI_MCASP_RFIFOCTL (0x1018)
113 #define DAVINCI_MCASP_RFIFOSTS (0x101C)
114 #define MCASP_VER3_WFIFOCTL (0x1000)
115 #define MCASP_VER3_WFIFOSTS (0x1004)
116 #define MCASP_VER3_RFIFOCTL (0x1008)
117 #define MCASP_VER3_RFIFOSTS (0x100C)
118
119 /*
120 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
121 * Register Bits
122 */
123 #define MCASP_FREE BIT(0)
124 #define MCASP_SOFT BIT(1)
125
126 /*
127 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
128 */
129 #define AXR(n) (1<<n)
130 #define PFUNC_AMUTE BIT(25)
131 #define ACLKX BIT(26)
132 #define AHCLKX BIT(27)
133 #define AFSX BIT(28)
134 #define ACLKR BIT(29)
135 #define AHCLKR BIT(30)
136 #define AFSR BIT(31)
137
138 /*
139 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
140 */
141 #define AXR(n) (1<<n)
142 #define PDIR_AMUTE BIT(25)
143 #define ACLKX BIT(26)
144 #define AHCLKX BIT(27)
145 #define AFSX BIT(28)
146 #define ACLKR BIT(29)
147 #define AHCLKR BIT(30)
148 #define AFSR BIT(31)
149
150 /*
151 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
152 */
153 #define DITEN BIT(0) /* Transmit DIT mode enable/disable */
154 #define VA BIT(2)
155 #define VB BIT(3)
156
157 /*
158 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
159 */
160 #define TXROT(val) (val)
161 #define TXSEL BIT(3)
162 #define TXSSZ(val) (val<<4)
163 #define TXPBIT(val) (val<<8)
164 #define TXPAD(val) (val<<13)
165 #define TXORD BIT(15)
166 #define FSXDLY(val) (val<<16)
167
168 /*
169 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
170 */
171 #define RXROT(val) (val)
172 #define RXSEL BIT(3)
173 #define RXSSZ(val) (val<<4)
174 #define RXPBIT(val) (val<<8)
175 #define RXPAD(val) (val<<13)
176 #define RXORD BIT(15)
177 #define FSRDLY(val) (val<<16)
178
179 /*
180 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
181 */
182 #define FSXPOL BIT(0)
183 #define AFSXE BIT(1)
184 #define FSXDUR BIT(4)
185 #define FSXMOD(val) (val<<7)
186
187 /*
188 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
189 */
190 #define FSRPOL BIT(0)
191 #define AFSRE BIT(1)
192 #define FSRDUR BIT(4)
193 #define FSRMOD(val) (val<<7)
194
195 /*
196 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
197 */
198 #define ACLKXDIV(val) (val)
199 #define ACLKXE BIT(5)
200 #define TX_ASYNC BIT(6)
201 #define ACLKXPOL BIT(7)
202 #define ACLKXDIV_MASK 0x1f
203
204 /*
205 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
206 */
207 #define ACLKRDIV(val) (val)
208 #define ACLKRE BIT(5)
209 #define RX_ASYNC BIT(6)
210 #define ACLKRPOL BIT(7)
211 #define ACLKRDIV_MASK 0x1f
212
213 /*
214 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
215 * Register Bits
216 */
217 #define AHCLKXDIV(val) (val)
218 #define AHCLKXPOL BIT(14)
219 #define AHCLKXE BIT(15)
220 #define AHCLKXDIV_MASK 0xfff
221
222 /*
223 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
224 * Register Bits
225 */
226 #define AHCLKRDIV(val) (val)
227 #define AHCLKRPOL BIT(14)
228 #define AHCLKRE BIT(15)
229 #define AHCLKRDIV_MASK 0xfff
230
231 /*
232 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
233 */
234 #define MODE(val) (val)
235 #define DISMOD (val)(val<<2)
236 #define TXSTATE BIT(4)
237 #define RXSTATE BIT(5)
238 #define SRMOD_MASK 3
239 #define SRMOD_INACTIVE 0
240
241 /*
242 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
243 */
244 #define LBEN BIT(0)
245 #define LBORD BIT(1)
246 #define LBGENMODE(val) (val<<2)
247
248 /*
249 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
250 */
251 #define TXTDMS(n) (1<<n)
252
253 /*
254 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
255 */
256 #define RXTDMS(n) (1<<n)
257
258 /*
259 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
260 */
261 #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
262 #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
263 #define RXSERCLR BIT(2) /* Receiver Serializer Clear */
264 #define RXSMRST BIT(3) /* Receiver State Machine Reset */
265 #define RXFSRST BIT(4) /* Frame Sync Generator Reset */
266 #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
267 #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
268 #define TXSERCLR BIT(10) /* Transmit Serializer Clear */
269 #define TXSMRST BIT(11) /* Transmitter State Machine Reset */
270 #define TXFSRST BIT(12) /* Frame Sync Generator Reset */
271
272 /*
273 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
274 */
275 #define MUTENA(val) (val)
276 #define MUTEINPOL BIT(2)
277 #define MUTEINENA BIT(3)
278 #define MUTEIN BIT(4)
279 #define MUTER BIT(5)
280 #define MUTEX BIT(6)
281 #define MUTEFSR BIT(7)
282 #define MUTEFSX BIT(8)
283 #define MUTEBADCLKR BIT(9)
284 #define MUTEBADCLKX BIT(10)
285 #define MUTERXDMAERR BIT(11)
286 #define MUTETXDMAERR BIT(12)
287
288 /*
289 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
290 */
291 #define RXDATADMADIS BIT(0)
292
293 /*
294 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
295 */
296 #define TXDATADMADIS BIT(0)
297
298 /*
299 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
300 */
301 #define FIFO_ENABLE BIT(16)
302 #define NUMEVT_MASK (0xFF << 8)
303 #define NUMDMA_MASK (0xFF)
304
305 #define DAVINCI_MCASP_NUM_SERIALIZER 16
306
307 static inline void mcasp_set_bits(void __iomem *reg, u32 val)
308 {
309 __raw_writel(__raw_readl(reg) | val, reg);
310 }
311
312 static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
313 {
314 __raw_writel((__raw_readl(reg) & ~(val)), reg);
315 }
316
317 static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
318 {
319 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
320 }
321
322 static inline void mcasp_set_reg(void __iomem *reg, u32 val)
323 {
324 __raw_writel(val, reg);
325 }
326
327 static inline u32 mcasp_get_reg(void __iomem *reg)
328 {
329 return (unsigned int)__raw_readl(reg);
330 }
331
332 static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
333 {
334 int i = 0;
335
336 mcasp_set_bits(regs, val);
337
338 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
339 /* loop count is to avoid the lock-up */
340 for (i = 0; i < 1000; i++) {
341 if ((mcasp_get_reg(regs) & val) == val)
342 break;
343 }
344
345 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
346 printk(KERN_ERR "GBLCTL write error\n");
347 }
348
349 static void mcasp_start_rx(struct davinci_audio_dev *dev)
350 {
351 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
352 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
353 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
354 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
355
356 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
357 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
358 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
359
360 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
361 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
362 }
363
364 static void mcasp_start_tx(struct davinci_audio_dev *dev)
365 {
366 u8 offset = 0, i;
367 u32 cnt;
368
369 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
370 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
371 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
372 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
373
374 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
375 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
376 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
377 for (i = 0; i < dev->num_serializer; i++) {
378 if (dev->serial_dir[i] == TX_MODE) {
379 offset = i;
380 break;
381 }
382 }
383
384 /* wait for TX ready */
385 cnt = 0;
386 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
387 TXSTATE) && (cnt < 100000))
388 cnt++;
389
390 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
391 }
392
393 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
394 {
395 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
396 if (dev->txnumevt) { /* enable FIFO */
397 switch (dev->version) {
398 case MCASP_VERSION_3:
399 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
400 FIFO_ENABLE);
401 mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
402 FIFO_ENABLE);
403 break;
404 default:
405 mcasp_clr_bits(dev->base +
406 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
407 mcasp_set_bits(dev->base +
408 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
409 }
410 }
411 mcasp_start_tx(dev);
412 } else {
413 if (dev->rxnumevt) { /* enable FIFO */
414 switch (dev->version) {
415 case MCASP_VERSION_3:
416 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
417 FIFO_ENABLE);
418 mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
419 FIFO_ENABLE);
420 break;
421 default:
422 mcasp_clr_bits(dev->base +
423 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
424 mcasp_set_bits(dev->base +
425 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
426 }
427 }
428 mcasp_start_rx(dev);
429 }
430 }
431
432 static void mcasp_stop_rx(struct davinci_audio_dev *dev)
433 {
434 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
435 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
436 }
437
438 static void mcasp_stop_tx(struct davinci_audio_dev *dev)
439 {
440 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
441 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
442 }
443
444 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
445 {
446 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
447 if (dev->txnumevt) { /* disable FIFO */
448 switch (dev->version) {
449 case MCASP_VERSION_3:
450 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
451 FIFO_ENABLE);
452 break;
453 default:
454 mcasp_clr_bits(dev->base +
455 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
456 }
457 }
458 mcasp_stop_tx(dev);
459 } else {
460 if (dev->rxnumevt) { /* disable FIFO */
461 switch (dev->version) {
462 case MCASP_VERSION_3:
463 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
464 FIFO_ENABLE);
465 break;
466
467 default:
468 mcasp_clr_bits(dev->base +
469 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
470 }
471 }
472 mcasp_stop_rx(dev);
473 }
474 }
475
476 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
477 unsigned int fmt)
478 {
479 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
480 void __iomem *base = dev->base;
481
482 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
483 case SND_SOC_DAIFMT_DSP_B:
484 case SND_SOC_DAIFMT_AC97:
485 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
486 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
487 break;
488 default:
489 /* configure a full-word SYNC pulse (LRCLK) */
490 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
491 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
492
493 /* make 1st data bit occur one ACLK cycle after the frame sync */
494 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
495 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
496 break;
497 }
498
499 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
500 case SND_SOC_DAIFMT_CBS_CFS:
501 /* codec is clock and frame slave */
502 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
503 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
504
505 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
506 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
507
508 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
509 ACLKX | ACLKR);
510 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
511 AFSX | AFSR);
512 break;
513 case SND_SOC_DAIFMT_CBM_CFS:
514 /* codec is clock master and frame slave */
515 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
516 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
517
518 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
519 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
520
521 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
522 ACLKX | ACLKR);
523 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
524 AFSX | AFSR);
525 break;
526 case SND_SOC_DAIFMT_CBM_CFM:
527 /* codec is clock and frame master */
528 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
529 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
530
531 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
532 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
533
534 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
535 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
536 break;
537
538 default:
539 return -EINVAL;
540 }
541
542 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
543 case SND_SOC_DAIFMT_IB_NF:
544 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
545 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
546
547 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
548 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
549 break;
550
551 case SND_SOC_DAIFMT_NB_IF:
552 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
553 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
554
555 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
556 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
557 break;
558
559 case SND_SOC_DAIFMT_IB_IF:
560 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
561 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
562
563 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
564 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
565 break;
566
567 case SND_SOC_DAIFMT_NB_NF:
568 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
569 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
570
571 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
572 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
573 break;
574
575 default:
576 return -EINVAL;
577 }
578
579 return 0;
580 }
581
582 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
583 {
584 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
585
586 switch (div_id) {
587 case 0: /* MCLK divider */
588 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
589 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
590 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
591 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
592 break;
593
594 case 1: /* BCLK divider */
595 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
596 ACLKXDIV(div - 1), ACLKXDIV_MASK);
597 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
598 ACLKRDIV(div - 1), ACLKRDIV_MASK);
599 break;
600
601 case 2: /* BCLK/LRCLK ratio */
602 dev->bclk_lrclk_ratio = div;
603 break;
604
605 default:
606 return -EINVAL;
607 }
608
609 return 0;
610 }
611
612 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
613 unsigned int freq, int dir)
614 {
615 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
616
617 if (dir == SND_SOC_CLOCK_OUT) {
618 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
619 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
620 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
621 } else {
622 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
623 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
624 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
625 }
626
627 return 0;
628 }
629
630 static int davinci_config_channel_size(struct davinci_audio_dev *dev,
631 int word_length)
632 {
633 u32 fmt;
634 u32 tx_rotate = (word_length / 4) & 0x7;
635 u32 rx_rotate = (32 - word_length) / 4;
636 u32 mask = (1ULL << word_length) - 1;
637
638 /*
639 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
640 * callback, take it into account here. That allows us to for example
641 * send 32 bits per channel to the codec, while only 16 of them carry
642 * audio payload.
643 * The clock ratio is given for a full period of data (for I2S format
644 * both left and right channels), so it has to be divided by number of
645 * tdm-slots (for I2S - divided by 2).
646 */
647 if (dev->bclk_lrclk_ratio)
648 word_length = dev->bclk_lrclk_ratio / dev->tdm_slots;
649
650 /* mapping of the XSSZ bit-field as described in the datasheet */
651 fmt = (word_length >> 1) - 1;
652
653 if (dev->op_mode != DAVINCI_MCASP_DIT_MODE) {
654 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
655 RXSSZ(fmt), RXSSZ(0x0F));
656 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
657 TXSSZ(fmt), TXSSZ(0x0F));
658 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
659 TXROT(tx_rotate), TXROT(7));
660 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
661 RXROT(rx_rotate), RXROT(7));
662 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG,
663 mask);
664 }
665
666 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
667
668 return 0;
669 }
670
671 static int davinci_hw_common_param(struct davinci_audio_dev *dev, int stream,
672 int channels)
673 {
674 int i;
675 u8 tx_ser = 0;
676 u8 rx_ser = 0;
677 u8 ser;
678 u8 slots = dev->tdm_slots;
679 u8 max_active_serializers = (channels + slots - 1) / slots;
680 /* Default configuration */
681 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
682
683 /* All PINS as McASP */
684 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
685
686 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
687 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
688 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
689 TXDATADMADIS);
690 } else {
691 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
692 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
693 RXDATADMADIS);
694 }
695
696 for (i = 0; i < dev->num_serializer; i++) {
697 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
698 dev->serial_dir[i]);
699 if (dev->serial_dir[i] == TX_MODE &&
700 tx_ser < max_active_serializers) {
701 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
702 AXR(i));
703 tx_ser++;
704 } else if (dev->serial_dir[i] == RX_MODE &&
705 rx_ser < max_active_serializers) {
706 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
707 AXR(i));
708 rx_ser++;
709 } else {
710 mcasp_mod_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
711 SRMOD_INACTIVE, SRMOD_MASK);
712 }
713 }
714
715 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
716 ser = tx_ser;
717 else
718 ser = rx_ser;
719
720 if (ser < max_active_serializers) {
721 dev_warn(dev->dev, "stream has more channels (%d) than are "
722 "enabled in mcasp (%d)\n", channels, ser * slots);
723 return -EINVAL;
724 }
725
726 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
727 if (dev->txnumevt * tx_ser > 64)
728 dev->txnumevt = 1;
729
730 switch (dev->version) {
731 case MCASP_VERSION_3:
732 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
733 NUMDMA_MASK);
734 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
735 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
736 break;
737 default:
738 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
739 tx_ser, NUMDMA_MASK);
740 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
741 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
742 }
743 }
744
745 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
746 if (dev->rxnumevt * rx_ser > 64)
747 dev->rxnumevt = 1;
748 switch (dev->version) {
749 case MCASP_VERSION_3:
750 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
751 NUMDMA_MASK);
752 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
753 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
754 break;
755 default:
756 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
757 rx_ser, NUMDMA_MASK);
758 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
759 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
760 }
761 }
762
763 return 0;
764 }
765
766 static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
767 {
768 int i, active_slots;
769 u32 mask = 0;
770
771 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
772 for (i = 0; i < active_slots; i++)
773 mask |= (1 << i);
774
775 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
776
777 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
778 /* bit stream is MSB first with no delay */
779 /* DSP_B mode */
780 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
781 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
782
783 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
784 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
785 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
786 else
787 printk(KERN_ERR "playback tdm slot %d not supported\n",
788 dev->tdm_slots);
789 } else {
790 /* bit stream is MSB first with no delay */
791 /* DSP_B mode */
792 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
793 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
794
795 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
796 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
797 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
798 else
799 printk(KERN_ERR "capture tdm slot %d not supported\n",
800 dev->tdm_slots);
801 }
802 }
803
804 /* S/PDIF */
805 static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
806 {
807 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
808 and LSB first */
809 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
810 TXROT(6) | TXSSZ(15));
811
812 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
813 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
814 AFSXE | FSXMOD(0x180));
815
816 /* Set the TX tdm : for all the slots */
817 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
818
819 /* Set the TX clock controls : div = 1 and internal */
820 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
821 ACLKXE | TX_ASYNC);
822
823 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
824
825 /* Only 44100 and 48000 are valid, both have the same setting */
826 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
827
828 /* Enable the DIT */
829 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
830 }
831
832 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
833 struct snd_pcm_hw_params *params,
834 struct snd_soc_dai *cpu_dai)
835 {
836 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
837 struct davinci_pcm_dma_params *dma_params =
838 &dev->dma_params[substream->stream];
839 int word_length;
840 u8 fifo_level;
841 u8 slots = dev->tdm_slots;
842 u8 active_serializers;
843 int channels;
844 struct snd_interval *pcm_channels = hw_param_interval(params,
845 SNDRV_PCM_HW_PARAM_CHANNELS);
846 channels = pcm_channels->min;
847
848 active_serializers = (channels + slots - 1) / slots;
849
850 if (davinci_hw_common_param(dev, substream->stream, channels) == -EINVAL)
851 return -EINVAL;
852 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
853 fifo_level = dev->txnumevt * active_serializers;
854 else
855 fifo_level = dev->rxnumevt * active_serializers;
856
857 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
858 davinci_hw_dit_param(dev);
859 else
860 davinci_hw_param(dev, substream->stream);
861
862 switch (params_format(params)) {
863 case SNDRV_PCM_FORMAT_U8:
864 case SNDRV_PCM_FORMAT_S8:
865 dma_params->data_type = 1;
866 word_length = 8;
867 break;
868
869 case SNDRV_PCM_FORMAT_U16_LE:
870 case SNDRV_PCM_FORMAT_S16_LE:
871 dma_params->data_type = 2;
872 word_length = 16;
873 break;
874
875 case SNDRV_PCM_FORMAT_U24_3LE:
876 case SNDRV_PCM_FORMAT_S24_3LE:
877 dma_params->data_type = 3;
878 word_length = 24;
879 break;
880
881 case SNDRV_PCM_FORMAT_U24_LE:
882 case SNDRV_PCM_FORMAT_S24_LE:
883 case SNDRV_PCM_FORMAT_U32_LE:
884 case SNDRV_PCM_FORMAT_S32_LE:
885 dma_params->data_type = 4;
886 word_length = 32;
887 break;
888
889 default:
890 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
891 return -EINVAL;
892 }
893
894 if (dev->version == MCASP_VERSION_2 && !fifo_level)
895 dma_params->acnt = 4;
896 else
897 dma_params->acnt = dma_params->data_type;
898
899 dma_params->fifo_level = fifo_level;
900 davinci_config_channel_size(dev, word_length);
901
902 return 0;
903 }
904
905 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
906 int cmd, struct snd_soc_dai *cpu_dai)
907 {
908 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
909 int ret = 0;
910
911 switch (cmd) {
912 case SNDRV_PCM_TRIGGER_RESUME:
913 case SNDRV_PCM_TRIGGER_START:
914 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
915 ret = pm_runtime_get_sync(dev->dev);
916 if (IS_ERR_VALUE(ret))
917 dev_err(dev->dev, "pm_runtime_get_sync() failed\n");
918 davinci_mcasp_start(dev, substream->stream);
919 break;
920
921 case SNDRV_PCM_TRIGGER_SUSPEND:
922 davinci_mcasp_stop(dev, substream->stream);
923 ret = pm_runtime_put_sync(dev->dev);
924 if (IS_ERR_VALUE(ret))
925 dev_err(dev->dev, "pm_runtime_put_sync() failed\n");
926 break;
927
928 case SNDRV_PCM_TRIGGER_STOP:
929 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
930 davinci_mcasp_stop(dev, substream->stream);
931 break;
932
933 default:
934 ret = -EINVAL;
935 }
936
937 return ret;
938 }
939
940 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
941 struct snd_soc_dai *dai)
942 {
943 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
944
945 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
946 return 0;
947 }
948
949 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
950 .startup = davinci_mcasp_startup,
951 .trigger = davinci_mcasp_trigger,
952 .hw_params = davinci_mcasp_hw_params,
953 .set_fmt = davinci_mcasp_set_dai_fmt,
954 .set_clkdiv = davinci_mcasp_set_clkdiv,
955 .set_sysclk = davinci_mcasp_set_sysclk,
956 };
957
958 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
959 SNDRV_PCM_FMTBIT_U8 | \
960 SNDRV_PCM_FMTBIT_S16_LE | \
961 SNDRV_PCM_FMTBIT_U16_LE | \
962 SNDRV_PCM_FMTBIT_S24_LE | \
963 SNDRV_PCM_FMTBIT_U24_LE | \
964 SNDRV_PCM_FMTBIT_S24_3LE | \
965 SNDRV_PCM_FMTBIT_U24_3LE | \
966 SNDRV_PCM_FMTBIT_S32_LE | \
967 SNDRV_PCM_FMTBIT_U32_LE)
968
969 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
970 {
971 .name = "davinci-mcasp.0",
972 .playback = {
973 .channels_min = 2,
974 .channels_max = 32 * 16,
975 .rates = DAVINCI_MCASP_RATES,
976 .formats = DAVINCI_MCASP_PCM_FMTS,
977 },
978 .capture = {
979 .channels_min = 2,
980 .channels_max = 32 * 16,
981 .rates = DAVINCI_MCASP_RATES,
982 .formats = DAVINCI_MCASP_PCM_FMTS,
983 },
984 .ops = &davinci_mcasp_dai_ops,
985
986 },
987 {
988 "davinci-mcasp.1",
989 .playback = {
990 .channels_min = 1,
991 .channels_max = 384,
992 .rates = DAVINCI_MCASP_RATES,
993 .formats = DAVINCI_MCASP_PCM_FMTS,
994 },
995 .ops = &davinci_mcasp_dai_ops,
996 },
997
998 };
999
1000 static const struct snd_soc_component_driver davinci_mcasp_component = {
1001 .name = "davinci-mcasp",
1002 };
1003
1004 static const struct of_device_id mcasp_dt_ids[] = {
1005 {
1006 .compatible = "ti,dm646x-mcasp-audio",
1007 .data = (void *)MCASP_VERSION_1,
1008 },
1009 {
1010 .compatible = "ti,da830-mcasp-audio",
1011 .data = (void *)MCASP_VERSION_2,
1012 },
1013 {
1014 .compatible = "ti,omap2-mcasp-audio",
1015 .data = (void *)MCASP_VERSION_3,
1016 },
1017 { /* sentinel */ }
1018 };
1019 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1020
1021 static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
1022 struct platform_device *pdev)
1023 {
1024 struct device_node *np = pdev->dev.of_node;
1025 struct snd_platform_data *pdata = NULL;
1026 const struct of_device_id *match =
1027 of_match_device(of_match_ptr(mcasp_dt_ids), &pdev->dev);
1028
1029 const u32 *of_serial_dir32;
1030 u8 *of_serial_dir;
1031 u32 val;
1032 int i, ret = 0;
1033
1034 if (pdev->dev.platform_data) {
1035 pdata = pdev->dev.platform_data;
1036 return pdata;
1037 } else if (match) {
1038 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1039 if (!pdata) {
1040 ret = -ENOMEM;
1041 goto nodata;
1042 }
1043 } else {
1044 /* control shouldn't reach here. something is wrong */
1045 ret = -EINVAL;
1046 goto nodata;
1047 }
1048
1049 if (match->data)
1050 pdata->version = (u8)((int)match->data);
1051
1052 ret = of_property_read_u32(np, "op-mode", &val);
1053 if (ret >= 0)
1054 pdata->op_mode = val;
1055
1056 ret = of_property_read_u32(np, "tdm-slots", &val);
1057 if (ret >= 0) {
1058 if (val < 2 || val > 32) {
1059 dev_err(&pdev->dev,
1060 "tdm-slots must be in rage [2-32]\n");
1061 ret = -EINVAL;
1062 goto nodata;
1063 }
1064
1065 pdata->tdm_slots = val;
1066 }
1067
1068 ret = of_property_read_u32(np, "num-serializer", &val);
1069 if (ret >= 0)
1070 pdata->num_serializer = val;
1071
1072 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1073 val /= sizeof(u32);
1074 if (val != pdata->num_serializer) {
1075 dev_err(&pdev->dev,
1076 "num-serializer(%d) != serial-dir size(%d)\n",
1077 pdata->num_serializer, val);
1078 ret = -EINVAL;
1079 goto nodata;
1080 }
1081
1082 if (of_serial_dir32) {
1083 of_serial_dir = devm_kzalloc(&pdev->dev,
1084 (sizeof(*of_serial_dir) * val),
1085 GFP_KERNEL);
1086 if (!of_serial_dir) {
1087 ret = -ENOMEM;
1088 goto nodata;
1089 }
1090
1091 for (i = 0; i < pdata->num_serializer; i++)
1092 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1093
1094 pdata->serial_dir = of_serial_dir;
1095 }
1096
1097 ret = of_property_read_u32(np, "tx-num-evt", &val);
1098 if (ret >= 0)
1099 pdata->txnumevt = val;
1100
1101 ret = of_property_read_u32(np, "rx-num-evt", &val);
1102 if (ret >= 0)
1103 pdata->rxnumevt = val;
1104
1105 ret = of_property_read_u32(np, "sram-size-playback", &val);
1106 if (ret >= 0)
1107 pdata->sram_size_playback = val;
1108
1109 ret = of_property_read_u32(np, "sram-size-capture", &val);
1110 if (ret >= 0)
1111 pdata->sram_size_capture = val;
1112
1113 return pdata;
1114
1115 nodata:
1116 if (ret < 0) {
1117 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1118 ret);
1119 pdata = NULL;
1120 }
1121 return pdata;
1122 }
1123
1124 static int davinci_mcasp_probe(struct platform_device *pdev)
1125 {
1126 struct davinci_pcm_dma_params *dma_data;
1127 struct resource *mem, *ioarea, *res;
1128 struct snd_platform_data *pdata;
1129 struct davinci_audio_dev *dev;
1130 int ret;
1131
1132 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1133 dev_err(&pdev->dev, "No platform data supplied\n");
1134 return -EINVAL;
1135 }
1136
1137 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
1138 GFP_KERNEL);
1139 if (!dev)
1140 return -ENOMEM;
1141
1142 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1143 if (!pdata) {
1144 dev_err(&pdev->dev, "no platform data\n");
1145 return -EINVAL;
1146 }
1147
1148 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1149 if (!mem) {
1150 dev_err(&pdev->dev, "no mem resource?\n");
1151 return -ENODEV;
1152 }
1153
1154 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1155 resource_size(mem), pdev->name);
1156 if (!ioarea) {
1157 dev_err(&pdev->dev, "Audio region already claimed\n");
1158 return -EBUSY;
1159 }
1160
1161 pm_runtime_enable(&pdev->dev);
1162
1163 ret = pm_runtime_get_sync(&pdev->dev);
1164 if (IS_ERR_VALUE(ret)) {
1165 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1166 return ret;
1167 }
1168
1169 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1170 if (!dev->base) {
1171 dev_err(&pdev->dev, "ioremap failed\n");
1172 ret = -ENOMEM;
1173 goto err_release_clk;
1174 }
1175
1176 dev->op_mode = pdata->op_mode;
1177 dev->tdm_slots = pdata->tdm_slots;
1178 dev->num_serializer = pdata->num_serializer;
1179 dev->serial_dir = pdata->serial_dir;
1180 dev->version = pdata->version;
1181 dev->txnumevt = pdata->txnumevt;
1182 dev->rxnumevt = pdata->rxnumevt;
1183 dev->dev = &pdev->dev;
1184
1185 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1186 dma_data->asp_chan_q = pdata->asp_chan_q;
1187 dma_data->ram_chan_q = pdata->ram_chan_q;
1188 dma_data->sram_pool = pdata->sram_pool;
1189 dma_data->sram_size = pdata->sram_size_playback;
1190 dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
1191 mem->start);
1192
1193 /* first TX, then RX */
1194 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1195 if (!res) {
1196 dev_err(&pdev->dev, "no DMA resource\n");
1197 ret = -ENODEV;
1198 goto err_release_clk;
1199 }
1200
1201 dma_data->channel = res->start;
1202
1203 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1204 dma_data->asp_chan_q = pdata->asp_chan_q;
1205 dma_data->ram_chan_q = pdata->ram_chan_q;
1206 dma_data->sram_pool = pdata->sram_pool;
1207 dma_data->sram_size = pdata->sram_size_capture;
1208 dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
1209 mem->start);
1210
1211 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1212 if (!res) {
1213 dev_err(&pdev->dev, "no DMA resource\n");
1214 ret = -ENODEV;
1215 goto err_release_clk;
1216 }
1217
1218 dma_data->channel = res->start;
1219 dev_set_drvdata(&pdev->dev, dev);
1220 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
1221 &davinci_mcasp_dai[pdata->op_mode], 1);
1222
1223 if (ret != 0)
1224 goto err_release_clk;
1225
1226 ret = davinci_soc_platform_register(&pdev->dev);
1227 if (ret) {
1228 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1229 goto err_unregister_component;
1230 }
1231
1232 return 0;
1233
1234 err_unregister_component:
1235 snd_soc_unregister_component(&pdev->dev);
1236 err_release_clk:
1237 pm_runtime_put_sync(&pdev->dev);
1238 pm_runtime_disable(&pdev->dev);
1239 return ret;
1240 }
1241
1242 static int davinci_mcasp_remove(struct platform_device *pdev)
1243 {
1244
1245 snd_soc_unregister_component(&pdev->dev);
1246 davinci_soc_platform_unregister(&pdev->dev);
1247
1248 pm_runtime_put_sync(&pdev->dev);
1249 pm_runtime_disable(&pdev->dev);
1250
1251 return 0;
1252 }
1253
1254 static struct platform_driver davinci_mcasp_driver = {
1255 .probe = davinci_mcasp_probe,
1256 .remove = davinci_mcasp_remove,
1257 .driver = {
1258 .name = "davinci-mcasp",
1259 .owner = THIS_MODULE,
1260 .of_match_table = of_match_ptr(mcasp_dt_ids),
1261 },
1262 };
1263
1264 module_platform_driver(davinci_mcasp_driver);
1265
1266 MODULE_AUTHOR("Steve Chen");
1267 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1268 MODULE_LICENSE("GPL");
1269
kernel source for telekom puls (alcatel/mediatek)