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Merge branch 'nohz/printk-v8' into irq/core
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / wm8961.c
1 /*
2 * wm8961.c -- WM8961 ALSA SoC Audio driver
3 *
4 * Copyright 2009-10 Wolfson Microelectronics, plc
5 *
6 * Author: Mark Brown
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Currently unimplemented features:
13 * - ALC
14 */
15
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/pm.h>
21 #include <linux/i2c.h>
22 #include <linux/regmap.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30
31 #include "wm8961.h"
32
33 #define WM8961_MAX_REGISTER 0xFC
34
35 static const struct reg_default wm8961_reg_defaults[] = {
36 { 0, 0x009F }, /* R0 - Left Input volume */
37 { 1, 0x009F }, /* R1 - Right Input volume */
38 { 2, 0x0000 }, /* R2 - LOUT1 volume */
39 { 3, 0x0000 }, /* R3 - ROUT1 volume */
40 { 4, 0x0020 }, /* R4 - Clocking1 */
41 { 5, 0x0008 }, /* R5 - ADC & DAC Control 1 */
42 { 6, 0x0000 }, /* R6 - ADC & DAC Control 2 */
43 { 7, 0x000A }, /* R7 - Audio Interface 0 */
44 { 8, 0x01F4 }, /* R8 - Clocking2 */
45 { 9, 0x0000 }, /* R9 - Audio Interface 1 */
46 { 10, 0x00FF }, /* R10 - Left DAC volume */
47 { 11, 0x00FF }, /* R11 - Right DAC volume */
48
49 { 14, 0x0040 }, /* R14 - Audio Interface 2 */
50
51 { 17, 0x007B }, /* R17 - ALC1 */
52 { 18, 0x0000 }, /* R18 - ALC2 */
53 { 19, 0x0032 }, /* R19 - ALC3 */
54 { 20, 0x0000 }, /* R20 - Noise Gate */
55 { 21, 0x00C0 }, /* R21 - Left ADC volume */
56 { 22, 0x00C0 }, /* R22 - Right ADC volume */
57 { 23, 0x0120 }, /* R23 - Additional control(1) */
58 { 24, 0x0000 }, /* R24 - Additional control(2) */
59 { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */
60 { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */
61 { 27, 0x0000 }, /* R27 - Additional Control (3) */
62 { 28, 0x0000 }, /* R28 - Anti-pop */
63
64 { 30, 0x005F }, /* R30 - Clocking 3 */
65
66 { 32, 0x0000 }, /* R32 - ADCL signal path */
67 { 33, 0x0000 }, /* R33 - ADCR signal path */
68
69 { 40, 0x0000 }, /* R40 - LOUT2 volume */
70 { 41, 0x0000 }, /* R41 - ROUT2 volume */
71
72 { 47, 0x0000 }, /* R47 - Pwr Mgmt (3) */
73 { 48, 0x0023 }, /* R48 - Additional Control (4) */
74 { 49, 0x0000 }, /* R49 - Class D Control 1 */
75
76 { 51, 0x0003 }, /* R51 - Class D Control 2 */
77
78 { 56, 0x0106 }, /* R56 - Clocking 4 */
79 { 57, 0x0000 }, /* R57 - DSP Sidetone 0 */
80 { 58, 0x0000 }, /* R58 - DSP Sidetone 1 */
81
82 { 60, 0x0000 }, /* R60 - DC Servo 0 */
83 { 61, 0x0000 }, /* R61 - DC Servo 1 */
84
85 { 63, 0x015E }, /* R63 - DC Servo 3 */
86
87 { 65, 0x0010 }, /* R65 - DC Servo 5 */
88
89 { 68, 0x0003 }, /* R68 - Analogue PGA Bias */
90 { 69, 0x0000 }, /* R69 - Analogue HP 0 */
91
92 { 71, 0x01FB }, /* R71 - Analogue HP 2 */
93 { 72, 0x0000 }, /* R72 - Charge Pump 1 */
94
95 { 82, 0x0000 }, /* R82 - Charge Pump B */
96
97 { 87, 0x0000 }, /* R87 - Write Sequencer 1 */
98 { 88, 0x0000 }, /* R88 - Write Sequencer 2 */
99 { 89, 0x0000 }, /* R89 - Write Sequencer 3 */
100 { 90, 0x0000 }, /* R90 - Write Sequencer 4 */
101 { 91, 0x0000 }, /* R91 - Write Sequencer 5 */
102 { 92, 0x0000 }, /* R92 - Write Sequencer 6 */
103 { 93, 0x0000 }, /* R93 - Write Sequencer 7 */
104
105 { 252, 0x0001 }, /* R252 - General test 1 */
106 };
107
108 struct wm8961_priv {
109 struct regmap *regmap;
110 int sysclk;
111 };
112
113 static bool wm8961_volatile(struct device *dev, unsigned int reg)
114 {
115 switch (reg) {
116 case WM8961_SOFTWARE_RESET:
117 case WM8961_WRITE_SEQUENCER_7:
118 case WM8961_DC_SERVO_1:
119 return true;
120
121 default:
122 return false;
123 }
124 }
125
126 static bool wm8961_readable(struct device *dev, unsigned int reg)
127 {
128 switch (reg) {
129 case WM8961_LEFT_INPUT_VOLUME:
130 case WM8961_RIGHT_INPUT_VOLUME:
131 case WM8961_LOUT1_VOLUME:
132 case WM8961_ROUT1_VOLUME:
133 case WM8961_CLOCKING1:
134 case WM8961_ADC_DAC_CONTROL_1:
135 case WM8961_ADC_DAC_CONTROL_2:
136 case WM8961_AUDIO_INTERFACE_0:
137 case WM8961_CLOCKING2:
138 case WM8961_AUDIO_INTERFACE_1:
139 case WM8961_LEFT_DAC_VOLUME:
140 case WM8961_RIGHT_DAC_VOLUME:
141 case WM8961_AUDIO_INTERFACE_2:
142 case WM8961_SOFTWARE_RESET:
143 case WM8961_ALC1:
144 case WM8961_ALC2:
145 case WM8961_ALC3:
146 case WM8961_NOISE_GATE:
147 case WM8961_LEFT_ADC_VOLUME:
148 case WM8961_RIGHT_ADC_VOLUME:
149 case WM8961_ADDITIONAL_CONTROL_1:
150 case WM8961_ADDITIONAL_CONTROL_2:
151 case WM8961_PWR_MGMT_1:
152 case WM8961_PWR_MGMT_2:
153 case WM8961_ADDITIONAL_CONTROL_3:
154 case WM8961_ANTI_POP:
155 case WM8961_CLOCKING_3:
156 case WM8961_ADCL_SIGNAL_PATH:
157 case WM8961_ADCR_SIGNAL_PATH:
158 case WM8961_LOUT2_VOLUME:
159 case WM8961_ROUT2_VOLUME:
160 case WM8961_PWR_MGMT_3:
161 case WM8961_ADDITIONAL_CONTROL_4:
162 case WM8961_CLASS_D_CONTROL_1:
163 case WM8961_CLASS_D_CONTROL_2:
164 case WM8961_CLOCKING_4:
165 case WM8961_DSP_SIDETONE_0:
166 case WM8961_DSP_SIDETONE_1:
167 case WM8961_DC_SERVO_0:
168 case WM8961_DC_SERVO_1:
169 case WM8961_DC_SERVO_3:
170 case WM8961_DC_SERVO_5:
171 case WM8961_ANALOGUE_PGA_BIAS:
172 case WM8961_ANALOGUE_HP_0:
173 case WM8961_ANALOGUE_HP_2:
174 case WM8961_CHARGE_PUMP_1:
175 case WM8961_CHARGE_PUMP_B:
176 case WM8961_WRITE_SEQUENCER_1:
177 case WM8961_WRITE_SEQUENCER_2:
178 case WM8961_WRITE_SEQUENCER_3:
179 case WM8961_WRITE_SEQUENCER_4:
180 case WM8961_WRITE_SEQUENCER_5:
181 case WM8961_WRITE_SEQUENCER_6:
182 case WM8961_WRITE_SEQUENCER_7:
183 case WM8961_GENERAL_TEST_1:
184 return true;
185 default:
186 return false;
187 }
188 }
189
190 /*
191 * The headphone output supports special anti-pop sequences giving
192 * silent power up and power down.
193 */
194 static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
195 struct snd_kcontrol *kcontrol, int event)
196 {
197 struct snd_soc_codec *codec = w->codec;
198 u16 hp_reg = snd_soc_read(codec, WM8961_ANALOGUE_HP_0);
199 u16 cp_reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_1);
200 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
201 u16 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
202 int timeout = 500;
203
204 if (event & SND_SOC_DAPM_POST_PMU) {
205 /* Make sure the output is shorted */
206 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
207 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
208
209 /* Enable the charge pump */
210 cp_reg |= WM8961_CP_ENA;
211 snd_soc_write(codec, WM8961_CHARGE_PUMP_1, cp_reg);
212 mdelay(5);
213
214 /* Enable the PGA */
215 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;
216 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
217
218 /* Enable the amplifier */
219 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;
220 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
221
222 /* Second stage enable */
223 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;
224 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
225
226 /* Enable the DC servo & trigger startup */
227 dcs_reg |=
228 WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR |
229 WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;
230 dev_dbg(codec->dev, "Enabling DC servo\n");
231
232 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
233 do {
234 msleep(1);
235 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
236 } while (--timeout &&
237 dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
238 WM8961_DCS_TRIG_STARTUP_HPL));
239 if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
240 WM8961_DCS_TRIG_STARTUP_HPL))
241 dev_err(codec->dev, "DC servo timed out\n");
242 else
243 dev_dbg(codec->dev, "DC servo startup complete\n");
244
245 /* Enable the output stage */
246 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;
247 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
248
249 /* Remove the short on the output stage */
250 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;
251 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
252 }
253
254 if (event & SND_SOC_DAPM_PRE_PMD) {
255 /* Short the output */
256 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
257 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
258
259 /* Disable the output stage */
260 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);
261 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
262
263 /* Disable DC offset cancellation */
264 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |
265 WM8961_DCS_ENA_CHAN_HPL);
266 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
267
268 /* Finish up */
269 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |
270 WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);
271 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
272
273 /* Disable the PGA */
274 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);
275 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
276
277 /* Disable the charge pump */
278 dev_dbg(codec->dev, "Disabling charge pump\n");
279 snd_soc_write(codec, WM8961_CHARGE_PUMP_1,
280 cp_reg & ~WM8961_CP_ENA);
281 }
282
283 return 0;
284 }
285
286 static int wm8961_spk_event(struct snd_soc_dapm_widget *w,
287 struct snd_kcontrol *kcontrol, int event)
288 {
289 struct snd_soc_codec *codec = w->codec;
290 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
291 u16 spk_reg = snd_soc_read(codec, WM8961_CLASS_D_CONTROL_1);
292
293 if (event & SND_SOC_DAPM_POST_PMU) {
294 /* Enable the PGA */
295 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;
296 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
297
298 /* Enable the amplifier */
299 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;
300 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
301 }
302
303 if (event & SND_SOC_DAPM_PRE_PMD) {
304 /* Disable the amplifier */
305 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);
306 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
307
308 /* Disable the PGA */
309 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);
310 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
311 }
312
313 return 0;
314 }
315
316 static const char *adc_hpf_text[] = {
317 "Hi-fi", "Voice 1", "Voice 2", "Voice 3",
318 };
319
320 static const struct soc_enum adc_hpf =
321 SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_2, 7, 4, adc_hpf_text);
322
323 static const char *dac_deemph_text[] = {
324 "None", "32kHz", "44.1kHz", "48kHz",
325 };
326
327 static const struct soc_enum dac_deemph =
328 SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_1, 1, 4, dac_deemph_text);
329
330 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
331 static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0);
332 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
333 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
334 static unsigned int boost_tlv[] = {
335 TLV_DB_RANGE_HEAD(4),
336 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
337 1, 1, TLV_DB_SCALE_ITEM(13, 0, 0),
338 2, 2, TLV_DB_SCALE_ITEM(20, 0, 0),
339 3, 3, TLV_DB_SCALE_ITEM(29, 0, 0),
340 };
341 static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0);
342
343 static const struct snd_kcontrol_new wm8961_snd_controls[] = {
344 SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
345 0, 127, 0, out_tlv),
346 SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2,
347 6, 3, 7, 0, hp_sec_tlv),
348 SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
349 7, 1, 0),
350
351 SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
352 0, 127, 0, out_tlv),
353 SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
354 7, 1, 0),
355 SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0),
356
357 SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0),
358 SOC_ENUM("DAC Deemphasis", dac_deemph),
359 SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0),
360
361 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0,
362 WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv),
363
364 SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0),
365 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
366
367 SOC_DOUBLE_R_TLV("Capture Volume",
368 WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME,
369 1, 119, 0, adc_tlv),
370 SOC_DOUBLE_R_TLV("Capture Boost Volume",
371 WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH,
372 4, 3, 0, boost_tlv),
373 SOC_DOUBLE_R_TLV("Capture PGA Volume",
374 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
375 0, 62, 0, pga_tlv),
376 SOC_DOUBLE_R("Capture PGA ZC Switch",
377 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
378 6, 1, 1),
379 SOC_DOUBLE_R("Capture PGA Switch",
380 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
381 7, 1, 1),
382 };
383
384 static const char *sidetone_text[] = {
385 "None", "Left", "Right"
386 };
387
388 static const struct soc_enum dacl_sidetone =
389 SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_0, 2, 3, sidetone_text);
390
391 static const struct soc_enum dacr_sidetone =
392 SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_1, 2, 3, sidetone_text);
393
394 static const struct snd_kcontrol_new dacl_mux =
395 SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone);
396
397 static const struct snd_kcontrol_new dacr_mux =
398 SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone);
399
400 static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = {
401 SND_SOC_DAPM_INPUT("LINPUT"),
402 SND_SOC_DAPM_INPUT("RINPUT"),
403
404 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0),
405
406 SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0),
407 SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0),
408
409 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0),
410 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0),
411
412 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8961_PWR_MGMT_1, 1, 0, NULL, 0),
413
414 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux),
415 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux),
416
417 SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0),
418 SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0),
419
420 /* Handle as a mono path for DCS */
421 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM,
422 4, 0, NULL, 0, wm8961_hp_event,
423 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
424 SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM,
425 4, 0, NULL, 0, wm8961_spk_event,
426 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
427
428 SND_SOC_DAPM_OUTPUT("HP_L"),
429 SND_SOC_DAPM_OUTPUT("HP_R"),
430 SND_SOC_DAPM_OUTPUT("SPK_LN"),
431 SND_SOC_DAPM_OUTPUT("SPK_LP"),
432 SND_SOC_DAPM_OUTPUT("SPK_RN"),
433 SND_SOC_DAPM_OUTPUT("SPK_RP"),
434 };
435
436
437 static const struct snd_soc_dapm_route audio_paths[] = {
438 { "DACL", NULL, "CLK_DSP" },
439 { "DACL", NULL, "DACL Sidetone" },
440 { "DACR", NULL, "CLK_DSP" },
441 { "DACR", NULL, "DACR Sidetone" },
442
443 { "DACL Sidetone", "Left", "ADCL" },
444 { "DACL Sidetone", "Right", "ADCR" },
445
446 { "DACR Sidetone", "Left", "ADCL" },
447 { "DACR Sidetone", "Right", "ADCR" },
448
449 { "HP_L", NULL, "Headphone Output" },
450 { "HP_R", NULL, "Headphone Output" },
451 { "Headphone Output", NULL, "DACL" },
452 { "Headphone Output", NULL, "DACR" },
453
454 { "SPK_LN", NULL, "Speaker Output" },
455 { "SPK_LP", NULL, "Speaker Output" },
456 { "SPK_RN", NULL, "Speaker Output" },
457 { "SPK_RP", NULL, "Speaker Output" },
458
459 { "Speaker Output", NULL, "DACL" },
460 { "Speaker Output", NULL, "DACR" },
461
462 { "ADCL", NULL, "Left Input" },
463 { "ADCL", NULL, "CLK_DSP" },
464 { "ADCR", NULL, "Right Input" },
465 { "ADCR", NULL, "CLK_DSP" },
466
467 { "Left Input", NULL, "LINPUT" },
468 { "Right Input", NULL, "RINPUT" },
469
470 };
471
472 /* Values for CLK_SYS_RATE */
473 static struct {
474 int ratio;
475 u16 val;
476 } wm8961_clk_sys_ratio[] = {
477 { 64, 0 },
478 { 128, 1 },
479 { 192, 2 },
480 { 256, 3 },
481 { 384, 4 },
482 { 512, 5 },
483 { 768, 6 },
484 { 1024, 7 },
485 { 1408, 8 },
486 { 1536, 9 },
487 };
488
489 /* Values for SAMPLE_RATE */
490 static struct {
491 int rate;
492 u16 val;
493 } wm8961_srate[] = {
494 { 48000, 0 },
495 { 44100, 0 },
496 { 32000, 1 },
497 { 22050, 2 },
498 { 24000, 2 },
499 { 16000, 3 },
500 { 11250, 4 },
501 { 12000, 4 },
502 { 8000, 5 },
503 };
504
505 static int wm8961_hw_params(struct snd_pcm_substream *substream,
506 struct snd_pcm_hw_params *params,
507 struct snd_soc_dai *dai)
508 {
509 struct snd_soc_codec *codec = dai->codec;
510 struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
511 int i, best, target, fs;
512 u16 reg;
513
514 fs = params_rate(params);
515
516 if (!wm8961->sysclk) {
517 dev_err(codec->dev, "MCLK has not been specified\n");
518 return -EINVAL;
519 }
520
521 /* Find the closest sample rate for the filters */
522 best = 0;
523 for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) {
524 if (abs(wm8961_srate[i].rate - fs) <
525 abs(wm8961_srate[best].rate - fs))
526 best = i;
527 }
528 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_3);
529 reg &= ~WM8961_SAMPLE_RATE_MASK;
530 reg |= wm8961_srate[best].val;
531 snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg);
532 dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n",
533 wm8961_srate[best].rate, fs);
534
535 /* Select a CLK_SYS/fs ratio equal to or higher than required */
536 target = wm8961->sysclk / fs;
537
538 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) {
539 dev_err(codec->dev,
540 "SYSCLK must be at least 64*fs for DAC\n");
541 return -EINVAL;
542 }
543 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) {
544 dev_err(codec->dev,
545 "SYSCLK must be at least 256*fs for ADC\n");
546 return -EINVAL;
547 }
548
549 for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) {
550 if (wm8961_clk_sys_ratio[i].ratio >= target)
551 break;
552 }
553 if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) {
554 dev_err(codec->dev, "Unable to generate CLK_SYS_RATE\n");
555 return -EINVAL;
556 }
557 dev_dbg(codec->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n",
558 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
559 wm8961->sysclk / fs);
560
561 reg = snd_soc_read(codec, WM8961_CLOCKING_4);
562 reg &= ~WM8961_CLK_SYS_RATE_MASK;
563 reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
564 snd_soc_write(codec, WM8961_CLOCKING_4, reg);
565
566 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
567 reg &= ~WM8961_WL_MASK;
568 switch (params_format(params)) {
569 case SNDRV_PCM_FORMAT_S16_LE:
570 break;
571 case SNDRV_PCM_FORMAT_S20_3LE:
572 reg |= 1 << WM8961_WL_SHIFT;
573 break;
574 case SNDRV_PCM_FORMAT_S24_LE:
575 reg |= 2 << WM8961_WL_SHIFT;
576 break;
577 case SNDRV_PCM_FORMAT_S32_LE:
578 reg |= 3 << WM8961_WL_SHIFT;
579 break;
580 default:
581 return -EINVAL;
582 }
583 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, reg);
584
585 /* Sloping stop-band filter is recommended for <= 24kHz */
586 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
587 if (fs <= 24000)
588 reg |= WM8961_DACSLOPE;
589 else
590 reg &= ~WM8961_DACSLOPE;
591 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
592
593 return 0;
594 }
595
596 static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
597 unsigned int freq,
598 int dir)
599 {
600 struct snd_soc_codec *codec = dai->codec;
601 struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
602 u16 reg = snd_soc_read(codec, WM8961_CLOCKING1);
603
604 if (freq > 33000000) {
605 dev_err(codec->dev, "MCLK must be <33MHz\n");
606 return -EINVAL;
607 }
608
609 if (freq > 16500000) {
610 dev_dbg(codec->dev, "Using MCLK/2 for %dHz MCLK\n", freq);
611 reg |= WM8961_MCLKDIV;
612 freq /= 2;
613 } else {
614 dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq);
615 reg &= ~WM8961_MCLKDIV;
616 }
617
618 snd_soc_write(codec, WM8961_CLOCKING1, reg);
619
620 wm8961->sysclk = freq;
621
622 return 0;
623 }
624
625 static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
626 {
627 struct snd_soc_codec *codec = dai->codec;
628 u16 aif = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
629
630 aif &= ~(WM8961_BCLKINV | WM8961_LRP |
631 WM8961_MS | WM8961_FORMAT_MASK);
632
633 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
634 case SND_SOC_DAIFMT_CBM_CFM:
635 aif |= WM8961_MS;
636 break;
637 case SND_SOC_DAIFMT_CBS_CFS:
638 break;
639 default:
640 return -EINVAL;
641 }
642
643 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
644 case SND_SOC_DAIFMT_RIGHT_J:
645 break;
646
647 case SND_SOC_DAIFMT_LEFT_J:
648 aif |= 1;
649 break;
650
651 case SND_SOC_DAIFMT_I2S:
652 aif |= 2;
653 break;
654
655 case SND_SOC_DAIFMT_DSP_B:
656 aif |= WM8961_LRP;
657 case SND_SOC_DAIFMT_DSP_A:
658 aif |= 3;
659 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
660 case SND_SOC_DAIFMT_NB_NF:
661 case SND_SOC_DAIFMT_IB_NF:
662 break;
663 default:
664 return -EINVAL;
665 }
666 break;
667
668 default:
669 return -EINVAL;
670 }
671
672 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
673 case SND_SOC_DAIFMT_NB_NF:
674 break;
675 case SND_SOC_DAIFMT_NB_IF:
676 aif |= WM8961_LRP;
677 break;
678 case SND_SOC_DAIFMT_IB_NF:
679 aif |= WM8961_BCLKINV;
680 break;
681 case SND_SOC_DAIFMT_IB_IF:
682 aif |= WM8961_BCLKINV | WM8961_LRP;
683 break;
684 default:
685 return -EINVAL;
686 }
687
688 return snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, aif);
689 }
690
691 static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
692 {
693 struct snd_soc_codec *codec = dai->codec;
694 u16 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_2);
695
696 if (tristate)
697 reg |= WM8961_TRIS;
698 else
699 reg &= ~WM8961_TRIS;
700
701 return snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg);
702 }
703
704 static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute)
705 {
706 struct snd_soc_codec *codec = dai->codec;
707 u16 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_1);
708
709 if (mute)
710 reg |= WM8961_DACMU;
711 else
712 reg &= ~WM8961_DACMU;
713
714 msleep(17);
715
716 return snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_1, reg);
717 }
718
719 static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
720 {
721 struct snd_soc_codec *codec = dai->codec;
722 u16 reg;
723
724 switch (div_id) {
725 case WM8961_BCLK:
726 reg = snd_soc_read(codec, WM8961_CLOCKING2);
727 reg &= ~WM8961_BCLKDIV_MASK;
728 reg |= div;
729 snd_soc_write(codec, WM8961_CLOCKING2, reg);
730 break;
731
732 case WM8961_LRCLK:
733 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_2);
734 reg &= ~WM8961_LRCLK_RATE_MASK;
735 reg |= div;
736 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_2, reg);
737 break;
738
739 default:
740 return -EINVAL;
741 }
742
743 return 0;
744 }
745
746 static int wm8961_set_bias_level(struct snd_soc_codec *codec,
747 enum snd_soc_bias_level level)
748 {
749 u16 reg;
750
751 /* This is all slightly unusual since we have no bypass paths
752 * and the output amplifier structure means we can just slam
753 * the biases straight up rather than having to ramp them
754 * slowly.
755 */
756 switch (level) {
757 case SND_SOC_BIAS_ON:
758 break;
759
760 case SND_SOC_BIAS_PREPARE:
761 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
762 /* Enable bias generation */
763 reg = snd_soc_read(codec, WM8961_ANTI_POP);
764 reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
765 snd_soc_write(codec, WM8961_ANTI_POP, reg);
766
767 /* VMID=2*50k, VREF */
768 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
769 reg &= ~WM8961_VMIDSEL_MASK;
770 reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
771 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
772 }
773 break;
774
775 case SND_SOC_BIAS_STANDBY:
776 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) {
777 /* VREF off */
778 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
779 reg &= ~WM8961_VREF;
780 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
781
782 /* Bias generation off */
783 reg = snd_soc_read(codec, WM8961_ANTI_POP);
784 reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
785 snd_soc_write(codec, WM8961_ANTI_POP, reg);
786
787 /* VMID off */
788 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
789 reg &= ~WM8961_VMIDSEL_MASK;
790 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
791 }
792 break;
793
794 case SND_SOC_BIAS_OFF:
795 break;
796 }
797
798 codec->dapm.bias_level = level;
799
800 return 0;
801 }
802
803
804 #define WM8961_RATES SNDRV_PCM_RATE_8000_48000
805
806 #define WM8961_FORMATS \
807 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
808 SNDRV_PCM_FMTBIT_S24_LE)
809
810 static const struct snd_soc_dai_ops wm8961_dai_ops = {
811 .hw_params = wm8961_hw_params,
812 .set_sysclk = wm8961_set_sysclk,
813 .set_fmt = wm8961_set_fmt,
814 .digital_mute = wm8961_digital_mute,
815 .set_tristate = wm8961_set_tristate,
816 .set_clkdiv = wm8961_set_clkdiv,
817 };
818
819 static struct snd_soc_dai_driver wm8961_dai = {
820 .name = "wm8961-hifi",
821 .playback = {
822 .stream_name = "HiFi Playback",
823 .channels_min = 1,
824 .channels_max = 2,
825 .rates = WM8961_RATES,
826 .formats = WM8961_FORMATS,},
827 .capture = {
828 .stream_name = "HiFi Capture",
829 .channels_min = 1,
830 .channels_max = 2,
831 .rates = WM8961_RATES,
832 .formats = WM8961_FORMATS,},
833 .ops = &wm8961_dai_ops,
834 };
835
836 static int wm8961_probe(struct snd_soc_codec *codec)
837 {
838 struct snd_soc_dapm_context *dapm = &codec->dapm;
839 int ret = 0;
840 u16 reg;
841
842 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
843 if (ret != 0) {
844 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
845 return ret;
846 }
847
848 /* Enable class W */
849 reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_B);
850 reg |= WM8961_CP_DYN_PWR_MASK;
851 snd_soc_write(codec, WM8961_CHARGE_PUMP_B, reg);
852
853 /* Latch volume update bits (right channel only, we always
854 * write both out) and default ZC on. */
855 reg = snd_soc_read(codec, WM8961_ROUT1_VOLUME);
856 snd_soc_write(codec, WM8961_ROUT1_VOLUME,
857 reg | WM8961_LO1ZC | WM8961_OUT1VU);
858 snd_soc_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
859 reg = snd_soc_read(codec, WM8961_ROUT2_VOLUME);
860 snd_soc_write(codec, WM8961_ROUT2_VOLUME,
861 reg | WM8961_SPKRZC | WM8961_SPKVU);
862 snd_soc_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
863
864 reg = snd_soc_read(codec, WM8961_RIGHT_ADC_VOLUME);
865 snd_soc_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
866 reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
867 snd_soc_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
868
869 /* Use soft mute by default */
870 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
871 reg |= WM8961_DACSMM;
872 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
873
874 /* Use automatic clocking mode by default; for now this is all
875 * we support.
876 */
877 reg = snd_soc_read(codec, WM8961_CLOCKING_3);
878 reg &= ~WM8961_MANUAL_MODE;
879 snd_soc_write(codec, WM8961_CLOCKING_3, reg);
880
881 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
882
883 snd_soc_add_codec_controls(codec, wm8961_snd_controls,
884 ARRAY_SIZE(wm8961_snd_controls));
885 snd_soc_dapm_new_controls(dapm, wm8961_dapm_widgets,
886 ARRAY_SIZE(wm8961_dapm_widgets));
887 snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
888
889 return 0;
890 }
891
892 static int wm8961_remove(struct snd_soc_codec *codec)
893 {
894 wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
895 return 0;
896 }
897
898 #ifdef CONFIG_PM
899 static int wm8961_suspend(struct snd_soc_codec *codec)
900 {
901 wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
902
903 return 0;
904 }
905
906 static int wm8961_resume(struct snd_soc_codec *codec)
907 {
908 snd_soc_cache_sync(codec);
909
910 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
911
912 return 0;
913 }
914 #else
915 #define wm8961_suspend NULL
916 #define wm8961_resume NULL
917 #endif
918
919 static struct snd_soc_codec_driver soc_codec_dev_wm8961 = {
920 .probe = wm8961_probe,
921 .remove = wm8961_remove,
922 .suspend = wm8961_suspend,
923 .resume = wm8961_resume,
924 .set_bias_level = wm8961_set_bias_level,
925 };
926
927 static const struct regmap_config wm8961_regmap = {
928 .reg_bits = 8,
929 .val_bits = 16,
930 .max_register = WM8961_MAX_REGISTER,
931
932 .reg_defaults = wm8961_reg_defaults,
933 .num_reg_defaults = ARRAY_SIZE(wm8961_reg_defaults),
934 .cache_type = REGCACHE_RBTREE,
935
936 .volatile_reg = wm8961_volatile,
937 .readable_reg = wm8961_readable,
938 };
939
940 static int wm8961_i2c_probe(struct i2c_client *i2c,
941 const struct i2c_device_id *id)
942 {
943 struct wm8961_priv *wm8961;
944 unsigned int val;
945 int ret;
946
947 wm8961 = devm_kzalloc(&i2c->dev, sizeof(struct wm8961_priv),
948 GFP_KERNEL);
949 if (wm8961 == NULL)
950 return -ENOMEM;
951
952 wm8961->regmap = devm_regmap_init_i2c(i2c, &wm8961_regmap);
953 if (IS_ERR(wm8961->regmap))
954 return PTR_ERR(wm8961->regmap);
955
956 ret = regmap_read(wm8961->regmap, WM8961_SOFTWARE_RESET, &val);
957 if (ret != 0) {
958 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
959 return ret;
960 }
961
962 if (val != 0x1801) {
963 dev_err(&i2c->dev, "Device is not a WM8961: ID=0x%x\n", val);
964 return -EINVAL;
965 }
966
967 /* This isn't volatile - readback doesn't correspond to write */
968 regcache_cache_bypass(wm8961->regmap, true);
969 ret = regmap_read(wm8961->regmap, WM8961_RIGHT_INPUT_VOLUME, &val);
970 regcache_cache_bypass(wm8961->regmap, false);
971
972 if (ret != 0) {
973 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);
974 return ret;
975 }
976
977 dev_info(&i2c->dev, "WM8961 family %d revision %c\n",
978 (val & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
979 ((val & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
980 + 'A');
981
982 ret = regmap_write(wm8961->regmap, WM8961_SOFTWARE_RESET, 0x1801);
983 if (ret != 0) {
984 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
985 return ret;
986 }
987
988 i2c_set_clientdata(i2c, wm8961);
989
990 ret = snd_soc_register_codec(&i2c->dev,
991 &soc_codec_dev_wm8961, &wm8961_dai, 1);
992
993 return ret;
994 }
995
996 static int wm8961_i2c_remove(struct i2c_client *client)
997 {
998 snd_soc_unregister_codec(&client->dev);
999
1000 return 0;
1001 }
1002
1003 static const struct i2c_device_id wm8961_i2c_id[] = {
1004 { "wm8961", 0 },
1005 { }
1006 };
1007 MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id);
1008
1009 static struct i2c_driver wm8961_i2c_driver = {
1010 .driver = {
1011 .name = "wm8961",
1012 .owner = THIS_MODULE,
1013 },
1014 .probe = wm8961_i2c_probe,
1015 .remove = wm8961_i2c_remove,
1016 .id_table = wm8961_i2c_id,
1017 };
1018
1019 module_i2c_driver(wm8961_i2c_driver);
1020
1021 MODULE_DESCRIPTION("ASoC WM8961 driver");
1022 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1023 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)